MAX98090 Ultra-Low Power Stereo Audio Codec

EVALUATION KIT AVAILABLE
MAX98090
Ultra-Low Power Stereo Audio Codec
General Description
The MAX98090 is a fully integrated audio codec whose
high-performance, ultra-low power consumption and
small footprint make it ideal for portable applications.
The device features a highly flexible input scheme with
six input pins (WLP) that can be configured as analog or
digital microphone inputs, differential or single-ended line
inputs, or as full-scale direct differential inputs. Analog
inputs can be routed to the record path ADC or directly to
any analog output mixer.
The device accepts master clock frequencies of either
256 x fS or from 10MHz to 60MHz. The digital audio interface supports master or slave mode operation, sample
rates from 8kHz to 96kHz, and standard PCM formats
such as I2S, left/right-justified, and TDM.
The record/playback paths feature FlexSound® technology
DSP. This includes digital gain and filtering, a biquad filter
(record), dynamic range control (playback), and a seven
band parametric equalizer (playback) that can improve loudspeaker performance by optimizing the frequency response.
The stereo Class D speaker amplifier provides efficient
amplification, features low radiated emissions, supports
filterless operation, and can drive both 4Ω and 8Ω loads.
The DirectDrive® stereo Class H headphone amplifier provides a ground referenced output eliminating the
need for large DC-blocking capacitors. The device also
includes a differential receiver (earpiece) amplifier that
can be reconfigured as a stereo single-ended line output.
Simplified Block Diagram
DIGITAL
MICROPHONE
STEREO DIGITAL
MICOPHONE
OR
OR
1
2
ANALOG
LINE INPUT
MICROPHONE
OR
ANALOG
LINE INPUT
MICROPHONE
OR
ANALOG
LINE INPUT
MICROPHONE
OR
3
4
5
6
LINE INPUT A PGA
(DIFFERENTIAL OR
SINGLE-ENDED)
● 99dB DR Stereo ADC (8kHz < fS < 96kHz)
● 4.2mW Stereo Record Power Consumption
● 3 Stereo Single-Ended/Differential Analog
Microphone/Line Inputs (WLP Version)
● Stereo PDM Digital Microphone Input
● Master Clock Frequencies from 256 x fS to 60MHz
● I2S/LJ/RJ/TDM Digital Audio Interface
● FlexSound Technology Signal Processing
• Record Path Biquad Filter
• Playback Path 7-Band Parametric EQ
• Playback Path Automatic Level Control
• Digital Filtering and Gain/Level Control
● Stereo Low EMI Class D Speaker Amplifiers
• 3.2W/Channel (RL = 4Ω, VSPK_VDD = 5V, WLP)
• 1.8W/Channel (RL = 8Ω, VSPK_VDD = 5V, WLP)
● Stereo DirectDrive Class H Headphone Amplifier
Jack Detection and Identification
● Differential Receiver Amplifier/Stereo Line Output
● Extensive Click-and-Pop Reduction Circuitry
● RF Immune Analog Inputs and Outputs
● Programmable Microphone Bias
● I2C Control Interface with Two Address Options
● 49-Bump 0.4mm WLP and 40-Pin TQFN Packages
I2S/TDM
I2C
POWER
MANAGEMENT
DIGITAL AUDIO
INTERFACE
CONTROL
REGISTERS
STEREO
ADC
FLEXSOUND DSP
• DIGITAL BIQUAD FILTER
(RECORD)
• 7-BAND PARAMETRIC
EQUALIZER (PLAYBACK)
• DYNAMIC RANGE CONTROL
(PLAYBACK)
• DIGITAL FILTERING
• DIGITAL GAIN/LEVEL
CONTROL
JACK DETECTION
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX98090.related.
Ordering Information appears at end of data sheet.
STEREO
DAC
STEREO LINE OUTPUT
CLASS AB AMPLIFIER
(SINGLE ENDED)
OR
SPEAKER LEFT
CLASS D AMPLIFIER
(DIFFERENTIAL)
SPEAKER LEFT
CLASS D AMPLIFIER
(DIFFERENTIAL)
SPEAKER RIGHT
CLASS D AMPLIFIER
(DIFFERENTIAL)
LINE OUTPUT
OR
RECEIVER/
EARPIECE
SPEAKER
LEFT/RIGHT
STEREO HEADPHONE
CLASS H AMPLIFIER
(SINGLE ENDED)
LINE INPUT B PGA
(DIFFERENTIAL OR
SINGLE-ENDED)
3-POLE (TRS) 4-POLE (TRRS)
19-6492; Rev 2; 8/13
● 102dB DR Stereo DAC to HP (8kHz < fS < 96kHz)
● 3.6mW Stereo Playback Power Consumption
BATTERY 1.8V 1.2V
MICROPHONE 1
PREAMP/PGA
(DIFFERENTIAL)
MICROPHONE 2
PREAMP/PGA
(DIFFERENTIAL)
Features and Benefits
MAX98090
CHARGE PUMP
HEADPHONES
OR
HEADSET
MAX98090
Ultra-Low Power Stereo Audio Codec
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital Filter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Digital Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Digital Microphone Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Quiescent Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bump/Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Bump/Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Device I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Power and Performance Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Device Performance Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Device Enable Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Analog Audio Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Analog Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Analog Microphone Preamplifier and PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Analog Microphone Bias Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Digital Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Digital Microphone Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Digital Microphone Frequency Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Analog Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Analog Line Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Analog Line Input PGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Analog Input PGA to Analog Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Analog Full-Scale Direct to ADC Mixer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Audio Record Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ADC Functional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Maxim Integrated │ 2
MAX98090
Ultra-Low Power Stereo Audio Codec
TABLE OF CONTENTS (continued)
ADC Input Mixer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Record Path FlexSound DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Record Path Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Record Path Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Record Path Digital Gain and Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Digital Audio Interface (DAI) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DAI Clock Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Master Mode Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Quick Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Exact Integer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Manual Ratio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Slave Mode Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DAI Digital Audio Data Path Control and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DAI Digital Audio Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TDM Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Audio Playback Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Playback Path FlexSound DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Playback Path Digital Gain and Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Playback Path 7-Band Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Playback Path Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Playback Path Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Digital-to-Analog Converter (DAC) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Analog Audio Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Analog Class AB Configurable Receiver/Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Receiver/Earpiece Mixer and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Line Output Mixer and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Analog Class D Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Speaker Output Mixer and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Efficient Class D Speaker Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Analog Class-H Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Headphone Output Mixer and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Headphone Ground Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
DirectDrive Headphone Output Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Class H Amplifier Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Jack Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Jack Detection Internal Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Jack Detection Programmable Debounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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Maxim Integrated │ 3
MAX98090
Ultra-Low Power Stereo Audio Codec
TABLE OF CONTENTS (continued)
Jack Detection Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Operation with an Internal Pullup Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Operation with an External Pullup Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Accessory Button Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Jack Detection with Internal Analog Microphones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Quick Setup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Device Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Status Flag Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Device Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Startup/Shutdown Register Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Filterless Class D Speaker Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
EMI Considerations and Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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Maxim Integrated │ 4
MAX98090
Ultra-Low Power Stereo Audio Codec
LIST OF FIGURES
Figure 1. I2S Audio Interface Timing Diagrams (TDM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2. TDM Audio Interface Short Mode Timing Diagram (TDM = 1, BCI = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. I2C Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. Digital Microphone Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5. Analog Audio Input Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 6. Analog Microphone Input Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 7. Digital Microphone Input Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 8. Digital Microphone Compensation Filter Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 9. Analog Line Input Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 10. Analog Line Input External Gain Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 11. Analog Direct to ADC Mixer Input Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 12. Record Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 13. Record Path ADC Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 14. Record Path FlexSound Technology DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 15. Simplified Digital Audio Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 16. DAI Clock Control and Configuration Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 17. DAI Digital Data Path Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 18. Digital Audio Interface (DAI) Data Path Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 19. DAI Timing for I2S Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 20. DAI Timing for Left Justified Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 21. DAI Timing for Right Justified Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 22. DAI Timing for TDM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 23. Playback Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 24. Playback Path Sidetone and Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 25. Playback Path DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 26. Dynamic Range Compression and Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 27. DRC Enable and Make-Up Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 28. DRC Compression Ratio and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 29. DRC Expansion Ratio and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 30. DRC Attack and Release Time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 31. Playback Path Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 32. Analog Audio Output Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 33. Receiver Output Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 34. Stereo Single-Ended Line Output Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 35. Class D Speaker Output Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 36. DirectDrive Headphone Output Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 37. Reduced Power DAC Playback to Headphone Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 38. Headphone Output Ground Sense Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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Maxim Integrated │ 5
MAX98090
Ultra-Low Power Stereo Audio Codec
LIST OF FIGURES (continued)
Figure 39. Conventional vs. DirectDrive Headphone Output Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 40. Class H Amplifier Charge Pump Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 41. Class H Amplifier Supply Range Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 42. Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 43. Block Diagram and Typical Application Circuit for Jack Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 44. Jack Detection Cases with Internal Pullup Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 45. Jack Detection Operation with External Pullup Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 46. Jack Detection with Internal Analog Microphones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 47. START, STOP, and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 48. Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 49. Writing One Byte of Data to the MAX98090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 50. Writing n-Bytes of Data to the MAX98090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 51. Reading One Byte of Data from the MAX98090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 52. Reading n-Bytes of Data from the MAX98090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 53. Typical Application Circuit with Analog Microphone Inputs and Receiver Output . . . . . . . . . . . . . . . . . . 158
Figure 54. Typical Application Circuit with Digital Microphone Input and Stereo Line Outputs . . . . . . . . . . . . . . . . . 159
Figure 55. Optional Class D Ferrite Bead EMI Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 56. Optional Class H Output RMI Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 57. PCB Breakout Routing Example for WLP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 58. WLP Package Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
LIST OF TABLES
Table 1. MAX98090 Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 2. Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 3. Bias Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4. DAC and Headphone Performance Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 5. ADC Performance Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 6. Device Shutdown Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 7. Input Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 8. Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 9. Microphone 1 Enable and Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 10. Microphone 2 Enable and Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 11. Microphone Bias Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 12. Digital Microphone Clocks for Commonly Used Master Clocks Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 13. Digital Microphone Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 14. Digital Microphone Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 15. Recommended Compensation Filter Settings for f MCLK = 11.2896MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Maxim Integrated │ 6
MAX98090
Ultra-Low Power Stereo Audio Codec
LIST OF TABLES (continued)
Table 16. Recommended Compensation Filter Settings for f MCLK = 12MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 17. Recommended Compensation Filter Settings for f MCLK = 12.288MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 18. Recommended Compensation Filter Settings for f MCLK = 13MHz/26MHz . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 19. Recommended Compensation Filter Settings for f MCLK = 19.2MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 20. Recommended Compensation Filter Settings for f MCLK = 256 x fS . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 21. Line Input Mixer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 22. External Gain Mode Series Resistance Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 23. Line Input Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 24. Input Mode and Source Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 25. Left ADC Mixer Input Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 26. Right ADC Mixer Input Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 27. DSP Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 28. DSP Biquad Filter Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 29. Record Path Biquad Digital Preamplifier Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 30. Record Path Biquad Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 31. Record Path Sidetone Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 32. Left Record Path Digital Gain Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 33. Right Record Path Digital Gain Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 34. System Master Clock (MCLK) Prescaler Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 35. Master Mode Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 36. Master Clock Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 37. Sample Rate Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 38. Quick Configuration Mode Lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 39. Clock Mode Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 40. Manual Clock Ratio Configuration Register (NI MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 41. Manual Clock Ratio Configuration Register (NI LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 42. Manual Clock Ratio Configuration Register (MI MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 43. Manual Clock Ratio Configuration Register (MI MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 44. Digital Audio Interface (DAI) Data Path Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 45. Digital Audio Interface (DAI) Input/Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 46. Digital Audio Interface (DAI) Format Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 47. Digital Audio Interface (DAI) TDM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 48. Digital Audio Interface (DAI) TDM Format Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 49. Playback Gain and Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 50. DSP Biquad Filter Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 51. Parametric Equalizer Playback Level Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 52. Parametric Equalizer Band N (1–7) Biquad Filter Coefficient Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 53. Dynamic Range Control (DRC) Timing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Maxim Integrated │ 7
MAX98090
Ultra-Low Power Stereo Audio Codec
LIST OF TABLES (continued)
Table 54. Dynamic Range Control (DRC) Gain Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 55. Dynamic Range Control (DRC) Compressor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 56. Dynamic Range Control (DRC) Expander Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 57. DSP Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 58. Receiver and Left Line Output Mixer Source Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 59. Receiver and Left Line Output Mixer Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 60. Receiver and Left Line Output Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 61. Right Line Output Mixer Source Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 62. Right Line Output Mixer Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 63. Right Line Output Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 64. Left Speaker Mixer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 65. Right Speaker Mixer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 66 Speaker Mixer Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 67. Left Speaker Amplifier Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 68. Right Speaker Amplifier Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 69. Left Headphone Mixer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 70. Right Headphone Mixer Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 71. Headphone Mixer Control and Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 72. Left Headphone Amplifier Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 73. Right Headphone Amplifier Volume Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 74. Charge-Pump Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 75. Zero-Crossing Detection and Volume Smoothing Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 76. Jack Detection Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 77. Jack Detect Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 78. Jack Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 79. Digital Audio Interface (DAI) Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 80. Playback Path Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 81. Analog Microphone/Direct Input to Record Path Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 82. Line Input to Record Path Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 83. Analog Microphone Input to Analog Output Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 84. Line Input to Analog Output Quick Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 85. Device Status Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 86. Device Status Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 87. Revision ID Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 88. Device I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 89. Detailed Device Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 90. Register Changes that Require SHDN = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 91. Unused Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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Maxim Integrated │ 8
MAX98090
Ultra-Low Power Stereo Audio Codec
Functional Diagram
MCLK
LRCLK
BCLK
SDOUT
DVDD
DVDDIO
SDIN
SCL
DIGITAL AUDIO INTERFACE
DATA OUTPUT
ENABLE
MAS
PRESCALED
CLOCK (PCLK)
GENERATION
BCI
FRAME
CLOCK
USE_MI
NI[14:0]
MI[14:0]
PSCLK[1:0]
OUTPUT SHIFT
REGISTER
LOOP
BACK MUX
CLOCK GENERATION
AND DISTRIBUTION
FREQ[3:0]
TO DIGITAL
MIC CONTROL
INPUT SHIFT
REGISTER
RJ, DLY
WS[1:0]
BSEL[2:0]
BIAS
MAX98090
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
DMONO
DAI: DATA PATH
TO RECORD AND
PLAYBACK PATHS
LEFT RECORD PATH
ADLEN
DIGITAL
MIC
LEFT
MUX
ADC
LEFT
LEFT
FILTERS
LEFT
SIDETONE
MODE
AHPF
DHF
RECBQEN
AVBQ[3:0]
REC_B0[23:0]
REC_B1[23:0]
REC_B2[23:0]
REC_A1[23:0]
REC_A2[23:0]
DSTS[1:0]
RIGHT
FILTERS
RIGHT
BIQUAD
FILTER
RIGHT
SIDETONE
DIGMICR
DIGITAL
MIC
RIGHT
MUX
ADC
RIGHT
LEFT
LEVEL
LEFT
GAIN
AVLG[2:0]
AVL[3:0]
DVG[1:0]
AVRG[2:0]
AVR[3:0]
RIGHT
LEVEL
RIGHT
GAIN
L/R ST
LEVEL
RIGHT RECORD PATH
SIDETONE TO
PLAYBACK PATH
ADREN
LEFT
SIDETONE
DSTS[1:0]
RIGHT
SIDETONE
LEFT
LEVEL
DVM
DV[3:0]
RIGHT
LEVEL
LEFT 7-BAND
PARAMETRIC
EQUALIZER
LEFT/RIGHT DRC:
DYNAMIC
RANGE CONTROL
LEFT
FILTERS
EQ_BANDEN
DVEQ[3:0]
EQCLP
B0_EQ_[23:0]
B1_EQ_[23:0]
B2_EQ_[23:0]
A1_EQ_[23:0]
A2_EQ_[23:0]
DRCEN
DRCG[4:0]
DRCRLS[2:0]
DRCATK[2:0]
DRCCMP[2:0]
DRCTHC[4:0]
DRCEXP[2:0]
DRCHE[4:0]
MODE
DHPF
RIGHT 7-BAND
PARAMETRIC
EQUALIZER
RIGHT ALC:
AUTOMATIC
LEVEL CONTROL
RIGHT
FILTERS
MBVSEL[1:0]
MICROPHONE
BIAS
GENERATOR
MICBIAS
EXTMIC[0]
IN1-IN2
IN5-IN6
PA1EN[1:0]
MIXSPL[5:0]
MIXSPLG[1:0]
MIC 1
INPUT
MUX
MIC 1
PREAMP
0dB
10dB
30dB
IN2/DMC
IN5-IN6
IN1SEEN
IN3SEEN
IN5SEEN
IN34DIFF
IN4
IN1
IN3
IN5
IN3-IN4
IN5
LINE A
INPUT
MIXER
MIXG135
IN6
(WLP ONLY)
MIXG246
IN2
IN4
IN6
IN6-IN5
PGAM1[4:0]
DAC TO
ANALOG
OUTPUTS
DACR
RCV/
-12dB TO 0dB
LINE
OUT
LEFT
LINE A MIXER
MIC 1
MIC 2
PREAMP
0dB
10dB
30dB
PA2EN[1:0]
LINE B
DMDL
DMDR
DACR
RCV/
LINE
OUT
MIC 2 RIGHT
LINE A MIXER
0dB TO 20dB
ZDENB
IN2SEEN
IN4SEEN
IN6SEEN
IN65DIFF
LINE B
MIXSPL[5:0]
MIXSPLG[1:0]
DACL
MIXSPL[5:0]
MIXSPLG[1:0]
SPK
LEFT
MIC 2
MIXER
LINE A
MIC 2
PGA
0dB TO 20dB
-12dB TO 0dB
SPEAKER
LEFT PGA
LINE B
MIXADL[6:0]
LINE A
PGA
-6dB
TO 20dB
LINAPGA[2:0]
LINBPGA[2:0]
LINE B
PGA
-6dB
TO 20dB
LINEBEN
EXTBUFB
RCVLVOL[4:0]
RCVLM
RCVLEN
-62dB TO 8dB
DACL
IN5-IN6
DACR
LINE A
MIC 1
SPK
RIGHT
MIC 2
MIXER
LINE A
MIC 2
LINE B
ADC
LEFT
LINE B MIXER
MIC 1
-12dB TO 0dB
SPEAKER
RIGHT PGA
-62dB TO 8dB
LINE OUT
RIGHT PGA
MIXSPL[5:0]
MIXSPLG[1:0]
DACL
IN5-IN6
ADC
RIGHT
LINE B MIXER
MIXHPL[5:0]
MIXHPLG[1:0]
DACR
LINE A
MIC 1
HP
MIC 2 LEFT
MIXER
LINE A
MIC 1
RCVRVOL[4:0]
RCVRM
RCVREN
SPVOLL[4:0]
SPLM
SPLEN
SPKLGND
-48dB TO 14dB
SPKLP
SPKLN
6dB
HP
LEFT
MUX
MIXHPLSEL
MIXHPRSEL
ANALOG INPUT
TO ANALOG OUTPUT
LINE A
LINE B
DGND
-48dB TO 14dB
SPKRP
SPKRN
6dB
SPVOLR[4:0]
SPLM
SPREN
SPKRGND
HPVOLL[4:0]
HPLM
HPLEN
HEADPHONE
LEFT PGA
-67dB TO 3dB
ZDEN
VS2EN
VSEN
HPL
HPSNS
DACL
DACR
MIC 1
AGND
SPK_VDD
-12dB TO 0dB
LINE B
MIXADR[6:0]
RCVN/
LOUTR
SPKSLAVE
IN1-IN2
IN3-IN4
RCVP/
LOUTL
ZDEN
VS2EN
VSEN
ZDEN
VS2EN
VSEN
IN3-IN4
MIC 2
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RCV/
LINE
OUT
MUX
MIC 1
MIC 2
LINE B
INPUT
MIXER
-12dB TO 0dB
IN1-IN2
LINEAEN
EXTBUFA
DACREN
LINMOD
DACL
MIC 1
PGA
PGAM2[4:0]
DAC
RIGHT
LINE OUT
LEFT PGA
MIC 2
DACR
MIC 2
INPUT
MUX
EXTMIC[1]
IN3
DIGITAL
MICROPHONE
CONTROL
ANALOG
INPUTS
TO ADC
PCLK
MIC 1
IN1/DMD
IN3-IN4
MICCLK[2:0]
DACHP
PERFMODE
FLEXSOUND TECHNOLOGY DSP
DACL
MBEN
DAC
LEFT
RIGHT PLAYBACK PATH
SIDETONE FROM
PLAYBACK PATH
DVST[4:0]
JACK
DETECTION
DACLEN
LEFT PLAYBACK PATH
LEFT
BIQUAD
FILTER
DIGMICL
ADCHP
OSR128
ADCDITHER
JACKSNS
AVDD REF
BIAS CONTROL
AND GENERATION
LOOP
THROUGH
MUX
LBEN SDIEN
DAI: CLOCK CONTROL
AND CONFIGURATION
IRQ
LTEN
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
BIT
CLOCK
WCI
SDOEN
HIZOFF
SDA
I2C INTERFACE
HP
RIGHT
MIXER
-12dB TO 0dB
HP
RIGHT
MUX
MIXHPR[5:0]
MIXHPRG[1:0]
HEADPHONE
RIGHT PGA
HPVOLR[4:0]
HPRM
HPREN
-67dB TO 3dB
HEADPHONE
DIRECTDRIVE
CHARGE PUMP
HPR
HPVDD
HPGND
CPVSS CPVDD C1N C1P
Maxim Integrated │ 9
MAX98090
Ultra-Low Power Stereo Audio Codec
Absolute Maximum Ratings
(Voltages with respect to AGND, unless otherwise noted.)
AVDD, DVDD, HPVDD..........................................-0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDIO..........................-0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND..............-0.1V to +0.1V
CPVDD.............................(VHPGND - 0.3V) to (VHPGND + 2.2V)
CPVSS.............................(VHPGND - 2.2V) to (VHPGND + 0.3V)
C1N...................................(VCPVSS - 0.3V) to (VHPGND + 0.3V)
C1P................................... (VHPGND - 0.3V) to (VCPVDD + 0.3V)
MICBIAS.......................................... -0.3V to (VSPKLVDD + 0.3V)
REF, BIAS............................................. -0.3V to (VAVDD + 0.3V)
MCLK, SDIN, SDA, SCL, IRQ...............................-0.3V to +6.0V
LRCLK, BCLK, SDOUT..................... -0.3V to (VDVDDIO + 0.3V)
IN1, IN2, IN3, IN4, IN5, IN6..................................-0.3V to +2.2V
HPSNS.............................(VHPGND - 0.3V) to (VHPGND + 0.3V)
HPL, HPR..........................(VCPVSS - 0.3V) to (VCPVDD + 0.3V)
RCVP/LOUTL............ (VSPKLGND - 0.3V) to (VSPKLVDD + 0.3V)
RCVN/LOUTR........... (VSPKLGND - 0.3V) to (VSPKLVDD + 0.3V)
SPKLP, SPKLN......... (VSPKLGND - 0.3V) to (VSPKLVDD + 0.3V)
SPKRP, SPKRN.......(VSPKRGND - 0.3V) to (VSPKRVDD + 0.3V)
JACKSNS..............................................................-0.3V to +6.0V
Continuous Power Dissipation (TA = +70°C)
WLP (derate 23.8mW/°C above +70°C)...........................1.9W
TQFN (derate 35.7mW/°C above +70°C)......................2.86W
Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (θJA)...........42°C/W
TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........28°C/W
Junction-to-Case Thermal Resistance (θJC)..................2°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VSPKLVDD, VSPKVDD,
VSPKRVDD
2.8
3.7
5.5
VAVDD, VHPVDD
1.65
1.8
2
VDVDD
1.08
1.2
1.98
VDVDDIO
1.65
1.8
3.6
Full-duplex 8kHz Analog
mono, receiver
Speaker
output
Digital
1.94
3.5
0.73
2
0.97
1.2
DAC playback
48kHz stereo,
headphone
outputs
Analog
1.45
2
0
0.005
Digital
1.04
1.3
DAC playback
48kHz stereo,
speaker outputs
Analog
0.91
2.4
Speaker
2.18
3
Digital
1.05
1.3
UNITS
POWER SUPPLY
Guaranteed by
PSRR (Note 3)
Supply Voltage Range
Quiescent Supply Current (Note 4)
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IVDD
Speaker
V
mA
Maxim Integrated │ 10
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
REF Voltage
TYP
MAX
1.25
BIAS Voltage
Shutdown Supply Current (Note 4)
BIAS from resistive division (BIAS_MODE
= 0)
0.90
BIAS from bandgap
(BIAS_MODE = 1)
0.78
TA = +25°C
UNITS
V
V
Analog
1
10
Speaker
1
5
2.1
20
Digital
Shutdown to Full Operation
µA
10
ms
97
dB
96
dB
DIFFERENTIAL INPUT (ANALOG MICROPHONE) TO ADC RECORD PATH
Dynamic Range (Note 5)
DR
fS = 48kHz, MODE = 1 (FIR audio),
A-weighting filter applied
fS = 8kHz, MODE = 0 (IIR voice),
A-weighting filter applied
90
AV_MICPRE = 20dB, VIN = 90mVRMS,
f = 1kHz,
Total Harmonic Distortion + Noise
Common-Mode Rejection Ratio
THD+N
CMRR
AV_MICPRE = 0dB, VIN = 900mVRMS,
Path Phase Delay
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PSRR
-91
f = 1kHz
AV_MICPRE = 30dB,
VIN = 28.5mVRMS, f = 1kHz
-73
f = 217Hz, VIN_CM = 100mVP-P
59
VAVDD = 1.65V to 2.0V,
input referred
Power-Supply Rejection Ratio
(Note 3)
-82
VRIPPLE = 100mVP-P,
input referred
1kHz, 0dB input,
highpass filter disabled
measured from analog
input to digital output
40
-75
dB
dB
57
f = 217Hz
60
f = 1kHz
60
f = 10kHz
59
MODE = 0
(voice) 8kHz
2.2
MODE = 0
(voice) 16kHz
1.1
MODE = 1
(music) 8kHz
4.5
MODE = 1
(music) 48kHz
0.8
dB
ms
Maxim Integrated │ 11
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Gain Error
CONDITIONS
MIN
DC accuracy
TYP
MAX
UNITS
1
6.2
%
DIFFERENTIAL (ANALOG MICROPHONE) PREAMP and PGA
Full-Scale Input
AV_MICPRE = 0dB
1
PA_EN[1:0] = 01
Microphone Preamplifier Gain
Microphone Level Adjust Gain
(PGA)
MIC Input Resistance
AV_MICPRE (Note 6)
AV_MICPGA (Note 6)
RIN_MIC
VRMS
0
PA_EN[1:0] = 10
19
20
21
PA_EN[1:0] = 11
29
30
31
PGAM_[4:0] = 0x00
19
20
21
PGAM_[4:0] = 0x14
0
All gain settings, measured at IN_
(measured single-ended)
28
50
ILOAD = 1mA, MBVSEL[1:0] = 00
2.1
2.2
2.3
ILOAD = 1mA, MBVSEL[1:0] = 01
2.3
2.4
2.5
ILOAD = 1mA, MBVSEL[1:0] = 10
2.475
2.57
2.7
ILOAD = 1mA, MBVSEL[1:0] = 11
2.7
2.8
2.9
dB
dB
kΩ
MICROPHONE BIAS
MICBIAS Output Voltage
VMICBIAS
WLP
±0.085
±0.5
TQFN
±0.085
±0.75
±0.01
±1
Load Regulation
ILOAD = 1mA to 2mA,
MBVSEL[1:0] = 00
Line Regulation
VSPKLVDD = 2.8V to 5.5V, MBVSEL[1:0]
= 00
Ripple Rejection
VRIPPLE (SPKLVDD)
= 100mVP-P
Noise Voltage
f = 217Hz
95
f = 1kHz
97
f = 10kHz
V
mV
mV
dB
85
A-weighted, f = 20Hz to 20kHz
7.4
µVRMS
f = 1kHz
52.3
nV/√Hz
fS = 48kHz, fMCLK = 12.288MHz, MODE =
1 (FIR audio)
98
dB
VIN = 0.222VRMS, f = 1kHz
-85
SINGLE-ENDED (LINE) INPUT TO ADC PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
-80
dB
SINGLE-ENDED (LINE) INPUT PGA
Full-Scale Input www.maximintegrated.com
VIN
0.5
AV_EXTERNAL = -6dB, EXTBUF = 1
1
VRMS
Maxim Integrated │ 12
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Line Input Level Adjust Gain (PGA) AV_LINEPGA (Note 6)
Line Input Amplifier Gain
Input Resistance
Feedback Resistance CONDITIONS
MIN
TYP
MAX
PGALIN = 0x0
18
20
21.5
PGALIN = 0x1
13
14
15
PGALIN = 0x2
2
3
4
PGALIN = 0x3
-1
0
+1
PGALIN = 0x4
-4
-3
-2
PGALIN = 0x5,
0x6, 0x7
-7
-6
-5
AV_LINEAMP Single-ended only
RIN
RIN_FB
TA = +25°C
UNITS
dB
6
dB
14
20
kΩ
19
20
21
kΩ
DIGITAL LOOP-THROUGH: RECORD OUTPUT TO PLAYBACK INPUT PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
fS = 48kHz, fMCLK = 12.288MHz, MODE =
1 (FIR audio)
97
fIN = 1kHz, fS = 48kHz, fMCLK =
12.288MHz, MODE = 1 (FIR audio)
-83
dB
-72
dB
DAC PLAYBACK PATH TO RECEIVER AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
fS = 48kHz, fMCLK = 12.288MHz
100
f = 1kHz, POUT = 20mW,
RREC = 32W
-68
dB
-58
dB
DIFFERENTIAL ANALOG INPUT TO RECEIVER AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
90
THD+N
VSPKLVDD = 2.8V to 5.5V
Power-Supply Rejection Ratio
(Note 3)
PSRR
VRIPPLE = 100mVP-P
68.4
96
dB
-71
dB
80
f = 217Hz
77
f = 1kHz
77
f = 10kHz
69
dB
RECEIVER AMPLIFIER (Note 7)
Output Power
Full-Scale Output
Receiver Volume Control (PGA)
www.maximintegrated.com
POUT
RREC = 32W, f = 1kHz, THD < 1%, BIAS_
MODE = 0
97
RREC = 32W, f = 1kHz, THD < 1%, BIAS_
MODE = 1
74
mW
AV_RECPGA = 0dB (Note 8)
AV_RECPGA (Notes 6 and 9)
1
VRMS
RCVLVOL = 0x00
-63
-61
-59.5
RCVLVOL = 0x1F
+7.2
+8
+8.75
dB
Maxim Integrated │ 13
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Volume Control Step Size
(Note 9)
Mute Attenuation
Output Offset Voltage
Click-and-Pop Level
CONDITIONS
TYP
+8dB to +6dB
0.5
+6dB to +0dB
1
0dB to -14dB
2
-14dB to -38dB
3
-38dB to -62dB
4
f = 1kHz
87
VOS
AV_REC = -62dB, TA = +25°C
KCP
Peak voltage,
A-weighted,
32 samples
per second,
AV_REC = 0dB
No sustained
oscillations
Capacitive Drive Capability
MIN
MAX
UNITS
dB
97
dB
±3
Into shutdown
-67
Out of shutdown
-68
RL = 32W
500
RL = ∞
100
mV
dBV
pF
DAC PLAYBACK PATH TO LINEOUT AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
fS = 48kHz, fMCLK = 12.288MHz
100
f = 1kHz, RLOUT = 10kW
(0.5VRMS output level)
-86
dB
-70
dB
SINGLE-ENDED ANALOG INPUT TO LINE OUT AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
f = 1kHz, RLOUT = 10kW
(0.5VRMS output level)
VSPK_VDD = 2.8V to 5.5V
Power-Supply Rejection Ratio
(Note 3)
PSRR
VRIPPLE = 100mVP-P
60
98
dB
-86
dB
74
f = 217Hz
74
f = 1kHz
74
f = 10kHz
73
dB
LINE OUT AMPLIFIER (Note 7)
Full-Scale Output
Line Output Amplifier Gain
www.maximintegrated.com
(Note 8)
AV_LOUTAMP
0.707
VRMS
-3
dB
Maxim Integrated │ 14
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
Line Output Volume
Control (PGA)
SYMBOL
AV_LOUTPGA (Notes 6 and 9)
Volume Control Step Size
(Note 9)
MIN
TYP
RCV_VOL = 0x00
-63
-61
-59.5
RCV_VOL = 0x1F
+7.2
+8
+8.75
CONDITIONS
8dB to 6dB
0.5
6dB to 0dB
1
0dB to -14dB
2
-14dB to -38dB
3
-38dB to -62dB
4
Mute Attenuation
f = 1kHz
Capacitive Drive Capability
No sustained
oscillations
87
MAX
UNITS
dB
dB
97
dB
RLOUT = 1kW
500
RLOUT = ∞
100
pF
DAC PLAYBACK PATH TO SPEAKER AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
Crosstalk
91
dB
f = 1kHz, POUT = 200mW, ZSPK = 8W +
68µH, fMCLK = 12.288MHz
-70
dB
SPKL to SPKR and SPKR to SPKL,
POUT = 640mW, f = 1kHz
-104
dB
27
µVRMS
Output referenced to 2VRMS
91
dB
f = 1kHz, POUT = 200mW,
ZSPK = 8W + 68mH
-70
dB
28
µVRMS
Output Noise
DIFFERENTIAL ANALOG INPUT TO SPEAKER AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
Output Noise
VSPK_VDD= 2.8V to 5.5V
Power-Supply Rejection Ratio
(Note 3)
www.maximintegrated.com
PSRR
VRIPPLE = 100mVP-P
50
80
f = 217Hz
68
f = 1kHz
67
f = 10kHz
61
dB
Maxim Integrated │ 15
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPEAKER AMPLIFIER (Note 7)
f = 1kHz, THD+N
= 1%, ZSPK =
8W + 68µH, WLP
package
Output Power
POUT
f = 1kHz, THD+N
= 10%, ZSPK =
8W + 68µH, WLP
package
f = 1kHz, THD+N
= 1%, ZSPK =
4W + 33µH, WLP
package
Output Power
POUT
f = 1kHz, THD+N
= 10%, ZSPK =
4W + 33µH, WLP
package
Full-Scale Output
1450
VSPK_VDD = 4.2V
1000
VSPK_VDD = 3.7V
780
VSPK_VDD = 3.3V
600
VSPK_VDD = 3.0V
500
VSPK_VDD = 5.0V
1800
VSPK_VDD = 4.2V
1250
VSPK_VDD = 3.7V
970
VSPK_VDD = 3.3V
760
VSPK_VDD = 3.0V
620
VSPK_VDD = 5.0V
2600
VSPK_VDD = 4.2V
1800
VSPK_VDD = 3.7V
1400
VSPK_VDD = 3.3V
1100
VSPK_VDD = 3.0V
900
VSPK_VDD = 5.0V
3250
VSPK_VDD = 4.2V
2250
VSPK_VDD = 3.7V
1700
VSPK_VDD = 3.3V
1350
VSPK_VDD = 3.0V
1100
AV_SPK = +6dB (Note 8)
Speaker Output Amplifier Gain
AV_SPKAMP
Speaker Volume Control (PGA)
AV_SPKPGA (Notes 6 and 9)
Volume Control Step Size
(Note 9)
VSPK_VDD = 5.0V
www.maximintegrated.com
2
VRMS
+6
dB
-51
-48
-44.5
SPVOLR = 0x1F
13
14
15
14dB to 9dB
0.5
+9dB to -6dB
1
-6dB to -14dB
2
-14dB to -32dB
3
f = 1kHz
mW
SPVOLL = 0x00
-32dB to -48dB
Mute Attenuation
mW
dB
dB
4
76
84
dB
Maxim Integrated │ 16
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
Output Offset Voltage
Click-and-Pop Level
SYMBOL
CONDITIONS
VOS
AV_SPKPGA = -62dB, TA = +25°C
KCP
Peak voltage,
A-weighted,
32 samples
per second,
AV_SPK = 0dB
MIN
Into shutdown
TYP
MAX
UNITS
±0.5
±4
mV
-65
dBV
Out of shutdown
-65
fS = 48kHz,
fMCLK =
12.288MHz
Master or slave
mode
102
f = 1kHz, POUT =
10mW
RHP = 16W
-86
RHP = 32W
-88
DAC PLAYBACK PATH TO HEADPHONE AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
DR
THD+N
Crosstalk
Slave mode
94
PSRR
dB
-88
f = 1kHz, VIN = -1dBFS, RHP = 10kW
-105
dB
HPL to HPR and HPR to HPL,
POUT = 5mW, f = 1kHz, RHP = 32W
-104
dB
70
f = 217Hz
VRIPPLE = 100mVP-P,
f = 1kHz
AV_HP = 0dB
f = 10kHz
1kHz, 0dB input,
highpass filter disabled
measured from digital
input to analog output
DAC Path Phase Delay
-77
f = 1kHz, VOUT = 1VRMS, RHP = 10kW
VAVDD = VHPVDD = 1.65V to 2.0V
Power-Supply Rejection Ratio
(Note 3)
dB
80
79
dB
79
74
MODE = 0 (voice)
8kHz
2.2
MODE = 0 (voice)
16kHz
1.1
MODE = 1
(music) 8kHz
4.5
MODE = 1
(music) 48kHz
0.76
ms
Gain Error
1
Channel Gain Mismatch
1
5
%
%
101
dB
-80
dB
-94
dB
SINGLE-ENDED ANALOG INPUT TO HEADPHONE AMPLIFIER PATH
Dynamic Range (Note 5)
Total Harmonic Distortion + Noise
Crosstalk
www.maximintegrated.com
AV_LINE = 0dB AV_HPPGA = 0 dB
THD+N
VIN = 250mVRMS, f =1kHz
HPL to HPR and HPR to HPL,
POUT = 5mW, f = 1kHz, RHP = 32W
Maxim Integrated │ 17
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
VAVDD = VHPVDD = 1.65V to 2.0V
Power-Supply Rejection Ratio
(Note 3)
PSRR
VRIPPLE = 100mVP-P,
AV_TOTAL = 0dB
MIN
TYP
40
60
f = 217Hz
61
f = 1kHz
61
f = 10kHz
60
MAX
UNITS
dB
HEADPHONE AMPLIFIER (Note 7)
Output Power
Total Harmonic Distortion + Noise
POUT
THD+N
Full-Scale Output
Headphone Volume Control (PGA)
RHP = 16W
20
RHP = 32W
RHP = 16W, POUT = 10mW, f = 1kHz
-88
RHP = 10kW, VOUT = 1VRMS,
f = 1kHz
-88
AV_HPPGA
Mute Attenuation
-69
-67
-65
HPVOL_ = 0x1F
2.5
3
3.5
0.5
1
-5dB to -19dB
2
-19dB to -43dB
3
-43dB to -67dB
4
No sustained
oscillations
Click-and-Pop Level
Peak voltage,
A-weighted,
32 samples
per second,
AV_HP = -67dB
KCP
dB
HPVOL_ = 0x00
+1dB to -5dB
Capacitive Drive Capability
-77
VRMS
+3dB to +1dB
AV_HP = -67dB
mW
1
f = 1kHz
VOS
40
30
AVHP = 0dB (Note 8)
Volume Control Step Size
(Note 9)
Output Offset Voltage
f = 1kHz, THD = 1%
dB
110
TA = +25°C
dB
±0.5
TA = TMIN to TMAX
dB
±1
±3
RHP = 32W
500
RHP = ∞
100
Into shutdown
-73
mV
pF
dBV
Out of shutdown
-73
JACK DETECTION
MICBIAS enabled
JACKSNS High Threshold
www.maximintegrated.com
VTH_HIGH
MICBIAS disabled
0.80 x
0.95 x
0.98 x
VMICBIAS VMICBIAS VMICBIAS
0.80 x
0.95 x
0.98 x
V
VSPKLVDD VSPKLVDD VSPKLVDD
Maxim Integrated │ 18
MAX98090
Ultra-Low Power Stereo Audio Codec
Electrical Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MICBIAS enabled
JACKSNS Low Threshold
VTH_LOW
MICBIAS disabled
JACKSNS Sense Voltage
VSENSE
JACKSNS Strong Pullup
Resistance
RSPU
MICBIAS disabled, JDWK = 0
JACKSNS Weak Pullup Current
IWPU
JACKSNS Glitch Debounce Period
www.maximintegrated.com
tGLITCH
MIN
TYP
MAX
0.06 x
0.10 x
0.17 x
VMICBIAS VMICBIAS VMICBIAS
0.06 x
0.10 x
0.17 x
UNITS
V
VSPKLVDD VSPKLVDD VSPKLVDD
MICBIAS disabled
VSPKLVDD
1.9
V
2.4
2.7
kΩ
MICBIAS disabled, JDWK = 1
5
12
µA
JDEB = 00
25
JDEB = 11
200
ms
Maxim Integrated │ 19
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Filter Specifications
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line Output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+3
dB
RECORD PATH LEVEL CONTROL
Record Level Adjust Range
AV_ADCLVL
AVL/AVR = 0xF to 0x0 (Note 6)
-12
Record Level Adjust Step Size
Record Gain Adjust Range
1
AV_ADCGAIN AVLG/AVRG = 0x0 to 0x3 (Note 6)
0
Record Gain Adjust Step Size
dB
42
6
dB
dB
RECORD PATH VOICE MODE IIR LOWPASS FILTER (MODE = 0)
Passband Cutoff fPLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff 0.444
x fS
-3dB cutoff 0.449
x fS
f < fPLP -0.1
fSLP
Stopband Attenuation
f > fSLP Hz
0.1
dB
0.47
x fS
Hz
74
dB
RECORD PATH STEREO MUSIC MODE FIR LOWPASS FILTER (MODE = 1, DHF = 0, fLRCLK < 50kHz)
Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff 0.43
x fS
-3dB cutoff 0.48
x fS
-6.02dB cutoff 0.5
x fS
f < fPLP -0.1
fSLP
Stopband Attenuation
f < fSLP Hz
+0.1
dB
0.58
x fS
Hz
60
dB
RECORD PATH STEREO MUSIC MODE FIR LOWPASS FILTER (MODE = 1, DHF = 1, fLRCLK > 50kHz)
Passband Cutoff fPLP
Passband Ripple
Stopband Cutoff
Stopband Attenuation
www.maximintegrated.com
Ripple Limit cutoff 0.208
x fS
-3dB cutoff 0.28
x fS
f < fPLP -0.1
fSLP
f < fSLP 60
Hz
+0.1
dB
0.45
x fS
Hz
dB
Maxim Integrated │ 20
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Filter Specifications (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line Output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RECORD PATH DC-BLOCKING HIGHPASS FILTER
DC Attenuation
AV_ADCHPF
AHPF = 1
90
dB
RECORD PATH PROGRAMMALE BIQUAD FILTER
Preattenuator Gain Range
-15
Preattenuator Step Size
0
1
Highpass filter
Cutoff Frequency
Quality Factor
Q
dB
dB
0.0008
x fS
High-frequency shelving filter
0.02
x fS
Lowpass filter
0.002
x fS
Low-frequency shelving filter
0.0008
x fS
Peak filter
0.0008
x fS
Hz
Peak filter
10
DIGITAL SIDETONE: RECORD PATH TO PLAYBACK PATH (MODE = 0)
Sidetone Level Adjust Range
AV_STLVL
DVST = 0x1F to 0x01
-60.5
Sidetone Level Adjust Step Side
-0.5
2
fIN = 1kHz, full-scale amplitude, fS = 8kHz
highpass filter disabled
fS = 16kHz
Sidetone Path Phase Delay
dB
dB
1.8
ms
0.9
PLAYBACK PATH LEVEL CONTROL Playback Path Attenuation
Range
Playback Path Attenuation Step
Size
Playback Path Gain Adjust
Range
www.maximintegrated.com
AV_DACLVL
DV = 0xF to 0x0 (Note 6)
-15
AV_DACGAIN DVG = 00 to 11 (Note 6)
0
1
0
dB
dB
18
dB
Maxim Integrated │ 21
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Filter Specifications (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line Output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 10)
Playback Path Gain Adjust Step
Size
PARAMETER
SYMBOL
6
CONDITIONS
MIN
dB
TYP
MAX
UNITS
PLAYBACK PATH VOICE MODE IIR LOWPASS FILTER (MODE = 0) Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
Ripple limit cutoff
0.448
x fS
-3dB cutoff
0.451
x fS
f < fPLP
fSLP
Stopband Attenuation (Note 11)
Hz
-0.1
f > fSLP +0.1
dB
0.476
x fS
Hz
75
dB
PLAYBACK PATH STEREO MUSIC MODE FIR LOWPASS FILTER (MODE = 1, DHF = 0, fLRCLK < 50kHz) Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
fSLP
Stopband Attenuation (Note 11)
Ripple limit cutoff 0.43
x fS
-3dB cutoff 0.47
x fS
-6.02dB cutoff 0.5
x fS
f < fPLP -0.1
Hz
f > fSLP +0.1
dB
0.58
x fS
Hz
60
dB
PLAYBACK PATH STEREO MUSIC MODE FIR LOWPASS FILTER (MODE1 = 1, DHF = 1 for fLRCLK > 50kHz) Passband Cutoff
fPLP
Passband Ripple
Stopband Cutoff
Stopband Attenuation (Note 11)
www.maximintegrated.com
fSLP
Ripple limit cutoff
0.24
x fS
-3dB cutoff
0.31
x fS
f < fPLP
-0.1
f < fSLP
60
Hz
+0.1
dB
0.477
x fS
Hz
dB
Maxim Integrated │ 22
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Filter Specifications (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line Output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 10)
PLAYBACK PATH DC-BLOCKING HIGHPASS FILTER
DC Attenuation
PARAMETER
DHPF = 1
SYMBOL
89
CONDITIONS
MIN
dB
TYP
MAX
UNITS
0
12
dB
-31
0
dBFS
-66
-35
dBFS
0.0005
0.2
s
0.0625
8
s
Number of Bands
Per Band Gain Range
-12
+12
dB
Preattenuator Gain Range
-15
0
dB
Preattenuator Step Size
Highpass filter
0.0008
x fS
PLAYBACK PATH DYNAMIC RANGE CONTROL Gain Range
Compression Threshold
Expansion Threshold
Attack Time
Release Time
PLAYBACK PATH PARAMETRIC EQUALIZER
Cutoff Frequency
Quality Factor
www.maximintegrated.com
Q
7
1
High-frequency shelving filter
0.02
x fS
Lowpass filter
0.002
x fS
Low-frequency shelving filter
0.0008
x fS
Peak filter
0.0008
x fS
Peak filter
Bands
dB
Hz
10
Maxim Integrated │ 23
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Input/Output Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MCLK
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
IIH, IIL
1.26
VDVDDIO = 2.0V, TA = +25°C
V
-1
Input Capacitance
0.6
V
+1
µA
10
pF
SDIN, BCLK, LRCLK (Input)
Input High Voltage
VIH
Input Low Voltage
VIL
0.7 x
VDVDDIO
0.3 x
VDVDDIO
Input Hysteresis
Input Leakage Current
V
100
IIH, IIL
VDVDDIO = 3.6V, TA = +25°C
-1
Input Capacitance
V
mV
+1
10
µA
pF
BCLK, LRCLK, SDOUT (Output)
Output High Voltage
VOH
IOH = 3mA
Output Low Voltage
VOL
IOL = 3mA
Input Leakage Current
IIH, IIL
VDVDDIO = 2.0V, TA = +25°C,
high-impedance state
VDVDDIO
- 0.4
V
-1
0.4
V
+1
µA
SDA, SCL (Input)
Input High Voltage
VIH
Input Low Voltage
VIL
0.7 x
VDVDDIO
0.3 x
VDVDDIO
Input Hysteresis
Input Leakage Current
V
100
IIH, IIL
VDVDDIO = 2.0V, TA = +25°C
Input Capacitance
-1
mV
+1
10
SDA, IRQ (Output)
V
µA
pF
Output Low Voltage
VOL
VDVDDIO = 1.65V, IOH = 3mA
0.2 x
VDVDDIO
V
Output High Current
IOH
VDVDDIO = 1.65V, IOL = 3mA
1
µA
www.maximintegrated.com
Maxim Integrated │ 24
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Input/Output Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL MICROPHONE DATA (DMD) INPUT
Input High Voltage
VIH
Input Low Voltage
VIL
0.65 x
VDVDDIO
0.35 x
VDVDDIO
Input Hysteresis
Input Leakage Current
V
100
IIH, IIL
VDVDDIO = 2.0V, TA = +25°C
-25
Input Capacitance
V
mV
+25
10
µA
pF
DIGITAL MICROPHONE CLOCK (DMC) OUTPUT
Output High Voltage
VOH
IOH = 3mA
Output Low Voltage
VOL
IOL = 3mA
www.maximintegrated.com
VAVDD 0.4
V
0.4
V
Maxim Integrated │ 25
MAX98090
Ultra-Low Power Stereo Audio Codec
Input Clock Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD= 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS
= 0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CLOCK CHARACTERISTICS
fS = 8kHz, voice mode filters
(MODE = 0)
MCLK Input Frequency
fMCLK
MCLK Input Duty Cycle
2.048
60
fS = 48kHz, music mode filters
(MODE = 1)
10
60
fS = 96kHz, music mode filters
(MODE = 1)
12.288
60
PSCLK = 01
40
PSCLK = 10 or 11
30
Maximum MCLK Input Jitter
LRCLK Sample Rate (Note 12)
DAI LRCLK Average Frequency
Error (Note 13)
fLRCLK
8
48
DHF = 1
48
96
FREQ = 0x8 to 0xF
FREQ = 0x0
8kHz ≤ fS ≤ 48kHz,
music mode filters
(MODE = 1), DHF = 0
0
0
-0.025
+0.025
OSR = 128
or 64
256 x fS
OSR = 128
256 x fS
OSR = 64
208 x fS
OSR = 64
128 x fS
www.maximintegrated.com
kHz
%
fPCLK
2
Maximum LRCLK Input Jitter
to Maintain PLL Lock
Soft-Start/Stop Time
%
ns
DHF = 0
48kHz < fS ≤ 96kHz,
music mode filters
(MODE = 1), DHF = 1
PLL Lock Time
60
70
1
8kHz ≤ fS ≤ 48kHz,
voice mode filters
(MODE = 0), DHF = 0
Minimum PCLK to LRCLK
Frequency Ratio
50
MHz
10
7
ms
±100
ns
ms
Maxim Integrated │ 26
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Audio Interface Timing Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS
BCLK Cycle Time
tBCLK
Slave mode
80
ns
BCLK High Time
tBCLKH
Slave mode
20
ns
BCLK Low Time
tBCLKL
Slave mode
20
ns
BCLK or LRCLK Rise and
Fall Time
SDIN to BCLK Setup Time
LRCLK to BCLK Setup Time
SDIN to BCLK Hold Time
LRCLK to BCLK Hold Time
tr, tf
tSETUP
tSYNCSET
Slave mode
tHOLD
tSYNCHOLD
Minimum Delay Time from LSB
BCLK Falling Edge to HighImpedance State
tHIZOUT
LRCLK Rising Edge to
SDOUT MSB Delay
tSYNCTX
BCLK to SDOUT Delay
Master mode, CL = 15pF
tCLKTX
Slave mode
Master mode
www.maximintegrated.com
tCLKSYNC
ns
20
ns
20
ns
20
Master mode
ns
20
TDM = 1, FSW = 1
20
TDM = 1, FSW = 0
20
TDM = 0, DLY = 1
20
C = 30pF, TDM = 1, FSW = 1
C = 30pF
ns
20
TDM = 1
ns
40
TDM = 1, BCLK
rising edge
50
TDM = 0
50
TDM = 1
Delay Time from BCLK to LRCLK
5
TDM = 0
-15
ns
ns
+15
0.8 x
tBCLK
ns
Maxim Integrated │ 27
MAX98090
Ultra-Low Power Stereo Audio Codec
tBCLK
tF
t
BCLK R
(OUTPUT)
tBCLKH
BCLK
(INPUT)
tCLKSYNC
tSYNCSET
LRCLK
(OUTPUT)
LSB
SDIN
(INPUT)
LSB
LRCLK
(INPUT)
tCLKTX
tHIZOUT
SDOUT
(OUTPUT)
tBCLKL
HI-Z
MSB
tSETUP tHOLD
MSB
MASTER MODE
tCLKTX
tHIZOUT
SDOUT
(OUTPUT)
LSB
SDIN
(INPUT)
LSB
HI-Z
MSB
tSETUP tHOLD
MSB
SLAVE MODE
Figure 1. I2S Audio Interface Timing Diagrams (TDM = 0)
TDM SHORT MODE TIMING (fSW= 0)
tF
BCLK
(OUTPUT)
BCLK
(OUTPUT)
HI-Z
MSB
tSETUP
SDIN
(INPUT)
tSYNCSET
LRCLK
(OUTPUT)
tHIZOUT
tCLKTX
LSB
LSB
tBCLKL
tBCLKH
tCLKSYNC
tCLKSYNC
LRCLK
(OUTPUT)
tHIZOUT
SDOUT
(OUTPUT)
tBCLK
tR
tHOLD
SDOUT
(OUTPUT)
tCLKTX
LSB
HI-Z
MSB
tHOLD
MASTER MODE
SLAVE MODE
TDM LONG MODE TIMING (fSW = 1)
tF
BCLK
(OUTPUT)
SDOUT
(OUTPUT)
SDIN
(INPUT)
tR
tENDSYNC
LRCLK
(OUTPUT)
tHI-ZOUT
HI-Z
tBCLKL
tCLKSYNC
tCLKTX
MSB
tSETUP
LSB
tBCLK
tBCLKH
BCLK
(OUTPUT)
tSYNCTX
LSB
tSETUP
MSB
LSB
SDIN
(INPUT)
MSB
tSYNCHOLD
MSB
tHOLD
LRCLK
(OUTPUT)
tHI-ZOUT
SDOUT
(OUTPUT)
LSB
SDIN
(INPUT)
MASTER MODE
tCLKTX
tSYNCTX
HI-Z
MSB
tSETUP
LSB
tHOLD
MSB
SLAVE MODE
Figure 2. TDM Audio Interface Short Mode Timing Diagram (TDM = 1, BCI = 1)
www.maximintegrated.com
Maxim Integrated │ 28
MAX98090
Ultra-Low Power Stereo Audio Codec
I2C Timing Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
I2C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS
Guaranteed by SCL pulse width low
and high
Serial Clock Frequency
fSCL
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD,STA
0.6
µs
SCL Pulse-Width Low
tLOW
1.3
µs
SCL Pulse-Width High
tHIGH
0.6
µs
tSU,STA
0.6
µs
Setup Time for a Repeated START
Condition
Data Hold Time
tHD,DAT
0
RPU = 475Ω, CB = 100pF, 400pF
0
900
Transmitting
0
900
Receiving
Data Setup Time
ns
0
tSU,DAT
100
ns
SDA and SCL Receiving Rise Time
tR
(Note 14)
20 + 0.1
x CB
300
ns
SDA and SCL Receiving Fall Time
tF
(Note 14)
20 + 0.1
x CB
300
ns
SDA Transmitting Fall Time
tF
RPU = 475Ω, CB = 100pF to 400pF
(Note 14)
20 + 0.1
x CB
250
ns
Setup Time for STOP Condition
tSU,STO
Bus Capacitance
CB
Pulse Width of Suppressed Spike
tSP
0.6
µs
Guaranteed by SDA transmitting fall
time
0
400
pF
50
ns
SDA
tSU,STA
tSU,DAT
tLOW
tHD,DAT
tHD,STA
tBUF
tSP
tSU,STO
tHIGH
SCL
tHD,STA
START CONDITION
tR
tF
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 3. I2C Interface Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 29
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Microphone Timing Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected
between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P =
CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS
DMC Frequency
fDMC
MICCLK = 000
fPCLK/2
MICCLK = 001
fPCLK/3
MICCLK = 010
fPCLK/4
MICCLK = 011
fPCLK/5
MICCLK = 100
fPCLK/6
MICCLK = 101
fPCLK/8
MHz
DMD to DMC Setup Time
tSU,MIC
Either clock edge
20
ns
DMD to DMC Hold Time
tHD,MIC
Either clock edge
0
ns
1/fDMC
DMC
tHD,MIC tSU,MIC
tHD,MIC tSU,MIC
DMD
LEFT
RIGHT
LEFT
RIGHT
Figure 4. Digital Microphone Timing Diagram
Note 2: The MAX98090 is 100% production tested at TA =+25°C. Specifications over temperature limits are guaranteed by design.
Note 3: BIAS derived from a bandgap reference (BIAS_MODE = 1).
Note 4: Analog supply current = AVDD + HPVDD, speaker supply current = SPKLVDD + SPKRVDD, and digital supply current =
DVDD + DVDDIO.
Note 5: Dynamic range measurements are performed with the EIAJ method (a -60dBFS output signal at 1kHz, A-weighted and normalized to 0dBFS; f = 20Hz – 20kHz).
Note 6: Gain measured relative to the 0dB setting.
Note 7: Performance measured using DAC Inputs, unless otherwise stated.
Note 8: Full-scale analog output with 0dB of programmable gain, and a 0dBFS DAC input amplitude, a 1VRMS differential analog
input amplitude, or a 0.5VRMS single-ended analog input amplitude.
Note 9: Performance measured using an analog input to amplifier output path.
Note 10:Digital filter performance is invariant over temperature and production tested at TA = +25°C.
Note 11:The filter specification is accurate only for synchronous clocking modes (integer MCLK to LRCLK ratio).
Note 12:fLRCLK may be any rate in the indicated range. Asynchronous and non-integer fMCLK/fLRCLK ratios can exhibit some fullscale performance degradation compared to synchronous integer ratios.
Note 13:In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 14:CB is in pF.
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Maxim Integrated │ 30
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
DEVICE MODE AND
CONFIGURATION
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
DIGITAL AUDIO INPUT TO PLAYBACK PATH TO HEADPHONE OUTPUT (MUSIC FILTERS)
Stereo DAC Playback to Headphone Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω
1.39
1.28
1.04
0.02
0.00
6.05
102
Stereo DAC Playback to Headphone Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω, low power mode
0.94
0.51
1.02
0.02
0.00
3.84
99
Stereo DAC Playback to Headphone Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω, dynamic range control
enabled
1.39
1.28
1.11
0.02
0.00
6.14
102
Stereo DAC Playback to Headphone Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω, parametric equalizer enabled
1.39
1.28
1.65
0.02
0.00
6.78
102
Stereo DAC Playback to Headphone Output
fMCLK = 12.288MHz, fS = 96kHz, 20-bit, music
filters, RLOAD = 32Ω
1.39
1.28
1.17
0.02
0.00
6.21
102
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 44.1kHz, 20-bit, music filters,
RLOAD = 32Ω
1.40
1.29
1.00
0.02
0.00
6.03
102
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 44.1kHz, 20-bit, music filters,
RLOAD = 32Ω, low power mode
0.96
0.51
1.00
0.02
0.00
3.85
99
www.maximintegrated.com
Maxim Integrated │ 31
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
DEVICE MODE AND
CONFIGURATION
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
DIGITAL AUDIO INPUT TO PLAYBACK PATH TO HEADPHONE OUTPUT (VOICE FILTERS)
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω
1.35
1.28
0.89
0.02
0.00
5.81
101
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
0.91
0.51
0.89
0.02
0.00
3.62
98.5
Mono DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω
0.78
0.69
0.82
0.02
0.00
3.64
101
Mono DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
0.56
0.30
0.82
0.02
0.00
2.55
98.5
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters,
RLOAD = 32Ω
1.35
1.28
0.94
0.02
0.00
5.87
99
Stereo DAC Playback to Headphone Output
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
0.91
0.50
0.94
0.02
0.00
3.68
97
DIGITAL AUDIO INPUT TO PLAYBACK PATH TO SPEAKER OUTPUT
Stereo DAC Playback to Speaker Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 8Ω, LLOAD = 68µH
1.10
0.00
1.04
0.02
2.18
11.47
91
Stereo DAC Playback to Speaker Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 8Ω, LLOAD = 68µH, low power
mode
0.91
0.00
1.03
0.02
2.18
10.93
91
Mono DAC Playback to Speaker Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 8Ω, LLOAD = 68µH
0.65
0.00
0.90
0.02
1.11
6.36
91
Mono DAC Playback to Speaker Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 8Ω, LLOAD = 68µH, low power
mode
0.51
0.00
0.90
0.02
1.11
6.09
91
Stereo DAC Playback to Speaker Output
fMCLK = 12.288MHz, fS = 96kHz, 20-bit, music
filters, RLOAD = 8Ω, LLOAD = 68µH
1.21
0.00
1.17
0.02
2.18
11.61
91
Stereo DAC Playback to Speaker Output
fMCLK = 13MHz, fS = 44.1kHz, 20-bit, music filters,
RLOAD = 8Ω, LLOAD = 68µH
1.21
0.00
1.06
0.02
2.18
11.50
91
www.maximintegrated.com
Maxim Integrated │ 32
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
DEVICE MODE AND
CONFIGURATION
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
ANALOG AUDIO LINE INPUT TO DIGITAL RECORD PATH OUTPUT
Stereo Differential Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
3.09
0.00
1.38
0.02
0.00
7.19
98
Stereo Differential Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
1.97
0.00
1.39
0.02
0.00
5.21
98
Stereo Differential Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, Digital Biquad Filter Enabled
3.10
0.00
1.46
0.02
0.00
7.30
98
Mono Differential Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
1.86
0.00
1.10
0.02
0.00
4.65
98
Stereo Single-Ended Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
3.19
0.00
1.35
0.02
0.00
7.33
97
Stereo Single-Ended Line Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
2.02
0.00
1.35
0.02
0.00
5.24
97
Stereo Single-Ended Line Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
2.90
0.00
0.90
0.02
0.00
6.28
98
Stereo Single-Ended Line Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
low power mode
1.73
0.00
0.90
0.02
0.00
4.20
97
www.maximintegrated.com
Maxim Integrated │ 33
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
DEVICE MODE AND
CONFIGURATION
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
ANALOG MICROPHONE INPUT TO DIGITAL RECORD PATH OUTPUT (MUSIC FILTERS)
Stereo Analog Microphone Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
3.50
0.00
1.36
0.02
0.00
7.88
97
Stereo Analog Microphone Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
2.22
0.00
1.38
0.02
0.00
5.65
97
Mono Analog Microphone Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
2.02
0.00
1.05
0.02
0.00
4.90
97
Mono Analog Microphone Input to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
1.35
0.00
1.08
0.02
0.00
3.74
97
ANALOG MICROPHONE INPUT TO DIGITAL RECORD PATH OUTPUT (VOICE FILTERS)
Stereo Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
3.20
0.00
0.91
0.02
0.00
6.81
99
Stereo Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
low power mode
1.93
0.00
0.92
0.02
0.00
4.57
98
Mono Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
1.87
0.00
0.82
0.02
0.00
4.35
99
Mono Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters
low power mode
1.20
0.00
0.83
0.02
0.00
3.18
98
Stereo Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters
3.26
0.00
1.11
0.02
0.00
7.16
98
Stereo Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters
low power mode
1.98
0.00
1.12
0.02
0.00
4.91
97
Mono Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters
1.90
0.00
0.94
0.02
0.00
4.54
98
Mono Analog Microphone Input to Record Path
fMCLK = 13MHz, fS = 16kHz, 16-bit, voice filters
low power mode
1.23
0.00
0.94
0.02
0.00
3.35
97
www.maximintegrated.com
Maxim Integrated │ 34
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
DEVICE MODE AND
CONFIGURATION
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
ANALOG AUDIO INPUT DIRECT TO DIGITAL RECORD PATH OUTPUT
Stereo Differential Input Direct to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
2.85
0.00
1.39
0.02
0.00
6.76
99
Stereo Differential Input Direct to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
1.84
0.00
1.39
0.02
0.00
4.98
98
Mono Differential Input Direct to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters
1.61
0.00
1.08
0.02
0.00
4.20
99
Mono Differential Input Direct to Record Path
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, low power mode
1.09
0.00
1.09
0.02
0.00
3.29
98
ANALOG AUDIO INPUT TO ANALOG AUDIO OUTPUT
Stereo Single-Ended Line Input to Headphones
(RLOAD = 32Ω)
1.12
2.42
0.00
0.00
0.00
6.34
99
Mono Single-Ended Line Input to Headphones
(RLOAD = 32Ω)
0.72
1.57
0.00
0.00
0.00
3.41
99
Stereo Differential Line Input to Headphones
(RLOAD = 32Ω)
1.07
1.26
0.00
0.00
0.00
4.19
100
Stereo Differential Line Input to Speaker Output
(RLOAD = 8Ω, LLOAD = 68µH)
0.36
0.00
0.00
0.00
2.08
8.34
91
Mono Differential Line Input to Speaker Output
(RLOAD = 8Ω, LLOAD = 68µH)
0.31
0.00
0.00
0.00
1.04
4.42
91
Stereo Single-Ended Line Input to Line Output
(RLOAD = 10kΩ)
0.76
0.00
0.00
0.00
0.74
4.12
99
www.maximintegrated.com
Maxim Integrated │ 35
MAX98090
Ultra-Low Power Stereo Audio Codec
Quiescent Power Consumption (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V, slave mode operation.)
IAVDD
(mA)
IHPVDD
(mA)
IDVDD
(mA)
IDVDDIO
(mA)
ISPK_VDD
(mA)
POWER
(mW)
DYNAMIC
RANGE
(dB)
Mono Full Duplex: Analog Microphone Input
to Record Path and DAC Playback to Receiver
Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω
2.67
0.00
0.95
0.02
0.73
8.61
REC: 99
PB: 100
Mono Full Duplex: Analog Microphone Input
to Record Path and DAC Playback to Receiver
Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
1.94
0.00
0.95
0.02
0.73
7.31
REC: 99
PB: 98
Mono Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphone
Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω
2.69
0.69
1.22
0.02
0.00
7.51
REC: 97
PB: 102
Mono Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphone
Output
fMCLK = 12.288MHz, fS = 48kHz, 20-bit, music
filters, RLOAD = 32Ω, low power mode
1.80
0.30
1.24
0.02
0.00
5.26
REC: 97
PB: 99
Mono Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphone
Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω
2.54
0.69
0.95
0.02
0.00
6.93
REC: 99
PB: 102
Mono Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphone
Output
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
1.66
0.30
0.96
0.02
0.00
4.67
REC: 99
PB: 99
Stereo Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphones
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω
4.44
1.28
1.14
0.02
0.00
11.54
REC: 99
PB: 102
Stereo Full Duplex: Analog Microphone Input to
Record Path and DAC Playback to Headphones
fMCLK = 13MHz, fS = 8kHz, 16-bit, voice filters,
RLOAD = 32Ω, low power mode
2.73
0.51
1.15
0.02
0.00
7.18
REC: 99
PB: 99
DEVICE MODE AND
CONFIGURATION
FULL-DUPLEX AUDIO OPERATION
www.maximintegrated.com
Maxim Integrated │ 36
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
ANALOG MICROPHONE INPUT TO ADC RECORD PATH OUTPUT
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
-50
-60
-70
MAX98090 toc02
-40
-50
-60
-30
-40
-50
-60
-70
-70
-90
-80
-90
-100
-90
-100
1k
10k
-40
1k
10k
100k
10
1k
10k
100k
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
-50
-60
-70
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 70.7mVRMS
AV_MIC = +20dB
CIN = 10µF
-20
-30
-40
0
-50
-60
-70
-20
-30
-40
-50
-60
-70
-90
-90
-90
-100
-100
-100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 22.4mVRMS
AV_MIC = +30dB
CIN = 10µF
-10
-80
100
MAX98090 toc06
0
-10
-80
10
100
FREQUENCY (Hz)
THD+N RATIO (dB)
-30
100
FREQUENCY (Hz)
THD+N RATIO (dB)
-20
10
FREQUENCY (Hz)
fMCLK = 12.288MHz
fLRCLK = 96kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-10
-80
MAX98090 toc05
0
100
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-20
-80
10
THD+N RATIO (dB)
-30
0
-10
THD+N RATIO (dB)
-40
-20
MAX98090 toc04
THD+N RATIO (dB)
-30
fMCLK = 13MHz
fLRCLK = 44.1kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-10
THD+N RATIO (dB)
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
-20
0
MAX98090 toc01
0
-10
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
MAX98090 toc03
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
-80
10
100
1k
FREQUENCY (Hz)
10k
10
100
1k
10k
FREQUENCY (Hz)
Maxim Integrated │ 37
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
ANALOG MICROPHONE INPUT TO ADC RECORD PATH OUTPUT (CONTINUED)
COMMON-MODE REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
70
60
60
50
30
-3
20
-4
10
-5
0
100
1k
10k
80
60
BIAS_MODE = 0
40
VSPK_VDD = 3.7V
VMICBIAS = 2.8V
10
100
1k
10k
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
20
100
fMCLK = 13MHz
fLRCLK = 8kHz
AV_MIC = 0dB
CIN = 10µF
0
100
0
10
-20
-40
FREQUENCY (Hz)
www.maximintegrated.com
10,000
100,000
0
100k
MAX98090 toc09
10
100
1k
10k
100k
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
-60
-80
-100
-120
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_MIC = 0dB
CIN = 10µF
0
-20
-40
-60
-80
-100
-120
-140
-140
1,000
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
CIN = 10µF
10
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPK_VDD to MICBIAS)
MAX98090 toc10
40
20
FREQUENCY (Hz)
BIAS_MODE = 1
50
30
fMCLK = 12.288MHz
fLRCLK = 48kHz
CIN = 10µF
FREQUENCY (Hz)
120
20
AV_MIC = +0dB
40
-2
10
POWER-SUPPLY REJECTION RATIO (dB)
70
MAX98090 toc12
-1
90
80
PSRR (dB)
0
100
OUTPUT AMPLITUDE (dBFS)
1
AV_MIC = +30dB
MAX98089 toc11
2
AV_MIC = +20dB
80
OUTPUT AMPLITUDE (dBFS)
NORMALIZED GAIN (dB)
3
90
CMRR (dB)
fMCLK = 13MHz
fLRCLK = 8kHz
VIN = 707mVRMS
AV_MIC = 0dB
CIN = 10µF
4
100
MAX98090 toc07
5
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MIC TO ADC)
MAX98090 toc08
GAIN vs. FREQUENCY (MIC TO ADC)
-160
-160
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Maxim Integrated │ 38
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
ANALOG MICROPHONE INPUT TO ADC RECORD PATH OUTPUT (CONTINUED)
-80
-100
-120
-140
-60
-80
-100
-120
-140
-160
5
10
15
20
-40
-80
-100
-120
-160
0
5
10
15
20
0
5
10
15
FREQUENCY (kHz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
-40
-60
-80
-100
-120
0
-20
-40
-60
-80
-100
-120
-140
-140
-160
-160
5
10
FREQUENCY (kHz)
www.maximintegrated.com
15
20
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_MIC = 0dB
CIN = 10µF
20
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_MIC = 0dB
CIN = 10µF
0
OUTPUT AMPLITUDE (dBFS)
-20
20
OUTPUT AMPLITUDE (dBFS)
0
MAX98090 toc16
FREQUENCY (kHz)
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_MIC = 0dB
CIN = 10µF
MAX98090 toc15
-60
FREQUENCY (kHz)
20
0
-20
-140
-160
0
OUTPUT AMPLITUDE (dBFS)
-40
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_MIC = 0dB
CIN = 10µF
0
-20
-40
20
MAX98090 toc18
-60
-20
20
OUTPUT AMPLITUDE (dBFS)
-40
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_MIC = 0dB
CIN = 10µF
0
MAX98090 toc17
OUTPUT AMPLITUDE (dBFS)
-20
20
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
MAX98090 toc14
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_MIC = 0dB
CIN = 10µF
0
OUTPUT AMPLITUDE (dBFS)
20
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (MIC TO ADC)
MAX98090 toc13
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (MIC TO ADC)
-60
-80
-100
-120
-140
-160
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 39
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DIGITAL MICROPHONE INPUT TO RECORD PATH OUTPUT
INBAND OUTPUT SPECTRUM,
-10dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
VIN = -3dBFS
-70
VIN = -26dBFS
-80
-80
-100
-120
-90
-140
-100
-160
100
1k
10k
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(DIGITAL MIC TO RECORD PATH)
0
-20
0
-40
-60
-80
-100
-120
fMCLK = 13MHz
fLRCLK = 16kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
-10
-20
THD+N RATIO (dB)
fMCLK = 13MHz
fLRCLK = 8kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
-80
-100
-120
-30
-50
-60
VIN = -3dBFS
VIN = -26dBFS
20
-20
-40
-60
-80
-100
-120
-140
-90
-140
-100
-160
FREQUENCY (Hz)
www.maximintegrated.com
10
100
1k
FREQUENCY (Hz)
10k
fMCLK = 13MHz
fLRCLK = 16kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
0
-160
500 1000 1500 2000 2500 3000 3500 4000
500 1000 1500 2000 2500 3000 3500 4000
INBAND OUTPUT SPECTRUM,
-10dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
-40
-70
0
FREQUENCY (Hz)
-80
0
MAX98090 toc21
-60
-160
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
20
-40
-140
0
MAX98090 toc22
10
OUTPUT AMPLITUDE (dBFS)
-60
-20
MAX98090 toc24
-60
-40
fMCLK = 13MHz
fLRCLK = 8kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
0
OUTPUT AMPLITUDE (dBFS)
-50
-20
20
OUTPUT AMPLITUDE (dBFS)
-40
fMCLK = 13MHz
fLRCLK = 8kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
0
MAX98090 toc23
-30
20
OUTPUT AMPLITUDE (dBFS)
fMCLK = 13MHz
fLRCLK = 8kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
-20
THD+N RATIO (dB)
MAX98090 toc19
0
-10
INBAND OUTPUT SPECTRUM,
-26dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
MAX98090 toc20
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(DIGITAL MIC TO RECORD PATH)
0
1k
2k
3k
4k
5k
6k
7k
8k
FREQUENCY (Hz)
Maxim Integrated │ 40
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DIGITAL MICROPHONE INPUT TO RECORD PATH OUTPUT (CONTINUED)
-100
-120
-80
-100
-120
-140
-160
-160
1k
2k
3k
4k
5k
6k
7k
8k
0
1k
2k
3k
4k
5k
6k
7k
INBAND OUTPUT SPECTRUM,
-10dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
INBAND OUTPUT SPECTRUM,
-26dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
-20
-40
-60
-80
-100
-120
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
fDMC = 3.072MHz
AV_DMIC = 0dB
0
OUTPUT AMPLITUDE (dBFS)
fMCLK = 12.288MHz
fLRCLK = 48kHz
fDMC = 3.072MHz
AV_DMIC = 0dB
-60
-20
-40
10
8k
-60
-80
-100
-120
-20
-40
-80
-100
-120
-140
www.maximintegrated.com
20k
0
5k
10k
FREQUENCY (Hz)
15k
100k
-60
-160
15k
20k
fMCLK = 12.288MHz
fLRCLK = 48kHz
fDMC = 3.072MHz
AV_DMIC = 0dB
0
-160
10k
10k
20
-160
FREQUENCY (Hz)
1k
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
-140
5k
100
FREQUENCY (Hz)
-140
0
VIN = -26dBFS
VIN = -3dBFS
-80
-120
FREQUENCY (Hz)
0
-40
-100
FREQUENCY (Hz)
20
MAX98090 toc26
-60
-140
0
OUTPUT AMPLITUDE (dBFS)
-40
MAX98090 toc30
-80
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
fDMC = 3.072MHz
AV_DMIC = 0dB
-20
THD+N RATIO (dB)
-60
0
0
OUTPUT AMPLITUDE (dBFS)
-40
fMCLK = 13MHz
fLRCLK = 16kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
MAX98090 toc29
-20
MAX98090 toc28
OUTPUT AMPLITUDE (dBFS)
0
20
OUTPUT AMPLITUDE (dBFS)
fMCLK = 13MHz
fLRCLK = 16kHz
fDMC = 3.25MHz
AV_DMIC = 0dB
MAX98090 toc25
20
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(DIGITAL MIC TO RECORD PATH)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
MAX98090 toc27
INBAND OUTPUT SPECTRUM,
-26dBFS INPUT
(DIGITAL MIC TO RECORD PATH)
0
5k
10k
15k
20k
FREQUENCY (Hz)
Maxim Integrated │ 41
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO ADC RECORD PATH OUTPUT
-50
-60
-70
DIFFERENTIAL
-80
SINGLE-ENDED
-40
MAX98090 toc32
-50
-60
-70
DIFFERENTIAL
-80
0
-20
SINGLE-ENDED
-30
-40
-50
-60
-80
-90
-100
-100
-100
1k
10k
100k
10
100
1k
10k
SINGLE-ENDED
DIFFERENTIAL
-70
-90
100
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_LINEPGA = +20dB
VIN_SE = 35.4mVRMS
VIN_DIFF = 70.7mVRMS
CIN = 10µF
-10
-90
10
100k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO ADC)
CROSSTALK vs. FREQUENCY
(LINE TO ADC)
-40
70
SINGLE-ENDED
-50
DIFFERENTIAL
-60
60
50
40
-70
30
-80
20
-90
10
-100
0
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
BIAS_MODE = 1
BIAS_MODE = 0
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 0.5mVRMS
AV_LINEPRE = 0dB
CIN = 10µF
-20
-40
-60
SINGLE-ENDED
-80
-100
-120
-140
10
100
1k
FREQUENCY (Hz)
100k
MAX98090 toc36
80
0
CROSSTALK (dB)
-30
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN SINGLE-ENDED
VRIPPLE = 100mVP-P
CIN = 10µF
90
MAX98090 toc35
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_LINEPGA = -9dB
VIN_SE = 2VRMS
CIN = 10µF
-20
100
MAX98090 toc34
0
-10
THD+N RATIO (dB)
-30
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
THD+N RATIO (dB)
-40
-20
PSRR (dB)
THD+N RATIO (dB)
-30
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_LINEPGA = 0dB
VIN_SE = 354mVRMS
VIN_DIFF = 707mVRMS
CIN = 10µF
-10
THD+N RATIO (dB)
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_LINEPGA = -6dB
VIN_SE = 0.5VRMS
VIN_DIFF = 1VRMS
CIN = 10µF
-20
0
MAX98090 toc31
0
-10
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
MAX98090 toc33
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
10k
100k
DIFFERENTIAL
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 42
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO ADC RECORD PATH OUTPUT (CONTINUED)
INBAND OUTPUT SPECTRUM
vs. FREQUENCY,-3dBFS INPUT
(LINE TO ADC)
OUTPUT AMPLITUDE (dBFS)
0
-20
-40
-60
-80
-100
-120
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 0.5mVRMS_SE
AV_PRE = 0dB
CIN = 10µF
0
-140
-20
-40
MAX98090 toc38
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 354mVRMS_SE
AV_PRE = 0dB
CIN = 10µF
OUTPUT AMPLITUDE (dBFS)
20
MAX98090 toc37
INBAND OUTPUT SPECTRUM
vs. FREQUENCY, -60dBFS INPUT
(LINE TO ADC)
-60
-80
-100
-120
-140
-160
0
5
10
15
-160
20
0
5
FREQUENCY (kHz)
10
15
20
FREQUENCY (kHz)
DIRECT ANALOG INPUT TO ADC RECORD PATH OUTPUT
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY
(INPUT DIRECT TO ADC MIXER)
80
-50
-60
60
50
40
-70
30
-80
20
-90
10
-100
0
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 0.5VRMS
CIN = 10µF
-20
CROSSTALK (dB)
70
-40
PSRR (dB)
THD+N RATIO (dB)
-30
MCLK = 12.288MHz
LRCLK = 48kHz
VRIPPLE = 100mVP-P
CIN = 10µF
90
MAX98090 toc41
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 707mVRMS
CIN = 10µF
-20
100
MAX98090 toc39
0
-10
CROSSTALK vs. FREQUENCY
(INPUT DIRECT TO ADC MIXER)
MAX98090 toc40
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(INPUT DIRECT TO ADC MIXER)
-40
-60
-80
RIGHT TO LEFT
-100
-120
10
100
1k
FREQUENCY (Hz)
10k
100k
LEFT TO RIGHT
-140
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 43
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DIRECT ANALOG INPUT TO ADC RECORD PATH OUTPUT (CONTINUED)
0
AMPLITUDE (dBFS)
-20
-40
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 1mVRMS
CIN = 10µF
0
-20
AMPLITUDE (dBFS)
fMCLK = 12.288MHz
fLRCLK = 48kHz
VIN = 0.707VRMS
CIN = 10µF
MAX98090 toc42
20
-60
-80
-100
-40
MAX98090 toc43
INBAND OUTPUT SPECTRUM,
-60dBFS (INPUT DIRECT TO ADC MIXER)
INBAND OUTPUT SPECTRUM,
-3dBFS (INPUT DIRECT TO ADC MIXER)
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
10
15
0
20
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
ADC RECORD PATH TO DAC PLAYBACK INTERNAL LOOP THROUGH
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
THD+N RATIO (dB)
-30
-40
-50
-60
POUT = 10mW POUT = 20mW
-70
-20
-30
-40
-50
-60
-70
POUT = 10mW POUT = 20mW
-80
-80
-90
-90
-100
-100
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
0
-20
-40
MAX98090 toc46
MAX98090 toc45
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
-10
THD+N RATIO (dB)
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
-20
0
MAX98090 toc44
0
-10
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
OUTPUT AMPLITUDE (dBFS)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
-60
-80
-100
-120
-140
10
100
1k
FREQUENCY (Hz)
10k
100k
-160
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 44
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
ADC RECORD PATH TO DAC PLAYBACK INTERNAL LOOP THROUGH (CONTINUED)
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
-140
-140
-140
-160
-160
-160
0
5
10
15
20
0
5
FREQUENCY (kHz)
10
15
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
0
MAX98090 toc49
0
20
OUTPUT AMPLITUDE (dBFS)
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
MAX98090 toc48
OUTPUT AMPLITUDE (dBFS)
0
20
OUTPUT AMPLITUDE (dBFS)
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_TOTAL = 0dB
RHP = 32I
CIN = 10µF
MAX98090 toc47
20
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT
(LINE TO ADC TO DAC TO HEADPHONE)
0
20
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
DAC PLAYBACK PATH INPUT TO RECEIVER OUTPUT
-40
fIN = 3000Hz
-50
-60
-70
-80
0.02
0.04
0.06
0.08
OUTPUT POWER (W)
www.maximintegrated.com
-40
0.10
0.12
MAX98090 toc51
fIN = 3000Hz
-50
-60
-70
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32I
-20
-30
-40
POUT = 25mW
-50
-60
-70
-80
fIN = 1000Hz
-90
-100
0
-30
-80
fIN = 1000Hz
fIN = 100Hz
-90
-20
0
-10
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
BIAS_MODE = 1
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32I
-10
THD+N RATIO (dB)
BIAS_MODE = 0
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32I
-20
0
MAX98090 toc50
0
-10
TOTAL HARMONIC DISTORTION
vs. FREQUENCY (DAC TO RECEIVER)
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER (DAC TO RECEIVER)
MAX98090 toc52
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(DAC TO RECEIVER)
POUT = 50mW
-90
fIN = 100Hz
-100
-100
0
0.02
0.04
0.06
0.08
OUTPUT POWER (W)
0.10
0.12
10
100
1k
FREQUENCY (Hz)
10k
Maxim Integrated │ 45
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO RECEIVER OUTPUT (CONTINUED)
75
BIAS_MODE = 0
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = +8dB
RREC = 32I
SPEAKER SUPPLY VOLTAGE (V)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO RECEIVER)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO RECEIVER)
4.0
4.5
PSRR (dB)
70
60
OTHER SUPPLIES
50
40
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
RREC = 32I
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
10
5.5
5.0
80
0
MAX98090 toc55
MAX98090 toc54
-5
3.5
SPK_VDD
10
-2
100
1k
FREQUENCY (Hz)
3.0
90
20
-1
160
120
80
fMCLK = 13MHz
fLRCLK = 8kHz
BIAS_MODE = 1
THD+N ≤ 1%
AV_REC = +8dB
RREC = 32I
40
-4
100
30
0
RREC = 16I
100k
20
-20
0
-60
-80
-100
-120
100
120
140
-40
-60
-80
-100
-120
-140
15
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = 0dB
RHP = 32I
-20
-160
10
80
0
-140
FREQUENCY (kHz)
60
20
-160
5
40
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO RECEIVER)
-40
0
20
OUTPUT POWER (mW)
fMCLK = 13MHz
fLRCLK = 8kHz
AV_REC = 0dB
RREC = 32I
0
0
10k
OUTPUT AMPLITUDE (dBV)
2.5
1
MAX98090 toc57
0
2
-3
OUTPUT AMPLITUDE (dBV)
25
3
200
POWER CONSUMPTION (mW)
100
fMCLK = 13MHz
fLRCLK = 8kHz
VOICE FILTER
AV_REC = 0dB
RREC = 32I
4
NORMALIZED GAIN (dB)
BIAS_MODE = 1
50
5
MAX98090 toc53
125
MAX98090 toc56
RECEIVER OUTPUT POWER (mW)
150
POWER CONSUMPTION vs.
OUTPUT POWER (DAC TO RECEIVER)
GAIN vs. FREQUENCY (DAC TO RECEIVER)
MAX98090 toc58
OUTPUT POWER vs. SPEAKER
SUPPLY VOLTAGE (DAC TO RECEIVER)
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 46
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO RECEIVER OUTPUT
-40
-50
fIN = 6000Hz
-60
-70
-80
0
0.02
0.04
-40
-50
fIN = 6000Hz
-60
-70
0.08
0.10
0.12
0
OUTPUT POWER (W)
0.02
0.04
2
-70
POUT = 80mW
0.08
0.10
10
0.12
100
1k
10k
100k
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO RECEIVER)
MAX98090 toc62
120
100
SPK_VDD
80
1
0
-1
60
OTHER SUPPLIES
40
-2
-3
DIFFERENTIAL INPUT
VRIPPLE = 100mVP-P
RREC = 32I
CIN = 10µF
20
-4
-5
0
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
-60
-100
0.06
PSRR (dB)
NORMALIZED GAIN (dB)
3
POUT = 25mW
-50
OUTPUT POWER (W)
DIFFERENTIAL INPUT
AV_TOTAL = 0dB
RREC = 32I
CIN = 10µF
4
-40
-90
GAIN vs. FREQUENCY
(LINE TO RECEIVER)
5
-30
-80
fIN = 100Hz
-100
0.06
DIFFERENTIAL INPUT
BIAS_MODE = 0
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32I
CIN = 10µF
-20
fIN = 1000Hz
-90
fIN = 100Hz
-100
-30
-80
fIN = 1000Hz
-90
MAX98090 toc60
-20
0
-10
MAX98090 toc63
-30
DIFFERENTIAL INPUT
BIAS_MODE = 1
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32I
CIN = 10µF
THD+N RATIO (dB)
THD+N RATIO (dB)
-20
0
-10
THD+N RATIO (dB)
DIFFERENTIAL INPUT
BIAS_MODE = 0
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32I
CIN = 10µF
MAX98090 toc59
0
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO RECEIVER)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(LINE TO RECEIVER)
MAX98090 toc61
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(LINE TO RECEIVER)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 47
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO RECEIVER OUTPUT (CONTINUED)
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE TO RECEIVER)
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
20
MAX98090 toc65
DIFFERENTIAL INPUT
AV_LINEPGA = 0dB
AV_REC = +8dB
RREC = 32I
CIN = 10µF
0
DIFFERENTIAL INPUT
AV_LINEPGA = 0dB
AV_REC = +6dB
RREC = 32I
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
20
MAX98090 toc64
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE TO RECEIVER)
-20
-40
-60
-80
-100
-120
-140
-140
-160
-160
0
5
10
15
0
20
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
DAC PLAYBACK PATH INPUT TO LINE OUTPUT
OUTPUT AMPLITUDE (dBV)
-20
-40
-60
-80
-100
-120
20
-20
-40
-60
-80
-100
-120
-140
-140
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
15
20
fMCLK = 13MHz
fLRCLK = 8kHz
AV_LOUT = +3dB
RLOUT = 10kI
0
OUTPUT AMPLITUDE (dBV)
fMCLK = 13MHz
fLRCLK = 8kHz
AV_LOUT = +3dB
RLOUT = 10kI
0
MAX98090 toc66
20
MAX98090 toc67
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO LINE OUT)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO LINE OUT)
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 48
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO LINE OUTPUT
-40
-50
-60
fIN = 6000Hz
-70
fIN = 100Hz
-30
-40
-50
VOUT = 300mVRMS
-60
VOUT = 0.707mVRMS
-70
-20
-30
-40
-50
-70
-90
-90
-90
-100
-100
0
0.2
0.4
0.6
-80
10
1.0
0.8
100
1k
10k
10
100
-20
-40
-60
-80
-100
-120
20
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kI
CIN = 10µF
0
OUTPUT AMPLITUDE (dBV)
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kI
CIN = 10µF
0
MAX98090 toc71
20
1k
10k
100k
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE IN TO LINE OUT)
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE IN TO LINE OUT)
OUTPUT AMPLITUDE (dBV)
100k
DIFFERENTIAL LINE INPUT
FREQUENCY (Hz)
OUTPUT LEVEL (V)
-20
-40
-60
-80
-100
-120
-140
-140
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
SINGLE-ENDED LINE INPUT
-60
-80
fIN = 1000Hz
VIN = 2VRMS
AV_EXTERNAL = -9dB
AV_LOUT = +3dB
RLOUT = 10kI
CIN = 10µF
-10
-80
-100
MAX98090 toc70
0
MAX98090 toc69
-20
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE IN TO LINE OUT)
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kI
CIN = 10µF
-10
THD+N RATIO (dB)
AV_LINEPGA = 0dB
AV_LOUT = +3dB
RLOUT = 10kI
CIN = 10µF
-20
0
MAX98090 toc68
0
-10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE IN TO LINE OUT)
MAX98090 toc72
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT LEVEL (LINE IN TO LINE OUT)
15
20
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 49
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT
-40
-20
-50
-60
-70
-80
-50
-60
-70
-20
0.5
1.0
1.5
2.0
-30
-40
fIN = 6000Hz
-50
-60
-70
fIN = 1000Hz
-80
-90
fIN = 100Hz
-100
0
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
-10
fIN = 1000Hz
-90
fIN = 100Hz
-100
fIN = 100Hz
-100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
-30
-40
-10
-20
-50
-60
-70
fIN = 1000Hz
-80
-30
-40
-50
-60
-70
-80
-90
0
0.1
0.2
0.3
0.4
0.5
OUTPUT POWER (W)
www.maximintegrated.com
0.6
0.7
0.8
0
0.5
1.0
1.5
-20
-30
-40
-50
-60
-70
fIN = 1000Hz
-90
fIN = 100Hz
-100
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB fIN = 6000Hz
ZSPK = 4I + 33µH
WLP PACKAGE
-10
-80
fIN = 1000Hz
-90
fIN = 100Hz
-100
0
fIN = 100Hz
-100
2.0
2.5
OUTPUT POWER (W)
3.0
3.5
MAX98090 toc78
-20
fIN = 6000Hz
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB fIN = 6000Hz
ZSPK = 4I + 33µH
WLP PACKAGE
THD+N RATIO (dB)
-10
0
THD+N RATIO (dB)
VSPK_VDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
MAX98090 toc76
0
THD+N RATIO (dB)
-40
-80
fIN = 1000Hz
-90
-30
fIN = 6000Hz
THD+N RATIO (dB)
-30
fIN = 6000Hz
-10
0
MAX98090 toc77
THD+N RATIO (dB)
-20
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98090 toc74
-10
0
THD+N RATIO (dB)
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
MAX98090 toc73
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98090 toc75
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
0.5
1.0
1.5
2.0
2.5
OUTPUT POWER (W)
Maxim Integrated │ 50
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
-40
-50
-60
-70
fIN = 1000Hz
-80
-90
0
-30
-40
MAX98090 toc80
-50
fIN = 6000Hz
-60
fIN = 1000Hz
-70
-90
fIN = 100Hz
-100
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0
0.2
0.4
0.6
0.8
1.0
1.2
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98090 toc82
-20
-30
-40
VSPKVDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-10
-20
-50
-60
-30
-40
-50
-60
-70
fIN = 6000Hz
-80
fIN = 1000Hz
-90
fIN = 100Hz
0.00
1.50
2.00
MAX98090 toc84
0
TQFN PACKAGE
VSPKVDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
-20
-60
1.00
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
-10
-50
0.50
OUTPUT POWER (W)
MAX98090 toc83
0
THD+N RATIO (dB)
-10
-40
1.4
OUTPUT POWER (W)
VSPKVDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-30
-100
OUTPUT POWER (W)
0
-20
-80
fIN = 100Hz
-100
THD+N RATIO (dB)
-20
VSPKVDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-10
THD+N RATIO (dB)
-30
VSPK_VDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4I + 33µH
WLP PACKAGE
-10
MAX98090 toc81
0
THD+N RATIO (dB)
THD+N RATIO (dB)
-20
fIN = 6000Hz
THD+N RATIO (dB)
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4I + 33µH
WLP PACKAGE
-10
0
MAX98090 toc79
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
-30
-40
-50
-60
-70
fIN = 6000Hz
-70
fIN = 6000Hz
-70
fIN = 6000Hz
-80
fIN = 1000Hz
-80
fIN = 1000Hz
-80
fIN = 1000Hz
-90
fIN = 100Hz
-90
fIN = 100Hz
-90
fIN = 100Hz
-100
-100
0.0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
www.maximintegrated.com
1.0
1.2
1.4
-100
0.0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
1.0
1.2
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT POWER (W)
Maxim Integrated │ 51
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
MAX98090 toc85
VSPKVDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 33µH
TQFN PACKAGE
-20
-40
-20
-50
-60
-30
-40
-60
-40
-50
-60
fIN = 6000Hz
-70
fIN = 6000Hz
-80
fIN = 1000Hz
-80
fIN = 1000Hz
-80
fIN = 1000Hz
fIN = 100Hz
-90
fIN = 100Hz
-90
fIN = 100Hz
-100
-100
2.0
3.0
0.0
0.5
1.5
2.0
OUTPUT POWER (W)
0
MAX98090 toc88
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
-10
-20
-50
-60
-30
-40
POUT = 1.00W
-50
-60
-70
fIN = 6000Hz
-70
-80
fIN = 1000Hz
-80
-90
fIN = 100Hz
-90
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
www.maximintegrated.com
1.0
1.2
1.4
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
-10
-20
-30
-40
-50
POUT = 0.76W
-60
-70
-80
POUT = 0.25W
POUT = 0.20W
-90
-100
-100
0.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
2.5
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
TQFN PACKAGE
VSPKVDD = 3V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 33µH
1.0
OUTPUT POWER (W)
10
100
1k
FREQUENCY (Hz)
10k
100k
MAX98090 toc90
1.0
THD+N RATIO (dB)
0.0
THD+N RATIO (dB)
THD+N RATIO (dB)
-40
-30
-70
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
-30
-20
-50
OUTPUT POWER (W)
-20
-10
fIN = 6000Hz
-100
-10
VSPKVDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 33µH
TQFN PACKAGE
-70
-90
0
MAX98090 toc87
0
MAX98090 toc89
THD+N RATIO (dB)
-30
VSPKVDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 33µH
TQFN PACKAGE
-10
THD+N RATIO (dB)
-10
MAX98090 toc86
0
THD+N RATIO (dB)
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
-100
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 52
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
-50
POUT = 0.60W
-60
-70
-80
-40
POUT = 2.00W
-60
-70
100
1k
10k
10
100k
100
-90
-50
10k
100k
POUT = 0.40W
-100
10
-60
-20
-30
-40
POUT = 1.00W
-30
-40
-50
-70
-80
-80
-90
-90
-90
POUT = 0.25W
-100
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
10
100
1,000
FREQUENCY (Hz)
POUT = 0.76W
-60
-70
POUT = 0.30W
100k
VSPKVDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-20
-80
-100
10k
MAX98090 toc96
0
-10
-50
-60
1k
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
-70
10
100
FREQUENCY (Hz)
VSPKVDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-10
THD+N RATIO (dB)
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4I + 33µH
WLP PACKAGE
POUT = 1.20W
-40
-70
MAX98090 toc95
0
MAX98090 toc94
0
-30
-60
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
-20
POUT = 1.50W
FREQUENCY (Hz)
FREQUENCY (Hz)
-10
1k
-50
-30
-80
-100
10
-40
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4I + 33µH
WLP PACKAGE
-20
POUT = 0.50W
-90
-100
THD+N RATIO (dB)
MAX98090 toc92
-50
-80
POUT = 0.15W
-90
-30
THD+N RATIO (dB)
-40
-20
0
-10
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4I + 33µH
WLP PACKAGE
-10
THD+N RATIO (dB)
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
WLP PACKAGE
-20
0
MAX98090 toc91
0
-10
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
MAX98090 toc93
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
10,000
100,000
-100
POUT = 0.2W
10
100
1,000
10,000
100,000
FREQUENCY (Hz)
Maxim Integrated │ 53
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
MAX98090 toc97
VSPKVDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
-20
-30
-40
VSPKVDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 68µH
TQFN PACKAGE
-10
-20
-50
POUT = 0.6W
-60
MAX98090 toc98
0
THD+N RATIO (dB)
-10
-30
-40
-20
POUT = 1.8W
-30
-40
-50
-70
-70
-80
-80
-90
-90
-90
POUT = 0.5W
-100
100
1,000
10,000
100,000
10
100
FREQUENCY (Hz)
-30
-40
TQFN PACKAGE
-50
POUT = 1.0W
-60
-70
-80
-90
100,000
MAX98090 toc101
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
WLP PACKAGE
2000
1500
1000
THD+N = 1%
0
1,000
FREQUENCY (Hz)
www.maximintegrated.com
10,000
100,000
MAX98090 toc102
4500
THD+N = 10%
500
1,000
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
POUT = 0.3W
100
100
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 68µH
WLP PACKAGE
4000
3500
3000
THD+N = 10%
2500
2000
1500
1000
THD+N = 1%
500
-100
10
10
FREQUENCY (Hz)
2500
OUTPUT POWER PER CHANNEL (mW)
VSPKVDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 68µH
-20
10,000
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
MAX98090 toc100
-10
1,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
0
POUT = 0.4W
-100
OUTPUT POWER PER CHANNEL (mW)
10
POUT = 1.3W
-60
-80
POUT = 0.15W
VSPKVDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 68µH
TQFN PACKAGE
-10
-50
-60
MAX98090 toc99
0
-70
-100
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
THD+N RATIO (dB)
0
THD+N RATIO (dB)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO SPEAKER)
10,000
100,000
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
Maxim Integrated │ 54
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
MAX98090 toc103
1500
OUTPUT POWER PER CHANNEL (mW)
2000
1000
500
THD+N = 1%
MAX98090 toc104
4500
THD+N = 10%
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 4Ω + 68µH
TQFN PACKAGE
4000
3500
3000
5
3
2500
2000
1500
1000
THD+N = 1%
3.0
3.5
4.0
4.5
5.0
5.5
2.5
SUPPLY VOLTAGE (V)
50
VSPK_VDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
WLP PACKAGE
10
4.0
4.5
5.0
80
ZSPK = 8I + 68µH
70
ZSPK = 4I + 33µH
50
40
VSPK_VDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
WLP PACKAGE
20
10
www.maximintegrated.com
3.5
0.5
1.0
1.5
2.0
2.5
OUTPUT POWER PER CHANNEL (W)
1k
10k
100
90
80
ZSPK = 8I + 68µH
70
100k
50
40
VSPK_VDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
WLP PACKAGE
30
20
10
3.0
ZSPK = 4I + 33µH
60
0
0
100
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
0
0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT POWER PER CHANNEL (W)
10
FREQUENCY (Hz)
60
30
0
0
-5
5.5
MAX98090 toc107
ZSPK = 4I + 33µH
60
20
3.5
90
EFFICIENCY (%)
EFFICIENCY (%)
80
30
3.0
100
MAX98090 toc106
90
40
-2
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
100
ZSPK = 8I + 68µH
0
-1
SUPPLY VOLTAGE (V)
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
70
1
-4
0
EFFICIENCY (%)
2.5
2
-3
500
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = 0dB
ZSPK = 8I + 68µH
4
THD+N = 10%
MAX98090 toc108
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
ZSPK = 8Ω + 68µH
TQFN PACKAGE
GAIN vs. FREQUENCY
(DAC TO SPEAKER)
NORMALIZED GAIN (dB)
2500
OUTPUT POWER PER CHANNEL (mW)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
MAX98090 toc105
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
OUTPUT POWER PER CHANNEL (W)
Maxim Integrated │ 55
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
MAX98090 toc109
100
90
80
80
70
70
ZSPK = 8W + 68µH
ZSPK = 4W + 33µH
50
40
VSPKVDD = 5V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
TQFN PACKAGE
20
10
60
ZSPK = 8W + 68µH
EFFICIENCY (%)
90
80
60
ZSPK = 4W + 33µH
50
40
VSPKVDD = 4.2V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
TQFN PACKAGE
30
20
10
0
3.5
0.0
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
fMCLK = 12.288MHz
fLRCLK = 48kHz
ZSPK = 8I + 68µH
4.5
4.0
120
100
3.5
SPK_VDD
2.0
1.0
60
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
ZSPK = 8I + 68µH
0.5
0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
www.maximintegrated.com
5.0
5.5
0.0
10
100
0.3
0.5
0.8
1.0
1.3
1.5
1.8
2.0
CROSSTALK vs. FREQUENCY
(DAC TO SPEAKER)
OTHER SUPPLIES
20
0
VSPKVDD = 3.7V
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = +8dB
TQFN PACKAGE
OUTPUT POWER PER CHANNEL (W)
40
1.5
40
0
3.0
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = 0dB
ZSPK = 8I + 68µH
-20
CROSSTALK (dB)
PSRR (dB)
2.5
ZSPK = 4W + 33µH
10
80
3.0
ZSPK = 8W + 68µH
50
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO SPEAKER)
MAX98090 toc112
5.0
0.5
1.0
1.5
2.0
2.5
OUTPUT POWER PER CHANNEL (W)
60
20
MAX98090 toc113
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT POWER PER CHANNEL (W)
70
30
0
0.0
MAX98090 toc111
100
90
30
SUPPLY CURRENT (mA)
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
MAX98090 toc110
100
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
MAX98090 toc114
EFFICIENCY vs. OUTPUT
POWER (DAC TO SPEAKER)
-40
-60
LEFT TO RIGHT
-80
RIGHT TO LEFT
-100
-120
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 56
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKER)
-60
-80
-100
-120
-140
-160
0
5
10
15
-40
-60
-80
-100
-60
-80
-100
-120
-140
-160
0
5
10
15
0
20
5
0
-20
-40
-60
-80
-100
-120
-140
20
fMCLK = 12.88MHz
fLRCLK = 48kHz
AV_SPKPGA = -6dB
ZSPK = 4I + 33µH
0
OUTPUT AMPLITUDE (dBV)
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_SPKPGA = -6dB
ZSPK = 8I + 68µH
15
20
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKER)
MAX98090 toc118
20
10
FREQUENCY (kHz)
FREQUENCY (kHz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKER)
OUTPUT AMPLITUDE (dBV)
-40
-140
FREQUENCY (kHz)
-20
-40
-60
-80
-100
-120
-140
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
-20
-120
-160
20
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_SPKPGA = -6dB
ZSPK = 8I + 68µH
0
MAX98090 toc117
-20
20
MAX98090 toc119
-40
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = -6dB
ZSPK = 8I + 68µH
0
OUTPUT AMPLITUDE (dBV)
OUTPUT AMPLITUDE (dBV)
-20
20
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKER)
MAX98090 toc116
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_SPKPGA = -6dB
ZSPK = 8I + 68µH
0
OUTPUT AMPLITUDE (dBV)
20
MAX98090 toc115
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO SPEAKER)
15
20
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 57
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO SPEAKER OUTPUT (CONTINUED)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO SPEAKER)
-40
-60
-80
-100
fMCLK = 12.88MHz
fLRCLK = 48kHz
AV_SPKPGA = 0dB
ZSPK = 8W + 68µH
-20
-120
MAX98090 toc121
OUTPUT AMPLITUDE (dBV)
-20
0
AMPLITUDE (dBV)
fMCLK = 12.88MHz
fLRCLK = 48kHz
AV_SPKPGA = -6dB
ZSPK = 4I + 33µH
0
MAX98090 toc120
20
WIDEBAND FREQUENCY SPECTRUM
(DAC TO SPEAKER)
-40
-60
-80
-100
-140
-120
-160
0
5
10
15
1
0.1
20
10
100
FREQUENCY (MHz)
FREQUENCY (kHz)
LINE INPUT TO SPEAKER OUTPUT
f = 6000Hz
-40
-50
-60
-70
-80
MAX98090 toc123
-20
-30
-40
-50
POUT = 0.60W
-60
-70
f = 1000Hz
f = 100Hz
-90
-100
0
0.2
0.4
0.6
OUTPUT POWER (W)
www.maximintegrated.com
0.8
1.0
AV_LINEPGA = 0dB
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
CIN = 10µF
4
3
2
1
0
-1
-2
-3
-80
-90
5
NORMALIZED GAIN (dB)
THD+N RATIO (dB)
-30
AV_LINEPGA = 0dB
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
CIN = 10µF
-10
THD+N RATIO (dB)
AV_LINEPGA = 0dB
AV_SPKPGA = +8dB
ZSPK = 8I + 68µH
CIN = 10µF
-20
0
MAX98090 toc122
0
-10
GAIN vs. FREQUENCY
(LINE TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO SPEAKER)
MAX98090 toc124
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO SPEAKER)
-4
POUT = 0.15W
-5
-100
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 58
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO SPEAKER OUTPUT (CONTINUED)
OTHER SUPPLIES
80
PSRR (dB)
60
SPK_VDD
40
30
VRIPPLE = 100mVP-P
ZSPK = 8I + 68µH
CIN = 10µF
0
10
100
RIGHT TO LEFT
-80
10k
1k
-120
100k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM,
-3dBV INPUT (LINE TO SPEAKER)
INBAND OUTPUT SPECTRUM,
-60dBV INPUT (LINE TO SPEAKER)
AV_LINEPGA = -6dB
AV_SPKPGA = 0dB
ZSPK = 8I + 68µH
CIN = 10µF
-20
OUTPUT AMPLITUDE (dBV)
-60
LEFT TO RIGHT
0
-40
-60
-80
-100
0
AV_LINEPGA = -6dB
AV_SPKPGA = 0dB
ZSPK = 8I + 68µH
CIN = 10µF
-20
-40
100k
-60
-80
-100
-120
-120
-140
-140
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
-40
-100
MAX98090 toc127
10
OUTPUT AMPLITUDE (dBV)
20
AV_LINEPGA = 0dB
AV_SPKPGA = 0dB
ZSPK = 8I + 68µH
CIN = 10µF
-20
CROSSTALK (dB)
70
50
0
MAX98090 toc128
90
MAX98090 toc125
100
MAX98090 toc126
CROSSTALK vs. FREQUENCY
(LINE TO SPEAKER)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO SPEAKER)
15
20
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 59
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
f = 1000Hz
f = 100Hz
-60
-70
-80
-50
-90
-100
0.03
0.04
f = 1000Hz
-70
-90
0.02
f = 6000Hz
-60
-100
0.01
MAX98090 toc130
-40
-30
-40
f = 1000Hz
-50
-60
f = 100Hz
-70
f = 6000Hz
-80
-90
f = 100Hz
0
0.05
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 32I
-20
-80
f = 3000Hz
0
0.01
0.02
0.03
-100
0.04
0.05
0
0.01
0.02
0.03
0.04
0.05
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
-40
f = 1000Hz
-50
-60
f = 100Hz
-70
f = 6000Hz
-80
-30
-40
f = 1000Hz
-50
-60
f = 100Hz
f = 6000Hz
-70
-80
-20
-30
-40
-70
-80
-90
-90
-100
-100
0.02
0.03
OUTPUT POWER (W)
www.maximintegrated.com
0.04
0.05
f = 1000Hz
-60
-90
0.01
f = 6000Hz
-50
-100
0
MAX98090 toc134
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 16I
-10
THD+N RATIO (dB)
-30
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 16I
-10
0
MAX98090 toc133
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = +3dB
RHP = 32I
-20
0
MAX98090 toc132
0
-10
THD+N RATIO (dB)
-30
0
-10
THD+N RATIO (dB)
-40
-50
-20
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = +3dB
RHP = 32I
-10
THD+N RATIO (dB)
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = +3dB
RHP = 32I
-20
0
MAX98090 toc129
0
-10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98090 toc131
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
0.01 0.02
0.03 0.04
0.05 0.06
OUTPUT POWER (W)
0.07
f = 100Hz
0
0.01 0.02
0.03 0.04
0.05 0.06
0.07
OUTPUT POWER (W)
Maxim Integrated │ 60
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT (CONTINUED)
f = 6000Hz
-50
f = 1000Hz
-60
-70
-30
-50
POUT = 0.01W
-70
POUT = 0.02W
-80
-80
f = 100Hz
-100
0
0.01
0.02
0.03
0.04
-30
-40
-50
-60
-70
POUT = 0.01W
-70
-90
-100
100
1k
10k
POUT = 0.01W
10
POUT = 0.02W
-80
0
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = +3dB
RHP = 32I
-10
-20
-30
-40
-50
-60
-70
POUT = 0.01W
POUT = 0.02W
-80
-30
-60
www.maximintegrated.com
POUT = 0.01W
-70
POUT = 0.025W
-80
-90
100k
MAX98090 toc137
-50
-100
10k
100k
-40
-90
1k
10k
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 16I
-20
-100
FREQUENCY (Hz)
1k
0
-10
-90
100
100
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO HEADPHONE)
-100
10
POUT = 0.02W
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO HEADPHONE)
THD+N RATIO (dB)
-20
-60
FREQUENCY (Hz)
MAX98090 toc138
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
RHP = 32I
-50
-100
10
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO HEADPHONE)
0
-40
-80
OUTPUT POWER (W)
-10
-30
-90
0.05
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = +3dB
RHP = 32I
-20
THD+N RATIO (dB)
-90
THD+N RATIO (dB)
MAX98090 toc136
-40
-60
0
-10
THD+N RATIO (dB)
-40
-20
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX98090 toc139
THD+N RATIO (dB)
-30
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = +3dB
RHP = 32I
-10
THD+N RATIO (dB)
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 32I
-20
0
MAX98090 toc135
0
-10
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX98090 toc140
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 61
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT (CONTINUED)
-40
POUT = 0.025W
-50
-60
-70
-30
-40
-60
-70
-80
-90
-90
POUT = 0.01W
10
100
1k
10k
100k
POUT = 0.02W
-50
-80
-100
MAX98090 toc142
-20
10
100
1k
10k
MAX98090 toc144
0
-1
-2
-3
100k
120
-5
10
100
1k
FREQUENCY (Hz)
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = +3dB
100
-5
100
1k
FREQUENCY (Hz)
10k
10k
RHP = 16I
80
60
40
RHP = 32I
20
-4
www.maximintegrated.com
-2
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO HEADPHONE)
1
10
0
-1
FREQUENCY (Hz)
CURRENT CONSUMPTION (mA)
NORMALIZED GAIN (dB)
2
1
-4
-100
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32I
3
2
-3
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
4
3
POUT = 0.01W
FREQUENCY (Hz)
5
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32I
4
100k
MAX98090 toc145
-30
5
NORMALIZED GAIN (dB)
THD+N RATIO (dB)
-20
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 32I
-10
THD+N RATIO (dB)
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
RHP = 16I
-10
0
MAX98090 toc141
0
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
MAX98090 toc143
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
0.1
1
10
OUTPUT POWER PER CHANNEL (mW)
100
Maxim Integrated │ 62
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT (CONTINUED)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO HEADPHONE)
SPK_VDD
100
RHP = 16I
80
PSRR (dB)
80
60
40
20
20
RHP = 32I
OTHER SUPPLIES
60
40
fMCLK = 12.288MHz
fLRCLK = 48kHz
VRIPPLE = 100mVP-P
RHP = 32I
0
0
1
10
OUTPUT POWER PER CHANNEL (mW)
100
10
100
OTHER SUPPLIES
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
VRIPPLE = 100mVP-P
RHP = 32I
40
20
0
10
100
100k
-40
-60
LEFT TO RIGHT
-80
RIGHT TO LEFT
-100
-120
1k
FREQUENCY (Hz)
www.maximintegrated.com
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32I
-20
CROSSTALK (dB)
80
60
0
MAX98090 toc148
SPK_VDD
1k
10k
FREQUENCY (Hz)
CROSSTALK vs. FREQUENCY
(DAC TO HEADPHONE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
120
100
MAX98090 toc149
0.1
PSRR (dB)
MAX98090 toc147
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = +3dB
100
120
MAX98090 toc146
CURRENT CONSUMPTION (mA)
120
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 63
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT (CONTINUED)
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
5
10
15
20
MAX98090 toc152
-20
-40
-60
-80
-100
-120
-140
-160
0
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = 0dB
RHP = 32I
0
-140
-160
-160
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
-40
-60
-80
-100
-120
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32I
0
-20
-40
-60
-80
-100
-120
20
-20
-40
-60
-80
-100
-120
-140
-140
-140
-160
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
15
20
0
5
10
FREQUENCY (kHz)
15
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32I
0
OUTPUT AMPLITUDE (dBV)
-20
20
OUTPUT AMPLITUDE (dBV)
fMCLK = 13MHz
fLRCLK = 44.1kHz
AV_HP = 0dB
RHP = 32I
0
MAX98090 toc155
FREQUENCY (kHz)
MAX98090 toc153
FREQUENCY (kHz)
20
OUTPUT AMPLITUDE (dBV)
-20
20
OUTPUT AMPLITUDE (dBV)
-40
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32I
0
MAX98090 toc154
OUTPUT AMPLITUDE (dBV)
-20
20
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
MAX98090 toc151
fMCLK = 13MHz
fLRCLK = 8kHz
AV_HP = 0dB
RHP = 32I
0
OUTPUT AMPLITUDE (dBV)
20
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
MAX98090 toc150
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
0
5
10
15
20
FREQUENCY (Hz)
Maxim Integrated │ 64
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
DAC PLAYBACK PATH INPUT TO HEADPHONE OUTPUT (CONTINUED)
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
5
10
15
20
MAX98090 toc158
-20
-40
-60
-80
-100
-120
-140
-160
0
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = 0dB
RHP = 32I
0
-140
-160
-160
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-6dBFS INPUT (DAC TO HEADPHONE)
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
-40
-60
-80
-100
-120
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 16I
0
-20
-40
-60
-80
-100
-120
20
-20
-40
-60
-80
-100
-120
-140
-140
-140
-160
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
15
20
0
5
10
FREQUENCY (kHz)
15
20
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 16I
0
OUTPUT AMPLITUDE (dBV)
-20
20
OUTPUT AMPLITUDE (dBV)
fMCLK = 12.288MHz
fLRCLK = 48kHz
LOW POWER MODE
AV_HP = 0dB
RHP = 32I
0
MAX98090 toc161
FREQUENCY (kHz)
MAX98090 toc159
FREQUENCY (kHz)
20
OUTPUT AMPLITUDE (dBV)
-20
20
OUTPUT AMPLITUDE (dBV)
-40
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = 0dB
RHP = 32I
0
MAX98090 toc160
OUTPUT AMPLITUDE (dBV)
-20
20
INBAND OUTPUT SPECTRUM,
-6dBFS INPUT (DAC TO HEADPHONE)
MAX98090 toc157
fMCLK = 12.288MHz
fLRCLK = 96kHz
AV_HP = 0dB
RHP = 32I
0
OUTPUT AMPLITUDE (dBV)
20
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (DAC TO HEADPHONE)
MAX98090 toc156
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (DAC TO HEADPHONE)
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 65
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO HEADPHONE OUTPUT
-60
-70
-80
-90
-100
-110
-120
MAX98090 toc163
-40
-50
-60
-70
POUT = 10mW
3
0.02
0.03
0.04
10
0.05
100
1k
10k
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
CROSSTALK vs. FREQUENCY
(LINE TO HEADPHONE)
80
BIAS_MODE = 1
60
40
20
-60
LEFT TO RIGHT
RIGHT TO LEFT
10
100
1k
FREQUENCY (Hz)
www.maximintegrated.com
10k
100k
90
80
100k
60
50
40
RHP = 32I
CIN = 10µF
AV_HP = 0dB
AV_LINEPGA = 0dB
20
-120
0
10k
100
30
-100
BIAS_MODE = 0
1k
FREQUENCY (Hz)
70
-40
-80
100
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
fMCLK = 12.288MHz
fLRCLK = 48kHz
AV_HP = 0dB
RHP = 32I
-20
10
CMRR (dBV)
100
0
CROSSTALK (dB)
VRIPPLE = 100mVP-P
RHP = 32I
CIN = 10µF
-2
100k
MAX98090 toc166
OUTPUT POWER (W)
120
0
-1
-5
-100
0.01
1
-4
-90
fIN = 1000Hz
2
-3
POUT = 20mW
-80
0
PSRR (dB)
-30
AV_LINEPGA = 0dB
AV_HP = 0dB
RHP = 32I
CIN = 10µF
4
MAX98090 toc167
fIN = 6000Hz
fIN = 100Hz
5
NORMALIZED GAIN (dB)
-50
-20
MAX98090 toc165
THD+N RATIO (dB)
-30
-40
GAIN vs. FREQUENCY
(LINE TO HEADPHONE)
AV_LINEPGA = 0dB
AV_HP = +8dB
RHP = 32I
CIN = 10µF
-10
THD+N RATIO (dB)
AV_LINEPGA = 0dB
AV_HP = +3dB
RHP = 32I
CIN = 10µF
-20
0
MAX98090 toc162
0
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO HEADPHONE)
MAX98090 toc164
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(LINE TO HEADPHONE)
10
0
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated │ 66
MAX98090
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(VAVDD = VHPVDD = VDVDDIO = 1.8V, VDVDD = 1.2V, VSPKLVDD = VSPKRVDD = VSPKVDD = 3.7V. Receiver load (RRCV) connected
between RCVP/LOUTL and RCVN/LOUTR (LINMOD = 0). Line output loads (RLOUT) connected between from RCVP/LOUTL and
RCVN/LOUTR to GND (LINMOD = 1). Headphone loads (RHP) connected from HPL or HPR to GND. Speaker loads (ZSPK) connected between SPK_P and SPK_N. RRCV = J, RLOUT = J, RHP = J, ZSPK = J. CREF = 2.2µF, CBIAS = CMICBIAS = 1µF, CC1N-C1P
= CCPVDD = CCPVSS = 1µF. AV_MICPRE_ = AV_MICPGA_ = AV_LINEPGA_= 0dB, AV_ADCLVL = AV_ADCGAIN = 0dB, AV_DACLVL =
AV_DACGAIN = 0dB, AV_MIXGAIN = 0dB, AV_RCV = AV_LOUT = AV_HP = AV_SPK = 0dB. fMCLK = 12.288MHz, fLRCLK = 48kHz, MAS =
0, 20-bit source data. TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
LINE INPUT TO HEADPHONE OUTPUT (CONTINUED)
OUTPUT AMPLITUDE (dBV)
0
-20
-40
-60
-80
-100
-120
-140
AV_LINEPGA = 0dB
AV_HP = 0dB
RHP = 32I
CIN = 10µF
0
-20
-40
-60
-80
-100
-120
-140
-160
-160
0
5
10
FREQUENCY (kHz)
www.maximintegrated.com
20
MAX98090 toc169
AV_LINEPGA = 0dB
AV_HP = 0dB
RHP = 32I
CIN = 10µF
OUTPUT AMPLITUDE (dBV)
20
INBAND OUTPUT SPECTRUM,
-60dBFS INPUT (LINE TO HEADPHONE)
MAX98090 toc168
INBAND OUTPUT SPECTRUM,
-3dBFS INPUT (LINE TO HEADPHONE)
15
20
0
5
10
15
20
FREQUENCY (kHz)
Maxim Integrated │ 67
MAX98090
Ultra-Low Power Stereo Audio Codec
IN4
27
MICBIAS
DVDD
28
REF
DVDDIO
29
BIAS
DGND
30
AVDD
SDIN
TOP VIEW
AGND
Bump/Pin Configurations
26
25
24
23
22
21
SDOUT 31
20 IN3
LRCLK 32
19 IN1/DMD
BCLK 33
18 IN2/DMC
17 SPKLGND
IRQ 34
MCLK 35
16 SPKLP
MAX98090
SCL 36
15 SPKLN
14 SPKLVDD
SDA 37
HPVDD 38
13 SPKRVDD
+
C1P 39
12 SPKRP
11 SPKRN
8
9
10
SPKRGND
HPR
7
RCVN/LOUTR
6
JACKSNS
5
RCVP/LOUTL
4
HPL
CPVSS
3
HPSNS
2
CPVDD
1
HPGND
C1N 40
TQFN
(5mm x 5mm x 0.75mm)
www.maximintegrated.com
Maxim Integrated │ 68
MAX98090
Ultra-Low Power Stereo Audio Codec
Bump/Pin Configurations (continued)
TOP VIEW
(BUMP SIDE DOWN)
+
MAX98090
1
2
3
4
5
6
7
SPKRGND
SPKRN
SPKRP
SPKLP
SPKLN
RCVN/LOUTR
N.C.
SPKVDD
SPKVDD
JACKSNS
IN3
IN2/DMC
RCVP/LOUTL
N.C.
N.C.
IN5
N.C.
IN4
MICBIAS
HPR
HPSNS
SCL
IN6
N.C.
REF
AGND
HPL
SDA
N.C.
N.C.
SDIN
BIAS
AVDD
CPVDD
C1N
C1P
IRQB
LRCLK
DVDDIO
DVDD
HPGND
CPVSS
HPVDD
MCLK
BCLK
SDOUT
DGND
SPKLGND IN1/DMD
A
B
C
D
E
F
G
WLP
(3.15mm x 3.15mm, 0.4 pitch)
www.maximintegrated.com
Maxim Integrated │ 69
MAX98090
Ultra-Low Power Stereo Audio Codec
Bump/Pin Descriptions
PIN
BUMP
TQFN
WLP
1
G1
HPGND
Headphone Ground
2
G2
CPVSS
Inverting Charge-Pump Output. Bypass to HPGND with a 1µF ceramic capacitor.
3
F1
CPVDD
Noninverting Charge-Pump Output. Bypass to HPGND with a 1µF ceramic capacitor.
4
E1
HPL
5
D2
HPSNS
6
D1
HPR
7
B5
JACKSNS
8
C1
RCVP/LOUTL
Positive Earpiece Amplifier Output/Left Line Output
Negative Earpiece Amplifier Output/Right Line Output
MAX98090
FUNCTION
Left-Channel Headphone Output
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or
connect to ground.
Right-Channel Headphone Output
Jack detection Input. Connect to the microphone terminal of the headset jack to detect
jack activity.
9
B1
RCVN/LOUTR
10
A1
SPKRGND
11
A2
SPKRN
Negative Right-Channel Class D Speaker Output
12
A3
SPKRP
Positive Right-Channel Class D Speaker Output
13
—
SPKRVDD
Right Speaker Power Supply. Bypass to SPKRGND with a 1µF capacitor and a single
10µF bulk capacitor shared with SPKLVDD.
14
—
SPKLVDD
Left Speaker and Microphone Bias Power Supply. Bypass to SPKLGND with a 1µF
capacitor and a single 10µF bulk capacitor shared with SPKRVDD.
15
A5
SPKLN
Negative Left-Channel Class D Speaker Output
16
A4
SPKLP
Positive Left-Channel Class D Speaker Output
17
A6
SPKLGND
18
B7
IN2/DMC
Negative Differential Microphone 1 Input or single-ended Line Input 2. AC-couple with a
series 1µF capacitor. Can be retasked as a digital microphone clock output.
19
A7
IN1/DMD
Positive Differential Microphone 1 Input or single-ended Line Input 1. AC-couple with a
series 1µF capacitor. Can be retasked as a digital microphone data input.
20
B6
IN3
Positive Differential Microphone 2 Input or single-ended Line Input 3. AC-couple with a
series 1µF capacitor.
21
C6
IN4
Negative Differential Microphone 2 Input or single-ended Line input 4. AC-couple with a
series 1µF capacitor.
22
C7
MICBIAS
23
D6
REF
Converter Reference. Bypass to AGND with a 2.2µF capacitor.
24
E6
BIAS
Common-Mode Reference Voltage. Bypass to AGND with a 1µF capacitor.
25
D7
AGND
Analog Ground.
26
E7
AVDD
Analog Power Supply. Bypass to AGND with a 1µF capacitor.
27
F7
DVDD
Digital Power Supply. Bypass to DGND with a 1µF capacitor.
28
F6
DVDDIO
www.maximintegrated.com
Right Speaker Amplifier Ground
Left Speaker Amplifier Ground.
Low-Noise Microphone Bias Voltage Output. Bypass to SPKLGND with a 1µF capacitor.
The bias voltage is programmable. An external resistor in the 2.2kΩ to 1kΩ range should
be used to set the microphone current.
Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF capacitor.
Maxim Integrated │ 70
MAX98090
Ultra-Low Power Stereo Audio Codec
Bump/Pin Descriptions (continued)
PIN
BUMP
TQFN
WLP
29
G7
DGND
Digital Ground
30
E5
SDIN
Digital Audio Serial Data Playback Input. The input voltage is referenced to DVDDIO.
31
G6
SDOUT
Digital Audio Serial Data Record Output. The output voltage is referenced to DVDDIO.
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and
determines whether audio data is routed to the left or right channel. In TDM mode, LRCLK
is a frame sync pulse. LRCLK is an input when the device is in slave mode and an output
when in master mode. The input voltage is referenced to DVDDIO.
MAX98090
FUNCTION
32
F5
LRCLK
33
G5
BCLK
34
F4
IRQ
35
G4
MCLK
36
D3
SCL
I2C Serial Clock Input. Connect a pullup resistor to DVDD for full output swing.
37
E2
SDA
I2C Serial Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
38
G3
HPVDD
39
F3
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF ceramic capacitor
between C1N and C1P.
40
F2
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF ceramic capacitor
between C1N and C1P.
—
B3, B4
SPKVDD
Speaker and Microphone Bias Power Supply. Bypass each bump to SPK_GND with a
1µF capacitor with a single shared 10µF bulk capacitor.
—
C4
IN5
Auxiliary Positive Differential Microphone Input or Single-Ended Line Input. AC-couple
with a series 1µF capacitor.
—
D4
IN6
Auxiliary Negative Differential Microphone Input or Single-Ended Line Input. AC-couple
with a series 1µF capacitor.
—
B2, C2,
C3, C5,
D5, E3,
E4
N.C.
Not Connected Internally
www.maximintegrated.com
Digital Audio Bit Clock Input/Output. BCLK is an input when the device is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDIO.
Active-Low Hardware Interrupt Output. Connect a 10kΩ pullup resistor to VDD.
Master Clock Input. Acceptable input frequency range is either 256 x fS or from 10MHz to
60MHz.
Headphone Power Supply. Bypass to HPGND with a 10µF bulk capacitor with a parallel
0.1µF capacitor as close as possible to the device.
Maxim Integrated │ 71
MAX98090
Detailed Description
The MAX98090 is a fully integrated stereo audio codec
with FlexSound audio processing and integrated input
and output audio amplifiers.
The device features either six (WLP package) or four
(TQFN package) flexible analog inputs. Each pair can
be configured as a differential analog microphone input,
a stereo single ended or differential line input(s), or as a
reduced power, direct differential analog input to the ADC
mixer. One input pair, IN1/IN2, can also be retasked to
support two digital microphones. As a result, two microphones (either analog or digital) can be recorded from
simultaneously. The input analog signals can be amplified
by up to 50dB, and then are either recorded by the stereo
ADC or routed directly to the analog output mixers for
playback.
The ADC supports sample rates between 8kHz and
96kHz, features two performance modes, and provides
two oversampling rate options. The ADC to DAI digital
record path features both voice (IIR) and Music (FIR)
filtering, an optional DC-blocking highpass filter, a fully
configurable biquad filter, and a -12dB to +45dB range of
programmable digital gain and level control.
The digital audio interface (DAI) can simultaneously
transmit and receive separate and distinct stereo audio
signals. The DAI supports a wide range of PCM digital
audio formats including I2S, left justified (LJ), right justified (RJ), and four slot TDM.
As with the record path, the DAI to DAC playback path
supports sample rates from 8kHz to 96kHz, both voice
(IIR) and music (FIR) filtering (high stop band attenuation
at fS/2), optional DC blocking filters, and a -15dB to +18dB
range of programmable digital gain and level control. In
addition, the playback path also features a 7-band parametric biquad equalizer, dynamic range control (DRC),
and a summing digital sidetone from the record path DSP.
The device includes three analog output drivers. The
first is a Class AB differential receiver/earpiece amplifier.
Alternatively, the receiver amplifier can also be configured
as a stereo single-ended line output driver.
www.maximintegrated.com
Ultra-Low Power Stereo Audio Codec
The second is an integrated, filterless, Class D stereo
speaker amplifier. This amplifier provides efficient amplification for two speakers, and includes active emissions
limiting to minimize the radiated emissions (EMI) traditionally associated with Class D. The right channel features a
slave mode, in which the switching is synchronized to that
of the left channel to eliminate the beat tone that can occur
with asynchronous operation. In most systems with short
speaker traces, no Class D output filtering is required.
The third is a Class H, ground referenced stereo headphone amplifier featuring Maxim’s second generation
DirectDrive architecture. The Class H headphone amplifier
features an internal charge pump that generates both a
positive and negative supply for the headphone amplifier. This provides a ground referenced output signal that
eliminates the need for either DC-blocking capacitors or
a midrail bias for the headphone jack ground return. The
headphone dedicated ground sense current return reduces crosstalk and output noise. A tracking circuit monitors
the signal level and automatically selects the appropriate
switching frequency and supply voltage level. For low
signal levels, the charge pump switches at a reduced frequency and outputs ±VHPVDD/2 for improved efficiency.
When the signal amplitude increases, the charge-pump
switching frequency also increases, and continues to output ±VHPVDD/2. For high signal levels, the charge pump
outputs full-scale rails at ±VHPVDD to maximize output
power.
The device also includes several additional features such
as a programmable external microphone bias, configurable
jack detection and identification, extensive click-and-pop
reduction circuitry, power and performance management
settings, and a full range of quick configuration options.
Device I2C Register Map
Table 1 lists all of the registers, their addresses, and
power-on-reset (PoR) states. Registers 0x01, 0x02, and
0xFF are read only. Registers 0x01, 0x02, and 0xFF are
read only. Registers 0x06 to 0x0B (quick setup) are write
only (push button). All of the remaining registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
Maxim Integrated │ 72
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
—
—
—
—
—
—
—
0x00
CLD
SLD
ULK
—
—
JDET
DRCACT
DRCCLP
0x00
—
—
—
—
—
LSNS
JKSNS
—
0x00
ICLD
ISLD
IULK
—
—
IJDET
BIT 7
RESET/STATUS/INTERRUPT REGISTERS
0x00 SOFTWARE RESET W SWRESET
0x01
0x02
DEVICE STATUS CoR
JACK STATUS
R
0x03 INTERUPT MASKS R/W
IDRCACT IDRCCLP
0x04
QUICK SETUP REGISTERS
0x04
SYSTEM CLOCK
W
26M
19P2M
13M
12P288M
12M
11P2896M
—
256FS
0x00
0x05
SAMPLE RATE
W
—
—
SR_96K
SR_32K
SR_48K
SR_44K1
SR_16K
SR_8K
0x00
0x06
DAI INTERFACE
W
—
—
RJ_M
RJ_S
LJ_M
LJ_S
I2S_M
I2S_S
0x00
0x07
DAC PATH
W
DIG2_HP
DIG2_
EAR
DIG2_
SPK
DIG2_
LOUT
—
—
—
—
0x00
0x08
MIC/DIRECT TO
ADC
IN34_
MIC2
—
—
IN12_
DADC
IN34_
DADC
IN56_
DADC
—
0x00
0x09
LINE TO ADC
W IN12_MIC1
W IN12S_AB IN34S_AB IN56S_AB IN34D_A
IN65D_B
—
—
—
0x00
IN12_
M1HPL
IN12_
M1SPKL
IN12_
M1EAR
IN12_
M1LOUTL
IN34_
M2HPR
IN34_
M2SPKR
IN34_
M2EAR
IN34_
M2LOUTR
0x00
W
IN12S_
ABHP
IN34D_
ASPKL
IN34D_
AEAR
IN12S_
ABLOUT
IN34S_
ABHP
IN65D
_BSPKR
IN65D_
BEAR
IN34S_
ABLOUT
0x00
—
—
—
—
—
—
—
—
—
0x00
0x0A ANALOG MIC LOOP W
0x0B
ANALOG LINE
LOOP
RESERVED REGISTER
0x0C
RESERVED
ANALOG INPUT CONFIGURATION REGISTERS
0x0D
LINE INPUT
CONFIG.
R/W IN34DIFF IN65DIFF
0x0E LINE INPUT LEVEL R/W MIXG135
0x0F
INPUT MODE
IN1SEEN IN2SEEN IN3SEEN
MIXG246
R/W EXTBUFA EXTBUFB
IN4SEEN
LINAPGA[2:0]
—
—
IN5SEEN IN6SEEN
LINBPGA[2:0]
—
—
0x00
0x1B
EXT_MIC[1:0]
0x00
0x10 MIC1 INPUT LEVEL R/W
—
PA1EN[1:0]
PGAM1[4:0]
0x14
0x11 MIC2 INPUT LEVEL R/W
—
PA2EN[1:0]
PGAM2[4:0]
0x14
MICROPHONE CONFIGURATION REGISTERS
0x12 MIC BIAS VOLTAGE R/W
—
0x13
DIGITAL MIC
ENABLE
R/W
—
0x14
DIGITAL MIC
CONFIG.
R/W
—
—
MICCLK[2:0]
DMIC_COMP[3:0]
—
—
—
MBVSEL[1:0]
0x00
—
—
DIGMICR DIGMICL
0x00
—
—
DMIC_FREQ[1:0]
0x00
Note: Register bits in bold italics are for the WLP package only.
www.maximintegrated.com
Maxim Integrated │ 73
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
ADC PATH AND CONFIGURATION REGISTERS
0x15
LEFT ADC MIXER R/W
—
MIXADL[6:0]
0x00
0x16 RIGHT ADC MIXER R/W
—
MIXADR[6:0]
0x00
LEFT RECORD
LEVEL
R/W
—
AVLG[2:0]
AVL[3:0]
0x03
0x18
RIGHT RECORD
R/W
LEVEL
—
AVRG[2:0]
AVR[3:0]
0x03
0x19
RECORD BIQUAD
R/W
LEVEL
—
AVBQ[3:0]
0x00
0x17
0x1A RECORD SIDETONE R/W
—
—
DSTS[1:0]
—
—
DVST[4:0]
0x00
CLOCK CONFIGURATION REGISTERS
0x1B
SYSTEM CLOCK R/W
—
—
PSCLK[1:0]
FREQ[3:0]
—
—
—
—
0x00
—
—
—
USE_MI
0x00
0x1C
CLOCK MODE
R/W
0x1D
CLOCK RATIO
NI MSB
R/W
0x1E
CLOCK RATIO
NI LSB
R/W
NI[7:0]
0x00
0x1F
CLOCK RATIO
MI MSB
R/W
MI[15:8]
0x00
0x20
CLOCK RATIO
MI LSB
R/W
MI[7:0]
0x00
0x21
MASTER MODE
R/W
—
MAS
NI[14:8]
—
—
—
—
0x00
BSEL[2:0]
0x00
INTERFACE CONTROL REGISTERS
0x22
INTERFACE
FORMAT
R/W
—
—
RJ
WCI
BCI
0x23
TDM CONTROL
R/W
—
—
—
—
—
0x24
TDM FORMAT
R/W
SLOTL[1:0]
SLOTR[1:0]
DLY
WS[1:0]
—
FSW
0x00
TDM
SLOTDLY[3:0]
0x00
0x00
0x25
I/O
R/W
CONFIGURATION
—
—
LTEN
LBEN
DMONO
HIZOFF
SDOEN
SDIEN
0x00
0x26
FILTER
R/W
CONFIGURATION
MODE
AHPF
DHPF
DHF
—
—
—
—
0x80
0x27
DAI PLAYBACK
LEVEL
R/W
DVM
—
0x28
EQ PLAYBACK
LEVEL
R/W
—
—
www.maximintegrated.com
DVG[1:0]
—
EQCLP
DV[3:0]
0x00
DVEQ[3:0]
0x00
Maxim Integrated │ 74
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
HEADPHONE (HP) CONTROL REGISTERS
R/W
—
—
MIXHPL[5:0]
0x00
0x2A RIGHT HP MIXER R/W
0x29
LEFT HP MIXER
—
—
MIXHPR[5:0]
0x00
0x2B
—
—
MIXHP
RSEL
0x2C LEFT HP VOLUME R/W
HPLM
—
—
HPVOLL[4:0]
0x1A
0x2D RIGHT HP VOLUME R/W
HPRM
—
—
HPVOLR[4:0]
0x1A
HP CONTROL
R/W
MIXHP
LSEL
MIXHPRG[1:0]
MIXHPLG[1:0]
0x00
SPEAKER (SPK) CONFIGURATION REGISTERS
0x2E LEFT SPK MIXER R/W
—
—
MIXSPL[5:0]
0x00
0x2F RIGHT SPK MIXER R/W
—
SPK_
SLAVE
MIXSPR[5:0]
0x00
0x30
—
—
0x31 LEFT SPK VOLUME R/W
SPLM
—
SPVOLL[5:0]
0x2C
RIGHT SPK
VOLUME
SPRM
—
SPVOLR[5:0]
0x2C
0x32
SPK CONTROL
R/W
R/W
—
—
MIXSPRG[1:0]
MIXSPLG[1:0]
0x00
DYNAMIC RANGE CONTROL (DRC) CONFIGURATION REGISTERS
0x33
DRC TIMING
0x34
DRC
COMPRESSOR
R/W
DRCCMP[2:0]
DRCTHC[4:0]
0x00
0x35
DRC EXPANDER R/W
DRCEXP[2:0]
DRCTHE[4:0]
0x00
DRCG[4:0]
0x00
0x36
DRC GAIN
R/W DRCEN
R/W
DRCRLS[2:0]
—
—
—
DRCATK[2:0]
—
0x00
RECEIVER (RCV OR EARPIECE) AND LINE OUTPUT (LOUT) REGISTERS
0x37 RCV/LOUTL MIXER R/W
—
—
0x38
RCV/LOUTL
CONTROL
R/W
—
—
—
0x39
RCV/LOUTL
VOLUME
R/W
RCVLM
—
—
0x3A
LOUTR MIXER
R/W LINMOD
—
0x3B LOUTR CONTROL R/W
0x3C
—
MIXRCVL[5:0]
—
—
—
0x00
MIXRCVLG[1:0]
RCVLVOL[4:0]
0x15
MIXRCVR[5:0]
—
—
0x00
—
—
—
—
JDWK
—
—
—
—
—
—
—
MBEN
LINEAEN
LINEBEN
ADREN
ADLEN
0x00
HPREN
HPLEN
SPREN
SPLEN
RCVLEN
RCVREN
DAREN
DALEN
0x00
—
—
—
—
—
ZDEN
VS2EN
VSEN
0x00
LOUTR VOLUME R/W RCVRM
—
0x00
MIXRCVRG[1:0]
RCVRVOL[4:0]
0x00
0x15
JACK DETECT AND ENABLE REGISTERS
0x3D
JACK DETECT
R/W JDETEN
0x3E
INPUT ENABLE
R/W
0x3F OUTPUT ENABLE R/W
0x40
LEVEL CONTROL R/W
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JDEB[1:0]
0x00
Maxim Integrated │ 75
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
REGISTER CONTENTS
ADDR
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
0x41
DSP FILTER
ENABLE
R/W
—
—
—
—
RECBQEN
BIT 2
BIT 1
BIT 0
EQ3BAND EQ5BAND EQ7BAND
EN
EN
EN
POR
STATE
0x00
BIAS AND POWER MODE CONFIGURATION REGISTERS
0x42
BIAS CONTROL
R/W
—
—
—
—
—
—
—
BIAS_
MODE
0x00
0x43
DAC CONTROL
R/W
—
—
—
—
—
—
PERF
MODE
DACHP
0x00
0x44
ADC CONTROL
R/W
—
—
—
—
—
OSR128
ADC
DITHER
ADCHP
0x06
0x45
DEVICE
SHUTDOWN
R/W
SHDN
—
—
—
—
—
—
—
0x00
PLAYBACK PARAMETRIC EQUALIZER BAND 1: BIQUAD FILTER COEFFICIENT REGISTERS
0x46
R/W
EQUALIZER
BAND 1
R/W
COEFFICIENT B0 R/W
B0_1[23:16]
—
B0_1[15:8]
—
B0_1[7:0]
—
R/W
EQUALIZER
BAND 1
0x4A
R/W
0x4B COEFFICIENT B1 R/W
B1_1[23:16]
—
B1_1[15:8]
—
B1_1[7:0]
—
0x4C
R/W
EQUALIZER
BAND 1
R/W
COEFFICIENT
B2
0x4E
R/W
B2_1[23:16]
—
0x4D
B2_1[15:8]
—
B2_1[7:0]
—
0x4F EQUALIZER BAND R/W
0x50
1
R/W
COEFFICIENT
A1
0x51
R/W
A1_1[23:16]
—
A1_1[15:8]
—
A1_1[7:0]
—
0x52
A2_1[23:16]
—
A2_1[15:8]
—
A2_1[7:0]
—
0x47
0x48
0x49
0x53
0x54
R/W
EQUALIZER
BAND 1
R/W
COEFFICIENT A2 R/W
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Maxim Integrated │ 76
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
PLAYBACK PARAMETRIC EQUALIZER BAND 2: BIQUAD FILTER COEFFICIENT REGISTERS
0x55
R/W
EQUALIZER
BAND 2
R/W
COEFFICIENT B0 R/W
B0_2[23:16]
—
B0_2[15:8]
—
B0_2[7:0]
—
R/W
EQUALIZER
0x59
BAND 2
R/W
0x5A COEFFICIENT B1 R/W
B1_2[23:16]
—
B1_2[15:8]
—
B1_2[7:0]
—
0x5B
R/W
EQUALIZER
BAND 2
R/W
COEFFICIENT
B2
0x5D
R/W
B2_2[23:16]
—
0x5C
B2_2[15:8]
—
B2_2[7:0]
—
0x5E
A1_2[23:16]
—
A1_2[15:8]
—
0x60
R/W
EQUALIZER
BAND 2
R/W
COEFFICIENT A1 R/W
A1_2[7:0]
—
0x61
R/W
A2_2[23:16]
—
A2_2[15:8]
—
A2_2[7:0]
—
0x56
0x57
0x58
0x5F
0x62
0x63
EQUALIZER
BAND 2
R/W
COEFFICIENT A2 R/W
PLAYBACK PARAMETRIC EQUALIZER BAND 3: BIQUAD FILTER COEFFICIENT REGISTERS
0x64
R/W
EQUALIZER
BAND 3
R/W
COEFFICIENT B0 R/W
B0_3[23:16]
—
B0_3[15:8]
—
B0_3[7:0]
—
B1_3[23:16]
—
B1_3[15:8]
—
0x69
R/W
EQUALIZER
BAND 3
R/W
COEFFICIENT B1 R/W
B1_3[7:0]
—
0x6A
R/W
EQUALIZER
0x6B
BAND 3
R/W
COEFFICIENT
B2
0x6C
R/W
B2_3[23:16]
—
B2_3[15:8]
—
B2_3[7:0]
—
0x6D
EQUALIZER
BAND 3
R/W
COEFFICIENT A1 R/W
A1_3[23:16]
—
A1_3[15:8]
—
A1_3[7:0]
—
R/W
EQUALIZER
BAND 3
R/W
COEFFICIENT A2 R/W
A2_3[23:16]
—
A2_3[15:8]
—
A2_3[7:0]
—
0x65
0x66
0x67
0x68
0x6E
0x6F
0x70
0x71
0x72
R/W
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Maxim Integrated │ 77
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
PLAYBACK PARAMETRIC EQUALIZER BAND 4: BIQUAD FILTER COEFFICIENT REGISTERS
0x73
R/W
EQUALIZER
BAND 4
R/W
COEFFICIENT B0 R/W
B0_4[23:16]
—
B0_4[15:8]
—
B0_4[7:0]
—
R/W
EQUALIZER
BAND 4
R/W
COEFFICIENT B1 R/W
B1_4[23:16]
—
B1_4[15:8]
—
B1_4[7:0]
—
0x79
R/W
EQUALIZER
BAND 4
R/W
COEFFICIENT
B2
0x7B
R/W
B2_4[23:16]
—
0x7A
B2_4[15:8]
—
B2_4[7:0]
—
0x7C
EQUALIZER
0x7D
BAND 4
R/W
COEFFICIENT
A1
0x7E
R/W
A1_4[23:16]
—
A1_4[15:8]
—
A1_4[7:0]
—
0x7F
A2_4[23:16]
—
A2_4[15:8]
—
A2_4[7:0]
—
0x74
0x75
0x76
0x77
0x78
0x80
0x81
R/W
R/W
EQUALIZER
BAND 4
R/W
COEFFICIENT A2 R/W
PLAYBACK PARAMETRIC EQUALIZER BAND 5: BIQUAD FILTER COEFFICIENT REGISTERS
0x82
B0_5[23:16]
—
B0_5[15:8]
—
0x84
R/W
EQUALIZER
BAND 5
R/W
COEFFICIENT B0 R/W
B0_5[7:0]
—
0x85
R/W
—
B1_5[15:8]
—
0x87
EQUALIZER
BAND 5
R/W
COEFFICIENT B1 R/W
B1_5[23:16]
B1_5[7:0]
—
0x88
R/W
EQUALIZER
0x89
BAND 5
R/W
0x8A COEFFICIENT B2 R/W
B2_5[23:16]
—
B2_5[15:8]
—
B2_5[7:0]
—
0x8B
R/W
EQUALIZER
0x8C
BAND 5
R/W
0x8D COEFFICIENT A1 R/W
A1_5[23:16]
—
A1_5[15:8]
—
A1_5[7:0]
—
0x8E
A2_5[23:16]
—
A2_5[15:8]
—
A2_5[7:0]
—
0x83
0x86
0x8F
0x90
R/W
EQUALIZER
BAND 5
R/W
COEFFICIENT A2 R/W
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Maxim Integrated │ 78
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
R/W
REGISTER CONTENTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
PLAYBACK PARAMETRIC EQUALIZER BAND 6: BIQUAD FILTER COEFFICIENT REGISTERS
0x91
R/W
EQUALIZER
BAND 6
R/W
COEFFICIENT B0 R/W
B0_6[23:16]
—
B0_6[15:8]
—
B0_6[7:0]
—
R/W
EQUALIZER
BAND 6
R/W
COEFFICIENT B1 R/W
B1_6[23:16]
—
B1_6[15:8]
—
B1_6[7:0]
—
B2_6[23:16]
—
B2_6[15:8]
—
0x99
R/W
EQUALIZER
BAND 6
R/W
COEFFICIENT B2 R/W
B2_6[7:0]
—
0x9A
R/W
EQUALIZER
0x9B
BAND 6
R/W
COEFFICIENT
A1
0x9C
R/W
A1_6[23:16]
—
A1_6[15:8]
—
A1_6[7:0]
—
0x9D
A2_6[23:16]
—
A2_6[15:8]
—
A2_6[7:0]
—
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x9E
0x9F
R/W
EQUALIZER
BAND 6
R/W
COEFFICIENT A2 R/W
PLAYBACK PARAMETRIC EQUALIZER BAND 7: BIQUAD FILTER COEFFICIENT REGISTERS
0xA0
R/W
EQUALIZER
BAND 7
R/W
COEFFICIENT
B0
0xA2
R/W
B0_7[23:16]
—
0xA1
B0_7[15:8]
—
B0_7[7:0]
—
0xA3
EQUALIZER
0xA4
BAND 7
R/W
COEFFICIENT
B1
0xA5
R/W
B1_7[23:16]
—
B1_7[15:8]
—
B1_7[7:0]
—
0xA6
EQUALIZER
0xA7
BAND 7
R/W
0xA8 COEFFICIENT B2 R/W
B2_7[23:16]
—
B2_7[15:8]
—
B2_7[7:0]
—
0xA9
R/W
EQUALIZER
0xAA
BAND 7
R/W
0xAB COEFFICIENT A1 R/W
A1_7[23:16]
—
A1_7[15:8]
—
A1_7[7:0]
—
0xAC
A2_7[23:16]
—
0xAD
A2_7[15:8]
—
A2_7[7:0]
—
R/W
R/W
R/W
EQUALIZER
BAND 7
R/W
COEFFICIENT
A2
0xAE
R/W
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Maxim Integrated │ 79
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR
NAME
REGISTER CONTENTS
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
POR
STATE
RECORD BIQUAD FILTER COEFFICIENT REGISTERS
0xAF
R/W
RECORD BIQUAD
0xB0
R/W
COEFFICIENT B0
0xB1
R/W
REC_B0[23:16]
—
REC_B0[15:8]
—
REC_B0[7:0]
—
0xB2
R/W
RECORD BIQUAD
0xB3
R/W
COEFFICIENT B1
0xB4
R/W
REC_B1[23:16]
—
REC_B1[15:8]
—
REC_B1[7:0]
—
0xB5
R/W
RECORD BIQUAD
R/W
COEFFICIENT B2
0xB7
R/W
REC_B2[23:16]
—
0xB6
REC_B2[15:8]
—
REC_B2[7:0]
—
0xB8
R/W
RECORD BIQUAD
R/W
COEFFICIENT A1
0xBA
R/W
REC_A1[23:16]
—
0xB9
REC_A1[15:8]
—
REC_A1[7:0]
—
0xBB
REC_A2[23:16]
—
REC_A2[15:8]
—
REC_A2[7:0]
—
REVID[7:0]
0x43
R/W
RECORD BIQUAD
0xBC
R/W
COEFFICIENT A2
0xBD
R/W
REVISION ID REGISTER
0xFF
REVISION ID
R
Software Reset
The device provides a software controlled reset (Table
2) that is used to return most registers to their default
(POR) states (the record biquad and playback parametric
equalizer coefficients are not reset). The software reset
register is a pushbutton, write only register. As a result,
a read of this register always returns 0x00. Writing logichigh to SWRESET triggers a software register reset, while
writing a logic-low to SWRESET has no effect.
Table 2. Software Reset Register
ADDRESS: 0x00
BIT
NAME
TYPE
POR
DESCRIPTION
Pushbutton Software Device Reset
0: Writing a logic low to SWRESET has no effect.
1: Reset all registers to their default POR values. This excludes the record biquad
and playback parametric equalizer filter coefficients (Table 30 and Table 52).
7
SWRESET
W
0
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
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Maxim Integrated │ 80
MAX98090
Ultra-Low Power Stereo Audio Codec
Power and Performance Management
The device includes comprehensive power management
to allow the disabling of unused blocks to minimize supply current. In addition to this, the available power modes
provide a software configurable choice between highest
performance and reduced power consumption.
Device Performance Configuration
The Bias Control register (Table 3) selects the method
used to derive the common-mode reference voltage. A
common-mode bias created by resistive division (from the
AVDD supply) facilitates lower overall power consumption
by disabling the bandgap reference circuit. However, this
type of BIAS reference has the disadvantage of scaling
with the AVDD supply voltage (and thus also has reduced
PSRR). When derived from a bandgap reference, BIAS
is constant regardless of the supply voltage, but the additional circuitry increases power consumption.
The ADC, DAC, and headphone playback all have optional high-performance modes (Tables 4 and 5). In each
case, these modes trade additional power consumption
for enhanced performance. The ADC also has optional
Table 3. Bias Control Register
ADDRESS: 0x42
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
BIAS_MODE
R/W
0
Select source for BIAS.
0: BIAS derived from resistive division.
1: BIAS created by bandgap reference.
Table 4. DAC and Headphone Performance Mode Control Register
ADDRESS: 0x43
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
PERFMODE
R/W
0
Performance Mode
Selects DAC to headphone playback performance mode:
1: Low power headphone playback mode.
0: High performance headphone playback mode.
0
DACHP
R/W
0
DAC High-Performance Mode
0: DAC settings optimized for lowest power consumption.
1: DAC settings optimized for best performance.
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Maxim Integrated │ 81
MAX98090
Ultra-Low Power Stereo Audio Codec
dither (recommended for the cleanest spectrum), and can
be configured to two different oversampling rates. See the
Analog-to-Digital Converter (ADC) section for additional
details on ADC operation.
Device Enable Configuration
In addition to a device global shutdown control, the major
input and output blocks can be independently enabled
(or disabled) to optimize power consumption. The device
global shutdown control is detailed in Table 6.
Table 5. ADC Performance Mode Control Register
ADDRESS: 0x44
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
OSR128
R/W
1
ADC Oversampling Rate
0: fADCCLK = 64 x fS
1: fADCCLK = 128 x fS
1
ADCDITHER
R/W
1
ADC Quantizer Dither
0: Dither disabled.
1: Dither enabled.
0
ADCHP
R/W
0
ADC High-Performance Mode
0: ADC is optimized for low power operation.
1: ADC is optimized for best performance.
Table 6. Device Shutdown Register
ADDRESS: 0x45
BIT
NAME
TYPE
POR
DESCRIPTION
Device Active-Low Global Shutdown Control
0: Device is in shutdown.
1: Device is active.
Certain registers should not be written to while the device is active (Table 90).
7
SHDN
R/W
0
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
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Maxim Integrated │ 82
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 7 details the available input signal path enables
(with the exception of the analog microphone inputs
1/2, which are enabled from registers 0x10 and 0x11, or
Tables 9 and 10, respectively). Table 8 details the available output signal path enables.
When the device is in global shutdown, the major input
and output blocks are all disabled to conserve power.
However, the I2C interface remains active and all device
registers can be configured. Certain registers should be
programmed while in shutdown only (detailed in Table
90). Changing these registers when the device is active
could result in unexpected behavior. For optimal minimized power consumption, only enable the stage blocks
that are part of the intended signal path configuration.
Table 7. Input Enable Register
ADDRESS: 0x3E
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
MBEN
R/W
0
Microphone Bias Enable
0: Microphone bias disabled.
1: Microphone bias enabled.
3
LINEAEN
R/W
0
Enables Line A Analog Input Block
0: Line A input amplifier disabled.
1: Line A input amplifier enabled.
2
LINEBEN
R/W
0
Enables Line B Analog Input Block
0: Line B input amplifier disabled.
1: Line B input amplifier enabled.
1
ADREN
R/W
0
Right ADC Enable
0: Right ADC disabled.
1: Right ADC enabled.
0
ADLEN
R/W
0
Left ADC Enable
0: Left ADC disabled.
1: Left ADC enabled.
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Maxim Integrated │ 83
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 8. Output Enable Register
ADDRESS: 0x3F
DESCRIPTION
BIT
NAME
TYPE
POR
7
HPREN
R/W
0
Right Headphone Output Enable
0: Right headphone output disabled.
1: Right headphone output enabled.
6
HPLEN
R/W
0
Left Headphone Output Enable
0: Left headphone output disabled.
1: Left headphone output enabled.
5
SPREN
R/W
0
Right Class D Speaker Output Enable
0: Right speaker output disabled.
1: Right speaker output enabled.
4
SPLEN
R/W
0
Left Class D Speaker Output Enable
0: Left speaker output disabled.
1: Left speaker output enabled.
3
RCVLEN
R/W
0
Receiver (Earpiece)/Left Line Output Enable
0: Receiver/left line output disabled.
1: Receiver/left line output enabled.
2
RCVREN
R/W
0
Right Line Output Enable
0: Right line output disabled.
1: Right line output enabled.
1
DAREN
R/W
0
Right DAC Digital Input Enable
0: Right DAC input disabled.
1: Right DAC input enabled.
0
DALEN
R/W
0
Left DAC Digital Input Enable
0: Left DAC input disabled.
1: Left DAC input enabled.
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Maxim Integrated │ 84
MAX98090
Ultra-Low Power Stereo Audio Codec
Audio Input Configuration
The device features either six (WLP package) or four
(TQFN package) flexible analog inputs. Each pair can
be configured as either an analog microphone input, a
MBEN
MBVSEL[1:0]
MICROPHONE
BIAS
GENERATOR
MICBIAS
IN1-IN2
IN5-IN6
PA1EN[1:0]
PGAM1[4:0]
MIC 1
INPUT
MUX
MIC 1
PREAMP
MIC 1
PGA
IN3
0dB
10dB
30dB
MIC 2
INPUT
MUX
MIC 2
PREAMP
EXTMIC[1]
PA2EN[1:0]
IN1SEEN
IN3SEEN
IN5SEEN
IN34DIFF
IN4
IN1
IN3
IN5
IN3-IN4
LINE A
INPUT
MIXER
PCLK
DIGMICR
DIGITAL
MIC DATA
LEFT MUX
DIGITAL
MIC DATA
LEFT MUX
DMDL
DMDR
ADCL
ADC
LEFT
ADLEN
IN2/DMC
IN5-IN6
DIGITAL
MICROPHONE
CONTROL
FLEXSOUND
TECHNOLOGY
DSP
DIGMICL
MICCLK[2:0]
EXTMIC[0]
IN1/DMD
IN3-IN4
single-ended or differential line input(s), or as a reduced
power, full-scale differential analog input direct to the ADC
mixer. The analog microphone and line inputs can either
be routed to the stereo ADC mixer for recording or directly
to any analog output mixer for playback.
ADCR
ADC
RIGHT
ADCHP
OSR128
ADCDITHER
ADREN
0dB TO 20dB
ZDENB
MIC 2
PGA
0dB TO 20dB
0dB
10dB
30dB
PGAM2[4:0]
IN1-IN2
IN3-IN4
LINEAEN
EXTBUFA
IN5-IN6
ADC
LEFT
LINE B MIXER
LINE A
MIC 1
MIXADL[6:0]
MIC 2
LINE A
PGA
-6dB TO 20dB
IN1-IN2
IN3-IN4
IN5
MIXG135
IN6
MIXG246
(WLP ONLY)
IN2
IN4
IN6
IN6-IN5
LINAPGA[2:0]
LINBPGA[2:0]
IN5-IN6
ADC
RIGHT
MIXER
LINE B
LINE A
MIC 1
MIXADR[6:0]
MIC 2
LINE B
INPUT
MIXER
IN2SEEN
IN4SEEN
IN6SEEN
IN65DIFF
LINE B
PGA
-6dB TO 20dB
LINEBEN
EXTBUFB
MAX98090
ANALOG
OUTPUT
MIXERS
Figure 5. Analog Audio Input Functional Diagram
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Maxim Integrated │ 85
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Microphone Inputs
additional analog input pair (IN5 and IN6) can be configured as a differential input (IN5 - IN6) to either microphone amplifier 1 or 2 (Table 24).
The device includes three differential microphone inputs
(three for the WLP package and two for the TQFN package) and a programmable, low-noise microphone bias
for powering a wide variety of external micro­
phones
(Figure 6). By default, analog inputs IN1 and IN2 differentially (IN1/IN2) provide the input to microphone amplifier
1, while IN3 and IN4 differentially (IN3/IN4) form the input
to microphone amplifier 2. For the WLP package, the
MBEN
In the typical application, one microphone input is used
for the handset microphone and the other is used as an
accessory microphone (IN1/IN2 and IN3/IN4). In systems
using a background noise microphone, IN5/IN6 (WLP
only) can be retasked as another microphone input.
MIXADL[6:0]
MBVSEL[1:0]
IN1-IN2
MICROPHONE
BIAS
GENERATOR
MICBIAS
EXTMIC[0]
PA1EN[1:0]
IN3-IN4
IN5-IN6
ADC
LEFT
MIC 2 MIXER
MIC 1
PGAM1[4:0]
LINE A
IN1/DMD
IN2/DMC
IN1-IN2
IN5-IN6
MIC 1
INPUT
MUX
IN5
LINE B
MIC 1
PREAMP
0dB
10dB
30dB
0dB TO 20dB
IN3-IN4
IN4
IN5-IN6
IN3-IN4
IN5-IN6
ADC
RIGHT
MIC 2 MIXER
ZDENB
LINE B
IN3
IN1-IN2
MIC 1
LINE A
IN6
(WLP ONLY)
MIC 1
PGA
MAX98090
MIC 2
INPUT
MUX
MIC 2
PREAMP
EXTMIC[1]
PA2EN[1:0]
0dB
10dB
30dB
LINE A
LINE B
MIXADR[6:0]
MIC 2
PGA
0dB TO 20dB
PGAM2[4:0]
ANALOG
OUTPUT
MIXERS
Figure 6. Analog Microphone Input Functional Diagram
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Maxim Integrated │ 86
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Microphone Preamplifier and PGA
The analog microphone inputs have two stages of programmable gain amplifiers, and are then routed to the
ADC mixer (record), the analog outputs (playback), or
simultaneously to both. The first, a coarse preamplifier
gain stage, includes the analog microphone enable, and
offers selectable 0dB, 20dB, or 30dB gain settings. The
second, a fine gain stage, is a programmable-gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps
(Tables 9 and 10). Together, the two stages provide up
to 50dB of signal gain for the analog microphone inputs.
To maximize the signal-to-noise ratio, use the coarse
gain settings of the first stage whenever possible. Zerocrossing detection is included on the PGA to minimize
zipper noise while making gain changes.
Table 9. Microphone 1 Enable and Level Configuration Register
ADDRESS: 0x10
BIT
NAME
TYPE
POR
7
—
—
—
DESCRIPTION
—
0
Microphone 1 Input Amplifier Enable and Coarse Gain Setting
00: Disabled 10: 20dB
01: 0dB
11: 30dB
4
1
Microphone 1 Programmable Gain Amplifier Fine Adjust Configuration
3
0
6
5
2
PA1EN[1:0]
PGAM1[4:0]
R/W
R/W
0
1
1
0
0
0
0x1F: 0dB
0x14: 0dB
0x13: 1dB
0x12: 2dB
0x11: 3dB
0x10: 4dB
0x0F: 5dB
0x0E: 6dB
0x0D: 7dB
0x0C: 8dB
0x0B: 9dB
0x0A: 10dB
0x09: 11dB
0x08: 12dB
0x07: 13dB
0x06: 14dB
0x05: 15dB
0x04: 16dB
0x03: 17dB
0x02: 18dB
0x01: 19dB
0x00: 20dB
Table 10. Microphone 2 Enable and Level Configuration Register
ADDRESS: 0x11
BIT
NAME
TYPE
POR
7
—
—
—
PA2EN[1:0]
R/W
DESCRIPTION
—
0
Microphone 2 Input Amplifier Enable and Coarse Gain Setting
00: Disabled 10: 20dB
01: 0dB
11: 30dB
4
1
Microphone 2 Programmable Gain Amplifier Fine Adjust Configuration
3
0
0x1F: 0dB
1
0x14: 0dB
0x13: 1dB
0x12: 2dB
0x11: 3dB
0x10: 4dB
0x0F: 5dB
6
5
2
PGAM2[4:0]
R/W
0
1
0
0
0
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0x0E: 6dB
0x0D: 7dB
0x0C: 8dB
0x0B: 9dB
0x0A: 10dB
0x09: 11dB
0x08: 12dB
0x07: 13dB
0x06: 14dB
0x05: 15dB
0x04: 16dB
0x03: 17dB
0x02: 18dB
0x01: 19dB
0x00: 20dB
Maxim Integrated │ 87
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Microphone Bias Voltage
The device features a regulated, low noise microphone
bias output (MICBIAS) that can be configured to power
a wide range of external microphone devices. To enable
the microphone bias output, set MBEN in the input enable
register (Table 7). When the device is powered and the
microphone bias is disabled (MBEN is low or the device
is in shutdown), MICBIAS is placed in a high-impedance
state. The microphone bias voltage can be set by the software to any one of 4 voltages (2.2V, 2.4V, 2.55V, or 2.8V)
by programming the Microphone Bias Level Configuration
register (Table 11).
Digital Microphone Inputs
One pair of microphone inputs (IN1/IN2) can also be
configured to interface to up to two digital microphones
(Figure 7). The record path DSP is automatically switched
to accept the appropriate digital microphone data channel
when enabled (Figure 13). Both channels (left and right)
must be enabled to use the digital microphone interface.
When both channels are enabled, the digital microphone
interface provides a digital microphone clock on IN2/DMC
and accepts PDM data on IN1/DMD. A single digital microphone input cannot be paired with a single analog microphone input. Left channel data is accepted on falling clock
edges while the right channel data is accepted on the rising
clock edges (see Figure 4 for timing requirements).
To avoid any potential clipping and distortion, always
enable the record path DC blocking filters to remove any
built-in DC offsets when using a digital microphone input
(AHPF, Table 21). The record path biquad filter and digital
gain and level control stages can also be applied to digital
microphone input signals.
Digital Microphone Clock Configuration
The digital microphone clock frequency (fDMC) can be
configured to any one of 6 settings using MICCLK[2:0]
(Table 13). The digital microphone clock is derived from
a PCLK divider, with available settings ranging incrementally from fPCLK/2 to fPCLK/8. This wide range of available
digital microphone clock frequencies is intended to support both current and next generation digital microphones.
Table 12 lists the resulting clock frequencies for commonly used master clock (and resulting PCLK) frequencies.
MICCLK[2:0]
IN2/DMC
IN1/DMD
IN3
IN4
PCLK
DIGITAL
MICROPHONE
CONTROL
ADC
LEFT
MIXER
ADC
LEFT
DIGMICL
DMDL
ADCL
DIGITAL
MIC
LEFT
MUX
FLEXSOUND
TECHNOLOGY
DSP
DMDR
MICBIAS
IN5
IN6
(WLP ONLY)
MAX98090
ADC
RIGHT
MIXER
ADC
RIGHT
ADCR
LEFT
RECORD
PATH DSP
DIGITAL
MIC
RIGHT
MUX
DAI
RIGHT
RECORD
PATH DSP
DIGMICR
Figure 7. Digital Microphone Input Functional Diagram
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Maxim Integrated │ 88
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 11. Microphone Bias Level Configuration Register
ADDRESS: 0x12
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
MBVSEL[1:0]
R/W
1
0
Microphone Bias Level Configuration
00: 2.2V 01: 2.4V
0
0
10: 2.55V
11: 2.8V
Table 12. Digital Microphone Clocks for Commonly Used Master Clocks Settings
Master Clock Frequency (fMCLK)
Approximate Digital
Microphone Clock
Frequency (fDMC)
10MHz
11.2896MHz
12MHz
12.288MHz
13/26MHz
19.2MHz
fPCLK/2
5.0MHz
5.645MHz
6.0MHz
6.144MHz
6.5MHz
—
fPCLK/3
3.333MHz
3.763MHz
4.0MHz
4.096MHz
4.333MHz
6.4MHz
fPCLK/4
2.5MHz
2.822MHz
3.0MHz
3.072MHz
3.25MHz
4.8MHz
fPCLK/5
2.0MHz
2.258MHz
2.4MHz
2.458MHz
2.6MHz
3.84MHz
fPCLK/6
1.667MHz
1.882MHz
2.0MHz
2.048MHz
2.167MHz
3.2MHz
fPCLK/8
1.25MHz
1.411MHz
1.5MHz
1.536MHz
1.625MHz
2.4MHz
Table 13. Digital Microphone Enable
ADDRESS: 0x13
BIT
NAME
TYPE
POR
7
—
—
—
6
5
0
DMICCLK[2:0]
R/W
4
0
0
DESCRIPTION
—
Digital Microphone Clock Rate Configuration
000: fDMC = fPCLK/2 100: fDMC = fPCLK/6
001: fDMC = fPCLK/3
101: fDMC = fPCLK/8
010: fDMC = fPCLK/4 110: Reserved
011: fDMC = fPCLK/5
111: Reserved
3
—
—
—
—
2
—
—
—
—
1
0
DIGMICR
DIGMICL
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R/W
R/W
0
Digital Microphone Clock and Right Channel Enable
0: Right record channel uses on-chip ADC.
1: Right record channel uses digital microphone input.
Digital microphone clock (DMC) is enabled once both data channels are enabled.
0
Digital Microphone Clock and Left Channel Enable
0: Left record channel uses on-chip ADC.
1: Left record channel uses digital microphone input.
Digital microphone clock (DMC) is enabled once both data channels are enabled.
Maxim Integrated │ 89
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Microphone Frequency Compensation
The digital microphone inputs can be configured to produce a wide range of digital microphone clock frequencies. To optimize performance over the entire range of
available frequencies, the device provides configurable
COMPENSATION FILTER RESPONSE (dB)
DIGITAL MICROPHONE COMPENSATION FILTER
RESPONSE vs. NORMALIZED FREQUENCY
2.5
DMIC_COMP = 6
DMIC_COMP = 5
2.0
DMIC_COMP = 4
1.5
DMIC_COMP = 3
DMIC_COMP = 2
DMIC_COMP = 1
DMIC_COMP = 0
1.0
0.5
0
0 x fS
DMIC_COMP = 8
DMIC_COMP = 7
0.1 x fS 0.2 x fS 0.3 x fS 0.4 x fS 0.5 x fS
NORMALIZED FREQUENCY
Figure 8. Digital Microphone Compensation Filter Frequency
Response
frequency range and compensation settings. Once the
master clock (and thus prescaled clock) frequency is
decided, and the digital microphone clock divider is chosen, the digital microphone frequency range bits should
be programmed to the correct range (DMIC_FREQ,
Table 14). If quick configuration mode is used and a
system clock bit is selected (Table 36), then the device
automatically calculates and selects the correct range
once the digital microphone clock divider is configured.
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The digital microphone inputs also provide a configurable
frequency compensation filter with 9 frequency response
settings (Figure 8). Every sample rate and MCLK/PCLK
frequency (and the resulting digital microphone clock
frequency) combination results in a different baseline
frequency response. Table 15 to Table 20 provide the
recommended compensation filter settings for the most
commonly used PCLK frequency and sample rate combinations. Choose the PCLK divider that results in the
DMC clock frequency closest to the optimal frequency for
the built-in digital MIC hardware, and then set the correct
DMIC frequency range (DMIC_FREQ, Table 14). Then,
based on the desired sample rate, select the appropriate
compensation settings from Table 14 (DMIC_COMP).
If the system PCLK frequency does not match one of
these commonly used rates, then refer to the table for the
PCLK frequency that is closest (e.g., if the system PCLK
frequency is 12.5MHz, see Table 17 as 12.288MHz is the
closest common PCLK frequency). As before, choose
the PCLK divider that results in the optimal DMC clock
frequency, and set the appropriate DMIC frequency range
(DMIC_FREQ, Table 14). Then choose the compensation
settings based on the row that is the closest match to the
configured DMC frequency. Similarly, for nonstandard
sample rates choose the column with the common value
closest to the actual system sample rate.
In quick configuration mode, once both the system clock
and sample rate bits are selected (Table 36 and Table
37), the device automatically selects the recommended
response curve once the digital microphone clock divider
is configured. The digital microphone input does not support sample rates in excess of 48kHz (where DHF = 1,
Table 27).
Maxim Integrated │ 90
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 14. Digital Microphone Configuration
ADDRESS: 0x14
BIT
NAME
TYPE
7
0
6
DESCRIPTION
POR
0
Digital Microphone Compensation Filter Configuration
0000–1000: Figure 8 details the available compensation filter configurations.
1001–1111: Configures the compensation filter to a pass through response.
The compensation filter response scales with the sample rate up to the Nyquist
bandwidth limit (fS/2). Automatically decoded in quick configuration mode.
DMIC_COMP[3:0]
R/W
3
—
—
—
—
2
—
—
—
—
R/W
0
R/W
0
5
0
4
0
1
DMIC_FREQ[1:0]
0
Digital Microphone Frequency Range Configuration
00: fDMC < 3.5MHz 10: 4.5MHz ≤ fDMC
01: 3.5MHz ≤ fDMC < 4.5MHz
11: Reserved
If any of the system clock quick configuration bits in register 0x04 are set, then the
frequency range configuration is automatically decoded.
Table 15. Recommended Compensation Filter Settings for fPCLK = 11.2896MHz
fPCLK = fMCLK/PSCLK (See Table 34)
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK
DIVIDER
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
0
fPCLK/2
5.6448
2
7
8
3
3
3
1
fPCLK/3
3.7632
1
7
8
2
2
2
2
fPCLK/4
2.8224
0
7
8
3
3
3
3
fPCLK/5
2.25792
0
7
8
6
6
6
4
fPCLK/6
1.8816
0
7
8
3
3
3
5
fPCLK/8
1.4112
0
7
8
3
3
3
Table 16. Recommended Compensation Filter Settings for fPCLK = 12MHz
fPCLK = fMCLK/PSCLK (See Table 34)
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK
DIVIDER
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
0
fPCLK/2
6
2
7
8
3
3
3
1
fPCLK/3
4
1
7
8
2
2
2
2
fPCLK/4
3
0
7
8
3
3
3
3
fPCLK/5
2.4
0
7
8
5
5
6
4
fPCLK/6
2
0
7
8
3
3
3
5
fPCLK/8
1.5
0
7
8
3
3
3
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Maxim Integrated │ 91
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 17. Recommended Compensation Filter Settings for fPCLK = 12.288MHz
fPCLK = fMCLK/PSCLK (See Table 34)
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK
DIVIDER
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
0
fPCLK/2
6.144
2
7
8
3
3
3
1
fPCLK/3
4.096
1
7
8
2
2
2
2
fPCLK/4
3.072
0
7
8
3
3
3
3
fPCLK/5
2.4576
0
7
8
6
6
6
4
fPCLK/6
2.048
0
7
8
3
3
3
5
fPCLK/8
1.536
0
7
8
3
3
3
Table 18. Recommended Compensation Filter Settings for fPCLK = 13MHz
fPCLK = fMCLK/PSCLK (See Table 34)
MICCLK
DIVIDER
0
1
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
fPCLK/2
6.5
2
7
8
1
1
1
fPCLK/3
4.333
1
7
8
0
0
1
2
fPCLK/4
3.25
0
7
8
1
1
1
3
fPCLK/5
2.6
0
7
8
4
4
5
4
fPCLK/6
2.167
0
7
8
1
1
1
5
fPCLK/8
1.625
0
7
8
1
1
1
Table 19. Recommended Compensation Filter Settings for fPCLK = 19.2MHz
fPCLK = fMCLK/PSCLK (See Table 34)
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK
DIVIDER
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
0
fPCLK/2
—
—
—
—
—
—
—
1
fPCLK/3
6.4
2
7
8
1
1
1
2
fPCLK/4
4.8
2
7
8
5
5
6
3
fPCLK/5
3.84
1
7
8
2
2
3
4
fPCLK/6
3.2
0
7
8
1
1
2
5
fPCLK/8
2.4
0
7
8
5
5
6
Table 20. Recommended Compensation Filter Settings for fPCLK = 256 x fS
fPCLK = fMCLK/PSCLK (See Table 34)
RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK
DIVIDER
fDMC (MHz)
DMIC_FREQ
8
16
32
44.1
48
0
fPCLK/2
—
—
7
8
3
3
3
1
fPCLK/3
—
—
7
8
2
2
2
2
fPCLK/4
—
—
7
8
3
3
3
3
fPCLK/5
—
—
7
8
6
6
6
4
fPCLK/6
—
—
7
8
3
3
3
5
fPCLK/8
—
—
7
8
3
3
3
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Maxim Integrated │ 92
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Line Inputs
Analog Line Input Mixers
The device includes multiple line level input options
and two analog line input programmable gain amplifiers
(PGAs, Figure 9). The line input structure supports multiple configurations including stereo single-ended inputs,
stereo differential inputs, and stereo mixed single-ended
inputs (any two per line input mixer).
The analog line input mixer allows the selection of either
single-ended or differential inputs to each line input channel (Table 21). The line A input mixer can accept singleended inputs from IN1, IN3, and IN5, or a differential input
from IN3 and IN4 (IN3 - IN4). The line B input mixer can
accept single-ended inputs from IN2, IN4, and IN6, or a
MIXG135
IN1/DMD
IN2/DMC
IN1-IN2
IN1
IN3
IN5
IN3-IN4
LINE A
INPUT
MIXER
-6dB/0dB
MIC 1
IN4
IN2SEEN
IN4SEEN
IN6SEEN
IN65DIFF
MIC 2
IN6
IN5
IN3-IN4
IN5-IN6
ADC
LEFT
MIC 2 MIXER
MIC 1
LINE A
LINEAEN
EXTBUFA
LINE B
IN1-IN2
MAX98090
MIC 2
IN2
IN4
IN6
IN6-IN5
-6dB TO 20dB
LINE A
PGA
IN1SEEN
IN3SEEN
IN5SEEN
IN34DIFF
MIC 1
IN3
MIXADL[6:0]
LINAPGA[2:0]
IN3-IN4
IN5-IN6
LINEBEN
EXTBUFB
ADC
RIGHT
MIC 2 MIXER
MIC 1
LINE A
LINE B
INPUT
MIXER
-6dB/0dB
-6dB TO 20dB
LINE B
PGA
LINE B
MIXADR[6:0]
(WLP ONLY)
MIXG246
ANALOG
OUTPUT
MIXERS
LINBPGA[2:0]
Figure 9. Analog Line Input Functional Diagram
Table 21. Line Input Mixer Configuration Register
ADDRESS: 0x0D
DESCRIPTION
BIT
NAME
TYPE
POR
7
IN34DIFF
R/W
0
Selects IN3, IN4 differentially as an input to the line A mixer.
6
IN65DIFF
R/W
0
Selects IN6, IN5 differentially as an input to the line B mixer (WLP only).
5
IN1SEEN
R/W
0
Selects IN1 single ended as an input to the line A mixer.
4
IN2SEEN
R/W
0
Selects IN2 single ended as an input to the line B mixer.
3
IN3SEEN
R/W
0
Selects IN3 single ended as an input to the line A mixer.
2
IN4SEEN
R/W
0
Selects IN4 single ended as an input to the line B mixer.
1
IN5SEEN
R/W
0
Selects IN5 single ended as an input to the line A mixer (WLP only).
0
IN6SEEN
R/W
0
Selects IN6 single ended as an input to the line B mixer (WLP only).
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Maxim Integrated │ 93
MAX98090
Ultra-Low Power Stereo Audio Codec
differential input from IN5 and IN6 (IN6 - IN5). Internally,
all analog signal paths are differential. As a result, singleended inputs have a built in baseline gain of +6dB (from
the single-ended to differential conversion) while differential inputs have 0dB of built in gain.
The line input mixer can also be set to accept and mix
any two single-ended inputs. To facilitate full-scale signals, when mixing two single-ended inputs an optional
-6dB of attenuation is available (MIXG135 and MIXG246,
Table 23). The line input mixer attenuation setting has
no effect if enabled when only a single input source is
selected. If a differential input to either mixer is enabled,
any single-ended inputs that are also selected are ignored,
and the mixer accepts only the differential input.
Analog Line Input PGAs
To facilitate a wide range of input signal levels, each analog
line input includes a coarse programmable gain amplifier
(PGA) that can provide from 6dB of attenuation to 20dB
of signal gain. The line inputs are then routed to either the
ADC mixer (record) or analog outputs (playback).
If the line input signal exceeds full scale and requires
additional attenuation, the external gain mode provides
trimmed internal feedback resistors (20kΩ) for custom
gain levels. Line input external gain mode is not intended
to provide positive gain, and as such for optimal performance any gain of -6dB of higher should be set using the
provided internal PGA gain settings.
Differentially, the external line input gain is set by using
two precision (1% or better), well-matched series input
resistors (Figure 10). Use the following formula to calculate the appropriate differential series input resistors:
AV_EXTLINE = 20 x log (20kΩ/RS_EXT)
For single-ended inputs, the external line input gain is set
using a single precision (1% or better) series input resistor (Figure 10). However, due to the internal single-ended
to differential conversion, this configuration creates an
unbalanced differential amplifier configuration (configured
external gain paired with a fixed internal gain of +6dB).
Table 22 provides the appropriate series resistance values for common attenuation settings.
Table 22. External Gain Mode Series Resistance Values
RS_EXT
LINE INPUT
EXTERNAL GAIN (dB)
DIFFERENTIAL (kΩ)
SINGLE-ENDED (kΩ)
AV_EXTLINE = -9.5
60
84.5
AV_EXTLINE = -12.0
80
115
AV_EXTLINE = -15.0
112
165
AV_EXTLINE = -18.0
160
237
DIFFERENTIAL LINE INPUT
SINGLE-ENDED LINE INPUT
RFB_INT+ = 20kΩ
VIN_DIFF+
VIN_DIFF-
RS_EXT+
LINE A
PGA
RS_EXTRFB_INT- = 20kΩ
RFB_INT+ = 20kΩ
VIN_SINGLE-ENDED
VCOMMON_MODE
RS_EXT+
LINE A
PGA
RS_EXT- = 15kΩ
RFB_INT- = 30kΩ
Figure 10. Analog Line Input External Gain Configurations
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Maxim Integrated │ 94
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 23. Line Input Level Configuration Register
ADDRESS: 0x0E
DESCRIPTION
BIT
NAME
TYPE
POR
7
MIXG135
R/W
0
Enable for a -6dB Reduction for Two Single-Ended Line A Mixer Inputs
0: Normal line A mixer operation.
1: Gain is reduced by -6dB when two single-ended inputs are selected.
6
MIXG246
R/W
0
Enable for a -6dB Reduction for Two Single-Ended Line B Mixer Inputs
0: Normal line B mixer operation.
1: Gain is reduced by -6dB when two single-ended inputs are selected
0
Line Input A Programmable Internal Preamp Gain Configuration
LINAPGA[2:0]
R/W
5
4
1
3
1
2
0
1
LINBPGA[2:0]
R/W
0
1
1
000: 20dB
001: 14dB
010: 3dB
011: 0dB
100: -3dB
101, 110, 111: -6dB
Line Input B Programmable Internal Preamp Gain Configuration
000: 20dB
001: 14dB
010: 3dB
011: 0dB
100: -3dB
101, 110, 111: -6dB
Table 24. Input Mode and Source Configuration Register
ADDRESS: 0x0F
DESCRIPTION
BIT
NAME
TYPE
POR
7
EXTBUFA
R/W
0
Selects external resistor gain mode for line input A.
6
EXTBUFB
R/W
0
Selects external resistor gain mode for line input B.
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
External Analog Microphone (IN5/IN6) MUX Configuration (WLP Only)
1
0
EXTMIC[1:0]
0
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R/W
0
00: External microphone disabled:
IN1/IN2 selected for MIC 1
IN3/IN4 selected for MIC 2
10: External microphone to MIC 2:
IN1/IN2 selected for MIC 1
IN5/IN6 selected for MIC 2
01: External microphone to MIC 1:
IN5/IN6 selected for MIC 1
IN3/IN4 selected for MIC 2
11: Reserved.
Maxim Integrated │ 95
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Input PGA to Analog Output Mixer
Analog Full-Scale Direct to ADC Mixer Inputs
The analog line input PGA and analog microphone PGA
outputs can be routed directly to any of the analog output mixers. This configuration allows the analog inputs
to operate as line or microphone level input amplifiers
capable of driving headphone, speaker, receiver, or line
output loads. The analog inputs can also be mixed with
the DAC outputs to any of the available analog output
mixers. The figures in the appropriate analog input and
output sections detail the signal routing.
The analog inputs can also be configured to accept and
route differential analog signals directly to the ADC mixers
(record path, Figure 11). By disabling and bypassing the
analog microphone and line input gain stages, this mode
provides a reduced power configuration for full-scale (up
to 1VRMS) analog input signals. Unlike the analog microphone and line input configurations, this mode does not
allow the input signals to be routed directly to the analog
output mixers (playback path, Figure 32).
MIXADL[6:0]
IN1/DMD
IN1-IN2
IN2/DMC
IN3-IN4
ADLEN
IN5-IN6
ADC
LEFT
MIC 2 MIXER
MIC 1
IN3
LINE A
IN4
LINE B
IN1-IN2
ADC
LEFT
ADCHP
OSR128
ADCDITHER
FLEXSOUND
TECHNOLOGY
DSP
IN3-IN4
IN5-IN6
ADC
RIGHT
MIC 2 MIXER
MIC 1
IN5
IN6
ADC
RIGHT
LINE A
(WLP ONLY)
LINE B
MAX98090
ADREN
MIXADR[6:0]
Figure 11. Analog Direct to ADC Mixer Input Functional Diagram
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Maxim Integrated │ 96
MAX98090
Ultra-Low Power Stereo Audio Codec
Audio Record Path
The device record path comprises several sequential
blocks. The first block is a stereo ADC with configurable
mixers that can accept input from the microphone PGAs,
line input PGAs, or directly differentially from any of the
analog input pairs. Internally, the digital record path has
two channels (left and right), which accept a digital signal
either from the appropriate digital microphone or ADC
output channel. The two channels then pass through several DSP stages before being routed into the digital audio
interface (DAI, Figure 12).
DIGITAL MIC DATA
IN1-IN2
IN3-IN4
MIXADL[6:0]
DMDL
IN5-IN6
ADC
LEFT
LINE B MIXER
LINE A
ADC
LEFT
ADCL
MIC 1
MIC 2
IN1-IN2
LEFT RECORD PATH
DIGITAL
MIC
LEFT
MUX
DIGMICL
ADLEN
ADREN
ADCHP
OSR128
ADCDITHER
DIGMICR
DMDR
IN3-IN4
IN5-IN6
ADC
LINE A RIGHT
LINE B MIXER
MIC 1
MIC 2
ADC
RIGHT
MIXADR[6:0]
ADCR
DIGITAL
MIC
RIGHT
MUX
LEFT
FILTERS
LEFT
BIQUAD
FILTER
MODE
AHPF
DHF
RECBQEN
AVBQ[3:0]
REC_B0[23:0]
REC_B1[23:0]
REC_B2[23:0]
REC_A1[23:0]
REC_A2[23:0]
DSTS[1:0]
RIGHT
FILTERS
RIGHT
BIQUAD
FILTER
RIGHT
SIDETONE
FLEXSOUND
TECHNOLOGY DSP
LEFT
SIDETONE
LEFT
LEVEL
AVLG[2:0]
AVL[3:0]
AVRG[2:0]
AVR[3:0]
DAI
RIGHT
LEVEL
RIGHT RECORD PATH
SIDETONE TO
PLAYBACK PATH
L/R ST
LEVEL
DVST[3:0]
Figure 12. Record Path Block Diagram
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Maxim Integrated │ 97
MAX98090
Ultra-Low Power Stereo Audio Codec
DIGITAL MIC DATA
IN1-IN2
IN3-IN4
MIXADL[6:0]
DMDL
IN5-IN6
ADC
LINE A LEFT
LINE B MIXER
ADC
LEFT
ADCL
MIC 1
MIC 2
IN1-IN2
LEFT RECORD PATH
DIGITAL
MIC
LEFT
MUX
DIGMICL
ADLEN
ADREN
ADCHP
OSR128
ADCDITHER
DIGMICR
DMDR
IN3-IN4
IN5-IN6
ADC
RIGHT
LINE B MIXER
LINE A
MIC 1
MIC 2
ADC
RIGHT
ADCR
MIXADR[6:0]
DIGITAL
MIC
RIGHT
MUX
LEFT
FILTERS
LEFT
BIQUAD
FILTER
MODE
AHPF
DHF
RECBQEN
AVBQ[3:0]
REC_B0[23:0]
REC_B1[23:0]
REC_B2[23:0]
REC_A1[23:0]
REC_A2[23:0]
DSTS[1:0]
RIGHT
FILTERS
RIGHT
BIQUAD
FILTER
RIGHT
SIDETONE
LEFT
SIDETONE
LEFT
LEVEL
AVLG[2:0]
AVL[3:0]
AVRG[2:0]
AVR[3:0]
DAI
RIGHT
LEVEL
RIGHT RECORD PATH
FLEXSOUND
TECHNOLOGY DSP
SIDETONE TO
PLAYBACK PATH
L/R ST
LEVEL
DVST[3:0]
Figure 13. Record Path ADC Section
Analog-to-Digital Converter (ADC)
The stereo ADC architecture includes two independent
audio paths and provides a flexible, fully configurable
input mixer, two performance and power based configuration options, oversampling rate selection, and an
input dither option (Figure 13). Both ADC channels can
be enabled independently allowing the device to support
both stereo and left or right mono configurations (Table 7).
ADC Functional Configuration
The ADC can be configured into one of two operating
modes. One operating mode is optimized for maximum
dynamic performance while the other is optimized for
lower power consumption (Table 5). Input dither can also
be added to the ADC record path. This feature consumes
almost no appreciable power, but raises the RMS level of
the noise floor slightly at the high end of the audio band.
The ADC supports both an over sampling rate (OSR) of
64 and 128 times the configured sampling frequency (fS).
An OSR of 128 x fS optimizes ADC performance at the
cost of slightly more power consumption than an OSR of
64 x fS.
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The DSP timing, however, places some limitations on
which OSR can be used. For voice applications using
standard (fS = 8kHz) and wideband (fS = 16kHz) sampling
rates, the DSP is typically configured to utilize the voice
filters (IIR). If the voice filters are enabled, the OSR is
automatically configured to 128 x fS and cannot be manually reprogrammed in order to meet timing requirements.
In most standard music/full audio range applications
(where fS = 32kHz, 44.1kHz, 48kHz, etc.) the music filters
(FIR) are used. If the music filters are enabled, the OSR
can be configured manually, however, the prescaled master clock (PCLK) must always be at least twice the frequency of the ADC sampling clock. To ensure this condition is met, if fPCLK < 256 x fS, then the OSR must be set
to 64 x fS. In addition, if the sampling rate exceeds 48kHz
(DHF = 1, such as fS = 96kHz), then the OSR must be
configured to 64 x fS regardless of the ratio. In any other
music filter configuration, OSR = 128 can be selected as
desired for optimal ADC performance.
Maxim Integrated │ 98
MAX98090
Ultra-Low Power Stereo Audio Codec
ADC Input Mixer Configuration
The device allows for each ADC input mixer to be configured separately to accept any combination of valid
input sources. The ADC mixers can accept input from
the microphone PGAs (1 or 2), line input PGAs (A or B),
or directly differentially from any of the analog input pairs
(IN1/IN2, IN3/IN4, or IN5/IN6). The ADC input mixers then
route the selected sources to the left and right ADC inputs
(Tables 25 and Table 26).
Record Path FlexSound DSP
The digital record path is part of the FlexSound technology DSP and comprises multiple sequential DSP
blocks. The first DSP stage contains digital filters including a voice filter (IIR), music filter (FIR), and a highpass
DC-blocking filter. The next stage is a digital biquad filter
with a pre-attenuation amplifier, and it is followed by a
digital gain and level control stage. The record path DSP
also features a digital sidetone path that is routed to and
mixed into the digital playback path (Figure 14).
Record Path Digital Filters
The record path DSP includes a digital filter stage. One
filter, set with the MODE bit (Table 27), offers the choice
between the IIR voice filters and the FIR music filters. The
IIR filters are optimized for standard (fS = 8kHz) and wideband (fS = 16kHz) voice applications, while the FIR filters
are optimized for low power operation at higher audio/
music sampling rates. For sampling rates in excess of
48kHz (fLRCLK > 48kHz), use the FIR music filters and set
the DHF bit. The MODE configuration selected applies to
both channels of both the record and playback path DSP.
The record path DSP also features a DC-blocking filter.
This filter can be used with both the IIR voice and FIR
music filters, and blocks low frequency (including DC)
input signals outside of the lower end of the audio band.
Table 25. Left ADC Mixer Input Configuration Register
ADDRESS: 0x15
BIT
NAME
7
—
TYPE
POR
DESCRIPTION
—
—
—
6
R/W
0
Selects microphone input 2 to left ADC mixer.
5
R/W
0
Selects microphone input 1 to left ADC mixer.
4
R/W
0
Selects line input B to left ADC mixer.
R/W
0
Selects line input A to left ADC mixer.
2
R/W
0
Selects IN5/IN6 differential input direct to left ADC mixer (WLP only).
1
R/W
0
Selects IN3/IN4 differential input direct to left ADC mixer.
0
R/W
0
Selects IN1/IN2 differential input direct to left ADC mixer.
3
MIXADL[6:0]
Table 26. Right ADC Mixer Input Configuration Register
ADDRESS: 0x16
BIT
NAME
7
—
TYPE POR
DESCRIPTION
—
—
6
R/W
0
Selects microphone input 2 to right ADC mixer.
5
R/W
0
Selects microphone input 1 to right ADC mixer.
4
R/W
0
Selects line input B to right ADC mixer.
3
—
R/W
0
Selects line input A to right ADC mixer.
2
R/W
0
Selects IN5/IN6 differential input direct to right ADC mixer (WLP only).
1
R/W
0
Selects IN3/IN4 differential input direct to right ADC mixer.
0
R/W
0
Selects IN1/IN2 differential input direct to right ADC mixer.
MIXADR[6:0]
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Maxim Integrated │ 99
MAX98090
Ultra-Low Power Stereo Audio Codec
DIGITAL MIC DATA
IN1-IN2
IN3-IN4
DMDL
MIXADL[6:0]
IN5-IN6
ADC
LEFT
LINE B MIXER
LINE A
ADCL
ADC
LEFT
MIC 1
LEFT RECORD PATH
DIGITAL
MIC
LEFT
MUX
DIGMICL
MIC 2
ADLEN
ADREN
IN1-IN2
ADCHP
OSR128
ADCDITHER
DIGMICR
DMDR
IN3-IN4
IN5-IN6
ADC
LINE A RIGHT
LINE B MIXER
MIC 1
ADCR
ADC
RIGHT
MIXADR[6:0]
MIC 2
DIGITAL
MIC
RIGHT
MUX
LEFT
FILTERS
LEFT
BIQUAD
FILTER
MODE
AHPF
DHF
RECBQEN
AVBQ[3:0]
REC_B0[23:0]
REC_B1[23:0]
REC_B2[23:0]
REC_A1[23:0]
REC_A2[23:0]
DSTS[1:0]
RIGHT
FILTERS
RIGHT
BIQUAD
FILTER
RIGHT
SIDETONE
LEFT
SIDETONE
LEFT
LEVEL
AVLG[2:0]
AVL[3:0]
AVRG[2:0]
AVR[3:0]
DAI
RIGHT
LEVEL
RIGHT RECORD PATH
SIDETONE TO
PLAYBACK PATH
FLEXSOUND
TECHNOLOGY DSP
L/R ST
LEVEL
DVST[3:0]
Figure 14. Record Path FlexSound Technology DSP Block
Table 27. DSP Filter Configuration Register
ADDRESS: 0x26
BIT
NAME
TYPE
POR
DESCRIPTION
7
MODE
R/W
1
Enables the Codec DSP FIR Music Filters (Default IIR Voice Filters)
0: The codec DSP filters operate in IIR voice mode with stop band frequencies below
the fS/2 Nyquist rate. The voice mode filters are optimized for 8kHz or 16kHz voice
application use.
1: The codec DSP filters operate in a linear phase FIR audio mode optimized to
maintain stereo imaging and operate at higher fS rates while utilizing lower power.
6
AHPF
R/W
0
Enables the Record Path DC-Blocking Filter
0: DC-blocking filter disabled.
1: DC-blocking filter enabled.
5
DHPF
R/W
0
Enables the Playback Path DC-Blocking Filter
0: DC-blocking filter disabled.
1: DC-blocking filter enabled.
4
DHF
R/W
0
Enables the DAC High Sample Rate Mode (LRCLK > 48kHz, FIR Only)
0: LRCLK is less than 48kHz. 8x FIR interpolation filter used.
1: LRCLK is greater than 48kHz. 4x FIR interpolation filter used.
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
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Maxim Integrated │ 100
MAX98090
Ultra-Low Power Stereo Audio Codec
Record Path Biquad Filter
The record path DSP has a single stage digital biquad filter with a programmable preattenuation amplifier. The digital biquad filter configuration applies to both the left and
right record channels. To enable the record path biquad
filter, set RECBQEN high (Table 28). Once enabled, the
level of preattenuation can be adjusted from 0dB down to
-15dB (denoted AV_BQ, see Table 29). The digital biquad
filter cannot be set to a gain greater than ±12dB, to a Q
greater than 10, or to below a minimum fC that varies by
filter type. See the Electrical Characteristics table.
The digital biquad coefficients are uninitialized at powerup, and if the filter is going to be used, the coefficients
must be programmed before the device and biquad filter
are enabled. The transfer function is:
H(z) =
B 0 + B 1 × Z −1 + B 2 × Z −2
A 0 + A 1 × Z −1 + A 2 × Z −2
Table 28. DSP Biquad Filter Enable Register
ADDRESS: 0x41
DESCRIPTION
BIT
NAME
TYPE POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
RECBQEN
R/W
0
Enable Biquad Filter in Record Path
0: Biquad filter not used.
1: Biquad filter used in record path.
2
EQ3BANDEN
R/W
0
Enable 3-Band EQ in Playback Path (Bands 4–7 Are Not Used)
0: 3-band EQ disabled.
1: 3-band EQ enabled. Only valid if EQ7BANDEN = 0 and EQ5BANDEN = 0.
1
EQ5BANDEN
R/W
0
Enable 5-Band EQ in Playback Path (Bands 6 and 7 Are Not Used)
0: 5-band EQ disabled.
1: 5-band EQ enabled. Only valid if EQ7BANDEN = 0
0
EQ7BANDEN
R/W
0
Enable 7-Band EQ in Playback Path
0 : 7-band EQ disabled.
1 : 7-band EQ enabled. This makes EQ5BANDEN and EQ3BANDEN redundant.
Table 29. Record Path Biquad Digital Preamplifier Level Configuration Register
ADDRESS: 0x19
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
2
1
0
AVBQ[3:0]
0
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R/W
0
0
0
ADC Biquad Digital Preamplifier Gain Configuration
0x0: +0dB
0x1: -1dB
0x2: -2dB
0x3: -3dB
0x4: -4dB
0x5: -5dB
0x6: -6dB
0x7: -7dB
0x8: -8dB
0x9: -9dB
0xA: -10dB
0xB: -11dB
0xC: -12dB
0xD: -13dB
0xE: -14dB
0xF: -15dB
Maxim Integrated │ 101
MAX98090
Ultra-Low Power Stereo Audio Codec
The digital biquad filter has five user-programmable
coefficients (B0, B1, B2, A1, and A2), and each individual
coefficient is 3 bytes (24 bits) long (A0 is fixed at 1). They
occupy 15 consecutive registers (Table 30) and each set
of three registers (per coefficient) must be programmed
consecutively for the settings to take effect. The coefficients are stored using a two’s complement format where
the first 4 bits are the integer portion and the last 20 bits
are the decimal portion (which results in an approximate
+8 to -8 range for each coefficient).
Record Path Sidetone
The record path sidetone is available to allow a low-level
copy of the recorded audio signal to be mixed back into
the playback audio signal. When enabled, the sidetone
can route the left channel, right channel, or both divided
by two and then summed back into the playback path
DSP. The sidetone digital gain can be programmed from
-0.5dB to -60.5dB (Table 31). The digital sidetone is commonly used in telephony to allow the speaker to hear their
own voice to provide a more natural user experience.
Table 30. Record Path Biquad Filter Coefficients
NAME
TYPE
0xAF
ADDRESS RANGE
0xB0
0xB1
RECORD BIQUAD COEFFICIENT B0
R/W
REC_B0[23:16]
COEFFICIENT SEGMENT
REC_B0[15:8]
REC_B0[7:0]
0xB2
0xB3
0xB4
RECORD BIQUAD COEFFICIENT B1
R/W
REC_B1[23:16]
REC_B1[15:8]
REC_B1[7:0]
0xB5
0xB6
0xB7
RECORD BIQUAD COEFFICIENT B2
R/W
REC_B2[23:16]
REC_B2[15:8]
REC_B2[7:0]
0xB8
0xB9
0xBA
RECORD BIQUAD COEFFICIENT A1
R/W
REC_A1[23:16]
REC_A1[15:8]
REC_A1[7:0]
0xBB 0xBC 0xBD
RECORD BIQUAD COEFFICIENT A2
R/W
REC_A2[23:16]
REC_A2[15:8]
REC_A2[7:0]
Table 31. Record Path Sidetone Configuration Register
ADDRESS: 0x1A
BIT
NAME
TYPE
7
0
DSTS[1:0]
6
5
0
—
—
0
3
0
DVST[4:0]
R/W
0
1
0
0
0
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Sidetone Enable and Digital Source Configuration
00: No sidetone selected 10: Right channel
01: Left channel
11: Left + right channel
—
4
2
DESCRIPTION
POR
—
Sidetone Digital Gain Configuration
0x00: OFF
0x01: -0.5dB
0x02: -2.5dB
0x03: -4.5dB
0x04: -6.5dB
0x05: -8.5dB
0x06: -10.5dB
0x07: -12.5dB
0x08: -14.5dB
0x09: -16.5dB
0x0A: -18.5dB
0x0B: -20.5dB
0x0C: -22.5dB
0x0D: -24.5dB
0x0E: -26.5dB
0x0F: -28.5dB
0x10: -30.5dB
0x11: -32.5dB
0x12: -34.5dB
0x13: -36.5dB
0x14: -38.5dB
0x15: -40.5dB
0x16: -42.5dB
0x17: -44.5dB
0x18: -46.5dB
0x19: -48.5dB
0x1A: -50.5dB
0x1B: -52.5dB
0x1C: -54.5dB
0x1D: -56.5dB
0x1E: -58.5dB
0x1F: -60.5dB
Maxim Integrated │ 102
MAX98090
Ultra-Low Power Stereo Audio Codec
Record Path Digital Gain and Level Control
The stereo record path DSP includes a digital gain
and level control stage. The settings can be configured
independently by channel, and are primarily used when
adjusting the record level for digital microphones. The
coarse digital gain adjustment can be set from 0dB to
+42dB in 6dB increments, and the fine adjust level control
gain can be set from -12dB to +3dB in 1dB increments
(Tables 32 and 33).
Table 32. Left Record Path Digital Gain Configuration Register
ADDRESS: 0x17
BIT
NAME
TYPE
POR
7
—
—
—
AVLG[2:0]
R/W
6
5
0
0
4
0
3
0
2
1
AVL[3:0]
R/W
0
0
1
1
DESCRIPTION
—
Left Record Path Digital Coarse Gain Configuration
000 : 0dB
010 : +12dB
100 : +24dB
001 : +6dB
011 : +18dB
101 : +30dB
110 : +36dB
111 : +42dB
Left Record Path Digital Fine Adjust Gain Configuration
0x0: +3dB
0x4: -1dB
0x8: -5dB
0x1: +2dB
0x5: -2dB
0x9: -6dB
0x2: +1dB
0x6: -3dB
0xA: -7dB
0x3: +0dB
0x7: -4dB
0xB: -8dB
0xC: -9dB
0xD: -10dB
0xE: -11dB
0xF: -12dB
Table 33. Right Record Path Digital Gain Configuration Register
ADDRESS: 0x18
BIT
NAME
TYPE
POR
7
—
—
—
6
5
0
AVRG[2:0]
R/W
0
4
0
3
0
2
0
1
AVR[3:0]
0
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R/W
1
1
DESCRIPTION
—
Right Record Path Digital Coarse Gain Configuration
000 : 0dB
010 : +12dB
100 : +24dB
001 : +6dB
011 : +18dB
101 : +30dB
110 : +36dB
111 : +42dB
Right Record Path Digital Fine Adjust Gain Configuration
0x0: +3dB
0x4: -1dB
0x8: -5dB
0x1: +2dB
0x5: -2dB
0x9: -6dB
0x2: +1dB
0x6: -3dB
0xA: -7dB
0x3: +0dB
0x7: -4dB
0xB: -8dB
0xC: -9dB
0xD: -10dB
0xE: -11dB
0xF: -12dB
Maxim Integrated │ 103
MAX98090
Ultra-Low Power Stereo Audio Codec
Digital Audio Interface (DAI) Configuration
the device is configured to slave mode, the internal PLL
quickly locks onto the external LRCLK frequency.
The digital audio interface (DAI) contains two primary sections (Figure 15). The first is the clock control and configuration section. The device supports both master and slave
mode operation, can accept a master clock of either 256
x fS or ranging from 10MHz to 60MHz, and can be configured for any digital audio sampling rate (fS) from 8kHz to
96kHz. When the device is configured as the digital audio
master, a variety of operating modes are available. These
include a simple quick configuration mode, exact integer
sampling mode, and a manual clock divider mode. When
MCLK
LRCLK
The second section is the digital audio data path control
and signal routing. This section supports a variety of stereo data path configurations including serial audio input
and output, audio loop through from the record to playback paths, and audio loop back from the serial data input
to the serial data output. The serial data interface also
supports several standard digital audio formats (PCM)
including I2S, left justified, right justified, and time division
multiplexed (TDM).
SDOUT
BCLK
SDIN
MAX98090
DATA OUTPUT
ENABLE
SDOEN
HIZOFF
LTEN
MAS
PRESCALED
CLOCK
GENERATION
PCLK
FRAME
CLOCK
BCI
WCI
1
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
BIT
CLOCK
USE_MI
NI[14:0]
MI[14:0]
PSCLK[1:0]
OUTPUT SHIFT
REGISTER
LOOP
BACK MUX
CLOCK GENERATION AND DISTRIBUTION
FREQ[3:0]
0
BSEL[2:0]
LBEN SDIEN
DAI: DATA PATH
RECORD PATH
CLOCKS
L/R AUDIO
OUTPUT
RECORD PATH DSP
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
1
DMONO
DAI: CLOCK CONTROL
AND CONFIGURATION
DIGITAL MIC CLOCK
CONFIGURATION
RJ, DLY
WS[1:0]
0
LOOP
THROUGH
MUX
PLAYBACK PATH
CLOCKS
PLAYBACK
INPUT MIXER
L/R AUDIO
INPUT
PLAYBACK PATH DSP
Figure 15. Simplified Digital Audio Interface Block Diagram
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Maxim Integrated │ 104
MAX98090
Ultra-Low Power Stereo Audio Codec
DAI Clock Control and Configuration
The device digital audio interface supports both master
and slave mode operation (Table 35). To properly time
the serial data input (SDIN) and output (SDOUT), the
DAI requires both a left-right frame clock (LRCLK) and a
bit clock (BCLK). In master mode, the device uses one
of several modes to generate both LRCLK and BCLK
from the internal prescaled master clock (PCLK). In slave
mode however, both LRCLK and BCLK must be externally provided.
The clock control and configuration section is one of the
two major blocks in the digital audio interface (Figure 16).
This section is responsible for accepting and scaling the
device master clock, for internal digital clock generation,
and for digital audio interface data clocking and timing.
The device can accept an external master clock (MCLK)
with a frequency ranging from 10MHz to 60MHz. However,
for digital operation, signal processing, and data conversion the device requires an internal clock between 10MHz
and 20MHz. To generate an internal master clock within
this frequency range, an internal clock divider is used
(Table 34). The internal clock divider can be set to frequency divide MCLK by a factor 1, 2, or 4 to create the
internal prescaled master clock (PCLK). PCLK is then
used, either directly or through additional divider/multiplier
blocks, to clock all internal digital sections.
Master Mode Clock Configuration
When the device is configured as the digital audio master, the frame clock (LRCLK) and bit clock (BCLK) are
configured as outputs and the device uses the internal
prescaled master clock (PCLK) to create them.
If no clock outputs or unexpected clock outputs are measured on LRCLK and/or BCLK, verify that the device is not
in shutdown and that all three clocks are configured correctly. If the master clock prescale value is not selected
(PSCLK[1:0]), the clock ratio is not fully configured (operating mode), or if the bit clock rate is not set (BSEL[2:0])
The digital audio interface signal paths support any sampling rate from 8kHz to 96kHz. The device has only a single
DAI, and as a result both the record (output) and playback
(input) digital audio paths use the same sampling rate.
MCLK
LRCLK
BCLK
SDOUT
SDIN
MAX98090
DATA OUTPUT
ENABLE
SDOEN
HIZOFF
LTEN
MAS
PRESCALED
CLOCK
GENERATION
PCLK
FRAME
CLOCK
BCI
WCI
1
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
BIT
CLOCK
USE_MI
NI[14:0]
MI[14:0]
PSCLK[1:0]
OUTPUT SHIFT
REGISTER
LOOP
BACK MUX
CLOCK GENERATION AND DISTRIBUTION
FREQ[3:0]
0
BSEL[2:0]
LBEN SDIEN
DAI: DATA PATH
RECORD PATH
CLOCKS
L/R AUDIO
OUTPUT
RECORD PATH DSP
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
1
DMONO
DAI: CLOCK CONTROL
AND CONFIGURATION
DIGITAL MIC CLOCK
CONFIGURATION
RJ, DLY
WS[1:0]
0
LOOP
THROUGH
MUX
PLAYBACK PATH
CLOCKS
PLAYBACK
INPUT MIXER
L/R AUDIO
INPUT
PLAYBACK PATH DSP
Figure 16. DAI Clock Control and Configuration Section
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Maxim Integrated │ 105
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 34. System Master Clock (MCLK) Prescaler Configuration Register
ADDRESS: 0x1B
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
0
PSCLK[1:0]
R/W
4
0
Master Clock (MCLK) Prescaler Configuration
00: Internal master clock generation disabled
01: fPCLK = fMCLK/1, 10MHz ≤ fMCLK ≤ 20MHz
10: fPCLK = fMCLK/2, 20MHz < fMCLK ≤ 40MHz
11: fPCLK = fMCLK/4, 40MHz < fMCLK ≤ 60MHz
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
Table 35. Master Mode Clock Configuration Register
ADDRESS: 0x21
BIT
NAME
TYPE
DESCRIPTION
POR
Master Mode Enable
0: Slave mode
(LRCLK/BCLK are inputs and accept external clock sources).
1: Master mode
(LRCLK/BCLK are outputs and timing signals are generated internally).
7
MAS
R/W
0
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
1
0
BSEL[2:0]
0
R/W
0
0
Bit Clock (BCLK) Configuration (Master Mode/Slave Right Justified Only)
000: Bit clock disabled
100: fBCLK = fPCLK/2
001: fBCLK = 32 x fS
101: fBCLK = fPCLK/4
010: fBCLK = 48 x fS
110: fBCLK = fPCLK/8
011: fBCLK = 64 x fS
111: fBCLK = fPCLK/16
then no valid clock output is present. In addition to this,
the device does not generate any clocks unless at least
one valid digital audio data path is enabled (ADC record,
DAC playback, digital microphone input, etc.).
In master mode, the device uses two integer values (NI
and MI) as a multiplier and divider (respectively) to scale
PCLK into LRCLK. BCLK is then created either from a
PCLK divider or from an LRCLK multiplier (Table 35).
Based on the oversampling rate selected (OSR, see the
ADC Functional Configuration section), and the config-
www.maximintegrated.com
ured NI/MI ratio, the output LRCLK frequency is calculated with the following relationship:
NI
f LRCLK
= f PCLK ×
MI × OSR
This expression illustrates that in master mode, the relationship between LRCLK and PCLK frequency (as well as
BCLK) is based on an integer ratio. As a result, any cycle
to cycle jitter or absolute frequency variation in MCLK
is translated first into PCLK and then into LRCLK (and
BCLK) based on the selected clock ratios.
Maxim Integrated │ 106
MAX98090
Ultra-Low Power Stereo Audio Codec
In master mode, the device provides three clock operating
modes. In reality all three modes operate in exactly the
same manner (using an internal MI and NI ratio to create
LRCLK). However, the first two modes will internally set
NI and MI automatically and are provided as configuration shortcuts for commonly used PCLK to LRCLK ratios.
The three operating modes are detailed below, and are
presented in order of activation priority.
Quick Configuration Mode
In quick configuration mode, the master clock frequency
(Table 36) and sample rate (Table 37) are selected from
a list of commonly used frequencies. Only a single bit in
each quick setup register can be enabled at any given
time. Quick configuration mode is activated anytime
that both a master clock frequency quick setup bit and
a sample rate quick setup bit are concurrently enabled.
Once enabled, this mode supersedes both of the other
operating modes and an internal preset ratio for NI and
MI is used to create LRCLK. As a result, when Quick
Configuration Mode is enabled the exact integer mode
settings (Table 39), and the manual ratio mode settings
(Tables 40 to 43) are preserved but ignored. If this mode
is later disabled, the preserved settings of any active
lower precedence modes reassert.
To ensure that the DSP is optimally configured and that all
timing requirements are met, when using quick configuration mode the master clock divider (PSCLK, Table 34),
digital filters (MODE, Table 27), and ADC oversampling
rate (OSR128, Table 5) are automatically configured.
While in quick configuration mode these registers are
Table 36. Master Clock Quick Setup Register
ADDRESS: 0x04
BIT
DESCRIPTION
NAME
TYPE
POR
7
26M
R/W
0
Setup device for operation with a 26MHz master clock (MCLK).
6
19P2M
R/W
0
Setup device for operation with a 19.2MHz master clock (MCLK).
5
13M
R/W
0
Setup device for operation with a 13MHz master clock (MCLK).
4
12P288M
R/W
0
Setup device for operation with a 12.288MHz master clock (MCLK).
3
12M
R/W
0
Setup device for operation with a 12MHz master clock (MCLK).
2
11P2896M
R/W
0
Setup device for operation with a 11.2896MHz master clock (MCLK).
1
—
—
—
0
256FS
R/W
0
—
Setup device for operation with a 256 x fS MHz master clock (MCLK)
Table 37. Sample Rate Quick Setup Register
ADDRESS: 0x05
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
SR_96K
R/W
0
Setup clocks and filters for a 96kHz sample rate.
4
SR_32K
R/W
0
Setup clocks and filters for a 32kHz sample fate.
3
SR_48K
R/W
0
Setup clocks and filters for a 48kHz sample rate.
2
SR_44K1
R/W
0
Setup clocks and filters for a 44.1kHz sample rate.
1
SR_16K
R/W
0
Setup clocks and filters for a 16kHz sample rate.
0
SR_8K
R/W
0
Setup clocks and filters for an 8kHz sample rate.
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Maxim Integrated │ 107
MAX98090
Ultra-Low Power Stereo Audio Codec
fixed and cannot be manually changed. In this mode,
when the sample rate is set to 8kHz or 16kHz, voice filters
(IIR) are automatically selected and the ADC oversampling rate is fixed to 128. For any other selected sample
rate, music filters (FIR) are selected and the ADC oversampling rate is configured to insure that the pre-scaled
master clock frequency is greater than or equal to 256 x
fS. If fPCLK ≥ 256 x fS then the oversampling rate (OSR) is
set to 128, otherwise OSR is set to 64. Table 38 provides
a complete lookup table for the resulting quick configuration mode settings.
Exact Integer Mode
In exact integer mode, the master clock frequency and sample rate can be set to one of eight preprogrammed combinations (Table 39). There are four different available master clock frequencies (12MHz/13MHz/16MHz/19.2MHz),
each of which can be selected with a sampling rate (fS)
of either 8kHz or 16kHz. Once a configuration is selected,
the NI and MI bits are internally programmed to the correct ratio. These combinations are primarily intended for
standard or wideband voice applications.
Table 38. Quick Configuration Mode Lookup
SELECTED SAMPLE RATE (kHz)
SELECTED MASTER CLOCK
FREQUENCY
8
16
32
44.1
96
DIVIDER
fPCLK
26MHz
2
13Mhz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
19.2MHz
1
19.2Mhz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
13MHz
1
13Mhz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
12.288MHz
1
12.288Mhz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
12MHz
1
12MHz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
11.2896MHz
1
11.2896MHz
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
OSR = 64
1
256 x fS
OSR = 128
OSR = 128
OSR = 128
OSR = 128
OSR = 64
—
2
128 x fS
—
—
—
—
—
OSR = 64
256 x fS
VOICE FILTER (IIR)
48
fMCLK
MUSIC FILTER (FIR)
Table 39. Clock Mode Configuration Register
ADDRESS: 0x1C
BIT
NAME
TYPE
POR
DESCRIPTION
5
0
4
0
Exact Integer Sampling Frequency (LRCLK) Configuration
Configure the DAI for specific PCLK to LRCLK ratios for fS = 8kHz/16kHz operation
(voice modes). Any setting other than 0x0 overrides manual ratio mode settings.
0000: Disabled 1XXX: Enabled
Other combinations are reserved
When enabled, the following PCLK to LRCLK ratios are available:
1000: fPCLK = 12MHz, fLRCLK = 8kHz
1001: fPCLK = 12MHz, fLRCLK = 16kHz
1010: fPCLK = 13MHz, fLRCLK = 8kHz
1011: fPCLK = 13MHz, fLRCLK = 16kHz
1100: fPCLK = 16MHz, fLRCLK = 8kHz
1101: fPCLK = 16MHz, fLRCLK = 16kHz
1110: fPCLK = 19.2MHz, fLRCLK = 8kHz
1111: fPCLK = 19.2MHz, fLRCLK = 16kHz
7
0
6
0
FREQ[3:0]
R/W
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
USE_MI
R/W
0
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Use MI[15:0] in Addition to NI[14:0] to set an Accurate Frequency Ratio
0 : MI = 65536; NI = (fLRCLK / fPCLK) x 65536 x 96
1 : MI is set to the value of MI[15:0] (Table 42 and Table 43).
Maxim Integrated │ 108
MAX98090
Ultra-Low Power Stereo Audio Codec
When FREQ[3:0] register is set to 0 (FREQ[3:0] = 0000),
exact integer mode is disabled. When the MSB is set to 1
(FREQ[3:0] = 1XXX) exact integer mode is enabled and
the remaining bits determine which setting is selected
(Table 39). If exact integer mode is enabled, the manual
ratio mode settings (Tables 40 to 43) are preserved but
ignored. However, if this mode is later disabled, the
manual ratio mode settings reassert.
Manual Ratio Mode
In manual ratio mode, the NI and MI registers (Table 40
to Table 43) are directly programmed to set up the clock
ratio. Manual ratio mode is only active when the quick
Configuration and Exact Integer Modes are disabled. In
manual ratio mode, if USE_MI (Table 39) is set to 0, MI
is fixed at its maximum value of 0xFFFF (65536) and
the programmed value has no effect. For optimal performance (especially with any noninteger PCLK to LRCLK
ratio), set USE_MI to 1 and calculate both MI and NI.
To calculate the appropriate NI and MI value, use the following method:
1) Choose the over sampling rate (OSR). If fPCLK < 256
x fLRCLK, then OSR must be set to 64. Otherwise,
OSR can be set to either 128 or 64. For optimal performance, choose OSR = 128 when possible.
2)Calculate the oversampling frequency using the
LRCLK frequency, and the selected oversampling rate:
fOSR = fLRCLK x OSR.
3) Calculate MI using the prescaled master clock frequency, and the greatest common denominator (GCD)
of the prescaled master clock frequency and the calculated oversampling frequency:
4) Calculate NI using the calculated oversampling frequency and MI value:
NI = fOSR x MI/fPCLK
Slave Mode Clock Configuration
When the device is configured as a digital audio slave, the
frame clock (LRCLK) and bit clock (BCLK) are configured
as external inputs. These inputs accept an externally
generated frame and bit clock, and then an internal PLL
determines the correct PCLK to LRCLK frequency ratio.
Within a few LRCLK cycles, the internal PLL is locked
onto the clock ratio and then automatically programs the
internal divider ratio appropriately. The external clocks
must not violate the minimum PCLK to LRCLK frequency
ratio. See the Input Clock Characteristics table. If the
minimum clock ratio is not satisfied, the FlexSound DSP
will not have enough clock cycles to operate correctly. As
a result, the audio quality and specifications are severely
compromised.
In slave mode, the clock generation register settings have
no effect (quick configuration, exact integer, and manual
ratio mode settings have no effect). The correct MCLK to
PCLK scaling factor, mode (voice/audio), and oversampling rate still need to be programmed. However, all other
clock configuration settings are for master mode only. The
only exception to this is when the digital audio format is
set to slave mode operation with right justified data. In
this configuration, the BCLK setting (BSEL[2:0], Table 35)
is used to determine the number of leading padding bits
(BCLK cycles) to insert (skip) before the data transmission/receiving in each frame.
MI = fPCLK /GCD(fPCLK, fOSR)
Table 40. Manual Clock Ratio Configuration Register (NI MSB)
ADDRESS: 0x1D
BIT
NAME
TYPE
POR
7
—
—
—
6
0
5
0
4
0
3
NI[14:8]
R/W
0
2
0
1
0
0
0
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DESCRIPTION
—
Upper half of the PLL N value used in master mode clock generation
to calculate the frequency ratio (manual ratio master mode).
Maxim Integrated │ 109
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 41. Manual Clock Ratio Configuration Register (NI LSB)
ADDRESS: 0x1E
BIT
NAME
TYPE
POR
7
0
6
0
5
0
4
3
NI[7:0]
R/W
0
0
2
0
1
0
0
0
DESCRIPTION
Lower half of the PLL N value used in master mode clock generation
to calculate the frequency ratio (manual ratio master mode).
Table 42. Manual Clock Ratio Configuration Register (MI MSB)
ADDRESS: 0x1F
BIT
NAME
TYPE
POR
7
0
6
0
5
0
4
3
MI[15:8]
R/W
0
0
2
0
1
0
0
0
DESCRIPTION
Upper half of the PLL M value used in master mode clock generation to
calculate an accurate noninteger frequency ratio (manual ratio master mode).
Table 43. Manual Clock Ratio Configuration Register (MI MSB)
ADDRESS: 0x20
BIT
NAME
TYPE
POR
7
0
6
0
5
0
4
3
MI[7:0]
R/W
0
0
2
0
1
0
0
0
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DESCRIPTION
Lower half of the PLL M value used in master mode clock generation to
calculate an accurate noninteger frequency ratio (manual ratio master mode).
Maxim Integrated │ 110
MAX98090
Ultra-Low Power Stereo Audio Codec
DAI Digital Audio Data Path Control
and Routing
for all valid data path combinations are detailed in
Table 44 and are illustrated in Figure 18.
The digital audio data path section supports a variety of
stereo data path configurations and formats (Figure 17).
SDOUT can be configured to go to either a high impedance state or to drive a valid logic level (LSB) after all
data bits have been transmitted. When high impedance
mode is enabled, SDOUT goes to a high-impedance state
quickly after the BCLK edge for the LSB occurs to avoid
potential bus contention. SDIN/loopthrough audio data
can be routed through the playback path input mixer as
either stereo audio data, or as a mono representation of
the input audio data. By default, playback mono mode is
disabled and the left/right input audio data is routed to
the left/right playback channels respectively. If playback
mono mode is enabled, the input audio data channels are
reduced in amplitude by 6dB, mixed together (summed),
and then routed to both the left and right record path
channels. The full list of DAI data path configuration control bits are detailed in Table 45.
The standard configuration is to route either the record
path digital audio output to the serial data output (record
path to SDOUT) or to route the serial data input to the digital audio playback path (SDIN to playback path). These
two primary configurations can be used either individually
or together as needed by the application.
The DAI data path also supports two loop configurations.
Loop back mode takes the digital audio serial data input
and routes it back to the serial data output (SDIN to
SDOUT). Loop through mode allows the record path audio
data output to be looped through to the digital audio playback path (and can be combined with the record path to
SDOUT configuration if desired). The configuration settings
MCLK
LRCLK
BCLK
SDOUT
SDIN
MAX98090
DATA OUTPUT
ENABLE
SDOEN
HIZOFF
LTEN
MAS
PRESCALED
CLOCK
GENERATION
PCLK
FRAME
CLOCK
BCI
WCI
1
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
BIT
CLOCK
USE_MI
NI[14:0]
MI[14:0]
PSCLK[1:0]
OUTPUT SHIFT
REGISTER
LOOP
BACK MUX
CLOCK GENERATION AND DISTRIBUTION
FREQ[3:0]
0
BSEL[2:0]
LBEN SDIEN
DAI: DATA PATH
RECORD PATH
CLOCKS
L/R AUDIO
OUTPUT
RECORD PATH DSP
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
1
DMONO
DAI: CLOCK CONTROL
AND CONFIGURATION
DIGITAL MIC CLOCK
CONFIGURATION
RJ, DLY
WS[1:0]
0
LOOP
THROUGH
MUX
PLAYBACK PATH
CLOCKS
PLAYBACK
INPUT MIXER
L/R AUDIO
INPUT
PLAYBACK PATH DSP
Figure 17. DAI Digital Data Path Configuration
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Maxim Integrated │ 111
MAX98090
Ultra-Low Power Stereo Audio Codec
SDOUT
SDIN
SDOUT
PATH 1:
RECORD
SDOUT
SDIN
SDIN
PATH 3:
FULL DUPLEX
PATH 2:
PLAYBACK
DATA OUTPUT
ENABLE
LOOP
THROUGH
MUX
DATA OUTPUT
ENABLE
LOOP
THROUGH
MUX
DATA OUTPUT
ENABLE
LOOP
THROUGH
MUX
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
LOOP
BACK
MUX
DATA INPUT
ENABLE
LOOP
BACK
MUX
DATA INPUT
ENABLE
LOOP
BACK
MUX
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
L/R AUDIO
(RECORD)
L/R AUDIO
(PLAYBACK)
SDOUT
PLAYBACK
INPUT MIXER
PLAYBACK
INPUT MIXER
L/R AUDIO
(RECORD)
L/R AUDIO
(RECORD)
L/R AUDIO
(PLAYBACK)
SDIN
SDOUT
L/R AUDIO
(PLAYBACK)
SDIN
PATH 5:
RECORD/
LOOP
THROUGH
PATH 4:
PLAYBACK/
LOOP BACK
DATA OUTPUT
ENABLE
LOOP
THROUGH
MUX
DATA OUTPUT
ENABLE
LOOP
THROUGH
MUX
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
LOOP
BACK
MUX
DATA INPUT
ENABLE
LOOP
BACK
MUX
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
L/R AUDIO
(RECORD)
L/R AUDIO
(PLAYBACK)
PLAYBACK
INPUT MIXER
L/R AUDIO
(RECORD)
L/R AUDIO
(PLAYBACK)
Figure 18. Digital Audio Interface (DAI) Data Path Configurations
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Maxim Integrated │ 112
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 44. Digital Audio Interface (DAI) Data Path Configurations
DAI DATA PATH CONFIGURATION
PATH
SDOEN
SDIEN
LTEN
LBEN
—
DAI data path disabled
DESCRIPTION
0
0
0
0
1
Record path to serial data output
1
0
0
0
2
Serial data input to playback path
0
1
0
0
3
Record path to serial data output/serial data input to
playback path
1
1
0
0
4
Serial data input loop back to serial data output
1
1
0
1
5
Record path to serial data output
and loop through to playback path
1
1
1
0
—
Invalid configurations
All other combinations
Table 45. Digital Audio Interface (DAI) Input/Output Configuration Register
ADDRESS: 0x25
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
LTEN
R/W
0
Enables Data Loop Through (Playback Path to Record Path)
1: ADC to DAC loop-through enabled.
0: ADC to DAC loop-through disabled.
4
LBEN
R/W
0
Enables Data Loop Back (SDIN to SDOUT)
1: DAI SDIN used as SDOUT data source.
0: ADC used as SDOUT data source.
0
Enables Playback Mono Mode (SDIN L/2 + R/2 to Playback Path)
1: The left- and right-channel SDIN audio input data are reduced in gain by 6dB,
mixed together (summed), and routed to both the left and right record paths.
0: The left- and right-channel SDIN audio input data are routed to the left and
right record path channels.
3
DMONO
R/W
2
HIZOFF
R/W
0
Disables Hi-Z Mode for SDOUT
1: SDOUT drives a valid logic level after all data bits have been transmitted.
0: SDOUT goes to a high-impedance state after all data bits have been
transmitted, allowing the SDOUT bus to be shared by other devices.
1
SDOEN
R/W
0
Enables the Serial Data Output (SDOUT)
1: Serial data output enabled.
0: Serial data output disabled.
0
SDIEN
R/W
0
Enables the Serial Data Input (SDIN/Loop-Through)
1: Serial data input enabled.
0: Serial data input disabled.
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Maxim Integrated │ 113
MAX98090
Ultra-Low Power Stereo Audio Codec
DAI Digital Audio Data Format
The serial data interface supports multiple pulse code modulated (PCM) digital audio formats including I2S, left justified, right justified, and time division multiplexed (TDM). If
TDM mode is enabled, it takes precedence and the DAI
data is in TDM format. In this case, all non-TDM digital
audio data format configuration registers have no effect.
If TDM mode is disabled, then the data format is determined by the configuration selected by the control bits
detailed in Table 46. These settings can be used to
change the DAI data format to several supported standards such as I2S (Figure 19), left justified (Figure 20)
or right justified (Figure 21). In addition, the configuration
settings can be enabled or disabled independently, allowing the device to support many nonstandard data format
variations.
Table 46. Digital Audio Interface (DAI) Format Configuration Register
ADDRESS: 0x22
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
0
Configures the DAI for Right Justified Mode (No Data Delay)
0: Left justified mode enabled with optional data delay.
1: Right justified mode enabled. DLY register is not used and BSEL[2:0] is used
to determine the timing (see the DAI Clock Control and Configuration section for
details).
Note: TDM has priority over all other data formats.
0
Configures the DAI for Frame Clock (LRCLK) Inversion
TDM = 0:
1: Right-channel data is transmitted while LRCLK is low.
0: Left-channel data is transmitted while LRCLK is low.
TDM = 1:
0: Start of a new frame is signified by the rising edge of the LRCLK pulse.
1: Start of a new frame is signified by the falling edge of the LRCLK pulse.
0
Configures the DAI for Bit Clock (BCLK) Inversion
1: SDIN is accepted on the falling edge of BCLK.
0: SDIN is accepted on the rising edge of BCLK.
Master Mode:
1: LRCLK transitions occur on the rising edge of BCLK.
0: LRCLK transitions occur on the falling edge of BCLK.
0
Configures the DAI for Data Delay (I2S Standard)
1: The most significant bit of an audio word is latched at the second BCLK edge
after the LRCLK transition.
0: The most significant bit of an audio word is latched at the first BCLK edge after
the LRCLK transition.
Set DLY = 1 to conform to the I2S standard. DLY is only effective when TDM = 0.
5
4
3
2
RJ
WCI
BCI
DLY
R/W
R/W
R/W
R/W
1
0
WS[1:0]
0
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R/W
0
DAI Input Data Word Size (TDM = 0)
If RJ = 1:
00: 16 bits 01: 20 bits
10: 24 bits If RJ = 0:
00: 16 bits 01, 10, 11: 20 bits
11: Reserved
Maxim Integrated │ 114
MAX98090
Ultra-Low Power Stereo Audio Codec
I2S MODE (TDM = 0, WCI = 0, BCI = 0, DLY = 1, RJ = 0, WS[1:0] = 00, HIZOFF = 0)
LRCLK
RIGHT
LEFT
HIZ
SDOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 19. DAI Timing for I2S Data Format
LEFT JUSTIFIED MODE – STANDARD (TDM = 0, WCI = 1, BCI = 0, DLY = 0, RJ = 0, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED MODE – LRLCK INVERTED (TDM = 0, WCI = 0, BCI = 0, DLY = 0, RJ = 0, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED MODE – BCLK INVERTED (TDM = 0, WCI = 1, BCI = 1, DLY = 0, RJ = 0, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 20. DAI Timing for Left Justified Data Formats
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Maxim Integrated │ 115
MAX98090
Ultra-Low Power Stereo Audio Codec
RIGHT JUSTIFIED MODE – STANDARD (TDM = 0, WCI = 1, BCI = 0, DLY = 0, RJ = 1, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT JUSTIFIED MODE – LRCLK INVERTED (TDM = 0, WCI = 0, BCI = 0, DLY = 0, RJ = 1, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT JUSTIFIED MODE – BCLK INVERTED (TDM = 0, WCI = 1, BCI = 1, DLY = 0, RJ = 1, WS[1:0] = 00, HIZOFF = 0)
LRCLK
SDOUT
RIGHT
LEFT
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0
HIZ
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIZ
BCLK
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 21. DAI Timing for Right Justified Data Formats
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Maxim Integrated │ 116
MAX98090
Ultra-Low Power Stereo Audio Codec
TDM Mode Data Format
If TDM mode is enabled (Table 47), the register settings
in Table 39 have no effect. TDM mode supports up to four
mono audio time slots in each frame. However, internally,
the device only has two digital audio channels (left and
right) that can be assigned to any two of the four available
time frames (Table 48). The remaining two time slots
remain free for another device to utilize. A data delay can
be set individually for each time frame, and when operating in master mode the frame sync pulse can be set to
transmit for either a single bit or an entire word in length.
TDM mode timing for common configuration options is
detailed in Figure 22.
Table 47. Digital Audio Interface (DAI) TDM Control Register
ADDRESS: 0x23
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
FSW
R/W
0
Configures the DAI Frame Sync Pulse Width (TDM = 1 and MAS = 1)
1: Frame sync pulse has a 50% duty cycle.
0: Frame sync pulse is one bit wide.
Note: In slave mode, the device accepts a frame sync pulse width up to
frame width - 1.
0
TDM
R/W
0
Enable for Time Division Multiplex (TDM) Mode
1: Enable TDM mode and configures the DAI to transmit and receive TDM data.
0: Disable TDM mode.
Table 48. Digital Audio Interface (DAI) TDM Format Register
ADDRESS: 0x24
BIT
7
6
NAME
TYPE
SLOTL[1:0]
R/W
SLOTR[1:0]
R/W
POR
0
0
DESCRIPTION
Selects the Time Slot to use for Left-Channel Data in TDM Mode
00: Time slot 1 10: Time slot 3
01: Time slot 2 11: Time slot 4
0
Selects the Time Slot to use for Right-Channel Data in TDM Mode
00: Time slot 1 10: Time slot 3
01: Time slot 2 11: Time slot 4
3
0
Enables data delay for slot 4 in TDM mode.
2
0
Enables data delay for slot 3 in TDM mode.
0
Enables data delay for slot 2 in TDM mode.
0
Enables data delay for slot 1 in TDM mode.
5
4
1
SLOTDLY[3:0]
0
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R/W
0
Maxim Integrated │ 117
MAX98090
Ultra-Low Power Stereo Audio Codec
TDM MODE WITH SINGLE BIT SYNC PULSE (TDM = 1, WCI = 0, BCI = 1, FSW = 0, WS[1:0] = 00, HIZOFF = 0, SLOTL[1:0] = 00, SLOTR[1:0] = 01)
LRCLK
SDOUT
HI-Z
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
HI-Z
BCLK
SDIN
TDM MODE WITH WORD LENGTH SYNC PULSE (TDM = 1, WCI = 0, BCI = 1, FSW = 1, WS[1:0] = 00, HIZOFF = 0, SLOTL[1:0] = 00, SLOTR[1:0] = 01)
LRCLK
SDOUT
HI-Z
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
HI-Z
BCLK
SDIN
TDM MODE WITH HI-Z MODE DISABLED (TDM = 1, WCI = 0, BCI = 1, FSW = 0, WS[1:0] = 00, HIZOFF = 1, SLOTL[1:0] = 00, SLOTR[1:0] = 01)
LRCLK
SDOUT
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCLK
SDIN
TDM MODE USING SLOTS 2 AND 3 (TDM = 1, WCI = 0, BCI = 1, FSW = 0, WS[1:0] = 00, HIZOFF = 0, SLOTL[1:0] = 10, SLOTR[1:0] = 11)
LRCLK
HI-Z
SDOUT
32 CYCLES
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
L15 L14 L13 L12 L11 L10 L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
HI-Z
BCLK
SDIN
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM MODE WITH 4 SLOTS (TDM = 1, WCI = 0, BCI = 1, FSW = 0, WS[1:0] = 00, HIZOFF = 0, SLOTL[1:0] = 00, SLOTR[1:0] = 01)
LRCLK
SDOUT
16 CYCLES
HI-Z
16 CYCLES
L
L
L
L
L
L
L
L
R
R
R
R
L
L
L
L
L
L
L
L
R
R
R
R
R
16 CYCLES
R
R
R
R
R
16 CYCLES
HI-Z
BCLK
SDIN
R
R
Figure 22. DAI Timing for TDM Data Format
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Maxim Integrated │ 118
MAX98090
Ultra-Low Power Stereo Audio Codec
Audio Playback Path
The device playback path has two channels (left and
right) and can accept digital audio input from the DAI
and/or the record path sidetone. The digital audio is then
routed through several stages of FlexSound DSP followed
by the digital to analog converter (Figure 23).
Playback Path FlexSound DSP
The first playback path section features the Maxim
FlexSound DSP stages. The first stage accepts and mixes
the DAI input with the record path sidetone (if enabled),
and contains separate digital gain and digital level control
stages. This stage is followed by three stereo DSP stages
including a 7-band parametric equalizer, a dynamic range
control section (DRC), and a digital filter stage. The play-
L/R ST
LEVEL
back path digital output is then routed into the DAC where
it is converted back to analog before being routed to the
analog output mixers.
Playback Path Digital Gain and Level Control
The stereo playback path DSP includes separate digital
gain and level control stages (Figure 24). Unlike the
record path, both playback path channels (left and right)
share the same digital gain and level control settings. The
coarse digital gain stage accepts its input from the DAI
digital data output and can be set from 0dB to +18dB in
6dB increments. The fine adjust, level control stage input
is the summation of the coarse gain stage output with the
record path sidetone signal. It can be adjusted from -15dB
to 0dB in 1dB increments (Table 49). The playback path
gain and level control stage also include a mute enable.
FLEXSOUND
TECHNOLOGY DSP
SIDETONE FROM
RECORD PATH
DALEN
LEFT PLAYBACK PATH
DVST[3:0]
LEFT
GAIN
DAI
DVG[1:0]
RIGHT
GAIN
LEFT
SIDETONE
DSTS[1:0]
RIGHT
SIDETONE
LEFT
LEVEL
DVM
DV[3:0]
RIGHT
LEVEL
LEFT 7-BAND
PARAMETRIC
EQUALIZER
LEFT ALC:
AUTOMATIC
LEVEL CONTROL
LEFT
FILTERS
EQ_BANDEN
DVEQ[3:0]
EQCLP
B0_EQ_[23:0]
B1_EQ_[23:0]
B2_EQ_[23:0]
A1_EQ_[23:0]
A2_EQ_[23:0]
DRCEN
DRCG[4:0]
DRCRLS[2:0]
DRCATK[2:0]
DRCCMP[2:0]
DRCTHC[4:0]
DRCEXP[2:0]
DRCTHE[4:0]
MODE
DHPF
RIGHT 7-BAND
PARAMETRIC
EQUALIZER
RIGHT ALC:
AUTOMATIC
LEVEL CONTROL
RIGHT
FILTERS
DAC
LEFT
DACHP
PERFMODE
TO THE
ANALOG
OUTPUT
MIXERS
DAC
RIGHT
RIGHT PLAYBACK PATH
DAREN
Figure 23. Playback Path Block Diagram
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Maxim Integrated │ 119
MAX98090
Ultra-Low Power Stereo Audio Codec
L/R ST
LEVEL
FLEXSOUND
TECHNOLOGY DSP
SIDETONE FROM
RECORD PATH
DALEN
DVST[3:0]
LEFT PLAYBACK PATH
LEFT
SIDETONE
LEFT
GAIN
DAI
DSTS[1:0]
DVG[1:0]
RIGHT
SIDETONE
RIGHT
GAIN
LEFT
LEVEL
DVM
DV[3:0]
RIGHT
LEVEL
LEFT 7-BAND
PARAMETRIC
EQUALIZER
LEFT ALC:
AUTOMATIC
LEVEL CONTROL
LEFT
FILTERS
EQ_BANDEN
DVEQ[3:0]
EQCLP
B0_EQ_[23:0]
B1_EQ_[23:0]
B2_EQ_[23:0]
A1_EQ_[23:0]
A2_EQ_[23:0]
DRCEN
DRCG[4:0]
DRCRLS[2:0]
DRCATK[2:0]
DRCCMP[2:0]
DRCTHC[4:0]
DRCEXP[2:0]
DRCTHE[4:0]
MODE
DHPF
RIGHT 7-BAND
PARAMETRIC
EQUALIZER
RIGHT ALC:
AUTOMATIC
LEVEL CONTROL
RIGHT
FILTERS
DAC
LEFT
DACHP
PERFMODE
TO THE
ANALOG
OUTPUT
MIXERS
DAC
RIGHT
RIGHT PLAYBACK PATH
DAREN
Figure 24. Playback Path Sidetone and Level Control
Table 49. Playback Gain and Level Configuration Register
ADDRESS: 0x27
DESCRIPTION
BIT
NAME
TYPE
7
DVM
R/W
0
Enables the playback path data input mute.
6
—
—
—
—
DVG[1:0]
R/W
5
4
3
2
1
DV[3:0]
0
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R/W
POR
0
Playback Path Coarse Adjust Gain Configuration
00: 0dB
10: +12dB
01: +6dB
11: +18dB
0
Playback Path Fine Level Control Configuration
0
0
0
0
0x0: 0dB 0x1: -1dB
0x2: -2dB
0x3: -3dB
0x4: -4dB
0x5: -5dB 0x6: -6dB 0x7: -7dB
0x8: -8dB
0x9: -9dB 0xA: -10dB 0xB: -11dB
0xC: -12dB
0xD: -13dB
0xE: -14dB
0xF: -15dB
Maxim Integrated │ 120
MAX98090
Ultra-Low Power Stereo Audio Codec
Playback Path 7-Band Parametric Equalizer
The playback path DSP features a 7-band parametric
equalizer with clipping detection and a programmable
pre-attenuation amplifier (Figure 25). Each of the 7 bands
is a full, individually programmable digital biquad filter.
The chosen configuration for any given band applies to
both the left and right playback channels.
L/R ST
LEVEL
The parametric equalizer can be enabled in a 3-band,
5-band, or the full 7-band configuration (Table 50). Once
the parametric equalizer is enabled, the clip detection can be set and the level of preattenuation can be
adjusted from 0dB down to -15dB (denoted AV_EQ, see
Table 51). No single band biquad filter can be set to a gain
greater than ±12dB, to a Q greater than 10, or to below
a minimum fC that varies by filter type. See the Electrical
Characteristics table.
FLEXSOUND
TECHNOLOGY DSP
SIDETONE FROM
RECORD PATH
DALEN
LEFT PLAYBACK PATH
DVST[3:0]
LEFT
GAIN
DAI
DVG[1:0]
RIGHT
GAIN
LEFT
SIDETONE
DSTS[1:0]
RIGHT
SIDETONE
LEFT
LEVEL
DVM
DV[3:0]
RIGHT
LEVEL
LEFT 7-BAND
PARAMETRIC
EQUALIZER
LEFT ALC:
AUTOMATIC
LEVEL CONTROL
LEFT
FILTERS
EQ_BANDEN
DVEQ[3:0]
EQCLP
B0_EQ_[23:0]
B1_EQ_[23:0]
B2_EQ_[23:0]
A1_EQ_[23:0]
A2_EQ_[23:0]
DRCEN
DRCG[4:0]
DRCRLS[2:0]
DRCATK[2:0]
DRCCMP[2:0]
DRCTHC[4:0]
DRCEXP[2:0]
DRCTHE[4:0]
MODE
DHPF
RIGHT 7-BAND
PARAMETRIC
EQUALIZER
RIGHT ALC:
AUTOMATIC
LEVEL CONTROL
RIGHT
FILTERS
DAC
LEFT
DACHP
PERFMODE
TO THE
ANALOG
OUTPUT
MIXERS
DAC
RIGHT
RIGHT PLAYBACK PATH
DAREN
Figure 25. Playback Path DSP
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Maxim Integrated │ 121
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 50. DSP Biquad Filter Enable Register
ADDRESS: 0x41
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
RECBQEN
R/W
0
Enable Biquad Filter in Record Path
0: Biquad filter not used.
1: Biquad filter used in ADC path.
2
EQ3BANDEN
R/W
0
Enable 3-Band EQ in DAC Path (Bands 4–7 Are Not Used)
0: 3-band EQ disabled.
1: 3-band EQ enabled. Only valid if EQ7BANDEN == 0 and EQ5BANDEN == 0.
1
EQ5BANDEN
R/W
0
Enable 5-Band EQ in DAC Path (Bands 6 and 7 Are Not Used)
0: 5-band EQ disabled.
1: 5-band EQ enabled. Only valid if EQ7BANDEN == 0
0
EQ7BANDEN
R/W
0
Enable 7-Band EQ in DAC Path
0: 7-band EQ disabled.
1: 7-band EQ enabled. This makes EQ5BANDEN and EQ3BANDEN redundant.
Table 51. Parametric Equalizer Playback Level Configuration Register
ADDRESS: 0x28
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
EQCLP
R/W
0
Enables DAI Digital Input Equalizer Clipping Detection
1: Equalizer clip detect disabled.
0: Equalizer clip detect enabled.
0
DAI Digital Input Equalizer Attenuation Level Configuration (AV_EQ)
3
2
1
DVEQ[3:0]
0
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R/W
0
0
0
0x0: 0dB 0x1: -1dB
0x2: -2dB
0x3: -3dB
0x4: -4dB
0x5: -5dB 0x6: -6dB 0x7: -7dB
0x8: -8dB
0x9: -9dB 0xA: -10dB 0xB: -11dB
0xC: -12dB
0xD: -13dB
0xE: -14dB
0xF: -15dB
Maxim Integrated │ 122
MAX98090
Ultra-Low Power Stereo Audio Codec
The parametric equalizer coefficients are uninitialized at
power-up, and when used the coefficients should be programmed before the device and equalizer are enabled.
The transfer function for each band is defined as:
H(z) =
B 0 + B 1 × Z −1 + B 2 × Z −2
A 0 + A 1 × Z −1 + A 2 × Z −2
The biquad filter in each band has 5 user programmable
coefficients (B0, B1, B2, A1, and A2), and each individual
coefficient is 3 bytes (24 bits) long (A0 is fixed at 1). They
occupy 15 consecutive registers per band for a total
of 105 consecutive registers for all 7 bands (Table 52).
Each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. The
coefficients are stored using a two’s complement format
where the first 4 bits are the integer portion and the last 20
bits are the decimal portion (which results in an approximate +8 to -8 range for each coefficient).
Table 52. Parametric Equalizer Band N (1–7) Biquad Filter Coefficient Registers
ADDRESS RANGE (BY BAND)
1
2
3
4
5
6
7
0x46
0x55
0x64
0x73
0x82
0x91
0xA0
0x47
0x56
0x65
0x74
0x83
0x92
0xA1
0x48
0x57
0x66
0x75
0x84
0x93
0xA2
0x49
0x58
0x67
0x76
0x85
0x94
0xA3
0x4A
0x59
0x68
0x77
0x86
0x95
0xA4
0x4B
0x5A
0x69
0x78
0x87
0x96
0xA5
0x4C
0x5B
0x6A
0x79
0x88
0x97
0xA6
0x4D
0x5C
0x6B
0x7A
0x89
0x98
0xA7
0x4E
0x5D
0x6C
0x7B
0x8A
0x99
0xA8
0x4F
0x5E
0x6D
0x7C
0x8B
0x9A
0xA9
0x50
0x5F
0x6E
0x7D
0x8C
0x9B
0xAA
0x51
0x60
0x6F
0x7E
0x8D
0x9C
0xAB
0x52
0x61
0x70
0x7F
0x8E
0x9D
0xAC
0x53
0x62
0x71
0x80
0x8F
0x9E
0xAD
0x54
0x63
0x72
0x81
0x90
0x9F
0xAE
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NAME
Equalizer Band N
Coefficient B0
Equalizer Band N
Coefficient B1
Equalizer Band N
Coefficient B2
Equalizer Band N
Coefficient A1
Equalizer Band N
Coefficient A2
TYPE
COEFFICIENT SEGMENT
R/W
B0_N[23:16]
R/W
B0_N[15:8]
R/W
B0_N[7:0]
R/W
B1_N[23:16]
R/W
B1_N[15:8]
R/W
B1_N[7:0]
R/W
B2_N[23:16]
R/W
B2_N[15:8]
R/W
B2_N[7:0]
R/W
A1_N[23:16]
R/W
A1_N[15:8]
R/W
A1_N[7:0]
R/W
A2_N[23:16]
R/W
A2_N[15:8]
R/W
A2_N[7:0]
Maxim Integrated │ 123
MAX98090
Ultra-Low Power Stereo Audio Codec
Playback Path Dynamic Range Control
compression is enabled, if the input signal amplitude
exceeds the compression threshold the gain is reduced
by the chosen compression ratio. This results in a smaller,
compressed output dynamic range relative to the input
dynamic range. When expansion is enabled, the gain is
decreased by the chosen expansion ratio if the input signal amplitude instead falls below the expansion threshold.
This results in a larger, expanded output dynamic range.
The playback path includes a dynamic range control
(DRC) section (Figure 25). The DRC is highly configurable and features digital make-up gain, a dynamic range
compression and expansion, and programmable attack
and release times.
The device dynamic range is determined by the difference
between the full-scale and the RMS noise floor amplitude
of the configured signal path. To avoid performance limiting, the application dynamic range is typically smaller
than the dynamic range of the selected signal path. With
dynamic range control disabled, the input dynamic range
is equal to the output dynamic range (Figure 26). When
DRC DISABLED
DYNAMIC RANGE COMPRESSION
FULL SCALE
0
-40
-60
APPLICATIN OUTPUT
DYNAMIC RANGE
-80
-100
-120
NOISE FLOOR
-140
APPLICATION INPUT
DYNAMIC RANGE
-40
-60
COMPRESSED OUTPUT
DYNAMIC RANGE
-80
COMPRESSION
THRESHOLD = -30dB
RATIO = 2:1
-100
-120
NOISE FLOOR
0
FULL SCALE
0
-20
-140
-140 -120 -100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
DYNAMIC RANGE EXPANSION
FULL SCALE
OUTPUT AMPLITUDE (dBFS)
-20
OUTPUT AMPLITUDE (dBFS)
OUTPUT AMPLITUDE (dBFS)
0
The DRC also features a digital make-up gain control section (Table 54), that can be programmed from 0dB to 12dB
in 1dB increments. To avoid clipping before compression
(during the attack time), the signal cannot at any time
exceed the uncompressed full-scale code. Therefore, the
APPLICATION INPUT
DYNAMIC RANGE
-140 -120 -100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
-20
-40
EXPANDED OUTPUT
DYNAMIC RANGE
-60
-80
EXPANSION
THRESHOLD =
-60dB, RATIO = 1:2
-100
-120
NOISE FLOOR
-140
0
APPLICATION INPUT
DYNAMIC RANGE
-140 -120 -100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
0
Figure 26. Dynamic Range Compression and Expansion
DRC DISABLED
0
AV_PLAYBACK = 0dB (DV[3:0] = 0x0)
0
OUTPUT AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
FULL-SCALE
AV_PLAYBACK = -10dB (DV[3:0] = 0xA)
-20
-40
-60
OUTPUT AMPLITUDE (dBFS)
FULL-SCALE
0
OUTPUT AMPLITUDE (dBFS)
DRC ENABLED
WITH MAKE-UP GAIN
DRC ENABLED
COMPRESSION
THRESHOLD = -30dB
RATIO = 4:1
EXPANSION
THRESHOLD = -60dB
RATIO = 1:2
-80
-100
AV_PLAYBACK = -10dB
(DV[3:0] = 0xA)
-120
-120
-100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
AV_PLAYBACK = -10dB (DV[3:0] = 0xF)
-20
AV_DRC = +10dB
-40
-60
-80
-100
-120
-120
0
FULL-SCALE
-120
-100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
0
-120
-100 -80 -60 -40 -20
INPUT AMPLITUDE (dBFS)
0
Figure 27. DRC Enable and Make-Up Gain
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Maxim Integrated │ 124
MAX98090
Ultra-Low Power Stereo Audio Codec
sum of the digital gain/level control, parametric equalizer
gain, and the DRC make-up gain must not exceed 0dB
total. Figure 27 shows the effect of enabling the DRC with
and without digital make-up gain.
input amplitude increases). The compression threshold
can be configured from -31dB to 0dB. The compression
ratios and a range of thresholds are illustrated in Figure 28.
The low amplitude expansion threshold is used to prevent
background noise from being amplified. When the signal
level drops below the expansion threshold, the DRC
reduces the gain until the signal increases above the
threshold. The expansion ratio can be set to a 1:1, 1:2, or
1:3 ratio while the threshold can be configured from ‑35dB
The DRC features two programmable signal thresholds.
The high amplitude compression threshold is used to
reduce the maximum sustained signal amplitude. The
compression ratio can be set to one of five options from
a 1:1 ratio to an infinite:1 ratio (or flat output amplitude as
DRC ENABLED
-10
-20
-30
COMPRESSION
THRESHOLD = -30dB
RATIO =4:1
-40
-50
-60
FULL SCALE
1:5:1
-10
-20
2:1
COMPRESSION
THRESHOLD = - 30dB
-30
4:1
INF:1
-40
-50
-60
-60
-50
-40
-30
-20
-10
0
1:1
RATIO OPTION
OUTPUT AMPLITUDE (dBFS)
0
OUTPUT AMPLITUDE (dBFS)
OUTPUT AMPLITUDE (dBFS)
0
COMPRESSION RATIO
FULL SCALE
COMPRESSION THRESHOLD
FULL SCALE
THRESHOLD OPTIONS
-10
-20
-30
COMPRESSION
RATION = 4:1
0dB
-5dB
-10dB
-15dB
-20dB
-25dB
-30dB
-40
-50
-60
0
-60
-50
INPUT AMPLITUDE (dBFS)
-40
-30
-20
-10
0
-60
-50
INPUT AMPLITUDE (dBFS)
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
Figure 28. DRC Compression Ratio and Threshold
EXPANSION RATIO
EXPANSION THRESHOLD
-30
-40
-40
-40
-50
-60
EXPANDER
THRESHOLD = -60dB
RATIO = 1:2
-70
-80
-50
-60
-70
-90
-80 -70 -60 -50 -40
INPUT AMPLITUDE (dBFS)
-30
EXPANSION
THRESHOLD = -60dB
RATIO
OPTIONS
-80
-90
-90
OUTPUT AMPLITUDE (dBFS)
-30
OUTPUT AMPLITUDE (dBFS)
OUTPUT AMPLITUDE (dBFS)
DRC ENABLED
-30
1:1
-90
1:2
-60
-70
THRESHOLD
OPTIONS
-80
-90
1:3
-80 -70 -60 -50 -40
INPUT AMPLITUDE (dBFS)
-50
-35dB
-40dB
-45dB
-50dB
EXPANSION
-55dB
RATIO = 1:2 -60dB
-65dB
-30
-90
-80 -70 -60 -50 -40
INPUT AMPLITUDE (dBFS)
-30
Figure 29. DRC Expansion Ratio and Threshold
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Maxim Integrated │ 125
MAX98090
Ultra-Low Power Stereo Audio Codec
COMPRESSION ATTACK TIME (2:1)
AMPLITUDE
INCREASES
COMPRESSION
THRESHOLD
COMPRESSED
AMPLITUDE
ATTACK
TIME
COMPRESSION RELEASE TIME (2:1)
COMPRESSED AMPLITUDE
AMPLITUDE
DECECREASES
RELEASE
TIME
RELEASED AMPLITUDE
Figure 30. DRC Attack and Release Time Waveforms
to ‑66dB. The expansion ratios and a range of threshold
are illustrated in Figure 29.
The DRC provides a wide range of programmable attack
and release times (Table 53). When the compression
is enabled and the signal amplitude increases until the
compression threshold is exceeded, the attack time
determines how quickly the selected compression ratio
is applied. When the signal amplitude decreases and the
compression threshold would no longer be exceeded, the
release time determines how quickly the gain returns to
normal (Figure 30).
When expansion is enabled and the signal amplitude
decreases until it drops below the expansion threshold,
the release time determines how quickly the selected
expansion ratio is applied. When the signal amplitude
increases and the expansion threshold would no longer
be exceeded, the attack time determines how quickly the
gain returns to normal.
The attack and release times are not absolute. They are
instead used to set the rate at which the gain is adjusted
once the signal amplitude is either above or below the
appropriate threshold. Therefore the selected attack/
release times are relative to the ratio of the new signal
amplitude to the selected compression and expansion
thresholds. The values provided in Table 53 all assume
the input signal amplitude changed to exceed the appro-
www.maximintegrated.com
priate threshold by a ratio of 12dB (above for compression
and below for expansion). If the appropriate threshold
is exceeded by a larger or smaller ratio, the attack time
is increased or decreased appropriately. The change is
proportional to the change in ratio in dB. For example,
release time is reduced by 50% for 6dB.
For compression, if the signal amplitude exceeds the
threshold by 12dB, the attack time when entering compression precisely matches the selected configuration.
Likewise, when exiting compression, the release time
is determined by the ratio by which the threshold was
exceeded prior to the amplitude dropping.
Expansion works in exactly the same fashion except for
two differences. The expansion ratio is applied when the
signal amplitude drops below the expansion threshold
(rather than above for compression), and the release time
(rather than attack time) determines how long it takes to
enter expansion (centered at 12dB below the expansion
threshold). Likewise, the attack time is then used when
exiting expansion. In addition, when entering expansion,
the ratio of the initial input amplitude to the expansion
threshold sets a delay before the expansion ratio is
applied. This delay is centered at 12dB above the expansion threshold and is determined by the selected release
time. There is no delay prior to the attack time when exiting expansion.
Maxim Integrated │ 126
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 53. Dynamic Range Control (DRC) Timing Register
ADDRESS: 0x33
DESCRIPTION
BIT
NAME
TYPE
POR
7
DRCEN
R/W
0
PLAYBACK DRC Enable
0: DRC disabled.
1: DRC enabled.
R/W
0
PLAYBACK DRC Release Time Configuration (12dB Relative to Threshold)
R/W
0
R/W
0
—
—
R/W
0
R/W
0
R/W
0
6
5
DRCRLS[2:0]
4
3
—
2
1
DRCATK[2:0]
0
0x0: 8s
0x1: 4s
0x2: 2s
0x3: 1s
0x4: 0.5s
0x5: 0.25s
0x6: 0.125s
0x7: 0.0625s
—
PLAYBACK DRC Attack Time Configuration (12dB Relative to Threshold)
0x0: 0.125ms
0x1: 0.25ms
0x2: 1.25ms
0x3: 2.5ms
0x4: 6.25ms
0x5: 12.5ms
0x6: 25ms
0x7: 50ms
Table 54. Dynamic Range Control (DRC) Gain Configuration Register
ADDRESS: 0x36
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
0
3
0
2
DRCG[4:0]
R/W
0
1
0
0
0
PLAYBACK DRC Make-Up Gain Configuration
0x0: +0dB
0x1: +1dB
0x2: +2dB
0x3: +3dB
0x4: +4dB
0x5: +5dB
0x6: +6dB
0x7: +7dB
0x8: +8dB
0x9: +9dB
0xA: +10dB
0xB: +11dB
0xC: +12dB
0xD: reserved
0xE: reserved
0xF: reserved
Table 55. Dynamic Range Control (DRC) Compressor Register
ADDRESS: 0x34
BIT
NAME
TYPE
DESCRIPTION
POR
5
0
PLAYBACK DRC Compression Ratio Configuration
0x0: 1:1
0x3: 4:1
0x1: 1.5:1
0x4: INF:1
0x2: 2:1
0x5–0x7: Reserved
4
0
PLAYBACK DRC Compression Threshold Configuration
3
0
7
6
2
0
DRCCMP[2:0]
DRCTHC[4:0]
R/W
R/W
0
0
1
0
0
0
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0x00: 0
0x01: -1dB
0x02: -2dB
0x03: -3dB
0x04: -4dB
0x05: -5dB
0x06: -6dB
0x07: -7dB
0x08: -8dB
0x09: -9dB
0x0A: -10dB
0x0B: -11dB
0x0C: -12dB
0x0D: -13dB
0x0E: -14dB
0x0F: -15dB
0x10: -16dB
0x11: -17dB
0x12: -18dB
0x13: -19dB
0x14: -20dB
0x15: -21dB
0x16: -22dB
0x17: -23dB
0x18: -24dB
0x19: -25dB
0x1A: -26dB
0x1B: -27dB
0x1C: -28dB
0x1D: -29dB
0x1E: -30dB
0x1F: -31dB
Maxim Integrated │ 127
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 56. Dynamic Range Control (DRC) Expander Register
ADDRESS: 0x35
BIT
NAME
TYPE
POR
7
—
—
—
DRCEXP[2:0]
R/W
DESCRIPTION
—
0
PLAYBACK DRC Expansion Ratio Configuration
0x0: 1:1
0x2: 1:3
0x1: 1:2
0x3–0x7: Reserved
4
0
PLAYBACK DRC Expansion Threshold Configuration
3
0
0x00: -35dB
0x01: -36dB
0x02: -37dB
0x03: -38dB
0x04: -39dB
0x05: -40dB
0x06: -41dB
0x07: -42dB
6
5
2
DRCTHE[4:0]
R/W
0
0
1
0
0
0
Playback Path Digital Filters
The playback path DSP includes a digital filter stage. One
filter, set with the MODE bit (Table 57), offers the choice
between the IIR voice filters and the FIR music filters.
The IIR filters are optimized for standard (fS = 8kHz) and
wideband (fS = 16kHz) voice applications, while the FIR
filters are optimized for low power operation at higher
audio/music sampling rates. For sampling rates in excess
of 50kHz (fLRCLK > 50kHz), the FIR audio filters must
be used, and the DHF bit should be set to appropriately
scale the FIR interpolation filter. The MODE configuration
selected applies to both channels of both the record and
playback path DSP.
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0x08: -43dB
0x09: -44dB
0x0A: -45dB
0x0B: -46dB
0x0C: -47dB
0x0D: -48dB
0x0E: -49dB
0x0F: -50dB
0x10: -51dB
0x11: -52dB
0x12: -53dB
0x13: -54dB
0x14: -55dB
0x15: -56dB
0x16: -57dB
0x17: -58dB
0x18: -59dB
0x19: -60dB
0x1A: -61dB
0x1B: -62dB
0x1C: -63dB
0x1D: -64dB
0x1E: -65dB
0x1F: -66dB
The playback path DSP also features a DC-blocking filter.
This filter can be used with both the IIR voice and FIR
music filters, and blocks low-frequency (including DC)
input signals outside of the lower end of the audio band.
Digital-to-Analog Converter (DAC)
Configuration
The stereo DAC architecture includes two independent
audio paths, analog outputs that can be routed to any
of the analog output mixers, and two operating modes
(Table 4). One operating mode is optimized for maximum
dynamic performance while the other is optimized for
lower power consumption. Both DAC channels can be
enabled independently, allowing the device to support
both stereo and left or right mono configurations (Table 8).
Maxim Integrated │ 128
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 57. DSP Filter Configuration Register
ADDRESS: 0x26
BIT
NAME
TYPE
DESCRIPTION
POR
7
MODE
R/W
1
Enables the CODEC DSP FIR Music Filters (Default IIR Voice Filters)
0: The codec DSP filters operate in IIR voice mode with stop band frequencies
below the fS/2 Nyquist rate. The voice mode filters are optimized for 8kHz or
16kHz voice application use.
1: The codec DSP filters operate in a linear phase FIR audio mode optimized to
maintain stereo imaging and operate at higher fS rates while utilizing
lower power.
6
AHPF
R/W
0
Enables the Record Path DC-Blocking Filter
0: DC-blocking filter disabled.
1: DC-blocking filter enabled.
5
DHPF
R/W
0
Enables the Playback Path DC-Blocking Filter
0: DC-blocking filter disabled.
1: DC-blocking filter enabled.
4
DHF
R/W
0
Enables the DAC High Sample Rate Mode (LRCLK > 50kHz, FIR Only)
0: LRCLK is less than 50kHz. 8x FIR interpolation filter used.
1: LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
L/R ST
LEVEL
FLEXSOUND
TECHNOLOGY DSP
SIDETONE FROM
RECORD PATH
DALEN
DVST[3:0]
LEFT
GAIN
DAI
DVG[1:0]
RIGHT
GAIN
LEFT PLAYBACK PATH
LEFT
SIDETONE
DSTS[1:0]
RIGHT
SIDETONE
LEFT
LEVEL
DVM
DV[3:0]
RIGHT
LEVEL
LEFT 7-BAND
PARAMETRIC
EQUALIZER
LEFT ALC:
AUTOMATIC
LEVEL CONTROL
LEFT
FILTERS
EQ_BANDEN
DVEQ[3:0]
EQCLP
B0_EQ_[23:0]
B1_EQ_[23:0]
B2_EQ_[23:0]
A1_EQ_[23:0]
A2_EQ_[23:0]
ALCEN
ALCG[4:0]
ALCRLS[2:0]
ALCATK[2:0]
ALCCMP[2:0]
ALCTHC[4:0]
ALCEXP[2:0]
ALCTHE[4:0]
MODE
DHPF
RIGHT 7-BAND
PARAMETRIC
EQUALIZER
RIGHT ALC:
AUTOMATIC
LEVEL CONTROL
RIGHT
FILTERS
DAC
LEFT
DACHP
PERFMODE
TO THE
ANALOG
OUTPUT
MIXERS
DAC
RIGHT
RIGHT PLAYBACK PATH
DAREN
Figure 31. Playback Path Digital-to-Analog Converter
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Maxim Integrated │ 129
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Audio Output Configuration
speakers. The headphone output drivers utilize Maxim’s
DirectDrive architecture with an integrated charge pump,
and provide configurable headphone and headset jack
detection. Each analog audio output driver has a programmable gain input mixer and output amplifier. Each mixer
accepts any combination of signals from the playback DAC,
the analog microphone amplifier, and the line input drivers.
The device features three independent integrated analog
audio output drivers (Figure 32). The receiver/line output
driver can be configured either as a differential receiver/
earpiece output or as a stereo single-ended line output
driver. The stereo speaker output drivers are filterless Class
D differential amplifiers capable of driving both 4Ω and 8Ω
MIXRVCL[5:0]
MIXRVCLG[1:0]
DACL
DACR
RCV/ -12dB TO 0dB
LINE
MIC 2 OUT
LEFT
LINE A MIXER
LINE B
MIC 1
FLEXSOUND
TECHNOLOGY
DSP
DACLEN
DAC
RIGHT
DACHP
PERFMODE
DACREN
DACL
-12dB TO 0dB
RCV/
LINE
OUT
MUX
MIXRVCL[5:0]
MIXRVCLG[1:0]
MIXSPL[5:0]
MIXSPLG[1:0]
DACR
SPK
LEFT
MIC 2
MIXER
LINE A
MIC 1
-12dB TO 0dB
SPEAKER
LEFT PGA
LINE B
-62dB TO 8dB
LINE OUT
RIGHT PGA
DACL
MIC 1
MIC 2
LINE A
SPK
RIGHT
MIXER
DACL
SPVOLL[4:0]
SPLM
SPLEN
SPKLGND
-48dB TO 14dB
SPKLP
SPKLN
6dB
LINE A
HP
LEFT
MIXER
-48dB TO 14dB
SPKRP
SPKRN
6dB
SPVOLR[4:0]
SPLM
SPREN
SPKRGND
HPVOLL[4:0]
HPLM
HPLEN
-12dB TO 0dB
HP
LEFT
MUX
LINE B
MIXHPLSEL
MIXHPRSEL
MAX98090
SPK_VDD
SPKSLAVE
MIXHPL[5:0]
MIXHPLG[1:0]
DACR
MIC 2
SPEAKER
RIGHT PGA
MIXSPL[5:0]
MIXSPLG[1:0]
LINE B
MIC 1
-12dB TO 0dB
RCVN/
LOUTR
RCVRVOL[4:0]
RCVRM
RCVREN
ZDEN
VS2EN
VSEN
DACR
RCVP/
LOUTL
ZDEN
VS2EN
VSEN
LINMOD
DACL
DAC
LEFT
-62dB TO 8dB
LINE OUT
LEFT PGA
DACR
RCV/
MIC 1 LINE
MIC 2 OUT
RIGHT
LINE A
MIXER
LINE B
RCVLVOL[4:0]
RCVLM
RCVLEN
HEADPHONE
LEFT PGA
-67dB TO 3dB
ZDEN
VS2EN
VSEN
HPL
HPSNS
DACL
DACR
MIC 1
ANALOG
INPUT
DRIVERS
HP
MIC 2 RIGHT
MIXER
LINE A
LINE B
-12dB TO 0dB
HP
RIGHT
MUX
MIXHPR[5:0]
MIXHPRG[1:0]
HEADPHONE
RIGHT PGA
HPVOLR[4:0]
HPRM
HPREN
-67dB TO 3dB
HEADPHONE
DIRECT DRIVE
CHARGE PUMP
HPR
HPVDD
HPGND
CPVSS CPVDD C1N C1P
Figure 32. Analog Audio Output Functional Diagram
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Maxim Integrated │ 130
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Class AB Configurable
Receiver/Line Output
configuration, both channels are configured individually
by the left and right channel registers.
The device features a configurable analog Class AB programmable gain amplifier output that can be configured to
act either a mono differential output or as a stereo singleended output. When configured as a differential analog
output (LINEMOD = 0, Table 61), the driver is an ideal
receiver driver capable of driving both 16Ω and 32Ω differential loads (such as an earpiece speaker). In the receiver
configuration, the mono output of the left receiver/line
output mixer is routed to both the left and right output drivers in a bridge tied load (BTL) configuration (Figure 33).
In this configuration, the mixer input signal source(s) and
both the mixer and output amplifier gain settings are determined by the left channel registers. All right output channel
register settings have no effect in receiver/earpiece mode.
Receiver/Earpiece Mixer and Gain Control
When configured as a stereo single-ended analog output (LINEMOD = 1, Table 61), the driver is optimized for
standard ground referenced, high impedance line outputs.
In the line output configuration, the output of the left and
right line output mixers are individually routed to the left
and right output drivers (respectively, Figure 34). In this
FLEXSOUND
TECHNOLOGY
DSP
When configured as a differential receiver output, only the
left output configuration registers are used. The receiver
mixer can be configured to accept any combination of
signals from the playback DAC, the analog microphone
amplifiers, and the line input drivers (Table 58). The
receiver input mixer also provides several attenuation
options (Table 59). The mixer attenuation options of -6dB,
-9.5dB, and -12dB are sized to prevent clipping when
several full-scale input sources are selected.
The receiver output is a programmable gain amplifier
(PGA) capable of driving a wide range of differential loads
(including standard 16Ω and 32Ω earpiece speakers). The
receiver PGA has a wide volume adjustment range from
-62dB to +8dB, provides a high attenuation mute control
(Table 60), and features programmable click and pop
reduction options. See the Click-and-Pop Reduction section for details. The receiver PGA output common-mode
voltage is either half of VAVDD (in resistive divider BIAS
mode) or about 0.78V (in bandgap BIAS mode).
SPEAKER/
HEADPHONES
DACR
DACL
DAC
LEFT
DACLEN
RCV/ -12dB TO 0dB
LINE
MIC 2 OUT
LEFT
LINE A MIXER
LINE B
MIC 1
DAC
RIGHT
DACHP
PERFMODE
MIXRVCL[5:0]
MIXRVCLG[1:0]
DACREN
DACR
DACL
ANALOG
INPUT
DRIVERS
RCV/
MIC 1 LINE
MIC 2 OUT
RIGHT
LINE A
MIXER
LINE B
-12dB TO 0dB
RCVLVOL[4:0]
RCVLM
RCVLEN
LINE OUT
LEFT PGA
MIXRVCL[5:0]
MIXRVCLG[1:0]
RCVP/
LOUTL
ZDEN
VS2EN
ZSEN
LINMOD
RCV/
LINE
OUT
MUX
-62dB TO 8dB
LINE OUT
RIGHT PGA
-62dB TO 8dB
RCVN/
LOUTR
MAX98090
RCVRVOL[4:0]
RCVRM
RCVREN
Figure 33. Receiver Output Functional Diagram
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Maxim Integrated │ 131
MAX98090
Ultra-Low Power Stereo Audio Codec
FLEXSOUND
TECHNOLOGY
DSP
SPEAKER/
HEADPHONES
DACR
DACL
DAC
LEFT
DACLEN
MIXRVCL[5:0]
MIXRVCLG[1:0]
RCV/
-12dB TO 0dB
LINE
OUT
MIC 2
LEFT
LINE A MIXER
MIC 1
DAC
RIGHT
DACHP
PERFMODE
RCVLVOL[4:0]
RCVLM
RCVLEN
DACREN
LINE OUT
LEFT PGA
LINE B
DACL
ANALOG
INPUT
DRIVERS
-12dB TO 0dB
RCVP/
LOUTL
ZDEN
VS2EN
ZSEN
LINMOD
DACR
RCV/
MIC 1 LINE
MIC 2 OUT
RIGHT
LINE A MIXER
LINE B
-62dB TO 8dB
RCV/
LINE
OUT
MUX
LINE OUT
RIGHT PGA
-62dB TO 8dB
RCVN/
LOUTR
MAX98090
MIXRVCL[5:0]
MIXRVCLG[1:0]
RCVRVOL[4:0]
RCVRM
RCVREN
Figure 34. Stereo Single-Ended Line Output Functional Diagram
Table 58. Receiver and Left Line Output Mixer Source Configuration Register
ADDRESS: 0x37
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
0
Selects MIC 2 as the input to the receiver/line out left mixer.
4
0
Selects MIC 1 as the input to the receiver/line out left mixer.
0
Selects line B as the input to the receiver/line out left mixer.
0
Selects line A as the input to the receiver/line out left mixer.
1
0
Selects DAC right as the input to the receiver/line out left mixer.
0
0
Selects DAC left as the input to the receiver/line out left mixer.
3
2
MIXRCVL[5:0]
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R/W
Maxim Integrated │ 132
MAX98090
Ultra-Low Power Stereo Audio Codec
Line Output Mixer and Gain Control
When configured as a stereo single-ended line output, the
left and right configuration registers can be programmed
independently. Each channel mixer can be configured
to accept any combination of signals from the playback
DAC, the analog microphone amplifiers, and the line input
drivers (Tables 58 and 61). The input mixers also provide
several attenuation options (Tables 59 and 62). The mixer
attenuation options of -6dB, -9.5dB, and -12dB are sized
to prevent clipping when several full-scale input sources
are selected.
The left and right line output drivers are independent
programmable gain amplifiers (PGAs) capable of driving high impedance ground referenced loads. The line
output PGAs have a wide volume adjustment range from
-62dB to +8dB, provide a high attenuation mute control
(Tables 60 and 63), and feature programmable click and
pop reduction options. See the Click-and-Pop Reduction
section for details. The output common-mode voltage is
either half of VAVDD (in resistive divider BIAS mode) or
about 0.78V (in bandgap BIAS mode). As a result of the
internal architecture, the left and right channel each have
a built in baseline gain of -3dB (when all programmable
gain options are set to 0dB).
Table 59. Receiver and Left Line Output Mixer Gain Control Register
ADDRESS: 0x38
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
MIXRCVLG[1:0]
R/W
1
0
0
0
Receiver/Line Output Left Mixer Gain Configuration
00: 0dB
10: -9.5dB
01: -6dB
11: -12dB
Table 60. Receiver and Left Line Output Volume Control Register
ADDRESS: 0x39
DESCRIPTION
BIT
NAME
TYPE
POR
7
RCVLM
R/W
0
6
—
—
—
—
5
—
—
—
—
4
1
3
0
2
RCVLVOL[4:0]
R/W
1
1
0
0
1
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Left Receiver/Line Output Mute
0: Left output amplifier not muted.
1: Left output amplifier is muted.
Receiver/Line Output Left PGA Volume Configuration
0x1F: +8dB
0x1E: +7.5dB
0x1D: +7dB
0x1C: +6.5dB
0x1B: +6dB
0x1A: +5dB
0x19: +4dB
0x18: +3dB
0x17: +2dB
0x16: +1dB
0x15: +0dB
0x14: -2dB
0x13: -4dB
0x12: -6dB
0x11: -8dB
0x10: -10dB
0x0F: -12dB
0x0E: -14dB
0x0D: -17dB
0x0C: -20dB
0x0B: -23dB
0x0A: -26dB
0x09: -29dB
0x08: -32dB
0x07: -35dB
0x06: -38dB
0x05: -42dB
0x04: -46dB
0x03: -50dB
0x02: -54dB
0x01: -58dB
0x00: -62dB
Maxim Integrated │ 133
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 61. Right Line Output Mixer Source Configuration Register
ADDRESS: 0x3A
BIT
NAME
TYPE
POR
7
LINMOD
R/W
0
6
—
—
—
DESCRIPTION
Selects Between Receiver BTL Mode and Line Output mode
0: Receiver BTL mode. All control of the output is from the left-channel registers.
1: Line Output mode. Left and right channels are programmed independently.
—
5
0
Selects MIC 2 as the input to the line out right mixer
4
0
Selects MIC 1 as the input to the line out right mixer
0
Selects Line B as the input to the line out right mixer
0
Selects Line A as the input to the line out right mixer
1
0
Selects DAC Right as the input to the line out right mixer
0
0
Selects DAC Left as the input to the line out right mixer
3
2
MIXRCVR[5:0]
R/W
Table 62. Right Line Output Mixer Gain Control Register
ADDRESS: 0x3B
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
1
0
MIXRCVRG[1:0]
R/W
0
0
—
Line Output Right Mixer Gain Configuration
00: 0dB
10: -9.5dB
01: -6dB
11: -12dB
Table 63. Right Line Output Volume Control Register
ADDRESS: 0x3C
DESCRIPTION
BIT
NAME
TYPE
POR
7
RCVRM
R/W
0
6
—
—
—
—
5
—
—
—
—
4
1
3
0
2
RCVRVOL[4:0]
R/W
1
1
0
0
1
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Right Receiver/Line Output Mute
0: Right output amplifier not muted.
1: Right output amplifier is muted.
Line Output Right PGA Volume Configuration
0x1F: +8dB
0x1E: +7.5dB
0x1D: +7dB
0x1C: +6.5dB
0x1B: +6dB
0x1A: +5dB
0x19: +4dB
0x18: +3dB
0x17: +2dB
0x16: +1dB
0x15: +0dB
0x14: -2dB
0x13: -4dB
0x12: -6dB
0x11: -8dB
0x10: -10dB
0x0F: -12dB
0x0E: -14dB
0x0D: -17dB
0x0C: -20dB
0x0B: -23dB
0x0A: -26dB
0x09: -29dB
0x08: -32dB
0x07: -35dB
0x06: -38dB
0x05: -42dB
0x04: -46dB
0x03: -50dB
0x02: -54dB
0x01: -58dB
0x00: -62dB
Maxim Integrated │ 134
MAX98090
Ultra-Low Power Stereo Audio Codec
Analog Class D Speaker Output
The device features an integrated stereo differential
speaker amplifier. The analog stereo speaker output has
three series sections comprising a flexible input mixer, a
FLEXSOUND
TECHNOLOGY
DSP
programmable gain amplifier, and a differential Class D
output driver (Figure 35). The speaker output is capable
of driving both 4Ω and 8Ω loads, utilizes a highly efficient
Class D architecture, and meets EMI emission standards
while driving a filterless speaker load.
RECEIVER/LINE OUT/
HEADPHONES
DACR
DACL
DAC
LEFT
DACLEN
MIC 1
DAC
RIGHT
DACHP
PERFMODE
SPK
LEFT
MIC 2 MIXER
LINE A
MIXSPL[5:0]
MIXSPLG[1:0]
DACREN
LINE B
-12dB TO 0dB
SPEAKER
LEFT PGA
SPVOLL[4:0]
SPLM
SPLEN
-48dB TO 14dB
SPKLP
6dB
ZDEN
VS2EN
ZSEN
MAX98090
SPK
RIGHT
MIC 2 MIXER
MIC 1
ANALOG
INPUT
DRIVERS
LINE A
LINE B
SPKLN
SPK_VDD
SPKSLAVE
DACR
DACL
SPKLGND
-12dB TO 0dB
SPEAKER
RIGHT PGA
MIXSPL[5:0]
MIXSPLG[1:0]
-48dB TO 14dB
SPKRP
6dB
SPVOLR[4:0]
SPLM
SPREN
SPKRN
SPKRGND
Figure 35. Class D Speaker Output Functional Diagram
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Maxim Integrated │ 135
MAX98090
Ultra-Low Power Stereo Audio Codec
Speaker Output Mixer and Gain Control
The speaker mixers can be configured to accept any
combination of signals from the playback DAC, the analog
microphone amplifiers, and the line input drivers (Tables 64
and 65). The input mixers also provide several attenuation
options (Table 66). The mixer attenuation options of -6dB,
-9.5dB, and -12dB are sized to prevent clipping when several full-scale input sources are selected.
Table 64. Left Speaker Mixer Configuration Register
ADDRESS: 0x2E
BIT
NAME
TYPE
POR
7
—
—
—
6
—
—
—
DESCRIPTION
—
—
5
0
Selects microphone input 2 to left speaker mixer
4
0
Selects microphone Input 1 to left speaker mixer
3
0
Selects line input B to left speaker mixer
2
MIXSPL[5:0]
R/W
0
Selects line input A to left speaker mixer
1
0
Selects right DAC output to left speaker mixer
0
0
Selects left DAC output to left speaker mixer
Table 65. Right Speaker Mixer Configuration Register
ADDRESS: 0x2F
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
6
SPK_SLAVE
—
—
Speaker Slave Mode Enable
0: Right-channel clock always generated independently.
1: Right channel uses left-channel clock if both channels are enabled.
5
0
Selects microphone input 2 to right speaker mixer.
4
0
Selects microphone input 1 to right speaker mixer.
3
0
Selects line input B to Right speaker mixer.
0
Selects line input A to right speaker mixer.
1
0
Selects right DAC output to right speaker mixer.
0
0
Selects left DAC output to right speaker mixer.
2
MIXSPR[5:0]
R/W
—
Table 66 Speaker Mixer Gain Control Register
ADDRESS: 0x30
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
MIXSPRG[1:0]
R/W
MIXSPLG[1:0]
R/W
3
2
1
0
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0
0
0
0
Right-Speaker Mixer Gain Configuration
00: +0dB 10: -9.5dB
01: -6dB 11: -12dB
Left-Speaker Mixer Gain Configuration
00: +0dB 10: -9.5dB
01: -6dB 11: -12dB
Maxim Integrated │ 136
MAX98090
Ultra-Low Power Stereo Audio Codec
The speaker output programmable gain amplifiers (PGAs)
have a wide volume adjustment range from -48dB to
+14dB, provide a high attenuation mute control (Table 67
and Table 68), and feature programmable click and pop
reduction options. See Click-and-Pop Reduction section
for details. In addition to the programmable gain range,
the Class D output driver also provides another 6dB of
built-in gain.
Table 67. Left Speaker Amplifier Volume Control Register
ADDRESS: 0x31
BIT
NAME
TYPE
POR
7
SPLM
R/W
0
6
—
—
—
5
1
4
0
3
1
2
SPVOLL[5:0]
R/W
1
1
0
0
0
DESCRIPTION
Left Speaker Output Mute Enable
0 : Speaker output volume set by the volume control bits.
1 : Left speaker output muted.
—
Left Speaker Output Amplifier Volume Control Configuration
0x3F: +14dB
0x3E: +13.5dB
0x3D: +13dB
0x3C: +12.5dB
0x3B: +12dB
0x3A: +11.5dB
0x39: +11dB
0x38: +10.5dB
0x37: +10dB
0x36: +9.5dB
0x35: +9dB
0x34: +8dB
0x33: +7dB
0x32: +6dB
0x31: +5dB
0x30: +4dB
0x2F: +3dB
0x2E: +2dB
0x2D: +1dB
0x2C: +0dB
0x2B: -1dB
0x2A: -2dB
0x29: -3dB
0x28: -4dB
0x27: -5dB
0x26: -6dB
0x25: -8dB
0x24: -10dB
0x23: -12dB
0x22: -14dB
0x21: -17dB
0x20: -20dB
0x1F: -23dB
0x1E: -26dB
0x1D: -29dB
0x1C: -32dB
0x1B: -36dB
0x1A: -40dB
0x19: -44dB
0x18: -48dB
Table 68. Right Speaker Amplifier Volume Control Register
ADDRESS: 0x32
BIT
NAME
TYPE
POR
7
SPRM
R/W
0
6
—
—
—
5
1
4
0
3
1
2
SPVOLR[5:0]
R/W
1
1
0
0
0
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DESCRIPTION
Right Speaker Output Mute Enable
0 : Speaker output volume set by the volume control bits.
1 : Right-speaker output muted.
—
Right Speaker Output Amplifier Volume Control Configuration
0x3F: +14dB
0x3E: +13.5dB
0x3D: +13dB
0x3C: +12.5dB
0x3B: +12dB
0x3A: +11.5dB
0x39: +11dB
0x38: +10.5dB
0x37: +10dB
0x36: +9.5dB
0x35: +9dB
0x34: +8dB
0x33: +7dB
0x32: +6dB
0x31: +5dB
0x30: +4dB
0x2F: +3dB
0x2E: +2dB
0x2D: +1dB
0x2C: +0dB
0x2B: -1dB
0x2A: -2dB
0x29: -3dB
0x28: -4dB
0x27: -5dB
0x26: -6dB
0x25: -8dB
0x24: -10dB
0x23: -12dB
0x22: -14dB
0x21: -17dB
0x20: -20dB
0x1F: -23dB
0x1E: -26dB
0x1D: -29dB
0x1C: -32dB
0x1B: -36dB
0x1A: -40dB
0x19: -44dB
0x18: -48dB
Maxim Integrated │ 137
MAX98090
Ultra-Low Power Stereo Audio Codec
Efficient Class D Speaker Output Driver
A Class D amplifier offers much higher efficiency than
a Class AB amplifier. The high efficiency is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with a Class D output
stage is primarily due to the loss in the MOSFET onresistance, and the baseline quiescent current overhead.
For comparison, the theoretical best-case efficiency of a
linear amplifier is 78%. However, that efficiency is only
possible at peak output power conditions. Under normal
operating levels (typical music reproduction levels), efficiency often falls below 30%. Under the same conditions,
the device’s differential Class D speaker output amplifier
still exhibits 80% efficiency.
By default, the Class D output switching clocks are independently generated for the left and right channels. With
slave mode enabled, the right channel becomes a slave
to the left channel and uses the same clock (Table 65).
In slave mode, the switching scheme is synchronous. As
FLEXSOUND
TECHNOLOGY
DSP
MIC 1
DAC
RIGHT
DACHP
PERFMODE
Analog Class-H Headphone Output
The stereo headphone output driver has a flexible input
mixer, programmable gain stage, an integrated charge
pump, and a ground referenced DirectDrive Class H
output amplifier (Figure 36). The headphone output
amplifier is capable of driving both 16Ω and 32Ω groundreferenced headphone loads.
MIXHPL[5:0]
MIXHPLG[1:0]
DACL
DACLEN
Traditional Class D amplifiers often require the use of
external LC filters and/or shielding to meet EN55022B
and FCC electromagnetic-interference (EMI) regulation
standards. Maxim’s patented active emissions limiting
edge-rate control circuitry reduces EMI emissions. This
allows the device to drive both 4Ω and 8Ω without any
additional output filtering. The filterless Class D outputs
are designed for typical applications where the trace
length to the speakers is short and has a low series
resistance. See the Filterless Class D Speaker Operation
section for application level details.
SPEAKER/RECEIVER/
LINE OUT
DACR
DAC
LEFT
a result, slave mode operation eliminates potential beat
tones that can occur with asynchronous stereo Class D
switching.
MIC 2
DACREN
LINE A
HP
LEFT
MIXER
LINE B
-12dB TO 0dB
HP
LEFT
MUX
MIXHPLSEL
MIXHPRSEL
MAX98090
DACR
DACL
ANALOG
INPUT
DRIVERS
HP
MIC 1
RIGHT
MIC 2
MIXER
LINE A
LINE B
HPVOLL[4:0]
HPLM
HPLEN
HP
RIGHT
-12dB TO 0dB MUX
MIXHPR[5:0]
MIXHPRG[1:0]
HEADPHONE
LEFT PGA
-67dB TO 3dB
ZDEN
VS2EN
ZSEN
HEADPHONE
RIGHT PGA
HPVOLR[4:0]
HPRM
HPREN
HPL
HPSNS
-67dB TO 3dB
HEADPHONE
DIRECT DRIVE
CHARGE PUMP
HPR
HPVDD
HPGND
C1P C1N CPVDD CPVSS
Figure 36. DirectDrive Headphone Output Functional Diagram
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Maxim Integrated │ 138
MAX98090
Ultra-Low Power Stereo Audio Codec
Headphone Output Mixer and Gain Control
The headphone mixers can be configured to accept any
combination of signals from the playback DAC, the analog
microphone amplifiers, and the line input drivers (Table 69
and Table 70). The input mixers also provide several attenuation options (Table 71). The mixer attenuation options of
-6dB, -9.5dB, and -12dB are sized to prevent clipping when
several full-scale input sources are selected.
Table 69. Left Headphone Mixer Configuration Register
ADDRESS: 0x29
BIT
NAME
TYPE
POR
7
—
—
—
6
—
—
—
DESCRIPTION
—
—
5
0
Selects microphone input 2 to left headphone mixer.
4
0
Selects microphone input 1 to left headphone mixer.
0
Selects line input B to left headphone mixer.
0
Selects line input A to left headphone mixer.
1
0
Selects right DAC output to left headphone mixer.
0
0
Selects left DAC output to left headphone mixer.
3
2
MIXHPL[5:0]
R/W
Table 70. Right Headphone Mixer Configuration Register
ADDRESS: 0x2A
BIT
NAME
TYPE
POR
7
—
—
—
6
—
—
—
DESCRIPTION
—
—
5
0
Selects microphone input 2 to right headphone mixer.
4
0
Selects microphone input 1 to right headphone mixer.
3
0
Selects line input B to right headphone mixer.
2
MIXHPR[5:0]
R/W
0
Selects line input A to right headphone mixer.
1
0
Selects right DAC output to right headphone mixer.
0
0
Selects left DAC output to right headphone mixer.
Table 71. Headphone Mixer Control and Gain Register
ADDRESS: 0x2B
BIT
NAME
TYPE
POR
7
—
—
—
6
—
—
—
DESCRIPTION
—
—
5
MIXHPRSEL
R/W
0
Select Headphone Mixer as Right Input Source (Default DAC Right Direct)
0: DAC only source (best dynamic range and power consumption)
1: Headphone mixer source
4
MIXHPLSEL
R/W
0
Select Headphone Mixer as Left Input Source (Default DAC Left Direct)
0: DAC only source (best dynamic range and power consumption)
1: Headphone mixer source
MIXHPRG[1:0]
R/W
MIXHPLG[1:0]
R/W
3
2
1
0
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0
0
0
0
Right-Headphone Mixer Gain Configuration
00: +0dB 10: -9.5dB
01: -6dB 11: -12dB
Left-Headphone Mixer Gain Configuration
00: +0dB 10: -9.5dB
01: -6dB 11: -12dB
Maxim Integrated │ 139
MAX98090
Ultra-Low Power Stereo Audio Codec
Additionally, the headphone output has a reduced power
direct from DAC playback mode (Figure 37). In this configuration, the stereo DAC outputs from the playback path
are routed around the headphone mixer directly to the
FLEXSOUND
TECHNOLOGY
DSP
SPEAKER/RECEIVER/
LINE OUT
DACR
MIXHPL[5:0]
MIXHPLG[1:0]
DACL
DAC
LEFT
DACLEN
MIC 1
DAC
RIGHT
DACHP
PERFMODE
headphone output amplifiers. When paired with the low
power headphone playback mode (Table 4), this combination is the lowest power digital to analog playback
configuration available.
MIC 2
DACREN
LINE A
HP
LEFT
MIXER
-12dB TO 0dB
HP
LEFT
MUX
LINE B
MIXHPLSEL
MIXHPRSEL
MAX98090
DACR
DACL
HP
RIGHT
MIC 2
MIXER
LINE A
MIC 1
ANALOG
INPUT
DRIVERS
LINE B
HPVOLL[4:0]
HPLM
HPLEN
HP
RIGHT
-12dB TO 0dB MUX
MIXHPR[5:0]
MIXHPRG[1:0]
HEADPHONE
LEFT PGA
-67dB TO 3dB
ZDEN
VS2EN
ZSEN
HEADPHONE
RIGHT PGA
HPVOLR[4:0]
HPRM
HPREN
HPL
HPSNS
-67dB TO 3dB
HEADPHONE
DIRECT DRIVE
CHARGE PUMP
HPR
HPVDD
HPGND
C1P C1N CPVDD CPVSS
Figure 37. Reduced Power DAC Playback to Headphone Output Configuration
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Maxim Integrated │ 140
MAX98090
Ultra-Low Power Stereo Audio Codec
The headphone output programmable gain amplifiers
(PGAs) have a wide volume adjustment range from -67dB
to +3dB, provide a high attenuation mute control (Table 72
and Table 73), and feature programmable click-and-pop
reduction options. See the Click-and-Pop Reduction section for details.
Table 72. Left Headphone Amplifier Volume Control Register
ADDRESS: 0x2C
DESCRIPTION
BIT
NAME
TYPE
POR
7
HPLM
R/W
0
6
—
—
—
—
5
—
—
—
—
4
1
3
1
2
HPVOLL[4:0]
R/W
0
1
1
0
0
Left Headphone Output Mute Enable
0 : Headphone output volume set by the volume control bits.
1 : Headphone output muted.
Left Headphone Output Amplifier Volume Control Configuration
0x1F: +3dB
0x1E: +2.5dB
0x1D: +2dB
0x1C: +1.5dB
0x1B: +1dB
0x1A: +0dB
0x19: -1dB
0x18: -2dB
0x17: -3dB
0x16: -4dB
0x15: -5dB
0x14: -7dB
0x13: -9dB
0x12: -11dB
0x11: -13dB
0x10: -15d
0x0F: -17dB
0x0E: -19dB
0x0D: -22dB
0x0C: -25dB
0x0B: -28dB
0x0A: -31dB
0x09: -34dB
0x08: -37dB
0x07: -40dB
0x06: -43dB
0x06: -47dB
0x04: -51dB
0x03: -55dB
0x02: -59dB
0x01: -63dB
0x00: -67dB
Table 73. Right Headphone Amplifier Volume Control Register
ADDRESS: 0x2D
BIT
NAME
7
HPRM
R/W
0
6
—
—
—
5
—
—
—
4
1
3
1
2
HPVOLR[4:0]
R/W
0
1
1
0
0
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DESCRIPTION
TYPE POR
Right Headphone Output Mute Enable
0 : Headphone output volume set by the volume control bits.
1 : Headphone output muted.
—
—
Right Headphone Output Amplifier Volume Control Configuration
0x1F: +3dB
0x1E: +2.5dB
0x1D: +2dB
0x1C: +1.5dB
0x1B: +1dB
0x1A: +0dB
0x19: -1dB
0x18: -2dB
0x17: -3dB
0x16: -4dB
0x15: -5dB
0x14: -7dB
0x13: -9dB
0x12: -11dB
0x11: -13dB
0x10: -15dB
0x0F: -17dB
0x0E: -19dB
0x0D: -22dB
0x0C: -25dB
0x0B: -28dB
0x0A: -31dB
0x09: -34dB
0x08: -37dB
0x07: -40dB
0x06: -43dB
0x06: -47dB
0x04: -51dB
0x03: -55dB
0x02: -59dB
0x01: -63dB
0x00: -67dB
Maxim Integrated │ 141
MAX98090
Ultra-Low Power Stereo Audio Codec
Headphone Ground Sense
To improve channel isolation, the device has a low-side
headphone sense (HPSNS) that senses the ground
return of the headphone load. For optimal performance,
connect the headphone sense line through an isolated
OPTIMAL GROUND SENSE CONFIGURATION
trace to a point as close as possible to the ground pole of
the headphone jack (Figure 38). If this is not possible, or
if headphone sense is not used, connect it to the analog
ground plane. In this configuration, channel isolation can
be degraded, resulting in increased channel-to-channel
crosstalk.
ALTERNATIVE GROUND SENSE CONFIGURATION
ISOLATED HP
SENSE TRACE
HEADPHONE
LEFT PGA
HP SENSE
TO GROUND
HPL
HEADPHONE
LEFT PGA
HPSNS
HEADPHONE
RIGHT PGA
HPR
HPL
HPSNS
CODEC
GROUND
PLANE
HEADPHONE
OUTPUT JACK
HEADPHONE
RIGHT PGA
HPR
CODEC
GROUND
PLANE
HEADPHONE
OUTPUT JACK
Figure 38. Headphone Output Ground Sense Connections
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Maxim Integrated │ 142
MAX98090
Ultra-Low Power Stereo Audio Codec
DirectDrive Headphone Output Amplifier
Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically at either
half the high-side supply, or at a bandgap referenced
common mode level). As a result, large coupling capacitors are needed to block this DC bias and AC-couple
the audio output to the headphone load. Without these
capacitors, a significant DC current would flow through
the ground referenced headphone load. The result is both
unnecessary power dissipation, and potential damage to
both the headphone load and amplifier.
Maxim’s second-generation DirectDrive architecture
solves this problem by using a charge pump to create
an internal negative supply voltage. This increases the
overall output signal swing while at the same time, allowing the headphone outputs to be biased at GND even
while operating from a single supply (Figure 39). Without
a DC bias component, there is no need for the large
AC-coupling capacitors. Instead of two large (typically
220µF) capacitors, the charge pump only requires three
small ceramic capacitors. This conserves board space,
reduces cost, and improves the frequency response of
the headphone amplifier.
Class H Amplifier Charge Pump
A Class H amplifier has the same output architecture as
a Class AB amplifier. However, in a Class H amplifier the
power supplies are modulated by the output signal. The
integrated headphone charge pump generates both the
positive and negative power supply for the headphone
output amplifier. To maximize efficiency, both the charge
pump’s switching frequency and output voltage level and
format change based on the headphone output signal level.
The charge pump has three different operating ranges
each with a different switching frequency. The two lower
power ranges use a three-level switching scheme to generate half supply rails at ±VHPVDD/2 while the high power
range uses a standard two-level switching scheme to
generate full supply rails at ±VHPVDD. The switching frequency and voltage levels of each range are optimized to
maintain high efficiency while meeting the different output
power requirements (Table 74).
Table 74. Charge-Pump Operating Ranges
CHARGE PUMP CONFIGURATION
RANGE
HEADPHONE
OUTPUT LEVEL
(% of VHPVDD)
FREQUENCY
(kHz)
VCPVDD/CPVSS
WAVEFORM
1
< 10
~82
±VHPVDD/2
Range 1
2
10 to 25
~660
±VHPVDD/2
Range 2
3
> 25
~500
±VHPVDD
Range 3
VHPVDD
+VHPVDD
VHP_OUT
VHPVDD
VHP_OUT
GND
2
-VHPVDD
GND
CONVENTIONAL HEADPHONE BIAS
DIRECTDRIVE HEADPHONE BIAS
Figure 39. Conventional vs. DirectDrive Headphone Output Bias
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Maxim Integrated │ 143
MAX98090
Ultra-Low Power Stereo Audio Codec
Range 1 (VHP_OUT < 10% of VHPVDD): When the output signal level is less than 10% of HPVDD, the output
signal swing is low and the power consumption for driving
the headphone load is small relative to the charge pump
quiescent consumption and switching losses. Therefore,
to minimize switching losses, the charge-pump frequency
is reduced to its lowest rate (~82kHz) and the bipolar output supply rails are set to half of HPVDD or ±VHPVDD/2
(Figure 40, Range 1).
Range 2 (10% of VHPVDD ≤ VHP_OUT < 25% of
VHPVDD): When the output signal level is between 10%
and 25% of HPVDD, the output signal swing is still less
than half of HPVDD. However, the load power consumption
requirements are now much higher than the charge-pump
POSITIVE TERMINAL (C1P)
Range 3 (25% of VHPVDD ≤ VHP_OUT): When the
output signal level exceeds 25% of HPVDD, the output
signal swing is much wider. As a result, the charge pump
now generates bipolar full HPVDD output supply rails
(±VHPVDD). The switching frequency in this range is
slightly lower (~500kHz). However, the increased voltage
differential allows the headphone output driver to reach
its maximum voltage swing and load driving capability
(Figure 40, Range 3).
OPERATING RANGE 2
10% VHPVDD ≤ VHP_OUT < 25% VHPVDD
OPERATING RANGE 1
VHP_OUT < 10% VHPVDD
VHPVDD
quiescent consumption and switching losses. To meet the
increased load power requirements, the charge-pump
switching frequency increases (~660kHz) while the bipolar
output supply rails remain at half of HPVDD or ±VHPVDD/2
(Figure 40, Range 2).
VHPVDD
POSITIVE TERMINAL (C1P)
OPERATING RANGE 3
25% VHPVDD ≤ VHP_OUT
VHPVDD
VHPVDD
2
VHPVDD
2
VHPVDD
2
GND
GND
GND
-VHPVDD
2
-VHPVDD
2
-VHPVDD
2
-VHPVDD
-VHPVDD
-VHPVDD
VHPVDD
NEGATIVE TERMINAL (C1N)
VHPVDD
NEGATIVE TERMINAL (C1N)
VHPVDD
VHPVDD
2
VHPVDD
2
VHPVDD
2
GND
GND
GND
-VHPVDD
2
-VHPVDD
2
-VHPVDD
2
-VHPVDD
-VHPVDD
-VHPVDD
POSITIVE TERMINAL (C1P)
NEGATIVE TERMINAL (C1N)
Figure 40. Class H Amplifier Charge Pump Operating Ranges
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Maxim Integrated │ 144
MAX98090
Ultra-Low Power Stereo Audio Codec
To prevent audible crosstalk, the switching frequency in
all three charge pump ranges is well outside of the audio
band. In addition, to prevent audible distortion during
supply range changes, the charge pump transitions from
one output power range to another very quickly. When
changing from the half supply range (±VHPVDD/2) to
the full supply range (±VHPVDD/2), the transition occurs
immediately if the threshold is exceeded (to avoid clipping
for a rapidly increasing audio output). When moving back
down, there is a 32ms delay between the threshold detection and the supply range transition. The quick supply
level transitions draw a significant transient current from
HPVDD. To prevent a droop/glitch on HPVDD, the bypass
capacitance must be appropriate to supply the required
transient current (Figures 53 and 54).
Click-and-Pop Reduction
The device includes extensive click-and-pop reduction
circuitry designed to minimizes audible clicks and pops
at turn-on, turn-off, and during volume changes. These
features include zero-crossing detection, volume change
smoothing, and volume change stepping (Table 75).
Zero-crossing detection is available on the analog microphone input PGAs and all analog output PGAs and
volume controls to prevent large glitches when volume
changes are made. Instead of making a volume change
immediately, the change is made when the audio signal
crosses the midpoint (Figure 42). If no zero crossing
occurs within the timeout window (100ms), the volume
change occurs regardless of signal level.
32ms
VHPVDD
VCPVDD
VHPVDD
2
VTH_25%
GND
-VTH_25%
VHP_OUT
-VHPVDD
2
VCPVSS
-VHPVDD
32ms
Figure 41. Class H Amplifier Supply Range Transitions
I2C PGA
VOLUME
CHANGE
GND
I2C PGA
VOLUME
CHANGE
GND
AUDIO
OUTPUT
VOLUME
CHANGE
ZERO-CROSSING DETECTION
DISABLED (ZDEN = 1)
AUDIO
OUTPUT
VOLUME
CHANGE
ZERO-CROSSING DETECTION
ENABLED (ZDEN = 0)
Figure 42. Zero-Crossing Detection
www.maximintegrated.com
Maxim Integrated │ 145
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 75. Zero-Crossing Detection and Volume Smoothing Configuration Register
ADDRESS: 0x40
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
ZDEN
R/W
0
Zero-Crossing Detection
0: Volume changes made only at zero crossings or after approximately 100ms.
1: Volume changes made immediately upon request.
1
VS2EN
R/W
0
Enhanced Volume Smoothing
Only valid is volume adjustment smoothing is enabled (VSEN = 0).
0: Each volume change waits until the previous volume step has been applied to the
output. Allows volume smoothing to function with zero-crossing timeout.
1: Volume smoothing enhancement is disabled.
0
VSEN
R/W
0
Volume Adjustment Smoothing
0: Volume changes are smoothed by stepping through intermediate levels.
1: Volume changes are made directly in a single step.
Volume smoothing is available on all analog output PGAs.
When enabled, all volume changes are broken into the
smallest available step size. The volume is then ramped
through each step between the initial and final volume setting at a rate of one step every 1ms. Volume smoothing
also occurs at device turn-on and turn-off. During turn-on,
the volume is first set to mute before the output is enabled.
Once enabled, mute is first disabled and then the volume
is ramped to the programmed level. At turn-off, the volume
is ramped down to the minimum gain, and then muted,
before the outputs are disabled. If zero-crossing detection
is enabled, each volume step occurs at a zero crossing.
When no audio signal is present, zero-crossing detection
can timeout and prevent volume smoothing from occurring.
Enable enhanced volume smoothing to prevent the
volume controller from requesting another volume step
www.maximintegrated.com
until the previous step has been set. Each step in the
volume ramp then occurs either after a zero crossing has
occurred in the audio signal or after the timeout window
has expired.
During PGA turn-off, volume smoothing ramps the volume
down to the minimum setting, if enabled. However, to
prevent long turn off times enhanced volume smoothing
and zero-crossing detection is not applied at PGA mute
or turn-off. If volume smoothing is too slow or is not used,
the zero-crossing detection can still be used to minimize
click and pop when disabling an output PGA. First ramp
the PGA volume down to (in one step or multiple steps)
its minimum volume setting. Zero-crossing detection is
applied to each step of the volume change. Then, once
at the minimum volume, either enable mute or disable the
output PGA.
Maxim Integrated │ 146
MAX98090
Ultra-Low Power Stereo Audio Codec
Jack Detection
The device features a flexible, software configurable
jack detection interface. Once enabled, the jack detection interface uses two internal comparators to sense the
insertion/removal of a jack and identify the type of jack
inserted (headphones or headset). When the device is in
shutdown or the microphone bias is disabled, the comparator thresholds are referenced to VSPKLVDD. When
the device is active and microphone bias is enabled, the
comparator thresholds are referenced to VMICBIAS.
Jack detection operation relies on a pullup resistance
to set the bias when no jack is inserted. When the
device is in shutdown mode or the microphone bias is
disabled (MICBIAS is high impedance), an internal pullup is enabled on JACKSNS, and is referenced to the
SPKLVDD supply. When the device is not in shutdown
and the microphone bias is enabled, the internal pullup
is disabled (JACKSNS is high impedance). In this state,
successful jack detection requires an external pullup
on JACKSNS to MICBIAS. The jack detection internal
interface structure and typical external application circuit
is shown in Figure 43.
MICBIAS
VSPKLVDD
1µF
2.2kΩ
1µF
INTERNAL
PULL-UP
CONTROL
VIN+
ANALOG
MIC INPUT
1µF
VIN-
JACKSNS
LOAD SENSE
COMPARATOR
VSPKLVDD
VMICBIAS
HPL
MIC
GND
RIGHT
JDETEN
JDWK
LSNS
VTH
95%
JDETEN
JDEB[1:0]
MBEN
LEFT
HPR
HPSNS
VSPKLVDD
VMICBIAS
JKSNS
VTH
10%
JACK SENSE
COMPARATOR
Figure 43. Block Diagram and Typical Application Circuit for Jack Detection
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Maxim Integrated │ 147
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 76. Jack Detection Status Results
JACKSNS VOLTAGE
JACK DETECTION RESULTS
LSNS
JKSNS
STATE
VTH_95% ≤ VJACKSNS
1
1
No jack detected
VTH_10% ≤ VJACKSNS < VTH_95%
0
1
Headset detected
VJACKSNS < VTH_10%
0
0
Headphones detected
No condition
1
0
Not possible/reserved
Jack Detection Internal Comparators
When enabled, the device detects jack insertion and
removal by monitoring the voltage on JACKSNS with two
internal comparators. The load sense comparator has a
95% threshold of the reference supply and is used to determine whether or not a jack has been inserted or removed.
The jack sense comparator has a threshold of 10% of the
reference supply, and is used to identify the type of jack
(headphones/headset) inserted (Table 78).
When a jack is not inserted (open), the pullup resistance
conducts high. In this state, VJACKSNS is above the load
sense comparator threshold and LSNS is set high to
indicate that no jack is inserted. When a jack is inserted
it loads JACKSNS and pulls the voltage below the load
sense comparator threshold. LSNS is then set low to indicate that a jack is now inserted. When the jack is removed,
the pullup resistance once again conducts high and LSNS
is set high to indicate that the jack was removed.
When a jack is inserted, the loading on JACKSNS pulls
the voltage below the load sense comparator threshold.
However, depending on the type of jack connected the
voltage may or may not be pulled below the jack sense
comparator threshold. If a headphone jack is inserted
(3 pole), JACKSNS is shorted to ground. This pulls the
voltage below the jack sense comparator threshold
www.maximintegrated.com
(10% of the reference supply) and JKSNS is set low to
indicate headphones are inserted. If instead, a headset
jack is inserted (4 pole, as shown in Figure 44), instead
JACKSNS is biased to a voltage somewhere between the
referenced supply and ground. In this case, VJACKSNS is
above the jack sense comparator threshold but below the
load sense comparator threshold. This state indicates that
a headset is inserted. Table 76 details the three possible
jack detection status results.
These comparators are only active when the JDETEN is
set high. When jack detection is disabled, JACKSNS is
in a high impedance state and the interface is completely
shut down. When the device is in shutdown and JDETEN
is low, LSNS and JKSNS retain their previous state
regardless of the jack status.
Jack Detection Programmable Debounce
The load sense and jack sense comparators also have a
programmable debounce timeout. The debounce timeout
ensures that the jack detection status doesn’t change
unless the new state is persistent for longer than the timeout. This prevents rapid changes on LSNS and JKSNS
during jack insertion/removal transients, and ensures
that false jack detection interrupts are not generated. The
debounce timeout can be programmed to one of four settings from 25ms to 200ms (Table 77).
Maxim Integrated │ 148
MAX98090
1
Ultra-Low Power Stereo Audio Codec
2
JACK DETECTION DISABLED
HI-Z
JDETEN = 0
MBEN = 0 OR
SHDN = 0
OPEN JACK
HI-Z
MICBIAS
VIN+
1µF
JDETEN = 1
MBEN = 0 OR
SHDN = 0
OPEN JACK
SPKLVDD
ANALOG
MIC INPUT
1µF
MICBIAS
1µF
1µF
2.2kΩ
OPEN JACK DETECT (INTERNAL PULLUP)
VIN-
2.2kΩ
VIN+
1µF
ANALOG
MIC INPUT
1µF
INTERNAL
PULLUP
DISABLED
HPL
HPR
JACKSNS
PULLUP PATH
JACK DETECT
COMPARATORS
DISABLED
HPL
HPR
HPSNS
JDWK = 0
3
LSNS/JKSNS =
LAST STATE
JDWK = 1
JDETEN = 1
MBEN = 1
SHDN = 1
HEADPHONE
JACK
LSNS/JKSNS =
LAST STATE
JDWK = 0
4
LSNS = 1
JKSNS = 1
HI-Z
JDETEN = 1
MBEN = 1
SHDN = 1
HEADSET
JACK
VIN+
1µF
ANALOG
MIC INPUT
1µF
VIN-
JDWK = 1
2.2kΩ
MICBIAS
1µF
VIN+
1µF
ANALOG
MIC INPUT
1µF
SPKLVDD
VIN-
GND
JDWK = 0
RIGHT
LSNS = 0
JKSNS = 0
HPL
LEFT
JACKSNS
BIAS CURRENT
JACK DETECT
COMPARATORS
ENABLED
MIC
GND
RIGHT
HPL
LEFT
HPR
HPR
HPSNS
HPSNS
JDWK = 1
SPKLVDD
PULLUP
PULLUP
JACKSNS
SHORT TO GND
LSNS = 1
JKSNS = 1
HEADSET DETECT (INTERNAL PULLUP)
MICBIAS
1µF
2.2kΩ
JACK DETECT
COMPARATORS
ENABLED
HPSNS
HEADPHONE DETECT (INTERNAL PULLUP)
HI-Z
SPKLVDD
PULLUP
JACKSNS
HI-Z
VIN-
LSNS = 0
JKSNS = 0
JDWK = 0
LSNS = 0
JKSNS = 1
JDWK = 1
JACK DETECT
COMPARATORS
ENABLED
LSNS = 0
JKSNS = 0
Figure 44. Jack Detection Cases with Internal Pullup Resistance
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Maxim Integrated │ 149
MAX98090
Jack Detection Interrupt Generation
Whenever a jack is inserted or removed and the state of
either LSNS or JKSNS changes, a jack detection event is
indicated with the jack configuration change flag (JDET,
Table 85). If the jack detection event is not masked
(IJDET, Table 86), it also generates an interrupt on IRQ.
The jack detection event bit (JDET) is clear on read. An
I2C read clears both the JDET bit status and the interrupt
assertion on IRQ (if present). Unless a read occurs after
each jack detection event, both the JDET bit and the IRQ
interrupt will remain asserted and no new events or interrupts can be detected.
A change in state from LSNS = 1 to LSNS = 0 indicates
that a jack has been inserted, while a change in state from
LSNS = 0 to LSNS = 1 indicates that a jack has been
removed. When an insertion occurs, if JKSNS does not
change and remains at JKSNS = 1, a headset insertion
is indicated, while a change in state from JKSNS = 1 to
JKSNS = 0 indicates headphones have been inserted. The
state transitions, and the interrupt events generated, are
ideally used for state machine control in any jack detection
software drivers.
Operation with an Internal Pullup Resistance
The device has both a strong and weak internal pullup
option. The internal pullup resistors are only active if
the device is in shutdown (SHDN = 0,Table 6) or when
MICBIAS is disabled (MBEN = 0, Table 7), and they
allow jack detection and identification to function in those
states. This functionality is ideal for cases where the
device is put into a sleep or shutdown state, but needs to
trigger a device or system level interrupt signal for wake
on insertion operation.
When JDWK is low (default, Table 77), the strong internal pullup is used (approximately 2.4kΩ referenced to
SPKLVDD). This configuration is capable of detecting and
identifying both headphone and headset insertion. When
JDWK is high, the weak internal pullup (approximately
5µA to SPKLVDD) is used. The weak internal pullup minimizes the supply current after jack insertion and is ideal
for wake on insertion cases where the system might not
immediately power up. The weak internal pullup cannot
bias a microphone load, and therefore, cannot identify
headset insertion or accessory button presses.
Figure 44 details how jack detection works with the
internal pullup resistance. In case 1, jack detection is
disabled and both MICBIAS and JACKSNS are high
www.maximintegrated.com
Ultra-Low Power Stereo Audio Codec
impedance. In this state, LSNS and JKSNS retain the last
valid jack detection result. In case 2, no jack is inserted
and the internal pullup resistance to SPKLVDD conducts
JACKSNS up above both the load and jack sense comparator thresholds. In this case, with an open circuit jack,
both the strong and weak internal pullups produce the
correct jack detection result and the only power consumption is that required to bias the internal comparators. In
case 3, a headphone jack is inserted shorting JACKSNS
to ground, well below both the load and jack sense
comparator thresholds. In this state, both the strong and
weak internal pullups produce the correct jack detection
result but the strong internal pullup consumes significantly
more current than the weak internal pullup. In case 4, a
headset jack is inserted. In this state, the strong and weak
internal pullups produce different jack detection results.
The strong internal pullup biases the headset MIC (and
JACKSNS) to a level between the load sense and jack
sense comparator thresholds that produces the correct
jack detection result. The weak internal pullup, however,
is not strong enough to bias a headset MIC and as a
result it falsely reports that a headphones jack is present.
Operation with an External Pullup Resistance
The internal pullup resistance is sufficient for wake on
interrupt or basic jack detection and identification, but
an external pullup resistance to MICBIAS is required to
properly bias and current limit a headset microphone
(Figure 43). When jack detect is enabled and the device is
active (SHDN = 1, Table 6) with MICBIAS enabled (MBEN
= 1, Table 7), JACKSNS is placed into a high-impedance
state and the internal pullup resistor is disabled. In this
state, the external pullup resistor then determines the bias
voltage level at JACKSNS.
Figure 45 details the operation of jack detection with an
external pullup resistance. In Case 1, jack detection is
disabled. As a result, the internal jack detect comparators are disabled and LSNS/JKSNS retain their last valid
jack detection result. In case 2, no jack is inserted and
the external pullup resistance to MICBIAS conducts
JACKSNS up above both the load and jack sense
comparator thresholds. In case 3, a headphone jack is
inserted shorting JACKSNS to ground, well below both
the load and jack sense comparator thresholds. In case 4,
a headset jack is inserted and the external pullup biases
the headset MIC (and JACKSNS) to a level between the
load sense and jack sense comparator thresholds.
Maxim Integrated │ 150
MAX98090
1
Ultra-Low Power Stereo Audio Codec
2
JACK DETECTION DISABLED
HI-Z
JDETEN = 0
JDWK = X
MBEN = 1
SHDN = 1
OPEN JACK
PULLUP PATH
MICBIAS
1µF
2.2kΩ
OPEN JACK DETECT (INTERNAL PULLUP)
VIN+
1µF
JDETEN = 1
JDWK = X
MBEN = 1
SHDN = 1
OPEN JACK
SPKLVDD
ANALOG
MIC INPUT
1µF
VIN-
1µF
2.2kΩ
VIN+
1µF
HPL
HPR
1µF
INTERNAL
PULLUP
DISABLED
HPL
JACK DETECT
COMPARATORS
DISABLED
HPR
HPSNS
INTERNAL
PULLUP
DISABLED
JACK DETECT
COMPARATORS
ENABLED
HPSNS
LSNS = 1
JKSNS = 1
4
HEADPHONE DETECT (INTERNAL PULLUP)
SHORT TO GND
JDETEN = 1
JDWK = X
MBEN = 1
SHDN = 1
HEADPHONE
JACK
VIN-
JACKSNS
HI-Z
LSNS /JKSNS =
LAST STATE
3
SPKLVDD
ANALOG
MIC INPUT
JACKSNS
HI-Z
MICBIAS
2.2kΩ
BIAS CURRENT
MICBIAS
1µF
VIN+
1µF
SPKLVDD
ANALOG
MIC INPUT
1µF
HEADSET DETECT (INTERNAL PULLUP)
VIN-
JDETEN = 1
JDWK = X
MBEN = 1
SHDN = 1
HEADSET
JACK
2.2kΩ
1µF
VIN+
1µF
GND
RIGHT
HPL
LEFT
HPR
SPKLVDD
ANALOG
MIC INPUT
1µF
INTERNAL
PULLUP
DISABLED
JACKSNS
HI-Z
MICBIAS
VIN-
INTERNAL
PULLUP
DISABLED
JACKSNS
JACK DETECT
COMPARATORS
ENABLED
HI-Z
MIC
RIGHT
LEFT
HPR
HPSNS
LSNS = 0
JKSNS = 0
GND
HPL
JACK DETECT
COMPARATORS
ENABLED
HPSNS
LSNS = 0
JKSNS = 1
Figure 45. Jack Detection Operation with External Pullup Resistance
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Maxim Integrated │ 151
MAX98090
Ultra-Low Power Stereo Audio Codec
1 FALSE JACK DETECTION WITH
INTERNAL ANALOG MICROPHONE
1µF
JDETEN = 1
JDWK = X
1µF
2.2kΩ
MBEN = 0 OR
SHDN = 0
2 SCHOTTKY DIODE BLOCKS BIAS CURRENT
PATH TO INTERNAL ANALOG MICROPHONE
1µF
VIN+
ANALOG
MIC INPUT 2
VIN-
JDETEN = 1
JDWK = X
1µF
1µF
ANALOG
SINGLE-ENDED
MICROPHONE
1µF
MICBIAS
OPEN
JACK
HI-Z
2.2kΩ
VIN+
ANALOG
MIC INPUT 1
VIN-
ANALOG
MIC INPUT 2
VIN-
1µF
MBEN = 0 OR
SHDN = 0
MICBIAS
OPEN
JACK
2.2kΩ
VIN+
1µF
2.2kΩ
SPKLVDD
PULLUP
HI-Z
ANALOG
SINGLE-ENDED
MICROPHONE
1µF
VIN+
ANALOG
MIC INPUT 1
VIN-
1µF
JACKSNS
BIAS CURRENT PATH
LSNS = 0
JKSNS = 1
HPL
SPKLVDD
PULLUP
JACKSNS
CURRENT PATH BLOCKED
JACK DETECT
COMPARATORS
ENABLED
HPR
HPSNS
LSNS = 0
JKSNS = 1
HPL
JACK DETECT
COMPARATORS
ENABLED
HPR
HPSNS
Figure 46. Jack Detection with Internal Analog Microphones
Accessory Button Detection
After jack insertion, the device can detect button presses
on any accessories that include a microphone and a
switch that shorts the microphone ring to ground. Button
presses can be detected either when MICBIAS is enabled
or if it is disabled and the strong internal pullup is used
(JDWK = 0). A button press changes the state of JKSNS
from 1 to 0 until the button is released, and this change
in state generates an event on the jack detection change
flag (JDET). This event is used to trigger the appropriate
action associated with the key press.
Jack Detection with Internal Analog
Microphones
If the application requires fixed internal analog
microphone(s), and must also detect, identify, and operate with a headset microphone, the general jack detecaion application circuit (Figure 43) does not operate
as expected. The complication introduced by an internal
analog microphone is detailed in Figure 46.
When no jack is inserted (case 1) the internal pullup resistance attempts to pull JACKSNS above the load sense
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comparator threshold. However, the external pullup to
MICBIAS creates an unintended current path through the
internal analog microphone pullup. As a result, the voltage at
JACKSNS is biased to a level between the jack sense and
load sense comparator thresholds, resulting in a false headset jack detection. When a headset jack is inserted, there is
a parallel load on JACKSNS between the inserted headset
jack and the internal analog microphone. This could potentially result in a headset being reported as headphones.
A Schottky diode with a very low forward drop (case 2)
can be inserted in series with the external pullup resistance. When MICBIAS is disabled, the Schottky diode
is reverse biased and the current path is blocked. When
MICBIAS is enabled, the diode is forward biased and the
external pullup to mic bias functions as detailed in Figure
45. The diode does introduce a series voltage drop, and
the MICBIAS voltage and/or the series resistance value
might need to be adjusted to compensate and ensure that
the headset MIC is properly biased. Alternatively, a switch
can be used in series either above or below the internal
analog microphone to break the bias current path when
MICBIAS is disabled.
Maxim Integrated │ 152
MAX98090
Ultra-Low Power Stereo Audio Codec
Table 77. Jack Detect Configuration Register
ADDRESS: 0x3D
DESCRIPTION
BIT
NAME
TYPE
POR
7
JDETEN
R/W
0
Jack Detect Enable
0: Jack detect circuitry disabled
1: Jack detect circuitry enabled
JACKSNS Pullup Configuration
0: 2.4kΩ resistor to SPKLVDD (allows microphone detection)
1: 5µA to SPKLVDD (minimizes supply current)
Valid when MICBIAS = 0 or SHDN = 0.
6
JDWK
R/W
0
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
—
—
—
—
1
0
JDEB[1:0]
R/W
0
0
Jack Detect Debounce
Configures the jack detect debounce time:
00: 25ms 10: 100ms
01: 50ms 11: 200ms
Table 78. Jack Status Register
ADDRESS: 0x02
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3
—
—
—
—
2
LSNS
R
0
Microphone Load Sense (Valid Only if JDETEN = 1)
0: VJACKSNS ≤ 0.95V x VSUPPLY
1: VJACKSNS > 0.95V x VSUPPLY
VSUPPLY is determined by the state of MBEN and SHDN so that:
MBEN = 0 or SHDN = 0: VSUPPLY = VSPKLVDD (internal pullup)
MBEN = 1 and SHDN = 1: VSUPPLY = VMICBIAS (external pullup)
Jack Connection Sense (Valid Only if JDETEN = 1)
0: VJACKSNS < 0.1V x VSUPPLY
1: VJACKSNS ≥ 0.1V x VSUPPLY
VSUPPLY is determined by the state of MBEN and SHDN so that:
MBEN = 0 or SHDN = 0: VSUPPLY = VSPKLVDD (internal pullup)
MBEN = 1 and SHDN = 1: VSUPPLY = VMICBIAS (external pullup)
1
JKSNS
R
0
0
—
—
—
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—
Maxim Integrated │ 153
MAX98090
Ultra-Low Power Stereo Audio Codec
Quick Setup Configuration
The quick setup configuration registers provide simple
device configuration options for commonly used signal
paths and settings. Each quick setup register contains
write only, push-button configuration bits. When written
high, a quick configuration bit will internally set all other
appropriate register bits to program the device to the
selected configuration. Writing a logical low to a quick
configuration bit has no effect, and when read back all
quick configuration bits always show a logic-low.
Quick setup bits change the state of registers appropriate
to the selected configuration only. As such, they do not
remove or reset existing device settings that do not share
the same configuration registers. This allows complementary selections from several different quick configuration registers to be used together in a logical sequence
to configure the device. Do not combine multiple quick
setup bits that configure either the same section or any
shared data path as part of a single sequence. This type
of sequence might not produce the desired results as later
quick setup bits may overwrite registers programmed by
earlier selections.
The digital audio interface (DAI) quick setup register
(Table 79) is used to select the DAI data format. The
configurations in this register program the master mode
clock configuration register (Table 34), the DAI format
configuration register (Table 46), and the DAI TDM control
register (Table 47).
The playback path quick setup register (Table 80) is
used to configure the digital playback path and to select
and program an analog output. The configuration bits in
this register program the DAI I/O configuration register
(Table 45), the output enable register (Table 8), and the
selected analog output mixer, volume, and control registers (headphones, receiver, speaker, or line output).
Table 79. Digital Audio Interface (DAI) Quick Setup Register
ADDRESS: 0x06
DESCRIPTION
BIT
NAME
TYPE
POR
7
—
—
—
—
6
—
—
—
—
5
RJ_M
W
0
Sets up DAI for right-justified master mode operation.
4
RJ_S
W
0
Sets up DAI for right-justified slave mode operation.
3
LJ_M
W
0
Sets up DAI for left-justified master mode operation.
2
LJ_S
W
0
Sets up DAI for left-justified slave mode operation.
1
I2S_M
W
0
Sets up DAI for I2S master mode operation.
0
I2S_S
W
0
Sets up DAI for I2S slave mode operation.
Table 80. Playback Path Quick Setup Register
ADDRESS: 0x07
BIT
DESCRIPTION
NAME
TYPE
POR
7
DIG2_HP
W
0
Sets up the DAC to headphone path.
6
DIG2_EAR
W
0
Sets up the DAC to receiver path.
5
DIG2_SPK
W
0
Sets up the DAC to speaker path
4
DIG2_LOUT
W
0
Sets up the DAC to line out path.
3
—
—
—
—
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
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Maxim Integrated │ 154
MAX98090
Ultra-Low Power Stereo Audio Codec
The analog microphone/direct input to record path quick
setup register (Table 81) is used to select and program
an analog input and to configure the digital record path.
The configuration bits in this register program the DAI I/O
configuration register (Table 45), the input enable register
(Table 7), and the appropriate input mixer, volume, and
control registers (analog microphone or direct to ADC
mixer).
The line input to record path quick setup register (Table 82)
is used to program the analog input and to configure the
digital record path. The configuration bits in this register
program the DAI I/O configuration register (Table 45), the
input enable register (Table 7), and the appropriate input
mixer, volume, and control registers (single-ended or differential line input).
Table 81. Analog Microphone/Direct Input to Record Path Quick Setup Register
ADDRESS: 0x08
DESCRIPTION
BIT
NAME
TYPE
POR
7
IN12_MIC1
W
0
Sets up the IN1/IN2 to microphone 1 to ADCL path
6
IN34_MIC2
W
0
Sets up the IN3/IN4 to microphone 2 to ADCR path
5
—
—
—
—
4
—
—
—
—
3
IN12_DADC
W
0
Sets up the IN1/IN2 direct to ADCL path
2
IN34_DADC
W
0
Sets up the IN3/IN4 direct to ADCR path
1
IN56_DADC
W
0
Sets up the IN5/IN6 direct to ADCL path (WLP only)
0
—
—
—
—
Table 82. Line Input to Record Path Quick Setup Register
ADDRESS: 0x09
DESCRIPTION
BIT
NAME
TYPE
POR
7
IN12S_AB
W
0
Sets up stereo single-ended record: IN1/IN2 to line in A/B to ADCL/R
6
IN34S_AB
W
0
Sets up stereo single-ended record: IN3/IN4 to line in A/B to ADCL/R
5
IN56S_AB
W
0
Sets up stereo single-ended record: IN5/IN6 to line in A/B to ADCL/R (WLP only)
4
IN34D_A
W
0
Sets up mono differential record: IN3/IN4 to line in A to ADCL
3
IN65D_B
W
0
Sets up mono differential record: IN6/IN5 to line in B to ADCR (WLP only)
2
—
—
—
—
1
—
—
—
—
0
—
—
—
—
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Maxim Integrated │ 155
MAX98090
Ultra-Low Power Stereo Audio Codec
The analog microphone input to analog output quick
setup register (Table 83) is used to configure the analog
input and to select and program an analog output. The
configuration bits in this register program the input enable
register (Table 7), the output enable register (Table 8),
and the appropriate input and output mixer, volume, and
control registers (analog microphone and either the headphones, speaker, receiver, or line output).
The line input to analog output quick setup register
(Table 84) is used to configure the analog input and to
select and program an analog output. The configuration
bits in this register program the input enable register
(Table 7), the output enable register (Table 8), and the
appropriate input and output mixer, volume, and control
registers (line input and either the headphones, speaker,
receiver, or line output).
Table 83. Analog Microphone Input to Analog Output Quick Setup Register
ADDRESS: 0x0A
DESCRIPTION
BIT
NAME
TYPE
POR
7
IN12_M1HPL
W
0
Sets up the IN1/IN2 differential to microphone 1 to headphone left path
6
IN12_M1SPKL
W
0
Sets up the IN1/IN2 differential to microphone 1 to speaker left path
5
IN12_M1EAR
W
0
Sets up the IN1/IN2 differential to microphone 1 to receiver path
4
IN12_M1LOUTL
W
0
Sets up the IN1/IN2 differential to microphone 1 to lineout left path
3
IN34_M2HPR
W
0
Sets up the IN3/IN4 differential to microphone 2 to headphone right path
2
IN34_M2SPKR
W
0
Sets up the IN3/IN4 differential to microphone 2 to speaker right path
1
IN34_M2EAR
W
0
Sets up the IN3/IN4 differential to microphone 2 to receiver path
0
IN34_M2LOUTR
W
0
Sets up the IN3/IN4 differential to microphone 2 to lineout right path
Table 84. Line Input to Analog Output Quick Setup Register
ADDRESS: 0x0B
BIT
DESCRIPTION
NAME
TYPE
POR
7
IN12S_ABHP
W
0
Sets up the IN1/IN2 single ended to line In A/B to headphone L/R path
6
IN34D_ASPKL
W
0
Sets up the IN3/IN4 differential to line in A to speaker left path
5
IN34D_AEAR
W
0
Sets up the IN3/IN4 differential to line in A to receiver path
4
IN12S_ABLOUT
W
0
Sets up the IN1/IN2 single ended to line in A/B to lineout L/R path
3
IN34S_ABHP
W
0
Sets up the IN3/IN4 single ended to line in A/B to headphone L/R path
2
IN65D_BSPKR
W
0
Sets up the IN6/IN5 differential to line in B to speaker right path (WLP only)
1
IN65D_BEAR
W
0
Sets up the IN6/IN5 differential to line in B to receiver path (WLP only)
0
IN34S_ABLOUT
W
0
Sets up the IN3/IN4 single ended to line in A/B to lineout L/R path
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Maxim Integrated │ 156
MAX98090
Ultra-Low Power Stereo Audio Codec
Device Status Flags
The device uses register 0x01 (Table 85) and IRQ to report
the status of various device functions. The status register
bits are set when their respective events occur, and cleared
upon reading the register. Device status can be determined
either by polling register 0x01, or by configuring IRQ to pull
low when specific events occur. IRQ is an open-drain output that requires a pullup resistor (10kΩ nominal) for proper
operation. When first exiting shutdown (into normal operation), other status flags may assert based on the device
settings, register sequencing, and clock sequencing.
Status Flag Masking
Register 0x03, the device status interrupt mask register
(Table 86) determines which bits in the device status interrupt register (Table 85) can trigger a hardware interrupt
Table 85. Device Status Interrupt Register
ADDRESS: 0x01
BIT
7
6
NAME
CLD
SLD
TYPE
CoR
CoR
POR
DESCRIPTION
0
Clipping Detect Flag
0: No clipping has occurred.
1: Digital record / playback clipping has occurred.
CLD asserts when the digital record or playback path is clipping due to signal amplitude
exceeding full-scale. This condition is detected at the record path gain control output
(AVLG/AVRG), the playback path gain control output (DVG), and the parametric equalizer
output. To resolve, adjust the gain settings near these detection points.
0
Slew Level Detect Flag
0: No volume slewing sequences have completed.
1: All volume / level slewing complete.
SLD asserts when any one (or more) of the programmable-gain analog output volume
controllers or digital level control arrays has completed slewing from a previous setting
to a new programmed setting. If multiple settings are changed at the same time, in either
the analog or digital domain, the SLD flag will assert only after the last slew is completed.
SLD also asserts when the serial interface soft-start or soft-stop process has completed.
5
ULK
CoR
0
Digital Audio Interface (DAI) Phase Locked Loop (PLL) Unlock Flag
0: PLL is locked (if enabled and operating properly).
1: PLL is not locked (if enabled and operating properly).
ULK reports that the digital audio phase-locked loop for DAI is not locked. This condition
only occurs in slave mode when the deviation on LRCLK relative to PCLK exceeds the
lock on range (approximately 4 PCLK periods). This condition can also occur if PCLK
is running and LRCLK has been stopped outside of shutdown. Deviation in BCLK (or
shutting it down) will never trigger a ULK assertion. DAI input and output data may not be
processed / clocked correctly if a ULK event occurs.
4
—
—
—
—
3
—
—
—
—
2
JDET
CoR
0
Jack Configuration Change Flag
0: No change in jack configuration.
1: Jack configuration has changed.
JDET asserts anytime jack detection is enabled, and either LSNS or JKSNS changes
state (Table 78). If jack detection is enabled, JDET will assert correctly even while the
device is in the shutdown state. This allows JDET to generate wake on insert interrupts.
1
DRCACT
CoR
0
DRC Compression Flag
0: The DRC is either disabled or not in the compression region.
1: The DRC is operating in the compression region.
0
DRCCLP
CoR
0
DRC Clipping Flag
0: The DRC is either disabled or no clipping has occurred.
1: DRC clipping has occurred.
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Maxim Integrated │ 157
MAX98090
Ultra-Low Power Stereo Audio Codec
on IRQ (assert low). By default, all of the device status
interrupts (except JDET) only set the corresponding
status bit and do not generate a hardware interrupt. Set
the corresponding bit high in the mask register to enable
hardware interrupts.
Device Revision Identification
The device provides a Revision ID Number register to
allow the software to identify the current version of the
device. The current device revision ID value is 0x43.
Table 86. Device Status Interrupt Mask Register
ADDRESS: 0x03
DESCRIPTION
BIT
NAME
TYPE
POR
7
ICLD
R/W
0
Clipping Detect Interrupt Enable
0: Clipping detection only sets CLD (0x01[7]).
1: Clipping detection triggers IRQ and sets CLD (0x02[7]).
6
ISLD
R/W
0
Slew Level Detect Interrupt Enable
0: Slew level detection only sets SLD (0x01[6]).
1: Slew level detection triggers IRQ and sets SLD (0x02[6]).
5
IULK
R/W
0
Digital PLL Unlock Interrupt Enable
0: PLL Unlock Condition only sets ULK (0x01[5]).
1: PLL Unlock Condition triggers IRQ and sets ULK (0x02[5]).
4
—
—
—
—
3
—
—
—
—
2
IJDET
R/W
1
Jack Configuration Change Interrupt Enable
0: Changes in headset configuration only sets JDET (0x01[2]).
1: Changes in headset configuration triggers IRQ and sets JDET (0x01[2]).
1
IDRCACT
R/W
0
DRC Compression Interrupt Enable
0: DRC compression only sets DRCACT (0x01[1]).
1: DRC compression triggers IRQ and sets DRCACT (0x01[1]).
0
IDRCCLP
R/W
0
DRC Clipping Interrupt Enable
0: DRC clipping only sets DRCCLP (0x01[0]).
1: DRC clipping triggers IRQ and sets DRCCLP (0x01[0]).
Table 87. Revision ID Number Register
ADDRESS: 0xFF
BIT
NAME
TYPE
POR
7
0
6
1
5
0
4
3
REV_ID[7:0]
R
0
0
2
0
1
1
0
1
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DESCRIPTION
Read Back the Revision ID of the Device
The current revision ID is 0x43.
Maxim Integrated │ 158
MAX98090
Ultra-Low Power Stereo Audio Codec
I2C Serial Interface
Bit Transfer
The MAX98090 features an I2C/SMBus-compatible,
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL
facilitate communication between the MAX98090 and the
master at clock rates up to 400kHz. Figure 3 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX98090 by transmitting the
proper slave address followed by the register address and
then the data word.
Each transmit sequence is framed by a START (S) or
REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX98090 is 8 bits long
and is followed by an acknowledge clock pulse. A master
reading data from the MAX98090 transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX98090 transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence
is framed by a START (S) or REPEATED START (Sr)
condition, a not acknowledge, and a STOP (P) condition.
SDA operates as both an input and an open-drain output.
A pullup resistor, typically greater than 500Ω, is required
on SDA. SCL operates only as an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there are
multiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX98090 from high voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Table 88. Device I2C Slave Address
PART NUMBER
READ ADDRESS
WRITE ADDRESS
MAX98090A
0x21
0x20
MAX98090B
0x23
0x22
S
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are control signals. See the START and STOP Conditions section.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high. A START condition
from the master signals the beginning of a transmission
to the MAX98090. The master terminates transmission,
and frees the bus, by issuing a STOP condition. The bus
remains active if a REPEATED START condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX98090 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the
MAX98090A, the seven most significant bits are 0010000.
Setting the read/write bit to 1 (slave address = 0x21)
configures the MAX98090A for read mode. Setting the
read/write bit to 0 (slave address = 0x20) configures the
MAX98090A for write mode. The address is the first byte
of information sent to the MAX98090 after the START
condition. Similarly, for the MAX98090B, the seven most
significant bits are 0010001. Setting the read/write bit to
1 (slave address = 0x23) configures the MAX98090B for
read mode. Setting the read/write bit to 0 (slave address
= 0x22) configures the MAX98090B for write mode. The
slave address are summarized in Table 88.
Sr
P
SCL
SDA
Figure 47. START, STOP, and REPEATED START Conditions
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Maxim Integrated │ 159
MAX98090
Ultra-Low Power Stereo Audio Codec
Acknowledge
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX98090, followed
by a STOP condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX98090 uses to handshake receipt each byte of data
when in write mode. The MAX98090 pulls down SDA
during the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when the
MAX98090 is in read mode. An acknowledge is sent by
Write Data Format
A write to the MAX98090 includes transmission of a
START condition, the slave address with the R /W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 49 illustrates the proper frame format
for writing one byte of data to the MAX98090. Figure 50
illustrates the frame format for writing n-bytes of data to
the MAX98090.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
2
1
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 48. Acknowledge Timing
ACKNOWLEDGE FROM MAX98090
B7
SLAVE ADDRESS
S
O
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM MAX98090
ACKNOWLEDGE FROM MAX98090
A
A
REGISTER ADDRESS
DATA BYTE
A
P
1 BYTE
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 49. Writing One Byte of Data to the MAX98090
ACKNOWLEDGE FROM MAX98090
ACKNOWLEDGE FROM MAX98090
S
SLAVE ADDRESS
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX98090
ACKNOWLEDGE FROM MAX98090
O
A
REGISTER ADDRESS
R/W
A
DATA BYTE 1
1 BYTE
B7 B6 B5 B4 B3 B2 B1 B0
A
DATA BYTE n
A
P
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 50. Writing n-Bytes of Data to the MAX98090
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Maxim Integrated │ 160
MAX98090
Ultra-Low Power Stereo Audio Codec
The slave address with the R /W bit set to 0 indicates that
the master intends to write data to the MAX98090. The
MAX98090 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the MAX98090’s internal register address pointer. The
pointer tells the MAX98090 where to write the next byte
of data. An acknowledge pulse is sent by the MAX98090
upon receipt of the address pointer data.
The third byte sent to the MAX98090 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX98090 signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This autoincrement feature allows a master to write to sequential
registers within one continuous frame. The master signals
the end of transmission by issuing a STOP condition.
Register addresses greater than 0xE7 are reserved. Do
not write to these addresses.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX98090 acknowledges receipt
of its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read command resets the address pointer to register 0x00.
ACKNOWLEDGE FROM MAX98090
S
O
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX98090
A
The address pointer can be preset to a specific register
before a read command is issued. The master presets the
address pointer by first sending the MAX98090’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The
MAX98090 then transmits the contents of the specified
register, and the address pointer autoincrements after
transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition.
Figure 51 illustrates the frame format for reading one byte
from the MAX98090. Figure 52 illustrates the frame format for reading multiple bytes from the MAX98090.
ACKNOWLEDGE FROM MAX98090
A Sr
REGISTER ADDRESS
The first byte transmitted from the MAX98090 is the contents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte to
be read will be from register 0x00.
A
R/W
REPEATED START
R/W
1
SLAVE ADDRESS
NOT ACKNOWLEDGE FROM MASTER
DATA BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 51. Reading One Byte of Data from the MAX98090
ACKNOWLEDGE FROM MAX98090
S
SLAVE ADDRESS
R/W
O
ACKNOWLEDGE FROM MAX98090
A
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX98090
A Sr
REPEATED START
SLAVE ADDRESS
1
R/W
A
DATA BYTE
A
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 52. Reading n-Bytes of Data from the MAX98090
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Maxim Integrated │ 161
MAX98090
Ultra-Low Power Stereo Audio Codec
Applications Information
Typical Application Circuits
Figures 53 and 54 are two example application circuits for the device. The external components shown are the minimum
required for the device to operate. Additional application specific components might be required.
1.8V
0.1µF
1µF
AVDD
1.8V
1.2V
1µF 1µF
10µF
HPVDD
DVDDIO
3.7V
1µF
DVDD
10µF
1µF
SPKLVDD*
SPKLVDD*
2.2µF
REF
10kΩ
CONTROLLER
INTERUPT
1µF
IRQ
VBIAS
SDA
I2C INTERFACE
SCL
MASTER CLOCK
(10MHz TO 60MHz)
MCLK
RCVP/LOUTL
16Ω/
32Ω
RCVN/LOUTR
BCLK
LRCLK
DIGITAL AUDIO
INTERFACE
PORT (DAI)
SPKLP
SPKLN
SDIN
RECEIVER/
LINE OUTPUT
(RECEIVER
BTL MODE)
4Ω/
8Ω
LEFT
SPEAKER
OUTPUT
4Ω/
8Ω
RIGHT
SPEAKER
OUTPUT
SDOUT
SPKRP
MICBIAS
SPKRN
MAX98090
2.2kΩ
1µF
IN1/DMD
ANALOG
SINGLE-ENDED
MICROPHONE
1µF
HPL
IN2/DMC
HEADPHONE
OUTPUT JACK
HPR
MICBIAS
HPSNS
1kΩ
1µF
IN3
ANALOG
DIFFERENTIAL
MICROPHONE
1µF
IN4
JACKSNS
1kΩ
2.2kΩ
MICBIAS
1µ F
LINE INPUT/
EXTERNAL
MICROPHONE
IN5*
1µF
MICBIAS
1µF
IN6*
AGND
HPGND
DGND
SPKLGND SPKRGND CPVDD
C1N
CPVSS
1µF
1µF
C1P
1µF
*IN5 AND IN6 ARE WLP PACKAGE ONLY. SPKLVDD/SPKRVDD ARE TITLED SPKVDD ON THE WLP PACKAGE (BYPASS EACH SPKVDD AS SHOWN).
Figure 53. Typical Application Circuit with Analog Microphone Inputs and Receiver Output
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Maxim Integrated │ 162
MAX98090
Ultra-Low Power Stereo Audio Codec
1.8V
1.2V
0.1µF
1µF
AVDD
1.8V
1µF
10µF
HPVDD
1µF
DVDDIO
3.7V
1µF
DVDD
10µF
1µF
SPKLVDD*
SPKRVDD*
2.2µF
REF
10kΩ
1µF
VBIAS
IRQ
CONTROLLER
INTERUPT
SDA
I2C INTERFACE
1µF
MASTER CLOCK
(10MHz TO 60MHz)
RECEIVER/
LINE OUTPUT
RCVP/LOUTL
SCL
1µF
MCLK
(SINGLE-ENDED
LINE OUT MODE)
RCVN/LOUTR
BCLK
SPKLP
LRCLK
DIGITAL AUDIO
INTERFACE
PORT (DAI)
SPKLN
SDIN
LEFT
SPEAKER
OUTPUT
4Ω/
8Ω
RIGHT
SPEAKER
OUTPUT
SDOUT
MAX98090
SPKRP
SPKRN
DIGITAL
MICROPHONE 1
4Ω/
8Ω
DATA
IN1/DMD
CLOCK
HPL
HEADPHONE
OUTPUT JACK
HPR
DIGITAL
MICROPHONE 2
DATA
HPSNS
CLOCK
IN2/DMC
1µF
DIFFERENTIAL
LINE INPUT
IN3
JACKSNS
1µF
IN4
2.2kΩ
1µF
DIFFERENTIAL
LINE INPUT
MICBIAS
IN5*
1µF
1µF
IN6*
AGND
HPGND
DGND
SPKLGND SPKRGND
CPVSS
CPVDD
1µF
C1N
1µF
C1P
1µF
*IN5 AND IN6 ARE WLP PACKAGE ONLY. SPKLVDD/SPKRVDD ARE TITLED SPKVDD ON THE WLP PACKAGE (BYPASS EACH SPKVDD AS SHOWN).
Figure 54. Typical Application Circuit with Digital Microphone Input and Stereo Line Outputs
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Maxim Integrated │ 163
MAX98090
Ultra-Low Power Stereo Audio Codec
Startup/Shutdown Register Sequencing
To ensure proper device initialization and minimal clickand-pop, program the devices control registers in the
correct order. To shut down the device, simply set
SHDN = 0. Table 89 details an example startup sequence
for the device. To minimize click and pop on the analog
output drivers (headphones, speakers, receiver, and line
outputs), the output drivers should be powered using the
following sequence:
1) Prior to powering the device (SHDN = 0) and before
enabling the outputs, the output driver mute(s) should
be enabled and the PGA gain(s) should be set to their
lowest setting.
2) After all configuration settings are complete, power up
the device (SHDN = 1).
3) Enable any analog outputs that are part of the desired
configuration.
4) Disable the mute on each respective analog output.
5) If volume smoothing is disabled (Table 75), ramp the
volume up, one register step at a time, from the minimum setting until the desired volume (gain) is reached
(this sequence is part of the example in Table 89). If
volume smoothing is enabled, this sequence is automatically implemented and the desired volume (gain)
can be programmed in a single step.
While many configuration options and settings can be
changed while the device is operating (SHDN = 1),
some settings should only be adjusted with the device
in shutdown (SHDN = 0). Table 90 lists the registers and
bits that should not be changed during active operation.
Changing these settings during normal operation (SHDN
= 1) can compromise device stability and performance
specifications. All external clocks (MCLK in master mode
and MCLK, LRCLK, and BCLK in slave mode) must
be running and stable before the device is taken out of
shutdown. If the clocks are enabled or changed while
the device is active (not in shutdown) phase errors and
audible glitches may be introduced.
Table 89. Detailed Device Startup Sequence
SEQUENCE
DESCRIPTION
REGISTERS
1
Set SHDN = 0
0x45 (Default POR State)
2
Configure Clocks (also enable all external clocks)
0x1B to 0x21
3
Configure Digital Audio Interface (DAI)
0x22 to 0x25
4
Configure Digital Signal processing (DSP)
5
Load Coefficients
6
Configure Power and Bias Mode
0x17 to 0x1A, 0x26 to 0x28, 0x33 to 0x36, 0x41
0x46 to 0xBD
0x42 to 0x44
7
Configure Analog Mixers
0x0D, 0x15, 0x16, 0x29, 0x2A, 0x2B, 0x2E,
0x2F, 0x37, 0x3A
8
Configure Analog Gain and Volume Controls. To Minimize Click
and Pop for Analog Outputs, Enable Mute and Set the Output
PGAs to the minimum gain setting.
0x0E to 0x11, 0x2B to 0x2D, 0x30 to 0x32,
0x38, 0x39, 0x3B, 0x3C
9
Configure Miscellaneous Functions
11
Set SHDN = 1 (Power Up)
0x03, 0x12, 0x13, 0x14, 0x40
0x45
10
Enable Desired Functions
0x3D to 0x3F
11
Disable Mute on Analog Output Drivers
12
For all Analog Output Drivers, if Gain Smoothing is Disabled
Ramp the Gain up One Volume Step per Write until the Desired
Gain is Reached. If it is Enabled, Program the Desired Gain in a
Single Step.
0x2C, 0x2D, 0x31, 0x32, 0x39, 0x3C
0x30 to 0x32, 0x38,
0x39, 0x3B, 0x3C
Table 90. Register Changes that Require SHDN = 0
DESCRIPTION
Clock Control and Quick Configuration Registers
DAC/ADC Enables (only these bits)
Bias/DAC/ADC Control
Digital Signal Processing Enables and Coefficients
Digital Microphone Configuration
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REGISTER
0x04 to 0x0B, 0x1B to 0x26
0x3E, 0x3F
0x42 to 0x44
0x33 to 0x35, 0x41, 0x46 to 0xBD
0x13, 0x14
Maxim Integrated │ 164
MAX98090
Ultra-Low Power Stereo Audio Codec
External Supply Sequencing
When powering-up the device, there is no requirement
for the sequence with which each supply is applied. All
supplies must be brought to their nominal voltage before
the part can be configured for proper operation. The part
should be placed into software shutdown before any
supplies are removed to avoid audible artifacts. Register
settings are retained as long as supply voltages are kept
above the power-on-reset voltages listed in Table 91.
Table 91. Power-On Reset Voltage
SUPPLY
POR VOLTAGE
AVDD
1.0V
HPVDD
NO POR
DVDD
1.0V
DVDDIO
NO POR
SPKVDD
1.2V
Component Selection
AC-Coupling Capacitors
An input capacitor, CIN, in conjunction with the input
impedance of the device line inputs forms a highpass
filter that removes the DC bias from an incoming analog
signal. The AC-coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level.
Assuming very low source impedance (comparatively),
the -3dB point of the highpass filter is given by:
f −3dB =
1
2π × R IN × C IN
Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality, use capacitors
whose dielectrics have low-voltage coefficients, such
as tantalum or aluminum electrolytic. Capacitors with
high-voltage coefficients, such as ceramics, can result
in increased distortion at low frequencies. If needed, line
output AC-coupling capacitor values can be calculated in
similar fashion by using the input resistance of the next
stage connected to the line output drivers.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩ for optimum
performance. Low-ESR ceramic capacitors minimize
the output resistance of the charge pump. Most surface
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
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The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the charge
pump. A value that is too small degrades the device’s
ability to provide sufficient current drive, which leads to a
loss of output voltage. Increasing the value of the flying
capacitor reduces the charge-pump output resistance to
an extent. Above 1µF, the on-resistance of the internal
switches and the ESR of external charge pump capacitors dominate.
The holding capacitor (bypassing HPVSS) value and ESR
directly affect the ripple at HPVSS. Increasing the capacitor’s value reduces output ripple. Likewise, decreasing
the ESR reduces both ripple and output resistance. Lower
capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load
Resistance graph in the Typical Operating Characteristics
section for more information.
Filterless Class D Speaker Operation
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s output. The
filters add cost, increase the solution size of the amplifier,
and can decrease efficiency and THD+N performance.
The traditional PWM scheme uses large differential output
swings (2 x SPK_VDD peak to peak) and causes large
ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency.
For typical applications (such as handsets, tablets, etc.)
where the trace length from driver the speaker is short
and low impedance, the device does not require an output
filter. The device relies on the inherent inductance of the
speaker coil and the natural filtering of both the speaker
and the human ear to recover the audio component of the
square-wave output. Eliminating the Class D output filter
results in a smaller, less costly, and more efficient solution.
In cases where the trace/wire length is long, and/or series
resistance/inductance is high, an output LC filter might be
required. In such a case, if the nominal impedance of the
load is not constant over the entire audio band, a Zobel
(impedance matching) circuit might be required.
Because the frequency of the IC’s output is well beyond
the bandwidth of most speakers, voice coil movement due
to the square-wave frequency is very small. Although this
movement is small, a speaker not designed to handle the
additional power can be damaged. For optimum results,
use a speaker with a series inductance > 10µH. Typical
8Ω speakers exhibit series inductances in the 20µH to
100µH range.
Maxim Integrated │ 165
MAX98090
Ultra-Low Power Stereo Audio Codec
EMI Considerations and Optional
Ferrite Bead Filter
Reducing trace length minimizes radiated EMI. On the
PCB, route SPKLP/SPKLN and SPKRP/SPKRN as differential pairs with the shortest trace lengths possible. This
minimizes trace loop area, and thereby, the inductance of
the circuit. If filter components are used on the speaker
outputs, minimize the trace length from any ground tied
passive components to SPK_GND to further minimize
radiated EMI.
In applications where speaker leads/wires are long
(exceeding approximately 12in), additional EMI suppression can be achieved by using a filter constructed from a
ferrite bead and a capacitor to ground (Figure 55). Use
a ferrite bead with low DC resistance, high frequency (>
600MHz) impedance between 100Ω and 600Ω, and rated
for at least 1A. The capacitor value varies based on the
ferrite bead chosen and the actual speaker lead length.
Select a capacitor less than 1nF with the value based
upon optimizing EMI performance.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers.
The device is designed specifically to reject RF signals;
however, PCB layout has a large impact on the susceptibility of the end product.
In RF applications, improvements to both layout and
component selection decreases the susceptibility to RF
noise and prevent RF signals from being demodulated
into audible noise. Trace lengths should be kept below
1/4 of the wavelength of the RF frequency of interest.
Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the device.
The wavelength (λ) in meters is given by: λ = c/f, where c
= 3 x 108 m/s, and f = the RF frequency of interest.
MAX98090
SPK_P
SPK_N
Figure 55. Optional Class D Ferrite Bead EMI Filter
HPL
HPR
HPSNS
MAX98090
JACKSNS
Figure 56. Optional Class H Output RFI Filter
Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors, as it
exhibits a frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capacitors
typically exhibit self-resonance at RF (high) frequencies.
These capacitors, when placed at the input pins, can
effectively shunt the RF noise at the inputs of the device.
For these capacitors to be effective, they must have a
low-impedance, low-inductance path to the ground plane.
Avoid using micro vias to connect to the ground plane as
these vias do not conduct well at RF frequencies. At the
Headphone outputs, additional RFI can be achieved by
using series ferrite beads with the parallel capacitors to
ground (Figure 56).
Route audio signals on inner layers of the PCB to allow
ground planes above and below to shield them from RF
interference. Ideally the top and bottom layers of the PCB
should primarily be ground planes to create effective
shielding.
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Maxim Integrated │ 166
MAX98090
Ultra-Low Power Stereo Audio Codec
LAYER 1
LAYER 2
LAYER 3
Figure 57. PCB Breakout Routing Example for WLP Package
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. When designing a PCB layout, partition
the circuitry so that the analog sections of the device are
separated from the digital sections. This ensures that the
analog audio traces are not routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect AGND,
DGND, and HPGND directly to the ground plane using the
shortest trace length possible. Proper grounding improves
audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the
analog audio signals.
Ground the bypass capacitors on MICBIAS, BIAS and
REF directly to the ground plane with minimum trace
length. Also be sure to minimize the path length to AGND,
and bypass AVDD directly to AGND. Connect all digital
I/O termination to the ground plane with minimum path
length to DGND, and bypass DVDD and DVDDIO directly
to DGND.
Place the capacitor between C1P and C1N as close as
possible to the device to minimize trace length from C1P
to C1N. Inductance and resistance added between C1P
and C1N reduce the output power of the headphone
amplifier. Bypass HPVDD, CPVDD and CPVSS with
capacitors located close to the pin with short trace lengths
to HPGND. Close decoupling of CPVDD and CPVSS
minimizes supply ripple and maximizes output power from
the headphone amplifier.
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HPSNS senses ground noise on the headphone jack and
adds the same noise to the output audio signal, thereby
making the output (headphone output, ground) noise free.
Connect HPSNS to the headphone jack shield to ensure
accurate pickup of headphone ground noise.
Bypass SPK_VDD to SPK_GND with the shortest trace
length possible and connect SPKLP, SPKLN, SPKRP, and
SPKRN to the stereo speakers using the shortest traces
possible. If filter components are used on the speaker
outputs, be sure to locate them as close as possible to the
device to ensure maximum effectiveness.
Route microphone signals from the microphone to the
device as a differential pair, ensuring that the positive
and negative signals follow the same path as closely
as possible with equal trace length. When using singleended microphones or other single-ended audio sources,
ground the negative microphone input as near to the
audio source as possible and then treat the positive and
negative traces as differential pairs.
An evaluation kit (EV Kit) is available to provide an example layout. The EV Kit allows quick setup of the device
and includes easy-to-use software allowing all internal
registers to be controlled.
Recommended PCB Routing
The IC uses a 49-bump WLP package. Figure 57 provides an example of how to connect to all active bumps
using 3 layers of the PCB. To ensure uninter­rupted
ground returns, use layer 2 as a connecting or dog-bone
layer between layer 1 and layer 3, and flood the remaining
area with a copper ground plane.
Maxim Integrated │ 167
MAX98090
Ultra-Low Power Stereo Audio Codec
Unused Pins
inputs might be enabled, then alternatively unused analog
audio inputs can be AC coupled to AGND (if component
cost and area allow it).
Table 92 shows how to connect the devices unused
pins when circuit blocks are disabled. If the system is
extremely noisy or there is a concern that unused analog
Table 92. Unused Pin Connections
PIN NAME
CONNECTION
PIN NAME
SUPPLY PLANES
CONNECTION
ANALOG AUDIO OUTPUTS
AVDD
Always connect
HPL
Unconnected
AGND
Always connect
HPR
Unconnected
HPVDD
Always connect
HPSNS
AGND
HPGND
Always connect
SPKLP
Unconnected
DVDD
Always connect
SPKLN
Unconnected
DVDDIO
Always connect
SPKRP
Unconnected
DGND
Always connect
SPKRN
Unconnected
SPKVDD
Always connect
RCVP / LOUTL
Unconnected
SPKLVDD
Always connect
RCVN / LOUTR
Unconnected
SPKRVDD
Always connect
SPKLGND
Always connect
SDIN
DGND
SPKRGND
Always connect
SDOUT
Unconnected
MCLK
Always connect
CPVDD
Unconnected
LRCLK
DGND
CPVSS
Unconnected
BCLK
C1P
Unconnected
CHARGE PUMP
C1N
Unconnected
ANALOG AUDIO INPUTS
DIGITAL AUDIO INTERFACE
DGND
I2C INTERFACE
SCL
Always connect
SDA
Always connect
IN1/DMD
Unconnected
IN2/DMC
Unconnected
IN3
Unconnected
MICBIAS
IN4
Unconnected
JACKSNS
Unconnected
IN5
Unconnected
BIAS
Always connect
IN6
Unconnected
REF
Always connect
www.maximintegrated.com
IRQ
Unconnected
OTHER
Unconnected
Maxim Integrated │ 168
MAX98090
Ultra-Low Power Stereo Audio Codec
Ordering Information
ADDRESS
TEMP RANGE
PIN-PACKAGE
MAX98090AEWJ+T
PART
0x20
MAX98090AETL+T
0x20
-40°C to +85°C
-40°C to +85°C
40 TQFN
MAX98090BEWJ+T
0x22
-40°C to +85°C
49 WLP
MAX98090BETL+T
0x22
-40°C to +85°C
40 TQFN
49 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Chip Information
PROCESS: CMOS
www.maximintegrated.com
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
49 WLP
W493B3+2
21-0443
Refer to
Application Note
1891
40 TQFN
T4055+1
21-0140
90-0121
Maxim Integrated │ 169
MAX98090
Ultra-Low Power Stereo Audio Codec
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/13
1
2
8/13
8/14
DESCRIPTION
Initial release
PAGES
CHANGED
—
Corrected various errors
1, 9, 11, 15–17,
20–26, 30,
37–48, 50–54,
56–63, 66–68,
72, 78, 79,
82, 84–88, 91,
92, 94–96, 98,
103–105, 110,
113, 120, 121,
129, 141, 142,
146, 149, 150,
151, 158–162,
164
Corrected various errors and made various updates
10, 11, 15, 16,
28, 38–66, 70,
89–92, 100,
111–113, 118,
124, 146, 147,
149, 151, 152,
165, 168
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
© 2013 Maxim Integrated │ 170

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