User Guide PC3-ALLEGRO • CompactPCI® PlusIO CPU Card Intel

User Guide PC3-ALLEGRO • CompactPCI® PlusIO CPU Card Intel

User Guide

PC3-ALLEGRO •

CompactPCI

®

PlusIO CPU Card

Intel

®

Core™ i7-3xxx Processor Quad-Core (Ivy Bridge)

Document No. 7106 • Edition 31 • 19 June 2017

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Contents

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edition History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Trade Marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Legal Disclaimer - Liability Exclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Technical Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Performance Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Top View Component Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Front Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Front Panel Switches & Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

On-Board Connectors & Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pin Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Graphics Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

LAN Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Serial ATA Interface (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCI Express® Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Utility Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PG (Power Good) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

GP (General Purpose) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

HD (Hard Disk Activity) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

EB (Ethernet Backplane) LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Hot Swap Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Power Supply Status (DEG#, FAL#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

© EKF -2- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Mezzanine Side Board Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

CompactPCI

®

PlusIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Installing and Replacing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Installing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Removing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

EMC Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Replacement of the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Technical Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Local PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Local SMB Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Hardware Monitor LM87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Board Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Write/Read Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Read/Clear Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Read/Clear Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Read PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

GPIO Usage QM77 PCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Configuration PCI Express Switch (DS-P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Loading UEFI BIOS Setup Defaults (P-GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Manufacturer Mode Jumper (P-MFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

RTC Reset (P-RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Front Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DisplayPort Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Screw Locking Option for mDP Connectors . . . . . . . . . . . . . . . . . . . . . . . 66

VGA Video Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Mezzanine Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Expansion Interface J-EXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

High Speed Expansion Connector J-HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PCI Express® Expansion Header J-PCIE . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SDVO/DisplayPort Expansion Header J-SDVO . . . . . . . . . . . . . . . . . . . . . . 79

Pin Headers & Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Front Panel Handle Microswitch Header P-FPH . . . . . . . . . . . . . . . . . . . . . 83

PLD Programming Header P-ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Processor Debug Header XDP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

© EKF -3- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

CompactPCI

J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

CompactPCI

J2 (PlusIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

© EKF -4- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

About this Manual

This manual describes the technical aspects of the PC3-ALLEGRO, required for installation and system integration. It is intended for the experienced user only.

Edition History

21

22

23

17

18

19

20

13

14

15

16

8

9

6

7

10

11

12

3

4

5

Ed.

Contents/

Changes

1

2

User Manual PC3-ALLEGRO, english, preliminary edition

Text #7106, File: pc3_ug.wpd

Error corrected on pg.44 , upper and lower table

24

25

26

27

Reworked section “Watchdog”

Power Requirements updated

Reworked sections Serial ATA Interface and High Speed Expansion

Connector J-HSE

Modified block diagram - RIO SATA configured to 3G by default

Table Feature Summary updated

Table Power Requirements updated

Table CompactPCI J2 updated

Added list of local pci devices, SDVO option removed on J-SDVO

Added photos PC3 w. PCL Side Card Assembly

Added photo PC3 w. PCL Side Card Assembly Exploded View

Added ‘Board Control and Status Registers’, updated links

Added note on operation in systems with a 64-bit CompactPCI ® backplane

Added additional function of HD LED

Added Power Requirements

Clarified resetting of UEFI BIOS settings to factory defaults

Universal V(I/O) on CPCI Interface

Added power requirements

Updated description of BCSR Status Registers 0 and 1, cleanup section

“Watchdog”

Added photos PC3-ALLEGRO with C47-MSATA & C48-M2

Updated LM87 Information

Table 'Feature Summary' BIOS replaced by Firmware (UEFI)

Table 'Reference Documents' UEFI & ACPI specifications

Removed redundant Operating Conditions

4HP Front panel illustration fixed marking for backplane Ethernet LED = EB, added 8HP and 12HP front panel illustrations

Table 'Feature Summary', added RT OS support

Completed Information about SATA on J-HSE

Author mib gn mib mib gn mib mib mib mib jj jj mib mib mib jj jj mib gn mib mib jj mib jj mib jj jj mib

Date

2013-09-09

2013-09-25

2013-12-06

2013-12-11

2014-01-10

15 January 2014

17 February 2014

3 April 2014

20 June 2014

21 July 2014

31 July 2014

11 August 2014

21 August 2014

4 September 2014

18 September 2014

12 December 2014

16 January 2015

27 January 2015

5 February 2015

7 April 2015

27 May 2015

28 May 2015

14 August 2015

3 September 2015

23 September 2015

30 September 2015

22 January 2016

© EKF -5- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Ed.

Contents/

Changes

28

29

Fixed typo in block diagram regarding J2 PCIe resources

Screw locking options for mDP connectors

30

31

Added Celeron® CPU to table 'Feature Summary'

Added photo USB cable connector fixation

Author jj jj jj jj

Date

29 November 2016

13 December 2016

6 April 2017

19 June 2017

Related Documents

Related Information PC3-ALLEGRO

PC3-ALLEGRO Home

PC3-ALLEGRO Product Information www.ekf.com/p/pc3/pc3.html

www.ekf.com/p/pc3/pc3_pi.pdf

Nomenclature

Signal names used herein with an attached '#' designate active low lines.

Trade Marks

Some terms used herein are property of their respective owners, e.g.

<

<

<

<

Chief River, Ivy Bridge, Panther Point, Core i7: ® Intel

CompactPCI, CompactPCI PlusIO, CompactPCI Serial: ® PICMG

Windows XP, Windows 7: ® Microsoft

EKF, ekf system: ® EKF

EKF does not claim this list to be complete.

Legal Disclaimer - Liability Exclusion

This manual has been edited as carefully as possible. We apologize for any potential mistake.

Information provided herein is designated exclusively to the proficient user (system integrator, engineer). EKF can accept no responsibility for any damage caused by the use of this manual.

© EKF -6- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Standards

Term

CFast™

CompactPCI ®

CompactPCI ®

PlusIO

CompactPCI ®

Serial

DisplayPort

DVI

Ethernet

LPC

Reference Documents

Document

CFast™ Specification Rev. 1.0

CompactPCI Specification, PICMG® 2.0 R3.0, Oct. 1, 1999

CompactPCI PlusIO Specification, PICMG® 2.30 R1.0,

November 11, 2009

CompactPCI Serial Specification, PICMG® CPCI-S.0 R1.0,

March 2, 2011

VESA DisplayPort Standard Version 1.1a

January 11, 2008

VESA Mini DisplayPort Connector Standard Version 1

October 26, 2009

Digital Visual Interface Rev. 1.0

Digital Display Working Group

IEEE Std 802.3, 2000 Edition

Low Pin Count Interface Specification, Revision 1.1

HD Audio

PCI Express®

SATA

UEFI

USB

High Definition Audio Specification Rev.1.0

PCI Express

®

Base Specification 3.0

Serial ATA 2.5/2.6 Specification

Serial ATA 3.0 & 3.1 Specification

Unified Extensible Firmware Interface

UEFI Specification Version 2.5

ACPI Specification Version 6.0

Universal Serial Bus 3.0 Specification, Revision 1.0

November 12, 2008

Origin www.compactflash.org

www.picmg.org

www.picmg.org

www.picmg.org

www.vesa.org

www.ddwg.org

standards.ieee.org

developer.intel.com/design/ chipsets/industry/lpc.htm

www.intel.com/design/chipsets/ hdaudio.htm

www.pcisig.com

www.sata-io.org

www.uefi.org

www.usb.org

© EKF -7- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Overview

The PC3-ALLEGRO is a rich featured high performance 4HP/3U CompactPCI

®

PlusIO CPU board, equipped with a 3

rd

Generation Intel

®

Core™ i7 Ivy Bridge + ECC (dual- or quad-core) mobile processor based on 22nm technology.

The PC3-ALLEGRO front panel is provided with two Gigabit Ethernet jacks, two USB 3.0

receptacles, and two Mini-DisplayPort connectors for attachment of high resolution digital displays, configured e.g. as extended desktop (option VGA).

The PC3-ALLEGRO is equipped with up to 16GB

RAM with ECC support. 8GB memory-down are provided for rugged applications, and another

8GB are available via the DDR3 ECC SO-DIMM socket. The PC3-ALLEGRO backplane connectors comply with the PICMG

®

CompactPCI

®

PlusIO system slot specification, suitable for a rear I/O module or hybrid CompactPCI

®

Serial Systems.

Several low profile mezzanine modules are available as mass storage solution.

CompactPCI® PlusIO (PICMG 2.30) is a new standard for rear I/O across J2, specified by the

PICMG®. High speed signal lines (PCI Express®,

SATA, Gigabit Ethernet and USB) are passed from the PC3-ALLEGRO through the special

UHM connector to the backplane, for usage either on a PlusIO rear I/O transition module, or

CompactPCI® Serial card slots.

CompactPCI® Serial (PICMG CPCIS.0) defines a completely new card slot, based on PCI

Express®, SATA, Gigabit Ethernet and USB serial data lines. On a hybrid backplane, both card styles can reside, CompactPCI® and

CompactPCI® Serial, with the PC3-ALLEGRO in the middle as system slot controller for both backplane segments.

The PC3-ALLEGRO is equipped with a set of local expansion interface connectors, which can be optionally used to attach a mezzanine side board. A variety of expansion cards is available, e.g. providing legacy I/O and additional PCI

Express® based I/O controllers such as SATA,

USB 3.0 and Gigabit Ethernet, or a third video output. Most mezzanine side cards can accommodate in addition a 2.5-inch drive.

Typically, the PC3-ALLEGRO and the related side card would come as a readily assembled 8HP unit. As an alternate, low profile Flash based mezzanine storage modules are available that fit on the PC3-ALLEGRO while maintaining the

4HP profile. The C48-M2 module e.g. is equipped with two M.2 SATA Solid State Drives

(SSD), suitable for installation of any popular operating system.

© EKF -8- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

© EKF -9- ekf.com

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User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Technical Features

Feature Summary

Feature Summary

CompactPCI® PlusIO (PICMG® CPCI 2.30) System Slot Controller

J1 Connector for Full CompactPCI® Classic 32-Bit Support, universal V(I/O) (3.3V or 5V)

J2 Connector (UHM High Speed) for CompactPCI® PlusIO Support

4 x PCIe

4 x SATA

4 x USB

2 x GbE

<

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Proven Intel® Mobile CPU Technology

3rd Generation Intel® Core™ Mobile + ECC CPU, Code Name Ivy Bridge i7-3612QE Processor 2.1GHz • 35W TDP Standard Voltage Quad-Core i7-3555LE Processor 2.5GHz • 25W TDP Low Voltage Dual-Core i7-3517UE Processor 1.7GHz • 17W TDP Ultra Low Voltage Dual-Core i5-3610ME Processor 2.7GHz • 35W TDP Standard Voltage Dual-Core i3-3120ME Processor 2.4GHz • 35W TDP Standard Voltage Dual-Core i3-3217UE Processor 1.6GHz • 17W TDP Ultra Low Voltage Dual-Core

Celeron® 1047UE Processor 1.4GHz • 17W TDP Ultra Low Voltage Dual-Core

Intel®

QM77 Panther Point

Platform Controller Hub (PCH)

<

<

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Integrated HD Graphics Engine, 3 Independent Displays, Enhanced Media Processing

Up to 3 Display Configuration (Front Panel: Dual mDP or Single VGA Connector Option)

Max Resolution 2560 x 1600 (DisplayPort), 1920 x 1200 (VGA)

3rd Display via Side Card PCS-BALLET

<

<

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<

<

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<

<

<

<

Integrated Memory Controller up to 16GB DDR3 +ECC 1600

DDR3 +ECC Soldered Memory up to 8GB

DDR3 +ECC SO-DIMM Memory Module Socket up to 8GB

SATA 6G &3G for Mass Storage

2 + 2 SATA Channels 6Gbps/3Gbps for Mezzanine Storage Modules (Connector HSE)

CompactFlash® Card with C40-SCFA Mezzanine Module Option (4HP Maintained)

CFast™ Card with C41-CFAST Mezzanine Module Option (4HP Profile Maintained)

SATA 1.8-Inch Solid State Drive with C42-SATA Mezzanine Card Option (4HP Maintained)

Dual mSATA Modules with C47-MSATA RAID Mezzanine Card Option (4HP Maintained)

4 x SATA RAID Channels to UHM Connector J2, for RIO Module or CPCI Serial Backplane Usage, limited to

3G SATA by CPCI PlusIO Specification

Hardware RAID Enabled by Marvell 88SE9230 ARM Powered Subsystem

RAID Configuration Level 0/1/10

© EKF -10- ekf.com

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User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Feature Summary

USB 3.0 XHCI SuperSpeed & USB 2.0 EHCI Support

2 x USB 3.0 F/P Connectors

6 x USB 2.0 to Mezzanine Connectors

4 x USB 2.0 to J2 (Backplane)

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Gigabit Ethernet Controllers

2 x GbE F/P RJ-45 Jacks

2 x GbE to Backplane Connector J2

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PCI Express® Based Design for Component Interconnect

PCI Express® for System Expansion by Mezzanine and Backplane or RIO

4 x PCI Express® Gen2 Lanes to CPCI PlusIO Backplane J2 Connector

4 x PCI Express® Gen2 Lanes to Mezzanine Connector

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Set of Mezzanine Connectors for Storage Module or Side Card

Legacy I/O Mezzanine Expansion Connector EXP (USB, HD Audio, LPC)

High Speed I/O Mezzanine Expansion Connector HSE (4 x SATA, 4 x USB)

PCI Express® Mezzanine Expansion Connector PCIE (4 Lanes)

Third Display Mezzanine Expansion Connector DP

Variety of Mezzanine Expansion Boards (Side Cards) Available

Most Mezzanines Optionally Equipped with 2.5-Inch Single- or Dual-Drive

Low Profile Storage Modules Maintain 4HP F/P Width

Side Cards with Additional Front Panel I/O Connectors (8HP & 12HP Assembly

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Phoenix® UEFI (Unified Extensible Firmware Interface) with CSM*

Fully Customizable by EKF

Secure Boot on Request

Windows®, Linux and other (RT)OS' Supported

* CSM (Compatibility Support Module) emulates a legacy BIOS environment, which allows to boot a legacy operating system such as DOS, 32-bit Windows and some RTOS'

<

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Best Suited e.g. for Industrial, Transportation & Instrumentation Applications

Long Term Availability

Rugged Solution

Coating, Sealing, Underfilling Available on Request

© EKF -11- ekf.com

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User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Feature Summary

RT OS Board Support Packages & Driver

LynxOS - on request

On Time RTOS-32 - on request

OS-9 - on request

QNX 4.x, 6.x - on request

Real-Time Linux (RT Patch) - on request

RTX - on request

VxWorks 6.9 - under development

VxWorks 7.0 - on request

Others - on request

© EKF -12- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Performance Rating

Performance Rating tbd

Operating Conditions

Thermal &

Environmental

Conditions

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Operating Conditions

Operating Temperature 0°C to +70°C (-40°C to +85°C on Request)

Storage temperature: -40°C to +85°C, max. Gradient 5°C/min

Humidity 5% ... 95% RH non Condensing

Altitude -300m ... +3000m

Shock 15g 0.33ms, 6g 6ms

Vibration 1g 5-2000Hz

EC Regulations <

<

MTBF

EN55022, EN55024, EN60950-1 (UL60950-1/IEC60950-1)

2002/95/EC (RoHS)

104 x 10

3

h (11.9 years) @ 50° C

Power Requirements

Board

PC3-68XX

PC3-48XX

PC3-22XX

PC3-046X

3)

Power Requirements

Load Current [A] at +3.3V (+0.17V/-0.1V) Load Current [A] at +5V (+0.25V/-0.15V)

Maximum Performance

LFM / HFM / Turbo

1)

5.0 / 5.0 / 5.0

2)

4.1 / 4.1 / 4.1 2)

TBD / TBD / TBD

2)

- / 2.65 / -

2)

Windows 7 Idle

LFM / HFM / Turbo

1)

2.7 / 2.7 / 2.7

2)

2.7 / 2.7 / 2.7 2)

TBD / TBD / TBD

2)

1.9 / 1.9 / -

2)

Maximum Performance

LFM / HFM / Turbo

1)

6.9 / 7.1 / 8.7

4.3 / 5.1 / 5.5

TBD / TBD / TBD

- / 2.45 / -

Windows 7 Idle

LFM / HFM / Turbo

1)

0.8 / 0.8 / 0.8

0.8 / 0.8 / 0.8

TBD / TBD / TBD

0.7 / 0.7 / -

1)

Intel SpeedStep Frequence Modes LFM: Low Frequency Mode, HFM: High Frequency Mode.

2)

Add 200/600mA (link only/active) @1Gbps per Ethernet Port.

3)

For Intel Celeron-1047UE there is no Turbo Mode at all and no low Frequency Mode at workload.

© EKF -13- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Block Diagram

DDR3 ECC Soldered

DDR3 ECC SODIMM

© EKF -14- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Top View Component Assembly

PC3-ALLEGRO

© EKF • ekf.com

SODIMM ECC DDR3

Soldered ECC DDR3

© EKF -15- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Front Panel Connectors

ETH1/2 mDP1/2 Mini DisplayPort digital video output receptacle (VGA connector available as alternate)

USB1/2

VGA

Dual Gigabit Ethernet RJ-45 receptacles with integrated indicator LEDs

Universal Serial Bus 3.0 type A receptacles

VGA analog video output connector (Mini DisplayPort connectors available as alternate)

GP

HD

PG

RST

Front Panel Switches & Indicators

EB

FPH

LED indicating Backplane Ethernet activity

Front Panel Handle with integrated switch (programmable function, power event button by default)

General Purpose bicolour LED

LED indicating any activity on SATA ports

Power Good/Board Healthy bicolour LED

System Reset Button (Option)

© EKF -16- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

On-Board Connectors & Sockets

J-EXPT

J-EXPB

1)

J-HSE

Utility EXPansion Interface Connector (LPC, USB, HD Audio, SMBus), available either from top (T) or bottom (B )

1)

of the board, interface to optional side board

High Speed Expansion Connector (4 x SATA, 4 x USB), interface to optional low profile mezzanine module or side board

J-PCIE

J-SDVO

J1/J2

PCI Express® Expansion Interface Connector, interface to optional side board

Digital Display Interface Connector (DisplayPort)

CompactPCI

Bus 32-bit (universal V(I/O)), 33MHz, PlusIO

SODM1 204-pin DDR3 ECC Memory Module SDRAM PC3-12800 Socket (ECC SODIMM)

XDP CPU Debug Port

1)

1)

Connector populated on customers request only

Pin Headers

P-FPH

P-ISP

Pin header suitable for Front Panel Handle switch cable harness

PLD glue logic device programming connector, not populated

Jumpers

DS-P

P-GP

P-MFG

P-RTC

Switches to configure link width and speed on J-PCIE

Jumper to reset UEFI BIOS Setup to EKF Factory Defaults

Jumper to enter Manufacturing Mode, not populated

Jumper to reset RTC circuitry (part of PCH), not populated

© EKF -17- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Microprocessor

The PC3-ALLEGRO is equipped with Intel® Core

TM

i7 or i5 3 rd

generation mobile ECC processor (code name Ivy Bridge). These low power processors provide integrated graphics and memory controller, which results in a very efficient platform design. The Core

TM

processors almost can be considered as a single-chip solution, since all functions of a typical north-bridge have been moved to the CPU.

The Core

TM

i7 and i5 processor family includes beside the Standard-Voltage (SV) also several Ultra

Low-Voltage (ULV) and Low-Voltage (LV) processors as listed below. The processors are housed in a

Micro FC-BGA package for direct soldering to the PCB, i.e. the chip cannot be removed or changed by the user.

The processors supported by the PC3-ALLEGRO are running at core clock speeds up to 2.1GHz for quad core and up to 2.5GHz on dual core devices. Due to Enhanced Intel® SpeedStep® and Intel®

Turbo Boost Technology each core can decrease or increase its nominal operating frequency. The clock speed is chosen depending on the power states of the processor cores/graphics engine, the currently required performance, and the actual core temperature.

Power is applied across the

CompactPCI

connectors J1 (3.3V, 5V). The processor core voltage is generated by a switched voltage regulator, sourced from the 5V plane. The processor signals its required core voltage by 7 dedicated pins according to Intels IMVP-7 voltage regulator specification.

Processor

Number i7-3612QE i7-3555LE i7-3517UE i5-3610ME

Physical

Cores

4

2

2

2

Intel® Core

TM

Processors Supported

Core Clock nom./max.

2.1/3.1GHz

Cache Gfx

Clock

Junction

Temp.

TDP CPU ID

4MB 650MHz +105°C 35W 306A9h

2.5/3.2GHz

1.7/2.8GHz

2.7/3.3GHz

4MB 550MHz +105°C 25W 306A9h

4MB 350MHz +105°C 17W 306A9h

3MB 650MHz +105°C 35W 306A9h

Stepping

E-1

L-1

L-1

L-1

SPEC

Code

SR0ND

SR0T5

SR0T6

SR0QK

© EKF -18- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Thermal Considerations

In order to avoid malfunctioning of the PC3-ALLEGRO, take care of appropriate cooling of the processor and system, e.g. by a cooling fan suitable to the maximum power consumption of the CPU chip actually in use. The processor contains digital thermal sensors (DTS) that are readable via special CPU registers. DTS allows to get the temperatures of each CPU core separately.

Two further temperature sensors, located in the system hardware monitor LM87, allows for acquisition of the boards surface temperature and the thermal state of the onboard system memory channel. Beside this the

LM87 also monitors most of the supply voltages. A suitable software on Microsoft Windows® systems to display both, the temperatures as well as the supply voltages, is Speedfan, which can be downloaded from the web. After installation, both temperatures and voltages can be observed permanently from the Windows® taskbar.

The PC3-ALLEGRO is equipped with a passive heatsink. Its height takes into account the 4HP limitation in mounting space of a

CompactPCI ®

board. In addition, a forced vertical airflow through the system enclosure

(e.g. bottom mount fan unit) is strongly recommended (>20m

3

/h or 2m/s (400LFM) around the CPU slot). Be sure to thoroughly discuss your actual cooling needs with EKF. Generally, the faster the CPU speed the higher its power consumption. For higher ambient temperatures, consider increasing the forced airflow to 3m/s

(600LFM) or more.

The table showing the supported processors above give also the maximum power consumption (TDP = Thermal

Design Power) of a particular processor. Fortunately, the power consumption is by far lower when executing typical Windows® or Linux tasks. The heat dissipation increases when e.g. rendering software like the Acrobat

Distiller is executed.

The Core

TM

i7 processors support Intel's Enhanced SpeedStep® technology. This enables dynamic switching between multiple core voltages and frequencies depending on core temperature and currently required performance. The processors are able to reduce their core speed and core voltage in multiple steps down to

1200MHz (800MHz for LV/ULV processors). Additional a reduction of the graphics core clock and voltage is possible. This leads to an obvious reduction of power consumption resulting in less heating. This mode of lowering the processor core temperature is called TM2 (TM=Thermal Monitor).

Another way to reduce power consumption is to modulate the processor clock. This mode (TM1) is achieved by actuating the 'Stop Clock' input of the CPU. A throttling of 50% e.g. means a duty cycle of 50% on the stop clock input. However, while saving considerable power consumption, the data throughput of the processor is also reduced. The processor works at full speed until the core temperature reaches a critical value. Then the processor is throttled by 50%. As soon as the high temperature situation disappears the throttling will be disabled and the processors runs at full speed again.

These features are controllable by BIOS menu entries. By default the BIOS of the PC3-ALLEGRO enables mode

TM2 which is the most efficient.

© EKF -19- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Main Memory

The PC3-ALLEGRO features two channels of DDR3 SDRAMs with support of ECC (Error Correction

Code). One channel is realized with 18 memory devices soldered to the board (Memory Down) and delivers a capacity of up to 8GB with a clock frequency of 1600MHz (PC3-12800).

The 2nd channel provides a socket for installing a 204-pin ECC SODIMM module thus allowing a simple expansion of system memory (max. module height = 1.25 inch). Supported are unbuffered

DDR3 ECC SODIMMs (72-bit) with V

DD

=1.5V featuring on-die termination (ODT), according the

PC3-12800 specification. Minimum module size is 512MB; maximum module size is 8GB. Please note that standard DDR3 SODIMMs without ECC feature do not work on PC3-ALLEGRO.

It is recommended to add a SODIMM module with same size as the Memory Down to get best performance (some of the system memory is dedicated to the graphics controller). This typically results in a size of 2x4GB of memory which is recommended to run the operating systems Windows® Vista or Windows® 7.

The memory controller supports symmetric and asymmetric memory organization. The maximum memory performance can be obtained by using the symmetric mode. When in this mode, the memory controller accesses the memory channels in an interleaved way. Since Core

TM

i7 processors support

Intels Flex Memory Technology, interleaved operation isn't limited to systems using memory channels of equal capacity. In the case of unequal memory population the smaller memory channel dictates the address space of the interleaved accessible memory region. The remainder of the memory is then accessed in non-interleaved mode.

In asymmetric mode the memory always will be accessed in a non-interleaved manner with the drawback of less bandwidth. The only meaningful application of asymmetric mode is the special case when only one memory channel is populated (i.e. the SODIMM socket may be left empty).

The contents of the SPD EEPROM on the SODIMM is used by the BIOS at POST (Power-on Self Test) to get any necessary timing parameters to program the memory controller within the chipset.

© EKF -20- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Top Side Soldered Memory

Bottom Side Soldered Memory

© EKF -21- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Graphics Subsystem

The graphics subsystem is part of the Intel Core

TM

i7 processor and the PCH QM77. While the graphics controller is located within the Core

TM

i7 processor, the different interfaces like DisplayPort and VGA are moved to the PCH. The PC3-ALLEGRO offers two Mini DisplayPort (mDP) interfaces in the front panel.

Adapters to convert Mini DisplayPort to any other popular interface standard are available.

A 3 rd

DisplayPort is fed to the on-board connector J-SDVO. EKF expansion boards like PCS-BALLET feature the possibility to gain access to the 3 rd

DisplayPort interface.

As an option, the PC3-ALLEGRO can be equipped with an ordinary HD D-Sub 15-lead connector (VGA style). This connector is suitable for analog signals only. Nevertheless also flat-panel displays can be attached to the D-Sub connector but with minor reduced image quality.

Independent from the video connector actually in use, Mini DisplayPort, DVI or VGA, the VESA DDC standard is supported. This allows to read out important parameters, e.g. the maximum allowable resolution, from the attached monitor. DDC Power, +3.3V or +5V on DisplayPort or VGA connector respectively, is delivered via a resettable fuse to protect the board from an external short-circuit condition (0.5A).

Graphics drivers for the Core

TM

i7 can be downloaded from the Intel web site.

© EKF -22- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

LAN Subsystem

The Ethernet LAN subsystem is composed of four Gigabit Ethernet ports: One Intel 82579LM Physical

Layer Transceiver (PHY) using the PCH QM77 internal MAC and three Intel 82574IT Gigabit Ethernet

Controllers. These devices provide also legacy 10Base-T and 100Base-TX connectivity. Two of the

Ethernet ports are fed to two RJ45 jacks located in the front panel, the others are attached to the

CompactPCI

®

PlusIO interface on J2. Each port includes the following features:

< One PCI Express lane per Ethernet port (250MB/s)

< 1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet) capability.

< Half- or full-duplex operation.

< IEEE 802.3u, 802.3ab Auto-Negotiation for the fastest available connection.

< Jumperless configuration (complete software-configurable).

Two bicoloured LEDs integrated into the dedicated RJ-45 connector in the front panel are used to signal the LAN link, the LAN connection speed and activity status. A further bicoloured LED in front panel labelled EB displays the state of the backplane network ports.

Each device is connected by a single PCI Express lane to the PCH. Their MAC addresses (unique hardware number) are stored in dedicated FLASH/EEPROM components. The Intel Ethernet software and drivers for the 82579 and 82574 is available from Intel's World Wide Web site for download.

When managing the board by Intel Active Management Technology (iAMT), the dedicated network port to do so is accessible by the RJ45 connector GbE1 (the upper port within the front panel).

© EKF -23- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Serial ATA Interface (SATA)

The PC3-ALLEGRO provides a total of eight serial ATA (SATA) ports, derived from two independent

SATA controllers. Two of these ports support data transfer rates of 6Gbps (600MB/s) while all ports are capable to work with 3Gbps (300MB/s) or 1.5Gbps (150MB/s).

The SATA controller that is located within the QM77 Platform Controller Hub hold two 6Gbps and two 3Gbps ports which are fed to the high speed expansion connector J-HSE. This connector allows the installation of low profile expansion boards like C41-CFAST or C42-SATA to attach the popular

CFast cards or Micro SATA SSDs (1.8-inch) respectively. Another mezzanine is the C47-MSATA, a carrier for two MSATA SSD modules, that is connected via J-HSE to the 6Gbps ports for fast data storage.

Four SATA interfaces are provided by a Marvell 88SE9230 Controller available on the Backplane connector J2. Hardware RAID configuration level 0/1/10 is supported. Please be aware that

CompactPCI PlusIO Specefication does not support SATA 6G. Therefore J2 SATA channels are configured as SATA 3G.

A LED named HD located in the front panel, signals disk activity status of any of the SATA devices.

Additionally a variety of side cards is available, suitable for mounting on the PC3-ALLEGRO in a 4HP

(20.32mm) distance (resulting in 8HP front panel width for the assembly). Some of these side boards can accommodate a SATA drive, e.g. a 2.5-inch SSD.

Available for download from Intel's web site are drivers for popular operating systems, e.g. Windows®

XP, Windows® Vista, Windows® 7 and Linux.

To manage the RAID configuration of the 88SE9230 a Windows® application is provided by Marvell that can be downloaded from EKF’s website.

© EKF -24- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PCI Express® Interface

The PC3-ALLEGRO is provided with several PCI Express (PCIe) lanes for I/O expansion. Four PCI Express

Gen 2 lanes (5GT/s), originating from the QM77, are available at the backplane connector J2. Another four PCI Express lanes are provided by the Intel Core

TM

i7 processor to the J-PCIE connector. A small

DIP switch (DS-P) located on the backside of the board are used to configure different lane widths to each of both downstream interfaces and to choose the interface transfer rate. Possible settings are

< Single link x 4 lanes to J-PCIE

< Four links x 1 lane to J-PCIE

< 2.5GT/s or 5GT/s transfer speed

See section “Configuration PCI Express Switch (DS-P)” for details.

© EKF -25- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Universal Serial Bus (USB)

The PC3-ALLEGRO is provided with twelve USB ports. All of them are USB 2.0 capable, but two ports, routed to front panel connectors, are also supporting the USB 3.0 SuperSpeed standard.

The USB 2.0 interfaces are distributed to the front panel (two ports), two to the expansion board interface connectors J-EXP, four to the high speed expansion connector J-HSE, and four ports are available across the backplane connector J2.

The front panel USB connectors can source a minimum of 1.5A/5V each, over-current protected by two electronic switches. Protection for the USB ports on the expansion interfaces and on the J2 PlusIO connector is located on expansion boards. The USB xHCI and two EHCI controllers handling the USB port operation at SuperSpeed, high-speed, full-speed and low-speed are integrated into the QM77

PCH.

Utility Interfaces

<

<

<

<

Besides the high speed mezzanine interface connectors J-HSE and J-PCIE, the PC3-ALLEGRO is provided with the utility interface expansion connector socket J-EXP. This connector comprises several interfaces, which may be useful for system expansion on mezzanine cards, as an option:

HD Audio

LPC (Low Pin Count)

SMBus

2 x USB

The SMBus is controlled by the QM77 platform controller hub. The SMBus signal lines on the J-EXP utility expansion connector can be switched on/off under software control (PCH GPIO) in order to isolate external components in case of an I

2

C address conflict.

The HD Audio port requires an additional audio codec, as provided e.g. on the PCS-BALLET side card.

The LPC bus presents an easy way to add legacy interfaces to the system. EKF offers a variety of mezzanine expansion boards (side cards), to be attached on top of the PC3-ALLEGRO, featuring all classic Super-I/O functionality, for example the PCS-BALLET or the CCO-CONCERT. Access to the connectors PS/2 (mouse, keyboard), COM, USB and audio in/out is given directly from the front panel.

© EKF -26- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Real-Time Clock

The PC3-ALLEGRO has a time-of-day clock and 100-year calendar, integrated into the QM77 PCH. A battery on the board keeps the clock current when the computer is turned off. The PC3 uses a BR2032 lithium battery soldered in the board, giving an autonomy of more than 5 years. Under normal conditions, replacement should be superfluous during lifetime of the board.

In applications were the use of a battery is not permitted, a SuperCap can be stuffed instead of the battery.

SPI Flash

The BIOS and iAMT firmware is stored in flash devices with Serial Peripheral Interface (SPI). Up to

16MByte of BIOS code, firmware and user data may be stored nonvolatile in these SPI Flashes.

The SPI Flash contents can be updated by a DOS or Linux based tool. This program and the latest

PC3-ALLEGRO BIOS binary are available from the EKF website. Read carefully the enclosed instructions.

If the programming procedure fails e.g. caused by a power interruption, the PC3-ALLEGRO may no more be operable. In this case you would possibly have to send in the board, because the Flash device is directly soldered to the PCB and cannot be changed by the user.

© EKF -27- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Reset

The PC3-ALLEGRO is provided with several supervisor circuits to monitor supply rails like the CPU core voltage, 1.5V, 3.3V or 5V. This circuitry is responsible also to generate a clean power-on reset signal.

To force a manual board reset, the PC3-ALLEGRO offers a small tactile switch within the front panel.

This push-button is indent mounted and requires a tool, e.g. a pen to be pressed, preventing from being inadvertently activated.

The ejector within the front panel contains a micro switch that is used to generate a power button event. This is done by pushing the red button of the ejector until the handle unlocks without ejecting the board. Immediately after that push up the ejector back to its original position (the red button jumps up as well). Animated GIF: www.ekf.com/c/ccpu/img/reset_400.gif

NOTE: To prevent the board to cause a power button override, the handle should be closed immediately after unlocking the front panel handle. A power button override is triggered by opening the front panel handle for at least 4 seconds, which results in bringing the board to power state S5.

In case of entering this state, unlock and lock the front panel handle a 2 nd

time to reenter normal power state S0 again. See also section 'PG (Power Good) LED' to see how the PC3-ALLEGRO indicates the different power states.

WARNING: The PC3-ALLEGRO will enter the power state S5 if the front panel handle is not closed properly when the system powers up. An open handle is signalled by a yellow blinking ‘PG LED’.

The manual reset push-button and the power button functionality of the front panel handle could be passivated by BIOS settings.

An alternative (and recommended) way to generate a system reset is to activate the signal PRST# located on

CompactPCI

connector J2 pin C17. Pulling this signal to GND will have the same effect as to push the tactile reset switch.

The healthy state of the PC3-ALLEGRO is indicated by the LED PG (Power Good) located in the front panel. This bicoloured LED signals different states of the board (see section below). As soon as this

LED begins to lite green, all power voltages are within their specifications and the reset signal has been deasserted.

© EKF -28- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

5

6

7

8

<4s

3

4

1

2

© EKF -29- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Watchdog

An important reliability feature is a software programmable watchdog function. The PC3-ALLEGRO contains two of these watchdogs. One is part of the QM77 PCH and also known as TCO Watchdog.

A detailed description is given in the QM77 data sheet. Operating systems like Linux offer a driver interface to the TCO watchdog.

The behaviour of the 2 nd

watchdog is defined within a PLD of the PC3, which activates/deactivates the watchdog and controls its time-out period. The time-out delay is adjustable in the steps 2, 10, 50 and

255 seconds. After alerting the WD and programming the time-out value, the related software (e.g.

application program) must trigger the watchdog periodically. For details on programming the watchdog see section “Board Control and Status Register (BCSR)”.

This watchdog is in a passive state after a system reset. There is no need to trigger it at boot time. The watchdog is activated on the first trigger request. If the duration between two trigger requests exceeds the programmed period, the watchdog times out and a full system reset will be generated.

The watchdog remains in the active state until the next system reset. There is no way to disable it once it has been put on alert, whereas it is possible to reprogram its time-out value at any time.

© EKF -30- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Front Panel LEDs

The PC3-ALLEGRO is equipped with four LEDs which can be observed from the front panel. Three of these LEDs are labelled according to their primary meaning, but should be interpreted altogether for system diagnosis:

PG

Green/Red

OFF

OFF

OFF

GREEN

GREEN

YELLOW BLINK

RED

RED BLINK

LED

GP

Green/Red

GREEN

GREEN

OFF

RED BLINK

X

X

X

X

HD

Green/Red

GREEN

OFF

GREEN

X

X

X

X

X

Status

Sleep State S5 (Soft Off)

Sleep State S4 (Suspend to Disk/Hibernate)

Sleep State S3 (Suspend to RAM/Standby)

After Reset

Board Healthy and in S0 State

Front panel handle is unlocked

Hardware Failure - Power Fault

Software Failure

© EKF -31- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PG (Power Good) LED

The PC3-ALLEGRO offers a bicolour LED labelled PG located within the front panel. After system reset, this LED defaults to signal different power states:

<

<

<

<

<

Off

Green

Sleep state S3, S4 or S5

Healthy

Yellow blink Front panel handle open

Red steady Hardware failure

Red blink Software failure

To enter the PG LED state

Software Failure,

the bit PGLED in the board control register CTRLL_REG must be set. The PG LED remains in this red blinking state until this bit is cleared. After that it falls back to its default function.

GP (General Purpose) LED

This programmable bicolour LED can be observed from the PC3-ALLEGRO front panel. The status of the red part within the LED is controlled by the GPIO18 of the PCH QM77. Setting GPIO18 to “1" will switch on the red LED. Turning on or off the green LED is done by setting the bit GPLED in the board control register CTRLH_REG.

The GP LED is not dedicated to any particular hardware or firmware function with exception of special power states of the LED PG as described above. Nevertheless, a red blinking GP LED is an indication that the BIOS code couldn't start.

While the CPU card is controlled by the BIOS firmware, the GP LED is used to signal board status information during POST (Power On Self Test). After successful operating system boot, the GP LED may be freely used by customer software. For details please refer to www.ekf.com/p/pc3/firmware/biosinfo.txt.

© EKF -32- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

HD (Hard Disk Activity) LED

The PC3-ALLEGRO offers a bicoloured LED marked as HD placed within the front panel. This LED, when blinking green, signals activity on any device attached to the SATA ports of the Intel® QM77

Panther Point Platform Controller Hub (PCH). Blinking yellow signals activity on any device attached to the SATA ports of the Marvell 88SE9230 SATA RAID Controller.

As previously described, the green part of this LED may change its function dependent on the state of the LED PG.

EB (Ethernet Backplane) LED

To monitor the link status and activity on both Ethernet ports attached to the backplane via the

CompactPCI

®

Serial connector P6 a single bicoloured LED is provided in the front panel. The states are decoded as follows:

1_ETH no link link no link link

2_ETH no link no link link link

LED EB

OFF

GREEN

YELLOW

GREEN/YELLOW

Blinking of the LED EB in the appropriate colour means that there is activity on the port.

© EKF -33- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Hot Swap Detection

The CompactPCI® specification added the signal ENUM# to the PCI bus to allow board hot swapping. This signal is routed to a GPIO (GPIO3 QM77 PCH) . An interrupt can be requested, if

ENUM# changes, caused by insertion or removal of a peripheral board.

Note that the PC3-ALLEGRO itself is not a hot swap device, because it makes no sense to remove the system controller from a CompactPCI® system. However, it is capable to recognize the hot swap of peripheral boards and to start software that is performing any necessary system reconfiguration.

Power Supply Status (DEG#, FAL#)

Power supply failures may be detected before the system crashes down by monitoring the signals

DEG# or FAL#. These active low lines are additions to the CompactPCI® specification and may be driven by the power supply. DEG# signals the degrading of the supply voltages, FAL# there possible failure. On the PC3-ALLEGRO DEG# is tied to VCC and FAL# is routed to QM77 PCH GPIO4.

© EKF -34- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Mezzanine Side Board Options

The PC3-ALLEGRO is provided with several stacking connectors for attachment of a mezzanine expansion module (aka side board), suitable for a variety of readily available mezzanine cards (please refer to www.ekf.com/c/ccpu/mezz_ovw.pdf for a more comprehensive overview). EKF furthermore offers custom specific development of side boads (please contact [email protected]).

2 x

USB

3.0

DP

1

VGA

DP

2

2 x SATA 6G

2 x SATA 3G

4 x USB

HSE

Dual

GbE

LPC USB

SMBus

HD Audio

EXP

PCI Express® x 4

PCIE

Mezzanine

& Backplane

Expansion

Options

Flat-

Panel

SDVO/DP

PC3-ALLEGRO

Intel® Ivy Bridge

Core™ i7 CPU

© •

J1

4 x PCIe

4 x SATA 3G

2 x GbE 4 x USB

® up to 4 Slots

CPCI-S.0

Peripheral

Boards or

CompactPCI® PlusIO

Rear I/O Module

® up to 8 Slots

CompactPCI®

Peripheral

Boards

Most mezzanine expansion modules require an assembly height of 8HP in total, together with the

CPU carrier board (resulting from two cards at 4HP pitch each). In addition, cropped low profile mass storage mezzanine modules can be attached to J-HSE, which maintain the 4HP envelope, for extremely compact systems. Furthermore these small size modules may be combined with the full-size expansion boards (that means an assembly comprised of 3 PCBs).

© EKF -35- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC3-ALLEGRO w. PCL-CAPELLA Side Card 8HP Assembly

Related Documents Mezzanine Modules and Side Cards

C40 ... C47 Series

Mezzanine Storage Modules www.ekf.com/c/ccpu/c4x_mezz_ovw.pdf

PCL-CAPELLA Mezzanine Side Card

PCS-BALLET Mezzanine Side Card www.ekf.com/p/pcl/pcl.html

www.ekf.com/p/pcs/pcs.html

© EKF -36- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

CompactPCI

®

PlusIO

CompactPCI® PlusIO (PICMG® 2.30) is a standard for rear I/O across J2. High speed signal lines (PCI

Express®, SATA, Gigabit Ethernet and USB) are passed from the PC3-ALLEGRO through the special

UHM J2 connector to the backplane, for usage either with a PlusIO rear I/O transition module, or

CompactPCI® Serial card slots.

CompactPCI® Serial (PICMG® CPCIS.0) defines a completely new card slot, based on PCI Express®,

SATA, Gigabit Ethernet and USB serial data lines. On a hybrid backplane, both card styles can reside,

CompactPCI® and CompactPCI® Serial, with the PC3-ALLEGRO in the middle as controller for both backplane segments.

The PC3-ALLEGRO can be used in any system with a CompactPCI

®

PlusIO backplane according to the

PICMG

®

2.30 specification. Hybrid backplanes allow the configuration of systems with CompactPCI

®

Serial slots in addition to classic CompactPCI

®

boards.

CompactPCI® PlusIO & CompactPCI® Serial

Hybrid Backplane

CompactPCI 32-Bit

Peripheral Slots

CPCIS.0

Peripheral Slots

Sample Small Systems Hybrid Backplane

© EKF -37- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Warning: Do not operate the PC3-ALLEGRO in systems with a 64-bit CompactPCI

®

backplane. The

J2/P2 pin assignments of a 64-bit CPCI backplane differ substantially from a CompactPCI

®

PlusIO backplane, which may result in a short circuit situation.

For use with a 64-bit CompactPCI

®

backplane special versions are available on request. 32-bit operation is supported only. The use of 64-bit CompactPCI

® peripheral boards may cause problems.

© EKF -38- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC1-GROOVE as System Controller in a Hybrid System

CompactPCI® PlusIO Racks Available

© EKF -39- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

As an alternate, the PC3-ALLEGRO can be combined with a CompactPCI

®

PlusIO rear I/O transition module, such as the PR1-RIO, which is provided with I/O connectors (on-board and back-panel) for all high speed signals.

PR1-RIO • Rear I/O Transition Module

© EKF -40- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Related Documents Mezzanine Modules and Side Cards

C4x Series Mezzanine Storage Modules

Mezzanine Modules Overview

The EKF Mezzanine Module Concept www.ekf.com/c/ccpu/c4x_mezz_ovw.pdf

www.ekf.com/c/ccpu/mezz_ovw.pdf

www.ekf.com/c/ccpu/cpci_mezzanine_evolution.pdf

I/F Type

LPC (Low Pin Count)

HD Audio

SMBus

2 x USB 2.0

J-EXP

J-HSE

I/F Type

SATA1, SATA4

SATA2, SATA3

4 x USB 2.0

J-PCIE

I/F Type

PCI Express®

Controller

CPU

CPU

CPU (buffered)

PCH

Controller

PCH 3GT/s

PCH 6GT/s

USB Hub

Controller

PE Switch

Related Documents

CompactPCI ®

Serial

CompactPCI

®

PlusIO & Serial Overview

CompactPCI

®

Serial Home

CompactPCI

®

PlusIO Home www.ekf.com/s/smart_solution.pdf

www.ekf.com/s/serial.html

www.ekf.com/p/plus.html

© EKF -41- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Installing and Replacing Components

Before You Begin

Warnings

The procedures in this chapter assume familiarity with the general terminology associated with industrial electronics and with safety practices and regulatory compliance required for using and modifying electronic p o w e r s o u r c e a n d f r o m a n y equipment. Disconnect the system from its modems before performing any of the procedures described in this chapter. Failure to disconnect power, or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage. Some parts of the system can continue to operate even though the power switch is in its off state.

Caution

Electrostatic discharge (ESD) can damage described in this chapter only at an ESD you can provide some ESD protection by components. Perform the procedures workstation. If such a station is not available, wearing an antistatic wrist strap and attaching it to a metal part of the system chassis or board front panel. Store the board only in its original ESD protected packaging. Retain the original packaging (antistatic bag and antistatic box) in case of returning the board to EKF for repair.

© EKF -42- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Installing the Board

Warning

This procedure should be done only by qualified technical personnel. Disconnect the system from its power source before doing the procedures described here. Failure to disconnect power, or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage.

C

C

Typically you will perform the following steps:

C

Switch off the system, remove the AC power cord

C

C

C

C

Attach your antistatic wrist strap to a metallic part of the system

Remove the board packaging, be sure to touch the board only at the front panel

Identify the related

CompactPCI

®

slot (peripheral slot for I/O boards, system slot for CPU boards, with the system slot typically most right or most left to the backplane)

Insert card carefully (be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels)

C

A card with onboard connectors requires attachment of associated cabling now

Lock the ejector lever, fix screws at the front panel (top/bottom)

Retain original packaging in case of return

© EKF -43- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Removing the Board

Warning

This procedure should be done only by qualified technical personnel. Disconnect the system from its power source before doing the procedures described here. Failure to disconnect power, or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage.

C

C

Typically you will perform the following steps:

C

Switch off the system, remove the AC power cord

C

C

Attach your antistatic wrist strap to a metallic part of the system

Identify the board, be sure to touch the board only at the front panel

Unfasten both front panel screws (top/bottom), unlock the ejector lever

C

C

C

Remove any onboard cabling assembly

Activate the ejector lever

Remove the card carefully (be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels)

Store board in the original packaging, do not touch any components, hold the board at the front panel only

Warning

Do not expose the card to fire. Battery cells and other components could explode and cause personal injury.

© EKF -44- ekf.com

C

C

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

EMC Recommendations

In order to comply with the CE regulations for EMC, it is mandatory to observe the following rules:

C

The chassis or rack including other boards in use must comply entirely with CE

C

Close all board slots not in use with a blind front panel

C

C

C

Front panels must be fastened by built-in screws

Cover any unused front panel mounted connector with a shielding cap

External communications cable assemblies must be shielded (shield connected only at one end of the cable)

Use ferrite beads for cabling wherever appropriate

Some connectors may require additional isolating parts

Recommended Accessories

Blind CPCI Front

Panels

Ferrit Bead Filters

Metal Shielding

Caps

EKF Elektronik

ARP Datacom,

63115 Dietzenbach

Conec-Polytronic,

59557 Lippstadt

Widths currently available

(1HP=5.08mm): with handle 4HP/8HP without handle

2HP/4HP/8HP/10HP/12HP

Ordering No.

102 820 (cable diameter 6.5mm)

102 821 (cable diameter 10.0mm)

102 822 (cable diameter 13.0mm)

Ordering No.

CDFA 09 165 X 13129 X (DB9)

CDSFA 15 165 X 12979 X (DB15)

CDSFA 25 165 X 12989 X (DB25)

© EKF -45- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Replacement of the Battery

When your system is turned off, a battery maintains the voltage to run the time-of-day clock and to keep the values in the CMOS RAM. The battery should last during the lifetime of the PC3-ALLEGRO.

For replacement, the old battery must be desoldered, and the new one soldered. We suggest that you send back the board to EKF for battery replacement.

Warning

Danger of explosion if the battery is incorrectly replaced or shorted. Replace only with the same or equivalent type. Do not expose a battery to fire.

© EKF -46- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Technical Reference

Local PCI Devices

The following table shows the on-board PCI devices and their location within the PCI configuration space. Several devices are part of the processor and platform controller hub QM77.

Bus #

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

7 2)

10

2)

11

2)

12 2)

1

2)

2

2)

0

0

Device #

0

27

28

29

31

31

22

25

26

2

20

22

22

22

1

1

1

6

31

31

31

00

01,05,07,09

0

00

00

00

0

0

0

0

0

3

5

6

0

Vendor ID

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

0x8086

Function #

0

0

0

0

0-7

2

3

0

0

0

1

0

0

2

0

1

2

0

0x8086

0x8086

0x8086

0x10B5

0x10B5

0x1B4B

0x8086

0x8086

0x8086

Device ID

0x0154

0x1E3D

0x1502

0x1E2D

0x1E20

0x2448

0x1E26

0x1E55

0x1E01

0x1E03

0x282A

0x1E07

0x1E22

0x0151

0x0155

0x0159

0x015D

0x0166

0x1E31

0x1E3A

0x1E3B

0x1E3C

0x1E09

0x1E24

0x8614

0x8614

0x9230

0x10D3

0x10D3

0x10D3

Description

Processor Host Bridge/DRAM Controller

Processor PCI Express Controller

Processor PCI Express Controller

Processor PCI Express Controller

Processor PCI Express Controller

Processor Integrated Graphics Device

USB xHCI Controller

Intel ME Interface #1

Intel ME Interface #2

Intel ME IDE Redirection

Intel ME Keyboard Text Redirection

PCH Gigabit LAN NC1 (82579LM)

USB EHCI Controller #2

Intel High Definition Audio Controller

PCH PCI Express Port 1-8

USB EHCI Controller #1

LPC Bridge

SATA: Non-AHCI/RAID (Ports 0-3)

1)

SATA: AHCI Mode

1)

SATA: Intel Rapid Storage Tech. RAID Mode

1)

SATA: RAID Mode Capable

1)

SMBus Controller

SATA: Non-AHCI/RAID (Ports 4/5)

Thermal Controller

PCIe Switch Root Port (PEX8608)

PCIe Switch Downstream Ports (PEX8608)

Marvell 9230 SATA Controller

Ethernet Controller NC2 (82574IT)

Ethernet Controller NC3 (82574IT)

Ethernet Controller NC4 (82574IT)

1)

Depends on BIOS settings.

2)

Bus number can vary depending on the PCI enumeration schema implemented in BIOS.

© EKF -47- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Local SMB Devices

The PC3-ALLEGRO contains devices that are attached to the System Management Bus (SMBus). These are the SPD EEPROMs for the on-board memory or the possibly plugged SODIMM, a general purpose serial EEPROM, a supply voltage/temperature controlling device and a set of board control and status registers. Additional devices may be connected to the SMBus via the

CompactPCI

®

Serial backplane signals I

2

C_SCL (P1 B2) and I

2

C_SDA (P1 B3), or pins 29/30 of the mezzanine expansion connector

J-EXP.

Address

0x58

0x5C

0xA0

0xA4

0xAE

Description

Hardware Monitor/Memory Down Temperature Sensor (LM87)

Board Control/Status

SPD of On-board Memory

SPD of SODIMM

General Purpose EEPROM

© EKF -48- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Hardware Monitor LM87

Attached to the SMBus, the PC3-ALLEGRO is provided with a hardware monitor (LM87). This device is capable to observe the board and on-board memory temperatures, as well as several supply voltage rails with a resolution of 8 bit. The following table shows the mapping of the voltage inputs of the

LM87 to the corresponding supply voltages of the PC3-ALLEGRO:

Input

AIN1

AIN2

VCCP1

VCCP2/D2-

+2.5V/D2+

+3.3V

+5V

+12V

Source

Processor Core Voltage

Graphics Core Voltage

+1.5V

+1.8V

+1.05V

+3.3V

+5V

+10V

Resolution

[mV]

9.8

9.8

14.1

14.1

13

17.2

26

62.5

Register

0x28

0x29

0x21

0x25

0x20

0x22

0x23

0x24

Beside the continuous measuring of temperatures and voltages the LM87 may compare these values against programmable upper and lower boundaries. As soon as a measurement violates the allowed value range, the LM87 can request an interrupt via the GPI13 input of the QM77 PCH (which may result in a system management interrupt).

© EKF -49- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Board Control and Status Registers

<

<

<

<

<

A set of board control and status registers allow to program special features on the PC3-ALLEGRO:

Assert a full reset

Control activity of front panel reset and power event button

Program time-outs and trigger a watchdog

Get access to two LEDs in the front panel

Get power fail and watchdog status of last board reset

The register set consists of five registers located on the SMBus at Device ID=0x5c on the following addresses:

<

<

<

<

<

<

<

0xA0: CMD_CTRL0_WR: Write to Control Register 0 (Write-Only)

0xA1: CMD_CTRL0_RD: Read from Control Register 0 (Read-Only)

0xB0: CMD_STAT0_WR: Write to Status Register 0 (Write-Clear)

0xB1: CMD_STAT0_RD: Read from Status Register 0 (Read-Only)

0xB2: CMD_STAT1_WR: Write to Status Register 1 (Write-Clear)

0xB3: CMD_STAT1_RD: Read from Status Register 1 (Read-Only)

0xC1: CMD_PLDREV_RD: Read from PLD Revision Register (Read-Only)

To prevent misfunction accesses to the registers should be done by SMBus “Byte Data” commands.

Further writes to read-only or reads to write-only registers should be omitted.

© EKF -50- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Write/Read Control Register 0

Write: SMBus Address 0xA0

Read: SMBus Address 0xA1

Default after reset: 0x00

Bit Description CMD_CTRL0

7

6

GPLED

0=Green part of the front panel LED GP is off (Default)

1=Green part of the front panel LED GP is on

FPDIS

0=Enable the power event button within the front panel handle (Default)

1=Disable the power event button within the front panel handle

5 FRDIS

0=Enable the system reset button within the front panel (Default)

1=Disable the system reset button within the front panel

4:3 WDGT0:WDGT1

Maximum Watchdog retrigger time:

0:0 2 sec

1:0

0:1

1:1

10 sec

50 sec

250 sec

2

1

0

WDGTRG

Retrigger Watchdog. Any change of this bit will retrigger the watchdog.

After a system reset the watchdog is in an inactive state. The watchdog is armed on the 1 st

edge of this bit.

PGLED

0=Red part of the front panel LED PG is off (Default)

1=Red part of the front panel LED PG is blinking

SRES

0=Normal operation (Default)

1=A full system reset is performed

© EKF -51- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Read/Clear Status Register 0

Write: SMBus Address 0xB0

Read: SMBus Address 0xB1

Bit

7

6

5

4

3

2

1

0

Description CMD_STAT0

PF18S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.8S voltage regulator

PF15S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.5S voltage regulator

RESERVED

Always read as 0

PFVSA

0=Normal operation

1=Last system reset may be caused by a power failure of the CPU +VCC_SA voltage regulator

PF105L

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.05LAN voltage regulator

PF105S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.05S voltage regulator

PFVRG

0=Normal operation

1=Last system reset may be caused by a power failure of the CPU +VCC_AXG voltage regulator

PFVRC

0=Normal operation

1=Last system reset may be caused by a power failure of the CPU +VCC_CPU voltage regulator

The bits in this register are sticky, i.e. their state will be kept even if a system reset occurs. To clear the bits a write to the register with arbitrary data may be performed.

© EKF -52- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Read/Clear Status Register 1

Write: SMBus Address 0xB2

Read: SMBus Address 0xB3

Bit

7

6

5

4

3

2

1

0

Description CMD_STAT1

RESERVED

Always read as 0

WDGRST

0=Normal operation

1=Last system reset may be caused by a watchdog time-out

WDGHT

0=Normal operation

1=The watchdog already has elapsed half of its time-out period

PF12A

0=Normal operation

1=Power failure on the +12V voltage rail

PF133S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.05S or +V3.3S voltages

PF133M

0=Normal operation

1=Last system reset may be caused by a power failure of the +V1.05M or +V3.3M voltages

RESERVED

Always read as 0

RESERVED

Always read as 0

Except of WDGHT the bits in this register are sticky, i.e. theire state will be kept even if a system reset occurs. To clear the bits a write to the register with arbitrary data may be performed.

© EKF -53- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Read PLD Revision Register

Write: Not allowed

Read: SMBus Address 0xC1

Bit

7:0 PLDREV

Read PLD Revison Number

Description CMD_PLDREV

© EKF -54- ekf.com

GPIO

GPIO 8

GPIO 9

GPIO 10

GPIO 11

GPIO 12

GPIO 13

GPIO 14

GPIO 15

GPIO 16

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

GPIO 6

GPIO 7

GPIO 17

GPIO 18

GPIO 19

GPIO 20

GPIO 21

GPIO 22

GPIO 23

GPIO 24

GPIO 25

GPIO26

GPIO 27

GPIO 28

GPIO 29

GPIO 30-32

GPIO 33

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

GPIO Usage

GPIO Usage QM77 PCH

-

O

-

-

-

-

O

O

O

-

O

O

-

O

-

Type

-

O

I

I

O

I

I

-

O

-

I

I

I

I

I

I

I

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

Tol.

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

5V

5V

5V

5V

3.3V

3.3V

GP_LED_RED

-

SE_SYS_WP

-

SGPIO_CLOCK

-

USB_POWEN1#

CLKOE_2J2

CLKOE_1J2

USB_POWEN2#

-

-

-

-

-

THRM_ALERT#

EXP_SMI#

CPCI_INTP

CPCI_ENUM#

CPCI_PS_FAL_ON#

PM_MEMTS#

-

CPCI_SYSEN_#

-

USB_HSE_OC5#

USB_OC6#

GP_JUMP#

NC1_ENABLE

HM_INT#

USB_OC7#

-

MODE_DP_SDVO#

GPIO Usage QM77 PCH

Function Description

Monitoring of processor PROCHOT#

Expansion Interface SMI Request (J-EXP Pin 15)

CompactPCI Interrupt Request Line INTP

CompactPCI System Enumeration Line ENUM#

CompactPCI Power Failure Line FAL# / PS_ON#

Memory Thermal Sensor

Not used, pulled to GND

Sense CPCI System Slot Enable

Not used, pulled to +V3.3A/

USB HSE Port #2 Overcurrent Detect

USB HSE Port #3 or #4 Overcurrent Detect

Reset UEFI BIOS Setup to Factory Defaults, Jumper P-GP

Enable Ethernet Controller NC2

Hardware Monitor LM87 Interrupt Line

USB J-EXP Port 1 or 2 Overcurrent Detect

Not used, pulled to +V3.3A

Switch Mode of J-SDVO Connector

LOW: J-SDVO in SDVO Mode

HIGH: J-SDVO in DisplayPort Mode

Not used, pulled to GND

General Purpose Red LED Control (via PLD)

Not used, pulled to +V3.3A

General Purpose Serial EEPROM Write Protection

Not used, pulled to +V3.3A

Serial GPIO Bus CLOCK

Not used, internally pulled up

USB Front Panel Right Port Power Enable

J2 PCIe2 clk enable, pulled to +V3.3A

J2 PCIe1 clk enable, pulled to +V3.3A

USB Front Panel Left Port Power Enable

Not used, pulled to +V3.3A

Fixed to chipset internal function

Not used, pulled to +V3.3A

Not used

© EKF -55- ekf.com

GPIO36-37

GPIO 38

GPIO 39

GPIO 40

GPIO 41

GPIO 42

GPIO 43

GPIO 44

GPIO 45

GPIO 46

GPIO 47

GPIO 48-49

GPIO 50-52

GPIO 53

GPIO 54

GPIO 55

GPIO 56

GPIO 57

GPIO 58

GPIO 59

GPIO 60

GPIO 61-62

GPIO 63

GPIO 64-67

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

GPIO

GPIO 34

GPIO 35

GPIO65

GPIO 66

GPIO 67

GPIO68-71

GPIO 72

GPIO 73

GPIO 74-75

-

I

-

-

O

I

I

I

-

-

I

O

I

-

-

O

O

-

-

I

O

-

O

-

O

I

O

O

-

O

O

Type

O

I

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

N/A

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

Tol.

3.3V

3.3V

-

SGPIO_LOAD

SGPIO_OUT

USB_OC1#

ENABLE_NC3

ENABLE_NC4

USB_OC4#

-

CLKOE_4J2

-

CLKOE_3J2

-

-

CPCI_CLKBUF_EN

-

ENABLE_NC2

-

CPCI_INTS

GPIO Usage QM77 PCH

Function

EXP_SMB_EN

Description

Connect SMBus on J-EXP to local SMBus

LOW: J-EXP disconnected from SMBus

HIGH: J-EXP connected to SMBus

CPCI_SMB_EN

USB_OC0#

N/A

HWREV

-

-

-

CLK_14_EXP

HWREV

HWREV

N/A

-

NC1_CLKREQ_#

-

Connect SMBus on CPCI to local SMBus

LOW: CPCI Backplane disconnected from SMBus

HIGH: CPCI Backplane connected to SMBus

Not used, pulled to GND

Serial GPIO Bus LOAD (Backplane J2)

Serial GPIO Bus DATAOUT (Backplane J2)

USB Front Panel Right Port Overcurrent Detect

Enable Ethernet Controller NC3

Enable Ethernet Controller NC4

USB J-HSE Port 1 Overcurrent Detect

Not used, pulled to GND

J2 PCIe4 clk enable, pulled to +V3.3A

Not used, pulled to GND

J2 PCIe3 clk enable, pulled to +V3.3A

Not used, pulled to GND

Not used, pulled to +V3.3S

Enable CompactPCI Clock Buffer

Not used, pulled to +V3.3S

Enable Ethernet Controller NC2

Not used, pulled to GND

LOW:

HIGH:

Isolate SERIRQ from CPCI_INTS

Connect SERIRQ to CPCI_INTS

Not used, pulled to +V3.3A

USB Front Panel Right Port Overcurrent Detect

Not used, pulled to +V3.3A

Not used

Multiplexed with chipset internal function

PCB Revision Code HW_REV[2:0]:

GPIO[67/66/64] 000 001

Revision 0 1 2

Used as 14MHz Clock

010 ...

100 ...

111

4 7

Used as HW_REV[1], see GPIO64

Used as HW_REV[2], see GPIO64

Not used

Not used, pulled to +V3.3A

Clock Enable Ethernet Controller NC1

Not used, pulled to +V3.3A

© EKF -56- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Configuration Jumpers

Configuration PCI Express Switch (DS-P)

The link width and transfer rate of the PCI Express interfaces attached to the local expansion connector

P-PCIE is configurable by two DIP switches (DS-P) located on the backside of the PC3-ALLEGRO. Note that changes in PCIe link configuration are honoured by the PC3-ALLEGRO not before a system reset was performed.

ON

1 2

DS-P

OFF

ON

OFF

ON

1

DS-P

2

OFF

OFF

ON

ON

PCIe Switch

Upstream

4 Lanes @ 5GT/s

PCIe Link Width

J-PCIE

4 Links x 1 Lane @ 5GT/s

4 Lanes @ 5GT/s

4 Lanes @ 2.5GT/s

4 Lanes @ 2.5GT/s

1 Link x 4 Lanes @ 5GT/s

4 Links x 1 Lane @ 2.5GT/s

1 Link x 4 Lanes @ 2.5GT/s

1)

Consists to the non fat pipe slots, generally periphery slots 3 to 6.

When the port on J-PCIE is configured as single link, the PCIe switch may size down the link width to x2 or x1 by auto-negotiation.

© EKF -57- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

The following table shows the factory settings of DS-P with different side boards mounted to the

PC3-ALLEGRO:

Side Board

None

CCI-RAP

1

DS-P

2

OFF OFF

OFF OFF

PCIe Link Width

J-PCIE

4 Links x 1 Lane @ 5GT/s

4 Links x 1 Lane @ 5GT/s

CCK-

MARIMBA

ON OFF 1 Link x 4 Lanes @ 5GT/s

CCL-CAPELLA ON OFF 1 Link x 4 Lanes @ 5GT/s

CCO-CONCERT OFF ON 4 Links x 1 Lane @ 2.5GT/s

PCS-BALLET OFF OFF 4 Links x 1 Lane @ 5GT/s

© EKF -58- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Loading UEFI BIOS Setup Defaults (P-GP)

The jumper P-GP may be used to reset the UEFI BIOS configuration settings to a default state. The UEFI

BIOS on PC3-ALLEGRO stores most of its settings in an area within the BIOS flash, e.g. the actual boot devices. Using the jumper P-GP is only necessary, if it is not possible to enter the setup of the BIOS. To reset the settings mount a jumper on P-GP and perform a system reset. As long as the jumper is stuffed the BIOS will use the default configuration values after any system reset. To get normal operation again, the jumper has to be removed.

1

P-GP

P-GP

Jumper Removed 1)

Jumper Installed

Function

Normal operation

BIOS configuration reset performed

1)

This setting is the factory default

© EKF -59- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Manufacturer Mode Jumper (P-MFG)

The jumper P-MFG is used to bring the board into the manufacturer mode. This is necessary only on board production time and should not used by customers. For normal operation the jumper should be removed. The pin header P-MFG is not stuffed on the PC3-ALLEGRO by default.

1

P-MFG

P-MFG

Jumper Removed

1)

Jumper Installed

Function

Normal operation

Entering Manufacturer Mode

1)

This setting is the factory default

© EKF -60- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

RTC Reset (P-RTC)

The jumper P-RTC may be used to reset certain register bits of the battery backed RTC core within the

PCH QM77. This can be necessary under rare conditions (e.g. battery undervoltage), if the CPU fails to enter the BIOS POST after power on. Note that installing of jumper P-RTC will neither set UEFI BIOS

Setup to EKF Factory Defaults nor resets the time and date register values of the RTC (Real Time Clock).

To reset the RTC core the board must be removed from the system rack. Short-circuit the pins of P-RTC for about 1 sec. Thereafter reinstall the board to the system and switch on the power. It is important to accomplish the RTC reset while the board has no power. The pin header P-RTC is not stuffed on the

PC3-ALLEGRO by default.

1

P-RTC

P-RTC

Jumper Removed

1)

Jumper Installed

Function

Normal operation

RTC reset performed

1)

This setting is the factory default.

© EKF -61- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Connectors

Caution

Some of the internal connectors provide operating voltage (3.3V and 5V) to devices inside the system chassis, such as internal peripherals. Not all of these connectors are short circuit protected. Do not use these internal connectors for powering devices external to the computer chassis. A fault in the load presented by the external devices could cause damage to the board, the interconnecting cable and the external devices themselves.

© EKF -62- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Front Panel Connectors

With respect to the video connector, the PC3-ALLEGRO is available in two flavours, either dual mDP or

VGA.

PG

USB 3.0

GP

1 mDP

2

RST

HD

G-ETH

EB

PG

GP

USB 3.0

RST

HD

EB

G-ETH

V

G

A

PC3-ALLEGRO

Dual - mDP

PC3-ALLEGRO

VGA

© EKF -63- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

DisplayPort Connectors

The Intel® i7 processors used on PC3-ALLEGRO are equipped with an integrated graphics controller, which supports DisplayPort and SDVO interfaces permitting simultaneous independent operation of up to three displays. Two DP receptacles are available from the PC3-ALLEGRO front panel, as mDP

(Mini DisplayPort) connectors, which is a space saving alternate to the standard DP connector and is also specified by the VESA.

20

2

19

1

Mini DisplayPort J-DP1/2

20 PWR

1)

18

16

14

AUX_CH(N)

AUX_CH(P)

GND

8

6

12

10

4

2

LANE3(N)

LANE3(P)

GND

CONFIG2 (GND)

CONFIG1

Hot Plug Detect

7

5

11

9

3

19

17

15

13

1

GND

LANE2(N)

LANE2(P)

GND

LANE1(N)

LANE1(P)

GND

LANE0(N)

LANE0(P)

GND

1)

+3.3V protected by a self resetting PolySwitch fuse 0.75A. This voltage is switched on in S0 state only.

Most DisplayPort monitors come with the standard DP connector, hence requiring a mDP to DP cable assembly for use with the PC3-ALLEGRO. For attachment of either a classic style analog RGB monitor,

DVI or HDMI type display to the J-DP receptacles, there are both adapters and also adapter cables available.

© EKF -64- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Specified by the VESA DisplayPort connector standard is a dedicated power pin 20 (+3.3V 0.5A). Both the GPU (source side) and a DP monitor (sink side) must provide power via this pin. A VESA specified standard DisplayPort cable however must not connect the pins 20 of both cable ends, in order to avoid a back driving conflict. Unfortunately there are cable assemblies available with pin 20 passed through, with unpredictable results on the system behaviour. Before ordering DP cable assemblies, verify the associated wiring diagram.

Sample VESA Compliant Mini DisplayPort Cable Assemblies

2.0m Mini DisplayPort (mDP) to DisplayPort (DP) plug to plug cable assembly, VESA compliant

EKF Part. #270.66.2.02.0

Astron T2M2M20020-R

Molex

Roline

0687850003

1045636

Wieson G9858

© EKF -65- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Screw Locking Option for mDP Connectors

Opposite to the Standard DisplayPort cable connectors, mDP connectors are not provided with a latching device. For rugged applications with need for a connector locking mechanism, EKF offers two methods of fixing.

Option Screw-Lock Plate for mDP Cable Connectors

1. The front panel is provided with a threaded hole for fixing a removable H-shape retainer plate, which is available from EKF as accessory (image above).

2. As an alternate, the customer can use cable assemblies with screw-locked mDP connectors (image below). The front panel has to be modified however for this solution (two threaded holes in addition, please specify when ordering).

Screw-Locked mDP Connector Cable Assembly (Delock)

© EKF -66- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

A third DisplayPort video output is available when combining the PC3-ALLEGRO with the mezzanine side card PCS-BALLET. The standard DP connector is provided with latches, which may be important for some applications.

PC3-ALLEGRO w. PCS-BALLET C32-FIO (12HP)

© EKF -67- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC3-ALLEGRO w. PCS-BALLET Side Card & 2.5-Inch SSD (8HP)

PC3-ALLEGRO w. PCS-BALLET C32-FIO C20-SATA (12HP)

© EKF -68- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

VGA Video Connector

As an option, the PC3-ALLEGRO can be equipped with a legacy VGA connector (High-Density D-Sub

15-position female connector). The connector VGA replaces the two Mini DisplayPort receptacles, and the digital video interface therefore is not available concurrently with this option.

15

11

10

6

5

1

J-VGA (Option)

10

11

8

9

6

7

4

5

12

13

14

15

1

2

3

RED

GREEN

BLUE

NC

GND

GND

GND

GND

DDC_POW

1)

GND

NC

VGA_DDC_SDA

HSYNC

VSYNC

VGA_DDC_SCL

1)

+3.3V protected by a self resetting PolySwitch fuse 0.75A. This voltage is switched on in S0 state only.

© EKF -69- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

USB Connectors

The Intel® QM77 Platform Controller Hub incorporates a four-port USB 3.0 xHCI host controller. Two ports are directly available on the PC3-ALLEGRO front panel (type A receptacle), for attachment of external USB devices.

1

USB • Dual USB 3.0 Receptacle

USB 3.0 dual type A receptacle, stacked, 18-position

USB 3.0

1

2

2

7

8

9

5

6

3

4

VBUS +5V, 1.5A max

1)

USB D-

USB D+

GND

SS RX-

SS RX+

GND

SS TX-

SS TX+

1)

+5V via 1.5A current-limited electronic power switch. Power rail may be switched off by software independently for each port.

Another two USB 3.0 connectors would be available when the PC3-ALLEGRO is combined with the

PCS-BALLET mezzanine side card. EKF offers USB cable connector retainer solutions, for rugged applications (picture below).

© EKF -70- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Another two USB 3.0 connectors would be available when the PC3-ALLEGRO is combined with the

PCS-BALLET mezzanine side card.

PC3-ALLEGRO w. PCS-BALLET Mezzanine Side Card (8HP)

© EKF -71- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PG

USB 3.0

1

USB 3.0

GP

1

2

RST

HD

EB

2 mDP

G-ETH

S

D

I

A

U

O

D

C

O

M

A

DP

OUT

IN

PG

USB 3.0

1

USB 3.0

2

C

O

M

D

GP

1

RST

2 mDP

G-ETH

S

A

U

D

I

O

DP

OUT

IN

/

M

K

B

S

U

S

B

HD

EB

D

C

O

M

A

C

O

M

C

PC3-ALLEGRO

Dual - mDP

PCS-BALLET

RS-232

PC3-ALLEGRO

Dual - mDP

PCS-BALLET

RS-232

C32-FIO

8HP and 12HP front panel assembly

© EKF -72- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Ethernet Connectors

1

1

270.02.08.5

Gigabit Ethernet Ports 1/2 (J-ETH, RJ-45)

3

4

1

2

Port 1

7

8

5

6

Port 2

6

7

8

3

4

1

2

5

NC1_MDX0+

NC1_MDX0-

NC1_MDX1+

NC1_MDX2+

NC1_MDX2-

NC1_MDX1-

NC1_MDX3+

NC1_MDX3-

NC2_MDX0+

NC2_MDX0-

NC2_MDX1+

NC2_MDX2+

NC2_MDX2-

NC2_MDX1-

NC2_MDX3+

NC2_MDX3-

The lower green LED indicates LINK established when continuously on, and data transfer (activity) when blinking. If the lower green LED is permanently off, no LINK is established. The upper green/yellow dual-LED signals the link speed 1Gbit/s when lit yellow, 100Mbit/s when lit green, and

10Mbit/s when off.

© EKF -73- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Mezzanine Connectors

Mezzanine Side Card Connector Suite

© EKF -74- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Expansion Interface J-EXP

1 2

1.27mm

Socket

40

J-EXPT (J-EXPB optinal)

GND

PCI_CLK (33MHz)

LPC_AD0

LPC_AD2

5

7

1

3

6

8

2

4

LPC_FRM#

GND

LPC_SERIRQ

EXP_SMI#

FWH_ID0

KBRST#

GND

USB_EXP2-

USB_EXP2+

USB_EXP_OC#

EXP_SCL

2)

GND

HDA_SDOUT

HDA_RST#CL_RST#

3)

HDA_CLK/CL_CLK

3)

SPEAKER

35

37

39

27

29

31

33

17

19

21

23

25

9

11

13

15

36

38

40

28

30

32

34

18

20

22

24

26

10

12

14

16

+3.3V

1)

RST_PLC#

LPC_AD1

LPC_AD3

LPC_DRQ#

+3.3V

1)

WAKE#

SIO_CLK (14.3MHz)

FWH_INIT#

A20GATE

+5V

1)

USB_EXP1-

USB_EXP1+

DBRESET#

EXP_SDA

2)

+5V

1)

HDA_SDIN0

HDA_SYNC

HDA_SDIN1/CL_DATA

3)

+12V

4)

1)

2)

3)

4)

Power rail switched on in state S0 only.

Connected to SMBus via buffered switch, isolated after reset.

Stuffing option, default is the HDA option.

Power rail switch off in state S5.

The expansion interface header footprint is available on both sides of the board, top (J-EXPT) and bottom (J-EXPB). The bottom side connector is stuffed only on customers request.

WARNING: The +3.3V/+5V/+12V power pins are not protected against a short circuit event. The connector J-EXP therefore should be used only for attachment of an approved expansion side card.

The maximum current flow across these pins should be limited to 1A per power pin.

© EKF -75- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

High Speed Expansion Connector J-HSE s1 a1 b1 s10 s9 a25 b25 s18

High Speed Expansion J-HSE

GND

SATA_HSE1_TXP

5)

SATA_HSE1_TXN

5)

GND

SATA_HSE1_RXN

5)

SATA_HSE1_RXP

5)

GND

SATA_HSE2_TXP

4) 5)

SATA_HSE2_TXN

4) 5)

GND

SATA_HSE2_RXN

4) 5)

SATA_HSE2_RXP

4) 5)

GND a9 a10 a11 a12 a13 a5 a6 a7 a8 a1 a2 a3 a4

USB_HSE1_P

USB_HSE1_N

GND

USB_HSE2_P

USB_HSE2_N

GND

USB_HSE_OC1#

USB_HSE_OC2#

+3.3VS

1)

+3.3VS

1)

+3.3VA

2)

+12V

3) a18 a19 a20 a21 a14 a15 a16 a17 a22 a23 a24 a25 b14 b15 b16 b17 b9 b10 b11 b12 b13 b5 b6 b7 b8 b1 b2 b3 b4 b22 b23 b24 b25 b18 b19 b20 b21

GND

SATA_HSE3_TXP

4) 5)

SATA_HSE3_TXN

4) 5)

GND

SATA_HSE3_RXN

4) 5)

SATA_HSE3_RXP

4) 5)

GND

SATA_HSE4_TXP

5)

SATA_HSE4_TXN

5)

GND

SATA_HSE4_RXN

5)

SATA_HSE4_RXP

5)

GND

USB_HSE3_P

USB_HSE3_N

GND

USB_HSE4_P

USB_HSE4_N

GND

USB_HSE_OC34#

USB_HSE_OC34#

+5VS

1)

+5VS

1)

+5VA

2)

+12V

3)

1)

2)

3)

4)

5)

Power rail switched on in state S0 only (Switched).

Power rail on with system stand-by power (Always).

Power rail switch off in state S5.

This SATA channel is capable to perform up to 6Gbps.

All TX/RX designations with respect to the SATA controller.

WARNING: The +3.3V/+5V/+12V power pins are not protected against a short circuit event. The connector J-HSE therefore should be used only for attachment of an approved expansion side card.

The maximum current flow through these power pins should be limited to 0.5A per pin.

© EKF -76- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC3-ALLEGRO w. C47-MSATA Dual SSD Mezzanine Storage Module

PC3-ALLEGRO w. C48-M2 Dual M.2 SATA SSD Module

© EKF -77- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PCI Express® Expansion Header J-PCIE

27

29

31

33

17

19

21

23

25

35

37

39

9

11

13

15

5

7

1

3

GND

+5V

1)

+5V

1)

GND

J-PCIE

GND

PE_3TP

PE_3TN

GND

PE_4TP

PE_4TN

GND

PE_CLKP

PE_CLKN

GND

PE_1TP

PE_1TN

GND

GND

PE_2TP

PE_2TN

28

30

32

34

18

20

22

24

26

36

38

40

10

12

14

16

6

8

2

4

PE_1RN

GND

GND

PE_2RP

PE_2RN

GND

PE_3RP

PE_3RN

GND

GND

+3.3V

1)

+3.3V

1)

GND

PLTRST#

PE_WAKE#

GND

PE_1RP

PE_4RP

PE_4RN

GND

1)

Power rail switched on in state S0 only.

WARNING: The +3.3V/+5V power pins are not protected against a short circuit event. The connector

J-PCIE therefore should be used only for attachment of an approved expansion side card. The maximum current flow through these power pins should be limited to 1A per pin.

© EKF -78- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

SDVO/DisplayPort Expansion Header J-SDVO

J-SDVO

GND

SDVO_RED+/DP_LANE0+

SDVO_RED-/DP_LANE0-

GND

SDVO_GREEN+/DP_LANE1+

SDVO_GREEN-/DP_LANE1-

GND

SDVO_BLUE+/DP_LANE2+

SDVO_BLUE-/DP_LANE2-

GND

9

11

13

15

17

19

5

7

1

3

10

12

14

16

18

20

6

8

2

4

GND

SDVO_CLK+/DP_LANE3+

SDVO_CLK-/DP_LANE3-

GND

SDVO_INT+/DP_AUX+

SDVO_INT-/DP_AUX-

GND

SDVO_CTR_CLK/DP_HPD

SDVO_CTR_DATA/DP_CFG1

GND

To use J-SDVO as either an SDVO or a further DisplayPort interface, some of the control lines are configurable by a multiplexer. The state of this multiplexer is controlled by PCH QM77 GPIO16 and adjustable by BIOS. Setting GPIO16 to LO configures the connector J-SDVO to work in SDVO mode.

In this case pins 10/12 carry the SDVO_INT and pins 16/18 the SDVO_CTR function.

This option was removed with BIOS#126!

With GPIO16 set to HIGH the connector behaves like a DisplayPort interface. The pins 10/12 function as DP_AUX while pin 16 and 18 are connected to DP_HPD and DP_CFG1 respectively.

© EKF -79- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC3-ALLEGRO w. PCS-BALLET & Half-Slim SATA SSD (8HP)

PC3-ALLEGRO w. PCS-BALLET & C41-CFAST (8HP)

© EKF -80- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Typical 8HP Assembly w. PCS-BALLET Side Card & C42-SATA

8HP Assembly w. PCS-BALLET Side Card & C47-MSATA

© EKF -81- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PC3-ALLEGRO w. PCL-CAPELLA Side Card 8HP Assembly

PC3-ALLEGRO w. PCL-CAPELLA Side Card 8HP Assembly

© EKF -82- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Pin Headers & Debug

Front Panel Handle Microswitch Header P-FPH

The jumper P-FPH is used for attachment of an external SPDT switch. By default, P-FPH is connected across a short cable harness to a microswitch, which is integrated into the PC3-ALLEGRO front panel handle (ejector lever). The switch performs a power button event (e.g. system shutdown) by shortcircuiting the pins 1 and 3 of P-FPH when activated (hold unlock button of front panel handle depressed momentarily).

P-FPH

# 276.02.003.11

© EKF • ekf.com

1

1

2

3 black red yellow

Microswitch Pole (Common), Wired to PLD

Microswitch Throw - F/P Handle Locked Position, NC

Microswitch Throw - F/P Handle Unlocked Position, Wired to GND

© EKF -83- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

PLD Programming Header P-ISP

The PC3-ALLEGRO is provided with a powerful PLD (in-System Programmable Logic Device) which replaces legacy glue logic. The programming header P-ISP is not stuffed (in use for manufacturing only). Its footprint is situated at the bottom side of the board.

P-ISP

240.1.08.I • © EKF • ekf.com

key

7

8

5

6

1

2

3

4

+3.3V

TDO

TDI

NC

KEY

TMS

GND

TCK

© EKF -84- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Processor Debug Header XDP1

The PC3-ALLEGRO may be equipped with a 26-position processor debug header for hard- and software debugging (specified by Intel® as XDP-SFF-26 Pin Platform Connection). The connector is suitable for installation of a flat flex cable (FFC), in order to attach an JTAG debugger (emulator) such as the Arium ECM-XDP3. An adapter (ITP-XDP-SFF-26) is required in addition to convert the 26-pin

XDP-SFF-26 Pin connector to the standard 60-pin XDP.

The header XDP1 would be mounted on the PCB bottom side, but is not stuffed by default.

XDP Processor Debug Connector

269.1.026.902

• FFC Connector

© EKF • ekf.com

13

15

17

19

21

23

25

9

11

5

7

1

3

OBSFN_A0 (PREQ#)

GND

OBSDATA_A1

OBSDATA_A2

GND

HOOK1 (XDP_PWRBTN)

HOOK3 (SYS_PWROK)

HOOK5 (BCLKN)

HOOK6 (PLTRST#)

GND

TRST#

TMS

GND

OBSFN_A1 (PRDY#)

OBSDATA_A0

GND

OBSDATA_A3

HOOK0 (CPU_PWRGOOD)

HOOK2 (CFG[0])

HOOK4 (BCLKP)

VCCOBS_AB (+1.05V)

HOOK7 (DBRESET#)

TDO

TDI

TCK1

TCK0 (TCK)

14

16

18

20

22

24

26

10

12

6

8

2

4

© EKF -85- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

Backplane Connectors

CompactPCI

J1

J1

25

7

6

5

12

11

10

9

8

2

1

4

3

15

14

13

18

17

16

21

20

19

24

23

22

AD18

AD21

C/BE3#

AD26

AD30

REQ# 1)

BRSVP1A5 4)

IPMB PWR

INTA#

1)

TCK 4)

5V

A

5V

AD1

3.3V

AD7

3.3V

AD12

3.3V

SERR#

1)

3.3V

DEVSEL#

1)

3.3V

AD17

GND

GND

GND

AD29

GND

BRSVP1B5 4)

GND

INTB#

1)

5V

-12V 5)

B

REQ64# 2)

5V

AD4

GND

AD9

GND

AD15

GND

IPMB SCL 3)

GND

FRAME#

1)

AD16

3.3V

AD23

V(I/O)

AD28

3.3V

RST#

V(I/O)

INTC#

1)

TMS 4)

TRST# 4)

C

ENUM# 1)

V(I/O)

AD3

3.3V

AD8

V(I/O)

AD14

3.3V

IPMB SDA 3)

V(I/O)

IRDY#

1)

KEY AREA

GND

AD20

GND

AD25

GND

CLK

GND

INTP

1)

5V

TDO 4)

+12V

D

3.3V

AD0

5V

AD6

GND/M66EN

7)

AD11

GND

PAR

GND

STOP#

1)

BD_SEL#

6)

C/BE2#

AD19

AD22

AD24

AD27

AD31

GNT#

INTS

1)

INTD#

1)

TDI 4)

5V

E

5V

ACK64# 2)

AD2

AD5

C/BE0#

AD10

AD13

C/BE1#

PERR# 1)

LOCK#

1)

TRDY#

1)

1)

2)

This pin is pulled up with 1kS to V(I/O).

This pin is not used on PC3-ALLEGRO, but pulled up with 1kS to V(I/O).

3)

4)

5)

This pin is pulled up with 3.0k to J1 pin A4.

This pin is not connected.

This pin is connected to a decoupling capacitor only and not used on PC3-ALLEGRO.

6)

7)

This pin is connected to power sequencing logic and should pulled low for normal operation.

This pin can be pulled down on PC3-ALLEGRO to force 33 MHz operation on request. The PC3-ALLEGRO is capable to

operate with 66 MHz on the CPCI Bus by default

.

© EKF -86- ekf.com

User Guide • PC3-ALLEGRO • CompactPCI

®

PlusIO CPU Board • Intel® i7-3xxx Processor

CompactPCI

J2 (PlusIO)

9

8

7

2_ETH_D+

BRSVP2A18

2_ETH_D-

BRSVP2A17

4_PE_CLK-

BRSVP2A16

4_PE_CLK+

BRSVP2A15

3_PE_CLK-

AD35

3_PE_CLK+

AD38

4_PE_RX00+

AD42

4_PE_RX00-

AD45

3_PE_RX00+

AD49

3_PE_RX00-

AD52

2_PE_RX00+

AD56

2_PE_RX00-

AD59

1_PE_RX00+

AD63

1_PE_RX00-

C/BE5#

V(I/O)

CLK4

CLK2

CLK1

This connector is a high speed UHM connector, suitable for Gigabit Serial I/O

Refer also to PICMG® 2.30 CompactPCI® PlusIO Specification

4

3

2

1

18

17

16

6

5

11

10

13

12

15

14

20

19

J2

22

21

A

GA4

2)

CLK6

CLK5

GND

B

GA3

2)

GND

GND

GND

3_PE_TX00+

GND

3_PE_TX00-

AD55

2_PE_TX00+

GND

2_PE_TX00-

AD62

1_PE_TX00+

64EN#

1_PE_TX00-

BRSVP2B4

GND

CLK3

GND

2_ETH_C+

BRSVP2B18

2_ETH_C-

GND

2_PE_CLK+

BRSVP2B16

2_PE_CLK-

GND

1_PE_CLK+

AD34

1_PE_CLK-

GND

1_PE_CLKE#

AD41

4_PE_TX00+

GND

4_PE_TX00-

AD48

DEG# 1)

FAL#

1)

(PSON#)

6)

4_PE_CLKE#

AD33

3_PE_CLKE#

V(I/O)

2_PE_CLKE#

AD40

4_USB2+

V(I/O)

4_USB2-

AD47

3_USB2+

V(I/O)

3_USB2-

AD54

2_USB2+

V(I/O)

2_USB2-

AD61

1_USB2+

V(I/O)

1_USB2-

C/BE7#

GNT3#

SYSEN#

3)

REQ1#

1)

C

GA2

2)

2_ETH_B+

RSV

2_ETH_B-

RSV

2_ETH_A+

RSV

2_ETH_A-

BRSVP2C18

PRST#

1)

GND

REQ5#

1)

SATA_SCL

GND

SATA_SDO

AD37

SATA_SDI 2)

GND

4_SATA_TX+

AD44

4_SATA_TX-

GND

3_SATA_TX+

AD51

3_SATA_TX-

GND

2_SATA_TX+

AD58

2_SATA_TX-

GND

1_SATA_TX+

C/BE4#

1_SATA_TX-

GND

REQ4# 1)

GNT2#

GNT1#

D

GA1

2)

1_ETH_D+

RSV

1_ETH_D-

GND

1_ETH_C+

RSV

1_ETH_C-

GND

REQ6#

1) reserved 2)

BRSVP2E16

GNT5# reserved 2)

AD32

SATA_SL

AD36

4_SATA_RX+

AD39

4_SATA_RX-

AD43

3_SATA_RX+

AD46

3_SATA_RX-

AD50

2_SATA_RX+

AD53

2_SATA_RX-

AD57

1_SATA_RX+

AD60

1_SATA_RX-

PAR64 reserved

2)

C/BE6#

GNT4#

REQ3#

1)

REQ2#

1)

E

GA0

2)

1_ETH_B+

RSV

1_ETH_B-

RSV

1_ETH_A+

RSV

1_ETH_A-

BRSVP2E18

GNT6#

© EKF -87- ekf.com

User Guide • PC3-ALLEGRO •

CompactPCI ® Serial

CPU Board • Intel® i7-3xxx Processor

1)

4)

5)

2)

3)

6)

This pin is pulled up with 1kS to V(I/O). Alternate pull up resistor values (e.g. 2.7kS for

V(I/O)=+3.3V) are available on request.

This pin is not connected.

This pin is pulled up with 10kS to +3.3V.

Pin positions printed italic: 64-bit system slot signals (for reference only).

Pin positions printed blue: PlusIO options.

As an exclusive stuffing option J2-C15 can be utilised as PSON# output. f e d c b a

25 f e d c b a

22

1 1

J2 UHM (Upper)

J1 (Lower)

© EKF -88- ekf.com

User Guide • PC3-ALLEGRO •

CompactPCI ® Serial

CPU Board • Intel® i7-3xxx Processor

Beyond All Limits:

EKF High Performance Embedded

Industrial Computers Made in Germany boards. systems. solutions.

EKF Elektronik GmbH

Philipp-Reis-Str. 4 (Haus 1)

Lilienthalstr. 2 (Haus 2)

59065 HAMM

Germany

Phone +49 (0)2381/6890-0

Fax +49 (0)2381/6890-90

Internet www.ekf.com

E-Mail [email protected]

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