SDR SODIMM based on 128Mb E-die_14.fm

SDR SODIMM based on 128Mb E-die_14.fm

64MB, 128MB Unbuffered SODIMM SDRAM

SDRAM Unbuffered SODIMM

144pin Unbuffered SODIMM based on 128Mb E-die

64-bit Non ECC

Revision 1.4

March. 2004

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

Revision History

Revision 1.0 (November, 2002)

- First release

Revision 1.1 (May. 2003)

- Merged Spec.

Revision 1.2 (June. 2003)

- Correct Typo.

Revision 1.3 (February. 2004)

- Correct Typo.

Revision 1.4 (March. 2004)

- Corrected package dimension.

SDRAM

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

144Pin Unbuffered DIMM based on 128Mb E-die (x16)

SDRAM

Ordering Information

Part Number

M464S0924ETS-C(L)7A

M464S1724ETS-C(L)7A

Density

64MB

128MB

Organization

8M x 64

16M x 64

Component Composition

8Mx16(K4S281632E) * 4EA

8Mx16( K4S281632E) * 8EA

Component

Package

54-TSOPII

54-TSOPII

Height

1,000mil

1,250mil

Operating Frequencies

- 7A

Maximum Clock Frequency

CL-tRCD-tRP(clock)

@CL3

133MHz(7.5ns)

3 - 3 - 3

Feature

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V

± 0.3V power supply

• MRS cycle with address key programs Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Serial presence detect with EEPROM

@CL2

100MHz(10ns)

2 - 2 - 2

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Back Pin Front Pin Back

25

27

29

31

33

17

19

21

23

7

9

11

13

15

1

3

5

43

45

47

49

35

37

39

41

DQ6

DQ7

VSS

DQM0

DQM1

VDD

A0

A1

A2

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

VSS

DQ8

DQ9

DQ10

DQ11

VDD

DQ12

DQ13

26

28

30

32

34

18

20

22

24

8

10

12

14

16

2

4

6

44

46

48

50

36

38

40

42

DQ38

DQ39

VSS

DQM4

DQM5

VDD

A3

A4

A5

VSS

DQ32

DQ33

DQ34

DQ35

VDD

DQ36

DQ37

VSS

DQ40

DQ41

DQ42

DQ43

VDD

DQ44

DQ45

51

53

55

57

59

87

89

91

93

79

81

83

85

69

71

73

75

77

61

63

65

67

DQ14

DQ15

VSS

NC

NC

Voltage Key

NC

VDD

DQ16

DQ17

DQ18

DQ19

VSS

DQ20

**CLK0

VDD

RAS

WE

**CS0

**CS1

DU

VSS

NC

52

54

56

58

60

88

90

92

94

80

82

84

86

70

72

74

76

78

62

64

66

68

DQ46

DQ47

Note :

1.* These pins are not used in this module.

2.Pins 141,142 should be NC in the system which does not support SPD.

3.** About these pins, Refer to the Block Diagram of each.

VSS

NC

NC

NC

VDD

DQ48

DQ49

DQ50

DQ51

VSS

DQ52

**CKE0

VDD

CAS

**CKE1

*A12

*A13

**CLK1

VSS

NC

Pin Description

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

CLK0 ~ CLK1

CKE0 ~ CKE1

CS0 ~ CS1

RAS

CAS

Function

Address input (Multiplexed)

Select bank

Data input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Pin Name

WE

DQM0 ~ 7

V

DD

V

SS

SDA

SCL

DU

NC

Function

Write enable

DQM

Power supply (3.3V)

Ground

Serial data I/O

Serial clock

Don

′t use

No connection

Pin

111

113

115

117

119

121

123

125

127

95

97

99

101

103

105

107

109

129

131

133

135

137

139

141

143

Front

A10/AP

VDD

DQM2

DQM3

VSS

DQ24

DQ25

DQ26

DQ27

DQ21

DQ22

DQ23

VDD

A6

A8

VSS

A9

VDD

DQ28

DQ29

DQ30

DQ31

VSS

SDA

VDD

Pin

112

114

116

118

120

122

124

126

128

96

98

100

102

104

106

108

110

130

132

134

136

138

140

142

144

SDRAM

Back

A11

VDD

DQM6

DQM7

VSS

DQ56

DQ57

DQ58

DQ59

DQ53

DQ54

DQ55

VDD

A7

BA0

VSS

BA1

VDD

DQ60

DQ61

DQ62

DQ63

VSS

SCL

VDD

* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM SDRAM

PIN CONFIGURATION DESCRIPTION

CLK

Pin

CS

CKE

A0 ~ A11

BA0 ~ BA1

Bank select address

RAS

CAS

WE

DQM0 ~ 7

DQ

0

~

63

V

DD

/V

SS

Name

System clock

Chip select

Clock enable

Address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+t

SS

prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11

Column address : (x16 : CA0 ~ CA8)

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

64MB, 8Mx64 Module (M464S0924ETS)

(Populated as 1 bank of x16 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

SDRAM

DQM0

CS0

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U0

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

DQn

10

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

Every DQ pin of SDRAM

V

DD

Three 0.1uF X7R 0603Capacitors per each SDRAM

Vss

To all SDRAMs

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

SCL

47K Ω

Serial PD

WP

SA0 SA1 SA2

CLK0

CLK1

U0

U1

U2

10

U3

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

SDA

10pF

Note :

Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs.

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

128MB, 16Mx64 Module (M464S1724ETS)

(Populated as 2 bank of x16 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

SDRAM

CS1

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM2

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U0

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

CKE1

DQn

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U3

SDRAM U4 ~ U7

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

10

Every DQ pin of SDRAM

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

SCL

47K

V

DD

Three 0.1 uF X7R 0603 Capacitors per each SDRAM

To all SDRAMs

CLK0/1

Vss

Note :

Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs.

Serial PD

WP

SA0 SA1 SA2

U0/U4

U1/U5

U2/U6

U3/U7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

SDA

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

DD

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

V

IN

, V

OUT

V

DD

, V

DDQ

T

STG

P

D

I

OS

Value

-1.0 ~ 4.6

-1.0 ~ 4.6

-55 ~ +150

1.0 * # of component

50

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

SDRAM

Unit

V

V

°C

W mA

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

SS

= 0V, T

A

= 0 to 70

°C)

Parameter

Supply voltage

Input high voltage

Input low voltage

Symbol

V

DD

V

IH

V

IL

Min

3.0

2.0

-0.3

Typ

3.3

3.0

0

Max

3.6

V

DDQ

+0.3

0.8

Unit

V

V

V

Output high voltage

Output low voltage

V

OH

V

OL

2.4

-

-

0.4

V

V

Input leakage current I

LI

-10 10 uA

Notes :

1. V

IH

(max) = 5.6V AC.The overshoot voltage duration is

≤ 3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

≤ 3ns.

3. Any input 0V

≤ V

IN

≤ V

DDQ

.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Note

1

2

I

OH

= -2mA

I

OL

= 2mA

3

CAPACITANCE

(V

DD

= 3.3V, T

A

= 23

°C, f = 1MHz, V

REF

= 1.4V

± 200 mV)

Parameter

Input capacitance (A

0

~ A

11

, BA0 ~ BA1)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0 ~ CKE1)

Input capacitance (CLK0 ~ CLK1)

Input capacitance (CS0 ~ CS1)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

Symbol

C

IN1

C

IN2

C

IN3

C

IN4

C

IN5

C

IN6

C

OUT

M464S0924ETS

Min Max

15

15

10

10

15

15

15

21

25

12

12

25

25

25

M464S1724ETS

Min Max

15

15

10

10

25

25

15

21

25

12

12

45

45

25

Unit

pF pF pF pF pF pF pF

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

DC CHARACTERISTICS

M464S0924ETS (8M x 64, 64MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

I

I

CC2

CC2

CC2

CC2

P

PS

N

NS

I

CC3

P

I

CC3

PS

I

CC3

N

I

CC3

NS

I

I

I

I

CC1

CC4

CC5

CC6

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

C

L

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

Version

-7A

400

40

20

20

120

8

8

80

100

560

800

8

3.2

mA mA mA mA mA mA mA

SDRAM

Unit Note

mA mA mA

1

1

2

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

DC CHARACTERISTICS

M464S1724ETS (16M x 64, 128MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

I

I

CC2

CC2

I

I

CC2

CC2

CC5

CC6

P

PS

N

NS

I

CC3

P

I

CC3

PS

I

CC3

N

I

CC3

NS

I

I

CC1

CC4

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

C

L

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

Version

-7A

520

80

40

40

240

16

16

160

200

680

920

16

6.4

mA mA mA mA

SDRAM

Unit Note

mA mA mA mA mA mA

1

1

2

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

AC OPERATING TEST CONDITIONS

(V

DD

= 3.3V

± 0.3V, T

A

= 0 to 70

°C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

3.3V

Output

870

1200

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

50pF

Output

SDRAM

Unit

V

V ns

V

Z0 = 50

Vtt = 1.4V

50

50pF

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

(Fig. 2) AC output load circuit

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

Row cycle time

Parameter

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay

Number of valid output data

Symbol

t

RRD

(min) t

RCD

(min) t

RP

(min) t

RAS

(min) t

RAS

(max) t

RC

(min) t

RDL

(min) t

DAL

(min) t

CDL

(min) t

BDL

(min) t

CCD

(min)

CAS latency=3

CAS latency=2

Version

- 7A

15

20

20

45

100

65

2

2 CLK + tRP

1

1

1

2

1

Unit

us ns

CLK

ns ns ns ns

CLK

CLK

CLK ea

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Note

1

2

4

1

1

1

1

2

2

3

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

t

CH t

CL t

SS t

SH t

SLZ

1.5

0.8

1

3

3

2.5

2.5

- 7A

Parameter

CLK cycle time

CLK to valid output delay

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

Output data hold time

CAS latency=3

CAS latency=2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3

CAS latency=2

Symbol

t t t

CC

SAC

OH

Min

7.5

10

Max

1000

5.4

6 t

SHZ

5.4

6

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

SDRAM

Unit

ns ns ns ns ns ns ns ns ns

Note

1

1,2

2

3

3

3

3

2

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM SDRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

′t care, H=Logic high, L=Logic low)

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA

0,1

A

10

/AP

A

0

~ A

9,

A

11

Register

Refresh

Mode register set

Auto refresh

Entry

Self refresh

Exit

H

H

L

X

H

L

H

L

L

L

H

L

L

L

H

X

L

L

L

H

X

H

L

H

H

X

H

X

X

X

OP code

X

X

Bank active & row addr.

Read & column address

Auto precharge disable

Auto precharge enable

Write & column address

Auto precharge disable

Auto precharge enable

Burst stop

H

H

H

H

X

X

X

X

L

L

L

H

H

H

L

L

H

H

L

L

X

X

X

X

V

V

V

L

H

Row address

L

H

Column address

Column address

X

Precharge

Bank selection

All banks

H X L L H L X

V

X

L

H

X

Clock suspend or active power down

Entry H L

H

L

X

V

X

V

X

V

X

X

Exit L H X

H

X

X

X

X

X

X

X

Precharge power down mode

Entry H L

L

H

H

X

H

X

H

X

X

X

Exit L H X

L V V V

DQM H

X

V X

Notes :

H X X X

No operation command H X X X

L H H H

1. OP Code : Operand code

A

0

~ A

11

& BA

0

~ BA

1

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

~ BA

1

: Bank select addresses.

If both BA

0

and BA

1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA

0

is "High" and BA

1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA

0

is "Low" and BA

1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA

0

and BA

1 are "High" at read, write, row active and precharge, bank D is selected.

If A

10

/AP is "High" at row precharge, BA

0

and BA

1

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Note

7

1,2

3

3

3

3

4

4,5

4

4,5

6

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

PACKAGE DIMENSIONS : 8Mx64 (M464S0924ETS)

SDRAM

Units : Inches (Millimeters)

2.66

(67.56)

2.50

(63.60)

0.16

±

0.039

(4.00

±

0.10)

0.13

(3.30)

1

0.15

(3.70)

2

0.91

(23.20)

0.10

(2.50)

59 61

0.18

(4.60)

0.083

(2.10)

1.29

(32.80)

Z

60 62

143

144

Y

2-

φ

0.07

(1.80)

2-R 0.078 Min

(2.00 Min)

0.150 Max

(3.80 Max)

0.04

(1.00

±

0.0039

±

0.10)

Tolerances :

± 0.006(.15) unless otherwise specified

The used device is 8Mx16 SDRAM, TSOPII

SDRAM Part No. : K4S281632E

0.16

±

0.0039

(4.00

±

0.10)

Detail Z

0.06

±

0.0039

(1.50

±

0.1)

0.024

±

0.001

(0.600

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.03 TYP

(0.80 TYP)

Detail Y

Rev. 1.4 March. 2004

64MB, 128MB Unbuffered SODIMM

PACKAGE DIMENSIONS : 16Mx64 (M464S1724ETS)

SDRAM

Units : Inches (Millimeters)

2.66

(67.56)

2.50

(63.60)

0.16

±

0.039

(4.00

±

0.10)

0.13

(3.30)

1

0.15

(3.70)

2

0.91

(23.20)

0.10

(2.50)

59 61

0.18

(4.60)

0.083

(2.10)

1.29

(32.80)

Z

60 62

143

144

Y

2-

φ

0.07

(1.80)

2-R 0.078 Min

(2.00 Min)

0.150 Max

(3.80 Max)

0.04

(1.00

±

0.0039

±

0.10)

Tolerances :

±.006(.15) unless otherwise specified

The used device is 8Mx16 SDRAM, TSOPII

SDRAM Part No. : K4S281632E

0.16

±

0.0039

(4.00

±

0.10)

Detail Z

0.06

±

0.0039

(1.50

±

0.1)

0.024

±

0.001

(0.600

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.03 TYP

(0.80 TYP)

Detail Y

Rev. 1.4 March. 2004

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