Keysight U7232D DisplayPort Electrical Performance Compliance

Keysight U7232D DisplayPort Electrical Performance Compliance
Keysight U7232D
DisplayPort Electrical
Performance Compliance
Test Application
Methods of
Implementation
Notices
© Keysight Technologies 2007-2017
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U7232-97005
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Software Version
03.61.0000
Edition
Tenth Edition, March 2017
Keysight Technologies, Inc.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort Automated Testing—At A Glance
The Keysight U7232D DisplayPort Electrical Performance Compliance Test Application helps you
verify compliance of the DisplayPort devices to DisplayPort specifications using Keysight Infiniium
Digital Storage Oscilloscopes with bandwidths of 13 GHz or higher. The DisplayPort Electrical
Performance Compliance Test Application:
NOTE
•
Lets you select individual or multiple tests to run.
•
Lets you identify the device being tested and its configuration.
•
Shows you how to make oscilloscope connections to the device under test.
•
Automatically checks for proper oscilloscope configuration.
•
Automatically sets up the oscilloscope for each test.
•
Provides detailed information for each test that has been run and lets you specify the thresholds
at which marginal or critical warnings appear.
•
Creates a printable HTML report of the tests that have been run.
The tests performed by the DisplayPort Electrical Performance Compliance Test Application are
intended to provide a quick check of the electrical health of the DUT. This testing is not a replacement
for an exhaustive test validation plan.
You may refer to the following specification documents for compliance testing measurements. For
more information, see the VESA web site at www.vesa.org.
Test Specification
Reference Documents
DisplayPort 1.4 (1.4)
VESA DisplayPort (DP) Standard Version 1.4, February 23, 2016
DisplayPort 1.2 (1.2b)
VESA DisplayPort Standard Version 1, Revision 2a, May 23, 2012
VESA DisplayPort PHY Compliance Test Specification Version 1.2b, November 26, 2012
Mobility DisplayPort 1.0 (MyDP)
VESA Mobility DisplayPort (MyDP) Standard Version 1, May 21, 2012
VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, April 26, 2013
SlimPort (MyDP HBR25)
SlimPort Compliance Test Specification Version 1, February 28, 2014
Required Equipment and Software
In order to run the DisplayPort automated tests, you need the following equipment and software:
•
Infiniium 90000A Series/90000X Series/90000Q Series/V-Series/Z-Series Digital Storage
Oscilloscopes with a bandwidth of 13GHz or higher.
•
The minimum version of Infiniium Oscilloscope Software (see the U7232D DisplayPort
Compliance Test Application Release Notes).
•
U7232D DisplayPort Electrical Performance Compliance Test Application.
•
Keyboard, qty = 1, (provided with the Keysight Infiniium oscilloscope).
•
Mouse, qty = 1, (provided with the Keysight Infiniium oscilloscope).
•
U7232D DisplayPort Electrical Performance Compliance Test Application license.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
3
In order to run the automated tests on DisplayPort DUTs, you need the following fixtures and
accessories:
•
DisplayPort Test Point Adapter:
For DUT Type
Required Fixtures/Accessories (Recommended)
Source
For DisplayPort Type-C Connector
• N7015A Type-C High-Speed Test Fixture
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
Sink or Cable
Quantity
Recommended Oscilloscope
1 (each)
Infiniium Series
For DisplayPort Connector
• Wilder technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Receptacle (mDP-TPA-R)**
For MyDP Connector
• Wilder Technologies (MYDP-TPA-R*)
* All Wilder Technologies Test Point Adapters require the Wilder Technologies DP-TPA-A Aux Control Board.
** All Luxshare ICT Test Point Adapters require the Luxshare ICT DP-TPA-A AUX Control Board.
• InfiniiMax Series Probe Amplifiers with minimum 12GHz bandwidth:
•
Required Fixtures/Accessories (Recommended)
Quantity
Recommended Oscilloscope
•
•
•
4
Infiniium Series
1169A 12GHz InfiniiMax II Series Probe Amplifier
N2832A 13GHz InfiniiMax III+ Series Probe Amplifier
N2800A 16GHz InfiniiMax III Series Probe Amplifier
InfiniiMax Series Probe Head with minimum 12GHz bandwidth:
Test Type
Required Fixtures/Accessories (Recommended)
Quantity
Physical Layer Tests
•
•
N5380A InfiniiMax II 12GHz Differential SMA Adapter
N5444A InfiniiMax III 28GHz SMA Probe Head
4
AUX Channel Tests
•
E2677A InfiniiMax 12GHz Differential Solder-In
Probe Head
E2678A/B InfiniiMax 12GHz
Single-Ended/Differential Probe Head & Accessories
•
4
Recommended Oscilloscope
Infiniium Series
1
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
•
•
Other Equipment (required for Internal/Self Calibration of the Infiniium Oscilloscope):
Required Fixtures/Accessories (Recommended)
Quantity
Recommended Oscilloscope/Description
BNC to SMA (male) Converter
4
Infiniium 90000A Series
SMA (male) to SMA (male) Converter
4
Infiniium 90000X Series/90000Q Series/V-Series/Z-Series
E2655A/B/C Probe De-Skew and Performance
Verification Kit
1
Infiniium Series
Calibration Cable
1
Infiniium Series
80 Ω Damping Resistors (01130-81506)
1
To be used with Socketed Differential Probe Head
Automation Controllers (Optional):
Testing Type
Supported Fixtures/Accessories (Optional)
For Source DUT Testing
Unigraf DPR-100 Compact Sized DisplayPort Reference
Sink
For Sink DUT Testing
Unigraf DPT-200 Compact Sized DisplayPort Reference
Source
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Quantity
Recommended Oscilloscope
1 (each)
Infiniium Series
5
In This Book
This manual describes the tests that are performed by the DisplayPort Electrical
Performance Compliance Test Application in more detail; it contains information from (and refers to)
various DisplayPort specifications and it describes how the tests are performed.
6
•
Chapter 1, “Installing the DisplayPort Electrical Performance Compliance Test Application”
shows how to install and license the automated test application (if it was purchased separately).
•
Chapter 2, “Preparing to Take Measurements” shows how to start the DisplayPort Electrical
Performance Compliance Test Application and gives a brief overview of how it is used.
•
Chapter 3, “DisplayPort 1.2 Source Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.2 source devices.
•
Chapter 4, “DisplayPort 1.2 Sink Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.2 sink devices.
•
Chapter 5, “DisplayPort 1.2 Cable Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.2 cable devices.
•
Chapter 6, “DisplayPort 1.2 AUX Channel Tests” describes the normative and informative AUX
channel physical layer tests for compliance verification of DisplayPort 1.2 source and sink
devices.
•
Chapter 7, “DisplayPort 1.2 Inrush Tests” describes the normative and informative inrush tests for
compliance verification of DisplayPort 1.2 source and sink devices as a power consumer.
•
Chapter 8, “DisplayPort 1.2 Dual Mode Tests” describes the normative and informative Dual
Mode physical layer tests for compliance verification of DisplayPort 1.2 source devices.
•
Chapter 9, “DisplayPort 1.4 Source Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.4 source devices.
•
Chapter 10, “DisplayPort 1.4 Sink Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.4 sink devices.
•
Chapter 11, “DisplayPort 1.4 Cable Tests” describes the normative and informative tests for
compliance verification of DisplayPort 1.4 cable devices.
•
Chapter 12, “DisplayPort 1.4 AUX Channel Tests” describes the normative and informative AUX
channel physical layer tests for compliance verification of DisplayPort 1.4 source and sink
devices.
•
Chapter 13, “DisplayPort 1.4 Inrush Tests” describes the normative and informative inrush tests
for compliance verification of DisplayPort 1.4 source and sink devices as a power consumer.
•
Chapter 14, “DisplayPort 1.4 Dual Mode Tests” describes the normative and informative Dual
Mode physical layer tests for compliance verification of DisplayPort 1.4 source devices.
•
Chapter 15, “MyDP 1.0 Source Tests” describes the normative and informative tests for
compliance verification of MyDP 1.0 source devices.
•
Chapter 16, “MyDP 1.0 Sink Tests” describes the normative and informative tests for compliance
verification of MyDP 1.0 sink devices.
•
Chapter 17, “MyDP 1.0 Cable Tests” describes the normative and informative tests for
compliance verification of MyDP 1.0 cable devices.
•
Chapter 18, “MyDP 1.0 AUX Channel Tests” describes the normative and informative AUX
channel physical layer tests for compliance verification of MyDP 1.0 source and sink devices.
•
Chapter 19, “MyDP 1.0 Inrush Tests” describes the normative and informative inrush tests for
compliance verification of MyDP 1.0 source and sink devices as a power consumer.
•
Chapter 20, “SlimPort Source Tests” describes the normative and informative tests for
compliance verification of SlimPort source devices.
•
Chapter 21, “SlimPort Sink Tests” describes the normative and informative tests for compliance
verification of SlimPort sink devices.
•
Chapter 22, “SlimPort Cable Tests” describes the normative and informative tests for compliance
verification of SlimPort cable devices.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
•
Chapter 23, “SlimPort AUX Channel Tests” describes the normative and informative AUX channel
physical layer tests for compliance verification of SlimPort source and sink devices.
•
Chapter 24, “SlimPort Inrush Tests” describes the normative and informative inrush tests for
compliance verification of SlimPort source and sink devices as a power consumer.
•
Chapter 25, “Calibrating the Infiniium Oscilloscope” describes how to calibrate the oscilloscope
in preparation for running the DisplayPort automated tests.
•
Appendix A, “DisplayPort AUX Channel Cookbook for Tx Automated Test” provides a guide on
how to implement the test automation features architected in the DisplayPort Specification 1.1a
using a sink emulator such as the Keysight W2642 DPTC controller.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
7
See Also
•
•
8
The DisplayPort Electrical Performance Compliance Test Application’s Online Help, which
describes:
•
Starting the DisplayPort Compliance Test Application
•
Creating or Opening a Test Project
•
Compliance Limits
•
Setting Up the Precision Probe/Cable
•
Setting Up Switch Matrix
•
Setting Up the Test Environment
•
Selecting Tests
•
Configuring Tests
•
Connecting the Oscilloscope to the DUT
•
Running Tests
•
Automating the Application
•
Viewing Results
•
Viewing/Exporting/Printing the Report
•
Understanding the Report
•
Saving Test Projects
•
User Defined Add-Ins
•
Controlling the Application via a Remote PC
•
Using a Second Monitor
DisplayPort References:
Test Specification
Reference Documents
DisplayPort 1.4 (1.4)
VESA DisplayPort (DP) Standard Version 1.4, February 23, 2016
DisplayPort 1.2 (1.2b)
VESA DisplayPort Standard Version 1, Revision 2a, May 23, 2012
VESA DisplayPort PHY Compliance Test Specification Version 1.2b, November 26, 2012
Mobility DisplayPort (MyDP 1.0)
VESA Mobility DisplayPort (MyDP) Standard Version 1, May 21, 2012
VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, April 8, 2013
SlimPort (MyDP HBR25)
SlimPort Compliance Test Specification Version 1, February 28, 2014
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
DisplayPort Automated Testing—At A Glance
In This Book
3
6
1 Installing the DisplayPort Electrical Performance Compliance Test Application
Installing the Software
48
Installing the License Key
49
2 Preparing to Take Measurements
Calibrating the Oscilloscope
52
Starting the DisplayPort Electrical Performance Compliance Test Application
Online Help Topics
53
55
3 DisplayPort 1.2 Source Tests
Overview
58
Test Point Definition for DisplayPort 1.2 (1.2b) Source Tests 61
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests
Probing/Connection Set Up for DisplayPort 1.2 Source Tests 63
Source Eye Diagram Test
Test ID 64
Test Overview 64
62
64
Test Conditions for Eye Diagram Test
Test Setup 65
Measurement Procedure 68
PASS Condition 68
Test References 69
Expected/Observable Results 70
64
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
9
Contents
Source Total Jitter Test
Test ID 71
Test Overview 71
71
71
Test Conditions for Total Jitter Test
Test Setup 72
Measurement Procedure 75
PASS Condition 75
Test References 75
Expected/Observable Results 75
Source Non ISI Jitter Test
Test ID 76
Test Overview 76
76
Test Conditions for Non ISI Jitter Test
Test Setup 77
Measurement Procedure 80
PASS Condition 80
Test References 80
Expected/Observable Results 80
76
Source Non Pre-Emphasis Level Test
Test ID 81
Test Overview 81
81
Test Conditions for Non Pre-Emphasis Level Test
Test Setup 82
Measurement Procedure 85
PASS Condition 87
Test References 88
Expected/Observable Results 88
Source Pre-Emphasis Level Test
Test ID 89
Test Overview 89
89
Test Conditions for Pre-Emphasis Level Test
Test Setup 90
Measurement Procedure 93
PASS Condition 95
Test References 96
Expected/Observable Results 96
10
81
89
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Non Transition Vol tage Range Measurement Test
Test ID 97
Test Overview 97
97
Test Conditions for Non Transition Voltage Range Measurement Test
Test Setup 98
Measurement Procedure 101
PASS Condition 103
Test References 103
Expected/Observable Results 103
Source Peak to Peak Vol tage Test
Test ID 104
Test Overview 104
104
Test Conditions for Peak to Peak Voltage Test
Test Setup 105
Measurement Procedure 108
PASS Condition 108
Test References 108
Expected/Observable Results 108
Source Inter Pair Skew Test
Test ID 109
Test Overview 109
97
104
109
Test Conditions for Inter Pair Skew Test
Test Setup 110
Measurement Procedure 113
PASS Condition 113
Test References 114
Expected/Observable Results 114
109
Source Main Link Frequency Compliance Test
Test ID 115
Test Overview 115
115
Test Conditions for Main Link Frequency Compliance Test
Test Setup 116
Measurement Procedure 119
PASS Condition 120
Test References 120
Expected/Observable Results 120
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
115
11
Contents
Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID 121
Test Overview 121
Test Conditions for SSC Modulation Frequency Test 121
Test Setup 122
Measurement Procedure 125
PASS Condition 125
Test References 126
Expected/Observable Results 126
Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID 127
Test Overview 127
Test Conditions for SSC Modulation Deviation Test 127
Test Setup 128
Measurement Procedure 131
PASS Condition 132
Test References 132
Expected/Observable Results 132
121
127
Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID 133
Test Overview 133
Test Conditions for SSC Deviation HF Variation Test 133
Test Setup 134
Measurement Procedure 137
PASS Condition 137
Test References 138
Expected/Observable Results 138
133
Source Post-Cursor 2 Verification Test (Informative) 139
Test ID 139
Test Overview 139
Test Conditions for Post Cursor 2 Verification Test 139
Test Setup 140
Measurement Procedure 143
PASS Condition 144
Test References 144
Expected/Observable Results 144
12
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Eye Diagram Test (TP3_EQ)
Test ID 145
Test Overview 145
145
145
Test Conditions for Eye Diagram Test (TP3_EQ)
Test Setup 146
Measurement Procedure for HBR 149
Measurement Procedure for HBR2 149
PASS Condition 151
Test References 153
Expected/Observable Results 153
Source Total Jitter Test (TP3_EQ)
Test ID 154
Test Overview 154
154
154
Test Conditions for Total Jitter Test (TP3_EQ)
Test Setup 155
Measurement Procedure 158
PASS Condition 158
Test References 159
Expected/Observable Results 159
Source Deterministic Jitter Test (TP3_EQ)
Test ID 160
Test Overview 160
160
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Setup 161
Measurement Procedure 164
PASS Condition 164
Test References 165
Expected/Observable Results 165
Source Random Jitter Test (TP3_EQ)
Test ID 166
Test Overview 166
160
166
Test Conditions for Random Jitter Test (TP3_EQ)
Test Setup 167
Measurement Procedure 170
PASS Condition 170
Test References 170
Expected/Observable Results 170
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
166
13
Contents
Source AC Common Mode Test (Informative)
Test ID 171
Test Overview 171
171
Test Conditions for AC Common Mode Test (Informative)
Test Setup 172
Measurement Procedure 175
PASS Condition 175
Test References 175
Expected/Observable Results 175
Source Intra-Pair Skew Test (Informative)
Test ID 176
Test Overview 176
171
176
Test Conditions for Intra-Pair Skew Test (Informative)
Test Setup 177
Measurement Procedure 180
PASS Condition 180
Test References 180
Expected/Observable Results 181
176
4 DisplayPort 1.2 Sink Tests
Overview
184
Test Point Definition for DisplayPort 1.2 (1.2b) Sink Tests 184
Calibration of Stress Signal 185
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Sink Tests
Probing/Connection Set Up for DisplayPort 1.2 Sink Tests 188
Sink Eye Diagram Test
Test ID 189
Test Overview 189
189
Test Conditions for Eye Diagram Test
Test Setup 190
Measurement Procedure 193
PASS Condition 193
Test References 195
Expected/Observable Results 195
14
186
189
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Sink Total Jitter Test 196
Test ID 196
Test Overview 196
Test Conditions for Total Jitter Test 196
Test Setup 197
Measurement Procedure 200
PASS Condition 200
Test References 201
Expected/Observable Results 201
Sink Non-ISI Jitter Test
Test ID 202
Test Overview 202
202
Test Conditions for Non-ISI Jitter Test
Test Setup 203
Measurement Procedure 206
PASS Condition 206
Test References 207
Expected/Observable Results 207
202
5 DisplayPort 1.2 Cable Tests
Overview
210
Test Point Definition for DisplayPort 1.2 (1.2b) Cable Tests 210
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Cable Tests
Probing/Connection Set Up for DisplayPort 1.2 Cable Tests 213
Cable Eye Diagram Test
Test ID 214
Test Overview 214
214
Test Conditions for Eye Diagram Test
Test Setup 215
Measurement Procedure 218
PASS Condition 218
Test References 219
Expected/Observable Results 219
Cable Total Jitter Test
Test ID 220
Test Overview 220
212
214
220
Test Conditions for Total Jitter Test 220
Test Setup 221
Measurement Procedure 224
PASS Condition 224
Test References 224
Expected/Observable Results 224
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
15
Contents
Cable Non-ISI Jitter Test
Test ID 225
Test Overview 225
225
Test Conditions for Non-ISI Jitter Test
Test Setup 226
Measurement Procedure 229
PASS Condition 229
Test References 229
Expected/Observable Results 229
225
6 DisplayPort 1.2 AUX Channel Tests
Overview
232
Test Point for AUX Channel Tests 232
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 AUX Channel
Tests 232
Setting Up for AUX PHY and Inrush Tests
235
Probing/Connection Set Up for AUX Channel Tests
241
AUX Channel Unit Interval Test 243
Test ID 243
Test Overview 243
Test Conditions 243
Measurement Procedure 243
PASS Condition 244
Test References 244
Expected/Observable Results 244
AUX Channel Eye Test 245
Test ID 245
Test Overview 245
Test Conditions 245
Measurement Procedure 245
PASS Condition 246
Test References 246
Expected/Observable Results
246
AUX Channel Peak-to-Peak Vol tage Test
Test ID 247
Test Overview 247
Test Conditions 247
Measurement Procedure 247
PASS Condition 248
Test References 248
Expected/Observable Results 248
16
247
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
AUX Channel Eye Sensitivity Calibration Test
Test ID 249
Test Overview 249
Test Conditions 249
Measurement Procedure 249
PASS Condition 250
Test References 250
Expected/Observable Results 250
249
AUX Channel Eye Sensitivity Test 251
Test ID 251
Test Overview 251
Test Conditions 251
Measurement Procedure 251
PASS Condition 251
Test References 252
Expected/Observable Results 252
7 DisplayPort 1.2 Inrush Tests
Overview
254
Test Point for Inrush Tests 254
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Inrush Tests
Inrush Energy Power Test
Test ID 257
Test Overview 257
Test Conditions 257
255
257
Measurement Procedure 257
PASS Condition 257
Test References 258
Expected/Observable Results 258
Inrush Peak Current Test
Test ID 259
Test Overview 259
Test Conditions 259
259
Measurement Procedure 259
PASS Condition 259
Test References 260
Expected/Observable Results 260
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
17
Contents
8 DisplayPort 1.2 Dual Mode Tests
Overview
262
Test Point 262
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Dual Mode Tests
Setting Up for Dual Mode Tests
262
265
Probing/Connection Set Up for Dual Mode Tests
Dual Mode TMDS Clock Duty Cycle Test
Test ID 269
Test Overview 269
Test Conditions 269
Measurement Procedure 269
PASS Condition 269
Test References 270
Expected/Observable Results 270
268
269
Dual Mode TMDS Clock Jitter Test 271
Test ID 271
Test Overview 271
Test Conditions 271
Measurement Procedure 271
PASS Condition 271
Test References 272
Expected/Observable Results 272
Dual Mode Eye Diagram Test 273
Test ID 273
Test Overview 273
Test Conditions 273
Measurement Procedure 273
PASS Condition 274
Test References 275
Expected/Observable Results 275
Dual Mode Data Jitter Test
Test ID 276
Test Overview 276
Test Conditions 276
276
Measurement Procedure 276
PASS Condition 277
Test References 277
Expected/Observable Results 277
18
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Dual Mode Data Peak-Peak Differential Vol tage Test
Test ID 278
Test Overview 278
Test Conditions 278
Measurement Procedure 278
PASS Condition 279
Test References 279
Expected/Observable Results 279
Dual Mode Inter-Pair Skew Test
Test ID 280
Test Overview 280
Test Conditions 280
Measurement Procedure 280
PASS Condition 281
Test References 281
Expected/Observable Results
Dual Mode Intra-Pair Skew Test
Test ID 282
Test Overview 282
Test Conditions 282
Measurement Procedure 282
PASS Condition 283
Test References 283
Expected/Observable Results
278
280
281
282
283
9 DisplayPort 1.4 Source Tests
Overview
286
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests
Probing/Connection Set Up for DisplayPort 1.4 Source Tests 293
Source Eye Diagram Test
Test ID 294
Test Overview 294
291
294
Test Conditions for Eye Diagram Test
Test Setup 295
Measurement Procedure 298
PASS Condition 298
Test References 299
Expected/Observable Results 300
294
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
19
Contents
Source Total Jitter Test
Test ID 301
Test Overview 301
301
Test Conditions for Total Jitter Test 301
Test Setup 302
Measurement Procedure 305
PASS Condition 305
Test References 305
Expected/Observable Results 305
Source Non-ISI Jitter Test
Test ID 306
Test Overview 306
306
Test Conditions for Non-ISI Jitter Test
Test Setup 307
Measurement Procedure 310
PASS Condition 310
Test References 310
Expected/Observable Results 310
306
Source Non Pre-Emphasis Level Test
Test ID 311
Test Overview 311
311
Test Conditions for Non Pre-Emphasis Level Test
Test Setup 312
Measurement Procedure 315
PASS Condition 317
Test References 318
Expected/Observable Results 318
Source Pre-Emphasis Level Test
Test ID 319
Test Overview 319
319
Test Conditions for Pre-Emphasis Level Test
Test Setup 320
Measurement Procedure 323
PASS Condition 325
Test References 326
Expected/Observable Results 326
20
311
319
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Non Transition Vol tage Range Measurement Test
Test ID 327
Test Overview 327
327
Test Conditions for Non-Transition Voltage Range Measurement Test
Test Setup 328
Measurement Procedure 331
PASS Condition 333
Test References 333
Expected/Observable Results 333
Source Peak to Peak Vol tage Test
Test ID 334
Test Overview 334
334
Test Conditions for Peak to Peak Voltage Test
Test Setup 335
Measurement Procedure 338
PASS Condition 338
Test References 338
Expected/Observable Results 338
Source Inter-Pair Skew Test
Test ID 339
Test Overview 339
327
334
339
Test Conditions for Inter Pair Skew Test
Test Setup 340
Measurement Procedure 343
PASS Condition 343
Test References 344
Expected/Observable Results 344
339
Source Main Link Frequency Compliance Test
Test ID 345
Test Overview 345
345
Test Conditions for Main Link Frequency Compliance Test
Test Setup 346
Measurement Procedure 349
PASS Condition 350
Test References 350
Expected/Observable Results 350
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
345
21
Contents
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID 351
Test Overview 351
Test Conditions for SSC Modulation Frequency Test 351
Test Setup 352
Measurement Procedure 355
PASS Condition 355
Test References 356
Expected/Observable Results 356
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID 357
Test Overview 357
Test Conditions for SSC Modulation Deviation Test 357
Test Setup 358
Measurement Procedure 361
PASS Condition 362
Test References 362
Expected/Observable Results 362
351
357
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID 363
Test Overview 363
Test Conditions for SSC Deviation HF Variation Test (Informative) 363
Test Setup 364
Measurement Procedure 367
PASS Condition 367
Test References 368
Expected/Observable Results 368
Source Eye Diagram Test (TP3_EQ)
Test ID 369
Test Overview 369
363
369
Test Conditions for Eye Diagram Test (TP3_EQ) 369
Test Setup 370
Measurement Procedure for HBR 373
Measurement Procedure for HBR2 and HBR3 373
PASS Condition 375
Test References 377
Expected/Observable Results 378
22
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Total Jitter Test (TP3_EQ)
Test ID 379
Test Overview 379
379
379
Test Conditions for Total Jitter Test (TP3_EQ)
Test Setup 380
Measurement Procedure 383
PASS Condition 383
Test References 384
Expected/Observable Results 384
Source Non ISI Jitter Test (TP3_EQ)
Test ID 385
Test Overview 385
385
Test Conditions for Non ISI Jitter Test (TP3_EQ)
Test Setup 386
Measurement Procedure 389
PASS Condition 389
Test References 390
Expected/Observable Results 390
Source Deterministic Jitter Test (TP3_EQ)
Test ID 391
Test Overview 391
385
391
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Setup 392
Measurement Procedure 395
PASS Condition 395
Test References 396
Expected/Observable Results 396
Source Random Jitter Test (TP3_EQ)
Test ID 397
Test Overview 397
391
397
Test Conditions for Random Jitter Test (TP3_EQ)
Test Setup 398
Measurement Procedure 401
PASS Condition 401
Test References 401
Expected/Observable Results 401
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
397
23
Contents
Source AC Common Mode Test (Informative)
Test ID 402
Test Overview 402
402
Test Conditions for AC Common Mode Test (Informative)
Test Setup 403
Measurement Procedure 406
PASS Condition 406
Test References 406
Expected/Observable Results 406
Source Intra-Pair Skew Test (Informative)
Test ID 407
Test Overview 407
402
407
Test Conditions for Intra-Pair Skew Test (Informative)
Test Setup 408
Measurement Procedure 411
PASS Condition 411
Test References 411
Expected/Observable Results 412
407
10 DisplayPort 1.4 Sink Tests
Overview
414
Test Point Definition for DisplayPort 1.4 Sink Tests 414
Calibration of Stress Signal 415
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Sink Tests
Probing/Connection Set Up for DisplayPort 1.4 Sink Tests 418
Sink Eye Diagram Test
Test ID 419
Test Overview 419
419
Test Conditions for Eye Diagram Test
Test Setup 420
Measurement Procedure 423
PASS Condition 423
Test References 425
Expected/Observable Results 426
24
416
419
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Sink Total Jitter Test 427
Test ID 427
Test Overview 427
Test Conditions for Total Jitter Test 427
Test Setup 428
Measurement Procedure 431
PASS Condition 431
Test References 432
Expected/Observable Results 432
Sink Non-ISI Jitter Test
Test ID 433
Test Overview 433
433
Test Conditions for Non-ISI Jitter Test
Test Setup 434
Measurement Procedure 437
PASS Condition 437
Test References 438
Expected/Observable Results 438
433
11 DisplayPort 1.4 Cable Tests
Overview
440
Test Point Definition for DisplayPort 1.4 Cable Tests 440
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Cable Tests
Probing/Connection Set Up for DisplayPort 1.4 Cable Tests 443
Cable Eye Diagram Test
Test ID 444
Test Overview 444
444
Test Conditions for Eye Diagram Test
Test Setup 445
Measurement Procedure 448
PASS Condition 448
Test References 449
Expected/Observable Results 449
Cable Total Jitter Test
Test ID 450
Test Overview 450
442
444
450
Test Conditions for Total Jitter Test 450
Test Setup 451
Measurement Procedure 454
PASS Condition 454
Test References 454
Expected/Observable Results 454
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
25
Contents
Cable Non-ISI Jitter Test
Test ID 455
Test Overview 455
455
Test Conditions for Non-ISI Jitter Test
Test Setup 456
Measurement Procedure 459
PASS Condition 459
Test References 459
Expected/Observable Results 459
455
12 DisplayPort 1.4 AUX Channel Tests
Overview
462
Test Point for AUX Channel Tests 462
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 AUX Channel
Tests 462
Setting Up for AUX PHY and Inrush Tests
465
Probing/Connection Set Up for AUX Channel Tests
471
AUX Channel Unit Interval Test 473
Test ID 473
Test Overview 473
Test Conditions 473
Measurement Procedure 473
PASS Condition 474
Test References 474
Expected/Observable Results 474
AUX Channel Eye Test 475
Test ID 475
Test Overview 475
Test Conditions 475
Measurement Procedure 475
PASS Condition 476
Test References 476
Expected/Observable Results
476
AUX Channel Peak-to-Peak Vol tage Test
Test ID 477
Test Overview 477
Test Conditions 477
Measurement Procedure 477
PASS Condition 478
Test References 478
Expected/Observable Results 478
26
477
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
AUX Channel Eye Sensitivity Calibration Test
Test ID 479
Test Overview 479
Test Conditions 479
Measurement Procedure 479
PASS Condition 480
Test References 480
Expected/Observable Results 480
479
AUX Channel Eye Sensitivity Test 481
Test ID 481
Test Overview 481
Test Conditions 481
Measurement Procedure 481
PASS Condition 481
Test References 482
Expected/Observable Results 482
13 DisplayPort 1.4 Inrush Tests
Overview
484
Test Point 484
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Inrush Tests
Inrush Energy Power Test
Test ID 487
Test Overview 487
Test Conditions 487
485
487
Measurement Procedure 487
PASS Condition 487
Test References 488
Expected/Observable Results 488
Inrush Peak Current Test
Test ID 489
Test Overview 489
Test Conditions 489
489
Measurement Procedure 489
PASS Condition 489
Test References 490
Expected/Observable Results 490
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
27
Contents
14 DisplayPort 1.4 Dual Mode Tests
Overview
492
Test Point 492
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Dual Mode Tests
Setting Up for Dual Mode Tests
493
496
Probing/Connection Set Up for Dual Mode Tests
Dual Mode TMDS Clock Duty Cycle Test
Test ID 500
Test Overview 500
Test Conditions 500
Measurement Procedure 500
PASS Condition 500
Test References 501
Expected/Observable Results 501
499
500
Dual Mode TMDS Clock Jitter Test 502
Test ID 502
Test Overview 502
Test Conditions 502
Measurement Procedure 502
PASS Condition 502
Test References 503
Expected/Observable Results 503
Dual Mode Eye Diagram Test 504
Test ID 504
Test Overview 504
Test Conditions 504
Measurement Procedure 504
PASS Condition 505
Test References 506
Expected/Observable Results 506
Dual Mode Data Jitter Test
Test ID 507
Test Overview 507
Test Conditions 507
507
Measurement Procedure 507
PASS Condition 508
Test References 508
Expected/Observable Results 508
28
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Dual Mode Data Peak-Peak Differential Vol tage Test
Test ID 509
Test Overview 509
Test Conditions 509
Measurement Procedure 509
PASS Condition 510
Test References 510
Expected/Observable Results 510
Dual Mode Inter-Pair Skew Test
Test ID 511
Test Overview 511
Test Conditions 511
Measurement Procedure 511
PASS Condition 512
Test References 512
Expected/Observable Results
Dual Mode Intra-Pair Skew Test
Test ID 513
Test Overview 513
Test Conditions 513
Measurement Procedure 513
PASS Condition 514
Test References 514
Expected/Observable Results
509
511
512
513
514
15 MyDP 1.0 Source Tests
Overview
516
Test Point Definition for MyDP 1.0 Source Tests 518
Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source
Tests 519
Probing/Connection Set Up for MyDP 1.0 Source Tests 521
Source Eye Diagram Test
Test ID 522
Test Overview 522
522
Test Conditions for Eye Diagram Test
Test Setup 523
Measurement Procedure 526
PASS Condition 526
Test References 527
Expected/Observable Results 528
522
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
29
Contents
Source Total Jitter Test
Test ID 529
Test Overview 529
529
Test Conditions for Total Jitter Test 529
Test Setup 530
Measurement Procedure 533
PASS Condition 533
Test References 533
Expected/Observable Results 533
Source Non-ISI Jitter Test
Test ID 534
Test Overview 534
534
Test Conditions for Non-ISI Jitter Test
Test Setup 535
Measurement Procedure 538
PASS Condition 538
Test References 538
Expected/Observable Results 538
534
Source Non Pre-Emphasis Level Test
Test ID 539
Test Overview 539
539
539
Test Conditions for Non Pre-Emphasis Level Test
Test Setup 540
Measurement Procedure 543
PASS Condition 545
Test References 546
Expected/Observable Results 546
Source Pre-Emphasis Level Differential Tests
Test ID 547
Test Overview 547
Test Conditions for Pre-Emphasis Level Test
Test Setup 548
Measurement Procedure 551
PASS Condition 553
Test References 554
Expected/Observable Results 554
30
547
547
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Non Transition Vol tage Range Measurement Test
Test ID 555
Test Overview 555
555
Test Conditions for Non Transition Voltage Range Measurement Test
Test Setup 556
Measurement Procedure 559
PASS Condition 561
Test References 561
Expected/Observable Results 561
Source Peak to Peak Vol tage Test
Test ID 562
Test Overview 562
555
562
Test Conditions for Peak to Peak Voltage Test
Test Setup 563
Measurement Procedure 566
PASS Condition 566
Test References 566
Expected/Observable Results 566
Source Main Link Frequency Compliance Test
Test ID 567
Test Overview 567
562
567
Test Conditions for Main Link Frequency Compliance Test
Test Setup 568
Measurement Procedure 571
PASS Condition 572
Test References 572
Expected/Observable Results 572
567
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID 573
Test Overview 573
Test Conditions for SSC Modulation Frequency Test 573
Test Setup 574
Measurement Procedure 577
PASS Condition 577
Test References 578
Expected/Observable Results 578
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
573
31
Contents
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID 579
Test Overview 579
Test Conditions for SSC Modulation Deviation Test 579
Test Setup 580
Measurement Procedure 583
PASS Condition 584
Test References 584
Expected/Observable Results 584
579
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID 585
Test Overview 585
Test Conditions for SSC Deviation HF Variation Test (Informative) 585
Test Setup 586
Measurement Procedure 589
PASS Condition 589
Test References 590
Expected/Observable Results 590
Post-Cursor 2 Verification Test (Informative)
Test ID 591
Test Overview 591
591
Test Conditions for Post-Cursor 2 Verification Test (Informative)
Test Setup 592
Measurement Procedure 595
PASS Condition 596
Test References 596
Expected/Observable Results 596
Eye Diagram Test (TP3_EQ)
Test ID 597
Test Overview 597
591
597
Test Conditions for Eye Diagram Test (TP3_EQ)
Test Setup 598
Measurement Procedure for HBR 601
Measurement Procedure for HBR2 601
PASS Condition 603
Test References 605
Expected/Observable Results 605
32
585
597
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Total Jitter Test (TP3_EQ)
Test ID 606
Test Overview 606
606
Test Conditions for Total Jitter Test (TP3_EQ)
Test Setup 607
Measurement Procedure 610
PASS Condition 610
Test References 611
Expected/Observable Results 611
Deterministic Jitter Test (TP3_EQ)
Test ID 612
Test Overview 612
606
612
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Setup 613
Measurement Procedure 616
PASS Condition 616
Test References 617
Expected/Observable Results 617
Random Jitter Test (TP3_EQ)
Test ID 618
Test Overview 618
612
618
Test Conditions for Random Jitter Test (TP3_EQ)
Test Setup 619
Measurement Procedure 622
PASS Condition 622
Test References 622
Expected/Observable Results 622
AC Common Mode Test (Informative)
Test ID 623
Test Overview 623
618
623
Test Conditions for AC Common Mode Test (Informative)
Test Setup 624
Measurement Procedure 627
PASS Condition 627
Test References 627
Expected/Observable Results 627
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
623
33
Contents
Intra-Pair Skew Test (Informative)
Test ID 628
Test Overview 628
628
Test Conditions for Intra-Pair Skew Test (Informative)
Test Setup 629
Measurement Procedure 632
PASS Condition 632
Test References 633
Expected/Observable Results 633
628
16 MyDP 1.0 Sink Tests
Overview
636
Test Point Definition for DisplayPort MyDP 1.0 Sink Tests 636
Calibration of Stress Signal 637
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Sink Tests
Probing/Connection Set Up for MyDP 1.0 Sink Tests 639
Sink Eye Diagram Test
Test ID 640
Test Overview 640
638
640
Test Conditions for Eye Diagram Test
Test Setup 641
Measurement Procedure 644
PASS Condition 644
Test References 646
Expected/Observable Results 646
640
Sink Total Jitter Test 647
Test ID 647
Test Overview 647
Test Conditions for Total Jitter Test 647
Test Setup 648
Measurement Procedure 651
PASS Condition 651
Test References 652
Expected/Observable Results 652
34
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Sink Non-ISI Jitter Tests
Test ID 653
Test Overview 653
653
Test Conditions for Non-ISI Jitter Test
Test Setup 654
Measurement Procedure 657
PASS Condition 657
Test References 658
Expected/Observable Results 658
653
17 MyDP 1.0 Cable Tests
Overview
660
Test Point Definition for MyDP 1.0 Cable Tests 660
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Cable Tests
Probing/Connection Set Up for MyDP 1.0 Cable Tests 663
Cable Eye Diagram Test
Test ID 664
Test Overview 664
664
Test Conditions for Eye Diagram Test
Test Setup 665
Measurement Procedure 668
PASS Condition 668
Test References 669
Expected/Observable Results 669
Cable Total Jitter Test
Test ID 670
Test Overview 670
662
664
670
Test Conditions for Total Jitter Test 670
Test Setup 671
Measurement Procedure 674
PASS Condition 674
Test References 674
Expected/Observable Results 674
Cable Non-ISI Jitter Test
Test ID 675
Test Overview 675
675
Test Conditions for Non-ISI Jitter Test
Test Setup 676
Measurement Procedure 679
PPASS Condition 679
Test References 679
Expected/Observable Results 679
675
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
35
Contents
18 MyDP 1.0 AUX Channel Tests
Overview
682
Test Point for MyDP 1.0 AUX Channel Tests 682
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 AUX Channel Tests
Setting Up for AUX PHY and Inrush Tests
682
685
Probing/Connection Set Up for AUX Channel Tests
691
AUX Channel Unit Interval Test 693
Test ID 693
Test Overview 693
Test Conditions 693
Measurement Procedure 693
PASS Condition 694
Test References 694
Expected/Observable Results 694
AUX Channel Eye Test 695
Test ID 695
Test Overview 695
Test Conditions 695
Measurement Procedure 695
PASS Condition 696
Test References 696
Expected/Observable Results
696
AUX Channel Peak-to-Peak Vol tage Test
Test ID 697
Test Overview 697
Test Conditions 697
Measurement Procedure 697
PASS Condition 698
Test References 698
Expected/Observable Results 698
697
AUX Channel Eye Sensitivity Calibration Test
Test ID 699
Test Overview 699
Test Conditions 699
Measurement Procedure 699
PASS Condition 700
Test References 700
Expected/Observable Results 700
36
699
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
AUX Channel Eye Sensitivity Test 701
Test ID 701
Test Overview 701
Test Conditions 701
Measurement Procedure 701
PASS Condition 701
Test References 702
Expected/Observable Results 702
19 MyDP 1.0 Inrush Tests
Overview
704
Test Point for MyDP 1.0 Inrush Tests 704
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Inrush Tests
Inrush Energy Power Test
Test ID 707
Test Overview 707
Test Conditions 707
705
707
Measurement Procedure 707
PASS Condition 707
Test References 707
Expected/Observable Results 708
Inrush Peak Current Test
Test ID 709
Test Overview 709
Test Conditions 709
709
Measurement Procedure 709
PASS Condition 709
Test References 709
Expected/Observable Results 710
20 SlimPort Source Tests
Overview
712
Test Point Definition for SlimPort Source Tests 715
Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests
Probing/Connection Set Up for SlimPort Source Tests 718
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
716
37
Contents
Source Eye Diagram Test
Test ID 719
Test Overview 719
719
Test Conditions for Eye Diagram Test
Test Setup 720
Measurement Procedure 723
PASS Condition 723
Test References 724
Expected/Observable Results 725
Source Total Jitter Test
Test ID 726
Test Overview 726
719
726
Test Conditions for Total Jitter Test 726
Test Setup 727
Measurement Procedure 730
PASS Condition 730
Test References 730
Expected/Observable Results 730
Source Non-ISI Jitter Test
Test ID 731
Test Overview 731
731
Test Conditions for Non-ISI Jitter Test
Test Setup 732
Measurement Procedure 735
PASS Condition 735
Test References 735
Expected/Observable Results 735
731
Source Non Pre-Emphasis Level Test
Test ID 736
Test Overview 736
736
Test Conditions for Non Pre-Emphasis Level Test
Test Setup 737
Measurement Procedure 740
PASS Condition 742
Test References 743
Expected/Observable Results 743
38
736
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Source Pre-Emphasis Level Test
Test ID 744
Test Overview 744
744
Test Conditions for Pre-Emphasis Level Test
Test Setup 745
Measurement Procedure 748
PASS Condition 750
Test References 751
Expected/Observable Results 751
744
Source Non Transition Vol tage Range Measurement Test
Test ID 752
Test Overview 752
752
Test Conditions for Non Transition Voltage Range Measurement Test
Test Setup 753
Measurement Procedure 756
PASS Condition 758
Test References 758
Expected/Observable Results 758
Source Peak to Peak Vol tage Test
Test ID 759
Test Overview 759
752
759
Test Conditions for Peak to Peak Voltage Test
Test Setup 760
Measurement Procedure 763
PASS Condition 763
Test References 763
Expected/Observable Results 763
Source Main Link Frequency Compliance Test
Test ID 764
Test Overview 764
759
764
Test Conditions for Main Link Frequency Compliance Test
Test Setup 765
Measurement Procedure 768
PASS Condition 769
Test References 769
Expected/Observable Results 769
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
764
39
Contents
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID 770
Test Overview 770
Test Conditions for SSC Modulation Frequency Test 770
Test Setup 771
Measurement Procedure 774
PASS Condition 774
Test References 775
Expected/Observable Results 775
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID 776
Test Overview 776
Test Conditions for SSC Modulation Deviation Test 776
Test Setup 777
Measurement Procedure 780
PASS Condition 781
Test References 781
Expected/Observable Results 781
770
776
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID 782
Test Overview 782
Test Conditions for SSC Deviation HF Variation Test (Informative) 782
Test Setup 783
Measurement Procedure 786
PASS Condition 786
Test References 787
Expected/Observable Results 787
Post-Cursor 2 Verification Test (Informative)
Test ID 788
Test Overview 788
Test Conditions for Post-Cursor 2 Verification Test
Test Setup 789
Measurement Procedure 792
PASS Condition 793
Test References 793
Expected/Observable Results 793
40
782
788
788
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Eye Diagram Test (TP3_EQ)
Test ID 794
Test Overview 794
794
Test Conditions for Eye Diagram Test (TP3_EQ) 794
Test Setup 795
Measurement Procedure for HBR and HBR25 798
Measurement Procedure for HBR2 798
PASS Condition 800
Test References 802
Expected/Observable Results 802
Total Jitter Test (TP3_EQ)
Test ID 803
Test Overview 803
803
Test Conditions for Total Jitter Test (TP3_EQ)
Test Setup 804
Measurement Procedure 807
PASS Condition 807
Test References 808
Expected/Observable Results 808
Deterministic Jitter Test (TP3_EQ)
Test ID 809
Test Overview 809
803
809
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Setup 810
Measurement Procedure 813
PASS Condition 813
Test References 814
Expected/Observable Results 814
Random Jitter Test (TP3_EQ)
Test ID 815
Test Overview 815
809
815
Test Conditions for Random Jitter Test (TP3_EQ)
Test Setup 816
Measurement Procedure 819
PASS Condition 819
Test References 819
Expected/Observable Results 819
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
815
41
Contents
AC Common Mode Test (Informative)
Test ID 820
Test Overview 820
820
Test Conditions for AC Common Mode Test (Informative)
Test Setup 821
Measurement Procedure 824
PASS Condition 824
Test References 824
Expected/Observable Results 824
Intra-Pair Skew Test (Informative)
Test ID 825
Test Overview 825
820
825
Test Conditions for Intra-Pair Skew Test (Informative)
Test Setup 826
Measurement Procedure 829
PASS Condition 829
Test References 830
Expected/Observable Results 830
825
21 SlimPort Sink Tests
Overview
832
Test Point Definition for SlimPort Sink Tests 832
Calibration of Stress Signal 833
Setting Up the DisplayPort Compliance Test Application for SlimPort Sink Tests
Probing/Connection Set Up for SlimPort Sink Tests 835
Sink Eye Diagram Test
Test ID 836
Test Overview 836
836
Test Conditions for Eye Diagram Test
Test Setup 837
Measurement Procedure 840
PASS Condition 840
Test References 842
Expected/Observable Results 842
42
834
836
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
Sink Total Jitter Test 843
Test ID 843
Test Overview 843
Test Conditions for Total Jitter Test 843
Test Setup 844
Measurement Procedure 847
PASS Condition 847
Test References 848
Expected/Observable Results 848
Sink Non-ISI Jitter Test
Test ID 849
Test Overview 849
849
Test Conditions for Non-ISI Jitter Test
Test Setup 850
Measurement Procedure 853
PASS Condition 853
Test References 854
Expected/Observable Results 854
849
22 SlimPort Cable Tests
Overview
856
Test Point Definition for SlimPort Cable Tests 856
Setting Up the DisplayPort Compliance Test Application for SlimPort Cable Tests
Probing/Connection Set Up for SlimPort Cable Tests 859
Cable Eye Diagram Test
Test ID 860
Test Overview 860
860
Test Conditions for Eye Diagram Test
Test Setup 861
Measurement Procedure: 864
PASS Condition 864
Test References 865
Expected/Observable Results 865
Cable Total Jitter Test
Test ID 866
Test Overview 866
858
860
866
Test Conditions for Total Jitter Test 866
Test Setup 867
Measurement Procedure 870
PASS Condition 870
Test References 870
Expected/Observable Results 870
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
43
Contents
Cable Non-ISI Jitter Test
Test ID 871
Test Overview 871
871
Test Conditions for Non-ISI Jitter Test
Test Setup 872
Measurement Procedure 875
PASS Condition 875
Test References 875
Expected/Observable Results 875
871
23 SlimPort AUX Channel Tests
Overview
878
Test Point for SlimPort AUX Channel Tests 878
Setting Up the DisplayPort Compliance Test Application for SlimPort AUX Channel Tests
Setting Up for AUX PHY and Inrush Tests
878
881
Probing/Connection Set Up for AUX Channel Tests
887
AUX Channel Unit Interval Test 889
Test ID 889
Test Overview 889
Test Conditions 889
Measurement Procedure 889
PASS Condition 890
Test References 890
Expected/Observable Results 890
AUX Channel Eye Test 891
Test ID 891
Test Overview 891
Test Conditions 891
Measurement Procedure 891
PASS Condition 892
Test References 892
Expected/Observable Results
892
AUX Channel Peak-to-Peak Vol tage Test
Test ID 893
Test Overview 893
Test Conditions 893
Measurement Procedure 893
PASS Condition 894
Test References 894
Expected/Observable Results 894
44
893
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Contents
AUX Channel Eye Sensitivity Calibration Test
Test ID 895
Test Overview 895
Test Conditions 895
Measurement Procedure 895
PASS Condition 896
Test References 896
Expected/Observable Results 896
895
AUX Channel Eye Sensitivity Test 897
Test ID 897
Test Overview 897
Test Conditions 897
Measurement Procedure 897
PASS Condition 897
Test References 898
Expected/Observable Results 898
24 SlimPort Inrush Tests
Overview
900
Test Point 900
Setting Up the DisplayPort Compliance Test Application for SlimPort Inrush Tests
Inrush Energy Power Test
Test ID 903
Test Overview 903
Test Conditions 903
901
903
Measurement Procedure 903
PASS Condition 903
Test References 904
Expected/Observable Results 904
Inrush Peak Current Test
Test ID 905
Test Overview 905
Test Conditions 905
905
Measurement Procedure 905
PASS Condition 905
Test References 906
Expected/Observable Results 906
25 Calibrating the Infiniium Oscilloscope
To Run the Sel f Calibration
908
Internal or Sel f Calibration
909
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
45
Contents
Probe Calibration and De-skew
913
Differential SMA Probe Head Attenuation/Offset Calibration 913
Differential SMA Probe Head Skew Calibration 917
Differential Socketed Probe Head Atten/Offset Calibration 917
Differential Socketed Probe Head Skew Calibration 921
A DisplayPort AUX Channel Cookbook for Tx Automated Test
AUX Channel and Hot Plug Detect (HPD)
DPTC Controller
924
925
Automated Test Sequence
OPTION 1 926
OPTION 2 930
926
Index
46
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
1
Installing the DisplayPort
Electrical Performance
Compliance Test Application
Installing the Software / 48
Installing the License Key / 49
If you purchased the U7232D DisplayPort Electrical Performance Compliance Test Application, you
need to install the software and license key.
1
Installing the DisplayPort Electrical Performance Compliance Test Application
Installing the Software
1
Make sure you have the minimum version of Infiniium oscilloscope software (see the U7232D test
application release notes) by choosing Help>About Infiniium... from the main menu.
2
To obtain the DisplayPort Electrical Performance Compliance Test Application, go to Keysight
website: http://www.keysight.com/find/scope-apps-sw.
Figure 1
3
48
Keysight website for software Downloads
Search the list on this web page for the link to the U7232D DisplayPort Electrical Performance
Compliance Test Application. Click the appropriate link and follow the instructions to download
and install the application.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Installing the DisplayPort Electrical Performance Compliance Test Application
1
Installing the License Key
1
Request a license code from Keysight by following the instructions on the Entitlement Certificate.
You will need the oscilloscope’s “Option ID Number”, which you can find in the Help>About
Infiniium... dialog box.
2
After you receive your license code from Keysight, choose Utilities>Install Legacy Licenses....
3
In the Install Option License dialog, enter your license code and click Install License.
4
Click OK in the dialog that tells you to restart the Infiniium oscilloscope application software to
complete the license installation.
5
Click Close to close the Install Option License dialog.
6
Choose File>Exit.
7
Restart the Infiniium oscilloscope application to complete the license installation.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
49
1
50
Installing the DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
2
Preparing to Take
Measurements
Calibrating the Oscilloscope / 52
Starting the DisplayPort Electrical Performance Compliance Test Application / 53
Online Help Topics / 55
Before running the DisplayPort automated tests, you must acquire the appropriate test fixtures, and
you should calibrate the oscilloscope and probe. After the oscilloscope and probe have been
calibrated, you are ready to start the DisplayPort Electrical Performance Compliance Test
Application and perform the measurements.
2
Preparing to Take Measurements
Calibrating the Oscilloscope
If you haven’t already calibrated the oscilloscope and probe, see Chapter 25, “Calibrating the Infiniium
Oscilloscope.
52
NOTE
If the ambient temperature changes more than 5 degrees Celsius from the calibration temperature,
internal calibration should be performed again. The delta between the calibration temperature and
the present operating temperature is shown in the Utilities>Calibration menu.
NOTE
If you switch cables between channels or other oscilloscopes, it is necessary to perform cable and
probe calibration again. Keysight recommends that, once calibration is performed, you label the
cables with the channel on which they were calibrated.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Preparing to Take Measurements
2
Starting the DisplayPort Electrical Performance Compliance Test Application
1
From the Infiniium oscilloscope’s main menu, choose Analyze>Automated Test Apps>U7232D
DisplayPort Test App.
Figure 2
The DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
53
2
Preparing to Take Measurements
NOTE
If DisplayPort Test does not appear in the Automated Test Apps menu, the DisplayPort
Electrical Performance Compliance Test Application has not been installed (see Chapter 1,
“Installing the DisplayPort Electrical Performance Compliance Test Application).
Figure 2 shows the DisplayPort Electrical Performance Compliance Test Application main window.
The task flow pane, and the tabs in the main pane, show the steps you take in running the automated
tests:
54
Tab
Description
Set Up
Lets you select your setup options. Allows you to setup by device type, test type, fixture type and connection type.
Select Tests
Lets you select the tests you want to run. The tests are organized hierarchically, so you can select all tests in a
group. After tests are run, status indicators show which tests have passed, failed, or not been run, and there are
indicators for the test groups.
Configure
Lets you enter information about the device being tested and configure test parameters (like memory depth). This
information appears in the HTML report.
Connect
Shows you how to connect the oscilloscope to the device under test for the tests to be run.
Run Tests
Starts the automated tests. If the connections to the device under test need to be changed while multiple tests are
running, the tests pause, show you how to change the connection, and wait for you to confirm that the connections
have been changed before continuing.
Automation
Enables construction of automated script of commands that drive the functionality of the test application.
Results
Contains more detailed information about the tests that have been run. You can change the thresholds at which
marginal or critical warnings appear.
HTML Report
Shows a compliance test report that can be printed.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Preparing to Take Measurements
2
Online Help Topics
For information on using the DisplayPort Electrical Performance Compliance Test Application, see
the Online Help (which you can access by choosing Help>Contents... from the application’s main
menu).
The DisplayPort Electrical Performance Compliance Test Application’s Online Help describes:
•
Starting the DisplayPort Compliance Test Application
• To view/minimize the task flow pane
• To view/hide the toolbar
•
Creating or Opening a Test Project
•
Compliance Limits
• To set load preferences
• To Activate/Refresh Limit Set
• To Create/Edit Limit Set
•
Setting Up the Precision Probe/Cable
•
Setting Up Switch Matrix
•
Setting Up the Test Environment
• Test Setup
• DisplayPort Test Controller
•
Selecting Tests
•
Configuring Tests
•
Connecting the Oscilloscope to the DUT
•
Running Tests
• To select the Store Mode
• To run multiple times
• To send email on pauses or stops
• To pause or stop on events
• To specify the event
• To set the display preferences
• To set the run preferences
•
Automating the Application
•
Viewing Results
• To delete trials from the results
• To show reference images and flash mask hits
• To change margin thresholds
• To change the test display order
• To set trial display preferences
•
Viewing/Exporting/Printing the Report
• To export the report
• To print the report
• To set HTML Report preferences
•
Understanding the Report
•
Saving Test Projects
• To set AutoRecovery preferences
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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2
Preparing to Take Measurements
•
User Defined Add-Ins
• To install an add-in
• To remove an add-in
•
Controlling the Application via a Remote PC
• To check for the App Remote license
• To identify the remote interface version
• To enable the remote interface
• To enable remote interface hints
•
56
Using a Second Monitor
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
3
DisplayPort 1.2 Source Tests
Overview / 58
Source Eye Diagram Test / 64
Source Total Jitter Test / 71
Source Non ISI Jitter Test / 76
Source Non Pre-Emphasis Level Test / 81
Source Pre-Emphasis Level Test / 89
Source Non Transition Voltage Range Measurement Test / 97
Source Peak to Peak Voltage Test / 104
Source Inter Pair Skew Test / 109
Source Main Link Frequency Compliance Test / 115
Spread Spectrum Clocking (SSC) Modulation Frequency Test / 121
Spread Spectrum Clocking (SSC) Modulation Deviation Test / 127
Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative) / 133
Source Post-Cursor 2 Verification Test (Informative) / 139
Source Eye Diagram Test (TP3_EQ) / 145
Source Total Jitter Test (TP3_EQ) / 154
Source Deterministic Jitter Test (TP3_EQ) / 160
Source Random Jitter Test (TP3_EQ) / 166
Source AC Common Mode Test (Informative) / 171
Source Intra-Pair Skew Test (Informative) / 176
This section provides the guidelines for source eye diagram differential tests using a Keysight 13 GHz
or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort
Electrical Performance Compliance Test Application.
3
DisplayPort 1.2 Source Tests
Overview
This section describes the normative and informative main link physical layer tests for compliance
verification of DisplayPort 1.2 source, sink and cable devices.
Test Point Definition for DisplayPort 1.2 (1.2b) Tests
Five different test points are identified for the physical layer measurement. See Figure 3
Figure 3
Test Points in a DisplayPort InterConnect System
Table 1 defines the Test Points used for various DisplayPort 1.2 Tests:
Table 1
Test Points for DisplayPort Tests
Test Point
Description
TP1
At the pins of the Transmitter Device
TP2
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Source device
TP3
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Sink device
TP3_EQ
At TP3, when a defined cable model with equalizer is applied. There are two defined
cable models:
• Worst Cable Model as defined in VESA DisplayPort 1.2a Standard,
• Zero length, zero loss cable. The equalizer is also defined in VESA DisplayPort 1.2a
Standard
TP4
At the pins of a receiving device
Cable Models
The two cable models defined in VESA DisplayPort 1.2a Standard are:
1
Worst Case Cable Model—To achieve the TP3_EQ signal with the worst case cable model:
•
Acquire the signal at TP2.
•
Embed the TP2 signal with a “worst case” HBR cable model using an InfiniiSim Waveform
Transformation Toolset software to emulate the insertion loss as defined in Figure 4-10 of the
VESA DisplayPort 1.2a Standard.
• For the DisplayPort Compliance Test Application, the “CIC_rev0p6.s4p” cable model transfer
function is used.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
2
Zero Length Cable Model—To achieve the TP3_EQ signal with the zero length cable model:
•
Acquire the signal at TP2.
•
No cable model is embedded for the Zero Length cable model.
•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
3
Equalization
When equalization is required, use the CTLE (Continuous Time Linear Equalization) transfer function,
as given in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a Standard.
For main link, use the CTLE model with the following transfer function for HBR (2.7 Gbps):
Figure 4
Transfer Function of the CTLE model for HBR
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3
DisplayPort 1.2 Source Tests
Table 2
CTLE Model for HBR
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.725 GHz
0.725 GHz
Pole 1 Frequency
1.35 GHz
1.35 GHz
Pole 2 Frequency
2.5 GHz
2.5 GHz
For main link, use the CTLE model with the following transfer function for HBR2 (5.4 Gbps):
Figure 5
Table 3
Transfer Function of the CTLE model for HBR2
CTLE Model for HBR2
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.64 GHz
0.64 GHz
Pole 1 Frequency
2.7 GHz
2.7 GHz
Pole 2 Frequency
4.5 GHz
4.5 GHz
Pole 3 Frequency
13.5 GHz
13.5 GHz
Clock Recovery
When Clock Recovery is required, the clock recovery technique follows the definition of the receiver
PLL as defined in Section 3.5.3.5 of the VESA DisplayPort 1.2a Standard. For main link, use the
second-order clock recovery function with a closed loop tracking bandwidth and damping factor,
with respect to the PRBS7 pattern, as shown in Table 4:
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
Table 4
3
Main Link Second-Order Clock Recovery Function
Bit Rate
Band wid th
Damping Factor
HBR2 (5.4 Gbps)
10 MHz
1.00
HBR (2.7 Gbps)
10 MHz
1.51
RBR (1.62 Gbps)
5.4 MHz
1.51
Test Point Definition for DisplayPort 1.2 (1.2b) Source Tests
Test the Source DUT at Test Point 2 (TP2) as shown in Figure 6. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 6
Test Point 2 Connection for DisplayPort 1.2 Source Tests
Table 5 defines the test point fixtures and instruments used for DisplayPort 1.2 (1.2b) Source Tests:
Table 5
Test Point Fixtures and Instruments for DisplayPort 1.2 Source Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
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3
DisplayPort 1.2 Source Tests
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in "Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 7)
Figure 7
62
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
9
3
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.2 Source Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 8
Sample connection diagram for DisplayPort 1.2 Source Tests
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3
DisplayPort 1.2 Source Tests
Source Eye Diagram Test
Test ID
1210001, 1210002, 1210003, 1210004 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
64
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
Spread Spectrum Clocking
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Swing
Level 2
Pre-Emphasis Level
Level 0
Post Cursor2 Level
Level 0
Lane Setting
All test lanes supported
Test Pattern
PRBS7
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
66
DisplayPort 1.2 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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3
DisplayPort 1.2 Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure VTOP and VBASE of the input signal using the pattern folding.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the input signal eye diagram to measure the left
edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the eye height of the eye diagram using the Histogram.
9
Measure the jitter of the eye diagram using the Histogram.
10 Calculate the eye width based on the measured jitter of the eye diagram.
11 Check for any signal trajectories that may have entered into the mask.
12 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 6 shows the voltage and time coordinates for the mask used
in the eye diagram.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
Table 6
Eye Diagram Mask Coord inates for HBR and RBR
Mask Point
Figure 9
3
Bit Rate
Reduced (1.62 Gb/s)
High (2.7 Gb/s)
1
0.127, 0.000
0.210, 0.000
2
0.291, 0.160
0.355, 0.140
3
0.500, 0.200
0.500, 0.175
4
0.709, 0.200
0.645, 0.175
5
0.873, 0.000
0.790, 0.000
6
0.709,-0.200
0.645,-0.175
7
0.500,-0.200
0.500,-0.175
8
0.291,-0.160
0.355,-0.140
The Source Eye Mask
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-24 for RBR and
Table 3-23 for HBR
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3
DisplayPort 1.2 Source Tests
Expected/Observable Results
The measured eye diagram for the source degraded signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
70
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Source Total Jitter Test
Test ID
1220001, 1220002, 1220003, 1220004 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
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3
DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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3
74
DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Report the measurement results.
PASS Condition
Table 7
Total Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.294 UI
0.420 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.180 UI
0.270 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Source Tests
Source Non ISI Jitter Test
Test ID
1230001, 1230002, 1230003, 1230004 — Non ISI Jitter Test
Test Overview
The objective of the test is to evaluate the amount of Non ISI jitter accompanying the data
transmission at either an explicit bit error rate of 10-9 or through an approved estimation technique.
This measurement is a data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Non ISI Jitter Test
76
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
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DisplayPort 1.2 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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3
DisplayPort 1.2 Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Calculate the Non ISI jitter using the following equation:
Non ISI Jitter = TJ - ISI
7
Report the measurement results.
PASS Condition
Table 8
Non-ISI Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.260 UI
0.276 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.160 UI
0.210 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.11
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Source Tests
3
Source Non Pre-Emphasis Level Test
Test ID
For RBR and HBR:
• 1261001, 1261002, 1261003, 1261004 — Non Pre-Emphasis Level Test (Swing 1/Swing 0)
• 1262001, 1262002, 1262003, 1262004 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
• 1263001, 1263002, 1263003, 1263004 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
For HBR2:
• 1264101, 1264102, 1264103, 1264104 — Non Pre-Emphasis Level Test (Swing 2/Swing 0)
• 1262101, 1262102, 1262103, 1262104 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
• 1263101, 1263102, 1263103, 1263104 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
Test Overview
The objective of this test is to ensure that the system budget elements are obeyed and to ensure that
the level settings are monotonic so that the sink relies on the source to incrementally increase upon
request by the sink.
Test Conditions for Non Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
For Voltage Level A with no pre-emphasis level:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_Lvl0_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 10
High Voltage measurement for RBR and HBR
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Figure 11
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in PLTPAT test pattern for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_Lvl0_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 12
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
86
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
j
3
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_Lvl0_PP = VT_Lvl0_H - VT_Lvl0_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_Lvl0_PP = VN_Lvl0_H - VN_Lvl0_L
2
Repeat Step 1 for Voltage Level B with no pre-emphasis level.
3
Calculate the non pre-emphasis level output voltage ratio using the equation:
Non Pre-Emphasis Level = 20 * Log10[Voltage Level A VN_Lvl0_PP / Voltage Level B VN_Lvl0_PP]
4
Report the measurement results.
PASS Condition
For each level setting testes, the following equation should be used:
Resultant = 20 * Log10[VoltagePeak-Peak_LevelA / VoltagePeak-Peak_LevelB]
Table 9
Compared Levels
Measurement#
Vol tagePeak-Peak_LevelA
VoltagePeak-Peak_LevelB
1
Level 1 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
2
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
3*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
4
Level 2 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
5
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
6*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
RBR & HBR
HBR2
* if device optionally capable of Level 3
The resultants specifications are as identified below:
Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB
Measurement 3: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 4: 5.2 dB ≤ Resultant ≤ 6.9 dB
Measurement 5: 1.6 dB ≤ Resultant ≤ 3.5 dB
Measurement 6: 1 dB ≤ Resultant ≤ 4.4 dB
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Table 10
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-OUTPUT-RATIO_RBR_HBR
VTX-OUTPUT-RATIO_HBR2
Parameter
Min
Nom
Max
Unit
Ratio of Output Voltage
Level 1/Level 0
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 1
0.1
-
5.1
dB
Ratio of Output Voltage
Level 3/Level 2
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 0
5.2
-
6.9
dB
Ratio of Output Voltage
Level 2/Level 1
1.6
-
3.5
dB
Ratio of Output Voltage
Level 3/Level 2
1
-
4.4
dB
Comments
Measured on non-transition
bits at Pre-emphasis level 0
setting
Measured on non-transition
bits at Pre-emphasis level 0
setting
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level ratio of the non pre-emphasis level test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Source Pre-Emphasis Level Test
Test ID
For RBR and HBR:
•
1270001, 1270002, 1270003, 1270004 — Pre-Emphasis Level Test
For HBR2:
•
1270501, 1270502, 1270503, 1270504 — Pre-Emphasis Level Test
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Test Conditions for Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
For a given Voltage Level and a Pre-Emphasis Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 13
High Voltage measurement for RBR and HBR
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Figure 14
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PLTPAT for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 15
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
94
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
j
3
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
l
Calculate the pre-emphasis level using the equation:
Pre-EmphasisLvlX = 20 * Log10[VT_LvlX_PP / VN_LvlX_PP]
2
For Pre-Emphasis Level 0 (no pre-emphasis level), the result for Pre-EmphasisLvl0 is compared
with the maximum pre-emphasis disabled limit.
3
Repeat Step 1 for the next Pre-Emphasis level and for each Pre-Emphasis levels, compare the
pre-emphasis delta with the pre-emphasis delta limits.
4
Calculate the pre-emphasis delta using the equation:
Pre-Emphasis Delta (Level 1 vs Level 0) = Pre-EmphasisLvl1 - Pre-EmphasisLvl0
Pre-Emphasis Delta (Level 2 vs Level 1) = Pre-EmphasisLvl2 - Pre-EmphasisLvl1
Pre-Emphasis Delta (Level 3 vs Level 2) = Pre-EmphasisLvl3 - Pre-EmphasisLvl2
5
Report the measurement results.
PASS Condition
Pre-emphasis values for the Level 0 (OFF) state (Normative)
Level 0 (OFF) Pre-emphasis measurement:
Resultant = 20 * Log [VoltageT_Lvl0_PP / VoltageN_Lvl0_PP] for all supported levels.
Level 0 (OFF) Pre-emphasis Measurement condition: +0.25 dB > Resultant
Pre-emphasis Delta values for:
a Level 1 vs. Level 0 Pre-emphasis settings (NORMATIVE)
b Level 2 vs. Level 1 Pre-emphasis settings (NORMATIVE)
c Level 3 vs. Level 2 Pre-emphasis settings (NORMATIVE)
Pre-emphasis Delta measurements:
•
Level 1 vs. Level 0
Resultant = 20 * Log [VoltageT_Lvl1_PP / VoltageN_Lvl1_PP] - 20 * Log [VoltageT_Lvl0_PP /
VoltageN_Lvl0_PP] for Voltage Swing Levels 0, 1 and 2.
•
Level 2 vs. Level 1
Resultant = 20 * Log [VoltageT_Lvl2_PP / VoltageN_Lvl2_PP] - 20 * Log [VoltageT_Lvl1_PP /
VoltageN_Lvl1_PP] for Voltage Swing Levels 0 and 1.
•
Level 3 vs. Level 2
Resultant = 20 * Log [VoltageT_Lvl3_PP / VoltageN_Lvl3_PP] - 20 * Log [VoltageT_Lvl2_PP /
VoltageN_Lvl2_PP] for Voltage Swing Level 0, if supported.
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Table 11
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
VTX-PREEMP-OFF
Maximum Pre-emphasis
when disabled
-
-
0.25
dB
Delta of Pre-emphasis
Level 1 vs. Level 0
2
-
-
dB
Delta of Pre-emphasis
Level 2 vs. Level 1
1.6
-
-
dB
Delta of Pre-emphasis
Level 3 vs. Level 2
1.6
-
-
dB
VTX-PREEMP-DELTA
Min
Nom
Max
Unit
Comments
Pre-emphasis Level 0 setting
must not show any
pre-emphasis at TP2 to
prevent link training issues.
Applies to all valid voltage
settings. Measured at
Pre-emphasis Post Cursor2
Level 0.
Support for Pre-emphasis
Level 3 is optional.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis level or pre-emphasis delta for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Source Non Transition Voltage Range Measurement Test
Test ID
For RBR and HBR:
•
1272001, 1272002, 1272003, 1272004 — Non Transition Voltage Range Measurement (Swing 0)
•
1273001, 1273002, 1273003, 1273004 — Non Transition Voltage Range Measurement (Swing 1)
•
1274001, 1274002, 1274003, 1274004 — Non Transition Voltage Range Measurement (Swing 2)
For HBR2:
•
1272101, 1272102, 1272103, 1272104 — Non Transition Voltage Range Measurement (Swing 0)
•
1273101, 1273102, 1273103, 1273104 — Non Transition Voltage Range Measurement (Swing 1)
•
1274101, 1274102, 1274103, 1274104 — Non Transition Voltage Range Measurement (Swing 2)
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Comparisons are also made for the Level 0 transition state as well as non-transition levels.
Test Conditions for Non Transition Voltage Range Measurement Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Transition Voltage Range Measurement Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
For a given Voltage Level, repeat the following steps for all pre-emphasis levels subjected to
constraints specified in Table 3-1 of the VESA DisplayPort 1.2a Standard:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 16
High Voltage measurement for RBR and HBR
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Figure 17
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PLTPAT for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 18
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
102
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
j
3
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
2
Calculate the non transition voltage range using the equation:
Non Transition Voltage Range = Minimum [(VN_LvlX_PP) / (VN_Lvl0_PP)]
where, VN_LvlX_PP) refers to all supported pre-emphasis levels (Level1, Level2, Level3 and so on
up to Level X).
3
Report the measurement results.
PASS Condition
Non-Transition Voltage Range Measurements
For Level 2 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 1 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 0 voltage setting: Resultant > 0.85 OR 20*log(Resultant) > -1.4dB
Table 12
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-DIFF_REDUCTION
Parameter
Min
Nom
Max
Unit
Non-transition reduction
Output Voltage Level 2
-
-
3
dB
Non-transition reduction
Output Voltage Level 1
-
-
3
dB
Non-transition reduction
Output Voltage Level 0
-
-
1.4
dB
Comments
VTX-DIFF at each non-zero
nominal pre-emphasis level
must not be lower than the
specified amount less than
VTX-DIFF at the zero nominal
pre-emphasis level.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level reduction of the non transition bit for the test signal shall be
within the conformance limits as specified in the specification mentioned under the “PASS Condition”
section for this test.
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Source Peak to Peak Voltage Test
Test ID
For RBR and HBR:
•
1266001, 1266002, 1266003, 1266004 — Peak to Peak Voltage Test
For HBR2:
•
1266101, 1266102, 1266103, 1266104 — Peak to Peak Voltage Test
Test Overview
The objective of this test is to evaluate the maximum differential peak to peak voltage.
Test Conditions for Peak to Peak Voltage Test
104
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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DisplayPort 1.2 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Peak to Peak Voltage Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure the maximum and minimum voltage of the input signal.
4
Calculate the peak to peak voltage using the equation:
Peak to Peak Voltage = Maximum Voltage - Minimum Voltage
5
Report the measurement results.
PASS Condition
For all Data Rates:
Maximum Differential Peak to Peak Voltage < 1.38V
Table 13
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
VTX-DIFFp-p_MAX
Max Output Voltage Level
-
Nom
-
Max
1.38
Unit
V
Comments
For all Output Level and
Pre-emphasis combinations.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured peak to peak voltage for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Inter Pair Skew Test
Test ID
1290001 — Lane0/Lane1 Inter-Pair Skew Test
1290002 — Lane0/Lane2 Inter-Pair Skew Test
1290003 — Lane0/Lane3 Inter-Pair Skew Test
1290004 — Lane1/Lane2 Inter-Pair Skew Test
1290005 — Lane1/Lane3 Inter-Pair Skew Test
1290006 — Lane2/Lane3 Inter-Pair Skew Test
Test Overview
The objective of the test is to evaluate the skew or time delay between differential data lanes in the
DisplayPort interface.
Test Conditions for Inter Pair Skew Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
For two lane operation:
Lane 0 to Lane 1
For four lane operation:
Lane 0 to Lane 1
Lane 0 to Lane 2
Lane 0 to Lane 3
Lane 1 to Lane 2
Lane 1 to Lane 3
Lane 2 to Lane 3
Test Pattern
PRBS7
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DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Inter Pair Skew Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
For a given inter-pair skew measurement of Lane A to Lane B:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the Lane A input signal.
ii
Scale the vertical display of the Lane A input signal to optimum value.
iii Measure VTOP and VBASE of the Lane A input signal.
iv Verify the trigger and the amplitude of the Lane B input signal.
v
Scale the vertical display of the Lane B input signal to optimum value.
vi Measure VTOP and VBASE of the Lane B input signal.
vii Measure the data rate of the Lane A input signal.
viii Measure the data rate of the Lane B input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
d Set up the parameter for the inter-pair skew measurement:
i
Set up two display grids such that each grid displays one test lane data signal.
ii
Set up the measurement threshold for each test lane data signal on the Transition
Voltage = 0V.
iii Decode the data signal for each test lane.
iv Search the desired pattern from the decoded data signal.
v
Measure the time difference between the corresponding edges of both test lanes:
TTransition_LaneA - TTransition_LaneB
vi Repeat the previous step until you measure 100 edges.
vii VESA DisplayPort 1.2a Standard specifies 20 UI offset Lane 0 to Lane 1, Lane 1 to Lane 2
and Lane 2 to Lane 3. The resultant offset is cumulative.
viii Calculate the inter-pair skew using the equation:
Inter-Pair Skew = {1/Number of Edges} ∑|TTransition_LaneA - TTransition_LaneB| - Nominal Skew
where, Nominal Skew is the expected offset between tested lanes.
2
Report the measurement results.
PASS Condition
For RBR or HBR: -2UI < Inter-Lane Skew Tolerance < 2UI.
For HBR2: -(4UI + 500ps) < Inter-Lane Skew Tolerance < (4UI + 500ps).
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Table 14
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
LTX-SKEW-INTER_PAIR-HBR_RBR
Lane-to-Lane Output
Skew
-
LTX-SKEW-INTER_PAIR-HBR2
Lane-to-Lane Output
Skew
-
Nom
Max
Unit
-
2
UI
-
4UI +
500ps
Comments
Applies to transmitters capable
of 2- and 4-lane operation.
Also, applies to all pairwise
combinations of supported
lanes.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured inter-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Source Main Link Frequency Compliance Test
Test ID
12193001 12193002 12193003 12193004 — Main Link Frequency Compliance
Test Overview
The objective of this test is to ensure that the average data rate under all conditions does not exceed
the minimum and maximum values as set by the VESA DisplayPort 1.2a Standard.
Test Conditions for Main Link Frequency Compliance Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
D10.2
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DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Main Link Frequency Compliance Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and the minimum measurement levels for the FUNC2 magnified unit
interval measurement trend.
d Set up two frequency measurement levels for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e For SSC Enabled Test condition, check the measured frequency to verify the existence of SSC
in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
For the test condition “SSC Enabled”, set up the parameter of the SSC measurement:
a Set up the memory depth and time-base to display one complete SSC cycle based on the
measured SSC modulation frequency in Step 5.
b Acquire the signal with one complete SSC cycle.
c Get the minimum of FUNC2 filtered unit interval measurement trend to calculate the maximum
data rate:
Maximum Data Rate = 1 / (Minimum Unit Interval)
d Get the maximum of FUNC2 filtered unit interval measurement trend to calculate the minimum
data rate:
Minimum Data Rate = 1 / (Maximum Unit Interval)
e Repeat steps b, c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rates.
10 Report the measurement results.
PASS Condition
Maximum Data Rate (Frequency Maxppm) < 300 ppm
Minimum Data Rate (Frequency Minppm) > -5300 ppm
Table 15
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Unit
fHBR2
Frequency for High
Bit Rate 2
5.37138
5.4
5.40162
Gbps
fHBR
Frequency for High
Bit Rate
2.68569
2.7
2.70081
Gbps
fRBR
Frequency for
Reduced Bit Rate
1.611414
1.62
1.620486
Gbps
Comments
Frequency high limit =
+300ppm
Frequency low limit =
-5300ppm
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.14
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured data rate for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID
12170001 12170002 12170003 12170004 — SSC Modulation Frequency Test
Test Overview
The objective of this test is to evaluate the frequency of the SSC modulation and to validate that the
frequency is within specification limits. This test includes the use of the 2nd order Butterworth
low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of
10 full SSC cycles. Calculate the SSC modulation frequency from the average of the measured SSC
modulation frequency for each cycle.
Test Conditions for SSC Modulation Frequency Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
D10.2
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DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Frequency Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
g Acquire the signal for 10 SSC Cycles.
6
Get the mean value for the SSC Modulation frequency.
7
Report the measurement results.
PASS Condition
30kHz < SSC Modulation Frequency (fSSC) < 33kHz
Table 16
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Down_Spread_Frequency
Link clock down-spreading
frequency
30
-
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Unit
kHz
Comments
Range: 30kHz ~ 33kHz when
down-spread enabled
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DisplayPort 1.2 Source Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.15
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation frequency for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID
12180001 12180002 12180003 12180004 — SSC Modulation Deviation Test
Test Overview
The objective of this test is to evaluate the range of SSC down-spreading of the transmitter signal in
ppm and to validate that the values are within specification limits. This test includes the use of the
2nd order Butterworth low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is
conducted over a minimum of 10 full SSC cycles. For each cycle, the minimum and maximum data
rate is evaluated. Calculate the SSC modulation deviation from the average of the maximum minus
the average of the minimum using the equation:
SSC Modulation Deviation = {[Average (Maximum Data Rate) - Average (Minimum Data Rate)]
/ Nominal Data Rate}*1e6
Test Conditions for SSC Modulation Deviation Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
D10.2
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DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Deviation Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and minimum measurements for the FUNC2 magnified unit interval
measurement trend.
d Set up two frequency measurements for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e Check the measured frequency to verify the existence of SSC in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point for three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 filtered unit interval measurement
trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurements for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
Set up the parameters for SSC measurement.
a Set up memory depth and time-base to display one complete SSC Cycle based on the
measured SSC modulation frequency in step 5.
b Acquire the signal with one complete SSC Cycle.
c Get the minimum of the FUNC2 filtered unit interval measurement trend to calculate the
maximum data rate:
Maximum Data Rate = 1/Minimum Unit Interval
d Get the maximum of the FUNC2 filtered unit interval measurement trend to calculate the
minimum data rate:
Minimum Data Rate = 1/Maximum Unit Interval
e Repeat steps b, c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rate.
10 Calculate the SSC Modulation Deviation using the equation:
SSC Modulation Deviation = (Maximum Data Rate - Minimum Data Rate) / (Nominal Data
Rate) * 1E6
11 Report the measurement results.
PASS Condition
-5000ppm < SSC Modulation Deviation (ResultantSSC Range) < 0ppm
Table 17
DisplayPort Main Link Transmitter System Parameters
Symbol
Parameter
Min
Nom
Max
Down_Spread_Amplitude
Link clock down-spreading
0
-
0.5
Unit
%
Comments
Range: 0% ~ 0.5% when
down-spread enabled
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.16
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation deviation for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID
12200001 12200002 12200003 12200004 — SSC Deviation HF Variation Test (Informative)
Test Overview
The objective of this test is to verify that the SSC profile does not include any frequency deviation
that may exceed 1250 ppm/µsec. This test includes the use of the 2nd order Butterworth low-pass
filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of 10 full
SSC cycles.
Test Conditions for SSC Deviation HF Variation Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Deviation HF Variation Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
6
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
Set up the parameters for the SSC measurement.
a Set up memory depth and time-base to display one complete SSC cycle using the measured
SSC Modulation Frequency in Step 5.
b Acquire the signal with one complete SSC Cycles.
c Read the FUNC2 filtered unit interval measurement trend.
d Compute the slope using the “Sliding Window” with 1.00 µsec window width. Calculate the
slope using the equation:
Slope = [f(t) - f(t-1.00 µsec)/1.00 µsec
e Repeat step b, c and d until you acquire 10 SSC Cycles.
f
7
Get the maximum value for the computed value of slope.
Report the measurement results.
PASS Condition
SSCt dF/dt < 1250ppm/µsec
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.17
Expected/Observable Results
The measured SSC deviation high frequency variation for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Source Post-Cursor 2 Verification Test (Informative)
Test ID
1279001 1279002 1279003 1279004 — Post Cursor 2 Verification Test - Level 1/Level 0 (Informative)
1279101 1279102 1279103 1279104 — Post Cursor 2 Verification Test - Level 2/Level 1 (Informative)
1279201 1279202 1279203 1279204 — Post Cursor 2 Verification Test - Level 3/Level 2 (Informative)
Test Overview
The objective of this test is to evaluate the effect of adding Post-Cursor 2 of the source waveform by
measuring the peak differential amplitude to assure accuracy of the Post-Cursor 2 settings.
Test Conditions for Post Cursor 2 Verification Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported subject to constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
All Post-Cursor 2 levels supported
Test Lane
All test lanes are supported
Test Pattern
PCTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Post Cursor 2 Verification Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
For a given Voltage Level, Pre-Emphasis Level and Post-Cursor 2 Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d Pattern fold the input signal based on the qualifying pattern 00101010 for the measurement of
voltage VT1010_PC2_LvlX_PP in the test pattern PLTPAT.
e Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1010_PC2_LvlX_H and Low Voltage VT1010_PC2_LvlX_L.
f
i
VT1010_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1010 portion of the qualifying pattern.
ii
VT1010_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1010 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1010_PC2_LvlX_PP using the equation:
VT1010_PC2_LvlX_PP = VT1010_PC2_LvlX_H - VT1010_PC2_LvlX_L
g Pattern fold the input signal based on the qualifying pattern 00011001100 for the
measurement of voltage VT1100_PC2_LvlX_PP in the test pattern PLTPAT.
h Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1100_PC2_LvlX_H and Low Voltage VT1100_PC2_LvlX_L.
i
i
VT1100_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1100 portion of the qualifying pattern.
ii
VT1100_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1100 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1100_PC2_LvlX_PP using the equation:
VT1100_PC2_LvlX_PP = VT1100_PC2_LvlX_H - VT1100_PC2_LvlX_L
j
Calculate the Post-Cursor 2 ratio using the equation:
Post-Cursor 2 RatioLvlX = VT1100_PC2_LvlX_PP / VT1010_PC2_LvlX_PP
2
Compare the pre-emphasis delta of Post-Cursor 2 Level with the limits by repeating Step 1 with
another Post-Cursor2 Level.
3
Calculate the pre-emphasis delta of Post-Cursor 2 Level using the equation:
Post-Cursor 2 Delta (Level 1 vs Level 0) = 20 * Log10[Post-Cursor 2 RatioLvl1 / Post-Cursor 2
RatioLvl0]
Post-Cursor 2 Delta (Level 2 vs Level 1) = 20 * Log10[Post-Cursor 2 RatioLvl2 / Post-Cursor 2
RatioLvl1]
Post-Cursor 2 Delta (Level 3 vs Level 2) = 20 * Log10[Post-Cursor 2 RatioLvl3 / Post-Cursor 2
RatioLvl2]
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4
Report the measurement results.
PASS Condition
Post Cursor 2 Verification Measurements
For Level 1 vs. Level 0 Pre-emphasis Post Cursor 2 settings: ResultantLvl0_to_Lvl1 < -0.45 dB
For Level 2 vs. Level 1 Pre-emphasis Post Cursor 2 settings: ResultantLvl1_to_Lvl2 < -0.5 dB
For Level 3 vs. Level 2 Pre-emphasis Post Cursor 2 settings: ResultantLvl2_to_Lvl3 < -0.6 dB
Table 18
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-PREEMP_POST2-DELTA
Parameter
Min
Delta of Pre-emphasis Post
Cursor2 Level 1 vs. Level 0
-0.45
Delta of Pre-emphasis Post
Cursor2 Level 2 vs. Level 1
Delta of Pre-emphasis Post
Cursor2 Level 3 vs. Level 2
Nom
Max
Unit
Comments
-
-
dB
Measured on 2nd TBIT at
Pre-emphasis Level 0
-0.5
-
-
dB
Support for Pre-emphasis
Post Cursor2 is optional
-0.6
-
-
dB
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2a, Section 3.3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis delta of Post-Cursor 2 for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Source Eye Diagram Test (TP3_EQ)
Test ID
For HBR:
•
1211001, 1211002, 1211003, 1211004 — Eye Diagram Test (TP3_EQ) - PRBS7
•
1211011, 1211012, 1211013, 1211014 — Eye Diagram Test with No Cable Model (TP3_EQ) PRBS7
For HBR2:
•
1215001, 1215002, 1215003, 1215004 — Eye Diagram Test (TP3_EQ) - HBR2CPAT
•
1215011, 1215012, 1215013, 1215014 — Eye Diagram Test with No Cable Model (TP3_EQ) HBR2CPAT
Test Overview
The objective of this test is to evaluate the waveform, ensuring that the timing variables and
amplitude trajectories support the overall DP system objectives of the Bit Error Rate in data
transmission.
Test Conditions for Eye Diagram Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR (Informative) and HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
HBR — Level 2
HBR2 — Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
HBR — Level 0
HBR2 — Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
HBR — Level 0
HBR2 — Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes are supported
Test Pattern
HBR—PRBS7
HBR2—HBR2CPAT
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure for HBR
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the jitter of the eye diagram using the Histogram.
9
Check for any signal trajectories that may have entered into the mask.
10 Report the measurement results.
Measurement Procedure for HBR2
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
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4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Pattern fold the equalized signal based on the High Level Voltage (VHIGH) random noise
configuration variable.
b Set up the vertical waveform histogram on the equalized signal to measure random noise of
High Level Voltage (VHIGH).
c Measure the High Level Voltage (VHIGH) random noise based on the standard deviation of the
waveform histogram.
d Pattern fold the equalized signal based on the Low Level Voltage (VLOW) random noise
configuration variable.
e Set up the vertical waveform histogram on the equalized signal to measure the random noise
of Low Level Voltage (VLOW).
f
Measure the Low Level Voltage (VLOW) random noise based on the standard deviation of the
waveform histogram.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge and right edge.
8
Set up the vertical waveform histogram on the equalized signal eye diagram to measure the eye
height from 0.375 UI to 0.625 UI.
9
Find the maximum eye height location of the eye diagram.
10 If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Set up the parameter of the jitter separation using the EZJIT Plus/Complete Software.
i
Load the jitter separation parameter into EZJIT Plus/Complete Software based on the
settings in the Configuration Variable.
ii
Acquire the signal until 1,000,000 edges are analyzed.
b Note the value of the jitter component from the EZJIT Plus/Complete Software.
11 Create the eye mask based on the following criteria:
a If you select more than one lane (2 lanes or 4 lanes DUT configuration), the eye mask height
and width is derate in the following manner, to include crosstalk as defined in DisplayPort 1.2b
Compliance Test Specification:
i
Eye Mask Width Derate (Crosstalk) = 0.04 UI
ii
Eye Mask Height Derate (Crosstalk) = 0.014V
b If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]: eye mask height and width is derate as below to comprehend the
noise/jitter extrapolated to BER 10-9 for an Eye Diagram Test (TP3_EQ) only acquiring 1e6 UI:
i
Calculate the Eye Mask Width Derate (Random Jitter) using the equation:
Eye Mask Width Derate (Random Jitter) = 2.5 * Random Jitterrms
ii
Calculate the Eye Mask Height Derate (Random Noise) using the equation:
VHIGH Eye Mask Height Derate (Random Noise) = 2.5 * VHIGH Random Noiserms
VLOW Eye Mask Height Derate (Random Noise) = 2.5 * VLOW Random Noiserms
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NOTE
3
The factor 2.5 is the delta between BER 10-6 (9.507) and 10-9 (11.996) to
comprehend the noise/jitter extrapolated to BER 10-9 as the Eye Diagram
Test (TP3_EQ) only acquiring 1e6 UI.
BER
N
10-6
9.507
10-7
10.399
10-8
11.224
10-9
11.996
c Place the eye mask height at the point of the maximum eye height found in Step 9.
d Calculate the Eye Mask Width:
Eye Mask Width = Eye Width Specification (0.38 UI) + Eye Mask Width Derate (Crosstalk) + 2 *
Eye Mask Width Derate (Random Jitter)
e Calculate the Eye Mask Height:
VHIGH Eye Mask Height = {Eye Height Specification (0.09 UI) + Eye Mask Height Derate
(Crosstalk)}/2 + VHIGH Eye Mask Height Derate (Random Noise)
VLOW Eye Mask Height = -{Eye Height Specification (0.09 UI) + Eye Mask Height Derate
(Crosstalk)}/2 - VLOW Eye Mask Height Derate (Random Noise)
12 Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram.
c Run the eye mask until 1,000,000 UI are folded.
13 Measure the eye height of the eye diagram using the Histogram.
14 Measure the jitter of the eye diagram using the Histogram.
15 Calculate the eye width based on the measured jitter of the eye diagram.
16 Check for any signal trajectories that may have entered into the mask.
17 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 19 and Table 20 show the voltage and time coordinates for
the mask used for the eye diagram.
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Table 19
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 19
152
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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Table 20
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Figure 20
3
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
The Sink Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-25 for HBR and
Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Source Total Jitter Test (TP3_EQ)
Test ID
For HBR2:
•
1222001, 1222002, 1222003, 1222004 — Total Jitter Test (TP3_EQ) - HBR2CPAT
•
1222011, 1222012, 1222013, 1222014 — Total Jitter Test with No Cable Model (TP3_EQ) HBR2CPAT
•
1221001, 1221002, 1221003, 1221004 — Total Jitter Test (TP3_EQ) - D10.2
•
1221011, 1221012, 1221013, 1221014 — Total Jitter Test with No Cable Model (TP3_EQ) - D10.2
Test Overview
The objective of this test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test (TP3_EQ)
154
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes are supported
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 21
Total Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.580 UI*
Ap-p
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
Table 22
Total Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.40 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured total jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Source Tests
Source Deterministic Jitter Test (TP3_EQ)
Test ID
•
1236001, 1236002, 1236003, 1236004 — Deterministic Jitter Test (TP3_EQ) - HBR2CPAT
•
1236011, 1236012, 1236013, 1236014 — Deterministic Jitter Test with No Cable Model (TP3_EQ)
- HBR2CPAT
•
1235001, 1235002, 1235003, 1235004 — Deterministic Jitter Test (TP3_EQ) - D10.2
•
1235011, 1235012, 1235013, 1235014 — Deterministic Jitter Test with No Cable Model (TP3_EQ)
- D10.2
Test Overview
The objective of this test is to evaluate the deterministic jitter accompanying the data transmission.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Deterministic Jitter Test (TP3_EQ)
160
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes are supported
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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DisplayPort 1.2 Source Tests
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Deterministic Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 23
Deterministic Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.49 UI
Ap-p
Table 24
Deterministic Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.25 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured deterministic jitter for the test signal at TP3_EQ shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Source Tests
Source Random Jitter Test (TP3_EQ)
Test ID
•
1238001, 1238002, 1238003, 1238004 — Random Jitter Test (TP3_EQ) - D10.2
•
1238011, 1238012, 1238013, 1238014 — Random Jitter Test with No Cable Model (TP3_EQ) D10.2
Test Overview
The objective of this test is to evaluate the random jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. The jitter is
separated into each jitter components and the random jitter is estimated to 10-9 BER based on the
Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Random Jitter Test (TP3_EQ)
166
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes are supported
Test Pattern
D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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DisplayPort 1.2 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Random Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 25
Random Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.23 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured random jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source AC Common Mode Test (Informative)
Test ID
12110001, 12110002, 12110003, 12110004 — AC Common Mode Test (Informative)
Test Overview
The objective of this test is to evaluate the AC Common Mode noise (unfiltered rms) of the differential
data line of the DP interface.
Test Conditions for AC Common Mode Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis level supported subject to the constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
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DisplayPort 1.2 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for AC Common Mode Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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DisplayPort 1.2 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Source Tests
3
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Create FUNC3 signal, which is the common mode signal of the input single-ended signal.
4
If the filter is enabled [“Filter” configuration variable set to “High Pass Filter”, “Low Pass Filter” or
“None” (Default)]:
a Create FUNC4 signal, which is the filtered FUNC3 signal by applying the High Pass filter or
Low Pass filter on the FUNC3 signal based on the Configuration Variable.
5
6
Set up two display grids such that one grid displays the input single-ended signal while the other
grid displays the common mode signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
7
Set up the parameters for RMS voltage measurement of the common mode signal.
a Set up the Vrms measurement for the common mode signal.
b Acquire the signal until 100,000 edges are measured.
8
Get the mean for the Vrms measurement.
9
Report the measurement results.
PASS Condition
For RBR and HBR:
AC Common Mode Voltage < 20mV
For HBR2:
AC Common Mode Voltage < 30mV
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.10
• VESA DisplayPort Standard Version 1, Revision 2a, Section 9.2, Table 9-6
Expected/Observable Results
The measured AC common mode noise for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Source Tests
Source Intra-Pair Skew Test (Informative)
Test ID
12100001, 12100002, 12100003, 12100004 — Intra-Pair Skew Test (Informative)
Test Overview
The objective of this test is to evaluate the skew or time delay between respective sides of a
differential data lane in the DP interface.
Test Conditions for Intra-Pair Skew Test (Informative)
176
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
For one lane operation:
Lane 0+ to Lane 0For two lane operation:
Lane 0+ to Lane 0Lane 1+ to Lane 1For four lane operation:
Lane 0+ to Lane 0Lane 1+ to Lane 1Lane 2+ to Lane 2Lane 3+ to Lane 3-
Test Pattern
D10.2
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
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DisplayPort 1.2 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Intra-Pair Skew Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Source Tests
3
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See "Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Source Tests" on page 62 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
4
Set up the parameters to perform High Level Voltage (VHIGH) and Low Level Voltage (VLOW) for
each input single-ended signal.
a Scale the vertical display of the input single-ended signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHIGH by measuring the average voltage at 0.06 UI to 0.75 UI of the High Level.
d Find VLOW by measuring the average voltage at 0.06 UI to 0.75 UI of the Low Level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHIGH + VLOW) / 2
5
Set up the parameters for the intra-pair skew measurement:
a Set up the measurement threshold for each single-ended data signal based on the measured
Transition Voltage.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) rising edge:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the intra-pair skew using the equation:
Intra-Pair Skew = {1/Number of Edges}
∑ {[(D+Transition_High - D-Transition_Low) + (D+Transition_Low - D-Transition_High)] / 2}
6
Report the measurement results.
PASS Condition
Intra Pair Skew ≤ 30 ps
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.5
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• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured intra-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “Test References” section for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
4
DisplayPort 1.2 Sink Tests
Overview / 184
Sink Eye Diagram Test / 189
Sink Total Jitter Test / 196
Sink Non-ISI Jitter Test / 202
4
DisplayPort 1.2 Sink Tests
Overview
Test Point Definition for DisplayPort 1.2 (1.2b) Sink Tests
NOTE
Sink Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Sink DUT at Test Point 3(TP3) as shown in Figure 21. Unless specifically stated under the Test
Conditions, all supported lanes for the DUT shall be evaluated:
Figure 21
Test Point 3 Connection for DisplayPort 1.2 Sink Tests
Table 26 defines the test point fixtures and instruments used for DisplayPort 1.2 (1.2b) Sink Tests:
Table 26
184
Test Point Fixtures and Instruments for DisplayPort 1.2 Sink Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
Calibration of Stress Signal
For the calibration of the stress signal, you must test the stress signal in the manner shown in the
Figure 22 for RBR and Figure 23 for HBR and HBR2.
Figure 22
Test Point 3 Connection for Stress Signal Calibration of RBR
Figure 23
Test Point 3 Connection for Stress Signal Calibration of HBR and HBR2
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DisplayPort 1.2 Sink Tests
Table 27 defines the Test Point 3 Connections for Stress Signal Calibration:
Table 27
Test Point Connections for Stress Signal Calibration
Test Requirement
Device Used
Stress Signal Generator (SSG)
Bit Error Rate Tester
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Jitter Measurement Device (JMD)
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Sink Tests
Perform the following steps before you run the compliance tests on the sink device:
186
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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3
4
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 24).
Figure 24
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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DisplayPort 1.2 Sink Tests
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.2 Sink Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 25
188
Sample connection diagram for DisplayPort 1.2 Sink Tests
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
Sink Eye Diagram Test
Test ID
12140001, 12140002, 12140003, 12140004 — Sink Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the following specifications for degradation:
• Voltage Level:
•
90mV peak to peak +/- 10% for HBR2 at TP3_EQ (Table 3-18, DP1.2a)
•
150mV peak to peak +/- 10% for HBR at TP3_EQ (Table 3-25, DP1.2a)
•
46mV peak to peak +/- 10% for RBR at TP3 (Table 3-26, DP1.2a)
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Eye Diagram Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
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DisplayPort 1.2 Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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DisplayPort 1.2 Sink Tests
4
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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DisplayPort 1.2 Sink Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Sink Tests" on page 186 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer).
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 28 shows the voltage and time coordinates for the mask
used for the eye diagram.
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DisplayPort 1.2 Sink Tests
Table 28
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 26
194
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
Table 29
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Figure 27
4
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
The Sink Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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DisplayPort 1.2 Sink Tests
Sink Total Jitter Test
Test ID
12210001, 12210002, 12210003, 12210004 — Sink Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Total Jitter Test
196
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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DisplayPort 1.2 Sink Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Sink Tests" on page 186 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Sink Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 30
Total Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
0.580 UI*
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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Table 31
4
Total Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Sink Tests
Sink Non-ISI Jitter Test
Test ID
12220001, 12220002, 12220003, 12220004 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non ISI jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Non-ISI Jitter Test
202
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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DisplayPort 1.2 Sink Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
4
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Sink Tests" on page 186 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Sink Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 32
Non ISI Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
206
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Sink Tests
Table 33
4
Non ISI Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
5
DisplayPort 1.2 Cable Tests
Overview / 210
Cable Eye Diagram Test / 214
Cable Total Jitter Test / 220
Cable Non-ISI Jitter Test / 225
5
DisplayPort 1.2 Cable Tests
Overview
Test Point Definition for DisplayPort 1.2 (1.2b) Cable Tests
NOTE
Cable Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Cable DUT at Test Point 3 (TP3) as shown in Figure 28. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 28
210
Test Point 3 Connection for DisplayPort 1.2 Cable Tests
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Cable Tests
5
Table 34 defines the test point fixtures and instruments used for DisplayPort 1.2 (1.2b) Cable Tests:
Table 34
Test Point Fixtures and Instruments for DisplayPort 1.2 Cable Tests
Test Requirement
Device Used
Stimulus Instrument
Pulse Pattern Generator
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Table 35 defines the input signal parameters applied by the stimulus instrument at TP2:
Table 35
Input Signal Parameters by Stimulus Instrument
RBR
•
•
•
•
Reference Table 3-22 and Table 3-24, DP 1.2a
Edge Rate (20-80): 155-165ps (260mUI)
Eye Height: 400mV
Total Jitter: 270mUI
• ISI: 100mUI
• Random Jitter (rms): 7.9mUI
• Sinusoidal Jitter: ~75mUI at 20MHz (Adjust to achieve Total Jitter)
HBR
•
•
•
•
Reference Table 3-22 and Table 3-23, DP 1.2a
Edge Rate (20-80): 90-100ps (260mUI)
Eye Height: 350mV
Total Jitter: 420mUI
• ISI: 144mUI
• Random Jitter (rms): 13.2mUI
• Sinusoidal Jitter: ~117mUI at 20MHz (Adjust to achieve Total Jitter)
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DisplayPort 1.2 Cable Tests
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Cable Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 29).
Figure 29
212
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Cable Tests
9
5
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.2 Cable Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 30
Sample connection diagram for DisplayPort 1.2 Cable Tests
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DisplayPort 1.2 Cable Tests
Cable Eye Diagram Test
Test ID
12150001, 12150002, 12150003, 12150004 — Cable Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
214
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 35
Crosstalk Signal Parameter
Quarter-rate clock signal (D24.3 pattern) is injected to lanes other than the lane under
test. The characteristics of the aggressor signals are:
Pattern—D24.3
Bit Rate—(Same as lane under test)
Voltage Amplitude—(Same as lane under test)
• RBR-400mV
• HBR-350mV
Edge Rate (20-80)—130ps at TP3
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Cable Tests
5
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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DisplayPort 1.2 Cable Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Cable Tests
5
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Cable Tests" on page 212 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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DisplayPort 1.2 Cable Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 36 shows the voltage and time coordinates for the mask
used for the eye diagram.
218
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Cable Tests
Table 36
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 31
5
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Cable Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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Cable Total Jitter Test
Test ID
12230001, 12230002, 12230003, 12230004 — Cable Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
220
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 35
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Cable Tests" on page 212 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 37
Total Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Cable Non-ISI Jitter Test
Test ID
12240001, 12240002, 12240003, 12240004 — Cable Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non-ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. This
measurement is a data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 35
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of Oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Cable Tests" on page 212 to
complete the task flow for DUT setup along with configuring the Compliance Application to run the
test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 38
Non ISI Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non-ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
6
DisplayPort 1.2 AUX Channel
Tests
Overview / 232
Setting Up for AUX PHY and Inrush Tests / 235
AUX Channel Unit Interval Test / 243
AUX Channel Eye Test / 245
AUX Channel Peak-to-Peak Voltage Test / 247
AUX Channel Eye Sensitivity Calibration Test / 249
AUX Channel Eye Sensitivity Test / 251
This section describes the normative and informative AUX Channel physical layer tests and inrush
tests for compliance verification of DisplayPort1.2 source and sink.
6
DisplayPort 1.2 AUX Channel Tests
Overview
Test Point for AUX Channel Tests
You must test the Source devices at Test Point 2 (TP2) while the Sink devices must be tested at Test
Point 3 (TP3). See Figure 32.
Figure 32
Test Point Connections for AUX Channel Tests
Table 39 defines the test point fixtures and instruments used for AUX Channel Tests:
Table 39
Test Point Fixtures and Instruments for AUX Channel Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Stimulus
Stimulus must be applied to the DUT to cause AUX Channel transactions to occur. This
stimulus shall not be included in or affect the measurements.
Reference Sink needed as stimulus for the Source DUT:
• Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Reference Source needed as stimulus for the Sink DUT:
• Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 AUX Channel Tests
Perform the following steps before you run the compliance tests on the source device:
232
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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6
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 33).
Figure 33
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Setting Up for AUX PHY and Inrush Tests
Perform the following steps before you run the Auxiliary Channel and Inrush tests on the source or
sink device:
1
After you select AUX PHY and Inrush Tests, click the Test Setup button on the Set Up tab.
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2
On the DUT/Connectivity page, select Source or Sink in the DUT Type area. In the Reference Device
area, select Yes if a reference sink/source is attached to device under test during testing. Click
Next.
3
On the Connection Setup page, depending on the probe connection you are using, select either
Differential Probe or Single-Ended in the Connection Type area and in the Connection area, select the
Oscilloscope channel that is connected to the Auxiliary Lane.
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6
On the Trigger Setup page, define the Oscilloscope parameters to trigger on an Auxiliary signal
during testing.
Hold Off Time — The Oscilloscope minimum hold off time before triggering the next waveform. Note
that any Auxiliary transaction from the source must receive a reply from the sink in 400 us, else such
a transaction is considered a timeout. Hold off time, in such cases, represents the minimum idle time
before each AUX transaction is initialized. It is defaulted to 300 us which is a safe timing value for
most devices tested in the lab. Most devices respond much faster than 300 us.
Trigger Level — The AUX Channel signal level on which to trigger. Note that for a bi-directional signal
(where a reference sink is attached), you must set the trigger level such that it crosses both the
source command and the sink reply signal. Figure 34 and Figure 35 shows correct and incorrect trigger
levels.
Figure 34
Correct Trigger Level
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Figure 35
Incorrect Trigger Level
Vertical Scale — The Oscilloscope vertical scale. Set the vertical to make sure that all signals are
visible on the oscilloscope display.
Offset — Set the offset so that the center point is aligned with the center of the oscilloscope display.
Upper Threshold/Lower Threshold — The threshold level of signal must be set properly so that both
upper and lower thresholds cross both the source and sink signals when the DUT is attached with a
reference sink. The threshold levels are important parameters because they are used for edge
detection when decoding a source command from a sink reply. Figure 36 and Figure 37 shows correct
and incorrect threshold levels.
Figure 36
238
Correct Threshold set
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Figure 37
6
Wrong Thresholds set
c On the Trigger Setup page, you may click the Learn button, which guides you through getting
the trigger setup parameters. However, please note that the learning guide may not
necessarily work many a times because the actual Auxiliary signals may vary for different
manufacturers. Keysight recommends that you must check to make sure that the parameters
are correctly set as previously described.
d Click Verify and follow the instructions, if you wish to check the AUX Channel trigger.
e You may Save or Load the trigger setup configuration as a *.tsf file.
5
On the Acquisition Mode page, either Finish the setup wizard or enable Offline Mode, which is
de-selected, by default. Offline Mode lets you save the waveform files so that you can avoid the
manual process to initiate Auxiliary transactions during the time of test runs.
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6
If you enable Offline Mode, define the number of waveforms to be saved. If required, click Start
Acquisition to start capturing and saving waveforms.
7
Click Finish to close the setup wizard. The Set Up tab displays.
8
Click the Select Tests tab and select the AUX Channel tests you want to run.
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Probing/Connection Set Up for AUX Channel Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests. When performing the Source AUX
Channel tests, a Reference Sink device is required. Similarly, when performing the Sink AUX Channel
tests, a Reference Source device is required.
Figure 38
Sample connection diagram for source AUX channel tests with source DUT connected to a reference sink
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Figure 39
Sample connection diagram for source AUX channel tests without connecting to a reference sink
Figure 40
Sample connection diagram for sink AUX channel tests with sink DUT connected to a reference source
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AUX Channel Unit Interval Test
Test ID
125000 — AUX Channel Unit Interval Test (Source)
125010 — AUX Channel Unit Interval Test (Sink)
Test Overview
The objective of the test is to evaluate the AUX Channel waveform, ensuring that the overall variation
of the Manchester transaction Unit Interval stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Set up the parameter of the measurement trend:
a Set up the Unit Interval measurement for the differential AUX Channel signal.
b Set up the frequency measurement for the Clock signal.
c Set up the measurement trend.
6
Set up the waveform Histogram on the measurement trend:
a Initialize AUX Channel transactions and acquire the differential AUX Channel signal.
b Identify the first and the last points for the desired transaction.
c Zoom-in on the desired transaction.
d Set up the Vertical Waveform Histogram on the measurement trend within the desired
transaction.
e Obtain the measurement for the mean, maximum and minimum values of the waveform
Histogram.
7
Repeat step 6 ten times.
8
Report the measurement results.
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PASS Condition
Manchester Transaction Unit Interval (UIMAN):
Minimum = 0.4 µsec
Maximum = 0.6 µsec
Test References
See:
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured unit interval for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Test
Test ID
125001 — AUX Channel Eye Test (Source)
125011 — AUX Channel Eye Test (Sink)
Test Overview
The objective of this test is to evaluate the transmitter AUX Channel waveform, ensuring that the
timing variables and amplitude trajectories support the overall DP system objectives of the Bit Error
Rate in data transmission.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the waveform Histogram on the AUX Channel eye diagram to measure the left edge and
the right edge.
8
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Initialize the AUX Channel transaction and run the eye mask until 10 waveforms are folded.
9
Check for any signal trajectories entering into the mask.
10 Report the measurement results.
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PASS Condition
PASS Value = 290mV_diff_pp or higher
FAIL Value = lower than 290mV_diff_pp
Table 40
Eye Mask Vertices for AUX Channel for Manchester Transactions
Mask Point
Time (from EYE Center)
Minimum Voltage Value at Six Vertices (mV)
1
-185ns
0
2
-135ns
145
3
135ns
145
4
185ns
0
5
135ns
-145
6
-135ns
-145
Figure 41
AUX Channel EYE Mask for Manchester Transactions
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2.6, Figure 3-29 and Table 3-8
Expected/Observable Results
The measured eye diagram for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
The rendered eye diagram shall have no signal trajectories entering the mask area.
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AUX Channel Peak-to-Peak Voltage Test
Test ID
125002 — AUX Channel Peak-to-Peak Voltage Test (Source)
125012 — AUX Channel Peak-to-Peak Voltage Test (Sink)
Test Overview
The objective of the test is to evaluate the transmitter AUX Channel Waveform, ensuring that the
peak-to-peak voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform Histogram on the AUX Channel eye diagram to measure the left
edge and the right edge.
8
If you have selected the “AUX Channel Eye Test” under the Select Tests tab of the compliance
application:
a Set up the parameter of the Mask Test:
i
Load the eye mask based on the settings in the Configuration Variable.
ii
Center the eye mask at the middle of the eye diagram based on the measured left edge
and right edge.
iii Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
b Check for any signal trajectories entering into the mask.
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9
Set up the waveform histogram on the AUX Channel eye diagram.
a Set up the vertical waveform histogram on the AUX Channel eye diagram to measure the peak
to peak voltage.
10 Report the measurement results.
PASS Condition
Table 41
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage at a transmitting device (VAUX-DIFFp-p)
0.29V
1.38V
Test References
See:
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the transmitter AUX Channel signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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AUX Channel Eye Sensitivity Calibration Test
Test ID
125021 — AUX Channel Eye Sensitivity Calibration (Reference Sink)
125031 — AUX Channel Eye Sensitivity Calibration (Reference Source)
Test Overview
The objective of this test is to calibrate the peak-to-peak voltage of the transmitter AUX Channel
waveform by reference device (reference source or reference sink), ensuring that the peak-to-peak
voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
6
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
7
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
8
Set up the waveform Histogram on the AUX Channel eye diagram:
a Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
b Set up the vertical waveform Histogram of width 0.6 UI at the center of the AUX Channel eye
diagram.
c Measure the VTOP and VBASE using the waveform Histogram mean value.
9
Repeat Step 8 three times.
10 Report the measurement results.
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PASS Condition
Table 42
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage for AUX Channel Eye Sensitivity
0.24V
0.28V
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the AUX Channel signal by reference device (reference
source or reference sink) shall be within the conformance limits as specified in the specification
mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Sensitivity Test
Test ID
125041 — AUX Channel Eye Sensitivity Test (Source)
125051 — AUX Channel Eye Sensitivity Test (Sink)
Test Overview
The objective of the test is to evaluate the sensitivity to the AUX Channel Eye Opening of the DUT as
per the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
6
Check if the reference device could detect the transaction or not.
7
Decode the AUX Channel signal and check whether the transaction passed or failed.
8
Report the measurement results.
PASS Condition
Determine whether the AUX Channel communication is successful. For example, the Transmitter
DUT sends an AUX Request to the Reference Receiver. The Reference Receiver acknowledges and
the Transmitter DUT responds to the to indicate that the acknowledgment was successfully received.
PASS = No errors observed in the response
FAIL = One or more errors observed
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DisplayPort 1.2 AUX Channel Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured AUX Channel transaction shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Method of Implementation
7
DisplayPort 1.2 Inrush Tests
Overview / 254
Inrush Energy Power Test / 257
Inrush Peak Current Test / 259
7
DisplayPort 1.2 Inrush Tests
Overview
This section describes the normative and informative inrush tests for compliance verification of
DisplayPort1.2 source and sink, which is a power consumer.
Test Point for Inrush Tests
The test fixture for inrush tests implements the schematic shown in Figure 42.
Figure 42
Schematics for testing Power Consumer Device
The test fixture must be designed and used according to the following guidelines:
• A high gate voltage FET on the DP_PWR line is recommended to allow a fast connect
capability, which allows a single connection event for testing. Without such an arrangement,
multiple connections will be required to obtain a reasonable “worst-case” attachment event.
• Connection length between the power supply and the test fixture must be minimized. A
maximum of four inches is recommended.
• The power supply must have enough outrush capability as to not negatively affect the test
fixture’s outrush capability.
• The power supply must be run at 3.6V (3.3V + 10%) read across VC.
Any Power Consumer test fixture must be calibrated using the Power User test fixture, as shown in
Figure 42. Testing with the two fixtures combined should result in the approximate values given below.
If required, the component values on the Power Consumer test fixture should be adjusted to match
the expected results.
• VC steady before connection = 3.6V
• VC droop = ~3.1V
• Inrush Current = ~13.0A
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Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Inrush Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 43).
Figure 43
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests. Refer to “Setting Up for AUX PHY and
Inrush Tests" on page 235 to know in detail how to set up the DUT for Inrush Tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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DisplayPort 1.2 Inrush Tests
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Inrush Energy Power Test
Test ID
127000 — Inrush Energy Power Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
Power (Ps) = Id*Vs
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush energy power measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Energy ResultantPEAK_CURRENT_Power_Consumer < 13.5 Amps
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.5
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.2.3
Expected/Observable Results
The measured worst case inrush energy power for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Inrush Peak Current Test
Test ID
127001 — Inrush Peak Current Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
Power (Ps) = Id*Vs
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush peak current measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Energy ResultantPEAK_CURRENT_Power_Consumer < 13.5 Amps
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DisplayPort 1.2 Inrush Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.5
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.2.3
Expected/Observable Results
The measured worst case inrush peak current for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Compliance Test Application
Method of Implementation
8
DisplayPort 1.2 Dual Mode
Tests
Overview / 262
Setting Up for Dual Mode Tests / 265
Dual Mode TMDS Clock Duty Cycle Test / 269
Dual Mode TMDS Clock Jitter Test / 271
Dual Mode Eye Diagram Test / 273
Dual Mode Data Jitter Test / 276
Dual Mode Data Peak-Peak Differential Voltage Test / 278
Dual Mode Inter-Pair Skew Test / 280
Dual Mode Intra-Pair Skew Test / 282
8
DisplayPort 1.2 Dual Mode Tests
Overview
This section describes the normative and informative dual mode physical layer (differential and
single-ended) tests for compliance verification of DisplayPort1.2 DUTs.
Test Point
The source device for dual mode tests must be tested at Test Point 2 (TP2), as shown in Figure 44.
Figure 44
Test Point 2 Connection for Dual Mode Source Tests
Table 43 defines the test point fixtures and instruments used for DisplayPort 1.2 Dual Mode Tests:
Table 43
Test Point Fixtures and Instruments for DisplayPort 1.2 Dual Mode Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.2 Dual Mode Tests
Perform the following steps before you run the compliance tests on the source device:
262
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Dual Mode Tests
3
8
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 45).
Figure 45
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.2b Standards, select 1.2b from the drop-down options
in the Test Specification area and select Dual Mode Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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DisplayPort 1.2 Dual Mode Tests
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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8
Setting Up for Dual Mode Tests
Perform the following steps before you run the Auxiliary Channel and Inrush tests on the source or
sink device:
1
On the DisplayPort Compliance Test Application, click the Test Setup button on the Set Up tab.
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DisplayPort 1.2 Dual Mode Tests
2
266
On the Dual Mode Setup page, select Single-Ended or Differential Probe from the drop-down in the
Connection Type area. The option to select the number of oscilloscope channel connections is
grayed out if you select Single-Ended connection type. For Differential Probe, you may choose either
a 2-Channel or a 4-Channel setup. Select the clock frequency for Dual Mode signal in the Pixel
Clock Frequency area. Click Next to go to next page.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Dual Mode Tests
3
8
On the Channel Selection page, you may assign the data lanes, clock lanes and oscilloscope
channels to establish an SMA (Single-Ended) or Differential Probe connection. Click Finish.
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DisplayPort 1.2 Dual Mode Tests
Probing/Connection Set Up for Dual Mode Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 46
268
Sample Connection diagram for a 4-Channel Dual Mode Test
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DisplayPort 1.2 Dual Mode Tests
8
Dual Mode TMDS Clock Duty Cycle Test
Test ID
501 — Dual Mode TMDS Clock Duty Cycle (Min)
502 — Dual Mode TMDS Clock Duty Cycle (Max)
Test Overview
The objective of the test is to confirm that the duty cycle of the TMDS Clock waveform of a Source
DUT operating in dual mode does not exceed the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_CLOCK
Measurement Procedure
1
Acquire and verify the input TMDS Clock signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Scale the vertical display of the input TMDS Clock signal to optimum value.
c Measure VTOP and VBASE of the input TMDS Clock signal.
d Measure the Clock Frequency of the input TMDS Clock signal.
2
Generate FUNC4 signal, which is the differential signal of the TMDS Clock signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit Clock, input TMDS Clock signal).
4
Overlap the TMDS Clock signal to fold the differential signal of the TMDS Clock signal.
a Acquire the signal until 10,000 clock periods are folded.
5
Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the minimum and maximum duty cycle.
a The minimum duty cycle is measured as the earliest crossing of the TMDS Clock signal falling
edge.
b The maximum duty cycle is measured as the latest crossing of the TMDS Clock signal falling
edge.
6
Report the measurement results.
PASS Condition
PASS: 40% < TMDS_CLOCK duty cycle < 60%.
FAIL: TMDS_CLOCK duty cycle < 40% or TMDS_CLOCK duty cycle > 60%
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DisplayPort 1.2 Dual Mode Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.18
Expected/Observable Results
The measured duty cycle of the dual mode TMDS Clock signal shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
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8
Dual Mode TMDS Clock Jitter Test
Test ID
For 25MHz < TMDS Clock Frequency < 165MHz
• 503 — Dual Mode TMDS Clock Jitter
For TMDS Clock Frequency > 165MHz
• 803 — Dual Mode TMDS Clock Jitter
Test Overview
The objective of the test is to confirm that the TMDS Clock waveform of a Source DUT operating in
dual mode does not carry excessive jitter than that defined in the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_CLOCK
Measurement Procedure
1
Acquire and verify the input TMDS Clock signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Scale the vertical display of the input TMDS Clock signal to optimum value.
c Measure VTOP and VBASE of the input TMDS Clock signal.
d Measure the Clock Frequency of the input TMDS Clock signal.
2
Generate FUNC4 signal, which is the differential signal of the TMDS Clock signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit Clock, input TMDS Clock signal).
4
Overlap the TMDS Clock signal to fold the differential signal of the TMDS Clock signal.
a Acquire the signal until 400,000 clock periods are folded.
5
Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
6
Report the measurement results.
PASS Condition
For 25MHz < TMDS Clock Frequency < 165MHz
• PASS: Measured TMDS Clock Jitter < 0.20 Tbit and Data Jitter < 0.25 Tbit
For 165MHz < TMDS Clock Frequency < 300MHz
• PASS: Measured TMDS Clock Jitter < 120 ps and Data Jitter < 150 ps
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DisplayPort 1.2 Dual Mode Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.18
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured jitter of the dual mode TMDS Clock signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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8
Dual Mode Eye Diagram Test
Test ID
601, 602, 603 — Dual Mode Eye Diagram Testing
Test Overview
The objective of the test is to evaluate the waveform ensuring that the timing variables and
amplitude trajectories of a Source DUT operating in dual mode meets the specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
8
Measure the eye height of the eye diagram using the histogram.
9
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
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DisplayPort 1.2 Dual Mode Tests
10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
Figure 47
274
TMDS Data EYE Mask for TMDS Clock Frequencies from 25MHz to 165MHz
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Dual Mode Tests
Figure 48
8
TMDS Data EYE Mask for TMDS Clock Frequencies above 165MHz
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.19
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2, Figure 3-10 (for 25MHz <
TMDS Clock Frequency < 165MHz) and Figure 3-11 (for TMDS Clock Frequency > 165MHz)
Expected/Observable Results
The measured eye diagram for the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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DisplayPort 1.2 Dual Mode Tests
Dual Mode Data Jitter Test
Test ID
For 25MHz < TMDS Clock Frequency < 165MHz
• 611, 612, 613 — Dual Mode Data Jitter
For TMDS Clock Frequency > 165MHz
• 911, 912, 913 — Dual Mode Data Jitter
Test Overview
The objective of the test is to confirm that the data waveform of a Source DUT operating in dual
mode does not carry excessive jitter than that defined in the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
276
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.2 Dual Mode Tests
8
Measure the eye height of the eye diagram using the histogram.
9
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
8
10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
For 25MHz < TMDS Clock Frequency < 165MHz
• PASS: Measured TMDS Clock Jitter < 0.20 Tbit and Data Jitter < 0.25 Tbit
For 165MHz < TMDS Clock Frequency < 300MHz
• PASS: Measured TMDS Clock Jitter < 120 ps and Data Jitter < 150 ps
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.19
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured jitter of the dual mode data signal shall be within the conformance limits as specified
in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Dual Mode Tests
Dual Mode Data Peak-Peak Differential Voltage Test
Test ID
811, 812, 813 — Dual Mode Peak-Peak Differential Voltage (Min)
821, 822, 823 — Dual Mode Peak-Peak Differential Voltage (Max)
Test Overview
The objective of the test is to evaluate and confirm that the data waveform ensuring that the timing
variables and amplitude trajectories of a Source DUT operating in a dual mode meets the
specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
278
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
8
Measure the eye height of the eye diagram using the histogram.
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8
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies:
•
Minimum Peak-Peak Differential Voltage: 180mV
•
Maximum Peak-Peak Differential Voltage: 1380mV
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured peak-peak differential voltage of the dual mode data signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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DisplayPort 1.2 Dual Mode Tests
Dual Mode Inter-Pair Skew Test
Test ID
711 — D0/D1 - Dual Mode Inter Pair Skew Test
712 — D0/D2 - Dual Mode Inter Pair Skew Test
713 — D1/D2 - Dual Mode Inter Pair Skew Test
Test Overview
The objective of the test is to evaluate and confirm that the skew or time delay between differential
data lane of a Source DUT operating in a dual mode meets the specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input Lane A data signal.
c Verify the trigger and the amplitude of the input Lane B data signal.
d Scale the vertical display of the input TMDS Clock signal to optimum value.
e Scale the vertical display of the input Lane A data signal to optimum value.
f
Scale the vertical display of the input Lane B data signal to optimum value.
g Measure VTOP and VBASE of the input TMDS Clock signal.
h Measure VTOP and VBASE of the input Lane A data signal.
2
i
Measure VTOP and VBASE of the input Lane B data signal.
j
Measure the Clock Frequency of the input TMDS Clock signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
3
Set up the parameter of the Inter Pair Skew measurement.
a Set up two display grids such that each grid displays one test lane data signal.
b Set up the measurement threshold of each test lane data signal on the Transition Voltage =
0V.
c Decode the data signal for each test lane.
d Search the desired pattern from the decoded data signal.
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e Measure the time difference between the corresponding edges of both the test lanes using the
equation:
TTransition_LaneA - TTransition_LaneB
f
Repeat the previous step until you measure 100 edges.
g Calculate the Inter Pair Skew using the equation:
Inter Pair Skew = {1/Number of Edges} ∑ |TTransition_LaneA - TTransition_LaneB|
4
Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies, Inter-Pair Skew < 976 ps
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured inter pair skew of the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.2 Dual Mode Tests
Dual Mode Intra-Pair Skew Test
Test ID
701, 702, 703 — Dual Mode Intra Pair Skew Test
Test Overview
The objective of the test is to evaluate and confirm that the skew or time delay between the
respective sides of the differential data lane of a Source DUT operating in a dual mode meets the
specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
3
Set up the parameter to perform High Level Voltage (VHigh) and Low Level Voltage (VLow) for
each single-ended data signal:
a Scale the vertical display of the single-ended input data signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHigh by measuring the average voltage at 0.6UI to 0.75UI of the High level.
d Find VLow by measuring the average voltage at 0.6UI to 0.75UI of the Low level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHigh + VLow)/2
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8
Set up the parameter of the Intra Pair Skew measurement.
a Set up measurement threshold od each single-ended data signal based on the Transition
Voltage measured.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure the time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge using the equation:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure the time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) falling edge using the equation:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the Intra Pair Skew using the equation:
Intra Pair Skew = {1/Number of Edges} ∑ {[(D+Transition_High - D-Transition_Low) +
(D+Transition_Low - D-Transition_High)]/2}
5
Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies, Intra-Pair Skew < 60 ps
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured intra pair skew of the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Method of Implementation
9
DisplayPort 1.4 Source Tests
Overview / 286
Source Eye Diagram Test / 294
Source Total Jitter Test / 301
Source Non-ISI Jitter Test / 306
Source Non Pre-Emphasis Level Test / 311
Source Pre-Emphasis Level Test / 319
Source Non Transition Voltage Range Measurement Test / 327
Source Peak to Peak Voltage Test / 334
Source Inter-Pair Skew Test / 339
Source Main Link Frequency Compliance Test / 345
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test / 351
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test / 357
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative) / 363
Source Eye Diagram Test (TP3_EQ) / 369
Source Total Jitter Test (TP3_EQ) / 379
Source Non ISI Jitter Test (TP3_EQ) / 385
Source Deterministic Jitter Test (TP3_EQ) / 391
Source Random Jitter Test (TP3_EQ) / 397
Source AC Common Mode Test (Informative) / 402
Source Intra-Pair Skew Test (Informative) / 407
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DisplayPort 1.4 Source Tests
Overview
This section describes the normative and informative main link physical layer tests for compliance
verification of DisplayPort 1.4 source, sink and cable devices.
Test Point Definition for DisplayPort 1.4 Tests
Five different test points are identified for the physical layer measurement. See Figure 49.
Figure 49
Test Points in a DisplayPort InterConnect System
Table 44 defines the Test Points used for various DisplayPort 1.4 Tests:
Table 44
Test Points for DisplayPort Tests
Test Point
Description
TP1
At the pins of the Transmitter Device
TP2
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Source device
TP3
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Sink device
TP3_EQ
At TP3, when a defined cable model with equalizer is applied. There are two defined
cable models:
• Worst Cable Model as defined in VESA DisplayPort 1.4 Standard,
• Zero length, zero loss cable. The equalizer is also defined in VESA DisplayPort 1.4
Standard
TP4
At the pins of a receiving device
Cable Models
The two cable models defined in VESA DisplayPort 1.4 Standard are:
1
Worst Case Cable Model—To achieve the TP3_EQ signal with the worst case cable model:
•
Acquire the signal at TP2.
•
Embed the TP2 signal with a “worst case” HBR cable model using an InfiniiSim Waveform
Transformation Toolset software to emulate the insertion loss as defined in Figure 4-10 of the
VESA DisplayPort 1.4 Standard.
• For the DisplayPort Compliance Test Application, the “CIC_rev0p6.s4p” cable model transfer
function is used.
•
286
Finally, apply the HBR, HBR2 or HBR3 equalization using the Serial Data Equalization software as
defined in the VESA DisplayPort 1.4 Standard.
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2
Zero Length Cable Model—To achieve the TP3_EQ signal with the zero length cable model:
•
Acquire the signal at TP2.
•
No cable model is embedded for the Zero Length cable model.
•
Finally, apply the HBR, HBR2 or HBR3 equalization using the Serial Data Equalization software as
defined in the VESA DisplayPort 1.4 Standard.
Equalization
When equalization is required, use the CTLE (Continuous Time Linear Equalization) transfer function,
as given in the VESA DisplayPort 1.4 Standard.
For main link, use the CTLE model or the DFE model with the following transfer function for HBR (2.7
Gbps):
Figure 50
Transfer Function of the CTLE/DFE model for HBR
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Table 45
CTLE Model for HBR
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.725 GHz
0.725 GHz
Pole 1 Frequency
1.35 GHz
1.35 GHz
Pole 2 Frequency
2.5 GHz
2.5 GHz
For main link, use the CTLE model or the DFE model with the following transfer function for HBR2
(5.4 Gbps):
Figure 51
288
Transfer Function of the CTLE/DFE model for HBR2
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Table 46
9
CTLE Model for HBR2
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.64 GHz
0.64 GHz
Pole 1 Frequency
2.7 GHz
2.7 GHz
Pole 2 Frequency
4.5 GHz
4.5 GHz
Pole 3 Frequency
13.5 GHz
13.5 GHz
For main link, use the CTLE model or the DFE model with the following transfer function for HBR3
(8.1 Gbps):
Figure 52
Table 47
Transfer Function of the CTLE/DFE model for HBR3
CTLE Model for HBR3
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.640 GHz
0.640 GHz
Pole 1 Frequency
4.050 GHz
4.050 GHz
Pole 2 Frequency
10.0 GHz
10.0 GHz
HBR3 Reference DFE: The HBR3 Reference Equalizer includes a CTLE cascaded with a one-tap
adaptive DFE with a coefficient limited to less than 50mV. The DFE behavior is described as:
yk = xk - d1sgn(yk-1)
where, yk is the DFE differential output voltage, yk* is the decision function output voltage, xk
is the differential input voltage after CTLE, d1 is the feedback coefficient, k is the UI sample.
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A flowchart representing the HBR3 Reference Equalizer is shown in Figure 53.
Figure 53
Table 48
HBR3 Reference Equalizer based on the DFE
DFE Model for HBR3
DFE Parameter
Value
Number of Taps
1
DFE Mode
Auto
Eye Width
0.0 UI
Max Tap value
0.050
Min Tap value
0.0
Clock Recovery
When Clock Recovery is required, the clock recovery technique follows the definition of the receiver
PLL as defined in Section 3.5.2.5 of the VESA DisplayPort 1.4 Standard. For main link, use the
second-order clock recovery function with a closed loop tracking bandwidth and damping factor,
with respect to the PRBS7 pattern, as shown in Table 49:
Table 49
290
Main Link Second-Order Clock Recovery Function
Bit Rate
Band wid th
Damping Factor
HBR3 (8.1 Gbps)
15 MHZ
1.00
HBR2 (5.4 Gbps)
10 MHz
1.00
HBR (2.7 Gbps)
10 MHz
1.51
RBR (1.62 Gbps)
5.4 MHz
1.51
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Test Point Definition for DisplayPort 1.4 Source Tests
Test the Source DUT at Test Point 2 (TP2) as shown in Figure 54. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 54
Test Point 2 Connection for DisplayPort 1.4 Source Tests
Table 50 defines the test point fixtures and instruments used for DisplayPort 1.4 Source Tests:
Table 50
Test Point Fixtures and Instruments for DisplayPort 1.4 Source Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
• For DisplayPort Type-C Connector
• N7015A Type-C High-Speed Test Fixture
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 55).
Figure 55
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.4 Source Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 56
Sample connection diagram for DisplayPort 1.4 Source Tests
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DisplayPort 1.4 Source Tests
Source Eye Diagram Test
Test ID
For Standard DP Pattern:
•
1210001, 1210002, 1210003, 1210004 — Eye Diagram Test
For Arbitrary Pattern:
•
1310001, 1310002, 1310003, 1310004 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
294
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure VTOP and VBASE of the input signal using the pattern folding.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the input signal eye diagram to measure the left
edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the eye height of the eye diagram using the Histogram.
9
Measure the jitter of the eye diagram using the Histogram.
10 Calculate the eye width based on the measured jitter of the eye diagram.
11 Check for any signal trajectories that may have entered into the mask.
12 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 51 shows the voltage and time coordinates for the mask
used in the eye diagram.
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Table 51
9
Eye Diagram Mask Coord inates
Mask Point
Bit Rate
Red uced (1.62 Gb/s)
High (2.7 Gb/s)
1
0.127, 0.000
0.210, 0.000
2
0.291, 0.160
0.355, 0.140
3
0.500, 0.200
0.500, 0.175
4
0.709, 0.200
0.645, 0.175
5
0.873, 0.000
0.790, 0.000
6
0.709,-0.200
0.645,-0.175
7
0.500,-0.200
0.500,-0.175
8
0.291,-0.160
0.355,-0.140
Figure 57
The Source Eye Mask
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1.4, Section 3.5.2.8.2, Table 3-28 for RBR, Table 3-27 for
HBR
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Expected/Observable Results
The measured eye diagram for the source degraded signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Source Total Jitter Test
Test ID
For Standard DP Pattern:
•
1220001, 1220002, 1220003, 1220004 — Total Jitter Test
For Arbitrary Pattern:
•
1320001, 1320002, 1320003, 1320004 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
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DisplayPort 1.4 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Report the measurement results.
PASS Condition
Table 52
Total Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.294 UI
0.420 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.180 UI
0.270 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.7.2, Table 3-23
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Source Non-ISI Jitter Test
Test ID
For Standard DP Pattern:
•
1230001, 1230002, 1230003, 1230004 — Non ISI Jitter Test
For Arbitrary Pattern:
•
1330001, 1330002, 1330003, 1330004 — Non ISI Jitter Test
Test Overview
The objective of the test is to evaluate the amount of Non ISI jitter accompanying the data
transmission.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Non-ISI Jitter Test
306
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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DisplayPort 1.4 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Calculate the Non ISI jitter using the following equation:
Non ISI Jitter = TJ - ISI
7
Report the measurement results.
PASS Condition
Table 53
Non-ISI Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.260 UI
0.276 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.160 UI
0.170 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.11
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.7.2, Table 3-23
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Source Non Pre-Emphasis Level Test
Test ID
For Standard DP Pattern (RBR and HBR):
•
1261001, 1261002, 1261003, 1261004 — Non Pre-Emphasis Level Test (Swing 1/Swing 0)
•
1262001, 1262002, 1262003, 1262004 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263001, 1263002, 1263003, 1263004 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
For Standard DP Pattern (HBR2 and HBR3):
•
1264101, 1264102, 1264103, 1264104 — Non Pre-Emphasis Level Test (Swing 2/Swing 0)
•
1262101, 1262102, 1262103, 1262104 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263101, 1263102, 1263103, 1263104 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
For Arbitrary Pattern:
•
1364101, 1364102, 1364103, 1364104 — Non Pre-Emphasis Level Test (Swing 2/Swing 0)
•
1362101, 1362102, 1362103, 1362104 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1363101, 1363102, 1363103, 1363104 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
Test Overview
The objective of this test is to ensure that the system budget elements are obeyed and to ensure that
the level settings are monotonic so that the sink relies on the source to incrementally increase upon
request by the sink.
Test Conditions for Non Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR3 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
For Voltage Level A with no pre-emphasis level:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_Lvl0_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 58
High Voltage measurement for RBR and HBR
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Figure 59
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR3 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_Lvl0_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 60
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
316
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
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9
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_Lvl0_PP = VT_Lvl0_H - VT_Lvl0_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_Lvl0_PP = VN_Lvl0_H - VN_Lvl0_L
2
Repeat Step 1 for Voltage Level B with no pre-emphasis level.
3
Calculate the non pre-emphasis level output voltage ratio using the equation:
Non Pre-Emphasis Level = 20 * Log10[Voltage Level A VN_Lvl0_PP / Voltage Level B VN_Lvl0_PP]
4
Report the measurement results.
PASS Condition
For each level setting testes, the following equation should be used:
Resultant = 20 * Log10[VoltagePeak-Peak_LevelA / VoltagePeak-Peak_LevelB]
Table 54
Compared Levels
Measurement#
Vol tagePeak-Peak_LevelA
VoltagePeak-Peak_LevelB
1
Level 1 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
2
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
3*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
4
Level 2 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
5
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
6*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
RBR & HBR
HBR2 and HBR3
* if device optionally capable of Level 3
The resultants specifications are as identified below:
Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB
Measurement 3: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 4: 5.2 dB ≤ Resultant ≤ 6.9 dB
Measurement 5: 1.6 dB ≤ Resultant ≤ 3.5 dB
Measurement 6: 1 dB ≤ Resultant ≤ 4.4 dB
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Table 55
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-OUTPUT-RATIO_RBR_HBR*
Parameter
Min
Nom
Max
Unit
Ratio of Output Voltage
Level 1/Level 0
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 1
0.1
-
5.1
dB
Ratio of Output Voltage
Level 3/Level 2
0.8
-
6.0
dB
Comments
Measured on non-transition
bits at Pre-emphasis level 0
setting. Support for Voltage
Level 3 is optional.
* Earlier versions of DisplayPort have the Main-Link DPTX output voltage ratios to ensure that the DPTX supports the
required range of output voltage levels. For HBR2 and higher, you need not test or specify exclusively because
the compliance test point is moved to TP3_EQ. So, the ratio of output voltage levels is removed from the table
above for HBR2 and above.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured output voltage level ratio of the non pre-emphasis level test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Source Pre-Emphasis Level Test
Test ID
For Standard DP Pattern (RBR and HBR):
•
1270001, 1270002, 1270003, 1270004 — Pre-Emphasis Level Test
For Standard DP Pattern (HBR2 and HBR3):
•
1270501, 1270502, 1270503, 1270504 — Pre-Emphasis Level Test
For Arbitrary Pattern:
•
1370501, 1370502, 1370503, 1370504 — Pre-Emphasis Level Test
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Test Conditions for Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.4 Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR3— PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
For a given Voltage Level and a Pre-Emphasis Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 61
High Voltage measurement for RBR and HBR
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Figure 62
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR3 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 63
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
324
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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j
9
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
l
Calculate the pre-emphasis level using the equation:
Pre-EmphasisLvlX = 20 * Log10[VT_LvlX_PP / VN_LvlX_PP]
2
For Pre-Emphasis Level 0 (no pre-emphasis level), the result for Pre-EmphasisLvl0 is compared
with the maximum pre-emphasis disabled limit.
3
Repeat Step 1 for the next Pre-Emphasis level and for each Pre-Emphasis levels, compare the
pre-emphasis delta with the pre-emphasis delta limits.
4
Calculate the pre-emphasis delta using the equation:
Pre-Emphasis Delta (Level 1 vs Level 0) = Pre-EmphasisLvl1 - Pre-EmphasisLvl0
Pre-Emphasis Delta (Level 2 vs Level 1) = Pre-EmphasisLvl2 - Pre-EmphasisLvl1
Pre-Emphasis Delta (Level 3 vs Level 2) = Pre-EmphasisLvl3 - Pre-EmphasisLvl2
5
Report the measurement results.
PASS Condition
Pre-emphasis values for the Level 0 (OFF) state (Normative)
Level 0 (OFF) Pre-emphasis measurement:
Resultant = 20 * Log [VoltageT_Lvl0_PP / VoltageN_Lvl0_PP] for all supported levels.
Level 0 (OFF) Pre-emphasis Measurement condition: +0.25 dB > Resultant
Pre-emphasis Delta values for:
a Level 1 vs. Level 0 Pre-emphasis settings (NORMATIVE)
b Level 2 vs. Level 1 Pre-emphasis settings (NORMATIVE)
c Level 3 vs. Level 2 Pre-emphasis settings (NORMATIVE)
Pre-emphasis Delta measurements:
•
Level 1 vs. Level 0
Resultant = 20 * Log [VoltageT_Lvl1_PP / VoltageN_Lvl1_PP] - 20 * Log [VoltageT_Lvl0_PP /
VoltageN_Lvl0_PP] for Voltage Swing Levels 0, 1 and 2.
•
Level 2 vs. Level 1
Resultant = 20 * Log [VoltageT_Lvl2_PP / VoltageN_Lvl2_PP] - 20 * Log [VoltageT_Lvl1_PP /
VoltageN_Lvl1_PP] for Voltage Swing Levels 0 and 1.
•
Level 3 vs. Level 2
Resultant = 20 * Log [VoltageT_Lvl3_PP / VoltageN_Lvl3_PP] - 20 * Log [VoltageT_Lvl2_PP /
VoltageN_Lvl2_PP] for Voltage Swing Level 0, if supported.
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Table 56
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
VTX-PREEMP-OFF
Maximum Pre-emphasis
when disabled
-
-
0.25
dB
Delta of Pre-emphasis
Level 1 vs. Level 0
2
-
-
dB
Delta of Pre-emphasis
Level 2 vs. Level 1
1.6
-
-
dB
Delta of Pre-emphasis
Level 3 vs. Level 2
1.6
-
-
dB
VTX-PREEMP-DELTA
Min
Nom
Max
Unit
Comments
Pre-emphasis Level 0 setting
must not show any
pre-emphasis at TP2 to
prevent link training issues.
Applies to all valid voltage
settings. Measured at
Pre-emphasis Post Cursor2
Level 0.
Support for Pre-emphasis
Level 3 is optional.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured pre-emphasis level or pre-emphasis delta for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Source Non Transition Voltage Range Measurement Test
Test ID
For Standard DP Pattern (RBR and HBR):
•
1272001, 1272002, 1272003, 1272004 — Non Transition Voltage Range Measurement (Swing 0)
•
1273001, 1273002, 1273003, 1273004 — Non Transition Voltage Range Measurement (Swing 1)
•
1274001, 1274002, 1274003, 1274004 — Non Transition Voltage Range Measurement (Swing 2)
For Standard DP Pattern (HBR2 and HBR3):
•
1272101, 1272102, 1272103, 1272104 — Non Transition Voltage Range Measurement (Swing 0)
•
1273101, 1273102, 1273103, 1273104 — Non Transition Voltage Range Measurement (Swing 1)
•
1274101, 1274102, 1274103, 1274104 — Non Transition Voltage Range Measurement (Swing 2)
For Arbitrary Pattern:
•
1372101, 1372102, 1372103, 1372104 — Non Transition Voltage Range Measurement (Swing 0)
•
1373101, 1373102, 1373103, 1373104 — Non Transition Voltage Range Measurement (Swing 1)
•
1374101, 1374102, 1374103, 1374104 — Non Transition Voltage Range Measurement (Swing 2)
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Comparisons are also made for the Level 0 transition state as well as non-transition levels.
Test Conditions for Non-Transition Voltage Range Measurement Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.4 Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR3 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-Transition Voltage Range Measurement Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
For a given Voltage Level, repeat the following steps for all pre-emphasis levels subjected to
constraints specified in Table 3-1 of the VESA DisplayPort 1.4 Standard:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 64
High Voltage measurement for RBR and HBR
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Figure 65
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR3 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 66
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
332
i
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
j
Calculate the peak-to-peak value of the transition voltage using the equation:
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VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
2
Calculate the non transition voltage range using the equation:
Non Transition Voltage Range = Minimum [(VN_LvlX_PP) / (VN_Lvl0_PP)]
where, VN_LvlX_PP) refers to all supported pre-emphasis levels (Level1, Level2, Level3 and so on
up to Level X).
3
Report the measurement results.
PASS Condition
Non-Transition Voltage Range Measurements
For Level 2 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 1 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 0 voltage setting: Resultant > 0.85 OR 20*log(Resultant) > -1.4dB
Table 57
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-DIFF_REDUCTION
Parameter
Min
Nom
Max
Unit
Non-transition reduction
Output Voltage Level 2
-
-
3
dB
Non-transition reduction
Output Voltage Level 1
-
-
3
dB
Non-transition reduction
Output Voltage Level 0
-
-
1.4
dB
Comments
VTX-DIFF at each non-zero
nominal pre-emphasis level
must not be lower than the
specified amount less than
VTX-DIFF at the zero nominal
pre-emphasis level.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured output voltage level reduction of the non transition bit for the test signal shall be
within the conformance limits as specified in the specification mentioned under the “PASS Condition”
section for this test.
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Source Peak to Peak Voltage Test
Test ID
For Standard DP Pattern (RBR and HBR):
•
1266001, 1266002, 1266003, 1266004 — Peak to Peak Voltage Test
For Standard DP Pattern (HBR2 and HBR3):
•
1266101, 1266102, 1266103, 1266104 — Peak to Peak Voltage Test
For Arbitrary Pattern:
•
1366101, 1366102, 1366103, 1366104 — Peak to Peak Voltage Test
Test Overview
The objective of this test is to evaluate the maximum differential peak to peak voltage.
Test Conditions for Peak to Peak Voltage Test
334
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.4 Standard.
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR3 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Peak to Peak Voltage Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure the maximum and minimum voltage of the input signal.
4
Calculate the peak to peak voltage using the equation:
Peak to Peak Voltage = Maximum Voltage - Minimum Voltage
5
Report the measurement results.
PASS Condition
For all Data Rates:
Maximum Differential Peak to Peak Voltage < 1.38V.
Table 58
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
VTX-DIFFp-p_MAX
Max Output Voltage Level
-
Nom
-
Max
1.38
Unit
V
Comments
For all Output Level and
Pre-emphasis combinations.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured peak to peak voltage for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Inter-Pair Skew Test
Test ID
For Standard DP Pattern:
•
1290001 — Lane0/Lane1 Inter-Pair Skew Test
•
1290002 — Lane0/Lane2 Inter-Pair Skew Test
•
1290003 — Lane0/Lane3 Inter-Pair Skew Test
•
1290004 — Lane1/Lane2 Inter-Pair Skew Test
•
1290005 — Lane1/Lane3 Inter-Pair Skew Test
•
1290006 — Lane2/Lane3 Inter-Pair Skew Test
For Arbitrary Pattern:
•
Not applicable for arbitrary pattern
Test Overview
The objective of the test is to evaluate the skew or time delay between differential data lanes in the
DisplayPort interface.
Test Conditions for Inter Pair Skew Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest Bit Rate supported (RBR, HBR, HBR2 or HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
For two lane operation:
Lane 0 to Lane 1
For four lane operation:
Lane 0 to Lane 1
Lane 0 to Lane 2
Lane 0 to Lane 3
Lane 1 to Lane 2
Lane 1 to Lane 3
Lane 2 to Lane 3
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Inter Pair Skew Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
For a given inter-pair skew measurement of Lane A to Lane B:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the Lane A input signal.
ii
Scale the vertical display of the Lane A input signal to optimum value.
iii Measure VTOP and VBASE of the Lane A input signal.
iv Verify the trigger and the amplitude of the Lane B input signal.
v
Scale the vertical display of the Lane B input signal to optimum value.
vi Measure VTOP and VBASE of the Lane B input signal.
vii Measure the data rate of the Lane A input signal.
viii Measure the data rate of the Lane B input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
d Set up the parameter for the inter-pair skew measurement:
i
Set up two display grids such that each grid displays one test lane data signal.
ii
Set up the measurement threshold for each test lane data signal on the Transition
Voltage = 0V.
iii Decode the data signal for each test lane.
iv Search the desired pattern from the decoded data signal.
v
Measure the time difference between the corresponding edges of both test lanes:
TTransition_LaneA - TTransition_LaneB
vi Repeat the previous step until you measure 100 edges.
vii VESA DisplayPort 1.4 Standard specifies 20 UI offset Lane 0 to Lane 1, Lane 1 to Lane 2
and Lane 2 to Lane 3. The resultant offset is cumulative.
viii Calculate the inter-pair skew using the equation:
Inter-Pair Skew = {1/Number of Edges} ∑ |TTransition_LaneA - TTransition_LaneB| - Nominal Skew
where, Nominal Skew is the expected offset between tested lanes.
2
Report the measurement results.
PASS Condition
-1250ps < Inter-Lane Skew Tolerance < 1250ps
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Table 59
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
tTX-SKEW-INTER_PAIR
Parameter
Lane-to-Lane Output
Skew
Min
-
Nom
-
Max
1250
Unit
ps
Comments
Applies to transmitters capable
of 2- and 4-lane operation.
Also, applies to all pairwise
combinations of supported
lanes for all data rates.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.4
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured inter-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Source Main Link Frequency Compliance Test
Test ID
For Standard DP Pattern:
•
12193001 12193002 12193003 12193004 — Main Link Frequency Compliance
For Arbitrary Pattern:
•
13193001 13193002 13193003 13193004 — Main Link Frequency Compliance
Test Overview
The objective of this test is to ensure that the average data rate under all conditions does not exceed
the minimum and maximum values as set by the VESA DisplayPort 1.4 Standard.
Test Conditions for Main Link Frequency Compliance Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Main Link Frequency Compliance Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and the minimum measurement levels for the FUNC2 magnified unit
interval measurement trend.
d Set up two frequency measurement levels for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e For SSC Enabled Test condition, check the measured frequency to verify the existence of SSC
in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
For the test condition “SSC Enabled”, set up the parameter of the SSC measurement:
a Set up the memory depth and time-base to display one complete SSC cycle based on the
measured SSC modulation frequency in Step 5.
b Acquire the signal with one complete SSC cycle.
c Get the minimum of FUNC2 filtered unit interval measurement trend to calculate the maximum
data rate:
Maximum Data Rate = 1 / (Minimum Unit Interval)
d Get the maximum of FUNC2 filtered unit interval measurement trend to calculate the minimum
data rate:
Minimum Data Rate = 1 / (Maximum Unit Interval)
e Repeat steps b, c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rates.
10 Report the measurement results.
PASS Condition
Maximum Data Rate (Frequency Maxppm) < 300 ppm
Minimum Data Rate (Frequency Minppm) > -5300 ppm
Table 60
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Unit
fHBR3
Frequency for High
Bit Rate 3
8.05707
8.1
8.10243
Gbps
fHBR2
Frequency for High
Bit Rate 2
5.37138
5.4
5.40162
Gbps
fHBR
Frequency for High
Bit Rate
2.68569
2.7
2.70081
Gbps
fRBR
Frequency for
Reduced Bit Rate
1.611414
1.62
1.620486
Gbps
Comments
Frequency high limit =
+300ppm
Frequency low limit =
-5300ppm
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.15
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-17
Expected/Observable Results
The measured data rate for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID
For Standard DP Pattern:
•
12170001 12170002 12170003 12170004 — SSC Modulation Frequency Test
For Arbitrary Pattern:
•
13170001 13170002 13170003 13170004 — SSC Modulation Frequency Test
Test Overview
The objective of this test is to evaluate the frequency of the SSC modulation and to validate that the
frequency is within specification limits. This test includes the use of the 2nd order Butterworth
low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of
10 full SSC cycles. Calculate the SSC modulation frequency from the average of the measured SSC
modulation frequency for each cycle.
Test Conditions for SSC Modulation Frequency Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR3)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Frequency Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Source Tests
9
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
g Acquire the signal for 10 SSC Cycles.
6
Get the mean value for the SSC Modulation frequency.
7
Report the measurement results.
PASS Condition
30kHz < SSC Modulation Frequency (fSSC) < 33kHz
Table 61
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Down_Spread_Frequency
Link clock down-spreading
frequency
30
-
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Unit
kHz
Comments
Range: 30kHz ~ 33kHz when
down-spread enabled
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.15
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-17
Expected/Observable Results
The measured SSC modulation frequency for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID
For Standard DP Pattern:
•
12180001 12180002 12180003 12180004 — SSC Modulation Deviation Test
For Arbitrary Pattern:
•
13180001 13180002 13180003 13180004 — SSC Modulation Deviation Test
Test Overview
The objective of this test is to evaluate the range of SSC down-spreading of the transmitter signal in
ppm and to validate that the values are within specification limits. This test includes the use of the
2nd order Butterworth low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is
conducted over a minimum of 10 full SSC cycles. For each cycle, the minimum and maximum data
rate is evaluated. Calculate the SSC modulation deviation from the average of the maximum minus
the average of the minimum using the equation:
SSC Modulation Deviation = {[Average (Maximum Data Rate) - Average (Minimum Data Rate)] /
Nominal Data Rate}*1e6
Test Conditions for SSC Modulation Deviation Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR3)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Deviation Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and minimum measurements for the FUNC2 magnified unit interval
measurement trend.
d Set up two frequency measurements for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e Check the measured frequency to verify the existence of SSC in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point for three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 filtered unit interval measurement
trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurements for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
Set up the parameters for SSC measurement.
a Set up memory depth and time-base to display one complete SSC Cycle based on the
measured SSC modulation frequency in step 5.
b Acquire the signal with one complete SSC Cycle.
c Get the minimum of the FUNC2 filtered unit interval measurement trend to calculate the
maximum data rate:
Maximum Data Rate = 1/Minimum Unit Interval
d Get the maximum of the FUNC2 filtered unit interval measurement trend to calculate the
minimum data rate:
Minimum Data Rate = 1/Maximum Unit Interval
e Repeat step b,c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rate.
10 Calculate the SSC Modulation Deviation using the equation:
SSC Modulation Deviation = (Maximum Data Rate - Minimum Data Rate) / (Nominal Data
Rate) * 1E6
11 Report the measurement results.
PASS Condition
-5000ppm < SSC Modulation Deviation (ResultantSSC Range) < 0ppm
Table 62
DisplayPort Main Link Transmitter System Parameters
Symbol
Parameter
Min
Nom
Max
Down_Spread_Amplitude
Link clock down-spreading
0
-
0.5
Unit
%
Comments
Range: 0% ~ 0.5% when
down-spread enabled
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.16
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-17
Expected/Observable Results
The measured SSC modulation deviation for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID
For Standard DP Pattern:
•
12200001 12200002 12200003 12200004 — SSC Deviation HF Variation Test (Informative)
For Arbitrary Pattern:
•
13200001 13200002 13200003 13200004 — SSC Deviation HF Variation Test (Informative)
Test Overview
The objective of this test is to verify that the SSC profile does not include any frequency deviation
that may exceed 1250 ppm/µsec. This test includes the use of the 2nd order Butterworth low-pass
filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of 10 full
SSC cycles.
Test Conditions for SSC Deviation HF Variation Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR3)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Deviation HF Variation Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
6
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
Set up the parameters for the SSC measurement.
a Set up memory depth and time-base to display one complete SSC cycle using the measured
SSC Modulation Frequency in Step 5.
b Acquire the signal with one complete SSC Cycles.
c Read the FUNC2 filtered unit interval measurement trend.
d Compute the slope using the “Sliding Window” with 1.00 µsec window width. Calculate the
slope using the equation:
Slope = [f(t) - f(t-1.00 µsec)/1.00 µsec
e Repeat step b, c and d until you acquire 10 SSC Cycles.
f
7
Get the maximum value for the computed value of slope.
Report the measurement results.
PASS Condition
SSCt dF/dt < 1250ppm/µsec
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.17
Expected/Observable Results
The measured SSC deviation high frequency variation for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Source Eye Diagram Test (TP3_EQ)
Test ID
For Standard DP Pattern (HBR):
•
1211001, 1211002, 1211003, 1211004 — Eye Diagram Test (TP3_EQ) - PRBS7
•
1211011, 1211012, 1211013, 1211014 — Eye Diagram Test with No Cable Model (TP3_EQ) PRBS7
For Standard DP Pattern (HBR2 and HBR3):
•
1215001, 1215002, 1215003, 1215004 — Eye Diagram Test (TP3_EQ) - HBR2CPAT
•
1215011, 1215012, 1215013, 1215014 — Eye Diagram Test with No Cable Model (TP3_EQ) HBR2CPAT
For Arbitrary Pattern:
•
1315001, 1315002, 1315003, 1315004 — Eye Diagram Test (TP3_EQ)
•
1315011, 1315012, 1315013, 1315014 — Eye Diagram Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the waveform, ensuring that the timing variables and
amplitude trajectories support the overall DP system objectives of the Bit Error Rate in data
transmission.
Test Conditions for Eye Diagram Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR (Informative), HBR2 and HBR3
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
HBR — Level 2
HBR2, HBR3 — Any Voltage Level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
HBR — Level 0
HBR2, HBR3 — Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
HBR — Level 0
HBR2, HBR3 — Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes supported
Test Pattern
HBR — PRBS7
HBR2 — HBR2CPAT
HBR3 — TPS4
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure for HBR
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the jitter of the eye diagram using the Histogram.
9
Check for any signal trajectories that may have entered into the mask.
10 Report the measurement results.
Measurement Procedure for HBR2 and HBR3
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
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4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Pattern fold the equalized signal based on the High Level Voltage (VHIGH) random noise
configuration variable.
b Set up the vertical waveform histogram on the equalized signal to measure random noise of
High Level Voltage (VHIGH).
c Measure the High Level Voltage (VHIGH) random noise based on the standard deviation of the
waveform histogram.
d Pattern fold the equalized signal based on the Low Level Voltage (VLOW) random noise
configuration variable.
e Set up the vertical waveform histogram on the equalized signal to measure the random noise
of Low Level Voltage (VLOW).
f
Measure the Low Level Voltage (VLOW) random noise based on the standard deviation of the
waveform histogram.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge and right edge.
8
Set up the vertical waveform histogram on the equalized signal eye diagram to measure the eye
height from 0.375 UI to 0.625 UI.
9
Find the maximum eye height location of the eye diagram.
10 If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Set up the parameter of the jitter separation using the EZJIT Plus/Complete Software.
i
Load the jitter separation parameter into EZJIT Plus/Complete Software based on the
settings in the Configuration Variable.
ii
Acquire the signal until 1,000,000 edges are analyzed.
b Note the value of the jitter component from the EZJIT Plus/Complete Software.
11 Create the eye mask based on the following criteria:
a If you select more than one lane (2 lanes or 4 lanes DUT configuration), the eye mask height
and width is derate in the following manner, to include crosstalk as defined in DisplayPort 1.4
Compliance Test Specification:
i
Eye Mask Width Derate (Crosstalk) = 0.04 UI
ii
Eye Mask Height Derate (Crosstalk) = 0.014V
b If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]: eye mask height and width is derate as below to comprehend the
noise/jitter extrapolated to BER 10-9 for an Eye Diagram Test (TP3_EQ) only acquiring 1e6 UI:
i
Calculate the Eye Mask Width Derate (Random Jitter) using the equation:
Eye Mask Width Derate (Random Jitter) = 2.5 * Random Jitterrms
ii
Calculate the Eye Mask Height Derate (Random Noise) using the equation:
VHIGH Eye Mask Height Derate (Random Noise) = 2.5 * VHIGH Random Noiserms
VLOW Eye Mask Height Derate (Random Noise) = 2.5 * VLOW Random Noiserms
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NOTE
9
The factor 2.5 is the delta between BER 10-6 (9.507) and 10-9 (11.996) to
comprehend the noise/jitter extrapolated to BER 10-9 as the Eye Diagram
Test (TP3_EQ) only acquiring 1e6 UI.
BER
N
10-6
9.507
10-7
10.399
10-8
11.224
10-9
11.996
c Place the eye mask height at the point of the maximum eye height found in Step 9.
d Calculate the Eye Mask Width:
Eye Mask Width = Eye Width Specification (0.38 UI) + Eye Mask Width Derate (Crosstalk) + 2 *
Eye Mask Width Derate (Random Jitter)
e Calculate the Eye Mask Height:
Eye Mask Height = {Eye Height Specification (0.09 UI) + Eye Mask Height Derate (Crosstalk)}/2
+ VHIGH Eye Mask Height Derate (Random Noise)
Eye Mask Height = -{Eye Height Specification (0.09 UI) + Eye Mask Height Derate
(Crosstalk)}/2 - VLOW Eye Mask Height Derate (Random Noise)
12 Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram.
c Run the eye mask until 1,000,000 UI are folded.
13 Measure the eye height of the eye diagram using the Histogram.
14 Measure the jitter of the eye diagram using the Histogram.
15 Calculate the eye width based on the measured jitter of the eye diagram.
16 Check for any signal trajectories that may have entered into the mask.
17 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 63 shows the voltage and time coordinates for the mask
used for the eye diagram.
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Table 63
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 67
376
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Source Tests
Table 64
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Table 65
Eye Diagram Mask Coord inates for TP3_EQ (HBR3)
Mask Point
Figure 68
9
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.35UI
0.00000
2
Any passing UI location between 0.375 and 0.625UI
0.00375
3
Point 1 + 0.35UI
0.00000
4
Same as Point 2
-0.00375
The Eye Mask at TP3_EQ (HBR2 and HBR3)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.8.1, Table 3-29 for HBR, Table 3-25
for HBR2 and Table 3-24 for HBR3
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Expected/Observable Results
The measured eye diagram for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Source Total Jitter Test (TP3_EQ)
Test ID
For Standard DP Pattern:
•
1222001, 1222002, 1222003, 1222004 — Total Jitter Test (TP3_EQ) - HBR2CPAT
•
1222011, 1222012, 1222013, 1222014 — Total Jitter Test with No Cable Model (TP3_EQ) HBR2CPAT
•
1221001, 1221002, 1221003, 1221004 — Total Jitter Test (TP3_EQ) - D10.2
•
1221011, 1221012, 1221013, 1221014 — Total Jitter Test with No Cable Model (TP3_EQ) - D10.2
For Arbitrary Pattern:
•
1322001, 1322002, 1322003, 1322004 — Total Jitter Test (TP3_EQ)
•
1322011, 1322012, 1322013, 1322014 — Total Jitter Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2, HBR3
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes supported
Test Pattern
HBR2CPAT and D10.2
HBR3: TPS4
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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9
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 66
Total Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 3 (8.1 Gb/s per lane)
0.65 UI
Ap-p
High-Bit Rate 2 (5.4 Gb/s per lane)
0.580 UI*
Ap-p
* The HBR2 limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
Table 67
Total Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) and High-Bit Rate 3 (8.1 Gb/s per lane)
Ap-p
0.40 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.7.2, Table 3-23
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-19
Expected/Observable Results
The measured total jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Non ISI Jitter Test (TP3_EQ)
Test ID
For Standard DP Pattern:
•
1231001, 1231002, 1231003, 1231004 — Non ISI Jitter Test (TP3_EQ) - HBR2CPAT
•
1231011, 1231012, 1231013, 1231014 — Non ISI Jitter Test with No Cable Model (TP3_EQ) HBR2CPAT
For Arbitrary Pattern:
•
1331001, 1331002, 1331003, 1331004 — Non ISI Jitter Test (TP3_EQ)
•
1331011, 1331012, 1331013, 1331014 — Non ISI Jitter Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the non ISI jitter accompanying the data transmission.
Test Conditions for Non ISI Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR3
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes supported
Test Pattern
TPS4
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non ISI Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Calculate the non ISI jitter base on following equation:
Non ISI Jitter = TJ - ISI
8
Report the measurement results.
PASS Condition
Table 68
Non ISI Jitter at TP3_EQ
Receiver Connector (TP3_EQ)
High-Bit Rate 3 (8.1 Gb/s per lane)
Ap-p
0.41 UI
UI is Unit Interval.
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Test References
See:
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.7.2, Table 3-23
Expected/Observable Results
The measured non ISI jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Deterministic Jitter Test (TP3_EQ)
Test ID
For Standard DP Pattern:
•
1236001, 1236002, 1236003, 1236004 — Deterministic Jitter Test (TP3_EQ) - HBR2CPAT
•
1236011, 1236012, 1236013, 1236014 — Deterministic Jitter Test with No Cable Model (TP3_EQ)
- HBR2CPAT
•
1235001, 1235002, 1235003, 1235004 — Deterministic Jitter Test (TP3_EQ) - D10.2
•
1235011, 1235012, 1235013, 1235014 — Deterministic Jitter Test with No Cable Model (TP3_EQ)
- D10.2
For Arbitrary Pattern:
•
1336001, 1336002, 1336003, 1336004 — Deterministic Jitter Test (TP3_EQ)
•
1336011, 1336012, 1336013, 1336014 — Deterministic Jitter Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the deterministic jitter accompanying the data transmission.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes supported
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Deterministic Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 69
Deterministic Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.49 UI
Ap-p
Table 70
Deterministic Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.27 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2.7.2, Table 3-23
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-19
Expected/Observable Results
The measured deterministic jitter for the test signal at TP3_EQ shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Random Jitter Test (TP3_EQ)
Test ID
For Standard DP Pattern:
•
1238001, 1238002, 1238003, 1238004 — Random Jitter Test (TP3_EQ) - D10.2
•
1238011, 1238012, 1238013, 1238014 — Random Jitter Test with No Cable Model (TP3_EQ) D10.2
For Arbitrary Pattern:
•
1338001, 1338002, 1338003, 1338004 — Random Jitter Test (TP3_EQ) - D10.2
•
1338011, 1338012, 1338013, 1338014 — Random Jitter Test with No Cable Model (TP3_EQ) D10.2
Test Overview
The objective of this test is to evaluate the random jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. The jitter is
separated into each jitter components and the random jitter is estimated to 10-9 BER based on the
Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Random Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
All test lanes supported
Test Pattern
D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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DisplayPort 1.4 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests and Data Pattern: as either Standard DP
Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Random Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 71
Random Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.13 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-19
Expected/Observable Results
The measured random jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.4 Source Tests
Source AC Common Mode Test (Informative)
Test ID
For Standard DP Pattern:
•
12110001, 12110002, 12110003, 12110004 — AC Common Mode Test (Informative)
For Arbitrary Pattern:
•
13110001, 13110002, 13110003, 13110004 — AC Common Mode Test (Informative)
Test Overview
The objective of this test is to evaluate the AC Common Mode noise (unfiltered rms) of the differential
data line of the DP interface.
Test Conditions for AC Common Mode Test (Informative)
402
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR3)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported subject to the constraints in Table 3-1 of the VESA
DisplayPort 1.4 Standard
Post-Cursor2 Level
Level 0
Test Lane
All test lanes are supported
Test Pattern
PRBS7
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests and Data Pattern: as either Standard
DP Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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DisplayPort 1.4 Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for AC Common Mode Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
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DisplayPort 1.4 Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Create FUNC3 signal, which is the common mode signal of the input single-ended signal.
4
If the filter is enabled [“Filter” configuration variable set to “High Pass Filter”, “Low Pass Filter” or
“None” (Default)]:
a Create FUNC4 signal, which is the filtered FUNC3 signal by applying the High Pass filter or
Low Pass filter on the FUNC3 signal based on the Configuration Variable.
5
6
Set up two display grids such that one grid displays the input single-ended signal while the other
grid displays the common mode signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
7
Set up the parameters for RMS voltage measurement of the common mode signal.
a Set up the Vrms measurement for the common mode signal.
b Acquire the signal until 100,000 edges are measured.
8
Get the mean for the Vrms measurement.
9
Report the measurement results.
PASS Condition
For RBR and HBR:
AC Common Mode Voltage < 20mV
For HBR2 and HBR3:
AC Common Mode Voltage < 30mV
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.10
• VESA DisplayPort (DP) Standard Version 1.4, Section D.2, Table D-3
Expected/Observable Results
The measured AC common mode noise for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Intra-Pair Skew Test (Informative)
Test ID
For Standard DP Pattern:
•
12100001, 12100002, 12100003, 12100004 — Intra-Pair Skew Test (Informative)
For Arbitrary Pattern:
•
13100001, 13100002, 13100003, 13100004 — Intra-Pair Skew Test (Informative)
Test Overview
The objective of this test is to evaluate the skew or time delay between respective sides of a
differential data lane in the DP interface.
Test Conditions for Intra-Pair Skew Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR3)
SSC
Both SSC conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
For one lane operation:
Lane 0+ to Lane 0For two lane operation:
Lane 0+ to Lane 0Lane 1+ to Lane 1For four lane operation:
Lane 0+ to Lane 0Lane 1+ to Lane 1Lane 2+ to Lane 2Lane 3+ to Lane 3-
Test Pattern
D10.2
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DisplayPort 1.4 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests and Data Pattern: as either Standard
DP Pattern (selected by default) or Arbitrary Pattern (if you have a DisplayPort Test Pattern with
specifications different from the standards).
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Intra-Pair Skew Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Source Tests" on page 291
to complete the task flow for DUT setup along with configuring the Compliance Application to
run the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
4
Set up the parameters to perform High Level Voltage (VHIGH) and Low Level Voltage (VLOW) for
each input single-ended signal.
a Scale the vertical display of the input single-ended signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHIGH by measuring the average voltage at 0.06 UI to 0.75 UI of the High Level.
d Find VLOW by measuring the average voltage at 0.06 UI to 0.75 UI of the Low Level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHIGH + VLOW) / 2
5
Set up the parameters for the intra-pair skew measurement:
a Set up the measurement threshold for each single-ended data signal based on the measured
Transition Voltage.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) rising edge:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the intra-pair skew using the equation:
Intra-Pair Skew = {1/Number of Edges}
∑ {[(D+Transition_High - D-Transition_Low) + (D+Transition_Low - D-Transition_High)] / 2}
6
Report the measurement results.
PASS Condition
Intra-Pair skew ≤ 30 ps
Test References
See:
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9
DisplayPort 1.4 Source Tests
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.5
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.5.2, Table 3-18
Expected/Observable Results
The measured intra-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Method of Implementation
10 DisplayPort 1.4 Sink Tests
Overview / 414
Sink Eye Diagram Test / 419
Sink Total Jitter Test / 427
Sink Non-ISI Jitter Test / 433
10
DisplayPort 1.4 Sink Tests
Overview
Test Point Definition for DisplayPort 1.4 Sink Tests
NOTE
Sink Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Sink DUT at Test Point 3(TP3) as shown in Figure 69. Unless specifically stated under the Test
Conditions, all supported lanes for the DUT shall be evaluated:
Figure 69
Test Point 3 Connection for DisplayPort 1.4 Sink Tests
Table 72 defines the test point fixtures and instruments used for DisplayPort 1.4 Sink Tests:
Table 72
414
Test Point Fixtures and Instruments for DisplayPort 1.4 Sink Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
10
Calibration of Stress Signal
For the calibration of the stress signal, you must test the stress signal in the manner shown in the
Figure 70 for RBR and Figure 71 for HBR and HBR2.
Figure 70
Test Point 3 Connection for Stress Signal Calibration of RBR
Figure 71
Test Point 3 Connection for Stress Signal Calibration of HBR and HBR2
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Table 73 defines the Test Point 3 Connections for Stress Signal Calibration:
Table 73
Test Point Connections for Stress Signal Calibration
Test Requirement
Device Used
Stress Signal Generator (SSG)
Bit Error Rate Tester
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Jitter Measurement Device (JMD)
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Sink Tests
Perform the following steps before you run the compliance tests on the sink device:
416
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
3
10
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 72).
Figure 72
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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DisplayPort 1.4 Sink Tests
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.4 Sink Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 73
418
Sample connection diagram for DisplayPort 1.4 Sink Tests
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
10
Sink Eye Diagram Test
Test ID
12140001, 12140002, 12140003, 12140004 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the following specifications for degradation:
• Voltage Level:
•
90mV peak to peak +/- 10% for HBR2 at TP3_EQ (Table 3-18, DP1.2a)
•
150mV peak to peak +/- 10% for HBR at TP3_EQ (Table 3-25, DP1.2a)
•
46mV peak to peak +/- 10% for RBR at TP3 (Table 3-26, DP1.2a
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Eye Diagram Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR3—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR, HBR2 and HBR3)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR3—HBR2CPAT
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DisplayPort 1.4 Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: and Data Pattern: automatically gray out.
c Click Next.
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10
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Sink Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Sink Tests" on page 416 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 74 shows the voltage and time coordinates for the mask
used for the eye diagram.
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DisplayPort 1.4 Sink Tests
Table 74
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 74
424
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
Table 75
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Table 76
Eye Diagram Mask Coord inates for TP3_EQ (HBR3)
Mask Point
Figure 75
10
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.35UI
0.00000
2
Any passing UI location between 0.375 and 0.625UI
0.00375
3
Point 1 + 0.35UI
0.00000
4
Same as Point 2
-0.00375
The Eye Mask at TP3_EQ (HBR2 and HBR3)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
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DisplayPort 1.4 Sink Tests
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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DisplayPort 1.4 Sink Tests
10
Sink Total Jitter Test
Test ID
12210001, 12210002, 12210003, 12210004 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR3—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR, HBR2 and HBR3)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR3—HBR2CPAT
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10
DisplayPort 1.4 Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: and Data Pattern: automatically gray out.
c Click Next.
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DisplayPort 1.4 Sink Tests
10
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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DisplayPort 1.4 Sink Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Sink Tests" on page 416 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
10
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 77
Total Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
0.580 UI*
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI limit in DisplayPort 1.2a Standard.
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DisplayPort 1.4 Sink Tests
Table 78
Total Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Sink Non-ISI Jitter Test
Test ID
12220001, 12220002, 12220003, 12220004 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR3—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR, HBR2 and HBR3)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR3—HBR2CPAT
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10
DisplayPort 1.4 Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: and Data Pattern: automatically gray out.
c Click Next.
434
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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10
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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10
436
DisplayPort 1.4 Sink Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Sink Tests" on page 416 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Sink Tests
10
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 79
Non ISI Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
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DisplayPort 1.4 Sink Tests
Table 80
Non ISI Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Compliance Test Application
Method of Implementation
11 DisplayPort 1.4 Cable Tests
Overview / 440
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Cable Total Jitter Test / 450
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11
DisplayPort 1.4 Cable Tests
Overview
Test Point Definition for DisplayPort 1.4 Cable Tests
NOTE
Cable Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Cable DUT at Test Point 3 (TP3) as shown in Figure 76. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 76
440
Test Point 3 Connection for DisplayPort 1.4 Cable Tests
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Cable Tests
11
Table 81 defines the test point fixtures and instruments used for DisplayPort 1.4 Cable Tests:
Table 81
Test Point Fixtures and Instruments for DisplayPort 1.4 Cable Tests
Test Requirement
Device Used
Stimulus Instrument
Pulse Pattern Generator
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Table 82 defines the input signal parameters applied by the stimulus instrument at TP2:
Table 82
Input Signal Parameters by Stimulus Instrument
RBR
•
•
•
•
Reference Table 3-22 and Table 3-24, DP 1.2a
Edge Rate (20-80): 155-165ps (260mUI)
Eye Height: 400mV
Total Jitter: 270mUI
• ISI: 100mUI
• Random Jitter (rms): 7.9mUI
• Sinusoidal Jitter: ~75mUI at 20MHz (Adjust to achieve Total Jitter)
HBR
•
•
•
•
Reference Table 3-22 and Table 3-23, DP 1.2a
Edge Rate (20-80): 90-100ps (260mUI)
Eye Height: 350mV
Total Jitter: 420mUI
• ISI: 144mUI
• Random Jitter (rms): 13.2mUI
• Sinusoidal Jitter: ~117mUI at 20MHz (Adjust to achieve Total Jitter)
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DisplayPort 1.4 Cable Tests
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Cable Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 77).
Figure 77
442
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for DisplayPort 1.4 Cable Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 78
Sample connection diagram for DisplayPort 1.4 Cable Tests
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Cable Eye Diagram Test
Test ID
12150001, 12150002, 12150003, 12150004 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
444
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 82
Crosstalk Signal Parameter
Quarter-rate clock signal (D24.3 pattern) is injected to lanes other than the lane under
test. The characteristics of the aggressor signals are:
Pattern—D24.3
Bit Rate—(Same as lane under test)
Voltage Amplitude—(Same as lane under test)
• RBR-400mV
• HBR-350mV
Edge Rate (20-80)—130ps at TP3
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: and Data Pattern: automatically gray out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Cable Eye
Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Cable Tests" on page 442 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 83 shows the voltage and time coordinates for the mask
used for the eye diagram.
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Table 83
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Figure 79
11
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
The Cable Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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Cable Total Jitter Test
Test ID
12230001, 12230002, 12230003, 12230004 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
450
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 82
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: and Data Pattern: automatically gray out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Cable Total
Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Cable Tests" on page 442 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 84
Total Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Cable Non-ISI Jitter Test
Test ID
12240001, 12240002, 12240003, 12240004 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non-ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. This
measurement is a data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
All test lanes supported
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 82
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: and Data Pattern: automatically gray out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Cable Non-ISI
Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Cable Tests" on page 442 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 85
Non ISI Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non-ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
12 DisplayPort 1.4 AUX Channel
Tests
Overview / 462
Setting Up for AUX PHY and Inrush Tests / 465
AUX Channel Unit Interval Test / 473
AUX Channel Eye Test / 475
AUX Channel Peak-to-Peak Voltage Test / 477
AUX Channel Eye Sensitivity Calibration Test / 479
AUX Channel Eye Sensitivity Test / 481
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DisplayPort 1.4 AUX Channel Tests
Overview
This section describes the normative and informative AUX Channel physical layer tests and inrush
tests for compliance verification of DisplayPort1.4 source and sink.
Test Point for AUX Channel Tests
You must test the Source devices at Test Point 2 (TP2) while the Sink devices must be tested at Test
Point 3 (TP3). See Figure 80.
Figure 80
Test Points for DisplayPort 1.4 AUX Channel Tests
Table 86 defines the test point fixtures and instruments used for DisplayPort 1.4 AUX Channel Tests:
Table 86
Test Point Fixtures and Instruments for DisplayPort 1.4 AUX Channel Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Stimulus
Stimulus must be applied to the DUT to cause AUX Channel transactions to occur. This
stimulus shall not be included in or affect the measurements.
Reference Sink needed as stimulus for the Source DUT:
• Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Reference Source needed as stimulus for the Sink DUT:
• Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 AUX Channel Tests
Perform the following steps before you run the compliance tests on the source device:
462
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 81).
Figure 81
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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DisplayPort 1.4 AUX Channel Tests
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Setting Up for AUX PHY and Inrush Tests
Perform the following steps before you run the Auxiliary Channel and Inrush tests on the source or
sink device:
1
After you select AUX PHY and Inrush Tests, click the Test Setup button on the Set Up tab.
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DisplayPort 1.4 AUX Channel Tests
2
On the DUT/Connectivity page, select Source or Sink in the DUT Type area. In the Reference Device
area, select Yes if a reference sink/source is attached to device under test during testing. Click
Next.
3
On the Connection Setup page, depending on the probe connection you are using, select either
Differential Probe or Single-Ended in the Connection Type area and in the Connection area, select the
oscilloscope channel that is connected to the Auxiliary Lane.
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On the Trigger Setup page, define the oscilloscope parameters to trigger on an Auxiliary signal
during testing.
Hold Off Time — The oscilloscope minimum hold off time before triggering the next waveform. Note
that any Auxiliary transaction from the source must receive a reply from the sink in 400 us, else such
a transaction is considered a timeout. Hold off time, in such cases, represents the minimum idle time
before each Aux transaction is initialized. It is defaulted to 300 us which is a safe timing value for
most devices tested in the lab. Most devices respond much faster than 300 us.
Trigger Level — The AUX Channel signal level on which to trigger. Note that for a bi-directional signal
(where a reference sink is attached), you must set the trigger level such that it crosses both the
source command and the sink reply signal. Figure shows correct and incorrect trigger levels.
Figure 82
Correct Trigger Level
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Figure 83
Incorrect Trigger Level
Vertical Scale — The oscilloscope vertical scale. Set the vertical to make sure that all signals are visible
on the oscilloscope display.
Offset — Set the offset so that the center point is aligned with the center of the oscilloscope display.
Upper Threshold/Lower Threshold — The threshold level of signal must be set properly so that both
upper and lower thresholds cross both the source and sink signals when the DUT is attached with a
reference sink. The threshold levels are important parameters because they are used for edge
detection when decoding a source command from a sink reply.
Figure 84
468
Correct Threshold set
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Figure 85
12
Wrong Thresholds set
c On the Trigger Setup page, you may click the Learn button, which guides you through getting
the trigger setup parameters. However, please note that the learning guide may not
necessarily work many a times because the actual Auxiliary signals may vary for different
manufacturers. Keysight recommends that you must check to make sure that the parameters
are correctly set as previously described.
d Click Verify and follow the instructions, if you wish to check the AUX Channel trigger.
e You may Save or Load the trigger setup configuration as a *.tsf file.
5
On the Acquisition Mode page, either Finish the setup wizard or enable Offline Mode, which is
de-selected, by default. Offline Mode lets you save the waveform files so that you can avoid the
manual process to initiate Auxiliary transactions during the time of test runs.
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6
If you enable Offline Mode, define the number of waveforms to be saved. If required, click Start
Acquisition to start capturing and saving waveforms.
7
Click Finish to close the setup wizard. The Set Up tab displays.
8
Click the Select Tests tab and select the AUX Channel tests you want to run.
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Probing/Connection Set Up for AUX Channel Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests. When performing the Source AUX
Channel tests, a Reference Sink device is required. Similarly, when performing the Sink AUX Channel
tests, a Reference Source device is required.
Figure 86
Sample connection diagram for source AUX channel tests with source DUT connected to a reference sink
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DisplayPort 1.4 AUX Channel Tests
Figure 87
Sample connection diagram for source AUX channel tests without connecting to a reference sink
Figure 88
Sample connection diagram for sink AUX channel tests with sink DUT connected to a reference source
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AUX Channel Unit Interval Test
Test ID
125000 — AUX Channel Unit Interval Test (Source)
125010 — AUX Channel Unit Interval Test (Sink)
Test Overview
The objective of the test is to evaluate the AUX Channel waveform, ensuring that the overall variation
of the Manchester transaction Unit Interval stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Set up the parameter of the measurement trend:
a Set up the Unit Interval measurement for the differential AUX Channel signal.
b Set up the frequency measurement for the Clock signal.
c Set up the measurement trend.
6
Set up the waveform Histogram on the measurement trend:
a Initialize AUX Channel transactions and acquire the differential AUX Channel signal.
b Identify the first and the last points for the desired transaction.
c Zoom-in on the desired transaction.
d Set up the Vertical Waveform Histogram on the measurement trend within the desired
transaction.
e Obtain the measurement for the mean, maximum and minimum values of the waveform
Histogram.
7
Repeat step 6 ten times.
8
Report the measurement results.
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PASS Condition
Manchester Transaction Unit Interval (UIMAN):
Minimum = 0.4 µsec
Maximum = 0.6 µsec
Test References
See:
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.4.2, Table 3-4
Expected/Observable Results
The measured unit interval for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Test
Test ID
125001 — AUX Channel Eye Test (Source)
125011 — AUX Channel Eye Test (Sink)
Test Overview
The objective of this test is to evaluate the transmitter AUX Channel waveform, ensuring that the
timing variables and amplitude trajectories support the overall DP system objectives of the Bit Error
Rate in data transmission.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the waveform Histogram on the AUX Channel eye diagram to measure the left edge and
the right edge.
8
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
9
Check for any signal trajectories entering into the mask.
10 Report the measurement results.
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DisplayPort 1.4 AUX Channel Tests
PASS Condition
PASS Value = 290mV_diff_pp or higher
FAIL Value = lower than 290mV_diff_pp
Table 87
Eye Mask Vertices for AUX Channel for Manchester Transactions
Mask Point
Time (from EYE Center)
Minimum Voltage Value at Six Vertices (mV)
1
-185ns
0
2
-135ns
145
3
135ns
145
4
185ns
0
5
135ns
-145
6
-135ns
-145
Figure 89
AUX Channel EYE Mask for Manchester Transactions
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.1
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.4.2.5, Figure 3-18 and Table 3-5
Expected/Observable Results
The measured eye diagram for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
The rendered eye diagram shall have no signal trajectories entering the mask area.
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AUX Channel Peak-to-Peak Voltage Test
Test ID
125002 — AUX Channel Peak-to-Peak Voltage Test (Source)
125012 — AUX Channel Peak-to-Peak Voltage Test (Sink)
Test Overview
The objective of the test is to evaluate the transmitter AUX Channel Waveform, ensuring that the
peak-to-peak voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform Histogram on the AUX Channel eye diagram to measure the left
edge and the right edge.
8
If you have selected the “AUX Channel Eye Test” under the Select Tests tab of the compliance
application:
a Set up the parameter of the Mask Test:
i
Load the eye mask based on the settings in the Configuration Variable.
ii
Center the eye mask at the middle of the eye diagram based on the measured left edge
and right edge.
iii Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
b Check for any signal trajectories entering into the mask.
9
Report the measurement results.
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DisplayPort 1.4 AUX Channel Tests
PASS Condition
Table 88
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage at a transmitting device (VAUX-DIFFp-p)
0.29V
0.40V
Test References
See:
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.4.2, Table 3-4
Expected/Observable Results
The measured peak-to-peak voltage for the transmitter AUX Channel signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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AUX Channel Eye Sensitivity Calibration Test
Test ID
125021 — AUX Channel Eye Sensitivity Calibration (Reference Sink)
125031 — AUX Channel Eye Sensitivity Calibration (Reference Source)
Test Overview
The objective of this test is to calibrate the peak-to-peak voltage of the transmitter AUX Channel
waveform by reference device (reference source or reference sink), ensuring that the peak-to-peak
voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
6
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
7
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
8
Set up the waveform Histogram on the AUX Channel eye diagram:
a Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
b Set up the vertical waveform Histogram of width 0.6 UI at the center of the AUX Channel eye
diagram.
c Measure the VTOP and VBASE using the waveform Histogram mean value.
9
Repeat Step 8 three times.
10 Report the measurement results.
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DisplayPort 1.4 AUX Channel Tests
PASS Condition
Table 89
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage for AUX Channel Eye Sensitivity
0.24V
0.28V
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.4.2, Table 3-4
Expected/Observable Results
The measured peak-to-peak voltage for the AUX Channel signal by reference device (reference
source or reference sink) shall be within the conformance limits as specified in the specification
mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Sensitivity Test
Test ID
125041 — AUX Channel Eye Sensitivity Test (Source)
125051 — AUX Channel Eye Sensitivity Test (Sink)
Test Overview
The objective of the test is to evaluate the sensitivity to the AUX Channel Eye Opening of the DUT as
per the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
6
Check if the reference device could detect the transaction or not.
7
Decode the AUX Channel signal and check whether the transaction passed or failed.
8
Report the measurement results.
PASS Condition
Determine whether the AUX Channel communication is successful. For example, the Transmitter
DUT sends an AUX Request to the Reference Receiver. The Reference Receiver acknowledges and
the Transmitter DUT responds to the to indicate that the acknowledgment was successfully received.
PASS = No errors observed in the response
FAIL = One or more errors observed
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DisplayPort 1.4 AUX Channel Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.4.2, Table 3-4
Expected/Observable Results
The measured AUX Channel transaction shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
13 DisplayPort 1.4 Inrush Tests
Overview / 484
Inrush Energy Power Test / 487
Inrush Peak Current Test / 489
13
DisplayPort 1.4 Inrush Tests
Overview
This section describes the normative and informative inrush tests for compliance verification of
DisplayPort1.4 source and sink (a power consumer).
Test Point
The test fixture for inrush tests implements the schematic shown in Figure 90.
Figure 90
Schematics for testing a Power Consumer Device
The test fixture must be designed and used according to the following guidelines:
• A high gate voltage FET on the DP_PWR line is recommended to allow a fast connect
capability, which allows a single connection event for testing. Without such an arrangement,
multiple connections will be required to obtain a reasonable “worst-case” attachment event.
• Connection length between the power supply and the test fixture must be minimized. A
maximum of four inches is recommended.
• The power supply must have enough outrush capability as to not negatively affect the test
fixture’s outrush capability.
• The power supply must be run at 3.6V (3.3V + 10%) read across VC.
Any Power Consumer test fixture must be calibrated using the Power User test fixture, as shown in
Figure 90. Testing with the two fixtures combined should result in the approximate values given below.
If required, the component values on the Power Consumer test fixture should be adjusted to match
the expected results.
• VC steady before connection = 3.6V
• VC droop = ~3.1V
• Inrush Current = ~13.0A
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Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Inrush Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 91).
Figure 91
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests. Refer to “Setting Up for AUX PHY and
Inrush Tests" on page 465 to know in detail how to set up the DUT for Inrush Tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Inrush Energy Power Test
Test ID
127000 — Inrush Energy Power Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
Power (Ps) = Id*Vs
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush energy power measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Energy ResultantPEAK_CURRENT_Power_Consumer < 13.5 Amps
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DisplayPort 1.4 Inrush Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.5
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.2.3
Expected/Observable Results
The measured worst case inrush energy power for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Inrush Peak Current Test
Test ID
127001 — Inrush Peak Current Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
Source—TP2
Sink—TP3
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
Power (Ps) = Id*Vs
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush peak current measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Energy ResultantPEAK_CURRENT_Power_Consumer < 13.5 Amps
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DisplayPort 1.4 Inrush Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.5
• VESA DisplayPort (DP) Standard Version 1.4, Section 3.2.3
Expected/Observable Results
The measured worst case inrush peak current for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
490
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
14 DisplayPort 1.4 Dual Mode
Tests
Overview / 492
Setting Up for Dual Mode Tests / 496
Dual Mode TMDS Clock Duty Cycle Test / 500
Dual Mode TMDS Clock Jitter Test / 502
Dual Mode Eye Diagram Test / 504
Dual Mode Data Jitter Test / 507
Dual Mode Data Peak-Peak Differential Voltage Test / 509
Dual Mode Inter-Pair Skew Test / 511
Dual Mode Intra-Pair Skew Test / 513
14
DisplayPort 1.4 Dual Mode Tests
Overview
This section describes the normative and informative dual mode physical layer (differential and
single-ended) tests for compliance verification of DisplayPort1.4 source.
Test Point
The source device for dual mode tests must be tested at Test Point 2 (TP2), as shown in Figure 92.
Figure 92
492
Test Point 2 Connection for Dual Mode Source Tests
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Table 90 defines the Test Points used for Dual Mode Tests:
Table 90
Test Point 2 Connections for Dual Mode Tests
Test Requirement
Device Used
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-P*
• W2641B DisplayPort Test Point Access Adapter
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-P*
• Luxshare ICT mDP Plug (mDP-TPA-P)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort 1.4 Dual Mode Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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DisplayPort 1.4 Dual Mode Tests
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 93).
Figure 93
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with DisplayPort 1.4 Standards, select 1.4 from the drop-down options in
the Test Specification area and select Dual Mode Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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14
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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DisplayPort 1.4 Dual Mode Tests
Setting Up for Dual Mode Tests
Perform the following steps before you run the Dual Mode tests on the source or sink device:
1
496
On the DisplayPort Compliance Test Application, click the Test Setup button on the Set Up tab.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort 1.4 Dual Mode Tests
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14
On the Dual Mode Setup page, select Single-Ended or Differential Probe from the drop-down in the
Connection Type area. The option to select the number of oscilloscope channel connections is
grayed out if you select Single-Ended connection type. For Differential Probe, you may choose either
a 2-Channel or a 4-Channel setup. Select the clock frequency for Dual Mode signal in the Pixel
Clock Frequency area. Click Next to go to next page.
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DisplayPort 1.4 Dual Mode Tests
3
498
On the Channel Selection page, you may assign the data lanes, clock lanes and oscilloscope
channels to establish an SMA (Single-Ended) or Differential Probe connection. Click Finish.
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DisplayPort 1.4 Dual Mode Tests
14
Probing/Connection Set Up for Dual Mode Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 94
Connection diagram for a 4-Channel Dual Mode Test
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DisplayPort 1.4 Dual Mode Tests
Dual Mode TMDS Clock Duty Cycle Test
Test ID
501 — Dual Mode TMDS Clock Duty Cycle (Min)
502 — Dual Mode TMDS Clock Duty Cycle (Max)
Test Overview
The objective of the test is to confirm that the duty cycle of the TMDS Clock waveform of a Source
DUT operating in dual mode does not exceed the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_CLOCK
Measurement Procedure
1
Acquire and verify the input TMDS Clock signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Scale the vertical display of the input TMDS Clock signal to optimum value.
c Measure VTOP and VBASE of the input TMDS Clock signal.
d Measure the Clock Frequency of the input TMDS Clock signal.
2
Generate FUNC4 signal, which is the differential signal of the TMDS Clock signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit Clock, input TMDS Clock signal).
4
Overlap the TMDS Clock signal to fold the differential signal of the TMDS Clock signal.
a Acquire the signal until 10,000 clock periods are folded.
5
Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the minimum and maximum duty cycle.
a The minimum duty cycle is measured as the earliest crossing of the TMDS Clock signal falling
edge.
b The maximum duty cycle is measured as the latest crossing of the TMDS Clock signal falling
edge.
6
Report the measurement results.
PASS Condition
PASS: 40% < TMDS_CLOCK duty cycle < 60%.
FAIL: TMDS_CLOCK duty cycle < 40% or TMDS_CLOCK duty cycle > 60%
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.18
Expected/Observable Results
The measured duty cycle of the dual mode TMDS Clock signal shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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DisplayPort 1.4 Dual Mode Tests
Dual Mode TMDS Clock Jitter Test
Test ID
For 25MHz < TMDS Clock Frequency < 165MHz
•
503 — Dual Mode TMDS Clock Jitter
For TMDS Clock Frequency > 165MHz
•
803 — Dual Mode TMDS Clock Jitter
Test Overview
The objective of the test is to confirm that the TMDS Clock waveform of a Source DUT operating in
dual mode does not carry excessive jitter than that defined in the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_CLOCK
Measurement Procedure
1
Acquire and verify the input TMDS Clock signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Scale the vertical display of the input TMDS Clock signal to optimum value.
c Measure VTOP and VBASE of the input TMDS Clock signal.
d Measure the Clock Frequency of the input TMDS Clock signal.
2
Generate FUNC4 signal, which is the differential signal of the TMDS Clock signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit Clock, input TMDS Clock signal).
4
Overlap the TMDS Clock signal to fold the differential signal of the TMDS Clock signal.
a Acquire the signal until 400,000 clock periods are folded.
5
Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
6
Report the measurement results.
PASS Condition
For 25MHz < TMDS Clock Frequency < 165MHz
• PASS: Measured TMDS Clock Jitter < 0.20 Tbit and Data Jitter < 0.25 Tbit
For 165MHz < TMDS Clock Frequency < 300MHz
• PASS: Measured TMDS Clock Jitter < 120 ps and Data Jitter < 150 ps
502
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.18
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured jitter of the dual mode TMDS Clock signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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DisplayPort 1.4 Dual Mode Tests
Dual Mode Eye Diagram Test
Test ID
601, 602, 603 — Dual Mode Eye Diagram Testing
Test Overview
The objective of the test is to evaluate the waveform ensuring that the timing variables and
amplitude trajectories of a Source DUT operating in dual mode meets the specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
504
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
8
Measure the eye height of the eye diagram using the histogram.
9
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
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10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
Figure 95
TMDS Data EYE Mask for TMDS Clock Frequencies from 25MHz to 165MHz
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DisplayPort 1.4 Dual Mode Tests
TMDS Data EYE Mask for TMDS Clock Frequencies above 165MHz
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.19
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2, Figure 3-10 (for 25MHz <
TMDS Clock Frequency < 165MHz) and Figure 3-11 (for TMDS Clock Frequency > 165MHz)
Expected/Observable Results
The measured eye diagram for the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Dual Mode Data Jitter Test
Test ID
For 25MHz < TMDS Clock Frequency < 165MHz
•
611, 612, 613 — Dual Mode Data Jitter
For TMDS Clock Frequency > 165MHz
•
911, 912, 913 — Dual Mode Data Jitter
Test Overview
The objective of the test is to confirm that the data waveform of a Source DUT operating in dual
mode does not carry excessive jitter than that defined in the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
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8
Measure the eye height of the eye diagram using the histogram.
9
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
For 25MHz < TMDS Clock Frequency < 165MHz
• PASS: Measured TMDS Clock Jitter < 0.20 Tbit and Data Jitter < 0.25 Tbit
For 165MHz < TMDS Clock Frequency < 300MHz
• PASS: Measured TMDS Clock Jitter < 120 ps and Data Jitter < 150 ps
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.19
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured jitter of the dual mode data signal shall be within the conformance limits as specified
in the specification mentioned under the “PASS Condition” section for this test.
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Dual Mode Data Peak-Peak Differential Voltage Test
Test ID
811, 812, 813 — Dual Mode Peak-Peak Differential Voltage (Min)
821, 822, 823 — Dual Mode Peak-Peak Differential Voltage (Max)
Test Overview
The objective of the test is to evaluate and confirm that the data waveform ensuring that the timing
variables and amplitude trajectories of a Source DUT operating in a dual mode meets the
specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery (Explicit First Order PLL, input TMDS Clock signal).
3
Fold the differential signal of the data signal to generate an eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
4
Set up the waveform histogram on the data signal eye diagram to measure the left edge and
right edge.
5
Set up the parameter of the Mask Test.
a Load the Eye mask.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Run the Eye mask until the 400,000 UI are folded.
6
Check for any signal trajectories entering into the mask.
7
Measure the jitter of the eye diagram using the histogram.
8
Measure the eye height of the eye diagram using the histogram.
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9
Measure the peak-to-peak voltage at 0.5UI of the eye diagram using the histogram.
10 Overlap the TMDS Clock Signal to fold the differential signal of the data signal.
a Acquire the signal until 400,000 clock period are folded.
11 Set up the waveform histogram on the differential signal of the TMDS Clock signal to measure
the total jitter of the TMDS Clock signal.
12 Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies:
•
Minimum Peak-Peak Differential Voltage: 180mV
•
Maximum Peak-Peak Differential Voltage: 1380mV
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured peak-peak differential voltage of the dual mode data signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Dual Mode Inter-Pair Skew Test
Test ID
711 — D0/D1 - Dual Mode Inter Pair Skew Test
712 — D0/D2 - Dual Mode Inter Pair Skew Test
713 — D1/D2 - Dual Mode Inter Pair Skew Test
Test Overview
The objective of the test is to evaluate and confirm that the skew or time delay between differential
data lane of a Source DUT operating in a dual mode meets the specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input Lane A data signal.
c Verify the trigger and the amplitude of the input Lane B data signal.
d Scale the vertical display of the input TMDS Clock signal to optimum value.
e Scale the vertical display of the input Lane A data signal to optimum value.
f
Scale the vertical display of the input Lane B data signal to optimum value.
g Measure VTOP and VBASE of the input TMDS Clock signal.
h Measure VTOP and VBASE of the input Lane A data signal.
2
i
Measure VTOP and VBASE of the input Lane B data signal.
j
Measure the Clock Frequency of the input TMDS Clock signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
3
Set up the parameter of the Inter Pair Skew measurement.
a Set up two display grids such that each grid displays one test lane data signal.
b Set up the measurement threshold of each test lane data signal on the Transition Voltage =
0V.
c Decode the data signal for each test lane.
d Search the desired pattern from the decoded data signal.
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e Measure the time difference between the corresponding edges of both the test lanes using the
equation:
TTransition_LaneA - TTransition_LaneB
f
Repeat the previous step until you measure 100 edges.
g Calculate the Inter Pair Skew using the equation:
Inter Pair Skew = {1/Number of Edges} ∑ |TTransition_LaneA - TTransition_LaneB|
4
Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies, Inter-Pair Skew < 976 ps
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured inter pair skew of the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Dual Mode Intra-Pair Skew Test
Test ID
701, 702, 703 — Dual Mode Intra Pair Skew Test
Test Overview
The objective of the test is to evaluate and confirm that the skew or time delay between the
respective sides of the differential data lane of a Source DUT operating in a dual mode meets the
specification requirements.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Clock Rate
Maximum TMDS Clock Rate supported by the DUT
Test Lane
TMDS_DATA0, TMDS_DATA1, TMDS_DATA2
Measurement Procedure
1
Acquire and verify the input TMDS Clock and data signal:
a Verify the trigger and the amplitude of the input TMDS Clock signal.
b Verify the trigger and the amplitude of the input data signal.
c Scale the vertical display of the input TMDS Clock signal to optimum value.
d Scale the vertical display of the input data signal to optimum value.
e Measure VTOP and VBASE of the input TMDS Clock signal.
f Measure VTOP and VBASE of the input data signal.
g Measure the Clock Frequency of the input TMDS Clock signal.
2
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain the statistical values of the measurement.
b Set up the measurement threshold.
3
Set up the parameter to perform High Level Voltage (VHigh) and Low Level Voltage (VLow) for
each single-ended data signal:
a Scale the vertical display of the single-ended input data signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHigh by measuring the average voltage at 0.6UI to 0.75UI of the High level.
d Find VLow by measuring the average voltage at 0.6UI to 0.75UI of the Low level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHigh + VLow)/2
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4
Set up the parameter of the Intra Pair Skew measurement.
a Set up measurement threshold od each single-ended data signal based on the Transition
Voltage measured.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure the time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge using the equation:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure the time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) falling edge using the equation:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the Intra Pair Skew using the equation:
Intra Pair Skew = {1/Number of Edges} ∑ {[(D+Transition_High - D-Transition_Low) +
(D+Transition_Low - D-Transition_High)]/2}
5
Report the measurement results.
PASS Condition
For all TMDS Clock Frequencies, Intra-Pair Skew < 60 ps
Test References
See:
• VESA DisplayPort Dual-Mode Standard Version 1.1, Section 3.6.2
Expected/Observable Results
The measured intra pair skew of the dual mode data signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
15 MyDP 1.0 Source Tests
Overview / 516
Source Eye Diagram Test / 522
Source Total Jitter Test / 529
Source Non-ISI Jitter Test / 534
Source Non Pre-Emphasis Level Test / 539
Source Pre-Emphasis Level Differential Tests / 547
Source Non Transition Voltage Range Measurement Test / 555
Source Peak to Peak Voltage Test / 562
Source Main Link Frequency Compliance Test / 567
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test / 573
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test / 579
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative) / 585
Post-Cursor 2 Verification Test (Informative) / 591
Eye Diagram Test (TP3_EQ) / 597
Total Jitter Test (TP3_EQ) / 606
Deterministic Jitter Test (TP3_EQ) / 612
Random Jitter Test (TP3_EQ) / 618
AC Common Mode Test (Informative) / 623
Intra-Pair Skew Test (Informative) / 628
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MyDP 1.0 Source Tests
Overview
This section describes the normative and informative main link physical layer tests for compliance
verification of Mobility DisplayPort (MyDP) sources.
Test Point Definition for MyDP Tests
Five different test points are identified for the physical layer measurement. See Figure 96.
Figure 96
Test Points in a DisplayPort InterConnect System
Table 91 defines the Test Points used for MyDP 1.0 Tests:
Table 91
Test Points for DisplayPort Tests
Test Point
Description
TP1
At the pins of the Transmitter Device
TP2
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Source device
TP3
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Sink device
TP3_EQ
At TP3, when a defined cable model with equalizer is applied. There are two defined
cable models:
• Worst Cable Model as defined in VESA DisplayPort 1.2a Standard,
• Zero length, zero loss cable. The equalizer is also defined in VESA DisplayPort 1.2a
Standard
TP4
At the pins of a receiving device
Cable Models
The two cable models defined in VESA DisplayPort 1.2a Standard are:
1
Worst Case Cable Model—To achieve the TP3_EQ signal with the worst case cable model:
•
Acquire the signal at TP2.
•
Embed the TP2 signal with a “worst case” HBR cable model using an InfiniiSim Waveform
Transformation Toolset software to emulate the insertion loss as defined in Figure 4-10 of the
VESA DisplayPort 1.2a Standard.
• For the DisplayPort Compliance Test Application, the “CIC_rev0p6.s4p” cable model transfer
function is used.
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•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
2
Zero Length Cable Model—To achieve the TP3_EQ signal with the zero length cable model:
•
Acquire the signal at TP2.
•
No cable model is embedded for the Zero Length cable model.
•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
15
Equalization
When equalization is required, use the CTLE (Continuous Time Linear Equalization) transfer function,
as given in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a Standard.
For main link, use the CTLE model with the following transfer function for HBR:
Figure 97
Transfer Function of the CTLE model for HBR
For main link, use the CTLE model with the following transfer function for HBR2:
Figure 98
Transfer Function of the CTLE model for HBR2
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Clock Recovery
When Clock Recovery is required, the clock recovery technique follows the definition of the receiver
PLL as defined in Section 3.5.3.5 of the VESA DisplayPort 1.2a Standard. For main link, use the
second-order clock recovery function with a closed loop tracking bandwidth and damping factor,
with respect to the PRBS7 pattern, as shown in Table 92:
Table 92
Main Link Second-Order Clock Recovery Function
Bit Rate
Band wid th
Damping Factor
HBR2
10 MHZ
1.00
HBR
10 MHz
1.51
RBR
5.4 MHz
1.51
Test Point Definition for MyDP 1.0 Source Tests
Test the Source DUT at Test Point 2 (TP2) as shown in Figure 99.
Figure 99
518
Test Point 2 Connection for MyDP 1.0 Source Tests
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Use MyDP Test Fixtures (MyDP-to-DP type or MyDP-to-SMA type) to perform PHY compliance tests
specific to MyDP. Figure 100 shows the layout of a MyDP passive cable adapter or a MyDP protocol
converter:
Figure 100
Schematics of MyDP to SMA Test Fixtures used for PHY Compliance Tests
Table 93 defines the test point fixtures and instruments used for MyDP 1.0 Source Tests:
Table 93
Test Point Fixtures and Instruments for MyDP 1.0 Source Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests
Perform the following steps before you run the compliance tests on the source device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 101).
Figure 101
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with Mobility DisplayPort 1.0 Standards, select MyDP 1.0 from the
drop-down options in the Test Specification area and select Physical Layer Tests in the Test Selection
area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for MyDP 1.0 Source Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 102
Sample connection diagram for MyDP 1.0 Source Tests
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Source Eye Diagram Test
Test ID
1210001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
522
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure VTOP and VBASE of the input signal using the pattern folding.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the input signal eye diagram to measure the left
edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the eye height of the eye diagram using the Histogram.
9
Measure the jitter of the eye diagram using the Histogram.
10 Calculate the eye width based on the measured jitter of the eye diagram.
11 Check for any signal trajectories that may have entered into the mask.
12 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 94 shows the voltage and time coordinates for the mask
used in the eye diagram.
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Table 94
15
Eye Diagram Mask Coord inates
Mask Point
Bit Rate
Red uced (1.62 Gb/s)
High (2.7 Gb/s)
1
0.127, 0.000
0.210, 0.000
2
0.291, 0.160
0.355, 0.140
3
0.500, 0.200
0.500, 0.175
4
0.709, 0.200
0.645, 0.175
5
0.873, 0.000
0.790, 0.000
6
0.709,-0.200
0.645,-0.175
7
0.500,-0.200
0.500,-0.175
8
0.291,-0.160
0.355,-0.140
Figure 103
The Source Eye Mask
Mask Test: Zero mask failures.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
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• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-24 for RBR and
Table 3-23 for HBR
Expected/Observable Results
The measured eye diagram for the source degraded signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
15
Source Total Jitter Test
Test ID
1220001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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MyDP 1.0 Source Tests
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Report the measurement results.
PASS Condition
Table 95
Total Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.294 UI
0.420 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.180 UI
0.270 UI
UI is Unit Interval.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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MyDP 1.0 Source Tests
Source Non-ISI Jitter Test
Test ID
1230001 — Non ISI Jitter Test
Test Overview
The objective of the test is to evaluate the amount of Non ISI jitter accompanying the data
transmission.
The jitter is separated into each jitter components based on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Non-ISI Jitter Test
534
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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MyDP 1.0 Source Tests
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Calculate the Non ISI jitter using the following equation:
Non ISI Jitter = TJ - ISI
7
Report the measurement results.
PASS Condition
Table 96
Non-ISI Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.260 UI
0.276 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.160 UI
0.210 UI
UI is Unit Interval.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.11
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
15
Source Non Pre-Emphasis Level Test
Test ID
For RBR and HBR:
•
1261001 — Non Pre-Emphasis Level Test (Swing 1/Swing 0)
•
1262001 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263001 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
For HBR2:
•
1264101 — Non Pre-Emphasis Level Test (Swing 2/Swing 0)
•
1262101 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263101 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
Test Overview
The objective of this test is to ensure that the system budget elements are obeyed and to ensure that
the level settings are monotonic so that the sink relies on the source to incrementally increase upon
request by the sink.
Test Conditions for Non Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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MyDP 1.0 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
For Voltage Level A with no pre-emphasis level:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_Lvl0_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 104
High Voltage measurement for RBR and HBR
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Figure 105
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_Lvl0_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 106
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
544
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
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Calculate the peak-to-peak value of the transition voltage using the equation:
VT_Lvl0_PP = VT_Lvl0_H - VT_Lvl0_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_Lvl0_PP = VN_Lvl0_H - VN_Lvl0_L
2
Repeat Step 1 for Voltage Level B with no pre-emphasis level.
3
Calculate the non pre-emphasis level output voltage ratio using the equation:
Non Pre-Emphasis Level = 20 * Log10[Voltage Level A VN_Lvl0_PP / Voltage Level B VN_Lvl0_PP]
4
Report the measurement results.
PASS Condition
For each level setting testes, the following equation should be used:
Resultant = 20 * Log10[VoltagePeak-Peak_LevelA / VoltagePeak-Peak_LevelB]
Table 97
Compared Levels
Measurement#
Vol tagePeak-Peak_LevelA
VoltagePeak-Peak_LevelB
1
Level 1 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
2
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
3*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
4
Level 2 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
5
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
6*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
RBR & HBR
HBR2
* if device optionally capable of Level 3
The resultants specifications are as identified below:
Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB
Measurement 3: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 4: 5.2 dB ≤ Resultant ≤ 6.9 dB
Measurement 5: 1.6 dB ≤ Resultant ≤ 3.5 dB
Measurement 6: 1 dB ≤ Resultant ≤ 4.4 dB
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Table 98
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-OUTPUT-RATIO_RBR_HBR
VTX-OUTPUT-RATIO_HBR2
Parameter
Min
Nom
Max
Unit
Ratio of Output Voltage
Level 1/Level 0
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 1
0.1
-
5.1
dB
Ratio of Output Voltage
Level 3/Level 2
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 0
5.2
-
6.9
dB
Ratio of Output Voltage
Level 2/Level 1
1.6
-
3.5
dB
Ratio of Output Voltage
Level 3/Level 2
1
-
4.4
dB
Comments
Measured on non-transition
bits at Pre-emphasis level 0
setting
Measured on non-transition
bits at Pre-emphasis level 0
setting
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level ratio of the non pre-emphasis level test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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MyDP 1.0 Source Tests
15
Source Pre-Emphasis Level Differential Tests
Test ID
For RBR and HBR:
•
1270001 — Pre-Emphasis Level Test
For HBR2:
•
1270501 — Pre-Emphasis Level Test
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Test Conditions for Pre-Emphasis Level Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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MyDP 1.0 Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
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Measurement Procedure
1
For a given Voltage Level and a Pre-Emphasis Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 107
High Voltage measurement for RBR and HBR
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Figure 108
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 109
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
552
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
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Calculate the peak-to-peak value of the transition voltage using the equation:
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
l
Calculate the pre-emphasis level using the equation:
Pre-EmphasisLvlX = 20 * Log10[VT_LvlX_PP / VN_LvlX_PP]
2
For Pre-Emphasis Level 0 (no pre-emphasis level), the result for Pre-EmphasisLvl0 is compared
with the maximum pre-emphasis disabled limit.
3
Repeat Step 1 for the next Pre-Emphasis level and for each Pre-Emphasis levels, compare the
pre-emphasis delta with the pre-emphasis delta limits.
4
Calculate the pre-emphasis delta using the equation:
Pre-Emphasis Delta (Level 1 vs Level 0) = Pre-EmphasisLvl1 - Pre-EmphasisLvl0
Pre-Emphasis Delta (Level 2 vs Level 1) = Pre-EmphasisLvl2 - Pre-EmphasisLvl1
Pre-Emphasis Delta (Level 3 vs Level 2) = Pre-EmphasisLvl3 - Pre-EmphasisLvl2
5
Report the measurement results.
PASS Condition
Pre-emphasis values for the Level 0 (OFF) state (Normative)
Level 0 (OFF) Pre-emphasis measurement:
Resultant = 20 * Log [VoltageT_Lvl0_PP / VoltageN_Lvl0_PP] for all supported levels.
Level 0 (OFF) Pre-emphasis Measurement condition: +0.25 dB > Resultant
Pre-emphasis Delta values for:
a Level 1 vs. Level 0 Pre-emphasis settings (NORMATIVE)
b Level 2 vs. Level 1 Pre-emphasis settings (NORMATIVE)
c Level 3 vs. Level 2 Pre-emphasis settings (NORMATIVE)
Pre-emphasis Delta measurements:
•
Level 1 vs. Level 0
Resultant = 20 * Log [VoltageT_Lvl1_PP / VoltageN_Lvl1_PP] - 20 * Log [VoltageT_Lvl0_PP /
VoltageN_Lvl0_PP] for Voltage Swing Levels 0, 1 and 2.
•
Level 2 vs. Level 1
Resultant = 20 * Log [VoltageT_Lvl2_PP / VoltageN_Lvl2_PP] - 20 * Log [VoltageT_Lvl1_PP /
VoltageN_Lvl1_PP] for Voltage Swing Levels 0 and 1.
•
Level 3 vs. Level 2
Resultant = 20 * Log [VoltageT_Lvl3_PP / VoltageN_Lvl3_PP] - 20 * Log [VoltageT_Lvl2_PP /
VoltageN_Lvl2_PP] for Voltage Swing Level 0, if supported.
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Table 99
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
VTX-PREEMP-OFF
Maximum Pre-emphasis
when disabled
-
-
0.25
dB
Delta of Pre-emphasis
Level 1 vs. Level 0
2
-
-
dB
Delta of Pre-emphasis
Level 2 vs. Level 1
1.6
-
-
dB
Delta of Pre-emphasis
Level 3 vs. Level 2
1.6
-
-
dB
VTX-PREEMP-DELTA
Min
Nom
Max
Unit
Comments
Pre-emphasis Level 0 setting
must not show any
pre-emphasis at TP2 to
prevent link training issues.
Applies to all valid voltage
settings. Measured at
Pre-emphasis Post Cursor2
Level 0.
Support for Pre-emphasis
Level 3 is optional.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis level or pre-emphasis delta for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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MyDP 1.0 Source Tests
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Source Non Transition Voltage Range Measurement Test
Test ID
For RBR and HBR:
•
1272001 — Non-Transition Voltage Range Measurement (Swing 0)
•
1273001 — Non-Transition Voltage Range Measurement (Swing 1)
•
1274001 — Non-Transition Voltage Range Measurement (Swing 2)
For HBR2:
•
1272101 — Non-Transition Voltage Range Measurement (Swing 0)
•
1273101 — Non-Transition Voltage Range Measurement (Swing 1)
•
1274101 — Non-Transition Voltage Range Measurement (Swing 2)
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Comparisons are also made for the Level 0 transition state as well as non-transition levels.
Test Conditions for Non Transition Voltage Range Measurement Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Transition Voltage Range Measurement Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
For a given Voltage Level, repeat the following steps for all pre-emphasis levels subjected to
constraints specified in Table 3-1 of the VESA DisplayPort 1.2a Standard:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 110
High Voltage measurement for RBR and HBR
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Figure 111
Low Voltage measurement for RBR and HBR
e For HBR2 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 112
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
560
i
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
j
Calculate the peak-to-peak value of the transition voltage using the equation:
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VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
2
Calculate the non transition voltage range using the equation:
Non Transition Voltage Range = Minimum [(VN_LvlX_PP) / (VN_Lvl0_PP)]
where, VN_LvlX_PP) refers to all supported pre-emphasis levels (Level1, Level2, Level3 and so on
up to Level X).
3
Report the measurement results.
PASS Condition
Non-Transition Voltage Range Measurements
For Level 2 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 1 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 0 voltage setting: Resultant > 0.85 OR 20*log(Resultant) > -1.4dB
Table 100
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-DIFF_REDUCTION
Parameter
Min
Nom
Max
Unit
Non-transition reduction
Output Voltage Level 2
-
-
3
dB
Non-transition reduction
Output Voltage Level 1
-
-
3
dB
Non-transition reduction
Output Voltage Level 0
-
-
1.4
dB
Comments
VTX-DIFF at each non-zero
nominal pre-emphasis level
must not be lower than the
specified amount less than
VTX-DIFF at the zero nominal
pre-emphasis level.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level reduction of the non transition bit for the test signal shall be
within the conformance limits as specified in the specification mentioned under the “PASS Condition”
section for this test.
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Source Peak to Peak Voltage Test
Test ID
For RBR and HBR:
•
1266001 — Peak to Peak Voltage Test
For HBR2:
•
1266101 — Peak to Peak Voltage Test
Test Overview
The objective of this test is to evaluate the maximum differential peak to peak voltage.
Test Conditions for Peak to Peak Voltage Test
562
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported with constraints specified in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2 — PLTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Peak to Peak Voltage Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
MyDP 1.0 Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure the maximum and minimum voltage of the input signal.
4
Calculate the peak to peak voltage using the equation:
Peak to Peak Voltage = Maximum Voltage - Minimum Voltage
5
Report the measurement results.
PASS Condition
For all Data Rates:
Maximum Differential Peak to Peak Voltage < 1.38V
Table 101
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
VTX-DIFFp-p_MAX
Max Output Voltage Level
-
Nom
-
Max
1.38
Unit
V
Comments
For all Output Level and
Pre-emphasis combinations.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured peak to peak voltage for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Main Link Frequency Compliance Test
Test ID
12193001 — Main Link Frequency Compliance
Test Overview
The objective of this test is to ensure that the average data rate under all conditions does not exceed
the minimum and maximum values as set by the VESA DisplayPort 1.2a Standard.
Test Conditions for Main Link Frequency Compliance Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Main Link Frequency Compliance Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and the minimum measurement levels for the FUNC2 magnified unit
interval measurement trend.
d Set up two frequency measurement levels for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e For SSC Enabled Test condition, check the measured frequency to verify the existence of SSC
in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
For the test condition “SSC Enabled”, set up the parameter of the SSC measurement:
a Set up the memory depth and time-base to display one complete SSC cycle based on the
measured SSC modulation frequency in Step 5.
b Acquire the signal with one complete SSC cycle.
c Get the minimum of FUNC2 filtered unit interval measurement trend to calculate the maximum
data rate:
Maximum Data Rate = 1 / (Minimum Unit Interval)
d Get the maximum of FUNC2 filtered unit interval measurement trend to calculate the minimum
data rate:
Minimum Data Rate = 1 / (Maximum Unit Interval)
e Repeat steps b, c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rates.
10 Report the measurement results.
PASS Condition
Maximum Data Rate (Frequency Maxppm) < 300 ppm
Minimum Data Rate (Frequency Minppm) > -5300 ppm
Table 102
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Unit
fHBR2
Frequency for High
Bit Rate 2
5.37138
5.4
5.40162
Gbps
fHBR
Frequency for High
Bit Rate
2.68569
2.7
2.70081
Gbps
fRBR
Frequency for
Reduced Bit Rate
1.611414
1.62
1.620486
Gbps
Comments
Frequency high limit =
+300ppm
Frequency low limit =
-5300ppm
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.14
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured data rate for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID
12170001 — SSC Modulation Frequency Test
Test Overview
The objective of this test is to evaluate the frequency of the SSC modulation and to validate that the
frequency is within specification limits. This test includes the use of the 2nd order Butterworth
low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of
10 full SSC cycles. Calculate the SSC modulation frequency from the average of the measured SSC
modulation frequency for each cycle.
Test Conditions for SSC Modulation Frequency Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Frequency Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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15
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
g Acquire the signal for 10 SSC Cycles.
6
Get the mean value for the SSC Modulation frequency.
7
Report the measurement results.
PASS Condition
30kHz < SSC Modulation Frequency (fSSC) < 33kHz
Table 103
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Down_Spread_Frequency
Link clock down-spreading
frequency
30
-
33
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Unit
kHz
Comments
Range: 30kHz ~ 33kHz when
down-spread enabled
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Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.15
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation frequency for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
578
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Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID
12180001 — SSC Modulation Deviation Test
Test Overview
The objective of this test is to evaluate the range of SSC down-spreading of the transmitter signal in
ppm and to validate that the values are within specification limits. This test includes the use of the
2nd order Butterworth low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is
conducted over a minimum of 10 full SSC cycles. For each cycle, the minimum and maximum data
rate is evaluated. Calculate the SSC modulation deviation from the average of the maximum minus
the average of the minimum using the equation:
SSC Modulation Deviation = {[Average (Maximum Data Rate) - Average (Minimum Data Rate)] /
Nominal Data Rate}*1e6
Test Conditions for SSC Modulation Deviation Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Deviation Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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15
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and minimum measurements for the FUNC2 magnified unit interval
measurement trend.
d Set up two frequency measurements for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e Check the measured frequency to verify the existence of SSC in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point for three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 filtered unit interval measurement
trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurements for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
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9
Set up the parameters for SSC measurement.
a Set up memory depth and time-base to display one complete SSC Cycle based on the
measured SSC modulation frequency in step 5.
b Acquire the signal with one complete SSC Cycle.
c Get the minimum of the FUNC2 filtered unit interval measurement trend to calculate the
maximum data rate:
Maximum Data Rate = 1/Minimum Unit Interval
d Get the maximum of the FUNC2 filtered unit interval measurement trend to calculate the
minimum data rate:
Minimum Data Rate = 1/Maximum Unit Interval
e Repeat step b,c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rate.
10 Calculate the SSC Modulation Deviation using the equation:
SSC Modulation Deviation = (Maximum Data Rate - Minimum Data Rate) / (Nominal Data
Rate) * 1E6
11 Report the measurement results.
PASS Condition
-5000ppm < SSC Modulation Deviation (ResultantSSC Range) < 0ppm
Table 104
DisplayPort Main Link Transmitter System Parameters
Symbol
Parameter
Min
Nom
Max
Down_Spread_Amplitude
Link clock down-spreading
0
-
0.5
Unit
%
Comments
Range: 0% ~ 0.5% when
down-spread enabled
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.16
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation deviation for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID
12200001 — SSC Deviation HF Variation Test (Informative)
Test Overview
The objective of this test is to verify that the SSC profile does not include any frequency deviation
that may exceed 1250 ppm/µsec. This test includes the use of the 2nd order Butterworth low-pass
filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of 10 full
SSC cycles.
Test Conditions for SSC Deviation HF Variation Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Deviation HF Variation Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
6
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
Set up the parameters for the SSC measurement.
a Set up memory depth and time-base to display one complete SSC cycle using the measured
SSC Modulation Frequency in Step 5.
b Acquire the signal with one complete SSC Cycles.
c Read the FUNC2 filtered unit interval measurement trend.
d Compute the slope using the “Sliding Window” with 1.00 µsec window width. Calculate the
slope using the equation:
Slope = [f(t) - f(t-1.00 µsec)/1.00 µsec]
e Repeat step b, c and d until you acquire 10 SSC Cycles.
f
7
Get the maximum value for the computed value of slope.
Report the measurement results.
PASS Condition
•
SSCt dF/dt < 1250ppm/µsec
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Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.17
Expected/Observable Results
The measured SSC deviation high frequency variation for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Post-Cursor 2 Verification Test (Informative)
Test ID
1279001 — Post Cursor 2 Verification Test - Level 1/Level 0 (Informative)
1279101 — Post Cursor 2 Verification Test - Level 2/Level 1 (Informative)
1279201 — Post Cursor 2 Verification Test - Level 3/Level 2 (Informative)
Test Overview
The objective of this test is to evaluate the effect of adding Post-Cursor 2 of the source waveform by
measuring the peak differential amplitude to assure accuracy of the Post-Cursor 2 settings.
Test Conditions for Post-Cursor 2 Verification Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
HBR2
SSC
Both SSC conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported subject to constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
All Post-Cursor 2 levels supported
Test Lane
Lane 0
Test Pattern
PCTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Post-Cursor 2 Verification Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
For a given Voltage Level, Pre-Emphasis Level and Post-Cursor 2 Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d Pattern fold the input signal based on the qualifying pattern 00101010 for the measurement of
voltage VT1010_PC2_LvlX_PP in the test pattern PLTPAT.
e Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1010_PC2_LvlX_H and Low Voltage VT1010_PC2_LvlX_L.
f
i
VT1010_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1010 portion of the qualifying pattern.
ii
VT1010_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1010 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1010_PC2_LvlX_PP using the equation:
VT1010_PC2_LvlX_PP = VT1010_PC2_LvlX_H - VT1010_PC2_LvlX_L
g Pattern fold the input signal based on the qualifying pattern 00011001100 for the
measurement of voltage VT1100_PC2_LvlX_PP in the test pattern PLTPAT.
h Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1100_PC2_LvlX_H and Low Voltage VT1100_PC2_LvlX_L.
i
i
VT1100_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1100 portion of the qualifying pattern.
ii
VT1100_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1100 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1100_PC2_LvlX_PP using the equation:
VT1100_PC2_LvlX_PP = VT1100_PC2_LvlX_H - VT1100_PC2_LvlX_L
j
Calculate the Post-Cursor 2 ratio using the equation:
Post-Cursor 2 RatioLvlX = VT1100_PC2_LvlX_PP / VT1010_PC2_LvlX_PP
2
Compare the pre-emphasis delta of Post-Cursor 2 Level with the limits by repeating Step 1 with
another Post-Cursor2 Level.
3
Calculate the pre-emphasis delta of Post-Cursor 2 Level using the equation:
Post-Cursor 2 Delta (Level 1 vs Level 0) = 20 * Log10[Post-Cursor 2 RatioLvl1 / Post-Cursor 2
RatioLvl0]
Post-Cursor 2 Delta (Level 2 vs Level 1) = 20 * Log10[Post-Cursor 2 RatioLvl2 / Post-Cursor 2
RatioLvl1]
Post-Cursor 2 Delta (Level 3 vs Level 2) = 20 * Log10[Post-Cursor 2 RatioLvl3 / Post-Cursor 2
RatioLvl2]
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Report the measurement results.
PASS Condition
Post Cursor 2 Verification Measurements
For Level 1 vs. Level 0 Pre-emphasis Post Cursor 2 settings: ResultantLvl0_to_Lvl1 < -0.45 dB
For Level 2 vs. Level 1 Pre-emphasis Post Cursor 2 settings: ResultantLvl1_to_Lvl2 < -0.5 dB
For Level 3 vs. Level 2 Pre-emphasis Post Cursor 2 settings: ResultantLvl2_to_Lvl3 < -0.6 dB
Table 105
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-PREEMP_POST2-DELTA
Parameter
Min
Delta of Pre-emphasis Post
Cursor2 Level 1 vs. Level 0
-0.45
Delta of Pre-emphasis Post
Cursor2 Level 2 vs. Level 1
Delta of Pre-emphasis Post
Cursor2 Level 3 vs. Level 2
Nom
Max
Unit
Comments
-
-
dB
Measured on 2nd TBIT at
Pre-emphasis Level 0
-0.5
-
-
dB
Support for Pre-emphasis
Post Cursor2 is optional
-0.6
-
-
dB
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2a, Section 3.3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis delta of Post-Cursor 2 for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Eye Diagram Test (TP3_EQ)
Test ID
For HBR
•
1211001 — Eye Diagram Test (TP3_EQ)
•
1211011 — Eye Diagram Test with No Cable Model (TP3_EQ)
For HBR2
•
1215001 — Eye Diagram Test (TP3_EQ)
•
1215011 — Eye Diagram Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the waveform, ensuring that the timing variables and
amplitude trajectories support the overall DP system objectives of the Bit Error Rate in data
transmission.
Test Conditions for Eye Diagram Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR (Informative) and HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
HBR — Level 2
HBR2 — Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
HBR — Level 0
HBR2 — Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
HBR — Level 0
HBR2 — Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
HBR—PRBS7
HBR2—HBR2CPAT
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure for HBR
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the jitter of the eye diagram using the Histogram.
9
Check for any signal trajectories that may have entered into the mask.
10 Report the measurement results.
Measurement Procedure for HBR2
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
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4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Pattern fold the equalized signal based on the High Level Voltage (VHIGH) random noise
configuration variable.
b Set up the vertical waveform histogram on the equalized signal to measure random noise of
High Level Voltage (VHIGH).
c Measure the High Level Voltage (VHIGH) random noise based on the standard deviation of the
waveform histogram.
d Pattern fold the equalized signal based on the Low Level Voltage (VLOW) random noise
configuration variable.
e Set up the vertical waveform histogram on the equalized signal to measure the random noise
of Low Level Voltage (VLOW).
f
Measure the Low Level Voltage (VLOW) random noise based on the standard deviation of the
waveform histogram.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge and right edge.
8
Set up the vertical waveform histogram on the equalized signal eye diagram to measure the eye
height from 0.375 UI to 0.625 UI.
9
Find the maximum eye height location of the eye diagram.
10 If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Set up the parameter of the jitter separation using the EZJIT Plus/Complete Software.
i
Load the jitter separation parameter into EZJIT Plus/Complete Software based on the
settings in the Configuration Variable.
ii
Acquire the signal until 1,000,000 edges are analyzed.
b Note the value of the jitter component from the EZJIT Plus/Complete Software.
11 Create the eye mask based on the following criteria:
a If you select more than one lane (2 lanes or 4 lanes DUT configuration), the eye mask height
and width is derate in the following manner, to include crosstalk as defined in DisplayPort 1.2b
Compliance Test Specification:
i
Eye Mask Width Derate (Crosstalk) = 0.04 UI
ii
Eye Mask Height Derate (Crosstalk) = 0.014V
b If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]: eye mask height and width is derate as below to comprehend the
noise/jitter extrapolated to BER 10-9 for an Eye Diagram Test (TP3_EQ) only acquiring 1e6 UI:
i
Calculate the Eye Mask Width Derate (Random Jitter) using the equation:
Eye Mask Width Derate (Random Jitter) = 2.5 * Random Jitterrms
ii
Calculate the Eye Mask Height Derate (Random Noise) using the equation:
VHIGH Eye Mask Height Derate (Random Noise) = 2.5 * VHIGH Random Noiserms
VLOW Eye Mask Height Derate (Random Noise) = 2.5 * VLOW Random Noiserms
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The factor 2.5 is the delta between BER 10-6 (9.507) and 10-9 (11.996) to
comprehend the noise/jitter extrapolated to BER 10-9 as the Eye Diagram
Test (TP3_EQ) only acquiring 1e6 UI.
BER
N
10-6
9.507
10-7
10.399
10-8
11.224
10-9
11.996
c Place the eye mask height at the point of the maximum eye height found in Step 9.
d Calculate the Eye Mask Width:
Eye Mask Width = Eye Width Specification (0.38 UI) + Eye Mask Width Derate (Crosstalk) + 2 *
Eye Mask Width Derate (Random Jitter)
e Calculate the Eye Mask Height:
Eye Mask Height = {Eye Height Specification (0.09 UI) + Eye Mask Height Derate (Crosstalk)}/2
+ VHIGH Eye Mask Height Derate (Random Noise)
Eye Mask Height = -{Eye Height Specification (0.09 UI) + Eye Mask Height Derate
(Crosstalk)}/2 - VLOW Eye Mask Height Derate (Random Noise)
12 Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram.
c Run the eye mask until 1,000,000 UI are folded.
13 Measure the eye height of the eye diagram using the Histogram.
14 Measure the jitter of the eye diagram using the Histogram.
15 Calculate the eye width based on the measured jitter of the eye diagram.
16 Check for any signal trajectories that may have entered into the mask.
17 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 106 shows the voltage and time coordinates for the mask
used for the eye diagram.
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Table 106
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 113
604
Bit Rate
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
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Table 107
15
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Figure 114
The Sink Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-25 for HBR and
Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Total Jitter Test (TP3_EQ)
Test ID
For HBR2:
•
1222001 — Total Jitter Test (TP3_EQ) — HBR2CPAT
•
1222011 — Total Jitter Test with No Cable Model (TP3_EQ) — HBR2CPAT
•
1221001 — Total Jitter Test (TP3_EQ) — D10.2
•
1221011 — Total Jitter Test with No Cable Model (TP3_EQ) — D10.2
Test Overview
The objective of this test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test (TP3_EQ)
606
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 108
Total Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.580 UI*
Ap-p
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
Table 109
Total Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.40 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured total jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Deterministic Jitter Test (TP3_EQ)
Test ID
For HBR2:
•
1236001 — Deterministic Jitter Test (TP3_EQ) — HBR2CPAT
•
1236011 — Deterministic Jitter Test with No Cable Model (TP3_EQ) — HBR2CPAT
•
1235001 — Deterministic Jitter Test (TP3_EQ) — D10.2
•
1235011 — Deterministic Jitter Test with No Cable Model (TP3_EQ) — D10.2
Test Overview
The objective of this test is to evaluate the deterministic jitter accompanying the data transmission.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Deterministic Jitter Test (TP3_EQ)
612
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Deterministic Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 110
Deterministic Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.49 UI
Ap-p
Table 111
Deterministic Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.25 UI
UI is Unit Interval.
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Test References
See:
For HBR2CPAT
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured deterministic jitter for the test signal at TP3_EQ shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
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Random Jitter Test (TP3_EQ)
Test ID
For HBR2:
•
1238001 — Random Jitter Test (TP3_EQ) — D10.2
•
1238011 — Random Jitter Test with No Cable Model (TP3_EQ) — D10.2
Test Overview
The objective of this test is to evaluate the random jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. The jitter is
separated into each jitter components and the random jitter is estimated to 10-9 BER based on the
Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Random Jitter Test (TP3_EQ)
618
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Random Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 112
Random Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
Ap-p
0.23 UI
UI is Unit Interval.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured random jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
622
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AC Common Mode Test (Informative)
Test ID
12110001 — AC Common Mode Test (Informative)
Test Overview
The objective of this test is to evaluate the AC Common Mode noise (unfiltered rms) of the differential
data line of the DP interface.
Test Conditions for AC Common Mode Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates are supported (RBR, HBR, HBR2)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis level supported subject to the constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for AC Common Mode Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Create FUNC3 signal, which is the common mode signal of the input single-ended signal.
4
If the filter is enabled [“Filter” configuration variable set to “High Pass Filter”, “Low Pass Filter” or
“None” (Default)]:
a Create FUNC4 signal, which is the filtered FUNC3 signal by applying the High Pass filter or
Low Pass filter on the FUNC3 signal based on the Configuration Variable.
5
6
Set up two display grids such that one grid displays the input single-ended signal while the other
grid displays the common mode signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
7
Set up the parameters for RMS voltage measurement of the common mode signal.
a Set up the Vrms measurement for the common mode signal.
b Acquire the signal until 100,000 edges are measured.
8
Get the mean for the Vrms measurement.
9
Report the measurement results.
PASS Condition
For RBR and HBR:
AC Common Mode Voltage < 20mV
For HBR2:
AC Common Mode Voltage < 30mV
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.10
• VESA DisplayPort Standard Version 1, Revision 2a, Section 9.2, Table 9-6
Expected/Observable Results
The measured AC common mode noise for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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Intra-Pair Skew Test (Informative)
Test ID
12100001 — Intra-Pair Skew Test (Informative)
Test Overview
The objective of this test is to evaluate the skew or time delay between respective sides of a
differential data lane in the DP interface.
Test Conditions for Intra-Pair Skew Test (Informative)
628
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR or HBR2)
SSC
Both SSC conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0 (Lane 0+ to Lane 0-)
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Intra-Pair Skew Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for DisplayPort MyDP 1.0 Source Tests" on
page 519 to complete the task flow for DUT setup along with configuring the Compliance
Application to run the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
4
Set up the parameters to perform High Level Voltage (VHIGH) and Low Level Voltage (VLOW) for
each input single-ended signal.
a Scale the vertical display of the input single-ended signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHIGH by measuring the average voltage at 0.06 UI to 0.75 UI of the High Level.
d Find VLOW by measuring the average voltage at 0.06 UI to 0.75 UI of the Low Level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHIGH + VLOW) / 2
5
Set up the parameters for the intra-pair skew measurement:
a Set up the measurement threshold for each single-ended data signal based on the measured
Transition Voltage.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) rising edge:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the intra-pair skew using the equation:
Intra-Pair Skew = {1/Number of Edges}
∑ {[(D+Transition_High - D-Transition_Low) + (D+Transition_Low - D-Transition_High)] / 2}
6
Report the measurement results.
PASS Condition
Intra-Pair Skew ≤ 30 ps
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Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.5
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured intra-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
16 MyDP 1.0 Sink Tests
Overview / 636
Sink Eye Diagram Test / 640
Sink Total Jitter Test / 647
Sink Non-ISI Jitter Tests / 653
16
MyDP 1.0 Sink Tests
Overview
Test Point Definition for DisplayPort MyDP 1.0 Sink Tests
NOTE
Sink Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Sink DUT at Test Point 3(TP3) as shown in Figure 115. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 115
Test Point 3 Connection for MyDP 1.0 Sink Tests
Table 113 defines the test point fixtures and instruments used for MyDP 1.0 Sink Tests:
Table 113
636
Test Point Fixtures and Instruments for MyDP 1.0 Sink Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
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Calibration of Stress Signal
For the calibration of the stress signal, you must test the stress signal in the manner shown in the
Figure 116 for RBR and Figure 117 for HBR and HBR2.
Figure 116
Test Point 3 Connection for Stress Signal Calibration of RBR
Figure 117
Test Point 3 Connection for Stress Signal Calibration of HBR and HBR2
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Table 114 defines the Test Point 3 Connections for Stress Signal Calibration:
Table 114
Test Point Connections for Stress Signal Calibration
Test Requirement
Device Used
Stress Signal Generator (SSG)
Bit Error Rate Tester
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Jitter Measurement Device (JMD)
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Sink Tests
Perform the following steps before you run the compliance tests on the sink device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 118).
Figure 118
638
Set Up tab on the DisplayPort Compliance Test App
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4
To test for compliance with Mobility DisplayPort 1.0 Standards, select MyDP 1.0 from the
drop-down options in the Test Specification area and select Physical Layer Tests in the Test Selection
area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for MyDP 1.0 Sink Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 119
Sample connection diagram for MyDP 1.0 Sink Tests
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Sink Eye Diagram Test
Test ID
12140001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the following specifications for degradation:
• Voltage Level:
•
90mV peak to peak +/- 10% for HBR2 at TP3_EQ (Table 3-18, DP1.2a)
•
150mV peak to peak +/- 10% for HBR at TP3_EQ (Table 3-25, DP1.2a)
•
46mV peak to peak +/- 10% for RBR at TP3 (Table 3-26, DP1.2a
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Eye Diagram Test
640
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Sink Tests" on page 638 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 115 shows the voltage and time coordinates for the mask
used for the eye diagram.
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Table 115
16
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 120
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
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Table 116
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Figure 121
The Sink Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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Sink Total Jitter Test
Test ID
12210001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Sink Tests" on page 638 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 117
Total Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
0.580 UI*
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
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Table 118
Total Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Sink Non-ISI Jitter Tests
Test ID
12220001 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non ISI jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR and HBR2)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2—HBR2CPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Sink Tests" on page 638 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 119
Non ISI Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
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Table 120
Non ISI Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Method of Implementation
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Cable Eye Diagram Test / 664
Cable Total Jitter Test / 670
Cable Non-ISI Jitter Test / 675
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Overview
Test Point Definition for MyDP 1.0 Cable Tests
NOTE
Cable Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Cable DUT at Test Point 3 (TP3) as shown in Figure 122. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 122
660
Test Point 3 Connection for MyDP 1.0 Cable Tests
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Table 121 defines the test point fixtures and instruments used for MyDP 1.0 Cable Tests:
Table 121
Test Point Fixtures and Instruments for MyDP 1.0 Cable Tests
Test Requirement
Device Used
Stimulus Instrument
Pulse Pattern Generator
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Table 122 defines the input signal parameters applied by the stimulus instrument at TP2:
Table 122
Input Signal Parameters by Stimulus Instrument
RBR
•
•
•
•
Reference Table 3-22 and Table 3-24, DP 1.2a
Edge Rate (20-80): 155-165ps (260mUI)
Eye Height: 400mV
Total Jitter: 270mUI
• ISI: 100mUI
• Random Jitter (rms): 7.9mUI
• Sinusoidal Jitter: ~75mUI at 20MHz (Adjust to achieve Total Jitter)
HBR
•
•
•
•
Reference Table 3-22 and Table 3-23, DP 1.2a
Edge Rate (20-80): 90-100ps (260mUI)
Eye Height: 350mV
Total Jitter: 420mUI
• ISI: 144mUI
• Random Jitter (rms): 13.2mUI
• Sinusoidal Jitter: ~117mUI at 20MHz (Adjust to achieve Total Jitter)
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Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Cable Tests
Perform the following steps before you run the compliance tests on the cable device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Table 123).
Figure 123
662
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with Mobility DisplayPort 1.0 Standards, select MyDP 1.0 from the
drop-down options in the Test Specification area and select Physical Layer Tests in the Test Selection
area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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17
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for MyDP 1.0 Cable Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 124
Sample connection diagram for MyDP 1.0 Cable Tests
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Cable Eye Diagram Test
Test ID
12150001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
664
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 122
Crosstalk Signal Parameter
Quarter-rate clock signal (D24.3 pattern) is injected to lanes other than the lane under
test. The characteristics of the aggressor signals are:
Pattern—D24.3
Bit Rate—(Same as lane under test)
Voltage Amplitude—(Same as lane under test)
• RBR-400mV
• HBR-350mV
Edge Rate (20-80)—130ps at TP3
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Cable Tests" on page 662 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 123 shows the voltage and time coordinates for the mask
used for the eye diagram.
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Table 123
17
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 125
The Cable Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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Cable Total Jitter Test
Test ID
12230001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
670
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 122
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Cable Tests" on page 662 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 124
Total Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Cable Non-ISI Jitter Test
Test ID
12240001 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non-ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. This
measurement is a data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 122
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Cable Tests" on page 662 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PPASS Condition
Table 125
Non ISI Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non-ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
18 MyDP 1.0 AUX Channel Tests
Overview / 682
Setting Up for AUX PHY and Inrush Tests / 685
AUX Channel Unit Interval Test / 693
AUX Channel Eye Test / 695
AUX Channel Peak-to-Peak Voltage Test / 697
AUX Channel Eye Sensitivity Calibration Test / 699
AUX Channel Eye Sensitivity Test / 701
18
MyDP 1.0 AUX Channel Tests
Overview
Test Point for MyDP 1.0 AUX Channel Tests
You must test the Source devices at Test Point 2 (TP2) while the Sink devices must be tested at Test
Point 3 (TP3). See Figure 126.
Figure 126
Test Points for MyDP 1.0 AUX Channel Tests
Table 126 defines the test point fixtures and instruments used for MyDP 1.0 AUX Channel Tests:
Table 126
Test Point Fixtures and Instruments for MyDP 1.0 AUX Channel Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Stimulus
Stimulus must be applied to the DUT to cause AUX Channel transactions to occur. This
stimulus shall not be included in or affect the measurements.
Reference Sink needed as stimulus for the Source DUT:
• Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Reference Source needed as stimulus for the Sink DUT:
• Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 AUX Channel Tests
Perform the following steps before you run the compliance tests on the AUX channel device:
682
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 126).
Figure 127
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with Mobility DisplayPort 1.0 Standards, select MyDP 1.0 from the
drop-down options in the Test Specification area and select AUX PHY and Inrush Tests in the Test
Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Setting Up for AUX PHY and Inrush Tests
Perform the following steps before you run the Auxiliary Channel and Inrush tests on the source or
sink device:
1
After you select AUX PHY and Inrush Tests, click the Test Setup button on the Set Up tab.
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2
On the DUT/Connectivity page, select Source or Sink in the DUT Type area. In the Reference Device
area, select Yes if a reference sink/source is attached to device under test during testing. Click
Next.
3
On the Connection Setup page, depending on the probe connection you are using, select either
Differential Probe or Single-Ended in the Connection Type area and in the Connection area, select the
oscilloscope channel that is connected to the Auxiliary Lane.
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On the Trigger Setup page, define the oscilloscope parameters to trigger on an Auxiliary signal
during testing.
Hold Off Time — The oscilloscope minimum hold off time before triggering the next waveform. Note
that any Auxiliary transaction from the source must receive a reply from the sink in 400 us, else such
a transaction is considered a timeout. Hold off time, in such cases, represents the minimum idle time
before each AUX transaction is initialized. It is defaulted to 300 us which is a safe timing value for
most devices tested in the lab. Most devices respond much faster than 300 us.
Trigger Level — The AUX channel signal level on which to trigger. Note that for a bi-directional signal
(where a reference sink is attached), you must set the trigger level such that it crosses both the
source command and the sink reply signal. Figure shows correct and incorrect trigger levels.
Figure 128
Correct Trigger Level
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Figure 129
Incorrect Trigger Level
Vertical Scale — The oscilloscope vertical scale. Set the vertical to make sure that all signals are visible
on the oscilloscope display.
Offset — Set the offset so that the center point is aligned with the center of the oscilloscope display.
Upper Threshold/Lower Threshold — The threshold level of signal must be set properly so that both
upper and lower thresholds cross both the source and sink signals when the DUT is attached with a
reference sink. The threshold levels are important parameters because they are used for edge
detection when decoding a source command from a sink reply.
Figure 130
688
Correct Threshold set
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Figure 131
18
Wrong Thresholds set
c On the Trigger Setup page, you may click the Learn button, which guides you through getting
the trigger setup parameters. However, please note that the learning guide may not
necessarily work many a times because the actual Auxiliary signals may vary for different
manufacturers. Keysight recommends that you must check to make sure that the parameters
are correctly set as previously described.
d Click Verify and follow the instructions, if you wish to check the AUX Channel trigger.
e You may Save or Load the trigger setup configuration as a *.tsf file.
5
On the Acquisition Mode page, either Finish the setup wizard or enable Offline Mode, which is
de-selected, by default. Offline Mode lets you save the waveform files so that you can avoid the
manual process to initiate Auxiliary transactions during the time of test runs.
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6
If you enable Offline Mode, define the number of waveforms to be saved. If required, click Start
Acquisition to start capturing and saving waveforms.
7
Click Finish to close the setup wizard. The Set Up tab displays.
8
Click the Select Tests tab and select the AUX Channel tests you want to run.
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Probing/Connection Set Up for AUX Channel Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests. When performing the Source AUX
Channel tests, a Reference Sink device is required. Similarly, when performing the Sink AUX Channel
tests, a Reference Source device is required.
Figure 132
Sample connection diagram for source AUX channel tests with source DUT connected to a reference sink
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Figure 133
Sample connection diagram for source AUX channel tests without connecting to a reference sink
Figure 134
Sample connection diagram for sink AUX channel tests with sink DUT connected to a reference source
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AUX Channel Unit Interval Test
Test ID
125000 — AUX Channel Unit Interval Test (Source)
125010 — AUX Channel Unit Interval Test (Sink)
Test Overview
The objective of the test is to evaluate the AUX Channel waveform, ensuring that the overall variation
of the Manchester transaction Unit Interval stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Set up the parameter of the measurement trend:
a Set up the Unit Interval measurement for the differential AUX Channel signal.
b Set up the frequency measurement for the Clock signal.
c Set up the measurement trend.
6
Set up the waveform Histogram on the measurement trend:
a Initialize AUX Channel transactions and acquire the differential AUX Channel signal.
b Identify the first and the last points for the desired transaction.
c Zoom-in on the desired transaction.
d Set up the Vertical Waveform Histogram on the measurement trend within the desired
transaction.
e Obtain the measurement for the mean, maximum and minimum values of the waveform
Histogram.
7
Repeat step 6 ten times.
8
Report the measurement results.
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PASS Condition
Manchester Transaction Unit Interval (UIMAN):
Minimum = 0.4 µsec
Maximum = 0.6 µsec
Test References
See:
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-2
Expected/Observable Results
The measured unit interval for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Test
Test ID
125001 — AUX Channel Eye Test (Source)
125011 — AUX Channel Eye Test (Sink)
Test Overview
The objective of this test is to evaluate the transmitter AUX Channel waveform, ensuring that the
timing variables and amplitude trajectories support the overall DP system objectives of the Bit Error
Rate in data transmission.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the waveform Histogram on the AUX Channel eye diagram to measure the left edge and
the right edge.
8
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
9
Check for any signal trajectories entering into the mask.
10 Report the measurement results.
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PASS Condition
PASS Value = 290mV_diff_pp or higher
FAIL Value = lower than 290mV_diff_pp
Table 127
Eye Mask Vertices for AUX Channel for Manchester Transactions
Mask Point
Time (from EYE Center)
Minimum Voltage Value at Six Vertices (mV)
1
-185ns
0
2
-135ns
145
3
135ns
145
4
185ns
0
5
135ns
-145
6
-135ns
-145
Figure 135
AUX Channel EYE Mask for Manchester Transactions
Mask Test: Zero mask failures.
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-1 and Table 2-2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2.6, Figure 3-29 and Table 3-8
Expected/Observable Results
The measured eye diagram for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
The rendered eye diagram shall have no signal trajectories entering the mask area.
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AUX Channel Peak-to-Peak Voltage Test
Test ID
125002 — AUX Channel Peak-to-Peak Voltage Test (Source)
125012 — AUX Channel Peak-to-Peak Voltage Test (Sink)
Test Overview
The objective of the test is to evaluate the transmitter AUX Channel Waveform, ensuring that the
peak-to-peak voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform Histogram on the AUX Channel eye diagram to measure the left
edge and the right edge.
8
If you have selected the “AUX Channel Eye Test” under the Select Tests tab of the compliance
application:
a Set up the parameter of the Mask Test:
i
Load the eye mask based on the settings in the Configuration Variable.
ii
Center the eye mask at the middle of the eye diagram based on the measured left edge
and right edge.
iii Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
b Check for any signal trajectories entering into the mask.
9
Report the measurement results.
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PASS Condition
Table 128
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage at a transmitting device (VAUX-DIFFp-p)
0.29V
1.38V
Test References
See:
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the transmitter AUX Channel signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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AUX Channel Eye Sensitivity Calibration Test
Test ID
125021 — AUX Channel Eye Sensitivity Calibration (Reference Sink)
125031 — AUX Channel Eye Sensitivity Calibration (Reference Source)
Test Overview
The objective of this test is to calibrate the peak-to-peak voltage of the transmitter AUX Channel
waveform by reference device (reference source or reference sink), ensuring that the peak-to-peak
voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
6
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
7
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
8
Set up the waveform Histogram on the AUX Channel eye diagram:
a Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
b Set up the vertical waveform Histogram of width 0.6 UI at the center of the AUX Channel eye
diagram.
c Measure the VTOP and VBASE using the waveform Histogram mean value.
9
Repeat Step 8 three times.
10 Report the measurement results.
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PASS Condition
Table 129
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage for AUX Channel Eye Sensitivity
0.24V
0.28V
Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the AUX Channel signal by reference device (reference
source or reference sink) shall be within the conformance limits as specified in the specification
mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Sensitivity Test
Test ID
125041 — AUX Channel Eye Sensitivity Test (Source)
125051 — AUX Channel Eye Sensitivity Test (Sink)
Test Overview
The objective of the test is to evaluate the sensitivity to the AUX Channel Eye Opening of the DUT as
per the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
6
Check if the reference device could detect the transaction or not.
7
Decode the AUX Channel signal and check whether the transaction passed or failed.
8
Report the measurement results.
PASS Condition
Determine whether the AUX Channel communication is successful. For example, the Transmitter
DUT sends an AUX Request to the Reference Receiver. The Reference Receiver acknowledges and
the Transmitter DUT responds to the to indicate that the acknowledgment was successfully received.
PASS = No errors observed in the response
FAIL = One or more errors observed
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Test References
See:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.1 and
Section 7.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured AUX Channel transaction shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
702
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Compliance Test Application
Method of Implementation
19 MyDP 1.0 Inrush Tests
Overview / 704
Inrush Energy Power Test / 707
Inrush Peak Current Test / 709
19
MyDP 1.0 Inrush Tests
Overview
This section describes the normative and informative inrush tests for compliance verification of
Mobility DisplayPort source and sink, which is a power consumer.
Test Point for MyDP 1.0 Inrush Tests
The test fixture for inrush tests implements the schematic shown in Figure 136.
Figure 136
Schematics for testing a Power Consumer Device
The test fixture must be designed and used according to the following guidelines:
• A high gate voltage FET on the MyDP_PWR line is recommended to allow a fast connect
capability, which allows a single connection event for testing. Without such an arrangement,
multiple connections will be required to obtain a reasonable “worst-case” attachment event.
• Connection length between the power supply and the test fixture must be minimized. A
maximum of four inches is recommended.
• The power supply must have enough outrush capability as to not negatively affect the test
fixture’s outrush capability.
• The power supply must be run at 5.5V (5.0V + 10%) read across VC.
Any Power Consumer test fixture must be calibrated using the Power User test fixture, as shown in
Figure. Testing with the two fixtures combined should result in the approximate values given below. If
required, the component values on the Power Consumer test fixture should be adjusted to match the
expected results.
For Source:
• VC steady before connection = 5.5V
• Inrush Current = ~9.0A
For Sink:
• VC steady before connection = 3.6V
• Inrush Current = ~13.0A
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Setting Up the DisplayPort Compliance Test Application for MyDP 1.0 Inrush Tests
Perform the following steps before you run the compliance tests on the DUT:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 137).
Figure 137
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with Mobility DisplayPort 1.0 Standards, select MyDP 1.0 from the
drop-down options in the Test Specification area and select AUX PHY and Inrush Tests in the Test
Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests. Refer to “Setting Up for AUX PHY and
Inrush Tests" on page 685 to know in detail how to set up the DUT for Inrush Tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
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MyDP 1.0 Inrush Tests
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Inrush Energy Power Test
Test ID
127000 — Inrush Energy Power Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Power (Ps) = Id*Vs
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush energy power measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Current ResultantPEAK_CURRENT_Power_Consumer < 9 Amps
Test References
See:
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MyDP 1.0 Inrush Tests
For Source:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.5
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
For Sink:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 3.4
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
Expected/Observable Results
The measured worst case inrush energy power for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Inrush Peak Current Test
Test ID
127001 — Inrush Peak Current Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Power (Ps) = Id*Vs
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush peak current measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Current ResultantPEAK_CURRENT_Power_Consumer < 9 Amps
Test References
See:
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MyDP 1.0 Inrush Tests
For Source:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.5
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
For Sink:
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 3.4
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
Expected/Observable Results
The measured worst case inrush peak current for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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Compliance Test Application
Method of Implementation
20 SlimPort Source Tests
Overview / 712
Source Eye Diagram Test / 719
Source Total Jitter Test / 726
Source Non-ISI Jitter Test / 731
Source Non Pre-Emphasis Level Test / 736
Source Pre-Emphasis Level Test / 744
Source Non Transition Voltage Range Measurement Test / 752
Source Peak to Peak Voltage Test / 759
Source Main Link Frequency Compliance Test / 764
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test / 770
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test / 776
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative) / 782
Post-Cursor 2 Verification Test (Informative) / 788
Eye Diagram Test (TP3_EQ) / 794
Total Jitter Test (TP3_EQ) / 803
Deterministic Jitter Test (TP3_EQ) / 809
Random Jitter Test (TP3_EQ) / 815
AC Common Mode Test (Informative) / 820
Intra-Pair Skew Test (Informative) / 825
20
SlimPort Source Tests
Overview
This section describes the normative and informative tests for compliance verification of SlimPort
source, sink and cable DUTs.
Test Point Definition for SlimPort
Five different test points are identified for the physical layer measurement. See Figure 138.
Figure 138
Test Points in a DisplayPort InterConnect System
Table 130 defines the Test Points used for SlimPort Tests:
Table 130
Test Points for DisplayPort Tests
Test Point
Description
TP1
At the pins of the Transmitter Device
TP2
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Source device
TP3
At the test interface on a test access fixture as close as possible to the DP mated
connection to a Sink device
TP3_EQ
At TP3, when a defined cable model with equalizer is applied. There are two defined
cable models:
• Worst Cable Model as defined in VESA DisplayPort 1.2a Standard,
• Zero length, zero loss cable. The equalizer is also defined in VESA DisplayPort 1.2a
Standard
TP4
At the pins of a receiving device
Cable Models
The two cable models defined in VESA DisplayPort 1.2a Standard are:
1
Worst Case Cable Model—To achieve the TP3_EQ signal with the worst case cable model:
•
Acquire the signal at TP2.
•
Embed the TP2 signal with a “worst case” HBR cable model using an InfiniiSim Waveform
Transformation Toolset software to emulate the insertion loss as defined in Figure 4-10 of the
VESA DisplayPort 1.2a Standard.
• For the DisplayPort Compliance Test Application, the “CIC_rev0p6.s4p” cable model transfer
function is used.
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•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
2
Zero Length Cable Model—To achieve the TP3_EQ signal with the zero length cable model:
•
Acquire the signal at TP2.
•
No cable model is embedded for the Zero Length cable model.
•
Finally, apply the HBR or HBR2 equalization using the Serial Data Equalization software as
defined in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a
Standard.
20
Equalization
When equalization is required, use the CTLE (Continuous Time Linear Equalization) transfer function,
as given in Figure 3-40 (for HBR) and Figure 3-41 (for HBR2) of the VESA DisplayPort 1.2a Standard.
For main link, use the CTLE model with the following transfer function for HBR (2.7 Gbps):
Figure 139
Transfer Function of the CTLE model for HBR
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Table 131
CTLE Model for HBR
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.725 GHz
0.725 GHz
Pole 1 Frequency
1.35 GHz
1.35 GHz
Pole 2 Frequency
2.5 GHz
2.5 GHz
For main link, use the CTLE model with the following transfer function for HBR2 (5.4 Gbps):
Figure 140
Table 132
Transfer Function of the CTLE model for HBR2
CTLE Model for HBR2
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
0.64 GHz
0.64 GHz
Pole 1 Frequency
2.7 GHz
2.7 GHz
Pole 2 Frequency
4.5 GHz
4.5 GHz
Pole 3 Frequency
13.5 GHz
13.5 GHz
For main link, use the following CTLE parameters for HBR25 (6.75 Gbps):
714
•
DC-Gain = 1.0
•
Zero = 1 GHz
•
Pole1 = 3.75 GHz
•
Pole2 = 13.5 GHz
•
Pole3 > 13.5 GHz
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Table 133
20
CTLE Model for HBR25
CTLE Parameter
Worst Case Cable Model
Zero Length Cable Model
Gain
1.0
1.0
Zero Frequency
1.0 GHz
2.0 GHz
Pole 1 Frequency
5.625 GHz
3.375 GHz
Pole 2 Frequency
13.5 GHz
5.625 GHz
Pole 3 Frequency
13.5 GHz
16.875 GHz
Clock Recovery
When Clock Recovery is required, the clock recovery technique follows the definition of the receiver
PLL as defined in Section 3.5.3.5 of the VESA DisplayPort 1.2a Standard. For main link, use the
second-order clock recovery function with a closed loop tracking bandwidth and damping factor,
with respect to the PRBS7 pattern, as shown in Table 134:
Table 134
Main Link Second-Order Clock Recovery Function
Bit Rate
Band wid th
Damping Factor
HBR25 (6.75 Gbps)
10 MHZ
1.00
HBR2 (5.4 Gbps)
10 MHz
1.00
HBR (2.7 Gbps)
10 MHz
1.51
RBR (1.62 Gbps)
5.4 MHz
1.51
Test Point Definition for SlimPort Source Tests
Test the Source DUT at Test Point 2 (TP2) as shown in Figure 141.
Figure 141
Test Point 2 Connection for SlimPort Source Tests
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SlimPort Source Tests
Use MyDP Test Fixtures (MyDP-to-DP type or MyDP-to-SMA type) to perform PHY compliance tests
specific to SlimPort. Figure 142 shows the layout of a MyDP passive cable adapter or a MyDP protocol
converter:
Figure 142
Schematics of SlimPort to SMA Test Fixtures used for PHY Compliance Tests
Table 135 defines the test point fixtures and instruments used for SlimPort (MyDP HBR25) Source
Tests:
Table 135
Test Point Fixtures and Instruments for SlimPort (MyDP HBR25) Source Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests
Perform the following steps before you run the compliance tests on the source device:
716
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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SlimPort Source Tests
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20
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 143).
Figure 143
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with SlimPort Standards, select MyDP HBR25 from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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SlimPort Source Tests
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for SlimPort Source Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 144
718
Sample connection diagram for SlimPort Source Tests
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
Source Eye Diagram Test
Test ID
1210001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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20
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure VTOP and VBASE of the input signal using the pattern folding.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the input signal eye diagram to measure the left
edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the eye height of the eye diagram using the Histogram.
9
Measure the jitter of the eye diagram using the Histogram.
10 Calculate the eye width based on the measured jitter of the eye diagram.
11 Check for any signal trajectories that may have entered into the mask.
12 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 136 shows the voltage and time coordinates for the mask
used in the eye diagram.
Figure 145
Eye Mask of Source at 6.75G
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Table 136
Eye Diagram Mask Coord inates
Mask Point
Bit Rate
Red uced (1.62 Gb/s)
High (2.7 Gb/s)
1
0.127, 0.000
0.210, 0.000
2
0.291, 0.160
0.355, 0.140
3
0.500, 0.200
0.500, 0.175
4
0.709, 0.200
0.645, 0.175
5
0.873, 0.000
0.790, 0.000
6
0.709,-0.200
0.645,-0.175
7
0.500,-0.200
0.500,-0.175
8
0.291,-0.160
0.355,-0.140
Figure 146
The Source Eye Mask
Mask Test: Zero mask failures.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-24 for RBR and
Table 3-23 for HBR
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Expected/Observable Results
The measured eye diagram for the source degraded signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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SlimPort Source Tests
Source Total Jitter Test
Test ID
1220001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
726
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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20
728
SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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20
SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Report the measurement results.
PASS Condition
Table 137
Total Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.294 UI
0.420 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.180 UI
0.270 UI
UI is Unit Interval.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
730
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Source Non-ISI Jitter Test
Test ID
1230001 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the amount of Non ISI jitter accompanying the data
transmission.
The jitter is separated into each jitter components based on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
RBR, HBR
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All Voltage Levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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20
SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
732
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
5
Note the jitter component value from the EZJIT Plus/Complete Software.
6
Calculate the Non ISI jitter using the following equation:
Non ISI Jitter = TJ - ISI
7
Report the measurement results.
PASS Condition
Table 138
Non-ISI Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.260 UI
0.276 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.160 UI
0.210 UI
UI is Unit Interval.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.11
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
SlimPort Source Tests
Source Non Pre-Emphasis Level Test
Test ID
For RBR and HBR:
•
1261001 — Non Pre-Emphasis Level Test (Swing 1/Swing 0)
•
1262001 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263001 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
For HBR2 and HBR25:
•
1264101 — Non Pre-Emphasis Level Test (Swing 2/Swing 0)
•
1262101 — Non Pre-Emphasis Level Test (Swing 2/Swing 1)
•
1263101 — Non Pre-Emphasis Level Test (Swing 3/Swing 2)
Test Overview
The objective of this test is to ensure that the system budget elements are obeyed and to ensure that
the level settings are monotonic so that the sink relies on the source to incrementally increase upon
request by the sink.
Test Conditions for Non Pre-Emphasis Level Test
736
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions are supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2 and HBR25 — PLTPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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738
SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
SlimPort Source Tests
Measurement Procedure
1
For Voltage Level A with no pre-emphasis level:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_Lvl0_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 147
740
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
High Voltage measurement for RBR and HBR
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
Figure 148
20
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR25 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level 0 (non pre-emphasis level):
•
The transition voltage measurement, VT_Lvl0_H and VT_Lvl0_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_Lvl0_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_Lvl0_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 149
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
SlimPort Source Tests
j
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_Lvl0_PP = VT_Lvl0_H - VT_Lvl0_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_Lvl0_PP = VN_Lvl0_H - VN_Lvl0_L
2
Repeat Step 1 for Voltage Level B with no pre-emphasis level.
3
Calculate the non pre-emphasis level output voltage ratio using the equation:
Non Pre-Emphasis Level = 20 * Log10[Voltage Level A VN_Lvl0_PP / Voltage Level B VN_Lvl0_PP]
4
Report the measurement results.
PASS Condition
For each level setting testes, the following equation should be used:
Resultant = 20 * Log10[VoltagePeak-Peak_LevelA / VoltagePeak-Peak_LevelB]
Table 139
Compared Levels
Measurement#
Vol tagePeak-Peak_LevelA
VoltagePeak-Peak_LevelB
1
Level 1 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
2
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
3*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
4
Level 2 (0 dB Pre-emphasis nominal)
Level 0 (0 dB Pre-emphasis nominal)
5
Level 2 (0 dB Pre-emphasis nominal)
Level 1 (0 dB Pre-emphasis nominal)
6*
Level 3 (0 dB Pre-emphasis nominal)
Level 2 (0 dB Pre-emphasis nominal)
RBR & HBR
HBR2 and HBR25
* if device optionally capable of Level 3
The resultants specifications are as identified below:
Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB
Measurement 3: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 4: 5.2 dB ≤ Resultant ≤ 6.9 dB
Measurement 5: 1.6 dB ≤ Resultant ≤ 3.5 dB
Measurement 6: 1 dB ≤ Resultant ≤ 4.4 dB
742
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
Table 140
20
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-OUTPUT-RATIO_RBR_HBR
VTX-OUTPUT-RATIO_HBR2
Parameter
Min
Nom
Max
Unit
Ratio of Output Voltage
Level 1/Level 0
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 1
0.1
-
5.1
dB
Ratio of Output Voltage
Level 3/Level 2
0.8
-
6.0
dB
Ratio of Output Voltage
Level 2/Level 0
5.2
-
6.9
dB
Ratio of Output Voltage
Level 2/Level 1
1.6
-
3.5
dB
Ratio of Output Voltage
Level 3/Level 2
1
-
4.4
dB
Comments
Measured on non-transition
bits at Pre-emphasis level 0
setting
Measured on non-transition
bits at Pre-emphasis level 0
setting
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level ratio of the non pre-emphasis level test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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743
20
SlimPort Source Tests
Source Pre-Emphasis Level Test
Test ID
For RBR and HBR:
•
1270001 — Pre-Emphasis Level Test
For HBR2 and HBR25:
•
1270501 — Pre-Emphasis Level Test
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Test Conditions for Pre-Emphasis Level Test
744
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR25 — PLTPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
745
20
746
SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Pre-Emphasis Level Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
SlimPort Source Tests
Measurement Procedure
1
For a given Voltage Level and a Pre-Emphasis Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 150
748
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
High Voltage measurement for RBR and HBR
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
Figure 151
20
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR25 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 152
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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20
SlimPort Source Tests
j
Calculate the peak-to-peak value of the transition voltage using the equation:
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
l
Calculate the pre-emphasis level using the equation:
Pre-EmphasisLvlX = 20 * Log10[VT_LvlX_PP / VN_LvlX_PP]
2
For Pre-Emphasis Level 0 (no pre-emphasis level), the result for Pre-EmphasisLvl0 is compared
with the maximum pre-emphasis disabled limit.
3
Repeat Step 1 for the next Pre-Emphasis level and for each Pre-Emphasis levels, compare the
pre-emphasis delta with the pre-emphasis delta limits.
4
Calculate the pre-emphasis delta using the equation:
Pre-Emphasis Delta (Level 1 vs Level 0) = Pre-EmphasisLvl1 - Pre-EmphasisLvl0
Pre-Emphasis Delta (Level 2 vs Level 1) = Pre-EmphasisLvl2 - Pre-EmphasisLvl1
Pre-Emphasis Delta (Level 3 vs Level 2) = Pre-EmphasisLvl3 - Pre-EmphasisLvl2
5
Report the measurement results.
PASS Condition
Pre-emphasis values for the Level 0 (OFF) state (Normative)
Level 0 (OFF) Pre-emphasis measurement:
Resultant = 20 * Log [VoltageT_Lvl0_PP / VoltageN_Lvl0_PP] for all supported levels.
Level 0 (OFF) Pre-emphasis Measurement condition: +0.25 dB > Resultant
Pre-emphasis Delta values for:
a Level 1 vs. Level 0 Pre-emphasis settings (NORMATIVE)
b Level 2 vs. Level 1 Pre-emphasis settings (NORMATIVE)
c Level 3 vs. Level 2 Pre-emphasis settings (NORMATIVE)
Pre-emphasis Delta measurements:
•
Level 1 vs. Level 0
Resultant = 20 * Log [VoltageT_Lvl1_PP / VoltageN_Lvl1_PP] - 20 * Log [VoltageT_Lvl0_PP /
VoltageN_Lvl0_PP] for Voltage Swing Levels 0, 1 and 2.
•
Level 2 vs. Level 1
Resultant = 20 * Log [VoltageT_Lvl2_PP / VoltageN_Lvl2_PP] - 20 * Log [VoltageT_Lvl1_PP /
VoltageN_Lvl1_PP] for Voltage Swing Levels 0 and 1.
•
Level 3 vs. Level 2
Resultant = 20 * Log [VoltageT_Lvl3_PP / VoltageN_Lvl3_PP] - 20 * Log [VoltageT_Lvl2_PP /
VoltageN_Lvl2_PP] for Voltage Swing Level 0, if supported.
750
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
Table 141
20
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
VTX-PREEMP-OFF
Maximum Pre-emphasis
when disabled
-
-
0.25
dB
Delta of Pre-emphasis
Level 1 vs. Level 0
2
-
-
dB
Delta of Pre-emphasis
Level 2 vs. Level 1
1.6
-
-
dB
Delta of Pre-emphasis
Level 3 vs. Level 2
1.6
-
-
dB
VTX-PREEMP-DELTA
Min
Nom
Max
Unit
Comments
Pre-emphasis Level 0 setting
must not show any
pre-emphasis at TP2 to
prevent link training issues.
Applies to all valid voltage
settings. Measured at
Pre-emphasis Post Cursor2
Level 0.
Support for Pre-emphasis
Level 3 is optional.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis level or pre-emphasis delta for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
751
20
SlimPort Source Tests
Source Non Transition Voltage Range Measurement Test
Test ID
For RBR and HBR:
•
1272001 — Non Transition Voltage Range Measurement (Swing 0)
•
1273001 — Non Transition Voltage Range Measurement (Swing 1)
•
1274001 — Non Transition Voltage Range Measurement (Swing 2)
For HBR2 and HBR25:
•
1272101 — Non Transition Voltage Range Measurement (Swing 0)
•
1273101 — Non Transition Voltage Range Measurement (Swing 1)
•
1274101 — Non Transition Voltage Range Measurement (Swing 2)
Test Overview
The objective of this test is to evaluate the effect of pre-emphasis of the source waveform by
measuring the peak differential amplitude to assure accuracy of the pre-emphasis settings.
Comparisons are also made for the Level 0 transition state as well as non-transition levels.
Test Conditions for Non Transition Voltage Range Measurement Test
752
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR25— PLTPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Source Tests
20
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non Transition Voltage Range Measurement Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
For a given Voltage Level, repeat the following steps for all pre-emphasis levels subjected to
constraints specified in Table 3-1 of the VESA DisplayPort 1.2a Standard:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d For RBR and HBR using the test pattern PRBS7:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 10111111
•
VL — 1010000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 6th bit of the seven successive transmitted
ones of the pattern while VN_LvlX_L is the average of the Low voltage over two UI ending at
the 50% point of the 4th bit of the four successive transmitted zeros of the pattern.
Figure 153
756
High Voltage measurement for RBR and HBR
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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Figure 154
20
Low Voltage measurement for RBR and HBR
e For HBR2 and HBR25 using the test pattern PLTPAT:
i
The qualifying pattern in the test pattern PRBS7 for VH and VL is:
•
VH — 011111
•
VL — 100000
ii
For a given voltage level and pre-emphasis level (LvlX):
•
The transition voltage measurement, VT_LvlX_H and VT_LvlX_L are the average values over
the 40% to 70% UI points in the transition bit.
•
The non-transition voltage measurement, VN_LvlX_H is the average of the High voltage
over three UI ending at the 50% point of the 5th bit of the five successive transmitted ones
of the pattern while VN_LvlX_L is the average of the Low voltage over three UI ending at the
50% point of the 5th bit of the five successive transmitted zeros of the pattern.
Figure 155
f
High Voltage and Low Voltage measurement for HBR2
Fold the pattern of the input signal based on the qualifying pattern for VH, as shown above.
g Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the High voltage.
h Fold the pattern of the input signal based on the qualifying pattern for VL, as shown above.
i
Set up the vertical waveform histogram on the input signal at the point specified earlier, so as
to measure the transition voltage and the non-transition voltage of the Low voltage.
j
Calculate the peak-to-peak value of the transition voltage using the equation:
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SlimPort Source Tests
VT_LvlX_PP = VT_LvlX_H - VT_LvlX_L
k Calculate the peak-to-peak value of the non-transition voltage using the equation:
VN_LvlX_PP = VN_LvlX_H - VN_LvlX_L
2
Calculate the non transition voltage range using the equation:
Non Transition Voltage Range = Minimum [(VN_LvlX_PP) / (VN_Lvl0_PP)]
where, VN_LvlX_PP) refers to all supported pre-emphasis levels (Level1, Level2, Level3 and so on
up to Level X).
3
Report the measurement results.
PASS Condition
Non-Transition Voltage Range Measurements
For Level 2 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 1 voltage setting: Resultant > 0.708 OR 20*log(Resultant) > -3dB
For Level 0 voltage setting: Resultant > 0.85 OR 20*log(Resultant) > -1.4dB
Table 142
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-DIFF_REDUCTION
Parameter
Min
Nom
Max
Unit
Non-transition reduction
Output Voltage Level 2
-
-
3
dB
Non-transition reduction
Output Voltage Level 1
-
-
3
dB
Non-transition reduction
Output Voltage Level 0
-
-
1.4
dB
Comments
VTX-DIFF at each non-zero
nominal pre-emphasis level
must not be lower than the
specified amount less than
VTX-DIFF at the zero nominal
pre-emphasis level.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured output voltage level reduction of the non transition bit for the test signal shall be
within the conformance limits as specified in the specification mentioned under the “PASS Condition”
section for this test.
758
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Source Peak to Peak Voltage Test
Test ID
For RBR and HBR:
•
1266001 — Peak to Peak Voltage Test
For HBR2 and HBR25:
•
1266101 — Peak to Peak Voltage Test
Test Overview
The objective of this test is to evaluate the maximum differential peak to peak voltage.
Test Conditions for Peak to Peak Voltage Test
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels are supported with constraints specified in Table 3-1 of the
VESA DisplayPort 1.2a Standard.
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR — PRBS7
HBR2, HBR25— PLTPAT
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
760
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Peak to Peak Voltage Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
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20
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Measure the maximum and minimum voltage of the input signal.
4
Calculate the peak to peak voltage using the equation:
Peak to Peak Voltage = Maximum Voltage - Minimum Voltage
5
Report the measurement results.
PASS Condition
For all Data Rates:
Maximum Differential Peak to Peak Voltage < 1.38V.
Table 143
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
VTX-DIFFp-p_MAX
Max Output Voltage Level
Min
-
Nom
-
Max
1.38
Unit
V
Comments
For all Output Level and
Pre-emphasis combinations.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured peak to peak voltage for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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SlimPort Source Tests
Source Main Link Frequency Compliance Test
Test ID
12193001 — Main Link Frequency Compliance
Test Overview
The objective of this test is to ensure that the average data rate under all conditions does not exceed
the minimum and maximum values as set by the VESA DisplayPort 1.2a Standard.
Test Conditions for Main Link Frequency Compliance Test
764
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Main Link Frequency Compliance Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and the minimum measurement levels for the FUNC2 magnified unit
interval measurement trend.
d Set up two frequency measurement levels for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e For SSC Enabled Test condition, check the measured frequency to verify the existence of SSC
in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
768
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For the test condition “SSC Enabled”, set up the parameter of the SSC measurement:
a Set up the memory depth and time-base to display one complete SSC cycle based on the
measured SSC modulation frequency in Step 5.
b Acquire the signal with one complete SSC cycle.
c Get the minimum of FUNC2 filtered unit interval measurement trend to calculate the maximum
data rate:
Maximum Data Rate = 1 / (Minimum Unit Interval)
d Get the maximum of FUNC2 filtered unit interval measurement trend to calculate the minimum
data rate:
Minimum Data Rate = 1 / (Maximum Unit Interval)
e Repeat steps b, c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rates.
10 Report the measurement results.
PASS Condition
Maximum Data Rate (Frequency Maxppm) < 300 ppm
Minimum Data Rate (Frequency Minppm) > -5300 ppm
Table 144
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
Parameter
Min
Nom
Max
Unit
fHBR2
Frequency for High
Bit Rate 2
5.37138
5.4
5.40162
Gbps
fHBR
Frequency for High
Bit Rate
2.68569
2.7
2.70081
Gbps
fRBR
Frequency for
Reduced Bit Rate
1.611414
1.62
1.620486
Gbps
Comments
Frequency high limit =
+300ppm
Frequency low limit =
-5300ppm
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.14
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured data rate for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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SlimPort Source Tests
Source Spread Spectrum Clocking (SSC) Modulation Frequency Test
Test ID
12170001 — SSC Modulation Frequency Test
Test Overview
The objective of this test is to evaluate the frequency of the SSC modulation and to validate that the
frequency is within specification limits. This test includes the use of the 2nd order Butterworth
low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of
10 full SSC cycles. Calculate the SSC modulation frequency from the average of the measured SSC
modulation frequency for each cycle.
Test Conditions for SSC Modulation Frequency Test
770
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR25)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Frequency Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
g Acquire the signal for 10 SSC Cycles.
6
Get the mean value for the SSC Modulation frequency.
7
Report the measurement results.
PASS Condition
30kHz < SSC Modulation Frequency (fSSC) < 33kHz
Table 145
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
774
Symbol
Parameter
Min
Nom
Max
Down_Spread_Frequency
Link clock down-spreading
frequency
30
-
33
Unit
kHz
Comments
Range: 30kHz ~ 33kHz when
down-spread enabled
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20
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.15
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation frequency for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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SlimPort Source Tests
Source Spread Spectrum Clocking (SSC) Modulation Deviation Test
Test ID
12180001 — SSC Modulation Deviation Test
Test Overview
The objective of this test is to evaluate the range of SSC down-spreading of the transmitter signal in
ppm and to validate that the values are within specification limits. This test includes the use of the
2nd order Butterworth low-pass filter with a 3dB corner frequency of 1.98MHz. The analysis is
conducted over a minimum of 10 full SSC cycles. For each cycle, the minimum and maximum data
rate is evaluated. Calculate the SSC modulation deviation from the average of the maximum minus
the average of the minimum using the equation:
SSC Modulation Deviation = {[Average (Maximum Data Rate) - Average (Minimum Data Rate)]
/ Nominal Data Rate}*1e6
Test Conditions for SSC Modulation Deviation Test
776
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR25)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Modulation Deviation Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to filter the unit interval measurement trend with 3dB corner
frequency of 1.98 MHz.
5
Set up the parameters for the verification of the existence of SSC in the input signal.
a Create FUNC2 signal, which is the magnify signal of the unit interval measurement trend.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the maximum and minimum measurements for the FUNC2 magnified unit interval
measurement trend.
d Set up two frequency measurements for the FUNC2 magnified unit interval measurement
trend (One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
e Check the measured frequency to verify the existence of SSC in the input signal.
6
Clear all measurements.
7
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point for three points to filter the unit interval measurement trend.
8
Set up the parameters for the unit interval and data rate measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 filtered unit interval measurement
trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurements for the FUNC2 filtered unit interval
measurement trend.
e Set up the data rate or clock recovery rate (CDR rate) for the input signal.
f
Acquire the signal for 10 SSC Cycles.
g Get the mean value for the data rate measurement.
780
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20
Set up the parameters for SSC measurement.
a Set up memory depth and time-base to display one complete SSC Cycle based on the
measured SSC modulation frequency in step 5.
b Acquire the signal with one complete SSC Cycle.
c Get the minimum of the FUNC2 filtered unit interval measurement trend to calculate the
maximum data rate:
Maximum Data Rate = 1/Minimum Unit Interval
d Get the maximum of the FUNC2 filtered unit interval measurement trend to calculate the
minimum data rate:
Minimum Data Rate = 1/Maximum Unit Interval
e Repeat step b,c and d until you acquire 10 SSC Cycles.
f
Calculate the mean value for the maximum and minimum data rate.
10 Calculate the SSC Modulation Deviation using the equation:
SSC Modulation Deviation = (Maximum Data Rate - Minimum Data Rate) / (Nominal Data
Rate) * 1E6
11 Report the measurement results.
PASS Condition
-5000ppm < SSC Modulation Deviation (ResultantSSC Range) < 0ppm
Table 146
DisplayPort Main Link Transmitter System Parameters
Symbol
Parameter
Min
Nom
Max
Down_Spread_Amplitude
Link clock down-spreading
0
-
0.5
Unit
%
Comments
Range: 0% ~ 0.5% when
down-spread enabled
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.16
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-16
Expected/Observable Results
The measured SSC modulation deviation for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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SlimPort Source Tests
Source Spread Spectrum Clocking (SSC) Deviation HF Variation Test (Informative)
Test ID
12200001 — SSC Deviation HF Variation Test (Informative)
Test Overview
The objective of this test is to verify that the SSC profile does not include any frequency deviation
that may exceed 1250 ppm/µsec. This test includes the use of the 2nd order Butterworth low-pass
filter with a 3dB corner frequency of 1.98MHz. The analysis is conducted over a minimum of 10 full
SSC cycles.
Test Conditions for SSC Deviation HF Variation Test (Informative)
782
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR25)
SSC
SSC Enabled
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
D10.2
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for SSC Deviation HF Variation Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
d Measure the data rate of the input signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
4
Set up the parameters for the measurement of measurement trend.
a Set up the unit interval measurement for the input signal.
b Set up the measurement trend for the unit interval measurement.
c Set up the smoothing point to three points to filter the unit interval measurement trend.
5
Set up the parameters for the frequency measurement.
a Create FUNC2 signal, which is the filtered signal of the unit interval measurement trend, using
a Butterworth Low Pass Filter with 3dB corner frequency of 1.98 MHz.
b Set up two display grids such that one grid displays the input signal and the unit interval
measurement trend while the other grid displays the FUNC2 magnified unit interval
measurement trend.
c Set up the memory depth and time-base using the settings defined in the Configuration
Variable.
d Set up the average, maximum and minimum measurement for the FUNC2 filtered unit interval
measurement trend.
e Set up two frequency measurements for the FUNC2 filtered unit interval measurement trend
(One frequency measurement based on the rising edge while the other frequency
measurement based on the falling edge).
f
6
Get the frequency measurement of the FUNC2 filtered unit interval measurement trend.
Set up the parameters for the SSC measurement.
a Set up memory depth and time-base to display one complete SSC cycle using the measured
SSC Modulation Frequency in Step 5.
b Acquire the signal with one complete SSC Cycles.
c Read the FUNC2 filtered unit interval measurement trend.
d Compute the slope using the “Sliding Window” with 1.00 µsec window width. Calculate the
slope using the equation:
Slope = [f(t) - f(t-1.00 µsec)/1.00 µsec]
e Repeat step b, c and d until you acquire 10 SSC Cycles.
f
7
Get the maximum value for the computed value of slope.
Report the measurement results.
PASS Condition
SSCt dF/dt < 1250ppm/µsec
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Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.17
Expected/Observable Results
The measured SSC deviation high frequency variation for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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SlimPort Source Tests
Post-Cursor 2 Verification Test (Informative)
Test ID
1279001 — Post Cursor 2 Verification Test - Level 1/Level 0 (Informative)
1279101 — Post Cursor 2 Verification Test - Level 2/Level 1 (Informative)
1279201 — Post Cursor 2 Verification Test - Level 3/Level 2 (Informative)
Test Overview
The objective of this test is to evaluate the effect of adding Post-Cursor 2 of the source waveform by
measuring the peak differential amplitude to assure accuracy of the Post-Cursor 2 settings.
Test Conditions for Post-Cursor 2 Verification Test
788
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
HBR2, HBR25
SSC
Both SSC conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage levels supported
Pre-Emphasis Level
All pre-emphasis levels supported subject to constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard.
Post-Cursor2 Level
All Post-Cursor 2 levels supported
Test Lane
Lane 0
Test Pattern
PCTPAT
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Post-Cursor 2 Verification Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
For a given Voltage Level, Pre-Emphasis Level and Post-Cursor 2 Level X:
a Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
b Acquire and verify the input signal:
i
Verify the trigger and the amplitude of the input signal.
ii
Scale the vertical display of the input signal to optimum value.
iii Measure VTOP and VBASE of the input signal.
iv Measure the data rate of the input signal.
c Set up the parameter of the measurement:
i
Enable measurement of all edges to obtain a statistical value of the measurement.
ii
Set up the measurement threshold.
iii Set up the Clock Recovery as described in the section “Clock Recovery”.
d Pattern fold the input signal based on the qualifying pattern 00101010 for the measurement of
voltage VT1010_PC2_LvlX_PP in the test pattern PLTPAT.
e Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1010_PC2_LvlX_H and Low Voltage VT1010_PC2_LvlX_L.
f
i
VT1010_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1010 portion of the qualifying pattern.
ii
VT1010_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1010 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1010_PC2_LvlX_PP using the equation:
VT1010_PC2_LvlX_PP = VT1010_PC2_LvlX_H - VT1010_PC2_LvlX_L
g Pattern fold the input signal based on the qualifying pattern 00011001100 for the
measurement of voltage VT1100_PC2_LvlX_PP in the test pattern PLTPAT.
h Set up the vertical waveform histogram on the input signal at the points specified below to
measure the High voltage VT1100_PC2_LvlX_H and Low Voltage VT1100_PC2_LvlX_L.
i
i
VT1100_PC2_LvlX_H is the average value over the 40% to 70% UI points in the fifth relevant
bit (1s bit) in the 1100 portion of the qualifying pattern.
ii
VT1100_PC2_LvlX_L is the average value over the 40% to 70% UI points in the sixth relevant
bit (0s bit) in the 1100 portion of the qualifying pattern.
Calculate the peak-to-peak voltage VT1100_PC2_LvlX_PP using the equation:
VT1100_PC2_LvlX_PP = VT1100_PC2_LvlX_H - VT1100_PC2_LvlX_L
j
Calculate the Post-Cursor 2 ratio using the equation:
Post-Cursor 2 RatioLvlX = VT1100_PC2_LvlX_PP / VT1010_PC2_LvlX_PP
2
Compare the pre-emphasis delta of Post-Cursor 2 Level with the limits by repeating Step 1 with
another Post-Cursor2 Level.
3
Calculate the pre-emphasis delta of Post-Cursor 2 Level using the equation:
Post-Cursor 2 Delta (Level 1 vs Level 0) = 20 * Log10[Post-Cursor 2 RatioLvl1 / Post-Cursor 2
RatioLvl0]
Post-Cursor 2 Delta (Level 2 vs Level 1) = 20 * Log10[Post-Cursor 2 RatioLvl2 / Post-Cursor 2
RatioLvl1]
Post-Cursor 2 Delta (Level 3 vs Level 2) = 20 * Log10[Post-Cursor 2 RatioLvl3 / Post-Cursor 2
RatioLvl2]
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Report the measurement results.
PASS Condition
Post Cursor2 Verification Measurements:
For Level 1 vs. Level 0 Pre-emphasis Post Cursor 2 settings: ResultantLvl0_to_Lvl1 < -0.45 dB
For Level 2 vs. Level 1 Pre-emphasis Post Cursor 2 settings: ResultantLvl1_to_Lvl2 < -0.5 dB
For Level 3 vs. Level 2 Pre-emphasis Post Cursor 2 settings: ResultantLvl2_to_Lvl3 < -0.6 dB
Table 147
DisplayPort Main Link Transmitter TP2 Parameters
TP2 (TX External Connector - Normative)
Symbol
VTX-PREEMP_POST2-DELTA
Parameter
Min
Delta of Pre-emphasis Post
Cursor2 Level 1 vs. Level 0
-0.45
Delta of Pre-emphasis Post
Cursor2 Level 2 vs. Level 1
Delta of Pre-emphasis Post
Cursor2 Level 3 vs. Level 2
Nom
Max
Unit
Comments
-
-
dB
Measured on 2nd TBIT at
Pre-emphasis Level 0
-0.5
-
-
dB
Support for Pre-emphasis
Post Cursor2 is optional
-0.6
-
-
dB
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2a, Section 3.3.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured pre-emphasis delta of Post-Cursor 2 for the test signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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SlimPort Source Tests
Eye Diagram Test (TP3_EQ)
Test ID
For HBR
•
1211001 — Eye Diagram Test (TP3_EQ)
•
1211011 — Eye Diagram Test with No Cable Model (TP3_EQ)
For HBR2 and HBR25
•
1215001 — Eye Diagram Test (TP3_EQ)
•
1215011 — Eye Diagram Test with No Cable Model (TP3_EQ)
Test Overview
The objective of this test is to evaluate the waveform, ensuring that the timing variables and
amplitude trajectories support the overall DP system objectives of the Bit Error Rate in data
transmission.
Test Conditions for Eye Diagram Test (TP3_EQ)
794
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR (Informative), HBR2 and HBR25
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
HBR — Level 2
HBR2, HBR25 — Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
HBR — Level 0
HBR2, HBR25 — Any pre-emphasis level such that the source meets the Pass/Fail
criteria.
Post-Cursor2 Level
HBR — Level 0
HBR2, HBR25 — Any post-cursor 2 level such that the source meets the Pass/Fail
criteria.
Test Lane
Lane 0
Test Pattern
HBR—PRBS7
HBR2, HBR25—HBR2CPAT
Cable Model
“Worst Case” and “Zero Length” conditions
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure for HBR and HBR25
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
6
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
7
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
8
Measure the jitter of the eye diagram using the Histogram.
9
Check for any signal trajectories that may have entered into the mask.
10 Report the measurement results.
Measurement Procedure for HBR2
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
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Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Pattern fold the equalized signal based on the High Level Voltage (VHIGH) random noise
configuration variable.
b Set up the vertical waveform histogram on the equalized signal to measure random noise of
High Level Voltage (VHIGH).
c Measure the High Level Voltage (VHIGH) random noise based on the standard deviation of the
waveform histogram.
d Pattern fold the equalized signal based on the Low Level Voltage (VLOW) random noise
configuration variable.
e Set up the vertical waveform histogram on the equalized signal to measure the random noise
of Low Level Voltage (VLOW).
f
Measure the Low Level Voltage (VLOW) random noise based on the standard deviation of the
waveform histogram.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge and right edge.
8
Set up the vertical waveform histogram on the equalized signal eye diagram to measure the eye
height from 0.375 UI to 0.625 UI.
9
Find the maximum eye height location of the eye diagram.
10 If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]:
a Set up the parameter of the jitter separation using the EZJIT Plus/Complete Software.
i
Load the jitter separation parameter into EZJIT Plus/Complete Software based on the
settings in the Configuration Variable.
ii
Acquire the signal until 1,000,000 edges are analyzed.
b Note the value of the jitter component from the EZJIT Plus/Complete Software.
11 Create the eye mask based on the following criteria:
a If random noise/ jitter derate includes [“Exclude Random Noise” configuration variable set to
“False” (Default)]: eye mask height and width is derate as below to comprehend the
noise/jitter extrapolated to BER 10-9 for an Eye Diagram Test (TP3_EQ) only acquiring 1e6 UI:
i
Calculate the Eye Mask Width Derate (Random Jitter) using the equation:
Eye Mask Width Derate (Random Jitter) = 2.5 * Random Jitterrms
ii
Calculate the Eye Mask Height Derate (Random Noise) using the equation:
VHIGH Eye Mask Height Derate (Random Noise) = 2.5 * VHIGH Random Noiserms
VLOW Eye Mask Height Derate (Random Noise) = 2.5 * VLOW Random Noiserms
NOTE
The factor 2.5 is the delta between BER 10-6 (9.507) and 10-9 (11.996) to
comprehend the noise/jitter extrapolated to BER 10-9 as the Eye Diagram
Test (TP3_EQ) only acquiring 1e6 UI.
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BER
N
-6
10
9.507
10-7
10.399
10-8
11.224
10-9
11.996
b Place the eye mask height at the point of the maximum eye height found in Step 9.
c Calculate the Eye Mask Width:
Eye Mask Width = Eye Width Specification (0.38 UI) + Eye Mask Width Derate (Crosstalk) + 2 *
Eye Mask Width Derate (Random Jitter)
d Calculate the Eye Mask Height:
Eye Mask Height = {Eye Height Specification (0.09 UI) + Eye Mask Height Derate (Crosstalk)}/2
+ VHIGH Eye Mask Height Derate (Random Noise)
Eye Mask Height = -{Eye Height Specification (0.09 UI) + Eye Mask Height Derate
(Crosstalk)}/2 - VLOW Eye Mask Height Derate (Random Noise)
12 Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram.
c Run the eye mask until 1,000,000 UI are folded.
13 Measure the eye height of the eye diagram using the Histogram.
14 Measure the jitter of the eye diagram using the Histogram.
15 Calculate the eye width based on the measured jitter of the eye diagram.
16 Check for any signal trajectories that may have entered into the mask.
17 Report the measurement results.
PASS Condition
The following table and figures define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 148 shows the voltage and time coordinates for the mask
used for the eye diagram.
Figure 156
800
Eye Mask at TP3_EQ (HBR25)
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Table 148
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 157
20
Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
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Table 149
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Figure 158
Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-25 for HBR and
Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test. The
rendered eye diagram shall have no signal trajectories entering the mask area.
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Total Jitter Test (TP3_EQ)
Test ID
For HBR2 and HBR25
•
1222001 — Total Jitter Test (TP3_EQ) - HBR2CPAT
•
1222011 — Total Jitter Test with No Cable Model (TP3_EQ) - HBR2CPAT
•
1221001 — Total Jitter Test (TP3_EQ) - D10.2
•
1221011 — Total Jitter Test with No Cable Model (TP3_EQ) - D10.2
Test Overview
The objective of this test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2, HBR25
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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806
SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 150
Total Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) and High-Bit Rate 25 (6.75 Gb/s per lane)
0.580 UI*
Ap-p
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI limit in DisplayPort 1.2a Standard.
Table 151
Total Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) and High-Bit Rate 25 (6.75 Gb/s per lane)
TTX-TJ_D10.2_HBR2
0.40 UI
UI is Unit Interval.
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SlimPort Source Tests
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured total jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
808
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Deterministic Jitter Test (TP3_EQ)
Test ID
For HBR2 and HBR25
•
1236001 — Deterministic Jitter Test (TP3_EQ) - HBR2CPAT
•
1236011 — Deterministic Jitter Test with No Cable Model (TP3_EQ) - HBR2CPAT
•
1235001 — Deterministic Jitter Test (TP3_EQ) - D10.2
•
1235011 — Deterministic Jitter Test with No Cable Model (TP3_EQ) - D10.2
Test Overview
The objective of this test is to evaluate the deterministic jitter accompanying the data transmission.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Deterministic Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2, HBR25
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
HBR2CPAT and D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Deterministic Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 152
Deterministic Jitter at TP3_EQ (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
0.49 UI
Ap-p
Table 153
Deterministic Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
TTX-DJ_D10.2_HBR2
0.25 UI
UI is Unit Interval.
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SlimPort Source Tests
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
For HBR2CPAT
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
For D10.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured deterministic jitter for the test signal at TP3_EQ shall be within the conformance limits
as specified in the specification mentioned under the “PASS Condition” section for this test.
814
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Random Jitter Test (TP3_EQ)
Test ID
For HBR2 and HBR25
•
1238001 — Random Jitter Test (TP3_EQ) - D10.2
•
1238011 — Random Jitter Test with No Cable Model (TP3_EQ) - D10.2
Test Overview
The objective of this test is to evaluate the random jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. The jitter is
separated into each jitter components and the random jitter is estimated to 10-9 BER based on the
Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Random Jitter Test (TP3_EQ)
Test Parameter
Cond ition
Test Point
TP3_EQ
Bit Rate
HBR2, HBR25
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Any voltage level such that the source meets the Pass/Fail criteria.
Pre-Emphasis Level
Any pre-emphasis level such that the source meets the Pass/Fail criteria.
Post-Cursor2 Level
Any post-cursor 2 level such that the source meets the Pass/Fail criteria.
Test Lane
Lane 0
Test Pattern
D10.2
Cable Model
“Worst Case” and “Zero Length” conditions
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Differential Tests.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Random Jitter Test (TP3_EQ)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
a For Eye Diagram Test (TP3_EQ): Use “Worst Cable Model” as defined in the section “Cable
Model”.
b For Eye Diagram Test with No Cable Model (TP3_EQ): Use “Zero Length Cable Model” as
defined in the section “Cable Model”.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Set up equalized signal as defined in the section “Equalization”.
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the clock recovery as defined in the section “Clock Recovery”.
5
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
6
Note the jitter component value from the EZJIT Plus/Complete Software.
7
Report the measurement results.
PASS Condition
Table 154
Random Jitter at TP3_EQ (for D10.2)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane)
TTX-RJ_D10.2_HBR2
0.23 UI
UI is Unit Interval.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.1
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.12.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-18
Expected/Observable Results
The measured random jitter for the test signal at TP3_EQ shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
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SlimPort Source Tests
AC Common Mode Test (Informative)
Test ID
12110001 — AC Common Mode Test (Informative)
Test Overview
The objective of this test is to evaluate the AC Common Mode noise (unfiltered rms) of the differential
data line of the DP interface.
Test Conditions for AC Common Mode Test (Informative)
820
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
All bit rates supported (RBR, HBR, HBR2, HBR25)
SSC
Both SSC Conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
All voltage level supported
Pre-Emphasis Level
All pre-emphasis level supported subject to the constraints in Table 3-1 of the VESA
DisplayPort 1.2a Standard
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
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SlimPort Source Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for AC Common Mode Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Create FUNC3 signal, which is the common mode signal of the input single-ended signal.
4
If the filter is enabled [“Filter” configuration variable set to “High Pass Filter”, “Low Pass Filter” or
“None” (Default)]:
a Create FUNC4 signal, which is the filtered FUNC3 signal by applying the High Pass filter or
Low Pass filter on the FUNC3 signal based on the Configuration Variable.
5
6
Set up two display grids such that one grid displays the input single-ended signal while the other
grid displays the common mode signal.
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
7
Set up the parameters for RMS voltage measurement of the common mode signal.
a Set up the Vrms measurement for the common mode signal.
b Acquire the signal until 100,000 edges are measured.
8
Get the mean for the Vrms measurement.
9
Report the measurement results.
PASS Condition
For RBR and HBR:
AC Common Mode Voltage < 20mV
For HBR2, HBR25:
AC Common Mode Voltage < 30mV
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.10
• VESA DisplayPort Standard Version 1, Revision 2a, Section 9.2, Table 9-6
Expected/Observable Results
The measured AC common mode noise for the test signal shall be within the conformance limits as
specified in the specification mentioned under the “PASS Condition” section for this test.
824
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Intra-Pair Skew Test (Informative)
Test ID
12100001 — Intra-Pair Skew Test (Informative)
Test Overview
The objective of this test is to evaluate the skew or time delay between respective sides of a
differential data lane in the DP interface.
Test Conditions for Intra-Pair Skew Test (Informative)
Test Parameter
Cond ition
Test Point
TP2
Bit Rate
Highest bit rate supported (RBR, HBR, HBR2 or HBR25)
SSC
Both SSC conditions supported (SSC Enabled and SSC Disabled)
Voltage Level
Level 2
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0 (Lane 0+ to Lane 0-)
Test Pattern
D10.2
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SlimPort Source Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Source, Test Type: as Single-Ended Tests.
c Click Next.
826
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Intra-Pair Skew Test (Informative)".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Source Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Source Tests" on page 716 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Source Tests
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input single-ended plus signal.
b Scale the vertical display of the input single-ended plus signal to the optimum value.
c Measure VTOP and VBASE of the input single-ended plus signal.
d Verify the trigger and the amplitude of the input single-ended minus signal.
e Scale the vertical display of the input single-ended minus signal to the optimum value.
f
Measure VTOP and VBASE of the input single-ended minus signal.
g Measure the data rate of the input single-ended signal.
3
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
4
Set up the parameters to perform High Level Voltage (VHIGH) and Low Level Voltage (VLOW) for
each input single-ended signal.
a Scale the vertical display of the input single-ended signal to optimum value.
b Acquire the signal for 100 waveforms.
c Find VHIGH by measuring the average voltage at 0.06 UI to 0.75 UI of the High Level.
d Find VLOW by measuring the average voltage at 0.06 UI to 0.75 UI of the Low Level.
e Calculate the Transition Voltage (VTrans) using the equation:
VTrans = (VHIGH + VLOW) / 2
5
Set up the parameters for the intra-pair skew measurement:
a Set up the measurement threshold for each single-ended data signal based on the measured
Transition Voltage.
b Set up InfiniiScan to trigger on the desired pattern.
c Set up delta time measurement to measure time difference between the rising edge of the
data true signal (D+) and the complement’s (D-) falling edge:
D+Transition_High - D-Transition_Low
d Set up delta time measurement to measure time difference between the falling edge of the
data true signal (D+) and the complement’s (D-) rising edge:
D+Transition_Low - D-Transition_High
e Acquire the signal until you measure 100 edges.
f
Calculate the intra-pair skew using the equation:
Intra-Pair Skew = {1/Number of Edges}
∑ {[(D+Transition_High - D-Transition_Low) + (D+Transition_Low - D-Transition_High)] / 2}
6
Report the measurement results.
PASS Condition
Intra-Pair Skew ≤ 30 ps
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SlimPort Source Tests
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 3.5
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3, Table 3-17
Expected/Observable Results
The measured intra-pair skew for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
830
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
21 SlimPort Sink Tests
Overview / 832
Sink Eye Diagram Test / 836
Sink Total Jitter Test / 843
Sink Non-ISI Jitter Test / 849
21
SlimPort Sink Tests
Overview
Test Point Definition for SlimPort Sink Tests
NOTE
Sink Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Sink DUT at Test Point 3 (TP3) as shown in Figure 159. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 159
Test Point 3 Connection for SlimPort Sink Tests
Table 155 defines the test point fixtures and instruments used for SlimPort (MyDP HBR25) Sink Tests:
Table 155
832
Test Point Fixtures and Instruments for SlimPort (MyDP HBR25) Sink Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
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21
Calibration of Stress Signal
For the calibration of the stress signal, you must test the stress signal in the manner shown in the
Figure 160 for RBR and Figure 161 for HBR and HBR2.
Figure 160
Test Point 3 Connection for Stress Signal Calibration of RBR
Figure 161
Test Point 3 Connection for Stress Signal Calibration of HBR and HBR2
Table 156 defines the Test Point Fixtures and Instruments for Stress Signal Calibration:
Table 156
Test Point Fixtures and Instruments for Stress Signal Calibration
Test Requirement
Device Used
Stress Signal Generator (SSG)
Bit Error Rate Tester
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Jitter Measurement Device (JMD)
Infiniium Series Oscilloscope
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SlimPort Sink Tests
Setting Up the DisplayPort Compliance Test Application for SlimPort Sink Tests
Perform the following steps before you run the compliance tests on the sink device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 162).
Figure 162
834
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with SlimPort Standards, select MyDP HBR25 from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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21
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for SlimPort Sink Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 163
Sample connection diagram for SlimPort Sink Tests
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SlimPort Sink Tests
Sink Eye Diagram Test
Test ID
12140001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the following specifications for degradation:
• Voltage Level:
•
90mV peak to peak +/- 10% for HBR2 at TP3_EQ (Table 3-18, DP1.2a)
•
150mV peak to peak +/- 10% for HBR at TP3_EQ (Table 3-25, DP1.2a)
•
46mV peak to peak +/- 10% for RBR at TP3 (Table 3-26, DP1.2a)
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Eye Diagram Test
836
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR25—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR, HBR2 and HBR25)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR25—HBR2CPAT
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Sink Tests
21
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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838
SlimPort Sink Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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21
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Sink Tests" on page 834 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Sink Tests
Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 157 shows the voltage and time coordinates for the mask
used for the eye diagram.
Figure 164
840
Eye Mask at TP3_EQ (HBR25)
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Sink Tests
Table 157
21
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 165
The Sink Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
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Table 158
Eye Diagram Mask Coord inates for TP3_EQ (HBR2)
Mask Point
Time (UI)
Vol tage (V)
1
Any UI location (x), where the EYE width is open from x to x + 0.38UI
0.000
2
Any passing UI location between 0.375 and 0.625UI
0.0045
3
Point 1 + 0.38UI
0.0000
4
Same as Point 2
-0.0045
Figure 166
The Sink Eye Mask at TP3_EQ (HBR2)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
842
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Sink Total Jitter Test
Test ID
12210001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Total Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR25—TP3_EQ
Bit Rate
All bit rates supported (RBR, HBR, HBR2 and HBR25)
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR25—HBR2CPAT
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SlimPort Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Sink Tests" on page 834 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 159
Total Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
0.580 UI*
* The limits for the Total Jitter are derated by 0.04 UI from 0.62 UI in DisplayPort 1.2a Standard.
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Table 160
Total Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Sink Non-ISI Jitter Test
Test ID
12220001 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non ISI jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
You can use this test to calibrate the degraded source signal or stress signal for sink jitter tolerance
test. To verify the sink performance, a source signal is degraded with a prescribed amount and type
of jitter as well as signal level, based on the specifications for degradation.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
With the degraded source signal applied to the sink (receiver), the sink shall perform at 10-9 BER or
better.
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR, HBR2, HBR25—TP3_EQ
Bit Rate
All bit rates (for RBR, HBR, HBR2 and HBR25) supported
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
RBR, HBR—PRBS7
HBR2, HBR25—HBR2CPAT
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SlimPort Sink Tests
Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Sink, Test Type: automatically grays out.
c Click Next.
850
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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SlimPort Sink Tests
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Sink Tests" on page 834 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Sink Equalizer)
a Scale the vertical display of the input signal to the optimum value.
b Measure VTOP and VBASE of the input signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
The calibrated EYE opening of the signal applied:
•
For HBR2: 90mV measured at TP3_EQ
•
For HBR: 150mV measured at TP3_EQ
•
For RBR: 46mV measured at TP3
Table 161
Non ISI Jitter (for HBR2CPAT)
Receiver Connector (TP3_EQ)
High-Bit Rate 2 (5.4 Gb/s per lane) at TP3_EQ
Ap-p
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Table 162
Non ISI Jitter (for PRBS7)
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 4.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
854
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
22 SlimPort Cable Tests
Overview / 856
Cable Eye Diagram Test / 860
Cable Total Jitter Test / 866
Cable Non-ISI Jitter Test / 871
22
SlimPort Cable Tests
Overview
Test Point Definition for SlimPort Cable Tests
NOTE
Cable Tests are meant only for the Test Automation of DisplayPort Receiver
Tests (Keysight N4990A-155 or BIT-2051-0155-0).
Test the Cable DUT at Test Point 3 (TP3) as shown in Figure 167. Unless specifically stated under the
Test Conditions, all supported lanes for the DUT shall be evaluated:
Figure 167
856
Test Point 3 Connection for SlimPort Cable Tests
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Table 163 defines the test point fixtures and instruments used for SlimPort (MyDP HBR25) Cable
Tests:
Table 163
Test Point Fixtures and Instruments for SlimPort (MyDP HBR25) Cable Tests
Test Requirement
Device Used
Stimulus Instrument
Pulse Pattern Generator
• N4903B J-BERT High Performance Serial BERT
• M8020A J-BERT High Performance BERT
Test Point Access Fixture
DisplayPort Test Point Adapter
For DisplayPort Connector
• Wilder Technologies DP-TPA-R*
For mini DisplayPort Connector
• Wilder Technologies mDP-TPA-R*
• Luxshare ICT mDP Plug (mDP-TPA-R)**
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
• **Use Luxshare ICT DP-TPA-A AUX Control board for all Luxshare ICT Test Point
Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Table 164 defines the input signal parameters applied by the stimulus instrument at TP2:
Table 164
Input Signal Parameters by Stimulus Instrument
RBR
•
•
•
•
Reference Table 3-22 and Table 3-24, DP 1.2a
Edge Rate (20-80): 155-165ps (260mUI)
Eye Height: 400mV
Total Jitter: 270mUI
• ISI: 100mUI
• Random Jitter (rms): 7.9mUI
• Sinusoidal Jitter: ~75mUI at 20MHz (Adjust to achieve Total Jitter)
HBR
•
•
•
•
Reference Table 3-22 and Table 3-23, DP 1.2a
Edge Rate (20-80): 90-100ps (260mUI)
Eye Height: 350mV
Total Jitter: 420mUI
• ISI: 144mUI
• Random Jitter (rms): 13.2mUI
• Sinusoidal Jitter: ~117mUI at 20MHz (Adjust to achieve Total Jitter)
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Setting Up the DisplayPort Compliance Test Application for SlimPort Cable Tests
Perform the following steps before you run the compliance tests on the cable device:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 168).
Figure 168
858
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with SlimPort Standards, select MyDP HBR25 from the drop-down options
in the Test Specification area and select Physical Layer Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
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22
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
Probing/Connection Set Up for SlimPort Cable Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests.
Figure 169
Sample connection diagram for SlimPort Cable Tests
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SlimPort Cable Tests
Cable Eye Diagram Test
Test ID
12150001 — Eye Diagram Test
Test Overview
The objective of the eye diagram test is to evaluate the waveform, ensuring that the amplitude
trajectories and timing variations of the waveform support the overall DP system objectives of Bit
Error Rate in Data transmission.
Test Conditions for Eye Diagram Test
860
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 164
Crosstalk Signal Parameter
Quarter-rate clock signal (D24.3 pattern) is injected to lanes other than the lane under
test. The characteristics of the aggressor signals are:
Pattern—D24.3
Bit Rate—(Same as lane under test)
Voltage Amplitude—(Same as lane under test)
• RBR-400mV
• HBR-350mV
Edge Rate (20-80)—130ps at TP3
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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SlimPort Cable Tests
3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Eye Diagram Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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22
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Cable Tests" on page 858 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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SlimPort Cable Tests
Measurement Procedure:
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Fold the equalized signal to generate an eye diagram at the middle of the screen such that it is
more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform histogram on the equalized signal eye diagram to measure the
left edge.
8
Set up the parameter for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge.
c Run the eye mask until 1,000,000 UI are folded.
9
Measure the jitter of the eye diagram using the Histogram.
10 Check for any signal trajectories that may have entered into the mask.
11 Report the measurement results.
PASS Condition
The following table and figure define the mask for the eye measurements. There can be no signal
trajectories entering into the mask. Table 165 shows the voltage and time coordinates for the mask
used for the eye diagram.
864
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Table 165
22
Eye Diagram Mask Coord inates for TP3 (RBR) and TP3_EQ (HBR)
Mask Point
Bit Rate
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 170
The Cable Eye Mask at TP3 (RBR) and TP3_EQ (HBR)
Mask Test: Zero mask failures.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.3
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.8, Table 3-26 for RBR, Table
3-25 for HBR and Table 3-18 for HBR2
Expected/Observable Results
The measured eye diagram for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test. The rendered eye
diagram shall have no signal trajectories entering the mask area.
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SlimPort Cable Tests
Cable Total Jitter Test
Test ID
12230001 — Total Jitter Test
Test Overview
The objective of the test is to evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10-9 or through an approved estimation technique. This measurement is a
data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Test Conditions for Total Jitter Test
866
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 164
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Total Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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22
5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Cable Tests" on page 858 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 166
Total Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.491 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.750 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured total jitter for the test signal shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
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Cable Non-ISI Jitter Test
Test ID
12240001 — Non-ISI Jitter Test
Test Overview
The objective of the test is to evaluate the Non-ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10-9 or through an approved estimation technique. This
measurement is a data time interval error (Data-TIE) jitter measurement.
The jitter is separated into each jitter components and the total jitter is estimated to 10-9 BER based
on the Dual-Dirac Model:
TJ = DJdd + n* RJrms
where, DJ is the Deterministic Jitter, RJ is the Random Jitter and n = 12.0 to accommodate
10-9 BER.
Calculate Non-ISI Jitter using the following equation:
Non-ISI Jitter = TJ - ISI Jitter
Test Conditions for Non-ISI Jitter Test
Test Parameter
Cond ition
Test Point
RBR—TP3
HBR—TP3_EQ
Bit Rate
RBR, HBR
SSC
SSC Disabled
Voltage Level
Level 0
Pre-Emphasis Level
Level 0
Post-Cursor2 Level
Level 0
Test Lane
Lane 0
Test Pattern
PRBS7
Input Signal Parameter Applied by
Stimulus at TP2
Refer to Table 164
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Test Setup
1
After you select the options in the Test Specification and Test Selection area of the Set Up tab, click
the Test Setup button. The Test Setup window displays.
2
On the Test Setup window,
a Define your DUT to distinguish between several test runs on the HTML report that the
application generates at the end of the test runs.
b Select Device Type: as Cable, Test Type: automatically grays out.
c Click Next.
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3
On the DUT Definition Setup window, select options based on the settings defined in "Test Conditions
for Non-ISI Jitter Test".
4
On the Test Connection Setup window, select the appropriate fixture type from the drop-down
options, type of probe connection and number of oscilloscope channels.
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5
On the Channel Selection Setup window, assign channels to lanes.
6
Click Finish. The Set Up tab displays.
7
Click the Select Tests tab to select the tests for DisplayPort test patterns defined above.
8
See “Setting Up the DisplayPort Compliance Test Application for SlimPort Cable Tests" on page 858 to
complete the task flow for DUT setup along with configuring the Compliance Application to run
the test.
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Measurement Procedure
1
Ensure that the InfiniiSim is configured based on the settings in the Configuration Variable.
2
Acquire and verify the input signal.
a Verify the trigger and the amplitude of the input signal.
b Scale the vertical display of the input signal to the optimum value.
c Measure VTOP and VBASE of the input signal.
3 Create FUNC3 signal, which is the magnify signal of the input signal.
4
Create FUNC4 signal, which is the equalized signal of the magnify signal. Equalized signal is
created by convolving the input signal with the transfer function of the cable model and equalizer
based on the settings in the Configuration Variable (Cable Equalizer).
a Scale the vertical display of the equalized signal to the optimum value.
b Measure VTOP and VBASE of the equalized signal.
c Measure the data rate of the equalized signal.
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery as described in the section “Clock Recovery”.
6
Set up the parameters for jitter separation using the EZJIT Plus/Complete Software.
a Load the jitter separation parameter into the EZJIT Plus/Complete software based on the
settings in the Configuration Variable.
b Acquire the signal until 1,000,000 edges are analyzed.
7
Note the jitter component value from the EZJIT Plus/Complete Software.
8
Report the measurement results.
PASS Condition
Table 167
Non ISI Jitter
Receiver Connector
High-Bit Rate (2.7 Gb/s per lane)
TP3_EQ
Ap-p
0.330 UI
Reduced-Bit Rate (1.62 Gb/s per lane)
TP3
Ap-p
0.180 UI
UI is Unit Interval.
Test References
See:
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 9.4
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.5.3.7.2, Table 3-22
Expected/Observable Results
The measured Non-ISI jitter for the test signal shall be within the conformance limits as specified in
the specification mentioned under the “PASS Condition” section for this test.
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Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
23 SlimPort AUX Channel Tests
Overview / 878
Setting Up for AUX PHY and Inrush Tests / 881
AUX Channel Unit Interval Test / 889
AUX Channel Eye Test / 891
AUX Channel Peak-to-Peak Voltage Test / 893
AUX Channel Eye Sensitivity Calibration Test / 895
AUX Channel Eye Sensitivity Test / 897
23
SlimPort AUX Channel Tests
Overview
This section describes the normative and informative AUX Channel physical layer tests and inrush
tests for compliance verification of SlimPort source and sink.
Test Point for SlimPort AUX Channel Tests
You must test the Source and Sink/Branch devices at Test Point 2 (TP2). See Figure 171.
Figure 171
Test Point for SlimPort AUX Channel Tests
Table 168 defines the test point fixtures and instruments used for SlimPort (MyDP HBR25) AUX
Channel Tests:
Table 168
Test Point Fixtures and Instruments for SlimPort (MyDP HBR25) AUX Channel Tests
Test Requirement
Device Used
Test Point Access Fixture
Mobility DisplayPort Test Point Adapter
For MyDP Connector
• Wilder Technologies MYDP-TPA-P*
• *Use Wilder Technologies DP-TPA-A AUX Control board for all Wilder
Technologies Test Point Adapters.
Signal Analyzer
Infiniium Series Oscilloscope
Setting Up the DisplayPort Compliance Test Application for SlimPort AUX Channel Tests
Perform the following steps before you run the compliance tests on the AUX channel device:
878
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
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On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 172).
Figure 172
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with SlimPort Standards, select MyDP HBR25 from the drop-down options
in the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
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Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
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Setting Up for AUX PHY and Inrush Tests
Perform the following steps before you run the Auxiliary Channel and Inrush tests on the source or
sink device:
1
After you select AUX PHY and Inrush Tests, click the Test Setup button on the Set Up tab.
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2
On the DUT/Connectivity page, select Source or Sink in the DUT Type area. In the Reference Device
area, select Yes if a reference sink/source is attached to device under test during testing. Click
Next.
3
On the Connection Setup page, depending on the probe connection you are using, select either
Differential Probe or Single-Ended in the Connection Type area and in the Connection area, select the
oscilloscope channel that is connected to the Auxiliary Lane.
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On the Trigger Setup page, define the oscilloscope parameters to trigger on an Auxiliary signal
during testing.
Hold Off Time — The oscilloscope minimum hold off time before triggering the next waveform. Note
that any Auxiliary transaction from the source must receive a reply from the sink in 400 us, else such
a transaction is considered a timeout. Hold off time, in such cases, represents the minimum idle time
before each AUX transaction is initialized. It is defaulted to 300 us which is a safe timing value for
most devices tested in the lab. Most devices respond much faster than 300 us.
Trigger Level — The AUX channel signal level on which to trigger. Note that for a bi-directional signal
(where a reference sink is attached), you must set the trigger level such that it crosses both the
source command and the sink reply signal. Figure 173 and Figure 174 show correct and incorrect
trigger levels.
Figure 173
Correct Trigger Level
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Figure 174
Incorrect Trigger Level
Vertical Scale — The oscilloscope vertical scale. Set the vertical to make sure that all signals are visible
on the oscilloscope display.
Offset — Set the offset so that the center point is aligned with the center of the oscilloscope display.
Upper Threshold/Lower Threshold — The threshold level of signal must be set properly so that both
upper and lower thresholds cross both the source and sink signals when the DUT is attached with a
reference sink. The threshold levels are important parameters because they are used for edge
detection when decoding a source command from a sink reply. Figure 175 and Figure 176 show the
correct and incorrect threshold sets.
Figure 175
884
Correct Threshold set
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Figure 176
23
Wrong Thresholds set
c On the Trigger Setup page, you may click the Learn button, which guides you through getting
the trigger setup parameters. However, please note that the learning guide may not
necessarily work many a times because the actual Auxiliary signals may vary for different
manufacturers. Keysight recommends that you must check to make sure that the parameters
are correctly set as previously described.
d Click Verify and follow the instructions, if you wish to check the AUX Channel trigger.
e You may Save or Load the trigger setup configuration as a *.tsf file.
5
On the Acquisition Mode page, either Finish the setup wizard or enable Offline Mode, which is
de-selected, by default. Offline Mode lets you save the waveform files so that you can avoid the
manual process to initiate Auxiliary transactions during the time of test runs.
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6
If you enable Offline Mode, define the number of waveforms to be saved. If required, click Start
Acquisition to start capturing and saving waveforms.
7
Click Finish to close the setup wizard. The Set Up tab displays.
8
Click the Select Tests tab and select the AUX Channel tests you want to run.
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Probing/Connection Set Up for AUX Channel Tests
After selecting the tests under the Select Tests tab on the DisplayPort Electrical Performance
Compliance Test Application, refer to the Connect tab to see the connection diagram and instructions
required to establish/check the physical connection prior to running the tests. When the tests are
running, the DisplayPort Electrical Performance Compliance Test Application may prompt you to
make/change the proper connections for certain type of tests. When performing the Source AUX
Channel tests, a Reference Sink device is required. Similarly, when performing the Sink AUX Channel
tests, a Reference Source device is required.
Figure 177
Sample connection diagram for source AUX channel tests with source DUT connected to a reference sink
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Figure 178
Sample connection diagram for source AUX channel tests without connecting to a reference sink
Figure 179
Sample connection diagram for sink AUX channel tests with sink DUT connected to a reference source
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AUX Channel Unit Interval Test
Test ID
125000 — AUX Channel Unit Interval Test (Source)
125010 — AUX Channel Unit Interval Test (Sink)
Test Overview
The objective of the test is to evaluate the AUX Channel waveform, ensuring that the overall variation
of the Manchester transaction Unit Interval stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Set up the parameter of the measurement trend:
a Set up the Unit Interval measurement for the differential AUX Channel signal.
b Set up the frequency measurement for the Clock signal.
c Set up the measurement trend.
6
Set up the waveform Histogram on the measurement trend:
a Initialize AUX Channel transactions and acquire the differential AUX Channel signal.
b Identify the first and the last points for the desired transaction.
c Zoom-in on the desired transaction.
d Set up the Vertical Waveform Histogram on the measurement trend within the desired
transaction.
e Obtain the measurement for the mean, maximum and minimum values of the waveform
Histogram.
7
Repeat step 6 ten times.
8
Report the measurement results.
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PASS Condition
Manchester Transaction Unit Interval (UIMAN):
Minimum = 0.4 µsec
Maximum = 0.6 µsec
Test References
See:
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-2
Expected/Observable Results
The measured unit interval for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Test
Test ID
125001 — AUX Channel Eye Test (Source)
125011 — AUX Channel Eye Test (Sink)
Test Overview
The objective of this test is to evaluate the transmitter AUX Channel waveform, ensuring that the
timing variables and amplitude trajectories support the overall DP system objectives of the Bit Error
Rate in data transmission.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the waveform Histogram on the AUX Channel eye diagram to measure the left edge and
the right edge.
8
Set up the parameters for the Mask Test.
a Load the eye mask based on the settings in the Configuration Variable.
b Center the eye mask at the middle of the eye diagram based on the measured left edge and
right edge.
c Initialize the AUX Channel transaction and run the eye mask until you obtain the required
number of waveforms.
9
Check for any signal trajectories entering into the mask.
10 Report the measurement results.
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PASS Condition
PASS Value = 290mV_diff_pp or higher
FAIL Value = lower than 290mV_diff_pp
Table 169
Eye Mask Vertices for AUX Channel for Manchester Transactions
Mask Point
Time (from EYE Center)
Minimum Voltage Value at Six Vertices (mV)
1
-185ns
0
2
-135ns
145
3
135ns
145
4
185ns
0
5
135ns
-145
6
-135ns
-145
Figure 180
AUX Channel EYE Mask for Manchester Transactions
Mask Test: Zero mask failures.
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.2
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-1 and Table 2-2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2.6, Figure 3-29 and Table 3-8
Expected/Observable Results
The measured eye diagram for the transmitter AUX Channel signal shall be within the conformance
limits as specified in the specification mentioned under the “PASS Condition” section for this test.
The rendered eye diagram shall have no signal trajectories entering the mask area.
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AUX Channel Peak-to-Peak Voltage Test
Test ID
125002 — AUX Channel Peak-to-Peak Voltage Test (Source)
125012 — AUX Channel Peak-to-Peak Voltage Test (Sink)
Test Overview
The objective of the test is to evaluate the transmitter AUX Channel Waveform, ensuring that the
peak-to-peak voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
2
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
3
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
6
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
7
Set up the horizontal waveform Histogram on the AUX Channel eye diagram to measure the left
edge and the right edge.
8
If you have selected the “AUX Channel Eye Test” under the Select Tests tab of the compliance
application:
a Set up the parameter of the Mask Test:
i
Load the eye mask based on the settings in the Configuration Variable.
ii
Center the eye mask at the middle of the eye diagram based on the measured left edge
and right edge.
iii Initialize the AUX Channel transaction and run the eye mask until ten waveforms are
folded.
b Check for any signal trajectories entering into the mask.
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9
Set up the waveform histogram on the AUX Channel eye diagram.
a Set up the vertical waveform histogram on the AUX Channel eye diagram to measure the peak
to peak voltage.
10 Report the measurement results.
PASS Condition
Table 170
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage at a transmitting device (VAUX-DIFFp-p)
0.29V
1.38V
Test References
See:
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 2, Table 2-1
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the transmitter AUX Channel signal shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
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AUX Channel Eye Sensitivity Calibration Test
Test ID
125021 — AUX Channel Eye Sensitivity Calibration (Reference Sink)
125031 — AUX Channel Eye Sensitivity Calibration (Reference Source)
Test Overview
The objective of this test is to calibrate the peak-to-peak voltage of the transmitter AUX Channel
waveform by reference device (reference source or reference sink), ensuring that the peak-to-peak
voltage stays within the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Generate FUNC2 (Clock) signal for the eye folding using the MATLAB script. The MATLAB script
generates the clock for the desired transaction (either Source transaction or Sink transaction
based on the type of DUT).
5
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
6
Generate FUNC3 signal, which is the second differential signal of the AUX Channel.
7
Fold the differential signals of the AUX Channel to generate the eye diagram at the middle of the
screen such that it is more than one full UI but no more than 2.5 UI.
8
Set up the waveform Histogram on the AUX Channel eye diagram:
a Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
b Set up the vertical waveform Histogram of width 0.6 UI at the center of the AUX Channel eye
diagram.
c Measure the VTOP and VBASE using the waveform Histogram mean value.
9
Repeat Step 8 three times.
10 Report the measurement results.
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PASS Condition
Table 171
DisplayPort AUX Channel Peak-to-Peak Voltage
Parameter
Min
Max
AUX Peak-to-Peak voltage for AUX Channel Eye Sensitivity
0.24V
0.28V
Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured peak-to-peak voltage for the AUX Channel signal by reference device (reference
source or reference sink) shall be within the conformance limits as specified in the specification
mentioned under the “PASS Condition” section for this test.
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AUX Channel Eye Sensitivity Test
Test ID
125041 — AUX Channel Eye Sensitivity Test (Source)
125051 — AUX Channel Eye Sensitivity Test (Sink)
Test Overview
The objective of the test is to evaluate the sensitivity to the AUX Channel Eye Opening of the DUT as
per the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Stimulus
Source—Unigraf DPR-100 Compact Sized DisplayPort Reference Sink
Sink—Unigraf DPT-200 Compact Sized DisplayPort Reference Source
Measurement Procedure
1
Set up the AUX Channel voltage level of the reference device (reference source or reference sink)
to the desired settings based on the settings in the Configuration Variable.
2
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Trigger Setup.
3
Generate FUNC1 signal, which is the first differential signal of the AUX Channel.
4
Set up the parameter of the measurement:
a Enable measurement of all edges to obtain a statistical value of the measurement.
b Set up the measurement threshold.
c Set up the Clock Recovery.
5
Initialize the AUX Channel transaction and acquire the differential AUX Channel signal.
6
Check if the reference device could detect the transaction or not.
7
Decode the AUX Channel signal and check whether the transaction passed or failed.
8
Report the measurement results.
PASS Condition
Determine whether the AUX Channel communication is successful. For example, the Transmitter
DUT sends an AUX Request to the Reference Receiver. The Reference Receiver acknowledges and
the Transmitter DUT responds to the to indicate that the acknowledgment was successfully received.
PASS = No errors observed in the response
FAIL = One or more errors observed
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Test References
See:
• SlimPort Compliance Test Specification Version 1, Section 2.2
• VESA DisplayPort PHY Compliance Test Specification Version 1.2b, Section 8.2
• VESA DisplayPort Standard Version 1, Revision 2a, Section 3.4.2, Table 3-6
Expected/Observable Results
The measured AUX Channel transaction shall be within the conformance limits as specified in the
specification mentioned under the “PASS Condition” section for this test.
898
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
24 SlimPort Inrush Tests
Overview / 900
Inrush Energy Power Test / 903
Inrush Peak Current Test / 905
24
SlimPort Inrush Tests
Overview
This section describes the normative and informative inrush tests for compliance verification of
SlimPort source and sink, which is a power consumer.
Test Point
The test fixture for inrush tests implements the schematic shown in Figure 181.
Figure 181
Schematics for testing a Power Consumer Device
The test fixture must be designed and used according to the following guidelines:
• A high gate voltage FET on the MyDP_PWR line is recommended to allow a fast connect
capability, which allows a single connection event for testing. Without such an arrangement,
multiple connections will be required to obtain a reasonable “worst-case” attachment event.
• Connection length between the power supply and the test fixture must be minimized. A
maximum of four inches is recommended.
• The power supply must have enough outrush capability as to not negatively affect the test
fixture’s outrush capability.
• The power supply must be run at 5.5V (5.0V + 10%) read across VC.
Any Power Consumer test fixture must be calibrated using the Power User test fixture, as shown in
Figure. Testing with the two fixtures combined should result in the approximate values given below. If
required, the component values on the Power Consumer test fixture should be adjusted to match the
expected results.
For Source:
• VC steady before connection = 5.5V
• Inrush Current = ~9.0A
For Sink:
• VC steady before connection = 3.6V
• Inrush Current = ~13.0A
900
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Inrush Tests
24
Setting Up the DisplayPort Compliance Test Application for SlimPort Inrush Tests
Perform the following steps before you run the compliance tests on the DUT:
1
Connect the appropriate test fixture to the device under test (DUT).
2
Start the automated testing application as described in “Starting the DisplayPort
Electrical Performance Compliance Test Application" on page 53.
3
On the DisplayPort Compliance Test Application, click the Set Up tab (see Figure 182).
Figure 182
Set Up tab on the DisplayPort Compliance Test App
4
To test for compliance with SlimPort Standards, select MyDP HBR25 from the drop-down options
in the Test Specification area and select AUX PHY and Inrush Tests in the Test Selection area.
5
De-select Show Normative Tests Only, if you want to run Informative Tests also. By default, this
check-box is selected.
6
Click the Test Setup button. The Test Setup wizard displays. Define the DUT parameters,
connection type and various settings required to run the tests. Refer to “Setting Up for AUX PHY and
Inrush Tests" on page 881 to know in detail how to set up the DUT for Inrush Tests.
7
After making the required changes under the Set Up tab, click the Select Tests tab to select a test
or a group of tests that you wish to run. Note that the tests displayed under this tab are
dependent on the parameters defined in the Set Up tab and the Test Setup dialog.
8
Once you select the tests under the Select Tests tab, the automated application automatically
optimizes the configuration options under the Configure tab. However, you may manually make
changes to one or more parameters, if required, for test runs under Compliance Mode or Debug
mode.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
901
24
SlimPort Inrush Tests
9
Click the Connect tab to see the connection diagram for the selected tests along with the
instructions to establish the physical connection. During test runs, the automated application
may prompt you for changes in the connection/physical setup, if required.
10 Run the selected tests and view the test results under the Resul ts tab once all test runs are
complete.
Refer to the Keysight U7232D DisplayPort Compliance Test Application’s Online Help for detailed
description on the working and functionality of each of the features/tabs on the Compliance Test
Application.
902
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Inrush Tests
24
Inrush Energy Power Test
Test ID
127000 — Inrush Energy Power Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Power (Ps) = Id*Vs
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush energy power measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Current ResultantPEAK_CURRENT_Power_Consumer < 9 Amps
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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24
SlimPort Inrush Tests
Test References
See:
For Source:
• SlimPort Compliance Test Specification Version 1, Section 2.3
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.5
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
For Sink:
• SlimPort Compliance Test Specification Version 1, Section 5.2
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 3.4
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
Expected/Observable Results
The measured worst case inrush energy power for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
904
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
SlimPort Inrush Tests
24
Inrush Peak Current Test
Test ID
127001 — Inrush Peak Current Test
Test Overview
The objective of the test is to evaluate the Inrush energy at the power supply input of a power
consuming DUT according to the specification limits.
Test Conditions
Test Parameter
Cond ition
Test Point
TP2
Measurement Procedure
1
Configure the Acquisition Setup and the Vertical Scale of the input signal based on the settings in
the Configuration Variable.
2
Generate FUNC1 signal (filtered Vd) by applying the low-pass filter on the Vd signal.
3
Generate FUNC2 signal (Current) by applying the following equation:
Current (Id) = Vd/Rm
4
Generate FUNC3 signal (Power) by applying the following equation:
5
Set up the trigger level of Vd signal and acquire the input signal.
6
Identify the first and the last points where the filtered Vd signal crosses the crossing point.
7
Calculate the Inrush Energy Power by summing the area under the power (FUNC3 signal) from
the first point to the last point where the filtered Vd signal crosses the crossing point.
8
Calculate the Inrush peak current using the following equation:
Power (Ps) = Id*Vs
Inrush Peak Current (Id_Peak) = Vd_Peak/Rm
where, Vd_Peak is the peak voltage on the Vd signal from the first point to the last point where
the filtered Vd signal crosses the crossing point (06A * Rm).
9
Repeat step 5 to 8 ten times to find the worst case (maximum) of inrush energy power and inrush
peak current.
10 Report the inrush peak current measurement results.
PASS Condition
Power Consumer Requirements:
•
Evaluated Inrush Energy (mJ) ResultantENERGY_Power_Consumer < 0.4mJ
•
Evaluated Inrush Current ResultantPEAK_CURRENT_Power_Consumer < 9 Amps
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
905
24
SlimPort Inrush Tests
Test References
See:
For Source:
• SlimPort Compliance Test Specification Version 1, Section 2.3
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 2.5
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
For Sink:
• SlimPort Compliance Test Specification Version 1, Section 5.2
• VESA Mobility DisplayPort (MyDP) Compliance Test Specification Version 1.0, Section 3.4
• VESA Mobility DisplayPort (MyDP) Standard Version 1, Section 6
Expected/Observable Results
The measured worst case inrush peak current for the power consuming DUT shall be within the
conformance limits as specified in the specification mentioned under the “PASS Condition” section
for this test.
906
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
25 Calibrating the Infiniium
Oscilloscope
To Run the Self Calibration / 908
Internal or Self Calibration / 909
This section describes the Keysight Infiniium Oscilloscopes calibration procedures.
25
Calibrating the Infiniium Oscilloscope
To Run the Self Calibration
NOTE
Let the Oscilloscope warm up before adjusting. Warm up the Oscilloscope for 30 minutes before
starting calibration procedure. Failure to allow warm up may result in inaccurate calibration.
The self calibration uses signals generated in the Oscilloscope to calibrate Channel sensitivity,
offsets, and trigger parameters. You should run the self calibration
•
yearly or according to your periodic needs,
•
when you replace the acquisition assembly or acquisition hybrids,
•
when you replace the hard drive or any other assembly,
•
when the oscilloscope’s operating temperature (after the 30 minute warm-up period) is more than
±5 °C different from that of the last calibration.
Before you begin calibrating the Infiniium Oscilloscope in preparation for running the DisplayPort
automated tests, you need the equipments described in the section Other Equipment (required for
Internal/Self Calibration of the Infiniium Oscilloscope) of the “Required Equipment and Software" on
page 3.
908
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
Internal or Self Calibration
NOTE
Calibration time: It takes approximately 1 hour to run the self calibration on the Oscilloscope,
including the time required to change cables from Channel to Channel.
1
Let the Oscilloscope warm up before running the Self Calibration.
Perform self calibration only after the oscilloscope has run for 30 minutes at ambient
temperature with the cover installed. Calibration of an Oscilloscope that has not warmed up may
result in an inaccurate calibration.
2
From the Infiniium Oscilloscope’s main menu, click Utilities>Calibration....
Figure 183
Accessing Calibration dialog on the Oscilloscope
The Calibration dialog appears.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
909
25
Calibrating the Infiniium Oscilloscope
3
To start the calibration process:
a Clear the Cal Memory Protect checkbox.
You cannot run self calibration if this box is checked. See Figure 184.
Figure 184
Clearing Cal Memory Protect and Starting Calibration
b Click Start to begin calibration.
c Follow the on-screen instructions.
910
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
d During the calibration of any Oscilloscope Channel, if the oscilloscope prompts you to perform
a Time Scale Calibration, select Standard Cal and Defaul t Time Scale in the Calibration Options
dialog.
Figure 185
Selecting options from the Calibration Options dialog
The options under the Calibration Options dialog are:
• Standard Calibration—Oscilloscope does not perform time scale calibration and uses calibration
factors from the previous time scale calibration and the reference signal is not required. The
rest of the calibration procedure continues.
• Standard and Time Scale Cal—Oscilloscope performs time scale calibration. You must connect a
reference signal to the Oscilloscope Channel, after ensuring that the reference signal meets
the following specifications. Failure to meet these specifications result in an inaccurate
calibration.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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25
Calibrating the Infiniium Oscilloscope
• Standard Cal and Defaul t Time Scale—Oscilloscope uses the default time scale calibration factors
and does not require the 10 MHz reference signal. The rest of the calibration procedure
continues.
e Disconnect everything from all inputs and AUX Out.
f
Connect the calibration cable from AUX Out to a specific Channel.
g Connect the calibration cable from AUX Out to each of the Channel inputs as requested.
h Connect the 50 Ω BNC cable from the AUX Out to the AUX Trig on the front panel of the
Oscilloscope.
912
i
A Passed/Failed indication is displayed for each calibration section. If any section fails, check
the calibration cables and run the Oscilloscope Sel f Test... in the Utilities... menu.
j
After the calibration procedure is completed, click Close.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
Probe Calibration and De-skew
Along with calibrating the Infiniium Oscilloscope, it is a good practice to calibrate and de-skew the
probes, before you start running the automated tests.
Differential SMA Probe Head Attenuation/Offset Calibration
Perform the following steps
1
Connect a shorting cap to the center SMA connector of the Differential SMA Probe Head.
2
Connect the BNC connector of the SMA to BNC adapter to AUX Out on the front panel of the
Infiniium Oscilloscope.
3
Using the Differential SMA Probe Head, connect the Oscilloscope’s AUX Out to the positive (+)
side of InfiniiMax Probe Amplifier. Keep the negative (-) side of the InfiniiMax Probe Amplifier
open.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
913
25
Calibrating the Infiniium Oscilloscope
4
On the Infiniium Oscilloscope,
a Click Setup>Channel 1....
b The Channel dialog displays to set up Channel 1 of the Oscilloscope.
914
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
c Click Probe.... The Probe Configuration dialog displays.
d In the Probe Head block, click the Select Head... button.
e Select N5380A/B from the list.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
915
25
Calibrating the Infiniium Oscilloscope
f
In the Calibration Status area, click the Cal... button corresponding to Atten/Offset.
g The Probe Calibration dialog displays. Click Start Atten/Offset Cal....
h The Calibration wizard displays. Follow the on-screen instructions. At the end of the
Atten/Offset Calibration, perform the Skew Calibration for the Differential SMA Probe Head.
916
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
Differential SMA Probe Head Skew Calibration
This procedure ensures that the timing skew errors between channels are minimized. After the
Atten/Offset Calibration is done, perform the following steps for skew calibration:
1
On the Probe Calibration dialog, click Start Skew Cal....
2
The Calibration wizard displays. Follow the on-screen instructions.
Differential Socketed Probe Head Atten/Offset Calibration
Perform the following steps
1
Ensure that an InfiniiMax Probe Amplifier, attached to a Differential Socketed Probe Head is
connected to Channel 1 of the Oscilloscope.
2
Install the 80 Ω resistors into the Differential Socketed Probe Head. These resistors are required
only for probe calibration and de-skew.
3
Connect the De-Skew fixture to AUX Out on the front panel of the Infiniium Oscilloscope.
4
Clip the resistors on the De-Skew fixture.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
917
25
Calibrating the Infiniium Oscilloscope
5
On the Infiniium Oscilloscope,
a Click Setup>Channel 1....
b The Channel dialog displays to set up Channel 1 of the Oscilloscope.
918
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
c Click Probe.... The Probe Configuration dialog displays.
d In the Probe Head block, click the Select Head... button.
e Select E2678A/B from the list.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
919
25
Calibrating the Infiniium Oscilloscope
f
In the Calibration Status area, click the Cal... button corresponding to Atten/Offset.
g The Probe Calibration dialog displays. Click Start Atten/Offset Cal....
h The Calibration wizard displays. Follow the on-screen instructions. At the end of the
Atten/Offset Calibration, perform the Skew Calibration for the Differential Socketed Probe
920
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope
25
Head.
Differential Socketed Probe Head Skew Calibration
This procedure ensures that the timing skew errors between channels are minimized. After the
Atten/Offset Calibration is done, perform the following steps for skew calibration:
1
On the Probe Calibration dialog, click Start Skew Cal....
2
The Calibration wizard displays. Follow the on-screen instructions.
For more information on connecting probes to the Infiniium Oscilloscope, refer to the De-skew and
Calibration manual. This manual comes together with the E2655A/B/C Probe De-skew and
Performance Verification Kit.
NOTE
Each probe is calibrated to the Oscilloscope Channel to which it is
connected. Do not switch probes between Channels or other Oscilloscopes,
else it becomes necessary to calibrate them again. One of the best practices
is to label the probes with the Channel number on which they are
calibrated.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
921
25
922
Calibrating the Infiniium Oscilloscope
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Keysight U7232D DisplayPort Electrical Performance
Compliance Test Application
Method of Implementation
A
DisplayPort AUX Channel
Cookbook for Tx Automated
Test
AUX Channel and Hot Plug Detect (HPD) / 924
DPTC Controller / 925
Automated Test Sequence / 926
This section describes what is required to implement the test automation features architected in the
DisplayPort Specification 1.1a. Automated DisplayPort tests require a source device that is able to
change test conditions such as data rate, level, pre-emphasis, test pattern, and SSC options as
requested. This cookbook provides a guide on how to perform these tasks using a sink emulator such
as Keysight W2642 DPTC controller.
A
DisplayPort Aux Channel Cookbook for Tx Automated Test
AUX Channel and Hot Plug Detect (HPD)
DisplayPort devices communicate with each other through the AUX Channel. The DisplayPort port
sink device provides memory that a source and a sink could read from or write to. The DisplayPort
Specification 1.1a has reserved a set of DCPD registers for the purpose of test automation.
There is also a HPD line between a source and a sink. For automation purposes, the HPD pulse is
used as an IRQ to notify the source about an automated test request.
924
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort Aux Channel Cookbook for Tx Automated Test
A
DPTC Controller
The Keysight DPTC Controller can be used as a sink emulator that tells the source to output desired
signals. Some fundamental functions provided which enable automation are:
NOTE
•
SetByte(Address, Value)
•
Send HPDPulse(Length)
•
PlugIn(Emulate Plug in event)
•
PlugOut(Emulate Plug out event)
Function names listed are for informative purpose only. They are not reflected to actual API call.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
925
A
DisplayPort Aux Channel Cookbook for Tx Automated Test
Automated Test Sequence
This section provides information on how to enable test automation in DisplayPort Transmitter test.
You should specify the Max link rate, lane count, preEmphasis, Level, and SSC options from the compliance
application.
OPTION 1
Step 1: Emulate successful link training (For SSC)
1
This step emulates an unplug and plug in event to initiate a fake link training.
2
To do this, the DPTC controller initiates the sequence below:
a Emulate PlugOut Event to put HPD line in Low for at least 2 ms. Source should RESET.
b Set Link Capability fields.
MAX_LINK_RATE = 0x0A.
MAX_LANE_COUNT = 0x04.
MAX_DOWNSPREAD = 0x01 to enable SSC / 0x00 to disable SSC.
c Set 0x202 (LANE0_1_STATUS) = 0x77.
d Set 0x203 (LANE2_3_STATUS) = 0x77.
e Set 0x204 (LANE_ALIGN__STATUS_UPDATED) = 0x81.
f
Note: 0x202, 0x203 and 0x204 must be preset for automation purposes.
g Emulate PlugIn Event to put HPD line in High.
h Source clears Link Configuration field and reads Link Capability.
i
Source enables/disables SSC based on the value of MAX_DOWNSPREAD (Enable SSC if value
is 1).
j
Source outputs 0x01 to TRAINING_PATTERN_SET.
k Source reads LANE0_1_STATUS, LANE2_3_STATUS and LANE_ALIGN__STATUS_UPDATED.
Because these registers are already set in a previous step, the source exits the Clock Recovery
Sequence for Link Training (Figure 186) and goes to the Channel Equalizer sequence for Link
Training (Figure 187).
l
Source set TRAINING_PATTERN_SET to 0x02.
m Source reads LANE0_1_STATUS, LANE2_3_STATUS and LANE_ALIGN__STATUS_UPDATED.
Because these registers are already set in a previous step, the source exits the Channel
Equalizer Sequence and ends the whole link training process.
926
3
From the state machine of link training of Display Port Specification 1.1a, these sequences cheat
a Display Port source into thinking that link training has already been performed without looping
through the actual link training. The Display Port Source device should exit link training
successfully.
4
The AUX Controller then checks DOWNS_SPREAD_CTRL if SSC support is changed.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort Aux Channel Cookbook for Tx Automated Test
Figure 186
A
Clock Recovery Sequence
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
927
A
DisplayPort Aux Channel Cookbook for Tx Automated Test
Figure 187
Clock Equalizer Sequence
Step 2: Change Bit Rate and Number of Lanes
1
To change the bit rate and Number of Lanes, the DPTC controller initiates the sequence below:
a Set 0x202 (LANE0_1_STATUS) = 0x77.
b Set 0x203 (LANE2_3_STATUS) = 0x77.
c Set 0x204 (LANE_ALIGN__STATUS_UPDATED) = 0x81.
d SetBit 0x201.1 (AUTOMATED_TEST_REQUEST).
e Clear 0x218 (TEST_REQUEST).
f
SetBit 0x218.0 (TEST_LINK_TRAINING).
g SetByte 0x219 (TEST_LINK_RATE) to 0x0A (2.7 Gbps) or 0x06 (1.62 Gbps).
h SetByte 0x220 (TEST_LANE_COUNT) to the desired lane count.
i
928
Trigger an IRQ Event (Send 1 ms HPD Pulse).
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
DisplayPort Aux Channel Cookbook for Tx Automated Test
2
A
When a 1 ms HPD pulse is received:
a Source reads bit 0x201.1 (AUTOMATED_TEST_REQUEST). If 0x201.1 is asserted go to 2.
b If 0x218.0 is asserted, Source clears LINK_BW_SET and LANE_COUNT_SET.
c Source reads 0x219 and 0x220 and output signals with desired lane count and data rate.
Step 3: Change PreEmphasis, Level, and Test pattern
1
To Change PreEmphasis, Level, and Test pattern, the DPTC initiates the following sequences:
a Set 0x202 (LANE0_1_STATUS) = 0x77.
b Set 0x203 (LANE2_3_STATUS) = 0x77.
c Set 0x204 (LANE_ALIGN__STATUS_UPDATED) = 0x81.
d SetBit 0x201.1 (AUTOMATED_TEST_REQUEST).
e Set 0x206 (ADJUST_REQUEST_LANE0_1) and 0x207 (ADJUST_REQUEST_LANE2_3) with
desired level and preemphasis.
Table 172
Mapping table for PreEmphasis and Level
VOLTAGE_SWING_LANEX (2 bits)
00:
400 mV
01:
600 mV
10:
800 mV
11:
1200 mV
PREEMPHASIS_SWINT_LANEX (2 bits)
00:
0 dB
01:
3.5 dB
10:
6 dB
11:
9.5 dB
f
Clear 0x218 and SetBit 0x218.3 (TEST_PATTERN_REQUEST).
g Set 0x248 (PHY_TEST_PATTERN) to desired pattern.
Bits 1:0 = PHY_TEST_PATTERN_SEL
00
= No test pattern selected
01
= D10.2 without scrambling
10
= Symbol_Error_Measurement_Count
11
= PRBS7V
h Send IRQ to source (HPD 1 ms Pulse).
2
When a 1 ms HPD pulse is received:
a Source reads bit 0x201.1 (AUTOMATED_TEST_REQUEST). If 0x201.1 is asserted, go to step 2.
b Source reads 0x248, 0x206, 0x207 and outputs signals with desired pattern, PreEmphasis, and
Level.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
929
A
DisplayPort Aux Channel Cookbook for Tx Automated Test
It might be necessary to repeat step 3 to set TEST_PATTERN back to “No pattern” (0x248=0h)
before repeating whole automation sequence (step 1 to 3).
NOTE
OPTION 2
This option provides a simple way to control test automation in one simple step, providing that a test
mode is supplied. However, it is less consistent with DisplayPort Automation scheme.
Step 1:
1
Source should always Scan for 0x201.1 (AUTOMATED_TEST_REQUEST).
2
Sink sets the following:
a SetByte 0x219 (TEST_LINK_RATE) to (2.7 Gbps) or 0x06 (1.62 Gbps)
b SetBit 0x03.1 (TEST_DOWNSPREAD) to turn on SSC. Clear 0x21A.1 to turn off SSC.
c SetByte 0x220 (TEST_LANE_COUNT) to desired lane count.
d Set 0x206 (ADJUST_REQUEST_LANE0_1) and 0x207 (ADJUST_REQUEST_LANE2_3) with
desired level and preemphasis.
e Set 0x248 (PHY_TEST_PATTERN) to desired pattern.
930
3
Sink sets 0x201.1.
4
When the Source detects 0x201.1 being set, it should respond by outputting signals as in step 2.
5
Sink wait for 3 seconds.
6
Sink set bit 0x218.0 back to 0.
7
Alternatively, HPD_IRQ (1 ms) mechanism could be used instead of keep scanning 0x201.1.
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
Index
A
Inrush Peak Current, 257, 259
Inter Pair Skew, 281
Inter-Pair Skew, 113
Intra Pair Skew, 283
Intra-Pair Skew, 180
Maximum Data Rate, 120, 132
Minimum Data Rate, 120, 132
Non ISI jitter, 80
Non Pre-Emphasis Level, 87
Non Transition Voltage Range, 103
Non-ISI Jitter, 202, 225
Peak to Peak Voltage, 108
peak-to-peak value of the non-transition
voltage, 87, 95
peak-to-peak value of the transition
voltage, 87, 95, 103
peak-to-peak voltage-1010, 143
peak-to-peak voltage-1100, 143
Post-Cursor 2 Level, 143
Post-Cursor 2 ratio, 143
Power (Ps), 257, 259
pre-emphasis delta, 95
pre-emphasis level, 95
Slope, 137
SSC Modulation Deviation, 127, 132
Total Jitter, 154
total jitter, 71, 196
Transition Voltage (VTrans), 180, 282
Aux Channel and Hot Plug Detect
(HPD), 924
Aux Channel tests, 231, 253, 261, 461,
483, 491, 681, 703, 877, 899
Aux Channel tests, setting up for, 235,
265, 465, 496, 685, 881
C
cable eye diagram tests, 209, 439, 659,
855
Cable Model
Worst Case, 58
Cable model
Serial Data Equalization software, 59
transfer function, 58
zero length, 59
calibrating the oscilloscope, 907
Characteristics
aggressor signals, 214
configure, 54
connect, 54
connection, Source Aux Channel
tests, 63, 213, 241, 268, 293, 418,
443, 471, 499, 521, 639, 663, 691, 718,
835, 859, 887
CTLE, 59
HBR (2.7 Gbps), 59
HBR2 (5.4 Gbps), 60
D
DisplayPort automated testing—at a
glance, 3
DisplayPort References, 8
DPTC controller, 925
Dual-Dirac Model, 71
E
Entitlement Certificate, 49
Equalized signal, 193, 200, 206, 224, 229
Equation
Current (Id), 257, 259
Eye Mask Height, 151
Eye Mask Height Derate (Random
Noise), 150
Eye Mask Width, 151
Eye Mask Width Derate (Random
Jitter), 150
H
high gate voltage, 254
Hold Off Time, Aux Channel tests set
up, 237, 467, 687, 883
I
in this book, 6
K
keyboard, 3
L
license code, 49
license key, installing, 49
Lower Threshold, Aux Channel tests set
up, 238, 468, 688, 884
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
M
MATLAB script, 243, 249
mouse, 3
N
non-transition voltage
measurement, 85, 86, 93, 94, 101,
102
O
Offline Mode, 239
Offset, Aux Channel tests set up, 238,
468, 688, 884
Online Help, 8
Option ID Number, 49
P
peak-to-peak voltage test, Source Aux
Channel, 247, 477, 697, 893
precision 3.5 mm BNC to SMA male
adapter, 3
probing for cable eye diagram
tests, 444
probing for main link frequency
compliance tests, 345
probing for source non-ISI jitter
tests, 306
Probing, Source Aux Channel tests, 63,
241, 268, 293, 418, 443, 471, 499, 521,
691, 718, 887
R
Reference Sink device, 241
Reference Source device, 241
report, 54
results, 54
run tests, 54
S
select tests, 54
sink eye diagram tests, 413, 635, 831
Source Aux Channel tests, 243, 257,
259, 269, 271, 273, 276, 278, 280, 282,
473, 487, 489, 500, 502, 504, 507, 509,
511, 513, 693, 707, 709, 889, 903, 905
931
Index
source eye diagram tests, 57, 231, 253,
261, 285, 461, 483, 491, 515, 681, 703,
711, 877, 899
starting the DisplayPort automated
test application, 53
Stress Signal Calibration, 185
T
threshold levels, 238
Threshold, Aux Channel tests set
up, 238, 468, 688, 884
transition voltage measurement, 85,
86, 93, 94, 101, 102
Trigger Level, Aux Channel tests set
up, 237, 467, 687, 883
trigger setup configuration, 239
U
U7232A DisplayPort Electrical
Performance Compliance Test
Application, 3
Upper Threshold, Aux Channel tests
set up, 238, 468, 688, 884
V
Vertical Scale, Aux Channel tests set
up, 238, 468, 688, 884
W
W2642 DPTC controller, 923
Web Site
Keysight, 48
VESA, 3
932
Keysight U7232D DisplayPort Electrical Performance Compliance Test Application
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