STMicroelectronics SPEAr1310 User Manual

STMicroelectronics

EVALSPEAr320CPU

SPEAr320 CPU evaluation board

UM1015

User manual

Doc ID 18124 Rev 1

October 2010 www.st.com

BLANK

UM1015

User manual

EVALSPEAr320CPU

SPEAr320 CPU evaluation board

Introduction

This document applies to revision 2.0 SPEAr320 CPU evaluation boards.

This board can be used to evaluate SPEAr320 microprocessors; the evaluation board kit comprises one board, one serial cable interface, and one power supply.

CPU board features

■

■

■

■

■

■

■

SPEAr320 embedded MPU

Up to 2 Gbit DDR2 333 MHz (standard 128 Mbytes)

Up to 16 Mbyte Serial Flash memory (standard 8 Mbytes)

Two USB 2.0 full host port channels

One USB 2.0 host device port

One serial port (up to 115 baud)

JTAG Debug ports

Figure 1.

SPEAr320 CPU evaluation board

Top Bottom

October 2010 Doc ID 18124 Rev 1 3/38 www.st.com

2

3

4

7

8

5

6

Contents

Contents

1

A

UM1015

Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2

Booting procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Expansion connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Switch and jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1

Switch 1 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Switch 2 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3

Jumpers and connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.1

Hardware revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.2

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

License agreements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4/38 Doc ID 18124 Rev 1

UM1015

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Switch SW1 bits [2:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CPU board extension connector J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CPU board extension connector J13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Switch 1 (SoC functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Switch 1 (debug configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Switch 1 (functional configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Switch 2 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CPU board components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Doc ID 18124 Rev 1 5/38

List of figures

List of figures

UM1015

Figure 1.

SPEAr320 CPU evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2.

EVALSPEAr320CPU board block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

Serial cable setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4.

86-pin connectors (J12 and J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Schematic interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6.

DDR interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.

USB interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8.

USB power and optional part schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9.

Miscellaneous interfaces schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10.

Power supply schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11.

Customization interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.

Daughterboard interface schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13.

Schematic revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14.

SPEAr320 CPU evaluation board layout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15.

SPEAr320 CPU evaluation board layout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6/38 Doc ID 18124 Rev 1

UM1015 Getting started

Warning: This board contains static sensitive devices.

The EVALSPEAr320CPU board is shipped in protective anti-static packaging. Do not submit the board to high electrostatic potentials, and follow good practices for working with static sensitive devices.

● Wear an anti-static wristband. Wearing a simple anti-static wristband can help prevent ESD from damaging the board.

●

●

Zero potential. Always touch a grounded conducting material before handling the board, and periodically while handling it.

Use an anti-static mat. When configuring the board, place it on and anti-static mat to reduce the possibility of ESD damage.

● Handle only the edges. Handle the board by its edges only, and avoid touching board components.

1.1 Connections

Refer to

Figure 14 on page 31 .

1.

Connect a serial cable from connector J17 (serial link) to a host PC.

2. On the host PC running Windows or Linux, start the Terminal program.

3. Connect the +5 V voltage adapter (supplied in the EVALSPEAR320CPU package) to the J11 power voltage connector on the CPU board.

4. Apply power to the board.

5. The Terminal program displays a sequence of boot messages followed by the Linux console prompt.

For more information, refer to user manual UM0844 Getting started with Linux for SPEAr, available at www.st.com/spear.

The SPEAr320 CPU evaluation board can boot a Linux kernel that has been pre-installed in the serial NOR Flash.

At power on, the serial port outputs a brief header message with some uBoot information

(uBoot version, SDK version, and some internal hardware information). At this point you can choose to:

●

●

Stop the system directly in uBoot: Press the spacebar on the host computer keyboard before the boot delay time expires (default is 3 seconds).

Boot Linux: The system logs you in automatically as super user, and displays the

Linux shell prompt on the screen.

Doc ID 18124 Rev 1 7/38

Block diagram

Figure 2.

EVALSPEAr320CPU board block diagram

UM1015

2.0.1

8/38

Dynamic memory subsystem

The Dynamic memory subsystem comprises three major parts:

Memory chip

The SPEAr320 MPU supports up to 256 Mbytes of memory. Place and route is provided for

2 chips but only one has been populated. The memory used is a Micron DDR2 device, its part number is MT47H64M16HR-3 and its size is 128 Mbits x 8 (16 Mbits x 8 x 8 banks).

Local power supply

The local power supply is based on a monolithic voltage regulator for the chip set and

DDR2/3 (PM6641). It is generated locally in order to minimize the layout impact and also to avoid any noise injection between different subsystems.

Signal termination

A parallel termination is added on the clock lines to compensate, if needed, for the layout dissymmetry. Two 100k ohm resistors are used for each line in order to obtain an impedance of 50 ohms. All the other terminations are directly inside the pads (both on the

SPEAr320 MPU and the memory sides).

Doc ID 18124 Rev 1

UM1015

2.0.2

Block diagram

Static memory subsystem (Serial Flash memory)

The SPEAr320 MPU supports up to 16 Mbytes of Serial Flash memory. Place and route for

2 blocks of 8 Mbytes are provided on the board, but only one is populated. It is based on an

M25P64-VMF6P (Numonix) Serial Flash memory device.

Resistor R8 protects the Flash memory from any unwanted write access.

Host ports

The board has two host ports that are fully compliant with the USB 2.0 specification (two controllers with one port each). This means that the two hosts can work in concurrent mode with the maximum possible bandwidth. Each host has also full control of the VBUS supplied by the ST2052 power switch that also provides over current protection in case of a short circuit in the USB cable.

Device port

The board has one USB 2.0 device port.

The JTAG interface can be used for static debugging, which means that it is possible to set a breakpoint, and when the system stops, verify the contents of the memory or registers, or both, and modify them if needed.

To select the debug feature, set Switch SW1 bits [2:1].

Table 1.

Bit 2

0

0

Switch SW1 bits [2:1]

Bit 1

0

1

Description

No debug features available

The ARM JTAG is connected to J4

For more information on the ETM interface, refer to the trace box manufacturer’s documentation (www.lauterbach.com, www.agilent.com, www.yokogawa.com).

One serial interface port is available. Typically used as an OS monitor, this port is available on the J17 connector. It is possible to simulate a cross cable by changing the position of the

J22 jumpers.

Figure 3.

Serial cable setting

2

J22

4

1 3

Nul

Modem

Cable

2

J22

4

1 3

Cross

Cable

Doc ID 18124 Rev 1 9/38

Block diagram UM1015

2.0.7

The real time clock (RTC) is powered by an external battery (3V) in order to prevent data loss even if the main power supply is switched off.

General power supply

●

●

●

●

From a 5 V external AC/DC regulator power source, this block generates all the required voltages as follows:

1.2V (Switching regulator PM6641) to supply the internal logic of the SPEAr320 MPU

1.8V (Switching regulator PM6641) for the DDR2 memory

2.5V (LDO regulator) for the analog portion of SPEAr320

3.3V (Switching regulator PM6641) to supply the other interfaces

A power monitor is also present to provide the general reset of the board.

A manual reset button (P1) on the top of the board (see Figure 14 on page 31 ) resets the

microprocessor on the core board.

10/38 Doc ID 18124 Rev 1

UM1015 Expansion connectors

Note:

The CPU board has two 86-pin connectors (J12 and J13) that are used to extend the board.

On the board the connectors are horizontally center-aligned, and the distance between the mechanical holes is 3400.00 th.

Table 2 lists connector J12 pins.

Table 3 on page 13

lists connector J13 pins.

Connector through hole pins (10 pins) are connected to GND

Figure 4.

86-pin connectors (J12 and J13)

75 1

76 2

Table 2.

Pin

CPU board extension connector J12

Description

1 +1.8V

3 +1.8V

5 +1.8V

7 +1.8V

9 PL_GPIO2 (RS232-TX LVTTL)

(1)

11 PL_GPIO3 (RS232-RX LVTTL)

(2)

13 RS232-TX

(3)

15 RS232-RX

(4)

17 PL_GPIO42

19 PL_GPIO43

21 PL_GPIO34

23 PL_GPIO33

25 PL_GPIO16

27 PL_GPIO24

29 PL_GPIO20

31 PL_GPIO23

33 PL_GPIO18

Pin Description

2 +5V

4 +5V

6 +5V

8 +5V

10 PL_GPIO44

12 PL_GPIO39

14 PL_GPIO40

16 PL_GPIO38

18 PL_GPIO29

20 PL_GPIO37

22 PL_GPIO30

24 PL_GPIO28

26 PL_GPIO26

28 PL_GPIO27

30 PL_GPIO9

32 PL_GPIO13

34 PL_GPIO8

Doc ID 18124 Rev 1 11/38

Expansion connectors UM1015

Table 2.

Pin

CPU board extension connector J12 (continued)

Description Pin Description

35 PL_GPIO11

37 PL_GPIO19

39 PL_GPIO15

41 PL_GPIO14

43 PL_GPIO36

45 PL_GPIO41

47 PL_GPIO35

49 PL_GPIO31

51 PL_GPIO32

53 PL_GPIO25

55 PL_GPIO22

57 PL_GPIO21

59 PL_GPIO17

61 PL_GPIO12

63 PL_GPIO10

77

79

81

83

85

65 PL_GPIO7

67 PL_GPIO1

69 PL_GPIO0

71 NC

73 NC

75 NC

GND

(5)

78

80

82

36 PL_GPIO6

38 PL_GPIO4

40 PL_GPIO5

42 NC

44 NC

46 NC

48 NC

50 +2.5V

52 +2.5V

54 +2.5V

56 +2.5V

58 INRESET

60 nRESET

62 +1.2V

64 +1.2V

66 +1.2V

68 +1.2V

70 +3.3V

72 +3.3V

74 +3.3V

76 +3.3V

84

86

GND

(5)

1.

If J20 Jumper is set to pin2-3, otherwise NC.

2.

If J21 Jumper is set to pin2-3, otherwise NC.

3.

If J22 Jumper is set to pin2-4 and pin1-3, otherwise RS232-RX.

4.

If J22 Jumper is set to pin2-4 and pin1-3, otherwise RS232-TX.

5.

Physically connected to the internal metal plane of the connector. Pins 77 through 81 and 82 through 86 are shorted together.

12/38 Doc ID 18124 Rev 1

UM1015 Expansion connectors

Table 3.

Pin

CPU board extension connector J13

Description

1 PL_GPIO47

3 PL_GPIO49

5 PL_GPIO56

7 PL_GPIO58

9 PL_GPIO64

11 PL_GPIO45

13 PL_GPIO48

15 PL_GPIO50

17 PL_GPIO55

19 PL_GPIO59

21 PL_GPIO60

23 PL_GPIO65

25 PL_GPIO62

27 PL_GPIO68

29 PL_GPIO52

31 PL_GPIO53

33 PL_GPIO51

35 PL_GPIO54

37 PL_GPIO74

39 PL_GPIO77

41 PL_GPIO78

43 PL_GPIO81

45 PL_GPIO80

47 PL_GPIO84

49 PL_GPIO83

51 PL_GPIO86

53 PL_GPIO91

55 PL_GPIO90

57 PL_GPIO96

59 PL_GPIO88

61 PL_GPIO89

63 PL_GPIO92

65 PL_GPIO93

67 PL_GPIO97

69 PL_CLK4

Pin Description

2 +3.3V

4 PL_GPIO63

6 PL_GPIO46

8 PL_GPIO57

10 PL_GPIO61

12 PL_GPIO66

14 PL_GPIO69

16 PL_GPIO72

18 PL_GPIO73

20 PL_GPIO70

22 PL_GPIO67

24 PL_GPIO71

26 PL_GPIO75

28 PL_GPIO82

30 PL_GPIO76

32 PL_GPIO85

34 PL_GPIO87

36 PL_GPIO95

38 PL_GPIO79

40 PL_GPIO94

42 ADC VREFN

44 AIN0

46 GND

48 AIN1

50 GND

52 AIN2

54 GND

56 AIN3

58 GND

60 AIN4

62 GND

64 AIN5

66 GND

68 AIN6

70 GND

Doc ID 18124 Rev 1 13/38

Expansion connectors UM1015

Table 3.

Pin

CPU board extension connector J13 (continued)

Description Pin Description

77

79

81

83

85

71 PL_CLK3

73 PL_CLK2

75 PL_CLK1

GND

(1)

72 AIN7

74 GND

76 ADC VREFP

78

80

82

84

86

GND

(1)

1.

Physically connected to the internal metal plane of the connector. Pins 77 through 81 and 82 through 86 are shorted together.

14/38 Doc ID 18124 Rev 1

UM1015

4 Switch and jumper settings

Switch and jumper settings

Note:

Table 4.

Bit

Switch 1 (SoC functional configuration)

Description

1 Test – see Debug configuration below

2 Reserved

3 Reserved

4 Reserved

5 Reserved

6 BootSel – see Debug configuration below

Table 5.

Switch 1 (debug configuration)

2

0

Test bit

Debug configuration

1

0 Normal Mode (No debug enabled)

0 1 ARM1 JTAG connected to J4

1 0 Reserved

Table 6.

Switch 1 (functional configuration)

Test bit

Functional configuration

6 5 4 3

1 0 1 1 Configuration 3

When Switch SW1-x is in the ON position, the bit value is 0. When Switch 1 is in the OFF position, the bit value is 1.

Bits 3, 4, 5 and 6 enable you to set the Functional configuration. The default configuration is

Configuration 3. For other configurations, refer to the SPEAr320 user manual available at www.st.com/spear.

Doc ID 18124 Rev 1 15/38

Switch and jumper settings UM1015

Note:

Table 7.

Switch 2 settings

Boot from SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 SW2-7 SW2-8

On Off On Off On Off On USB_BOOT

ETH (parameter from I2C

ROM)

Off

On

ETH (parameter from SPI

ROM)

Off

Serial NOR (default setting) On

Parallel NOR 8 (EMI with ACK) Off

Parallel NOR 16 (EMI with

ACK)

Parallel NAND 8

Parallel NAND 16

Reserved for SPI

Reserved for I²C

On

Off

On

Off

On

Off

On

UART_BOOT

BootROM bypass

Parallel NOR 8 (EMI without

ACK)

Parallel NOR 16 (EMI without

ACK)

Reserved

Reserved

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

Off

On

On

Off

Off

On

On

Off

Off

On

On

Off

Off

On

On

On

Off

Off

On

On

Off

Off

On

On

Off

Off

On

On

Off

Off

Off

Off

Off

On

On

On

On

Off

Off

Off

Off

On

On

On

On

On

On

On

Off

Off

Off

Off

On

On

On

On

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

Off

On

On

On

On

On

On

On

On

On

On

On

On

On

Off

Off

Off

Off

On

On

Off

Off

Off

Off

If SW2-1 and SW2-2 are both off, B0 (pin PL_GPIO51) is in HiZ state, and can be controlled from the application board.

If SW2-3 and SW2-4 are both off, B1 (pin PL_GPIO52) is in HiZ state, and can be controlled from the application board.

If SW2-5 and SW2-6 are both off, B2 (pin PL_GPIO53) is in HiZ state, and can be controlled from the application board.

If SW2-7 and SW2-8 are both off, B3 (pin PL_GPIO54) is in HiZ state, and can be controlled from the application board.

SW2-1 and SW2-2 on: invalid condition

SW2-3 and SW2-4 on: invalid condition

SW2-5 and SW2-6 on: invalid condition

SW2-7 and SW2-8 on: invalid condition

16/38 Doc ID 18124 Rev 1

UM1015 Switch and jumper settings

4.3 Jumpers connectors

The jumpers and connectors numbered below refer to the CPU board schematics (available on www.st.com/spear).

Sheet 4

●

●

●

Connector J3 is a standard 20-pin 2.54 mm connector used for JTAG connections.

Jumper J5 enables the power supply to the Real Time Clock block.

If jumper J5 is closed, the RTC is powered (standard).

Connector J10 is a 2 vie 1.25 mm pitch connector for battery back-up with cable.

Sheet 5

● Connector J11 is a standard power connector for the ADC power supply with a 2.1-mm central pitch.

Sheet 6

● Jumpers J6, J7, J8 and J9 are serial jumpers for the SPEAr power rail.

All jumpers MUST be closed. This configuration is used for power measurements.

●

●

Sheet 7

●

●

Jumper J22 is a 4-pin symmetric IDC (or strip) connector that switches RX and TX signals for different types of RS-232 cables

(a)

:

– Two pins are connected to the ST3232 Receive/Transmit side.

– Two pins are connected to the RS-232 Receive/Transmit connector side.

Connector J17 is a connector for standard IDC-to-DSUB converters.

Jumper J20 switches between RS-232 transmit signals or GPIO2:

– If jumper is on pins 1 and 2, pin PL_GPIO2 is connected to U12 (ST3232) and the

COM0 is available on J17.

– If jumper is on pins 2 and 3, pin PL_GPIO2 is connected to the expansion connector J12 pin 9. In this case the COM0 is available on CN13.

Jumper J21 switches between RS-232 receive signals or GPIO3:

– If jumper is on pins 1 and 2, pin PL_GPIO3 is connected to U12 (ST3232) and the

COM0 is available on J17.

– If jumper is on pins 2 and 3, pin PL_GPIO3 is connected to the expansion connector J12 pin 11. In this case the COM0 is available on CN13.

a.

With 2 jumpers (inserted) it is possible to switch between two jumper inserted vertically and two jumpers inserted horizontally. This enables the serial cable (null modem cable) to be adapted to the CPU board.

Doc ID 18124 Rev 1 17/38

Board components

Table 8.

CPU board components

Component

Capacitor

Resistor

Resistor

Inductor

Designator

C1 C2 C3

C4 C5 C6

C7 C8 C9

C10 C11

C12 C13

C14 C15

C16 C17

C18 C19

C20 C21

C22 C23

C24 C25

C26 C27

C28 C29

C30 C31

C32 C33

C34 C35

C36 C37

C38 C39

C40 C41

C42 C43

C44 C45

C46 C47

C48 C49

C50 C56

C57 C58

C59 C60

C99 C100

C101 C102

R42 R43

R44 R45

R46 R47

R48 R50

R30 R31

R32 R33

R34 R35

R36 R37

R38 R72

R73 R74

0402

0603

0603

L3

Footprint

LPS3.9X3.9

Capacitor

Inductor

Resistor

Resistor

C89

L1 L2

R59 R60

R27 R28

0603

LPS3.9X3.9

0603

0603

Description

Ceramic capacitor 0.1uF 10% 10V X5R 0402

Resistor 0603 0 ohm

Resistor 0603 1k ohm 1% 0.1W

Power Inductor 1uH 1.7A 3.9x3.9mm SMD

Ceramic capacitor 2.2nF 10% 50V X7R 0603

Power Inductor 2.2uH 1.2A 3.9x3.9mm SMD

Resistor 0603 4.3 ohm 1% 0.1W

Resistor 0603 4.7k ohm 1% 0.1W

18/38 Doc ID 18124 Rev 1

UM1015

UM1015 Board components

Table 8.

Component

Resistor

Capacitor

Capacitor

Resistor

Capacitor

Capacitor

Capacitor

CPU board components (continued)

Designator

R10 R11

R12 R13

R14 R15

R16 R17

R18 R19

R20 R21

R22 R23

R24 R25

R26

C75 C76

C77

C61 C62

C63 C64

C65 C66

C67 C68

C69 C70

C71 C72

C73 C74

C98

0603

0603

0805

Footprint

R68

C78 C79

C87 C88

C91

C93

0603

0603

0603

1206

Description

Resistor 0603 10k ohm 1% 0.1W

Ceramic capacitor 10 nF 10% 50V X7R 0603

Ceramic capacitor 10uF 10% 10V X5R 0805

Resistor 0603 15k ohm 1% 0.1W

Ceramic capacitor 15pF 5% 50V COG 0603

Ceramic capacitor 22nF 10% 50V X7R 0603

Ceramic capacitor 22 uF Y5V -20+80% 6.3V 1206

Crystal oscillator Y2

Resistor R70

Crystal oscillator Y1

Capacitor

Capacitor

Resistor

Resistor

Capacitor

C92

C80 C81

R29

R69

C82 C83

C84 C85

C86 C94

C95 C96

C97

Resistor

Resistor

Resistor

Resistor

R49

R62 R63

R64 R65

R66 R67

R61

R2 R3 R4

R5 R6 R7

RAD-HC49

0603

XT38T

0603

0603

0805

0603

3528+

0603

0603

0603

0603

Crystal Oscillator 24MHz 30ppm through-hole

Resistor 0603 27k ohm 1% 0.1W

Crystal Oscillator 32.768KHz 20ppm d2x6mm

Ceramic capacitor 33 nF 10% 50V X7R 0603

Ceramic capacitor 33pF 5% 50V COG 0603

Resistor 0805 43.2 ohm 0.1% 0.1W

Resistor 0603 47k ohm 1% 0.1W

Tantalium Capacitor 47uF 10% 10V 3528-21

Resistor 0603 56k ohm 1% 0.1W

Resistor 0603 68k ohm 1% 0.1W

Resistor 0603 75k ohm 1% 0.1W

Resistor 0603 100 ohm 1% 0.1W

Doc ID 18124 Rev 1 19/38

Board components UM1015

Table 8.

CPU board components (continued)

Component Designator Footprint Description

Resistor

Resistor

Resistor

Resistor

Resistor

Resistor

Capacitor

Resistor

Battery

Ferrite bead

R1 R53

R55 R56

R57

R39 R40

R75

R58

R8 R9

C90

R41

U8

FB3 FB4

FB5 FB6

FB7

0805

0603

0603

0603

0603

0603

0603

0603

BR2032

0805

Resistor 0805 121k ohm 0.1% 0.1W

Resistor 0603 150 Kohm 1% 0.1W

Resistor 0603 150 ohm 1% 0.1W

Resistor 0603 330 ohm 1% 0.1W

Resistor 0603 390k ohm 1% 0.1W

Resistor 0603 470 ohm 1% 0.1W

Ceramic capacitor 470 pF 10% 50V X7R 0603

Resistor 0603 680 ohm 1% 0.1W

BATT BR2032: Coin type Lithium batterie 3V straight d20mm

Ferrite Murata BLM21BD601SN1D

600 ohm/100MHz 200mA 0.35hm 0805

Diode D3 SOT23

DC power socket J11

DIP switch SW1

DIP switch

Ferrite bead

LED

DPS2.5MM

SWM-6X-SMD

SW2

D5 D6 D7

D8 D9

SWM-8X-SMD

FB8 FB9

FB12 FB13

FB14 FB15

FB10 FB16

0603

0805P

Connector

Connector

LED

Memory

Diode

Connector

SDRAM

Transistor

Transistor

Pad

Resistor

J17

J3

D1 D2

U5

Z1

J10

U2 U3

Q1

Q2 Q3

PD1

R54

Hi speed switching dual diode 200mA 70V

D BAV70

DC Power socket 2.5mm

Surface mount 6-way micro dip switch pitch1.27mm

Surface mount 8-way micro dip switch pitch1.27mm

Ferrite 2506033007Y0 SMD 400mA

LED SMD 2,0 x 1,25mm Superbright Green

IDC5X2MD

IDC10X2MD

0805P

SO16

IDC 5X2 MD POL; IDC header 10pin p2.54mm straight male polarized

IDC header 20pin p2.54mm straight male polarized

Led SMD 2,0 x 1,25mm Superbright red

M25P64; Numonix 64Mbit SPI Serial Flash Memory 3.3V

16pin SO

SOD123-C425 MMSZ5232BT1; Zener Diode 5.6V 0.5W

MLX-1.25MM-M MOLEX 1.25MM 2W M; Molex 1.25mm 2way male straight

FBGA84

SOT23

SOT23

MT47H64M16HR3; MICRON DDR2 128MB 1.8V FBGA84

NPN BC848; NPN transistor 30Vbc 5Vbe 100mA

NPN PDTD123Y; Digital transistor NPN Rb 2.2K Re 10K

500mA 250mW SOT23

PDX280H60SQ

0603

PADX2-80H60; Two square pad 80x80mils 60mils Hole

100mils pitch

R 0603 0 OHM; Resistor 0603 0 ohm

20/38 Doc ID 18124 Rev 1

UM1015 Board components

Table 8.

CPU board components (continued)

Component Designator

Connector J12 J13

Rectifier

Embedded microprocessor

D4

U1

Power distribution switch

U4

RS-232 driver and receiver

U12

SO8

Footprint

MIS-038

DPAK

SG-BGA-6004

SO16

Description

SAMTEC-MIS-038; SAMTEC MIS series 76pin 0.64mm pitch

SCR TS420-B_1; Schottky barrier rectifier 1A 60V SMD

SPEAR300; STmicroelectronics Spear330

ST2052; STm Current limited power distribution switches

ST3232C; STm RS-232 driver and receiver

Voltage regulator U9

Reset circuit U7

SOT223

SOT143-4

VFQFPN-48

ST LD1117S25TR; STm low drop fixed positive voltage regulator 2.5V 800mA

STM811; STm Reset generator and power monitor 3.3V

SOT143-4

ST PM6641; STm DDR2/3 Voltage Regulator 48pin VFQFPN Voltage regulator U10

Connector

J5 J6 J7

J8 J9

Connector

Connector

Overvoltage protection

ESD protection circuit

J22

J20 J21

U16

U13 U14

U15

2X1-2.54-MD

2X2-2.54-MD

3X1-2.54-MD

TDFN-10

SOT23-6L

STRIP-2X1-2.54-MD; Strip vertical male 2X1 2.54mm

STRIP-2X2-2.54-MD; Strip vertical male 2X2 2.54mm

STRIP-3X1; Strip vertical male 3X1 2.54mm

ST STBP120C; STm overvoltage protection device Vout max

5.5V

ST USBLC6-2SC6; STm USB 2.0 ESD protections

Switch

Connector

Connector

Ferrite bead

P1

J2

J1

FB1 FB2

SW-PB-SMD6x6.6

SW-PB-SMD; Mechanical key switch SMD 6x6.6mm h4.3mm

USB-A-RA-DB

USB-B-RA-1

0805

USB A-TYPE RA DOUBLE; USB double A-type connector right angle

USB B-TYPE RA SH; USB B-type connector right angle

WURTH 742792023; Ferrite Wurth 742792023 SMD 500mA

Doc ID 18124 Rev 1 21/38

Schematics

6 Schematics

Figure 5.

Schematic interconnections

02 - DDR Interface

02 - DDR Interface.SchDoc

VREF

03 - USB Interface

03 - USB Interface.SchDoc

22/38

ADC_VREFP

ADC_VREFN

04 - Misc

04 - Misc.SchDoc

ADC_VREFP

ADC_VREFN

AIN[0..7]

INRESET nRESET

05 - Power

05 - Power.SchDoc

VREF nRESET

VREF

PL_GPIO[0..97]

PL_CLK[1..4]

06 - PL_GPIO

06 - PL_GPIO.SchDoc

PL_GPIO[0..97]

PL_CLK[1..4]

AIN[0..7]

07 - OutCon

07 - OutCon.SchDoc

AIN[0..7]

ADC_VREFN

ADC_VREFP

PL_GPIO[0..97]

PL_CLK[1..4] nRESET

INRESET

INRESET

In

Figure 5 :

●

●

●

●

●

●

02: DDR2 intrface and power

03: USB interface

04: Miscellaneous (serial flash, RTC power, boot options, JTAG, reset)

05: Power supply

06: PL_GPIO interface, extended boot options

07: Daughterboard and UART connectors

Doc ID 18124 Rev 1

UM1015

Figure 6.

DDR interface schematic

8 7 6 5 4 3 2 1

ADDR[0..13]

DATA[0..15]

4

3

2

1

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

T17

T16

U17

U16

U14

U13

T13

R13

P11

R11

T11

U11

T12

R12

P12

P13 nRAS nCAS nWE nCS0 nCS1

DQS0 nDQS0

DQS1 nDQS1

ODT0

ODT1

DQM0

DQM1

U8

T8

T7

P9

R9

U10

T10

U15

T15

T3

T4

R10

R14

U12

T14

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15 nRAS nCAS nWE

BA0

BA1

BA2 nCS0 nCS1

DQS0 nDQS0

CLK_EN

CLK nCLK

VREF

DQS1 nDQS1

ODT0

ODT1

COMP_2V5_REXT

GATE_OPEN0

GATE_OPEN1

DQM0

DQM1 COMP_2V5_GND

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

R5

P5

P6

R6

T6

U6

R7

T2

T1

U1

U2

U3

U4

U5

T5

P7

P8

R8

U7

T9

U9

P10

P4

R4

BA0

BA1

BA2

CLK_EN

CLK nCLK

VREF

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

1

2

Place close to pins

1

2

DATA5

DATA4

DATA0

DATA3

DATA2

DATA1

DATA7

DATA6

DATA12

DATA9

DATA14

DATA11

DATA8

DATA13

DATA10

DATA15

DQM0

DQM1

DQS0 nDQS0

DQS1 nDQS1 nCS1 nWE nRAS nCAS

L8

K3

K7

L7

CLK_EN

CLK nCLK

K2

J8

K8

ODT1 K9

F3

B3

F7

E8

B7

A8

C8

C2

D7

D3

D1

D9

B1

B9

G8

G2

H7

H3

H1

H9

F1

F9

LDM

UDM

LDQS nLDQS

UDQS nUDQS nCS nWE nRAS nCAS

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

CKE

CLK nCLK

ODT

R3

R7

E2

A2

RFU1

RFU2

NC1

NC2

J7

P9

N1

J3

E3

A3

VSSDL

VSS1

VSS2

VSS3

VSS4

VSS5

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

BA2

BA1

BA0

P8

P3

M2

P7

R2

R8

M8

M3

M7

N2

N8

N3

N7

P2

L1

L3

L2

VREF

VDD1V8_1

VDD1V8_2

VDD1V8_3

VDD1V8_4

VDD1V8_5

VDDL1V8

VDDQ1V8_1

VDDQ1V8_2

VDDQ1V8_3

VDDQ1V8_4

VDDQ1V8_5

VDDQ1V8_6

VDDQ1V8_7

VDDQ1V8_8

VDDQ1V8_9

VDDQ1V8_10

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

A9

C1

C3

C7

C9

E9

G1

G3

G7

G9

A7

B2

B8

D2

D8

E7

F2

F8

H2

H8

J2

A1

E1

M9

R1

J9

J1

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

BA2

BA1

BA0

VREF

1.8V_SP

Place close to pin

Place close to pin

1.8V_SP

1.8V_SP

1.8V_SP

CLK

R2

100 Ohm

R4

100 Ohm

1.8V_SP

R3

100 Ohm nCLK

R5

100 Ohm

1.8V_SP

R8

470 Ohm

VREF

R9

470 Ohm

VREF Place close to DDR2 Chip

1.8V_SP

C61

10 uF X5R 10V

Place close to LAST DDR2 Chip

8 7 6 5 4

DATA4

DATA5

DATA3

DATA0

DATA1

DATA2

DATA6

DATA7

DATA9

DATA12

DATA11

DATA14

DATA13

DATA8

DATA15

DATA10

DQM0

DQM1

DQS0 nDQS0

DQS1 nDQS1 nCS0 nWE nRAS nCAS

L8

K3

K7

L7

CLK_EN

CLK nCLK

K2

J8

K8

ODT0 K9

F3

B3

F7

E8

B7

A8

C8

C2

D7

D3

D1

D9

B1

B9

G8

G2

H7

H3

H1

H9

F1

F9

LDM

UDM

LDQS nLDQS

UDQS nUDQS nCS nWE nRAS nCAS

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

CKE

CLK nCLK

ODT

R3

R7

E2

A2

RFU1

RFU2

NC1

NC2

J7

P9

N1

J3

E3

A3

VSSDL

VSS1

VSS2

VSS3

VSS4

VSS5

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

BA2

BA1

BA0

P8

P3

M2

P7

R2

R8

M8

M3

M7

N2

N8

N3

N7

P2

L1

L3

L2

VREF

VDD1V8_1

VDD1V8_2

VDD1V8_3

VDD1V8_4

VDD1V8_5

VDDL1V8

VDDQ1V8_1

VDDQ1V8_2

VDDQ1V8_3

VDDQ1V8_4

VDDQ1V8_5

VDDQ1V8_6

VDDQ1V8_7

VDDQ1V8_8

VDDQ1V8_9

VDDQ1V8_10

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

A9

C1

C3

C7

C9

E9

G1

G3

G7

G9

A7

B2

B8

D2

D8

E7

F2

F8

H2

H8

J2

A1

E1

M9

R1

J9

J1

4

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

BA2

BA1

BA0

VREF

1.8V_SP

Place close to pin

C4

0.1 uF X5R 10V 3

Place close to pin

1.8V_SP

1.8V_SP

2

1.8V_SP

1.8V_SP

C62

10 uF X5R 10V

Place close to DDR2 Chip

3 2

Spear300

DDR2 interface

20 Oct 2009

CPU Board

2

2.3

8

1

1

Figure 7.

USB interface schematic

Vb

D--

D+

Gn

Shield1

Shield2

1

2

3

4

5

6

USB_DEV_5V

USB_DEV_INF_DM

USB_DEV_INF_DP

H0-Vbus

H0-DM

H0-DP

H0-GND

H1-Vbus

H1-DM

H1-DP

H1-GND

Shield1

Shield2

Shield3

Shield4

7

8

5

6

3

4

1

2

9

10

11

12

HOST0_5V

HOST0_INF_DM

HOST0_INF_DP

HOST1_5V

HOST1_INF_DM

HOST1_INF_DP

USB Interface

USB_DEV_VBUS G3

USB_DEV_DM

USB_DEV_DP

M2

M1

HOST0_VBUS

HOST0_DM

HOST0_DP

J3

K2

K1

HOST0_OVERCUR H4

USB_DEV_VBUS

USB_DEV_DM

USB_DEV_DP

USB_DEV_VDD3V3

USB_HOST0_VDD3V3

USB_HOST1_VDD3V3

USB_DEV_VDD2V5

USB_HOST0_VDD2V5

USB_HOST1_VDD2V5

USB_HOST0_VBUS

N3

K4

J1

N1

L2

K3

B_DEV_VDD3V3

B_HOST_VDD3V3

B_DEV_VDD2V5

B_HOST_VDD2V5

USB_HOST0_DM

USB_HOST0_DP

USB_HOST0_OVERCUR

USB_DVDD1V2

M3 USB_VDD1V2

HOST1_VBUS H3

HOST1_DM

HOST1_DP

H2

H1

HOST1_OVERCUR J4

K5

L4

USB_HOST1_VBUS

USB_HOST1_DM

USB_HOST1_DP

USB_HOST1_OVERCUR

USB_COMMON_VSSac

USB_DVSS

USB_TXR_TUNE

USB_ANALOG_TEST

USB_DEV_VSSa

USB_HOST0_VSSa

USB_HOST1_VSSa

L3

L5

N2

L1

J2

1.2V_SP

USB Power

3.3V_SP

2.5V_SP

UM1015

Figure 8.

USB power and optional part schematic

USB Power

Schematics

HOST0_VBUS

HOST1_VBUS

5V

2

3

4

IN OUT1

OUT2

EN1

EN2 nOC1 nOC2

ST2052

GND

8

5

7

6

1

5V

HOST0_5V

HOST1_5V

HOST0_OVERCUR

HOST1_OVERCUR

R30

1 Kohm

D1

Led red

R31

1 Kohm

D2

Led red

3.3V

Optional part

USB_DEV_DM

USB_DEV_DP

USB_DEV_5V

1

3

I/O1

I/O2

I/O1

I/O2

6

4

5

Vbus GND

2

USB_DEV_INF_DM

USB_DEV_INF_DP

HOST0_DM

HOST0_DP

HOST0_5V

1

3

I/O1

I/O2

I/O1

I/O2

6

4

5

Vbus GND

2

HOST0_INF_DM

HOST0_INF_DP

HOST1_DM

HOST1_DP

HOST1_5V

1

3

I/O1

I/O2

I/O1

I/O2

6

4

5

Vbus GND

2

HOST1_INF_DM

HOST1_INF_DP

Place C102 close to U13.5 VBus

Place C101 close to U14.5 VBus

Place C100 close to U15.5 Vbus

Doc ID 18124 Rev 1 25/38

Figure 9.

Miscellaneous interfaces schematic

8 7 6 5 4 3 2 1

4

3

2

3.3V

JTAG Connector

3.3V

INRESET

1

3

2

4

10

12

14

16

6

8

2

4

18

20

9

11

13

15

5

7

1

3

17

19

3.3V

nTRST

TDI

TMS

TCK

TDO

POWERGOOD

2.5V_SP

R45

0 Ohm

3.3V

SMI_DATAOUT

SMI_CLK

SMI_nWE0

SMI_nCS0

15

16

9

7

1

3.3V

5

6

3

4

2

CS0

SDI

CLK

SDO

WR-VPP

CSEL

HOLD

NC

NC

NC

NC

Vcc

NC

NC

NC

NC

GND

8

11

12

13

14

10

SMI_DATAIN nTRST

TDI

TMS

TCK

TDO

TEST0

TEST1

TEST2

TEST3

TEST4

BOOT_SEL

DDR_EN

L16

L14

L13

L17

L15

K16

K15

K14

K13

J15

J14

J13

E2 nTRST

TDI

TMS

TCK

TDO

TEST0

TEST1

TEST2

TEST3

TEST4

BOOT_SEL

DDR2_EN

RTC_XI

SMI_CLK

SMI_DATAIN

SMI_DATAOUT

SMI_CS0

SMI_CS1

N17

M13

M14

M15

M16

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

ADC_VREFP

ADC_VREFN

ADC_AVDD2V5

ADC_AGND

N16

N15

P17

P16

P15

R17

R16

R15

P14

N14

N13

N12

Y1

32.768Khz

E1

RTC_XO

P1

MCLK_XI RTC_VDD1V5

F1

Y2

24Mhz

P2

M17

G4

F4

MCLK_VDD2V5

MCLK_VDD1V2

MCLK_XO DITH_PLL_AVDD_2V5

DITH_PLL_VDD2V5

MRESET

DIGITAL_REXT

DITH_PLL_AVSS_2V5

DITH_PLL_VSS2V5

MCLK_GND_SUB

DIGITAL_GND_BCOMP

MCLK_GND

RTC_GND

G1

N4

R3

P3

F2

R2

R1

G2

M4

SMI_CLK

SMI_DATAIN

SMI_nCS0

SMI_nCS1

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

ADC_VREFP

ADC_VREFN

ADC_AVDD2V5

ADC_AGND

RTC_VDD1V5

MCLK_VDD2V5

MCLK_VDD1V2

DITH_PLL_VDD2V5

AIN[0..7]

R43 0 Ohm

R44 0 Ohm

AIN[0..7]

ADC_VREFP

ADC_VREFN

FERRITE

FB14

2.5V_SP

1.2V_SP

2.5V_SP

2.5V_SP

3.3V

R34

1 Kohm SMI_DATAOUT

SMI_CLK

SMI_nWE1

SMI_nCS1

15

16

9

7

1

3.3V

5

6

3

4

2

CS1

SDI

CLK

SDO

WR-VPP

CSEL

HOLD

NC

NC

NC

NC

Vcc

NC

NC

NC

NC

GND

8

11

12

13

14

10

1

2

SMI_DATAIN

INRESET 3.3V

4

3

1

VCC(3.3V)

RST IN

GND nRST

2 nRESET nRESET

3.3V

Reset management

R77

NC

1

4

3

2

3.3V

3

GND

+3V

+3V

1

2 3.3V

1

8

TEST0

TEST1

TEST2

TEST3

TEST4

BOOT_SEL

7

Boot Sel

3

4

1

2

5

6

7

8

9

10

11

12

6 5 4

J10

MOLEX 1.25MM 2W M

3

RTC Power

2

Spear300

Miscellaneus interface

20 Oct 2009

CPU Board

4

2.3

8

1

1

Figure 10.

Power supply schematic

8 7

4

C94 Place close to IN(4,5) PIN

DC POWER

2.1mm

1

2

3

4

5

10

1

8

9

11

12

IN

IN

EN

OUT

OUT

FLT

NC

NC

NC

PAD1

PAD2

GND

6

7

3

2

1

2

6

R28

4.7 Kohm

5

+

C83

5V

4

5V

AVCC

C35

0.1 uF X5R 10V

3 2

5V

3

1

Vin

Vout (tab)

GND

Vout

2

4

2.5V

C64

10 uF X5R 10V

1

4

3

2

1

1.2V

AVCC AVCC

3.3V

8

C89

2.2 nF X7R

AVCC

AVCC

7

AVCC

1.8V

1.8V

From farthest 1.8V point

5V

44

46

2

4

39

LDOIN

DSCG

SET_SWF

CSNS

SET_PH1

9

10

11

12

13

24

37

VIN1_1S8

VIN2_1S8

VFB_1S8

COMP_1S8

SS_1S8

PG_1S8

EN_1S8

VOUT_1S8

VSW1_1S8

VSW2 _1S8

VSW1_1S05

VSW2_1S05

3

7

8

19

20

VSW1_1S5

VSW2_1S5

31

32

Place near pin 33

From farthest point

48

41

AVCC

21

22

16

15

14

23

34

33

28

27

26

25

35

47

36

VIN1_1S05

VIN2_1S05

VFB_1S05

COMP_1S05

SS_1S05

PG_1S05

EN_1S05

VIN_1S5

VFB_1S5

COMP_1S5

SS_1S5

PG_1S5

EN_1S5

VTTFB

EN_VTT

VCC

AVCC

VTT

VTTREF

43

45

SGND1_1S8

SGND2_1S8

SGND1_1S05

SGND2_1S05

SGND2_1S5

SGND1_1S5

AGND1

AGND2

AGND3

1

38

40

VTTGND

42

THERMAL

49

5

6

17

18

30

29

VTT

C38

0.1 uF X5R 10V

6

AVCC

5 4

Place near PM6641

1.8V

+

C84

47 uF Tan 10V

1.2V

+ C85

47 uF Tan 10V

3.3V

+ C86

47 uF Tan 10V

Place faraway

R51 0 ohm,NC VREF

R52 0 ohm,NC

VREF

3

2

5V

D7

GREEN

3.3V

2.5V

1.2V

5V 1.8V

5V

D8

GREEN

D9

GREEN

R6

100 Ohm

1

3

2

D5

GREEN

R7

100 Ohm

1

3

2

D6

GREEN

1

3 2

Spear300

Power supply

20 Oct 2009

CPU Board

5

2.3

8

1

Figure 11.

Customization interface schematic

8 7 6

4

3

2

PL_GPIO[0..97]

PL_GPIO0

PL_GPIO1

PL_GPIO2

PL_GPIO3

PL_GPIO4

PL_GPIO5

PL_GPIO6

PL_GPIO7

PL_GPIO8

PL_GPIO9

PL_GPIO10

PL_GPIO11

PL_GPIO12

PL_GPIO13

PL_GPIO14

PL_GPIO15

PL_GPIO16

PL_GPIO17

PL_GPIO18

PL_GPIO19

PL_GPIO20

PL_GPIO21

PL_GPIO22

PL_GPIO23

PL_GPIO24

PL_GPIO25

PL_GPIO26

PL_GPIO27

PL_GPIO28

PL_GPIO29

PL_GPIO30

PL_GPIO31

PL_GPIO32

PL_GPIO33

PL_GPIO34

PL_GPIO35

PL_GPIO36

PL_GPIO37

PL_GPIO38

PL_GPIO39

PL_GPIO40

PL_GPIO41

PL_GPIO42

PL_GPIO43

PL_GPIO44

PL_GPIO45

PL_GPIO46

PL_GPIO47

PL_GPIO48

PL_CLK1

PL_CLK2

PL_CLK3

PL_CLK4

B5

C6

A5

B6

A6

A7

B7

C7

E6

C4

D5

A3

B4

C5

D6

A4

C2

B2

C3

E5

D4

A1

A2

B3

F3

E3

E4

D1

C1

D2

B1

D3

B9

C9

D9

E9

A10

B10

A11

C10

B11

D7

E7

E8

D8

C8

B8

A8

A9

PL_GPIO0

PL_GPIO1

PL_GPIO2

PL_GPIO3

PL_GPIO4

PL_GPIO5

PL_GPIO6

PL_GPIO7

PL_GPIO8

PL_GPIO9

PL_GPIO10

PL_GPIO11

PL_GPIO12

PL_GPIO13

PL_GPIO14

PL_GPIO15

PL_GPIO16

PL_GPIO17

PL_GPIO18

PL_GPIO19

PL_GPIO20

PL_GPIO21

PL_GPIO22

PL_GPIO23

PL_GPIO24

PL_GPIO25

PL_GPIO26

PL_GPIO27

PL_GPIO28

PL_GPIO29

PL_GPIO30

PL_GPIO31

PL_GPIO32

PL_GPIO33

PL_GPIO34

PL_GPIO35

PL_GPIO36

PL_GPIO37

PL_GPIO38

PL_GPIO39

PL_GPIO40

PL_GPIO41

PL_GPIO42

PL_GPIO43

PL_GPIO44

PL_GPIO45

PL_GPIO46

PL_GPIO47

PL_GPIO48

K17

J17

J16

H17

PL_CLK1

PL_CLK2

PL_CLK3

PL_CLK4

D16

F14

D15

B17

F13

E14

C16

A17

B16

D14

C15

A16

B15

C14

E13

B14

D13

C13

A15

E12

A14

B13

D12

E11

C12

A13

E10

D11

B12

D10

A12

C11

H16

H15

H14

H13

G17

G16

G15

G14

F17

F16

G13

E17

F15

D17

E16

E15

C17

PL_GPIO97

PL_GPIO96

PL_GPIO95

PL_GPIO94

PL_GPIO93

PL_GPIO92

PL_GPIO91

PL_GPIO90

PL_GPIO89

PL_GPIO88

PL_GPIO87

PL_GPIO86

PL_GPIO85

PL_GPIO84

PL_GPIO83

PL_GPIO82

PL_GPIO81

PL_GPIO80

PL_GPIO79

PL_GPIO78

PL_GPIO77

PL_GPIO76

PL_GPIO75

PL_GPIO74

PL_GPIO73

PL_GPIO72

PL_GPIO71

PL_GPIO70

PL_GPIO69

PL_GPIO68

PL_GPIO67

PL_GPIO66

PL_GPIO65

PL_GPIO64

PL_GPIO63

PL_GPIO62

PL_GPIO61

PL_GPIO60

PL_GPIO59

PL_GPIO58

PL_GPIO57

PL_GPIO56

PL_GPIO55

PL_GPIO54

PL_GPIO53

PL_GPIO52

PL_GPIO51

PL_GPIO50

PL_GPIO49

PL_GPIO97

PL_GPIO96

PL_GPIO95

PL_GPIO94

PL_GPIO93

PL_GPIO92

PL_GPIO91

PL_GPIO90

PL_GPIO89

PL_GPIO88

PL_GPIO87

PL_GPIO86

PL_GPIO85

PL_GPIO84

PL_GPIO83

PL_GPIO82

PL_GPIO81

PL_GPIO80

PL_GPIO79

PL_GPIO78

PL_GPIO77

PL_GPIO76

PL_GPIO75

PL_GPIO74

PL_GPIO73

PL_GPIO72

PL_GPIO71

PL_GPIO70

PL_GPIO69

PL_GPIO68

PL_GPIO67

PL_GPIO66

PL_GPIO65

PL_GPIO64

PL_GPIO63

PL_GPIO62

PL_GPIO61

PL_GPIO60

PL_GPIO59

PL_GPIO58

PL_GPIO57

PL_GPIO56

PL_GPIO55

PL_GPIO54

PL_GPIO53

PL_GPIO52

PL_GPIO51

PL_GPIO50

PL_GPIO49

PL_CLK[1..4]

PL_CLK[1..4]

3.3V

5 4 3 2

3.3V

3.3V_SP

+

C94

47 uF Tan 10V

2.5V

2.5V_SP

+

C95

47 uF Tan 10V

1.8V

1.8V_SP

+ C96

47 uF Tan 10V

1.2V

Place Cap near jumpers

1.2V_SP

+ C97

47 uF Tan 10V

1.8V_SP

1.2V_SP

G6

G7

G8

G9

G10

G11

H6

H7

H8

H9

H10

H11

M5

N5

N6

N7

N8

N9

N10

N11

F8

F9

G12

H5

H12

J5

L11

M6

M7

M11

VDD1V2_1

VDD1V2_2

VDD1V2_3

VDD1V2_4

VDD1V2_5

VDD1V2_6

VDD1V2_7

VDD1V2_8

VDD1V2_9

VDD1V2_10

DDR_VDD1V8_1

DDR_VDD1V8_2

DDR_VDD1V8_3

DDR_VDD1V8_4

DDR_VDD1V8_5

DDR_VDD1V8_6

DDR_VDD1V8_7

DDR_VDD1V8_8

VDD3V3_1

VDD3V3_2

VDD3V3_3

VDD3V3_4

VDD3V3_5

VDD3V3_6

VDD3V3_7

VDD3V3_8

VDD3V3_9

VDD3V3_10

VDD3V3_11

GND_1

GND_2

GND_3

GND_4

GND_5

GND_6

GND_7

GND_8

GND_9

GND_10

GND_11

GND_12

GND_32

GND_31

GND_30

GND_29

GND_28

GND_27

GND_26

GND_25

GND_24

GND_23

GND_22

GND_21

GND_20

GND_19

GND_18

GND_17

GND_16

GND_15

GND_14

GND_13

F5

F6

F7

F10

F11

F12

G5

J12

K12

L12

M12

M10

M9

M8

L10

L9

L8

L7

L6

K11

K10

K9

K8

J9

J8

J7

J6

K7

K6

J11

J10

3.3V_SP

1

3.3V_SP

1.8V_SP

1.2V_SP

1

7

8

5

6

3

4

1

2

9

10

11

12

13

14

15

16

PL_GPIO51

PL_GPIO52

PL_GPIO53

PL_GPIO54

B0-3 booting options

1

1

GND

FMEC3.2

FM2

GND

1

GND

1

GND

8 7 6 5 4 3 2

Spear300

Customization interface

20 Oct 2009

CPU Board

6

2.3

8

1

4

3

2

1

Figure 12.

Daughterboard interface schematic

8 7 6 5

4

3

2

1

PL_GPIO[0..97]

PL_GPIO[0..97]

PL_GPIO2

PL_GPIO3

PL_CLK[1..4]

PL_CLK[1..4]

PL_GPIO77

PL_GPIO78

PL_GPIO81

PL_GPIO80

PL_GPIO84

PL_GPIO83

PL_GPIO86

PL_GPIO91

PL_GPIO90

PL_GPIO96

PL_GPIO88

PL_GPIO89

PL_GPIO92

PL_GPIO93

PL_GPIO97

PL_CLK4

PL_CLK3

PL_CLK2

PL_CLK1

PL_GPIO47

PL_GPIO49

PL_GPIO56

PL_GPIO58

PL_GPIO64

PL_GPIO45

PL_GPIO48

PL_GPIO50

PL_GPIO55

PL_GPIO59

PL_GPIO60

PL_GPIO65

PL_GPIO62

PL_GPIO68

PL_GPIO52

PL_GPIO53

PL_GPIO51

PL_GPIO54

PL_GPIO74

1.8V

GPIO2

GPIO3

RS232_TXD

RS232_RXD

PL_GPIO42

PL_GPIO43

PL_GPIO34

PL_GPIO33

PL_GPIO16

PL_GPIO24

PL_GPIO20

PL_GPIO23

PL_GPIO18

PL_GPIO11

PL_GPIO19

17

19

21

23

25

27

29

31

9

11

13

15

5

7

1

3

33

35

37

PL_GPIO15

PL_GPIO14

PL_GPIO36

PL_GPIO41

PL_GPIO35

PL_GPIO31

PL_GPIO32

PL_GPIO25

PL_GPIO22

PL_GPIO21

PL_GPIO17

PL_GPIO12

PL_GPIO10

PL_GPIO7

PL_GPIO1

PL_GPIO0

63

65

67

69

55

57

59

61

47

49

51

53

39

41

43

45

71

73

75

77

78

79

80

81

25

27

29

31

17

19

21

23

9

11

13

15

5

7

1

3

33

35

37

63

65

67

69

55

57

59

61

39

41

43

45

47

49

51

53

71

73

75

GB1

GB2

GB3

GB4

GB5

GB6

GB7

GB8

GB9

GB10

18

20

22

24

26

28

30

32

10

12

14

16

6

8

2

4

34

36

38

26

28

30

32

18

20

22

24

10

12

14

16

6

8

2

4

34

36

38

64

66

68

70

56

58

60

62

48

50

52

54

40

42

44

46

72

74

76

64

66

68

70

56

58

60

62

40

42

44

46

48

50

52

54

72

74

76

82

83

84

85

86

5V

PL_GPIO44

PL_GPIO39

PL_GPIO40

PL_GPIO38

PL_GPIO29

PL_GPIO37

PL_GPIO30

PL_GPIO28

PL_GPIO26

PL_GPIO27

PL_GPIO9

PL_GPIO13

PL_GPIO8

PL_GPIO6

PL_GPIO4

PL_GPIO5

TP-TH

TP-TH

TP5

TP-TH TP6

TP-TH

TP6

TP7

TP-TH TP8

2.5V

TP8

1.2V

3.3V

INRESET nRESET

INRESET nRESET

56

58

60

62

64

66

68

70

48

50

52

54

40

42

44

46

72

74

76

82

83

84

85

86

26

28

30

32

18

20

22

24

10

12

14

16

6

8

2

4

34

36

38

77

78

79

80

81

25

27

29

31

17

19

21

23

9

11

13

15

5

7

1

3

33

35

37

25

27

29

31

17

19

21

23

5

7

1

3

9

11

13

15

33

35

37

55

57

59

61

63

65

67

69

47

49

51

53

39

41

43

45

71

73

75

63

65

67

69

55

57

59

61

47

49

51

53

39

41

43

45

71

73

75

GB1

GB2

GB3

GB4

GB5

GB6

GB7

GB8

GB9

GB10

26

28

30

32

18

20

22

24

10

12

14

16

6

8

2

4

34

36

38

64

66

68

70

56

58

60

62

48

50

52

54

40

42

44

46

72

74

76

3.3V

PL_GPIO63

PL_GPIO46

PL_GPIO57

PL_GPIO61

PL_GPIO66

PL_GPIO69

PL_GPIO72

PL_GPIO73

PL_GPIO70

PL_GPIO67

PL_GPIO71

PL_GPIO75

PL_GPIO82

PL_GPIO76

PL_GPIO85

PL_GPIO87

PL_GPIO95

PL_GPIO79

PL_GPIO94

ADC_VREFN

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

ADC_VREFP

ADC_VREFN

ADC_VREFP

AIN[0..7]

AIN[0..7]

8 7 6 5

4

4

J20

STRIP-3X1

J21

STRIP-3X1

3

3

RS232_RXD

RS232_TXD

2

PL_GPIO2

GPIO2

PL_GPIO3

GPIO3

11

10

2

6

12

9

4

5

1

3 C1+

C1-

C2+

C2-

V+

V-

T1IN

T2IN

R1OUT

R2OUT

VCC

GND

16

15

T1OUT

T2OUT

R1IN

R2IN

14

7

13

8

3.3V

1

3

1

3

2

4

2

4

5

7

1

3

9

6

8

2

4

10

1

2

Spear300

DaughterBoard interface

20 Oct 2009

CPU Board

7

2.3

8

1

4

3

2

1

Figure 13.

Schematic revision history

4

3

2

1

4

Revision Descriptions

Revision History

1.0

1.1

Initial release

C78, C79 : connected to GND instead of 2.5V

Add signal nRESET to daughter-board connectors (pinout to be defined)

Add three optionals USBLC6 (U13, U14, U15) for ESD protection

Add optional STBP120B (U16) for overvoltage protection

Add two Spare Resistor for RTC Power (R76, R77)

Add four 3.2mm mechanical holes

Add two GND pins on 32.768Khz oscillator for PCB footprint

Changed daughter-board connectors (Tyco MICTOR instead Samtec QTH)

Made some cosmetic changes

1.2

1.3

1.4

1.5

1.5.1

1.6

3

Date

20 May 2009

28 May 2009

Changed daughter-board connectors ( Samtec MIS instead Tyco MICTOR) 10 June 2009

Add four 47uF capacitor (C94, C95, C96, C97) 25 June 2009

Remove UART Solution 1 at Page 7

Remove JTAG alternativ Optional part at Page 4

Add a 10uF capacitor at input pot of STBP120, C98

Add two net: RS232_RXD and RS232_TXD at Page 7 U12-pin 14 and U12-pin13, these two net are connected to Pin40 and Pin42 of J13, Remove Test Point TP3 and TP4

Change footprint of D4(TS420-B), from DO-214AC to DPAK

Add C99 0.1uF,0402 capacitor to Spear300 VREF pin

Add R78 0ohm resistor to Pin17 of J3 JTAG Port, and another pad be connected to GND

Add R79 0ohm resistor to Pin19 of J3 JTAG Port, and another pad be connected to GND

Add GND to C94, C95,C96,C97

FB8 is only connected to PIN 6 of J1 at Page3

Add a FB16, FB16 is connected to PIN 5 of J1 at Page3

FB9 is connected to PIN 9 and PIN 11 of J2 at Page3

FB10 is connected to PIN 10 and PIN 12 of J2 at Page3

Swap U2 and U3 data signals for better pcb routing at Page2

Swap Socket J12 and J13 signals and add four 1.8V power pins to J12 at Page7

R11~R21 pull up to 3.3V (change from 3.3V_SP)at Page4

D3 Pin.A1 connect to 3.3V (change from 3.3V_SP)at Page4

Change all "Motherboard" to "CPU Board"

Apdate Fiducial (REF*) symbol.

03 July 2009

03 July 2009

10 July 2009

17 July 2009

1.7

1.8

1.9

Pull down U10.4 CSNS to AGND

Connect U10.39 SET_PH1 to AGND

Change U13.5 net to USB_DEV_5V, Add C102 to Vbus pin

Change U14.5 net to HOST0_5V, Add C101 to Vbus pin

Change U15.5 net to HOST1_5V, Add C100 to Vbus pin

Modify USB ESD circuit design, insert ESD IC into USB signals: DM and DP, include USB DEV and Two USB Host

Pull up R61 to 1.2V

Change RS232-TXD net to J17.5 pin

Change RS232-RXD net to J17.3 pin

Change R72,R73,R74 value to 1K ohm

Change R41 value to 680 ohm

Change R75 value to 330 ohm

21 July 2009

23 July 2009

10 Sep 2009

4 3

NOTE:

2

Revision Descriptions

Revision History

2.0

Change R49 Value to 56K ohm

2.1

2.2

Date

1

23 Sep 2009

Add TP30 for DQS1 test; Add J22 for serial cable jumper ; Use NC for no pop components

16 Oct 2009

Change R8 and R9 to "470 ohm" (remove NC), and R51 and R52 to "0 ohm,NC"

20 Oct 2009

2.3

Made some cosmetic changes 20 Oct 2009

2

4

3

2

Spear300

Release note

20 Oct 2009

1

CPU Board

8

2.3

8

1

UM1015

Figure 14.

SPEAr320 CPU evaluation board layout (top view)

Power (J11) Reset button (P1)

Board layout

Serial link (J17)

USB host (J2) USB device (J1)

Figure 15.

SPEAr320 CPU evaluation board layout (bottom view)

Doc ID 18124 Rev 1 31/38

Revision history UM1015

8.1 Hardware revision history

Revision 2.0 SPEAr320 CPU evaluation boards are documented in revision 1 of the

EVALSPEAr320CPU user manual.

Earlier board revisions are documented in UM0842, the EVALSPEAr320PLC user manual.

Table 9.

Date

22-Oct-2010

Document revision history

Revision

1 Initial release.

Changes

32/38 Doc ID 18124 Rev 1

UM1015

Appendix A License agreements

License agreements

DEMO PRODUCT LICENSE AGREEMENT

By using this Demonstration Product, You are agreeing to be bound by the terms and conditions of this agreement.

Do not use this Demonstration Product until You have read and agreed to the following terms and conditions. The use of the Demonstration Product implies automatically the acceptance of the following terms and conditions.

LICENSE. STMicroelectronics ("ST") grants You the right to use the enclosed demonstration board offering limited features only to evaluate and test ST products, including any incorporated and/or accompanying demo software, components and documentation identified with the order code "EVALSPEAr320CPU" (collectively, the "Demo Product") solely only for your evaluation and testing purposes. The Demo Product shall not be, in any case, directly or indirectly assembled as a part in any production of Yours as it is solely developed to serve demonstration purposes and has no direct function and is not a finished product. Certain demo software included with the Demo Product may be covered under a separate accompanying end user license agreement, in which case the terms and conditions of such end user license agreement shall apply to that demonstration software.

DEMO PRODUCT STATUS. The Demo Product is offering limited features allowing You only to evaluate and test the ST products. You are not authorized to use the Demo Product in any production system, and may not be offered for sale or lease, or sold, leased or otherwise distributed. If the Demo Product is incorporated in a demonstration system, the demonstration system may be used by You solely for your evaluation and testing purposes. Such demonstration system may not be offered for sale or lease or sold, leased or otherwise distributed and must be accompanied by a conspicuous notice as follows: "This device is not, and may not be, offered for sale or lease, or sold or leased or otherwise distributed".

OWNERSHIP AND COPYRIGHT. Title to the Demo Product, demo software, related documentation and all copies thereof remain with ST and/or its licensors. You may not remove the copyrights notices from the Demo Product. You may make one

(1) copy of the software for back-up or archival purposes provided that You reproduce and apply to such copy any copyright or other proprietary rights notices included on or embedded in the demonstration software. You agree to prevent any unauthorized copying of the Demo Product, demonstration software and related documentation.

RESTRICTIONS. You may not sell, assign, sublicense, lease, rent or otherwise distribute the Demo Product for commercial purposes (unless you are an authorized ST distributor provided that all the other clauses of this DEMO PRODUCT LICENSE

AGREEMENT shall apply entirely), in whole or in part, or use Demo Product in production system. Except as provided in this Agreement or in the Demo Product's documentation, You may not reproduce the demonstration software or related documentation, or modify, reverse engineer, de-compile or disassemble the demonstration software, in whole or in part.

You warrant to ST that the Demo Product will be used and managed solely and exclusively in a laboratory by skilled professional employees of Yours with proven expertise in the use and management of such products and that the

Demo Product shall be used and managed according to the terms and conditions set forth in the related documentation provided with the Demo Product.

According to European Semiconductor Industry Association (ESIA) letter, "ESIA Response on WEEE Review (May

2008) of the Directive 2002/96/EC on Waste Electrical and Electronic Equipment (WEEE)"; Semiconductor products and evaluation & demonstration boards are not in the scope of the Directive 2002/96/EC of the European Parliament and of the Council on waste electrical and electronic equipment (WEEE). Consequently aforementioned products do not have to be registered nor are they subject to the subsequent obligations.

NO WARRANTY. The Demo Product is provided "as is" and "with all faults" without warranty of any kind expressed or implied. ST and its licensors expressly disclaim all warranties, expressed, implied or otherwise, including without limitation, warranties of merchantability, fitness for a particular purpose and non-infringement of intellectual property rights. ST does not warrant that the use in whole or in part of the Demo Product will be interrupted or error free, will meet your requirements, or will operate with the combination of hardware and software selected by You. You are responsible for determining whether the Demo Product will be suitable for your intended use or application or will achieve your intended results.

ST shall not have any liability in case of damages, losses, claims or actions anyhow caused from combination of the Demo

Product with another product, board, software or device.

ST has not authorized anyone to make any representation or warranty for the Demo Product, and any technical, applications or design information or advice, quality characterization, reliability data or other services provided by ST shall not constitute any representation or warranty by ST or alter this disclaimer or warranty, and in no additional obligations or liabilities shall arise from ST's providing such information or services. ST does not assume or authorize any other person to assume for it any other liability in connection with its Demo Products.

All other warranties, conditions or other terms implied by law are excluded to the fullest extent permitted by law.

LIMITATION OF LIABILITIES. In no event ST or its licensors shall be liable to You or any third party for any indirect, special, consequential, incidental, punitive damages or other damages (including but not limited to, the cost of labour, requalification, delay, loss of profits, loss of revenues, loss of data, costs of procurement of substitute goods or services or the like) whether based on contract, tort, or any other legal theory, relating to or in connection with the Demo Product, the documentation or this Agreement, even if ST has been advised of the possibility of such damages. In no event shall ST's

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TERMINATION. ST may terminate this license at any time if You are in breach of any of its terms and conditions. Upon termination, You will immediately destroy or return all copies of the demo software and documentation to ST.

APPLICABLE LAW AND JURISDICTION. In case of dispute and in the absence of an amicable settlement, the only competent jurisdiction shall be the Courts of Geneva, Switzerland. The applicable law shall be the law of Switzerland. The

UN Convention on contracts for the International Sales of Goods shall not apply to these General Terms and Conditions of

Sale.

SEVERABILITY. If any provision of this agreement is or becomes, at any time or for any reason, unenforceable or invalid, no other provision of this agreement shall be affected thereby, and the remaining provisions of this agreement shall continue with the same force and effect as if such unenforceable or invalid provisions had not been inserted in this Agreement.

WAIVER. The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.

RELATIONSHIP OF THE PARTIES. Nothing in this Agreement shall create, or be deemed to create, a partnership or the relationship of principal and agent or employer and employee between the Parties. Neither Party has the authority or power to bind, to contract in the name of or to create a liability for the other in any way or for any purpose.

RECYCLING. The Demo Product is not to be disposed as an urban waste. At the end of its life cycle, differentiated waste collection must be followed, as stated in the directive 2002/96/EC.

In all the countries belonging to the European Union (EU Dir. 2002/96/EC) and those following differentiated recycling, the

Demo Product is subject to differentiated recycling at the end of its life cycle, therefore:

It is forbidden to dispose the Demo Product as an undifferentiated waste or with other domestic wastes. Consult the local authorities for more information on the proper disposal channels.

It is mandatory to sort the demo product and deliver it to the appropriate collection centers, or, when possible, return the demo product to the seller.

An incorrect Demo Product disposal may cause damage to the environment and is punished by the law.

10-Nov-2008

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SOFTWARE LICENSE AGREEMENT

This Software License Agreement ("Agreement") is displayed for You to read prior to downloading and using the

Licensed Software. If you choose not to agree with these provisions, do not download or install the enclosed

Licensed Software and the related documentation and design tools. By using the Licensed Software, You are agreeing to be bound by the terms and conditions of this Agreement. Do not use the Licensed Software until You have read and agreed to the following terms and conditions. The use of the Licensed Software implies automatically the acceptance of the following terms and conditions.

DEFINITIONS

Licensed Software: means the enclosed demonstration software and all the related documentation and design tools licensed in the form of object and/or source code as the case maybe.

Product: means a product or a system that includes or incorporates solely and exclusively an executable version of the

Licensed Software and provided further that such Licensed

Software executes solely and exclusively on ST products.

LICENSE

STMicroelectronics ("ST") grants You a non-exclusive, worldwide, non-transferable (whether by assignment, law, sublicense or otherwise), revocable, royalty-free limited license to:

(i) make copies, prepare derivatives works, display internally and use internally the source code version of the Licensed

Software for the sole and exclusive purpose of developing executable versions of such Licensed Software only for use with the Product;

(ii) make copies, prepare derivatives works, display internally and use internally object code versions of the Licensed

Software for the sole purpose of designing, developing and manufacturing the Products;

(iii) make, use, sell, offer to sell, import or otherwise distribute Products.

OWNERSHIP AND COPYRIGHT

Title to the Licensed Software, related documentation and all copies thereof remain with ST and/or its licensors. You may not remove the copyrights notices from the Licensed Software.

You may make one (1) copy of the Licensed Software for back-up or archival purposes provided that You reproduce and apply to such copy any copyright or other proprietary rights notices included on or embedded in the Licensed Software. You agree to prevent any unauthorized copying of the Licensed Software and related documentation.

RESTRICTIONS

Unless otherwise explicitly stated in this Agreement, You may not sell, assign, sublicense, lease, rent or otherwise distribute the Licensed for commercial purposes, in whole or in part purposes (unless you are an authorized ST distributor provided that all the other clauses of this DEMO PRODUCT LICENSE AGREEMENT shall apply entirely).

You acknowledge and agree that any use, adaptation translation or transcription of the

Licensed Software or any portion or derivative thereof, for use with processors manufactured by or for an entity other than

ST is a material breach of this Agreement and requires a separate license from ST. No source code and/or object code relating to and/or based upon Licensed Software is to be made available by You to any third party for whatever reason.

You acknowledge and agrees that the protection of the source code of the Licensed Software warrants the imposition of security precautions and You agree to implement reasonable security measures to protect ST's proprietary rights in the source code of the Licensed Software. You shall not under any circumstances copy, duplicate or otherwise reproduce the source code of the Licensed Software in any manner, except as reasonably necessary to exercise Your rights hereunder and make one back-up copy. You are granted the right to make one archival or backup copy of the source code of the

Licensed Software, which copy shall be marked as an archival copy and as the confidential information of ST. Access to the source code of the Licensed Software shall be restricted to only those of Your employees with a need-to-know for the purpose of this Agreement.

You will not under any circumstances permit the source code of the Licensed Software in any form or medium (including, but not limited to, hard copy or computer print-out) to be removed from your official premises as you have informed us. The source code of the Licensed Software must remain inside your official premises, as you have informed us. You will lock the source code of the Licensed Software and all copies thereof in a secured storage inside your official premises at all times when the source code of the Licensed Software is not being used as permitted under this Agreement.

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You will inform all Your employees who are given access to the source code of the Licensed Software of the foregoing requirements, and You will take all reasonable precautions to ensure and monitor their compliance with such requirements.

You agree to promptly notify ST in the event of a violation of any of the foregoing, and to cooperate with ST to take any remedial action appropriate to address the violation. You shall keep accurate records with respect to its use of the source code of the Licensed Software. In the event ST demonstrates to You a reasonable belief that the source code of the

Licensed Software has been used or distributed in violation of this Agreement, ST may by written notification request certification as to whether such unauthorized use or distribution has occurred. You shall reasonably cooperate and assist

ST in its determination of whether there has been unauthorized use or distribution of the source code of the Licensed

Software and will take appropriate steps to remedy any unauthorized use or distribution.

You agree that ST shall have the right (where ST reasonably suspects that the terms and conditions of this Agreement with reference to Restriction clause have not been complied with) upon reasonable notice to enter Your official premises in order to verify your compliance with this Restriction clause.

NO WARRANTY

The Licensed Software is provided "as is" and "with all faults" without warranty of any kind expressed or implied. ST and its licensors expressly disclaim all warranties, expressed, implied or otherwise, including without limitation, warranties of merchantability, fitness for a particular purpose and non-infringement of intellectual property rights. ST does not warrant that the use in whole or in part of the Licensed Software will be interrupted or error free, will meet your requirements, or will operate with the combination of hardware and software selected by You.

You are responsible for determining whether the Licensed Software will be suitable for your intended use or application or will achieve your intended results. ST has not authorized anyone to make any representation or warranty for the Licensed

Software, and any technical, applications or design information or advice, quality characterization, reliability data or other services provided by ST shall not constitute any representation or warranty by ST or alter this disclaimer or warranty, and in no additional obligations or liabilities shall arise from ST's providing such information or services. ST does not assume or authorize any other person to assume for it any other liability in connection with its Licensed Software.

Nothing contained in this Agreement will be construed as:

(i) a warranty or representation by ST to maintain production of any ST device or other hardware or software with which the

Licensed Software may be used or to otherwise maintain or support the Licensed Software in any manner; and

(ii) a commitment from ST and/or its licensors to bring or prosecute actions or suits against third parties for infringement of any of the rights licensed hereby, or conferring any rights to bring or prosecute actions or suits against third parties for infringement. However, ST has the right to terminate this Agreement immediately upon receiving notice of any claim, suit or proceeding that alleges that the Licensed Software or your use or distribution of the

Licensed

Software infringes any third party intellectual property rights.

All other warranties, conditions or other terms implied by law are excluded to the fullest extent permitted by law.

LIMITATION OF LIABILITIES

In no event ST or its licensors shall be liable to You or any third party for any indirect, special, consequential, incidental, punitive damages or other damages (including but not limited to, the cost of labour, re-qualification, delay, loss of profits, loss of revenues, loss of data, costs of procurement of substitute goods or services or the like) whether based on contract, tort, or any other legal theory, relating to or in connection with the Licensed Software, the documentation or this Agreement, even if ST has been advised of the possibility of such damages.

In no event shall ST's liability to You or any third party under this Agreement, including any claim with respect of any third party intellectual property rights, for any cause of action exceed

100 US$. This section does not apply to the extent prohibited by law. For the purposes of this section, any liability of ST shall be treated in the aggregate.

TERMINATION

ST may terminate this license at any time if You are in breach of any of its terms and conditions. Upon termination, You will immediately destroy or return all copies of the software and documentation to ST.

APPLICABLE LAW AND JURISDICTION

In case of dispute and in the absence of an amicable settlement, the only competent jurisdiction shall be the Courts of

Geneva, Switzerland. The applicable law shall be the law of Switzerland.

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SEVERABILITY

If any provision of this agreement is or becomes, at any time or for any reason, unenforceable or invalid, no other provision of this agreement shall be affected thereby, and the remaining provisions of this agreement shall continue with the same force and effect as if such unenforceable or invalid provisions had not been inserted in this Agreement.

WAIVER

The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.

RELATIONSHIP OF THE PARTIES

Nothing in this Agreement shall create, or be deemed to create, a partnership or the relationship of principal and agent or employer and employee between the Parties. Neither Party has the authority or power to bind, to contract in the name of or to create a liability for the other in any way or for any purpose.

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UM1015

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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