PN7120

PN7120

Full NFC Forum-compliant controller with integrated firmware and NCI interface

Rev. 2 — 15 June 2015

312420

Preliminary data sheet

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1. Introduction

This document describes the functionality and electrical specification of the NFC

Controller PN7120.

Additional documents describing the product functionality further are available for design-in support. Refer to the references listed in this document to get access to the full for full documentation provided by NXP.

PN7120 is a full NFC controller solution with integrated firmware and NCI interface designed for contactless communication at 13.56 MHz.

PN7120 is the ideal solution for rapidly integrating NFC technology in any application, especially those running O/S environment like Linux and Android, reducing Bill of Material

(BOM) size and cost, thanks to:

•

full NFC forum compliancy (see Ref. 11 ) with small form factor antenna

•

embedded NFC firmware providing all NFC protocols as pre-integrated feature

•

direct connection to the main host or microcontroller, by I

2

C-bus physical and NCI protocol

•

ultra-low power consumption in polling loop mode

•

Highly efficient integrated power management unit (PMU) allowing direct supply from a battery

PN7120 embeds a new generation RF contactless front-end supporting various transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693,

ISO/IEC 18000-3, MIFARE and FeliCa specifications. It embeds an ARM Cortex-M0 microcontroller core loaded with the integrated firmware supporting the NCI 1.0 host communication.

The contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load modulation communication enabling the support of small antenna form factor

Supported transmission modes are listed in

Figure 1 . For contactless card functionality,

the PN7120 can act autonomously if previously configured by the host in such a manner.

NXP Semiconductors

PN7120

Full NFC Forum-compliant controller with integrated firmware

PN7120 integrated firmware provides an easy integration and validation cycle as all the

NFC real-time constraints, protocols and device discovery (polling loop) are being taken care internally. In few NCI commands, host SW can configure the PN7120 to notify for card or peer detection and start communicating with them.

NFC FORUM

NFC-IP MODES

READER

(PCD - VCD)

CARD

(PICC)

READER FOR NFC FORUM

TAGS 1 TO 4

P2P ACTIVE

106 TO 424 kbps

INITIATOR AND TARGET

P2P PASSIVE

106 TO 424 kbps

INITIATOR AND TARGET

ISO/IEC 14443 A

ISO/IEC 14443 B

ISO/IEC 15693

MIFARE 1K / 4K

MIFARE DESFire

Sony FeliCa

(1)

ISO/IEC 14443 A

ISO/IEC 14443 B

aaa-015868

(1) According to ISO/IEC 18092 (Ecma 340) standard.

Fig 1.

PN7120 transmission modes

3. Features and benefits

 ARM Cortex-M0 microcontroller core

 Highly integrated demodulator and decoder



Buffered output drivers to connect an antenna with minimum number of external components

 Integrated RF level detector

 Integrated Polling Loop for automatic device discovery

 RF protocols supported

 NFCIP-1, NFCIP-2 protocol (see

Ref. 7 and Ref. 10 )

 ISO/IEC 14443A, ISO/IEC 14443B PICC mode via host interface (see

Ref. 2 )

 ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital protocol T4T platform and ISO-DEP (see

Ref. 11

)

 FeliCa PCD mode

 MIFARE PCD encryption mechanism (MIFARE 1K/4K)

 NFC Forum tag 1 to 4 (MIFARE Ultralight, Jewel, Open FeliCa tag, DESFire) (see

Ref. 11

)

 ISO/IEC 15693/ICODE VCD mode (see

Ref. 8 )

 Supported host interfaces



NCI protocol interface according to NFC Forum standardization (see Ref. 1 )



I

2

C-bus High-speed mode (see

Ref. 3 )

 Integrated power management unit

 Direct connection to a battery (2.3 V to 5.5 V voltage supply range)

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 Support different Hard Power-Down/Standby states activated by firmware



Autonomous mode when host is shut down

 Automatic wake-up via RF field, internal timer and I

2

C-bus interface

 Integrated non-volatile memory to store data and executable code for customization

4. Applications

 All devices requiring NFC functionality especially those running in an Android or Linux environment

 TVs, set-top boxes, Blu-ray decoders, audio devices

 Home automation, gateways, wireless routers

 Home appliances



Wearables, remote controls, healthcare, fitness

 Printers, IP phones, gaming consoles, accessories

5. Quick reference data

Table 1.

Quick reference data

Symbol

V

BAT

V

DD

V

DD(PAD)

Parameter

battery supply voltage Card Emulation and Passive

Target; V

SS

= 0 V supply voltage

Reader, Active Initiator and

Active Target; V

SS

= 0 V internal supply voltage

V

DD(PAD)

Conditions

supply voltage supply voltage for host interface

I

I

BAT

O(VDDPAD) battery supply current output current on pin

V

DD(PAD)

1.8 V host supply;

V

SS

= 0 V

3.3 V host supply;

V

SS

= 0 V in Hard Power Down state;

V

BAT

= 3.6 V; T = 25 °C in Standby state;

V

BAT

= 3.6 V; T = 25 °C in Monitor state;

V

BAT

= 2.75 V; T = 25 °C in low-power polling loop;

V

BAT

= 3.6 V; T = 25 °C; loop time = 500 ms

PCD mode at typical 3 V total current which can be pulled on V outputs

DD(PAD)

referenced

[1]

[2]

[1]

[2]

[1]

[1]

[3]

-

-

-

-

-

-

Min Typ Max Unit

2.3

5.5

V

2.7

V

1.65 1.8

1.95 V

1.65 1.8

1.95 V

3.0

-

-

-

-

-

10

150 -

5.5

3.6

12

20

12

V

A

A

A

A

170 mA

15 mA

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Table 1.

Quick reference data

…continued

Symbol Parameter Conditions

I th(Ilim)

P

T tot amb current limit threshold current current limiter on V

DD(TX)

pin;

V

DD(TX)

= 3.1 V total power dissipation Reader; I

VDD(TX)

V

BAT

= 5.5 V

= 100 mA; ambient temperature JEDEC PCB-0.5

[3]

[4]

-


180 mA

-

30 +25

0.5

+85

W

C

[1] V

SS

represents V

SS

, V

SS1

, V

SS2

, V

SS3

, V

SS4

, V

SS(PAD)

and V

SS(TX)

.

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account).

[3] The antenna shall be tuned not to exceed the maximum of I

VBAT

.

[4] This is the threshold of a built-in protection done to limit the current out of V

DD(TX)

in case of any issue at

I antenna pins to avoid burning the device. It is not allowed in operational mode to have I

VDD(TX)

VBAT

maximum value is exceeded.

such that

7. Marking

Table 2.

Ordering information

Type number Package

Name

PN7120A0EV/C1xxxx

Description

VFBGA49 plastic very thin fine-pitch ball grid array package; 49 balls

Version

SOT1320-1

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Fig 2.

PN7120 package marking (top view)

aaa-007526


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Table 3.

Marking code

Line number

Line 1

Marking code

product version identification

Line 2

Line 3 diffusion batch sequence number manufacturing code including:

•

diffusion center code:

– N: TSMC

– s: Global Foundry

•

assembly center code:

– S: APK

– X: ASEN

•

RoHS compliancy indicator:

– D: Dark Green; fully compliant RoHS and no halogen and antimony

•

manufacturing year and week, 3 digits:

– Y: year

– WW: week code

•

product life cycle status code:

– X: means not qualified product

– nothing means released product

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CLESS

INTERFACE UNIT

SENSOR

DEMOD

DRIVER

ADC

TxCtrl

PLL

VMID

BG

POWER

MANAGEMENT UNIT

3 V

BATTERY

MONITOR

TX-LDO

1.8 V

DSLDO

CLESS UART

RX CODEC

SIGNAL

PROCESSING

TX CODEC

HOST INTERFACE

I

2

C-BUS

ARM

CORTEX M0

AHB to APB

MISCELLANEOUS

TIMERS

CRC

COPROCESSOR

RANDOM

NUMBER

GENERATOR

CLOCK MGT UNIT

OSC

380 kHz

OSC

20 MHz

FRACN

PLL

QUARTZ

OSCILLATOR

MEMORY

CONTROL

DATA

MEMORY

SRAM

EEPROM

CODE

MEMORY

ROM

EEPROM

aaa-015869

Fig 3.

PN7120 block diagram

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9.1 Pinning

E

D

C

B

A

G

F ball A1 index area

Fig 4.

PN7120 pinning (bottom view)

1 2 3 4 5 6 7

aaa-007528

PN7120


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i.c.

i.c.

I2CSCL

I2CADR0 i.c.

i.c.

i.c.

V

SS1 i.c.

I2CSDA

V

SS(PAD)

XTAL2

V

SS n.c.

V

DD

V

BAT

IRQ

Table 4.

PN7120 pin description

Symbol

i.c.

CLK_REQ

XTAL1 i.c.

i.c.

Pin Type

[1]

A1 -

A2

A3

A4

A5

A6

A7 -

B1 I

B2 I

B3 -

B4 -

B5 -

I

-

-

-

O

-

-

-

-

-

Refer

-

-

V

DD(PAD)

V

DD

-

V

DD(PAD)

V

DD(PAD)

B6

B7

C1

C2

C3

C4

C5

C6

C7

D1

-

-

G

I/O

G

O

G

P

P

O

n/a

V

DD(PAD) n/a

V

DD n/a

n/a n/a

V

DD(PAD)


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Description

internally connected; leave open clock request pin

PLL clock input. Oscillator input internally connected; leave open internally connected; must be connected to ground internally connected; leave open internally connected; leave open

I

2

C-bus serial clock input

I

2

C-bus address bit 0 input internally connected; leave open internally connected; leave open internally connected; must be connected to ground ground internally connected; leave open

I

2

C-bus serial data pad ground oscillator output ground not connected

LDO output supply voltage battery supply voltage interrupt request output


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Table 4.

PN7120 pin description

…continued

Symbol Pin Type [1] Refer

BOOST_CTRL

V

DD(PAD)

V

SS2 i.c.

V

SS3 i.c.

VEN

V

SS(DC_DC) n.c.

n.c.

n.c.

n.c.

V

DD(TX) i.c.

i.c.

V

SS4 i.c.

RXN

RXP

V

DD(MID)

V

BAT2

V

BAT1

TX1

V

SS(TX)

TX2

ANT2

ANT1

D2

D3

D4

D5

D6

D7

E1

E2

E3

E4

E5 -

E6 -

E7 P

F1

F2 -

F3 G

F4 -

F5 I

F6 I

F7 P

G1

G2

-

-

-

I

-

-

O

P

G

G

G

P

P

G3 O

G4 G

G5 O

G6 P

G7 P

-

-

-

-

-

-

-

-

-

V

DD(PAD) n/a n/a n/a

V

BAT n/a n/a n/a

V

DD

V

DD n/a n/a n/a

V

DD(TX) n/a

V

DD(TX) n/a n/a

Description

booster control, see Ref. 5

pad supply voltage ground internally connected; leave open ground internally connected; leave open reset pin. Set the device in Hard Power Down ground not connected not connected not connected not connected contactless transmitter output supply voltage for decoupling internally connected; leave open internally connected; leave open ground internally connected; leave open negative receiver input positive receiver input receiver reference input supply voltage battery supply voltage; must be connected to

V

BAT battery supply voltage; must be connected to

V

BAT antenna driver output contactless transmitter ground antenna driver output antenna connection for Listen mode antenna connection for Listen mode

[1] P = power supply; G = ground; I = input, O = output; I/O = input/output.

10. Functional description

PN7120


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PN7120 can be connected on a host controller through I

2

C-bus. The logical interface

towards the host baseband is NCI-compliant Ref. 1

with additional command set for

NXP-specific product features. This IC is fully user controllable by the firmware interface

described in Ref. 4

.

Moreover, PN7120 provides flexible and integrated power management unit in order to preserve energy supporting Power Off mode.

In the following chapters you will find also more details about PN7120 with references to very useful application note such as:



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PN7120


•

PN7120 User Manual (

Ref. 4 ):

User Manual describes the software interfaces (API) based on the NFC forum NCI standard. It does give full description of all the NXP NCI extensions coming in addition to NCI standard (

Ref. 1

).

•

PN7120 Hardware Design Guide (

Ref. 5 ):

Hardware Design Guide provides an overview on the different hardware design options offered by the IC and provides guidelines on how to select the most appropriate ones for a given implementation. In particular, this document highlights the different chip power states and how to operate them in order to minimize the average NFC-related power consumption so to enhance the battery lifetime.

•

PN7120 Antenna and Tuning Design Guide (

Ref. 6

):

Antenna and Tuning Design Guide provides some guidelines regarding the way to design an NFC antenna for the PN7120 chip.

It also explains how to determine the tuning/matching network to place between this antenna and the PN7120.

Standalone antenna performances evaluation and final RF system validation (PN7120

+ tuning/matching network + NFC antenna within its final environment) are also covered by this document.

•

PN7120 Low-Power Mode Configuration (

Ref. 9 ):

Low-Power Mode Configuration documentation provides guidance on how PN7120 can be configured in order to reduce current consumption by using Low-power polling mode.

BATTERY/PMU

HOST

CONTROLLER host interface control

NFCC

ANTENNA

MATCHING

aaa-016739

Fig 5.

PN7120 connection

10.1 System modes

10.1.1 System power modes

PN7120 is designed in order to enable the different power modes from the system.

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2 power modes are specified: Full power mode and Power Off mode.

Table 5.

System power modes description

System power mode

Full power mode

Power Off mode

Description

the main supply (V

BAT

) as well as the host interface supply (V available, all use cases can be executed the system is kept Hard Power Down (HPD)

DD(PAD)

) is

Full power mode

[V

BAT

= On && V

DD(PAD)

= On

VEN = On]

[V

BAT

= Off || VEN = Off]

Power Off mode

[VEN = Off]

aaa-015871

Fig 6.

System power mode diagram

Table 6 summarizes the system power mode of the PN7120 depending on the status of

the external supplies available in the system:

Table 6.

System power modes configuration

V

BAT

Off

VEN

X

Power mode

Power Off mode

On

On

Off

On

Power Off mode

Full power mode

Depending on power modes, some application states are limited:

Table 7.

System power modes description

System power mode

Power Off mode

Full power mode

Allowed communication modes

no communication mode available

Reader/Writer, Card Emulation, P2P modes

10.1.2 PN7120 power states

Next to system power modes defined by the status of the power supplies, the power states include the logical status of the system thus extend the power modes.

4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active.

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Table 8.

PN7120 power states

Power state name Description

Monitor The PN7120 is supplied by V

BAT

which voltage is below its programmable critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The system power mode is Power Off mode.

Hard Power Down The PN7120 is supplied by V

BAT

which voltage is above its programmable critical level when Monitor state is enabled and PN7120 is kept in Hard

Power Down (VEN voltage is kept low by host or SW programming) to have the minimum power consumption. The system power mode is in Power Off.

Standby The PN7120 is supplied by V

BAT

which voltage is above its programmable critical level when the Monitor state is enabled, VEN voltage is high (by host or SW programming) and minimum part of PN7120 is kept supplied to enable configured wake-up sources which allow to switch to Active state; RF field,

Host interface. The system power mode is Full power mode.

Active The PN7120 is supplied by V

BAT

which voltage is above its programmable critical level when Monitor state is enabled, VEN voltage is high (by host or

SW programming) and the PN7120 internal blocks are supplied. 3 functional modes are defined: Idle, Target and Initiator. The system power mode is Full power mode.

At application level, the PN7120 will continuously switch between different states to

optimize the current consumption (polling loop mode). Refer to Table 1 for targeted

current consumption in here described states.

The PN7120 is designed to allow the host controller to have full control over its functional states, thus of the power consumption of the PN7120 based NFC solution and possibility to restrict parts of the PN7120 functionality.

10.1.2.1 Monitor state

In Monitor state, the PN7120 will exit it only if the battery voltage recovers over the critical level. Battery voltage monitor thresholds show hysteresis behavior as defined in

Table 26 .

10.1.2.2 Hard Power Down (HPD) state

The Hard Power Down state is entered when V

DD(PAD)

and V

BAT

are high by setting VEN voltage < 0.4 V. As these signals are under host control, the PN7120 has no influence on entering or exiting this state.

10.1.2.3 Standby state

Active state is PN7120’s default state after boot sequence in order to allow a quick configuration of PN7120. It is recommended to change the default state to Standby state after first boot in order to save power. PN7120 can switch to Standby state autonomously

(if configured by host).

In this state PN7120 most blocks including CPU are no more supplied. Number of wake-up sources exist to put PN7120 into Active state:

•

I

2

C-bus interface wake-up event

•

Antenna RF level detector

•

Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled)

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If wake-up event occurs, PN7120 will switch to Active state. Any further operation depends on software configuration and/or wake-up source.

10.1.2.4 Active state

Within the Active state, the system is acting as an NFC device. The device can be in 3 different functional modes: Idle, Poller and Target.

Table 9.

Functional modes in active state

Functional modes Description

Idle the PN7120 is active and allows host interface communication. The RF interface is not activated.

Listener the PN7120 is active and is configured for listening to external device.

Poller the PN7120 is active and is configured in Poller mode. It polls external device

Poller mode:

In this mode, PN7120 is acting as Reader/Writer or NFC Initiator, searching for or communicating with passive tags or NFC target. Once RF communication has ended, PN7120 will switch to active battery mode (that is, switch off RF transmitter) to save energy. Poller mode shall be used with 2.7 V < V voltage > 1.1 V. Poller mode shall not be used with V

operational range (see Table 1 ).

BAT

< 5.5 V and VEN

BAT

< 2.7 V. V

DD(PAD)

is within its

Listener mode:

In this mode, PN7120 is acting as a card or as an NFC Target. Listener mode shall be used with 2.3 V < V

BAT

< 5.5 V and VEN voltage > 1.1 V.

10.1.2.5 Polling loop

The polling loop will sequentially set PN7120 in different power states (Active or Standby).

All RF technologies supported by PN7120 can be independently enabled within this polling loop.

There are 2 main phases in the polling loop:

•

Listening phase. The PN7120 can be in Standby power state or Listener mode

•

Polling phase. The PN7120 is in Poller mode

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Listening phase

PN7120


Emulation

Pause

Type A

Type B

Type F

@424

Type F

@212

ISO15693

Polling phase

aaa-016741

Fig 7.

Polling loop: all phases enabled

Listening phase uses Standby power state (when no RF field) and PN7120 goes to

Listener mode when RF field is detected. When in Polling phase, PN7120 goes to Poller mode.

To further decrease the power consumption when running the polling loop, PN7120 features a low-power RF polling. When PN7120 is in Polling phase instead of sending regularly RF command PN7120 senses with a short RF field duration if there is any NFC

Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms

(configurable duration, see

Ref. 4 ) listening phase duration, the average power

consumption is around 150

A.

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Listening phase

PN7120


Emulation

Pause

Polling phase

aaa-016743

Fig 8.

Polling loop: low-power RF polling

Detailed description of polling loop configuration options is given in

Ref. 4 .

10.2 Microcontroller

PN7120 is controlled via an embedded ARM Cortex-M0 microcontroller core.

PN7120 features integrated in firmware are referenced in

Ref. 4

10.3 Host interfaces

PN7120 provides the support of an I

2

C-bus Slave Interface, up to 3.4 MBaud.

The host interface is waken-up on I

2

C-bus address.

To enable and ensure data flow control between PN7120 and host controller, additionally a dedicated interrupt line IRQ is provided which Active state is programmable. See

Ref. 4

for more information.

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10.3.1 I

2

C-bus interface

The I

2

C-bus interface implements a slave I

2

C-bus interface with integrated shift register, shift timing generation and slave address recognition.

I

2

C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode

(3.4 MHz SCL) are supported.

The mains hardware characteristics of the I

2

C-bus module are:

•

Support slave I

2

C-bus

•

Standard, Fast and High-speed modes supported

•

Wake-up of PN7120 on its address only

•

Serial clock synchronization can be used by PN7120 as a handshake mechanism to suspend and resume serial transfer (clock stretching)

The I

2

C-bus interface module meets the I

2

C-bus specification

Ref. 3 except General call,

10-bit addressing and Fast mode Plus (Fm+).

10.3.1.1 I

2

C-bus configuration

The I

2

C-bus interface shares four pins with I

2

C-bus interface also supported by PN7120.

When I

2

C-bus is configured in EEPROM settings, functionality of interface pins changes to one described in

Table 10 .

Table 10.

Functionality for I

2

C-bus interface

Pin name

I2CADR0

I2CSDA

I2CSCL

Functionality

I

2

C-bus address 0

I

2

C-bus data line

I

2

C-bus clock line

PN7120 supports 7-bit addressing mode. Selection of the I

2

C-bus address is done by

2-pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, 0, I2CADR0, R/W.

Table 11.

I

2

C-bus interface addressing

I2CADR0 I

2

C-bus address

(R/W = 0, write)

0 0x50

1 0x52

I

2

C-bus address

(R/W = 1, read)

0x51

0x53

10.4 PN7120 clock concept

There are 4 different clock sources in PN7120:

•

27.12 MHz clock coming either/or from:

– Internal oscillator for 27.12 MHz crystal connection

– Integrated PLL unit which includes a 1 GHz VCO

•

13.56 MHz RF clock recovered from RF field

•

Low-power oscillator 20 MHz

•

Low-power oscillator 380 kHz

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10.4.1 27.12 MHz quartz oscillator

When enabled, the 27.12 MHz quartz oscillator applied to PN7120 is the time reference for the RF front end when PN7120 is behaving in Reader mode or NFCIP-1 initiator.

Therefore stability of the clock frequency is an important factor for reliable operation. It is

recommended to adopt the circuit shown in Figure 9

.

PN7120

XTAL1 XTAL2 c crystal

27.12 MHz c

aaa-015872

Fig 9.

27.12 MHz crystal oscillator connection

Table 12 describes the levels of accuracy and stability required on the crystal.

Table 12.

Crystal requirements

Symbol Parameter

f xtal

f xtal

ESR

C

L

P o(xtal) crystal frequency

Conditions

ISO/IEC and FCC compliancy crystal frequency accuracy full operating range all V

BAT

range;

T = 20 °C all temperature range;

V

BAT

= 3.6 V equivalent series resistance load capacitance crystal output power

[1]

[1]

[1]

-

-

-

Min

100

-

50

-

50

-

-

Typ

27.12 -

50

10 -

Max Unit

MHz

+100 ppm

+50

+50

100

 pF

100

W

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and

ISO/IEC 18092, then

 14 kHz apply.

ppm ppm

10.4.2 Integrated PLL to make use of external clock

When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock

13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz.

The 27.12 MHz of the PLL is used as the time reference for the RF front end when

PN7120 is behaving in Reader mode or NFC Initiator as well as in NFC Target when configured in Active communication mode.

The input clock on XTAL1 shall comply with the.following phase noise requirements for the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and

52 MHz:

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dBc/Hz

-20dBc/Hz

Input reference

noise floor

-140 dBc/Hz

PN7120


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Input reference noise corner

50 kHz

Hz

aaa-007232

Fig 10. Input reference phase noise characteristics

This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For

configuration of input frequency, refer to Ref. 8

. There are 6 pre programmed and validated frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and

52 MHz.

Table 13.

PLL input requirements

Coupling: single-ended, AC coupling;


f f clk i(ref)acc clock frequency reference input frequency accuracy

ISO/IEC and FCC compliancy full operating range; frequencies typical values:

13 MHz, 26 MHz and

52 MHz full operating range; frequencies typical values:

19.2 MHz, 24 MHz and

38.4 MHz input noise floor at 50 kHz

[1]

[1]

-

-

Min Typ Max

13 -

19.2 -

-

24 -

26 -

38.4 -

-

25

-

52 -

+25

50

+50

Unit

MHz

MHz

MHz

MHz

MHz

MHz ppm ppm

 n phase noise

140 -

-

Sinusoidal shape

V i(p-p) peak-to-peak input voltage

V i(clk) clock input voltage

Square shape

V i(clk) clock input voltage

0.2

0 -

1.8

1.8

0 1.8

 10

%

[1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and

ISO/IEC 18092, then

 400 ppm limits apply.

V

V

V dB/

Hz

For detailed description of clock request mechanisms, refer to Ref. 4

and

Ref. 5 .


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10.4.3 Low-power 20 MHz oscillator

Low-power 20 MHz oscillator is used as system clock of the system.

10.4.4 Low-power 380 kHz oscillator

A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up

PN7120 from Standby state. This allows implementation of low-power reader polling loop at application level. Moreover, this 380 kHz is used as the reference clock for write access to EEPROM memory.

10.5 Power concept

10.5.1 PMU functional description

The Power Management Unit of PN7120 generates internal supplies required by PN7120 out of V

BAT

input supply voltage:

•

V

DD

: internal supply voltage

•

V

DD(TX)

: output supply voltage for the RF transmitter

The Figure 11

describes the main blocks available in PMU:

V

BAT

V

DD

V

BAT1

and V

BAT2

DSLDO

BANDGAP

TXLDO

V

DD(TX)

NFCC

aaa-016748

Fig 11. PMU functional diagram

10.5.2 DSLDO: Dual Supply LDO

The input pin of the DSLDO is V

BAT

.

The Low drop-out regulator provides V

DD

required in PN7120.

10.5.3 TXLDO

This is the LDO which generates the transmitter voltage.

The value of V

DD(TX)

is configured at 3.1 V

 0.2 V.

V

DD(TX)

value is given according to the minimum targeted V

BAT

value for which Reader mode shall work.

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For V

BAT

above 3.1 V, V

DD(TX)

= 3.1 V:

V

BAT



3.1V



V

DD TX



= 3.1V

3.1V V

BAT



2.3V



V

DD TX



=

V

BAT

In Standby state, V

DD(TX)

is around 2.5 V with some ripples; it toggles between 2.35 V to

2.65 V with a period which depends on the capacitance and load on V

DD(TX)

.

Figure 12

shows V

DD(TX)

behavior for 3.1 V:

V

V

BAT

3.1 V

Fig 12. V

DD(TX)

offset disabled behavior

Figure 13

shows the case where the PN7120 is in Standby state:

V

V

BAT time

aaa-015875

2.65 V

2.5 V

2.35 V time

aaa-007538

Fig 13. V

DD(TX)

behavior when PN7120 is in Standby state

10.5.3.1 TXLDO limiter

The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in reader or initiator modes.

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The current limiter block compares an image of the TXLDO output current to a reference.

Once the reference is reached, the output current gets limited which is equivalent to a typical output current of 220 mA whatever V

BAT

= 2.7 V and 180 mA for V

BAT

= 3.1 V.

10.5.4 Battery voltage monitor

The PN7120 features low-power V

BAT battery from being discharged below critical levels. When V

V

BATcritical

voltage monitor which protects the host device principle schematic of the battery monitor.

BAT

voltage goes below

threshold, then the PN7120 goes in Monitor state. Refer to Figure 14 for

The battery voltage monitor is enabled via an EEPROM setting.

The V

BATcritical

threshold can be configured to 2.3 V or 2.75 V by an EEPROM setting.

At the first start-up, V

BAT

voltage monitor functionality is OFF and then enabled if properly configured in EEPROM. The PN7120 monitors battery voltage continuously.

V

BAT

V

DD

EEPROM REGISTERS enable threshold selection

VBAT

MONITOR

POWER

MANAGEMENT low-power

SYSTEM

MANAGEMENT power off

POWER SWITCHES

V

DD(CPU)

DIGITAL

(memories, cpu, etc,...)

aaa-015877

Fig 14. Battery voltage monitor principle

The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting.

This value has a typical hysteresis around 150 mV.

10.6 Reset concept

10.6.1 Resetting PN7120

To enter reset there are 2 ways:

•

Pulling VEN voltage low (Hard Power Down state)

•

if V

BAT

monitor is enabled: lowering V

VEN voltage is kept above 1.1 V)

BAT

below the monitor threshold (Monitor state, if

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Reset means resetting the embedded FW execution and the registers values to their default values. Part of these default values is defined from EEPROM data loaded values, others are hardware defined. See

Ref. 4 to know which ones are accessible to tune

PN7120 to the application environment.

To get out of reset:

•

Pulling VEN voltage high with V

BAT

above V

BAT

monitor threshold if enabled

Figure 15

shows reset done via VEN pin.

V

BAT

V

DD(PAD)

V

EN t w(VEN) t boot host communication possible

aaa-015878

Fig 15. Resetting PN7120 via VEN pin

See

Section 15.2.2

for the timings values.

10.6.2 Power-up sequences

There are 2 different supplies for PN7120. PN7120 allows these supplies to be set up independently, therefore different power-up sequences have to be considered.

10.6.2.1 V

BAT

is set up before V

DD(PAD)

This is at least the case when V

BAT

PN7120 V

BAT

pin is directly connected to the battery and when

is always supplied as soon the system is supplied.

As VEN pin is referred to V

BAT

pin, VEN voltage shall go high after V

BAT

has been set.

V

BAT

V

DD(PAD) t t(VDD(PAD)-VEN) t boot

V

EN

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Fig 16. V

BAT is set up before V

DD(PAD)


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PN7120


See

Section 15.2.3


10.6.2.2 V

DD(PAD)

and V

BAT

are set up in the same time

It is at least the case when V

BAT

V

DD(PAD)

.

pin is connected to a PMU/regulator which also supply

V

BAT t t(VBAT-VEN)

V

DD(PAD) t boot

V

EN host communication possible

aaa-015881

Fig 17. V

DD(PAD)

and V

BAT

are set up in the same time

See

Section 15.2.3


10.6.2.3 PN7120 has been enabled before V

DD(PAD) off

is set up or before V

DD(PAD)

has been cut

This can be the case when V

BAT

pin is directly connected to the battery and when V

DD(PAD) is generated from a PMU. When the battery voltage is too low, then the PMU might no more be able to generate V

DD(PAD) set up again.

. When the device gets charged again, then V

DD(PAD)

is

As the pins to select the interface are biased from V

DD(PAD)

, when V

DD(PAD)

disappears the pins might not be correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after V

DD(PAD)

is set up again.

V

BAT

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V

DD(PAD) t t(VDD(PAD)-VEN) t boot

V

EN t

W(VEN) host communication possible

aaa-015884

Fig 18. V

DD(PAD)

is set up or cut-off after PN7120 has been enabled

See

Section 15.2.3



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10.6.3 Power-down sequence

t

VBAT(L)

V

BAT t > 0 ms

(nice to have) t > 0 ms

V

EN

V

DD(PAD)

aaa-015886

Fig 19. PN7120 power-down sequence

10.7 Contactless Interface Unit

PN7120 supports various communication modes at different transfer speeds and modulation schemes. The following chapters give more detailed overview of selected communication modes.

Remark: all indicated modulation index and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.

10.7.1 Reader/Writer communication modes

Generally 5 Reader/Writer communication modes are supported:

•

PCD Reader/Writer for ISO/IEC 14443A/MIFARE

•

PCD Reader/Writer for Jewel/Topaz tags

•

PCD Reader/Writer for FeliCa cards

•

PCD Reader/Writer for ISO/IEC 14443B

•

VCD Reader/Writer for ISO/IEC 15693/ICODE

10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode

The ISO/IEC 14443A/MIFARE PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443A specification. This modulation scheme is as well used for communications with Jewel/Topaz cards.

Figure 20

describes the communication on a physical level, the communication table describes the physical parameters (the numbers take the antenna effect on modulation depth for higher data rates).

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PCD to PICC

100 % ASK at 106 kbit/s

> 25 % ASK at 212, 424 or 848 kbit/s

Modified Miller coded

NFCC PICC (Card)

PICC to PCD, subcarrier load modulation

Manchester coded at 106 kbit/s

BPSK coded at 212, 424 or 848 kbit/s ISO/IEC 14443A - MIFARE

PCD mode

ISO/IEC 14443A - MIFARE

Fig 20. ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram

aaa-016749

Table 14.

Overview for ISO/IEC 14443A/MIFARE Reader/Writer communication mode

Communication direction

ISO/IEC 14443A/

MIFARE/

Jewel/

Topaz

ISO/IEC 14443A higher transfer speeds

Transfer speed

Bit length

106 kbit/s

(128/13.56)

s

212 kbit/s

(64/13.56)

s

424 kbit/s

(32/13.56)

s

848 kbit/s

(16/13.56)

s

PN7120

 PICC

(data sent by PN7120 to a card) modulation on

PN7120 side bit coding

100 % ASK

Modified Miller

> 25 % ASK

Modified Miller

> 25 % ASK

Modified Miller

> 25 % ASK

Modified Miller

PICC

 PN7120

(data received by PN7120 from a card) modulation on

PICC side subcarrier frequency bit coding subcarrier load modulation

13.56 MHz/16

Manchester subcarrier load modulation

13.56 MHz/16

BPSK subcarrier load modulation

13.56 MHz/16


13.56 MHz/16

BPSK

The contactless coprocessor and the on-chip CPU of PN7120 handle the complete

ISO/IEC 14443A/MIFARE RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.

10.7.1.2 FeliCa PCD communication mode

The FeliCa communication mode is the general Reader/Writer to card communication scheme according to the FeliCa specification.

Figure 21

describes the communication on a physical level, the communication overview describes the physical parameters.

PCD to PICC,

8 - 12 % ASK at 212 or 424 kbits/s

Manchester coded


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ISO/IEC 18092 - FeliCa

PCD mode

PICC to PCD, load modulation

Manchester coded at 212 or 424 kbits/s

FeliCa card

aaa-016750

Fig 21. FeliCa Reader/Writer communication mode diagram


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Table 15.

Overview for FeliCa Reader/Writer communication mode


Transfer speed

Bit length

FeliCa

212 kbit/s

(64/13.56)

s

PN7120

 PICC


PN7120 side

8 %

 12 % ASK bit coding Manchester

PICC

 PN7120

(data received by PN7120 from a card) modulation on PICC side load modulation subcarrier frequency no subcarrier bit coding Manchester

FeliCa higher transfer speeds

424 kbit/s

(32/13.56)

s

8 %

 12 % ASK

Manchester load modulation no subcarrier

Manchester

The contactless coprocessor of PN7120 and the on-chip CPU handle the FeliCa protocol.

Nevertheless a dedicated external host has to handle the application layer communication.

10.7.1.3 ISO/IEC 14443B PCD communication mode

The ISO/IEC 14443B PCD communication mode is the general reader to card

communication scheme according to the ISO/IEC 14443B specification.

Figure 22

describes the communication on a physical level, the communication table describes the physical parameters.

PCD to PICC,

8 - 14 % ASK at 106, 212, 424 or 848 kbit/s

NRZ coded


PICC to PCD, subcarrier load modulation

BPSK coded at 106, 212, 424 or 848 kbit/s ISO/IEC 14443 Type B

PCD mode

ISO/IEC 14443 Type B

aaa-016751

Fig 22. ISO/IEC 14443B Reader/Writer communication mode diagram

Table 16.

Overview for ISO/IEC 14443B Reader/Writer communication mode


Transfer speed

Bit length

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

106 kbit/s

(128/13.56)

s

212 kbit/s

(64/13.56)

s

424 kbit/s

(32/13.56)

s

848 kbit/s

(16/13.56)

s

PN7120

 PICC


PN7120 side

8 %

 14 % ASK 8 %  14 % ASK 8 %  14 % ASK 8 %  14 % ASK bit coding NRZ NRZ NRZ NRZ

PICC

 PN7120

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Table 16.

Overview for ISO/IEC 14443B Reader/Writer communication mode

…continued


Transfer speed

Bit length

ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds

106 kbit/s

(128/13.56)

s

212 kbit/s

(64/13.56)

s

424 kbit/s

(32/13.56)

s

848 kbit/s

(16/13.56)

s

(data received by PN7120 from a card) modulation on

PICC side subcarrier frequency bit coding subcarrier load modulation

13.56 MHz/16


13.56 MHz/16


13.56 MHz/16


13.56 MHz/16

BPSK

The contactless coprocessor and the on-chip CPU of PN7120 handles the complete

ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.

10.7.1.4 ISO/IEC 15693 VCD communication mode

The ISO/IEC 15693 VCD Reader/Writer communication mode is the general reader to card communication scheme according to the ISO/IEC 15693 specification. PN7120 will communicate with VICC using only the higher data rates of the VICC (26.48 kbit/s with single subcarrier and 26.69 kbit/s with dual subcarrier).

PN7120 supports the commands as defined by the ETSI HCI (see

Ref. 1 ) and on top

offers the inventory of the tags (anticollision sequence) on its own.

VCD to VICC,

10 - 30 % or 100 % ASK at 1.65 or 26.48 kbit/s pulse position coded

NFCC Card

(VICC/TAG)

VICC to VCD, subcarrier load modulation

Manchester coded at 26.48 or 26.69 kbit/s ISO/IEC 15693

VCD mode

ISO/IEC 15693

aaa-016752

Fig 23. ISO/IEC 15693 VCD communication mode diagram

Figure 23

shows the communication schemes used.

2 communication schemes can be used from card to PN7120 and 2 communication schemes can be used from PN7120 to card.

Thus, 4 communication schemes are possible.

Table 17.

Overview for ISO/IEC 15693 VCD communication mode


PN7120

 VICC

(data sent by PN7120 to a tag) transfer speed bit length modulation on

PN7120 side bit coding

1.65 kbit/s

(8192/13.56) pulse position modulation 1 out of

256 mode

s

10 %

 30 % or 100 % ASK

26.48 kbit/s

(512/13.56)

s

10 %

 30 % or 100 % ASK pulse position modulation 1 out of

4 mode

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Table 17.

Overview for ISO/IEC 15693 VCD communication mode

…continued


VICC

 PN7120

(data received by PN7120 from a tag) transfer speed bit length modulation on VICC side

26.48 kbit/s

(512/13.56)

s subcarrier load modulation subcarrier frequency single subcarrier bit coding Manchester

26.69 kbit/s

(508/13.56)

s subcarrier load modulation dual subcarrier

Manchester

10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes

An NFCIP-1 communication takes place between 2 devices:

•

NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.

•

NFC Target: responds to NFC Initiator command either in a load modulation scheme in Passive communication mode or using a self-generated and self-modulated RF field for Active communication mode.

The NFCIP-1 communication differentiates between Active and Passive communication modes.

•

Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data

•

Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme. The NFC Initiator is active in terms of generating the RF field.

PN7120 supports the Active Target, Active Initiator, Passive Target and Passive Initiator communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard.

BATTERY BATTERY

NFCC NFCC

HOST HOST

NFC Initiator: Passive or Active Communication modes NFC Target: Passive or Active Communication modes

aaa-016755

Fig 24. NFCIP-1 communication mode

Nevertheless a dedicated external host has to handle the application layer communication.

10.7.2.1 ACTIVE communication mode

Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data.

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host

NFC Initiator

1. NFC Initiator starts the communication at selected transfer speed power to generate the field

NFCC

NFC Target host power for digital processing host

NFC Initiator

2. NFC Target answers at the same transfer speed

NFCC

NFC Target host power for digital processing power to generate the field

aaa-016756

Fig 25. Active communication mode

The following table gives an overview of the Active communication modes:

Table 18.

Overview for Active communication mode

Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1

Baud rate

Bit length

106 kbit/s

(128/13.56)

s

212 kbit/s

(64/13.56)

s

NFC Initiator to NFC Target

modulation bit coding

100 % ASK

Modified Miller

8 %

 30 % ASK

[1]

Manchester

NFC Target to NFC Initiator


100 % ASK

Miller

424 kbit/s

(32/13.56)

8 %

s

 30 % ASK

Manchester

[1]

8 %

 30 % ASK

[1]

8 %

 30 % ASK

[1]

Manchester Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see

Ref. 6 .

10.7.2.2 Passive communication mode

Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme.

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host

NFC Initiator

1. NFC Initiator starts the communication at selected transfer speed power to generate the field

NFCC

NFC Target host power for digital processing host

NFC Initiator

2. NFC Target answers using load modulation at the same transfer speed

NFCC

NFC Target host power to generate the field power for digital processing

aaa-016757

Fig 26. Passive communication mode

Table 19 gives an overview of the Passive communication modes:

Table 19.

Overview for Passive communication mode

Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1

Baud rate

Bit length

106 kbit/s

(128/13.56)

s

212 kbit/s

(64/13.56)

s

NFC Initiator to NFC Target


100 % ASK

Modified Miller

8 %

 30 % ASK

[1]

Manchester

NFC Target to NFC Initiator

modulation subcarrier frequency bit coding subcarrier load modulation

13.56 MHz/16


Manchester

424 kbit/s

(32/13.56)

s

8 %

 30 % ASK [1]


Manchester

[1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see

Ref. 6 .

10.7.2.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive communication modes are defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340.

10.7.2.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard.

However the datalink layer is according to the following policy:

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•

Transaction includes initialization, anticollision methods and data transfer. This sequence must not be interrupted by another transaction

•

PSL shall be used to change the speed between the target selection and the data transfer, but the speed should not be changed during a data transfer

10.7.3 Card communication modes

PN7120 can be addressed as a ISO/IEC 14443A or ISO/IEC 14443B cards. This means that PN7120 can generate an answer in a load modulation scheme according to the

ISO/IEC 14443A or ISO/IEC 14443B interface description.

Remark: PN7120 does not support a complete card protocol. This has to be handled by the host controller.

Table 20 and Table 21 describe the physical parameters.

10.7.3.1 ISO/IEC 14443A/MIFARE card communication mode

Table 20.

Overview for ISO/IEC 14443A/MIFARE card communication mode


Transfer speed

Bit length

ISO/IEC 14443A

106 kbit/s

(128/13.56)

s

ISO/IEC 14443A higher transfer speeds

212 kbit/s 424 kbit/s

(64/13.56)

s

(32/13.56)

s

PCD

 PN7120

(data received by PN7120 from a card) modulation on PCD side bit coding

100 % ASK

Modified Miller

> 25 % ASK

Modified Miller

> 25 % ASK

Modified Miller

PN7120

 PCD


PN7120 side subcarrier frequency bit coding subcarrier load modulation

13.56 MHz/16

Manchester subcarrier load modulation

13.56 MHz/16


13.56 MHz/16

BPSK

10.7.3.2 ISO/IEC 14443B card communication mode

Table 21.

Overview for ISO/IEC 14443B card communication mode


Transfer speed

Bit length

ISO/IEC 14443B

106 kbit/s

(128/13.56)

s

PCD

 PN7120

(data received by PN7120 from a Reader) modulation on PCD side

8 %

 14 % ASK bit coding NRZ

PN7120

 PCD

(data sent by PN7120 to a

Reader) modulation on

PN7120 side subcarrier frequency bit coding subcarrier load modulation

13.56 MHz/16

BPSK

ISO/IEC 14443B higher transfer speeds

212 kbit/s

(64/13.56)

s

424 kbit/s

(32/13.56)

s

8 %

 14 % ASK

NRZ subcarrier load modulation

13.56 MHz/16

BPSK

8 %

 14 % ASK

NRZ subcarrier load modulation

13.56 MHz/16

BPSK

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10.7.4 Frequency interoperability

When in communication, PN7120 is generating some RF frequencies. PN7120 is also sensitive to some RF signals as it is looking from data in the field.

In order to avoid interference with others RF communication, it is required to tune the

antenna and design the board according to Ref. 5

.

Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of

13.56 MHz

 7 kHz, FCC regulation does not allow this wide spread and limits the dispersion to

 50 ppm, which is in line with PN7120 capability.

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11. Application design-in information

4

Y2

CLOCK INTERFACE

3

CXTAL 1

10 pF

2

27.12 MHz

1

CXTAL 2

10 pF

HOST INTERFACE host controller I

2

C-bus host controller I

2

C-bus clock host controller I

2

C-bus data host controller external interrupt input (optional) host controller GPIO (output) - reset control

POWER INTERFACE controller IO power supply (1.8 V or 3.3 V) battery power (2.75 V up to 5.5 V)

Cpvdd

1 μF main ground (GND)

XTAL1

B5

A3

XTAL2

C3

I2CADR0

B2 n.c.

BOOST_CTRL

D2

I2CSCL

B1

I2CSDA

C1

IRQ

D1

VEN

E1 i.c.

A1

CLK_REQ n.c.

A2 n.c.

i.c.

B3

V

DD(PAD)

D3

V

BAT

C7

V

DD

C6

B4 A4 A5 E5 D5 E3 E4 F4 E6

PN7120

C5 B7 A7 A6

Ctvdd

1 μF

E7

G7

ANT1

RXP

F6

V

DD(TX)

TX1

G3

TX2

G5

RXN

F5

ANT2

G6

V

DD(MID)

F7 i.c.

D7 i.c.

F1

F2 i.c.

V

BAT1

G2

V

BAT2

G1

C2 B6 C4 D4 D6 F3 E2 G4

Cvbat

4.7 μF Cvdd

1 μF

VBAT

Cvbat2

100 nF

ANTENNA MATCHING/TUNING CIRCUIT

Cant1

Crxp

1 nF/16 V

Lemc1

560 nH

Crxn

Lemc2

560 nH

1 nF/16 V xxx(1) pF/50 V

Rrxp2 n.c.

Rrxp1

1 kΩ

Cemc1

180 pF/16 V

Cemc2

Cs1 xxx(1) pF/50 V

180 pF/16 V

Cs2

Rrxn1

1 kΩ xxx(1) pF/50 V

Cant2

Rrxn2 n.c.

Rq1

Cp1 0 Ω xxx(1) pF/50 V

Cp2 xxx(1) pF/50 V

Rq2

0 Ω xxx(1) pF/50 V

Cvmid

100 nF

ANTENNA

aaa-015905

(1) xxx: customer antenna matching tuning.

Fig 27. Application schematic


PN7120


12. Limiting values

Table 22.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).


V

DD(PAD)

V

DD(PAD)


V

BAT

V

ESD battery supply voltage electrostatic discharge voltage HBM; 1500

, 100 pF;

EIA/JESD22-A114-D

CDM; field induced model;

EIA/JESC22-C101-C

T stg

P tot

V

RXN(i)

V

RXP(i) storage temperature total power dissipation

RXN input voltage

RXP input voltage all modes

[1]

-

-

-

-

Min Max

4.2

6

1.5

500

-

55

+150

C

0.55

W

0 2.5

V

0 2.5

V

[1] The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the field or generated by PN7120 does not exceed this value.

Unit

V

V kV

V

13. Recommended operating conditions

Table 23.

Operating conditions


T amb

V

BAT

V

V

DD

DD(PAD) ambient temperature battery supply voltage

Conditions

JEDEC PCB-0.5

battery monitor enabled;

V

SS

= 0 V

Card Emulation and

Passive Target;

V

SS

= 0 V

Reader, Active Initiator and Active Target;

V

SS

= 0 V supply voltage

V

DD(PAD)


I

P tot

O(VDDTX)

1.8 V host supply;

V

SS

= 0 V

3 V host supply;

V

SS

= 0 V total power dissipation Reader;

I

VDD(TX)

V

BAT

= 100 mA;

= 5.5 V output current on pin

V

DD(TX)

[1]

[1]

[2]

[1]

[2]


30

+25 +85

C

2.3

5.5

V

2.3

2.7

[1]

1.65

1.8 1.95

V

[1]

[2]

-

-

1.65

3.0

-

-

-

-

-

1.8

5.5

5.5

1.95

3.6

0.5

100

V

V

V

V

W mA

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Table 23.

Operating conditions

…continued


I

BAT battery supply current

I

VBAT(tot) in Hard Power Down state; V

BAT

T = 25 °C

= 3.6 V; in Standby state;

V

BAT

= 3.6 V; T = 25 °C in Monitor state;

V

BAT

= 2.75 V; T = 25 °C in low-power polling loop; V

BAT

T = 25 °C;

= 3.6 V; loop time = 500 ms

PCD mode at typical 3 V

I th(Ilim) total supply current on

V

BAT current limit threshold current current limiter on V pin; V

DD(TX)

= 3.1 V

DD(TX)

[3]

-

[3]

[4]

-

-

-

-

-


10 12

A

-

-

-

150

180 -

-

20

12

170

A

A

A mA mA

[1] V

SS

represents V

SS

, V

SS1

, V

SS2

, V

SS3

, V

SS4

, V

SS(PAD)

and V

SS(TX)

.

[2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account).

[3] The antenna shall be tuned not to exceed the maximum of I

VBAT

.

[4] This is the threshold of a built-in protection done to limit the current out of V

DD(TX)

in case of any issue at

I antenna pins to avoid burning the device. It is not allowed in operational mode to have I

VDD(TX)

VBAT

maximum value is exceeded.

such that

14. Thermal characteristics

Table 24.

Thermal characteristics


R th(j-a) thermal resistance from junction to ambient in free air with exposed pad soldered on a 4 layer JEDEC PCB

-


74 K/W

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15. Characteristics

15.1 Current consumption characteristics

Table 25.

Current consumption characteristics for operating ambient temperature range

I

Symbol

BAT

Parameter Conditions

battery supply current in Hard Power Down state;

V

BAT

= 3.6 V; VEN voltage = 0 V

-


10 18

A

[1]

20 35

A in Standby state;

V

BAT

= 3.6 V; including emulation phase of polling loop

[2]

6 mA in Idle and Target Active power states; V

BAT

= 3.6 V in Initiator Active power state; V

BAT

= 3.6 V in Monitor state;

V

BAT

= 2.75 V

[2]

[3]

-

13

10

-

18 mA

A

I

I

O(VDDTX)

O(VDDPAD) output current on pin

V

DD(TX) output current on pin

V

DD(PAD) total current which can be pulled on V

DD(PAD) referenced outputs

[4]

[5]

-

-

-

30 100

15 mA mA

[1]

Refer to Section 10.1.2.4

for the description of the power modes.

[2]

Refer to Section 10.1.2.5

for the description of the polling loop.

[3] This is the same value for V

BAT

= 2.3 V when the monitor threshold is set to 2.3 V.

[4] I

VDD(TX)

depends on V

DD(TX)

and on the external circuitry connected to TX1 and TX2.

[5]

During operation with a typical circuitry as recommended by NXP in Ref. 6

, the overall current is below

100 mA even when loaded by target/card/tag.

15.2 Functional block electrical characteristics

15.2.1 Battery voltage monitor characteristics

Table 26.

Battery voltage monitor characteristics


V th threshold voltage

Conditions

set to 2.3 V set to 2.75 V

V hys hysteresis voltage

15.2.2 Reset via VEN

Table 27.

Reset timing

Symbol

t

W(VEN) t boot

Parameter

VEN pulse width boot time

Conditions

to reset

Min

2.2

2.65

100

Typ

2.3

2.75

150

Max

2.4

2.85

200

Unit

V

V mV

-


3 -

s

2.5

ms

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15.2.3 Power-up timings

Table 28.

Power-up timings

t t

Symbol

t t(VBAT-VEN) t(VDDPAD-VEN) t(VBAT-VDDPAD)

Parameter

transition time from pin V

BAT to pin VEN transition time from pin

V

DD(PAD)

to pin VEN transition time from pin V

BAT to pin V

DD(PAD)

Conditions

V

BAT

, VEN voltage = HIGH

V

DD(PAD)

, VEN voltage = HIGH

V

BAT

,

V

DD(PAD)

= HIGH

15.2.4 Power-down timings

Table 29.

Power-down timings


t

VBAT(L) time V

BAT

LOW

15.2.5 Thermal protection

Table 30.

Thermal threshold


T th(act)otp overtemperature protection activation threshold temperature

Conditions

Conditions

15.2.6 I

2

C-bus timings

Here below are timings and frequency specifications.

t f(HIF3) t r(HIF3)


0 ms

0

0 -

-

-

ms ms


20 ms


120 125 130

C t

HD;DAT

HIF3 (SDA) t

SU;STA t

HD;STA t

HIGH t

SU;DAT t

LOW

HIF4 (SCL)

aaa-014046

Fig 28. I

2

C-bus timings

PN7120


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Table 31.

High-speed mode I

2

C-bus timings specification

t t f

Symbol

clk(I2CSCL)

SU;STA

HD;STA

Parameter

clock frequency on pin

I2CSCL set-up time for a repeated

START condition hold time (repeated) START condition

Conditions

I

2

C-bus SCL;

C b

< 100 pF

C b

< 100 pF

C b

< 100 pF


Rev. 2 — 15 June 2015

312420

Min

0

160

160 -

-

Max Unit

3.4

MHz ns ns


36 of 55


PN7120


Table 31.

High-speed mode I

2


…continued

Symbol Parameter Conditions Min

t t

LOW t

HIGH t

SU;DAT t

HD;DAT t r(I2CSDA) f(I2CSDA)

V hys

LOW period of the SCL clock C b

< 100 pF

HIGH period of the SCL clock C b

< 100 pF data set-up time C b

< 100 pF data hold time rise time on pin I2CSDA fall time on pin I2CSDA hysteresis voltage

C b

< 100 pF

I

2

C-bus SDA;

C b

< 100 pF

I

2

C-bus SDA;

C b

< 100 pF

Schmitt trigger inputs;

C b

< 100 pF

160

60

10

0

10

10

0.1V

DD(PAD)

-

80

-

-

80

-

-

Max Unit

ns ns ns ns ns ns

V

Table 32.

Fast mode I

2


) f t


clk(I2CSCL

SU;STA set-up time for a repeated

START condition

Conditions

clock frequency on pin I2CSCL I

2

C-bus SCL;

C b

< 400 pF

C b

< 400 pF t

HD;STA t t t t

LOW

HIGH

SU;DAT

HD;DAT

V hys hold time (repeated) START condition

C b

< 400 pF

LOW period of the SCL clock C b

< 400 pF

HIGH period of the SCL clock C b

< 400 pF data set-up time C b

< 400 pF data hold time hysteresis voltage

C b

< 400 pF

Schmitt trigger inputs;

C b

< 400 pF

Min

0

600 -

Max Unit

400 kHz ns

600 ns

1.3

600

100

0

0.1V

DD(PAD)

-

-

-

s ns ns

-

900 ns

V

15.3 Pin characteristics

15.3.1 XTAL1 and XTAL2 pins characteristics

Table 33.

Input clock characteristics on XTAL1 when using PLL

Symbol

V i(p-p)



Parameter

peak-to-peak input voltage duty cycle

Conditions Min Typ Max Unit

0.2

1.8

V

35 65 %

Table 34.

Pin characteristics for XTAL1 when PLL input

I


IH

I

IL

V i

V i(clk)(p-p)

HIGH-level input current

LOW-level input current input voltage peak-to-peak clock input voltage

C i input capacitance

Conditions

V

I

= V

DD

V

I

= 0 V all power modes -

-

-


1 -

-

-

1

A

A

200 -

-

-

V

DD

V mV

2 pF

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Table 35.

Pin characteristics for 27.12 MHz crystal oscillator

Symbol

C i(XTAL1)

C i(XTAL2)

Parameter Conditions

XTAL1 input capacitance V

DD

V

DC

V

AC

= 1.8 V;

= 0.65 V;

= 0.9 V(p-p)

XTAL2 input capacitance

-

-

Min Typ

2

2

-

-

Max Unit

pF pF

[1] See the

Figure 27

for example of appropriate connected components. The layout should ensure minimum distance between the pins and the components.

Table 36.

PLL accuracy

f


o(acc)

Conditions

output frequency accuracy deviation added to XTAL1 frequency on RF frequency generated; worst case whatever input frequency


50 -

+50 ppm

15.3.2 VEN input pin characteristics

Table 37.

VEN input pin characteristics


I

V

IH

V

IL

I

IH

IL

HIGH-level input voltage

LOW-level input voltage


LOW-level input current

VEN voltage = V

BAT

VEN voltage = 0 V

C i input capacitance -

-

Min

1.1

0

1 -

-

-

-

Typ

5 -

-

Max

V

BAT

0.4

1

Unit

V

V

A

A pF

15.3.3 Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL

Table 38.

pin characteristics for IRQ, CLK_REQ and BOOST_CTRL


V

OH

HIGH-level output voltage

I

Conditions

OH

< 3 mA

Min

V

DD(PAD)

 0.4

-

Typ Max

V

DD(PAD)

V

OL

I

OL

< 3 mA 0 0.4

t

C f

L

LOW-level output voltage load capacitance fall time

20

C

L

= 12 pF max high speed slow speed

1

2

-

-

3.5

10 t r

R pd rise time pull-down resistance

C

L

= 12 pF max high speed slow speed

[1]

1

2

0.4

-

-

3.5

10

0.75

[1] Activated in HPD and Monitor states.

Unit

V

V pF ns ns ns ns

M



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15.3.4 ANT1 and ANT2 pin characteristics

Table 39.

Electrical characteristics of ANT1 and ANT2

Symbol

Z i(ANT1-ANT2)

Parameter

input impedance between ANT1 and

ANT2

Conditions

low impedance

V th(ANT1)

V th(ANT2)

ANT1 threshold voltage

ANT2 threshold voltage

I = 10 mA

I = 10 mA

15.3.5 Input pin characteristics for RXN and RXP

Table 40.

Input pin characteristics for RXN and RXP


V

RXN(i)

V

RXP(i)

C i(RXN)

C i(RXP)

Z i(RXN-VDDMI

D)

)

Z i(RXP-VDDMID

V i(dyn)(RXN)

RXN input voltage

RXP input voltage

RXN input capacitance

RXP input capacitance input impedance between

RXN and V

DD(MID) input impedance between

RXP and V

DD(MID)

Reader, Card and

P2P modes

Reader, Card and

P2P modes

RXN dynamic input voltage Miller coded

106 kbit/s

V i(dyn)(RXP)

212 to 424 kbit/s

RXP dynamic input voltage Miller coded

106 kbit/s

212 to 424 kbit/s

V i(dyn)(RXN)

V

V

V

V i(dyn)(RXP) i(dyn)(RXN) i(dyn)(RXP) i(RF)

RXN dynamic input voltage Manchester, NRZ or BPSK coded;

106 to 848 kbit/s

RXP dynamic input voltage Manchester, NRZ or BPSK coded;

106 to 848 kbit/s

RXN dynamic input voltage All data coding;

106 kbit/s to

848 kbit/s

RXP dynamic input voltage All data coding;

106 kbit/s to

848 kbit/s

RF input voltage RF input voltage detected; Initiator modes

-

-

-

-

-

-

-

-

-


10 17



3.3

-

3.3

-

-

-


0

0

0

-

-

12 -

V

DD

V

DD

V

V pF

-

12 pF

15 k



0

V

DD

-

V

DD

-

-

V

V

150 200 mV(p-p)

150 200 mV(p-p)

150 200 mV(p-p)

150 200 mV(p-p)

150 200 mV(p-p)

150 200 mV(p-p)

100 -

-

-

15 k



V(p-p)

V(p-p) mV(p-p)

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15.3.6 Output pin characteristics for TX1 and TX2

Table 41.

Output pin characteristics for TX1 and TX2

Symbol

V

OH

Parameter

HIGH-level output voltage I

Conditions

V

DD(TX)

OH

= 3.1 V and

= 30 mA;

PMOS driver fully on

V

OL

LOW-level output voltage I

V

DD(TX)

OL

= 3.1 V and

= 30 mA;

NMOS driver fully on

-

Min Typ

V

DD(TX)

 150 -

-

-

Max Unit

mV

200 mV

Table 42.

Output resistance for TX1 and TX2


R

R

R

OL

OL

OH

LOW-level output resistance

LOW-level output resistance

HIGH-level output resistance

V

DD(TX)

 100 mV;

CWGsN = 01h

V

DD(TX)

 100 mV;

CWGsN = 0Fh

V

DD(TX)

 100 mV

-

-

-

Min

-

-

-

Typ Max

80

5

4

Unit







15.3.7 Input pin characteristics for I2CADR0

Table 43.

Input pin characteristics for I2CADR0


V

IH

V

IL



I

I

IH

IL

C i


LOW-level input current input capacitance

V

I

= V

DD(PAD)

;

T = 125 °C

V

I

= 0 V;

T = 125 °C

-

-

Min

0.65V

DD(PAD)

-

Typ Max

V

DD(PAD)

0

1

-

-

-

5 -

-

Unit

V

0.35V

DD(PAD)

V

1

15.3.8 Pin characteristics for I2CSDA and I2CSCL

Table 44.

Pin characteristics for I2CSDA and I2CSCL

Below values are given for V

DD(PAD)

in the range of 1.8 V; unless specified.

Symbol Parameter Conditions Min Typ Max

V

OL

C

L

LOW-level output voltage load capacitance

I

OL

< 3 mA

-

0

-

0.4

10

A

A pF

Unit

V pF

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Table 44.

Pin characteristics for I2CSDA and I2CSCL

…continued

Below values are given for V

DD(PAD)

in the range of 1.8 V; unless specified.

Symbol Parameter Conditions Min Typ Max

t f fall time 30 250 C

L

= 100 pF;

Rpull-up = 1.8 k

;

Standard and Fast mode

C

L

= 100 pF;

V

DD(PAD)

= 3.3 V;

Rpull-up = 3.3 k

;


30 250

80 110 t r rise time

C

L

= 100 pF;

Rpull-up = 1 k

;

High-speed mode

C

L

= 100 pF;

Rpull-up = 1.8 k

;


C

L

= 100 pF;

V

DD(PAD)

= 3.3 V;

Rpull-up = 3.3 k

;


C

L

= 100 pF;

Rpull-up = 1 k

;

High-speed mode

30

30

10 -

-

250

250

100

I

I

V

IH

V

IH

IL

C i

IL




LOW-level input current input capacitance

V

I

= V

DD(PAD)

; high impedance

V

I

= 0 V; high impedance

-

-

0.7V

DD(PAD)

0

1

-

-

-

-

5 -

-

V

DD(PAD)

0.3V

1

DD(PAD)

Unit

ns ns ns ns ns ns

V

V

A

A pF

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16. Package outline

VFBGA49: plastic very thin fine-pitch ball grid array package; 49 balls SOT1320-1

D B A ball A1 index area

A

A

2

E

A

1 detail X e

1 e b

Ø v

Ø w

C

C

A B ball A1 index area

G

F

E

D

C

B

A

1 2 3 4 5 6 7 e e

2 y

1

C

C y

X

0

Dimensions (mm are the original dimensions) mm

Unit A A

1

A

2 b D E e max nom min

1.00

0.25

0.90

0.20

0.80

0.15

0.75

0.70

0.65

0.35

4.1

4.4

0.30

4.0

4.3

0.5

0.25

3.9

4.2

e

1 e

2 scale v w y y

1

3.0

3.0

0.15

0.05

0.08

0.1

5 mm

Outline version

IEC JEDEC

References

JEITA

SOT1320-1

Fig 29. Package outline, VFBGA49, SOT1320-1, MSL 1

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sot1320-1_po

Issue date

11-11-11

11-12-30


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17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

•

Through-hole components

•

Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•

Board specifications, including the board finish, solder masks and vias

•

Package footprints, including solder thieves and orientation

•

The moisture sensitivity level of the packages

•

Package placement

•

Inspection and repair

•

Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

•

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave

•

Solder bath specifications, including temperature and impurities

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17.4 Reflow soldering

Key characteristics in reflow soldering are:

•

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30 ) than a SnPb process, thus

reducing the process window

•

Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board

•

Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 45 and 46

Table 45.

SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm

3

)

< 350

 350

< 2.5

 2.5

235

220

220

220

Table 46.

Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm

3

)

< 1.6

< 350

260

350 to 2000

260

1.6 to 2.5

> 2.5

260

250

250

245

> 2000

260

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see

Figure 30 .

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temperature maximum peak temperature

= MSL limit, damage level minimum peak temperature

= minimum soldering temperature peak

temperature time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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18. Abbreviations

Table 47.

Abbreviations

Acronym Description

API

ASK

Application Programming Interface

Amplitude Shift keying

ASK modulation index

Automatic device discovery

BPSK

Card Emulation

The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/

(Vmax + Vmin)

 100 %

Detect and recognize any NFC peer devices (initiator or target) like: NFC initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Standard and Ultralight PICC, ISO/IEC 15693 VICC

Bit Phase Shift Keying

The IC is capable of handling a PICC emulation on the RF interface including part of the protocol management. The application handling is done by the host controller

Data Exchange Protocol DEP

DSLDO

FW

HPD

LDO

LFO

MOSFET

Dual Supplied LDO

FirmWare

Hard Power Down

Low Drop Out

Low Frequency Oscillator

Metal Oxide Semiconductor Field Effect Transistor

Moisture Sensitivity Level

NFC Controller Interface

MSL

NCI

NFC

NFCC

NFC Initiator

NFCIP

NFC Target

NRZ

P2P

PCD

PCD -> PICC

PICC

PICC-> PCD

PMOS

PMU

PSL

TXLDO

UM

Near Field Communication

NFC Controller, PN7120

in this data sheet

Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

NFC Interface and Protocol

Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication

Non Return to Zero

Peer to Peer

Proximity Coupling Device. Definition for a Card reader/writer device according to the ISO/IEC 14443 specification or MIFARE

Communication flow between a PCD and a PICC according to the

ISO/IEC 14443 specification or MIFARE

Proximity Interface Coupling Card. Definition for a contactless Smart Card according to the ISO/IEC 14443 specification or MIFARE

Communication flow between a PICC and a PCD according to the

ISO/IEC 14443 specification or MIFARE

P-channel MOSFET

Power Management Unit

Parameter SeLection

Transmitter LDO

User Manual

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Table 47.

Abbreviations

…continued

Acronym Description

VCD Vicinity Coupling Device. Definition for a reader/writer device according to the

ISO/IEC 15693 specification

Voltage Controlled Oscillator VCO

VICC

WUC

Vicinity Integrated Circuit Card

Wake-Up Counter

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19. References

[1]

NFC Controller Interface (NCI) Technical Specification — V1.0

[2]

ISO/IEC 14443 — parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1

2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008)

[3] I

2

C Specification — I

2

C Specification, UM10204 rev4 (13/02/2012)

[4]

PN7120 User Manual — UM10819 PN7120 User Manual

[5]

PN7120 Hardware Design Guide — AN11565 PN7120 Hardware Design Guide

[6]

PN7120 Antenna and Tuning Design Guide — AN11564 PN7120 Antenna and

Tuning Design Guide

[7]

ISO/IEC 18092 (NFCIP-1) — edition, 15/032013. This is similar to Ecma 340.

[8]

ISO/IEC15693 — part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001)

[9]

PN7120 Low-Power Mode Configuration — AN11562 PN7120 Low-Power Mode

Configuration

[10] ISO/IEC 21481 (NFCIP-2) — edition, 01/07/2012. This is similar to Ecma 352.

[11] NFC Forum Device Requirements — V1.3

[12] ETSI SWP — TS 102 613; UICC - Contacless Front-end (CLF) Interface; Part 1:

Physical and data link layer characteristics (Release 9)

[13] ETSI HCI — TS 102 622; UICC - Contacless Front-end (CLF) Interface; Host

Controller Interface (HCI) (Release 9)

[14] ETSI UICC — TS 102 221; UICC - Terminal Interface; Physical and logical characteristics (Release 9)

[15] EMVCo — EMV Contactless Specifications for Payment Systems - Book D - EMV

Contactless Communication Protocol Specification”, version 2.3.1, December 2013

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20. Revision history

Table 48.

Revision history

Document ID Release date

PN7120 v.2

Modifications:

PN7120 v.1

20150615

•

Table 33 : updated.

20150506

Data sheet status

Preliminary data sheet

Objective data sheet -

-

Change notice

-

Supersedes

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21. Legal information

PN7120


Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

21.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

21.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

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Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.



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Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

21.4 Licenses

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s

Contactless Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC in systems and/or end-user equipment.

RATP/Innovatron

Technology

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.

21.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I

2

C-bus — logo is a trademark of NXP Semiconductors N.V.

DESFire — is a trademark of NXP Semiconductors N.V.

MIFARE — is a trademark of NXP Semiconductors N.V.

MIFARE Classic — is a trademark of NXP Semiconductors N.V.

MIFARE Ultralight — is a trademark of NXP Semiconductors N.V.

ICODE and I-CODE — are trademarks of NXP Semiconductors N.V.

22. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

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23. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .4

Table 3. Marking code . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. PN7120 pin description . . . . . . . . . . . . . . . . . . .7

Table 5. System power modes description . . . . . . . . . .10

Table 6. System power modes configuration . . . . . . . . .10

Table 7. System power modes description . . . . . . . . . .10

Table 8. PN7120 power states . . . . . . . . . . . . . . . . . . . 11

Table 9. Functional modes in active state . . . . . . . . . . .12

Table 10. Functionality for I

2

C-bus interface . . . . . . . . . .15

Table 11. I

2

C-bus interface addressing . . . . . . . . . . . . . .15

Table 12. Crystal requirements . . . . . . . . . . . . . . . . . . . .16

Table 13. PLL input requirements . . . . . . . . . . . . . . . . . .17

Table 14. Overview for ISO/IEC 14443A/MIFARE

Reader/Writer communication mode . . . . . . . .24

Table 15. Overview for FeliCa

Reader/Writer communication mode . . . . . . . .25

Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode . . . . . . . . . . . . . . . . . . .25

Table 17. Overview for ISO/IEC 15693 VCD communication mode . . . . . . . . . . . . . . . . . . .26

Table 18. Overview for Active communication mode . . . .28

Table 19. Overview for Passive communication mode . .29

Table 20. Overview for ISO/IEC 14443A/MIFARE card communication mode . . . . . . . . . . . . . . . . . . .30

Table 21. Overview for ISO/IEC 14443B card communication mode . . . . . . . . . . . . . . . . . . .30

Table 22. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 23. Operating conditions . . . . . . . . . . . . . . . . . . . .33

Table 24. Thermal characteristics . . . . . . . . . . . . . . . . . .34

Table 25. Current consumption characteristics for operating ambient temperature range . . . . . . .35

Table 26. Battery voltage monitor characteristics . . . . . .35

Table 27. Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 28. Power-up timings . . . . . . . . . . . . . . . . . . . . . . .36

Table 29. Power-down timings . . . . . . . . . . . . . . . . . . . .36

Table 30. Thermal threshold . . . . . . . . . . . . . . . . . . . . . .36

Table 31. High-speed mode I

2

C-bus timings specification . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 32. Fast mode I

2

C-bus timings specification . . . . .37

Table 33. Input clock characteristics on XTAL1 when using PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 34. Pin characteristics for XTAL1 when PLL input .37

Table 35. Pin characteristics for 27.12 MHz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 36. PLL accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 37. VEN input pin characteristics . . . . . . . . . . . . . .38

Table 38. pin characteristics for IRQ, CLK_REQ and

BOOST_CTRL . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 39. Electrical characteristics of ANT1 and ANT2 . .39

Table 40. Input pin characteristics for RXN and RXP . . .39

Table 41. Output pin characteristics for TX1 and TX2 . . .40

Table 42. Output resistance for TX1 and TX2 . . . . . . . . .40

Table 43. Input pin characteristics for I2CADR0 . . . . . . .40

Table 44. Pin characteristics for I2CSDA and I2CSCL . .40

Table 45. SnPb eutectic process (from J-STD-020D) . . .44

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Table 46. Lead-free process (from J-STD-020D) . . . . . . 44

Table 47. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 48. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 49


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24. Figures

Fig 1. PN7120 transmission modes. . . . . . . . . . . . . . . . .2

Fig 2. PN7120 package marking (top view) . . . . . . . . . . .4

Fig 3. PN7120 block diagram . . . . . . . . . . . . . . . . . . . . .6

Fig 4. PN7120 pinning (bottom view). . . . . . . . . . . . . . . .7

Fig 5. PN7120 connection . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 6. System power mode diagram . . . . . . . . . . . . . . .10

Fig 7. Polling loop: all phases enabled . . . . . . . . . . . . .13

Fig 8. Polling loop: low-power RF polling. . . . . . . . . . . .14

Fig 9. 27.12 MHz crystal oscillator connection. . . . . . . .16

Fig 10. Input reference phase noise characteristics . . . .17

Fig 11. PMU functional diagram . . . . . . . . . . . . . . . . . . .18

Fig 12. V

DD(TX)

offset disabled behavior . . . . . . . . . . . . .19

Fig 13. V

DD(TX)

behavior when PN7120 is in Standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 14. Battery voltage monitor principle . . . . . . . . . . . . .20

Fig 15. Resetting PN7120 via VEN pin . . . . . . . . . . . . . .21

Fig 16. V

BAT

Fig 17. V

is set up before V

DD(PAD)

DD(PAD)

and V

BAT

. . . . . . . . . . . . . . .21

are set up in the same time . .22

Fig 18. V

DD(PAD)

is set up or cut-off after PN7120 has been enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 19. PN7120 power-down sequence. . . . . . . . . . . . . .23

Fig 20. ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram. . . . . . . . . . . . . . .24

Fig 21. FeliCa Reader/Writer communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 22. ISO/IEC 14443B Reader/Writer communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 23. ISO/IEC 15693 VCD communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 24. NFCIP-1 communication mode . . . . . . . . . . . . . .27

Fig 25. Active communication mode . . . . . . . . . . . . . . . .28

Fig 26. Passive communication mode . . . . . . . . . . . . . . .29

Fig 27. Application schematic . . . . . . . . . . . . . . . . . . . . .32

Fig 28. I

2

C-bus timings . . . . . . . . . . . . . . . . . . . . . . . . . .36

Fig 29. Package outline, VFBGA49, SOT1320-1,

MSL 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Fig 30. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

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25. Contents

1

2

3

4

5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

6

7

8

Ordering information . . . . . . . . . . . . . . . . . . . . . 4

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

9

9.1

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

10 Functional description . . . . . . . . . . . . . . . . . . . 8

10.1 System modes . . . . . . . . . . . . . . . . . . . . . . . . . 9

10.1.1 System power modes . . . . . . . . . . . . . . . . . . . . 9

10.1.2 PN7120 power states . . . . . . . . . . . . . . . . . . . 10

10.1.2.1 Monitor state . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10.1.2.2 Hard Power Down (HPD) state. . . . . . . . . . . . 11

10.1.2.3 Standby state . . . . . . . . . . . . . . . . . . . . . . . . . 11

10.1.2.4 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10.1.2.5 Polling loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10.2 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 14

10.3

10.3.1 I

Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 14

2

C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15

10.3.1.1 I 2

C-bus configuration . . . . . . . . . . . . . . . . . . . 15

10.4 PN7120 clock concept . . . . . . . . . . . . . . . . . . 15

10.4.1 27.12 MHz quartz oscillator . . . . . . . . . . . . . . 16

10.4.2 Integrated PLL to make use of external clock 16

10.4.3 Low-power 20 MHz oscillator . . . . . . . . . . . . . 18

10.4.4 Low-power 380 kHz oscillator. . . . . . . . . . . . . 18

10.5 Power concept . . . . . . . . . . . . . . . . . . . . . . . . 18

10.5.1 PMU functional description. . . . . . . . . . . . . . . 18

10.5.2 DSLDO: Dual Supply LDO . . . . . . . . . . . . . . . 18

10.5.3 TXLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.5.3.1 TXLDO limiter . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.5.4 Battery voltage monitor. . . . . . . . . . . . . . . . . . 20

10.6 Reset concept. . . . . . . . . . . . . . . . . . . . . . . . . 20

10.6.1 Resetting PN7120 . . . . . . . . . . . . . . . . . . . . . 20

10.6.2 Power-up sequences . . . . . . . . . . . . . . . . . . . 21

10.6.2.1 V

BAT

is set up before V

DD(PAD)

10.6.2.2 V

DD(PAD)

and V

BAT

. . . . . . . . . . . . 21

are set up in the same time 22

10.6.2.3 PN7120 has been enabled before V

is set up or before V

DD(PAD)

DD(PAD)

has been cut off . 22

10.6.3 Power-down sequence . . . . . . . . . . . . . . . . . . 23

10.7 Contactless Interface Unit. . . . . . . . . . . . . . . . 23

10.7.1 Reader/Writer communication modes . . . . . . 23

10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz

PCD communication mode. . . . . . . . . . . . . . . 23

10.7.1.2 FeliCa PCD communication mode. . . . . . . . . 24

10.7.1.4 ISO/IEC 15693 VCD communication mode . . 26

10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes . . . . . . . . . . . . . . . . . . 27

10.7.2.1 ACTIVE communication mode. . . . . . . . . . . . 27

10.7.2.2 Passive communication mode . . . . . . . . . . . . 28

10.7.2.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 29

10.7.2.4 NFCIP-1 protocol support . . . . . . . . . . . . . . . 29

10.7.3 Card communication modes . . . . . . . . . . . . . 30 communication mode. . . . . . . . . . . . . . . . . . . 30

10.7.3.2 ISO/IEC 14443B card communication mode . 30

10.7.4 Frequency interoperability . . . . . . . . . . . . . . . 31

11

12

Application design-in information. . . . . . . . . 32

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

13

14

Recommended operating conditions . . . . . . 33

Thermal characteristics . . . . . . . . . . . . . . . . . 34

15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

15.1

15.2

Current consumption characteristics . . . . . . . 35

Functional block electrical characteristics . . . 35

15.2.1 Battery voltage monitor characteristics . . . . . 35

15.2.2 Reset via VEN . . . . . . . . . . . . . . . . . . . . . . . . 35

15.2.3 Power-up timings . . . . . . . . . . . . . . . . . . . . . . 36

16

17

17.1

17.2

17.3

17.4

18

15.2.5 Thermal protection . . . . . . . . . . . . . . . . . . . . . 36

15.2.6 I

2

C-bus timings. . . . . . . . . . . . . . . . . . . . . . . . 36

15.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 37

15.3.1 XTAL1 and XTAL2 pins characteristics . . . . . 37

15.3.2 VEN input pin characteristics . . . . . . . . . . . . . 38

15.3.3 Pin characteristics for IRQ, CLK_REQ and

BOOST_CTRL . . . . . . . . . . . . . . . . . . . . . . . . 38

15.3.4 ANT1 and ANT2 pin characteristics. . . . . . . . 39

15.3.5 Input pin characteristics for RXN and RXP . . 39

15.3.6 Output pin characteristics for TX1 and TX2 . . 40

15.3.7 Input pin characteristics for I2CADR0 . . . . . . 40

15.3.8 Pin characteristics for I2CSDA and I2CSCL . 40

19

20

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42

Soldering of SMD packages . . . . . . . . . . . . . . 43

Introduction to soldering. . . . . . . . . . . . . . . . . 43

Wave and reflow soldering. . . . . . . . . . . . . . . 43

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

continued >>

PN7120


COMPANY PUBLIC


Rev. 2 — 15 June 2015

312420


54 of 55


PN7120


21

21.1

21.2

21.3

21.4

21.5

22

23

24

25

Legal information. . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Contact information. . . . . . . . . . . . . . . . . . . . . 51

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2015.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 15 June 2015

312420

PN7120

Full NFC Forum-compliant controller with integrated firmware and NCI interface

1. Introduction

3. Features and benefits

4. Applications

5. Quick reference data

7. Marking

10. Functional description

11. Application design-in information

12. Limiting values

13. Recommended operating conditions

14. Thermal characteristics

15. Characteristics

16. Package outline

17. Soldering of SMD packages

18. Abbreviations

19. References

20. Revision history

21. Legal information

22. Contact information

23. Tables

24. Figures

25. Contents

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