SiI9233A HDMI Receiver with Repeater, Multi

SiI9233A HDMI Receiver with Repeater, Multi

SiI9233A HDMI Receiver with Repeater,

Multi-channel Audio, and Deep Color

Data Sheet

SiI-DS-1061-C

March 2016

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Contents

1.

General Description ...................................................................................................................................................... 6

1.1.

Inputs .................................................................................................................................................................... 6

1.2.

Digital Video Output ............................................................................................................................................. 6

1.3.

Digital Audio Interface .......................................................................................................................................... 6

1.4.

Control .................................................................................................................................................................. 6

1.5.

Package ................................................................................................................................................................. 6

2.

System Applications ...................................................................................................................................................... 7

3.

Comparing Features of Lattice Semiconductor Receiver Devices ................................................................................ 7

4.

Functional Description .................................................................................................................................................. 8

4.1.

TMDS Digital Cores ............................................................................................................................................... 8

4.2.

Active Port Detection and Selection ..................................................................................................................... 8

4.3.

HDCP Decryption Engine/XOR Mask ................................................................................................................... 10

4.4.

HDCP Embedded Keys ......................................................................................................................................... 10

4.5.

Data Input and Conversion ................................................................................................................................. 10

4.5.1.

Mode Control Logic ..................................................................................................................................... 10

4.5.2.

Video Data Conversion and Video Output .................................................................................................. 10

4.5.3.

Deep Color Support..................................................................................................................................... 11

4.5.4.

xvYCC Support ............................................................................................................................................. 11

4.6.

3D Video Formats ............................................................................................................................................... 12

4.6.1.

Default Video Configuration ....................................................................................................................... 12

4.6.2.

Automatic Video Configuration .................................................................................................................. 13

4.7.

Audio Data Output Logic ..................................................................................................................................... 14

4.7.1.

S/PDIF .......................................................................................................................................................... 14

4.7.2.

I2S ............................................................................................................................................................... 14

4.7.3.

One-Bit Audio Input (DSD/SACD) ................................................................................................................ 14

4.7.4.

High-Bitrate Audio on HDMI ....................................................................................................................... 14

4.7.5.

Auto Audio Configuration ........................................................................................................................... 16

4.7.6.

Soft Mute .................................................................................................................................................... 16

4.8.

Control and Configuration .................................................................................................................................. 17

4.8.1.

Register/Configuration Logic ...................................................................................................................... 17

4.8.2.

I

2

C Serial Ports ............................................................................................................................................. 17

4.8.3.

EDID FLASH and RAM Block ........................................................................................................................ 17

4.8.4.

CEC Interface ............................................................................................................................................... 18

4.8.5.

Standby and HDMI Port Power Supplies ..................................................................................................... 18

5.

Electrical Specifications .............................................................................................................................................. 19

5.1.

Absolute Maximum Conditions .......................................................................................................................... 19

5.2.

Normal Operating Conditions ............................................................................................................................. 20

5.3.

DC Specifications ................................................................................................................................................. 21

5.3.1.

DC Power Supply Pin Specifications ............................................................................................................ 22

5.4.

AC Specifications ................................................................................................................................................. 24

5.4.1.

Video Output Timings ................................................................................................................................. 24

5.4.2.

Audio Output Timings ................................................................................................................................. 25

5.4.3.

Miscellaneous Timings ................................................................................................................................ 26

5.4.4.

Interrupt Timings ........................................................................................................................................ 27

6.

Timing Diagrams ......................................................................................................................................................... 28

6.1.

TMDS Input Timing Diagrams ............................................................................................................................. 28

6.2.

Power Supply Control Timings ............................................................................................................................ 28

6.3.

Reset Timings ...................................................................................................................................................... 29

6.4.

Digital Video Output Timing Diagrams................................................................................................................ 29

6.4.1.

Output Transition Times ............................................................................................................................. 29

6.4.2.

Output Clock to Output Data Delay ............................................................................................................ 30

6.5.

Digital Audio Output Timings .............................................................................................................................. 30

2

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

6.6.

Calculating Setup and Hold Times for Video Bus ................................................................................................ 31

6.6.1.

24/30/36-Bit Mode ..................................................................................................................................... 31

6.6.2.

12/15/18-Bit Dual-Edge Mode .................................................................................................................... 32

6.7.

Calculating Setup and Hold Times for I

2

S Audio Bus ........................................................................................... 33

7.

Pin Diagram and Descriptions ..................................................................................................................................... 34

7.1.

Pin Diagram ......................................................................................................................................................... 34

7.2.

Pin Descriptions .................................................................................................................................................. 35

7.2.1.

Differential Signal Data Pins........................................................................................................................ 35

7.2.2.

Digital Video Output Data Pins ................................................................................................................... 36

7.2.3.

Digital Video Output Control Pins ............................................................................................................... 37

7.2.4.

HDMI Control Signal Pins ............................................................................................................................ 37

7.2.5.

Digital Audio Output Pins ............................................................................................................................ 38

7.2.6.

Configuration/Programming Pins ............................................................................................................... 39

7.2.7.

Power and Ground Pins .............................................................................................................................. 39

7.2.8.

Reserved and Not Connected Pins .............................................................................................................. 39

8.

Feature Information ................................................................................................................................................... 40

8.1.

Video Path........................................................................................................................................................... 40

8.1.1.

HDMI Input Modes to SiI9233A Receiver Output Modes ........................................................................... 40

8.1.2.

Output Mode Configuration ....................................................................................................................... 44

8.2.

I

2

C Interfaces ....................................................................................................................................................... 58

8.2.1.

HDCP E-DDC / I

2

C Interface ......................................................................................................................... 58

8.2.2.

Local I

2

8.2.3.

8.2.4.

I

C Interface ....................................................................................................................................... 59

Video Requirement for I

2

2

C Access .............................................................................................................. 59

C Registers ................................................................................................................................................ 59

9.

Design Recommendations .......................................................................................................................................... 60

9.1.

Power Control ..................................................................................................................................................... 60

9.2.

Power-on Sequencing ......................................................................................................................................... 60

9.3.

Power Pin Current Demands .............................................................................................................................. 60

9.4.

HDMI Receiver DDC Bus Protection .................................................................................................................... 61

9.5.

Decoupling Capacitors ........................................................................................................................................ 61

9.6.

ESD Protection .................................................................................................................................................... 61

9.7.

HDMI Receiver Layout ........................................................................................................................................ 62

9.8.

EMI Considerations ............................................................................................................................................. 63

9.9.

Typical Circuit ...................................................................................................................................................... 63

9.9.1.

Power Supply Decoupling ........................................................................................................................... 64

9.9.2.

HDMI Port Connections .............................................................................................................................. 65

9.9.3.

Digital Video Output Connections .............................................................................................................. 66

9.9.4.

Digital Audio Output Connections .............................................................................................................. 67

9.9.5.

Control Signal Connections ......................................................................................................................... 67

9.10.

Layout—TMDS Input Port Connections .......................................................................................................... 68

10.

Package Information ................................................................................................................................................... 69

10.1.

ePad Requirements......................................................................................................................................... 69

10.2.

PCB Layout Guidelines .................................................................................................................................... 69

10.3.

Package Dimensions ....................................................................................................................................... 70

10.4.

Marking Diagram ............................................................................................................................................ 71

10.5.

Ordering Information ...................................................................................................................................... 71

References .......................................................................................................................................................................... 72

Standards Documents..................................................................................................................................................... 72

Lattice Semiconductor Documents ................................................................................................................................. 72

Technical Support ........................................................................................................................................................... 72

Revision History .................................................................................................................................................................. 73

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 3

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Figures

Figure 1.1. Typical Application .............................................................................................................................................. 6

Figure 4.1. A/V Receiver Block Diagram ............................................................................................................................... 8

Figure 4.2. Functional Block Diagram ................................................................................................................................... 9

Figure 4.3. Default Video Processing Path .......................................................................................................................... 13

Figure 4.4. High Speed Data Transmission .......................................................................................................................... 15

Figure 4.5. High-Bitrate Stream Before and After Reassembly and Splitting ..................................................................... 15

Figure 4.6. High-Bitrate Stream After Splitting ................................................................................................................... 15

Figure 4.7. I

2

C Register Domains ......................................................................................................................................... 17

Figure 4.8. Power Island ..................................................................................................................................................... 18

Figure 5.1. Test Point VCCTP for VCC Noise Tolerance Spec .............................................................................................. 20

Figure 5.2. Audio Crystal Schematic ................................................................................................................................... 25

Figure 5.3. SCDT and CKDT Timing from DE or RXC Inactive/Active ................................................................................... 27

Figure 6.1. TMDS Channel-to-Channel Skew Timing .......................................................................................................... 28

Figure 6.2. Power Supply Sequencing ................................................................................................................................. 28

Figure 6.3. RESET# Minimum Timings................................................................................................................................. 29

Figure 6.4. Video Digital Output Transition Times .............................................................................................................. 29

Figure 6.5. Receiver Clock-to-Output Delay and Duty Cycle Limits .................................................................................... 30

Figure 6.6. I

2

S Output Timings ............................................................................................................................................ 30

Figure 6.7. S/PDIF Output Timings ...................................................................................................................................... 31

Figure 6.8. MCLK Timings .................................................................................................................................................... 31

Figure 6.9. 24/30/36-Bit Mode Receiver Output Setup and Hold Times ............................................................................ 31

Figure 6.10. 12/15/18-Bit Mode Receiver Output Setup and Hold Times .......................................................................... 32

Figure 7.1. Pin Diagram ....................................................................................................................................................... 34

Figure 8.1. Receiver Video and Audio Data Processing Paths ............................................................................................ 40

Figure 8.2. HDMI RGB 4:4:4 Input to Video Output Transformations ................................................................................ 41

Figure 8.3. HDMI YCbCr/xvYCC 4:4:4 Input to Video Output Transformations .................................................................. 42

Figure 8.4. HDMI YCbCr/xvYCC 4:2:2 Input to Video Output Transformations .................................................................. 43

Figure 8.5. 4:4:4 Timing Diagram ........................................................................................................................................ 46

Figure 8.6. YC Timing Diagram ............................................................................................................................................ 49

Figure 8.7. YC 4:2:2 Embedded Sync Timing Diagram ........................................................................................................ 52

Figure 8.8. YC Mux 4:2:2 Timing Diagram ........................................................................................................................... 54

Figure 8.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram ................................................................................. 56

Figure 8.10. 18-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 57

Figure 8.11. 15-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 57

Figure 8.12. 12-Bit Output 4:4:4 Timing Diagram ............................................................................................................... 57

Figure 8.13. I

2

Figure 8.14. I

2

C Byte Read ................................................................................................................................................... 58

C Byte Write .................................................................................................................................................. 58

Figure 8.15. Short Read Sequence ...................................................................................................................................... 58

Figure 9.1. Decoupling and Bypass Capacitor Placement ................................................................................................... 61

Figure 9.2. Cut-out Reference Plane Dimensions ............................................................................................................... 62

Figure 9.3. HDMI to Receiver Routing – Top View .............................................................................................................. 63

Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic .................................................................................... 64

Figure 9.5. HDMI Port Connections Schematic ................................................................................................................... 65

Figure 9.6. Digital Display Schematic .................................................................................................................................. 66

Figure 9.7. Audio Output Schematic ................................................................................................................................... 67

Figure 9.8. Controller Connections Schematic .................................................................................................................... 67

Figure 9.9. TMDS Input Signal Assignments ....................................................................................................................... 68

Figure 10.1. 144-Pin TQFP Package Diagram ...................................................................................................................... 70

Figure 10.2. Marking Diagram ............................................................................................................................................ 71

4

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Tables

Table 3.1. Comparison of Lattice Semiconductor Receiver Devices ..................................................................................... 7

Table 4.1. Digital Video Output Formats ............................................................................................................................ 10

Table 4.2. Supported 3D Video Formats ............................................................................................................................. 12

Table 4.3. Default Video Processing ................................................................................................................................... 12

Table 4.4. AVI InfoFrame Video Path Details ...................................................................................................................... 13

Table 4.5. Digital Output Formats Configurable through Auto Output Format Register ................................................... 14

Table 4.6. Supported MCLK Frequencies ............................................................................................................................ 14

Table 4.7. Maximum Audio Sampling Frequency for All Video Format Timings ................................................................ 16

Table 5.1. Absolute Maximum Conditions .......................................................................................................................... 19

Table 5.2. Normal Operating Conditions ............................................................................................................................ 20

Table 5.3. Digital I/O Specifications .................................................................................................................................... 21

Table 5.4. Total Power versus Power-Down Modes ........................................................................................................... 22

Table 5.5. Power-down Mode Definitions .......................................................................................................................... 23

Table 5.6. TMDS Input Timings ........................................................................................................................................... 24

Table 5.7. 12/15/18-Bit Data Output Timings .................................................................................................................... 24

Table 5.8. 16/20/24/30/36-Bit Data Output Timings ......................................................................................................... 24

Table 5.9. I

2

S Output Port Timings ...................................................................................................................................... 25

Table 5.10. S/PDIF Output Port Timings ............................................................................................................................. 25

Table 5.11. Audio Crystal Timings ....................................................................................................................................... 25

Table 5.12. Miscellaneous Timings ..................................................................................................................................... 26

Table 5.13. Interrupt Output Pin Timings ........................................................................................................................... 27

Table 6.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ............................................................................... 32

Table 6.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ............................................................................... 32

Table 6.3. I

2

S Setup and Hold Time Calculations ................................................................................................................ 33

Table 8.1. Translating HDMI Formats to Output Formats .................................................................................................. 40

Table 8.2. Output Video Formats ....................................................................................................................................... 44

Table 8.3. 4:4:4 Mappings .................................................................................................................................................. 45

Table 8.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................ 47

Table 8.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ............................................................................... 48

Table 8.6. YC 4:2:2 Embedded Sync Pin Mappings ............................................................................................................. 50

Table 8.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping ............................................................................. 51

Table 8.8. YC Mux 4:2:2 Mappings ..................................................................................................................................... 53

Table 8.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ...................................................................................................... 55

Table 8.10. 12/15/18-Bit Output 4:4:4 Mappings .............................................................................................................. 56

Table 8.11. Control of the Default I

2

C Addresses with the CI2CA Pin ................................................................................. 59

Table 9.1. Maximum Power Domain Current versus Video Mode ..................................................................................... 60

Table 10.1. SiI9233A HDMI Receiver Device Ordering Information ................................................................................... 71

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 5

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

1. General Description

The Lattice Semiconductor SiI9233A HDMI Receiver with

Repeater, Multi-channel Audio, and Deep Color is a

4-port HDMI

®

receiver device. AV receivers that connect to DTVs displaying 10/12-bit color depth can now provide the highest quality protected digital audio and video, including common 3D formats up to 12-bit, 1080p at 24 Hz resolution. The receiver supports Deep Color video up to 12-bit, 1080p at 60 Hz. Efficient color space conversion receives RGB or YCbCr video data and sends either standard-definition or high-definition RGB or

YCbCr formats.

The SiI9233A receiver supports the extended gamut YCC or xvYCC color space, described in the IEC 61966-2-4 specification, that supports approximately 1.8 times the number of colors as the RGB color space. The xvYCC color space also makes full use of the range on the standard 8bit resolution per pixel.

The SiI9233A receiver device is pre-programmed with

High-bandwidth Digital Content Protection (HDCP) keys; this helps reduce programming overhead and lowers manufacturing costs.

An integrated Extended Display Identification Data

(EDID) block stored in non-volatile memory (NVM) can be programmed at the time of manufacture using the local I

2

C bus. On-board RAM can also be loaded with

EDID data from the system microcontroller during initialization if the NVM is not used. The EDID is reflected on the four HDMI ports through the DDC bus.

Flexibility allows mixing different EDID formats in an application. This feature can eliminate up to four EDID

ROMs while also saving board space.

Flexible power management provides extremely low standby power consumption; standby power can be supplied from an HDMI 5 V signal or from a separate standby power pin. If the NVM stores the EDID, only the 5 V power from the source device is needed to read the EDID.

1.1. Inputs

Four HDMI/DVI-compatible ports

TMDS™ core runs at 25 MHz – 225 MHz

1.2. Digital Video Output

 xvYCC to extended RGB

36-bit RGB / YCbCr 4:4:4

16/20/24-bit YCbCr 4:2:2

8/10/12-bit YCbCr 4:2:2 (ITU BT.656)

True 12-bit accurate output data using an internal14-bit wide processing path

Programmable drive strength from 2 mA to 14 mA

1.3. Digital Audio Interface

DTS-HD and Dolby

®

TrueHD high bit rate audio

I

2

S output with 4 data signals for multi-channel formats and flexible, programmable channel mapping

S/PDIF output supports PCM, Dolby

®

Digital, DTS digital audio transmission with a 32 kHz – 192 kHz

Fs sample rate

Intelligent audio mute capability avoids pops and noise with automatic soft mute and unmute

IEC60958 or IEC61937 compatible

1.4. Control

Consumer Electronics Control (CEC) interface incorporates an HDMI CEC I/O and an integrated

CEC Programming Interface (CPI)

Automatic Feature Abort response for unsupported commands and automatic message retry on transmit

1.5. Package

20 mm × 20 mm 144-pin TQFP package with exposed pad (ePad)

Figure 1.1. Typical Application

6

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

2. System Applications

The SiI9233A receiver device is designed for digital televisions that require support for HDMI Deep Color. The device allows receipt of 10/12-bit color depth up to 1080p resolutions. A single receiver provides four HDMI input ports. The video output interfaces to a video processor and the audio output can interface directly to an audio DAC or an audio

DSP for further processing as shown in Figure 1.1

on the previous page.

3. Comparing Features of Lattice Semiconductor Receiver

Devices

Table 3.1

compares the features of the SiI9127A, SiI9125, SiI9135A, SiI9223A, and SiI9233A receiver devices.

Table 3.1. Comparison of Lattice Semiconductor Receiver Devices

Feature

HDMI Input Connections

TMDS Input Ports

Color Depth

DDC Input Ports

Maximum TMDS Input Clock

SiI9125

2

2

SiI9127A

2

2

Video Output

Digital Video Output Ports

Maximum Output Pixel Clock

Maximum Output Bus Width

Audio Formats

S/PDIF Output Ports

I

2

S Output

DSD Output

High Bit Rate Audio Support

Compressed DTS-HD and Dolby True-

HD

Maximum Audio Sample Rate (Fs)

Video Processing

Color Space Converter

1

36

1

2 channel

2 channel

No

RGB to/from

YCbCr

1

36

1

2 channel

NA

No

RGB to/from YCbCr xvYCC to RGB

SiI9135A

2

8/10/12-bit

2

225 MHz

1

165 MHz

36

1

8 channel

6 channel

Yes

192 kHz

RGB to/from

YCbCr

SiI9223A

4

4

1

36

1

2 channel

NA

No

RGB to/from YCbCr xvYCC to RGB

SiI9233A

4

4

1

36

1

8 channel

8 channel

Yes

RGB to/from

YCbCr xvYCC to RGB

Pixel Clock Divider

Digital Video Bus Mapping

Other Features

Local fixed I

2

C Device Address

1

Programmable I

2

C Device Address

1

NA 0x64, 0xC0, 0xE0

÷ 4, ÷ 2

Swap Cb, Cr pins

0x60/0x68 or 0x62/0x6A

NA 0x64, 0xC0, 0xE0 0x64, 0xC0, 0xE0

Reserved I

2

C Device Address

2

NA 0x90, 0xD0, 0xE6 NA 0x90, 0xD0, 0xE6 0x90, 0xD0, 0xE6

3D Support

CEC

EDID

HDCP Repeater Support

Interlaced Format Detection Pin

Package

No

No

No

No

Yes

144-pin TQFP ePad

Yes

Yes

NVRAM

No

Yes

128-pin TQFP ePad

No

No

No

Yes

Yes

144-pin TQFP ePad

Yes

Yes

NVRAM

No

Yes

144-pin TQFP ePad

Yes

Yes

NVRAM

Yes

Yes

144-pin TQFP ePad

Notes:

1. Refer to the SiI9223A/9233A/9127A HDMI Receivers Programmer Reference for a description of these I

2

C register addresses.

2. These are reserved I

2

C register addresses which are within the I

2

C register address map of the chip. Do not access these registers on the chip, and do not use these addresses for other devices in the system which use the same I

2

C bus.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 7

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

4. Functional Description

The SiI9233A receiver provides a complete solution for receiving HDMI digital audio and video. Specialized audio and video processing is available within the receiver to add HDMI capability to consumer electronics such as DTVs.

Figure 4.1

is a block diagram showing the SiI9233A receiver device incorporated into an AV receiver. Figure 4.2

on the

next page shows the functional blocks of the chip. The receiver supports four HDMI input ports. Only one port can be active at any time.

HDMI Port 3

Connector

CEC

R3PWR5V

TMDS3

DDC3

HPD3

HDMI Port 2

Connector

CEC

R2PWR5V

TMDS 2

DDC 2

HDMI Port 1

Connector

CEC

HPD 2

R1PWR5V

TMDS 1

DDC1

SiI9233A

Receiver

Digital Video

Video

Processor

SiI9134

Transmitter

MCLK

SPDIF

I

2

S/

DSD

CEC

HPD1

I

2

C

HDMI Port 0

Connector

CEC

R0PWR5V

TMDS0

DDC0

HPD0

Microcontroller

Audio DSP

Other Audio Sources

Figure 4.1. A/V Receiver Block Diagram

I 2 S

Audio

DAC

Speakers

4.1. TMDS Digital Cores

The TMDS Digital core can receive TMDS data at up to 225 MHz. Each core performs 10-to-8-bit TMDS decoding on the video data and 10-to-4 bit TMDS decoding on the audio data received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the receiver device into power-down mode.

4.2. Active Port Detection and Selection

Only one port can be active at a time, under control of the receiver firmware. Active TMDS signaling can arrive at any port, but only one has internal circuitry enabled. The firmware in the display controls these states using register settings.

Other control signals are associated with the TMDS signals on each HDMI port.

The receiver can monitor the +5 V supply from each attached host. The firmware can poll registers to check on which ports are connected. The firmware also controls functional connection to one of the four Extended DDC (E-DDC) buses, enabling one while disabling the others. An attached host determines the active status of an attached HDMI device by

8

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

polling the E-DDC bus to the device. See the Programmer Reference (see the

References section on page 72) for a

description of port detection and selection. The Programmer Reference requires an NDA with Lattice Semiconductor.

CEC_A

DSDA0

DSDA1

DSDA2

DSDA3

DSCL0

DSCL1

DSCL2

DSCL3

Serial

Host

Interface

(DDC)

CEC

HDCP

Registers

SRAM

EDID

NVRAM

CSDA

CSCL

CI2CA

Serial

Host

Interface

(local)

RPI

Registers and State

Machine

Configuration and Status

Registers

R2XC+

R2XC-

R2X0+

R2X0-

R2X1+

R2X1-

R2X2+

R2X2-

R3XC+

R3XC-

R3X0+

R3X0-

R3X1+

R3X1-

R3X2+

R3X2-

R0XC+

R0XC-

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R1XC+

R1XC-

R1X0+

R1X0-

R1X1+

R1X1-

R1X2+

R1X2-

HDMI

Receiver

Mux

SCDT

Logic

A/V Split

Video

HDCP

Unmask

HDMI

Decode

Audio

HDCP

Unmask

HDCP

Engine

Embedded

HDCP Keys

Hot Plug

Controller

Video Processing

Deep

Color

Color

Space

Converter

Up/Down

Sampling

Auto Video Configuration

Audio Clock

Regeneration

APLL

Auto

Audio

Video

Output

Format

Audio Processing

Audio Output

S/PDIF

Output

I

2

S/

DSD

Output

CEC_D

HPD0

HPD1

HPD2

HPD3

INT

ODCK

Q[35:0]

DE

HSYNC

VSYNC

EVNODD

SPDIF

SCK/DCLK

WS

SD[3:0]

DR[3:0]

DR[3:0]

MUTEOUT

XTALIN

XTALOUT

MCLK

SCDT

R0PWR5V

R1PWR5V

R2PWR5V

R3PWR5V

RESET#

Reset

Logic

Figure 4.2. Functional Block Diagram

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 9

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

4.3. HDCP Decryption Engine/XOR Mask

The HDCP decryption engine contains all the necessary logic to decrypt the incoming audio and video data. The decryption process is entirely controlled by the host side microcontroller/microprocessor through a set sequence of register reads and writes through the DDC channel. Pre-programmed HDCP keys and a Key Selection Vector (KSV) stored in the on-chip non-volatile memory are used in the decryption process. A resulting calculated value is applied to an XOR mask during each clock cycle to decrypt the audio/video data.

The SiI9233A receiver also contains all the necessary logic to support full HDCP repeaters. The KSV values of up to 16 downstream devices (up to 16 total) are written to the receiver through the local I

2

C bus (CSDA/CSCL). As defined in the

HDCP specification, Vi is calculated and made available to the host on the DDC bus (DSDA/DSCL).

4.4. HDCP Embedded Keys

The receiver comes pre-programmed with a set of production HDCP keys stored on-chip in non-volatile memory.

System manufacturers do not need to purchase key sets from the Digital-Content LLC. All purchasing, programming, and security for the HDCP keys is handled by Lattice Semiconductor. The pre-programmed HDCP keys provide the highest level of security, as keys cannot be read out of the device after they are programmed. Before receiving samples of the SiI9233A receiver, customers must sign the HDCP license agreement (available from Digital Content Protection,

LLC) or a special NDA with Lattice Semiconductor.

4.5. Data Input and Conversion

4.5.1. Mode Control Logic

The mode control logic determines if the decrypted data is video, audio, or auxiliary information and directs it to the appropriate logic block.

4.5.2. Video Data Conversion and Video Output

The SiI9233A receiver can output video in many different formats (see examples in Table 4.1

) and can process the video

data before it is sent, as shown in Figure 4.3 on page 13. It is possible to bypass each of the processing blocks by setting

the appropriate register bits.

Table 4.1. Digital Video Output Formats

Color

Space

Video

Format

Bus

Width

HSYNC/

VSYNC

RGB

YCbCr

4:4:4

4:4:4

36

30

Separate

Separate

24 Separate

12/15/18 Separate

36

30

Separate

Separate

24 Separate

12/15/18 Separate

4:2:2 16/20/24 Separate

16/20/24 Embedded

8/10/12 Separate

8/10/12 Embedded

Output Clock (MHz)

480i/576i

2,

3

480p XGA 720p 1080i SXGA 1080p UXGA

27

27

27

27

65

65

74.25

74.25

74.25

74.25

108

108

148.5

148.5

162

162

27

27

27

27

27

27

27

27

65

65

65

65

74.25

74.25

74.25

74.25

74.25

74.25

74.25

74.25

108

148.5

162

108 148.5 162

108 148.5 162

27

27

27

27

27

27

27

27

27

27

54

54

65

65

74.25

74.25

74.25

74.25

148.5

148.5

74.25

74.25

74.25

74.25

148.5

148.5

108 148.5 162

148.5

148.5

162

162

Notes

:

1. Embedded syncs use SAV/EAV coding.

2. 480i and 576i modes can output a 13.25 MHz clock using the internal clock divider.

3. Output clock frequency depends on programming of internal registers. Differential TMDS clock is always 25 MHz or faster.

4. Output clock supports 12/15/18-bit mode by using both edges.

Notes

4

1

1

4

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

4.5.2.1. Color Range Scaling

The color range depends on the video format, according to the CEA-861D specification. In some applications the 8-bit input range uses the entire span of 0x00 (0) to 0xFF (255) values. In other applications the range is scaled narrower.

The receiver cannot detect the incoming video data range and there is no required range specification in the HDMI AVI packet. The device chooses scaling depending on the detected video format. 10 and 12-bit color range scaling are both handled the same way. Refer to the Programmer Reference for more details.

When the receiver outputs embedded syncs (SAV/EAV codes), it also limits the YCbCr data output values to 1 to 254.

4.5.2.2. Up Sample / Down Sample

Additional logic can convert from 4:2:2 to 4:4:4 (8/10/12-bit) or from 4:4:4 (8/10/12-bit) to 4:2:2 YCbCr format. All processing is done with 14 bits of accuracy for true 12-bit data.

4.5.3. Deep Color Support

The SiI9233A device supports color depth modes greater than 24 bits, known as Deep Color modes, introduced in the

HDMI v1.3 Specification. The Deep Color modes employ a new pixel packing scheme to enable the extra bits of higher color depth data to be carried over the existing TMDS data encoding scheme. Currently, three Deep Color modes are defined: 30-bit, 36-bit and 48-bit. The SiI9233A receiver supports two of these three Deep Color modes: 30 and 36-bit modes. In addition, each Deep Color mode is supported to 1080p HD format.

For Deep Color modes, the TMDS clock is run faster than the pixel clock in order to create extra bandwidth for the additional bits of the higher color depth data. The increase in the TMDS clock is by the ratio of the pixel size to 24 bits, as follows:

30-bit mode: TMDS clock = 1.25x pixel clock (5:4)

36-bit mode: TMDS clock = 1.5x pixel clock (3:2)

Because the receiver supports 36-bit mode at 1080p, the highest TMDS clock rate it supports is 225 MHz. When in

Deep Color mode, the transmitter periodically sends a General Control Packet with the current color depth and pixel packing phase information to the receiver. The receiver captures the color depth information in a register, which the firmware can then use to set the appropriate clock divider to recover the pixel clock and data.

4.5.4. xvYCC Support

The SiI9233A receiver adds support for the extended gamut xvYCC color space; this extended format has roughly 1.8 times more colors than the RGB color space. The use of the xvYCC color space is made possible because of the availability of LED and laser-based light sources for the next generation displays. This format also makes use of the full range of values (1 to 254) in an 8-bit space instead of 16 to 235 in the RGB format. The use of xvYCC along with Deep

Color helps in reducing color banding and allows the display of a larger range of colors than is currently possible.

4.5.4.1. Color Space Conversion

Color space converter (CSC) blocks are provided to convert RGB data to Standard-Definition (ITU.601) or High-

Definition (ITU.709) YCbCr formats, and vice-versa. To support the latest extended-gamut xvYCC displays, the Sil9233 device implements color space converter blocks to convert RGB data to extended-gamut Standard-Definition (ITU.601) or High-Definition (ITU.709) xvYCC formats, and vice-versa.

RGB to YCbCr

The RGB

YCbCr color space converter (CSC) can convert from video data RGB to standard definition

(ITU.601) or to high definition (ITU.709) YCbCr formats. The HDMI AVI packet defines the color space of the incoming video.

YCbCr to RGB The YCbCr

RGB color space converter is available to interface to MPEG decoders with RGB-only inputs. The CSC can convert from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 11

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

4.6. 3D Video Formats

The SiI9233A receiver has support for the 3D video modes described in the HDMI 1.4 Specification. All modes support RGB

4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formats and 8-, 10-, and 12-bit data width per color component. Table 4.2

shows

only the maximum possible resolution with a given frame rate; for example, Side-by-Side (Half) mode is defined for

1080p60, which implies that 720p60 and 480p60 are also supported. Furthermore, a frame rate of 24 Hz also means that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also means a frame rate of 59.94 Hz is supported. The input pixel clock changes accordingly.

When using Side-by-Side formats the use of 4:2:2 to 4:4:4 up-sampling and 4:4:4 to 4:2:2 down-sampling should not be enabled as it may result in visible artifacts.

Video processing should be bypassed in the case of L + depth format.

Table 4.2. Supported 3D Video Formats

3D Format Extended Definition Input Pixel Clock (MHz)

Frame Packing

L + depth

Side-by-Side

— interlaced

— full half

Resolution

1080p

720p

1080i

1080p

720p

1080p

720p

1080p

1080i

Frame Rate (Hz)

24

50 / 60

50 / 60

24

50 / 60

24

50 / 60

50 / 60

50 / 60

148.5

74.25

4.6.1. Default Video Configuration

After hardware RESET, the SiI9233A chip is configured in its default mode. This mode is summarized in Table 4.3

. For

more details and for a complete register listing, refer to the Programmer Reference. The Programmer Reference

requires an NDA with Lattice Semiconductor.

Table 4.3. Default Video Processing

Video Control

HDCP Decryption

Color Space Conversion

Color Space Selection

Color Range Scaling

Upsampling/Downsampling

HSYNC & VSYNC Timing

Data Bit Width

Pixel Clock Replication

Power Down

Default after Hardware Reset

HDCP decryption is OFF

No color space conversion

BT.601 selected

No range scaling

No upsampling or downsampling

No inversions of HSYNC or VSYNC

Uses 8-bit data

No pixel clock replication

Everything is powered down

Note: The receiver device assumes DVI mode after reset, which is RGB 24-bit 4:4:4 video with 0–255 range.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

12 SiI-DS-1061-C

TMDS HDCP

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Widen to

14-Bits

RGB to

YCbCr bypass

YCbCr

Range

Reduce bypass

Down

Sample

4:4:4 to

4:2:2 bypass

Upsample

4:2:2 to

4:4:4 bypass xvYCC/

YCbCr to

RGB bypass

RGB

Range

Expand bypass

Dither

Module

Mux

656

Video

Timing

DE

HSYNC

VSYNC

ODCK

Q[35:0]

Figure 4.3. Default Video Processing Path

4.6.2. Automatic Video Configuration

The SiI9233A receiver adds automatic video configuration to simplify the firmware’s task of updating the video path whenever the incoming video changes format. Bits in the HDMI Auxiliary Video Information (AVI) InfoFrame are used to reprogram the registers in the video path.

Table 4.4. AVI InfoFrame Video Path Details

AVI Byte 1 Bits [6:5]

Y[1:0]

00

01

10

11

Color Space

RGB 4:4:4

YCbCr 4:2:2

YCbCr 4:4:4

Future

AVI Byte 2 Bits [7:6]

C[1:0]

00

01

10

11

Colorimetric

No Data

ITU 601

ITU 709

Extended Colorimetry

Information Valid

Notes on Table 4.4:

1. The Auto Video Configuration assumes that the AVI information is accurate. If information is not available, then the receiver must choose the video path based on measurement of the incoming resolution.

2. Refer to EIA/CEA-861D Specification for details.

3. The SiI9233A device can support only pixel replication modes 0b0000, 0b0001, and 0b0011. Other modes are unsupported and can result in unpredictable behavior.

AVI Byte 5 Bits [3:0]

PR[3:0] Pixel Repetition

0000

0001

0010

0011

No repetition

Pixel sent 2 times

Pixel sent 3 times

Pixel sent 4 times

0100

0101

0110

0111

1000

1001

Pixel sent 5 times

Pixel sent 6 times

Pixel sent 7 times

Pixel sent 8 times

Pixel sent 9 times

Pixel sent 10 times

The format of the digital video output bus can be automatically configured to many different formats by programming the Auto Output Format Register. The available formats are listed in the table below. For detailed definitions of how to set this register, refer to the Programmer Reference.

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SiI-DS-1061-C 13

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Table 4.5. Digital Output Formats Configurable through Auto Output Format Register

Digital Output Formats

Color Width

RGB

YCbCr

4:4:4

4:4:4

YCbCr

YCbCr

YCbCr

4:2:2

4:2:2

4:2:2

MUX

N

N

N

Y

Y

Sync

Separate

Separate

Separate

Separate

Embedded

4.7. Audio Data Output Logic

The SiI9233A receiver can send digital audio over S/PDIF, four I

2

S outputs, or eight one-bit audio outputs.

4.7.1. S/PDIF

The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for multichannel (IEC 61937) formats. The audio data output logic forms the audio data output stream from the HDMI audio packets. The S/PDIF output supports audio sampling rates from 32 to 192 kHz. A separate master clock output (MCLK), coherent with the S/PDIF output, is provided for time-stamping purposes. Coherent means that the MCLK and S/PDIF are created from the same clock source.

4.7.2. I2S

The I

2

S bus format is programmable through registers, to allow interfacing with I inputs. Refer to the Programmer Reference for the different options on the I

2

2

S audio DACs or audio DSPs with I

S bus. Additionally, the MCLK (audio

2

S master clock) frequency is selectable to be an integer multiple of the audio sample rate F s

.

MCLK frequencies support various audio sample rates as shown in Table 4.6

.

Table 4.6. Supported MCLK Frequencies

Audio Sample Rate, Fs : I

2

S and S/PDIF Supported Rates

Multiple of Fs

128

32 kHz

4.096 MHz

44.1 kHz

5.645 MHz

48 kHz

6.144 MHz

88.2 kHz 96 kHz 176.4 kHz 192 kHz

11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz

192 6.144 MHz 8.467 MHz 9.216 MHz 16.934 MHz 18.432 MHz 33.868 MHz 36.864 MHz

256

384

512

8.192 MHz

12.288 MHz

16.384 MHz

11.290 MHz 12.288 MHz 22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz

16.934 MHz 18.432 MHz 33.864 MHz 36.864 MHz

22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz

4.7.3. One-Bit Audio Input (DSD/SACD)

DSD (direct stream digital) is an audio data format defined for SACD (Super Audio CD) applications. It consists of four data outputs for the left channel, four data outputs for the right channel, and a clock for up to 8-channel support. Onebit Audio supports 64 • Fs, with Fs being either 44.1 kHz or 88.2 kHz.

The one bit audio outputs are synchronous to the positive edge of the DSD Clock. For one bit audio, the sampling information is carried in the Audio InfoFrame, instead of the Channel Status bits.

4.7.4. High-Bitrate Audio on HDMI

The new high-bitrate compressed standards such as DTS-HD and Dolby TrueHD transmit data at bitrates as high as 18 to 24 Mbps. Because these bitrates are so high, DVD decoders and HDMI transmitters (as source devices), and DSP and

HDMI receivers (as sink devices) must carry the data using four I

2

S lines rather than using a single very-high-speed

S/PDIF or I

2

S bus (see Figure 4.4 on the next page).

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

14 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Four I

2

S

Data Lines

Four I

2

S

Data Lines

MPEG Tx Rx DSP

Figure 4.4. High Speed Data Transmission

The high-bitrate audio stream is originally encoded as a single stream. To send it over four I

2

S lines, the DVD decoder needs to split this single stream into four streams. Because the single stream of data is being sent over four lines, the programmable ACR (Audio Clock Regeneration) rate is now four times the sample rate of 96 kHz (384 kHz), or 192 kHz

(768 kHz).

Figure 4.5

shows the high-bitrate stream before it has been split into four I

2

S lines, and after it has been reassembled.

0 1 2 3 4 5

……….

N-1

N

16-Bit

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Figure 4.5. High-Bitrate Stream Before and After Reassembly and Splitting

Figure 4.6

shows the same high-bitrate audio stream after being split into four I

2

S lines:

WS

Left Right Left Right

SD0

SD1

SD2

SD3

Sample 0

Sample 2

Sample 4

Sample 1 Sample 8 Sample 9

Sample 3

Sample 10

Sample 11

Sample 5 Sample 12 Sample 13

Sample 6 Sample 7 Sample 14 Sample 15

Figure 4.6. High-Bitrate Stream After Splitting

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SiI-DS-1061-C 15

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Table 4.7. Maximum Audio Sampling Frequency for All Video Format Timings

Max fs

8 ch (kHz)

Description

Format

Timing

Pixel

Repetition

Vertical Freq.

(Hz)

4:2:2 and 4:4:4

24-bit

4:4:4 Deep Color

(depth in bits)

576i

576i

288p

288p

576p

576p

576p

720p/50

1080i/50

1080p/50

VGA

480i

480i

240p

240p

480p

480p

480p

720p

1080i

1080p

1080p

1080p

1080p

60 Hz Formats

640x480p none

1440x480i

2880x480i

1440x240p

2880x240p

2

4

2

4

720x480p

1440x480p

2880x480p

1280x720p

1920x1080i none

2

4 none none

1920x1080p none

50 Hz Formats

1440x576i

2880x576i

2

4

1440x288p

2880x288p

720x576p

1440x576p

2

4 none

2

2880x576p

1280x720p

1920x1080i

1920x1080p

4 none none none

1080p @ 24 Hz – 30 Hz

1920x1080p

1920x1080p

1920x1080p none none none

50

50

50

50

50

50

50

50

50

50

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

59.94/60

24

25

29.97/30

48

192

48

96

192

192

192

192

Standard

192

192

192

Standard

48

48

192

48

192

48

96

192

192

192

192

Standard

48

192

48

192

48

96

192

192

192

192

10

192

192

192

48

96

192

192

192

192

10

48

192

10

48

48

192

48

192

48

192

48

96

192

192

192

192

12

192

192

192

48

96

192

192

192

192

12

48

192

12

48

48

192

48

192

Max fs

2 ch (kHz)

4.7.5. Auto Audio Configuration

The SiI9233A receiver can control the audio output based on the current states of CablePlug, FIFO, Video, ECC, ACR,

PLL, InfoFrame, and HDMI. Audio output is enabled only when all necessary conditions are met. If any critical condition is missing, then the audio output is disabled automatically.

4.7.6. Soft Mute

On command from a register bit or when automatically triggered with Automatic Audio Control (AAC), the receiver progressively reduces the audio data amplitude to mute the sound in a controlled manner. This feature is useful when there is an interruption to the HDMI audio stream (or an error) to prevent any audio pop from being sent to the I

2

S or

S/PDIF outputs.

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

192

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

16 SiI-DS-1061-C

4.8. Control and Configuration

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

4.8.1. Register/Configuration Logic

The register/configuration logic block incorporates all the registers required for configuring and managing the features of the SiI9233A receiver. These registers are used to perform HDCP authentication, audio/video/auxiliary format processing, CEA-861B InfoFrame Packet format, and power-down control.

The registers are accessible from one of two serial ports. The first port is the DDC port, which is connected through the

HDMI cable to the HDMI host. It is used to control the SiI9233A receiver from the host system for HDCP operation. The second port is the local I

2

C port, which is used to control the SiI9233A device from the display system. This is shown in

Figure 4.7

. The Local Bus accesses the General Registers and the Common Registers. The DDC Bus accesses the HDCP

Operation registers and the Common Registers.

Accessible from DDC

I

2

C Bus

HDCP

Operation

Common

Registers

General

Registers

Video

Processing

Audio

Processing

InfoFrames

Repeater

Interrupts

Accessible from Local

I

2

C Bus

Figure 4.7. I

2

C Register Domains

4.8.2. I

2

C Serial Ports

The SiI9233A receiver provides 5 I

2

C serial interfaces: 4 DDC ports to communicate back to the HDMI or DVI hosts; one

I

2

C port for initialization and control by a local microcontroller in the display. Each interface is 5 V tolerant.

4.8.2.1. E-DDC Bus Interface to HDMI Host

The four DDC interfaces (DSDA0-3 and DSCL0-3) on the receiver are slave interfaces that can run up to 100 kHz. Each interface is connected to one E-DDC bus and is used for reading the integrated EDID in addition to HDCP authentication.

The SiI9233A receiver is accessible on the E-DDC bus at device addresses 0xA0 for the EDID, and 0x74 for HDCP control.

This feature is compliant with the HDCP 1.3 Specification.

4.8.3. EDID FLASH and RAM Block

The EDID block consists of 1024 bytes of RAM. Each port has a block of 256 bytes of RAM for EDID data. This feature allows simultaneous reads of all ports from four different source devices that are connected to the SiI9233A device. In addition to the RAM, the EDID block contains 256 bytes of FLASH that is shared by all ports. As a result, the timing information must be identical among all the ports if the internal EDID is used. An additional area of FLASH contains unique CEC physical address and checksum values for each of the four ports. This feature allows simultaneous reads of all ports from four different source devices if they are connected and attempt an EDID read at the same time. If independent EDIDs are required on any of the ports, a CPU can externally load the 256 bytes of RAM for that port, by using the local I

2

C bus.

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SiI-DS-1061-C 17

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

The internal EDID can be selected on a per-port basis using registers on the local I

2

C bus. For example, Port 0 and Port 1 can use the internal EDID, and Port 2 and Port 3 can use a discrete EEPROM for the EDID.

4.8.4. CEC Interface

The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the

LVTTL signals of an external microcontroller (CEC host-side or transmit-side) to CEC signaling levels for CEC devices at the receive-side, and vice versa.

Additionally, a CEC controller compatible with the Lattice Semiconductor CEC Programming Interface (CPI) is included on-chip. This CEC controller has a high-level register interface accessible through the I

2

C interface which can be used to send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the burden of having a host CPU perform these low-level transactions on the CEC bus.

4.8.4.1. I

2

C Interface to Display Controller

The Controller I

2

C interface (CSDA, CSCL) on the SiI9233A receiver is a slave interface capable of running up to 400 kHz.

This bus is used to configure the chip by reading/writing to the appropriate registers. It is accessible on the local I

2

C bus at two device addresses. Refer to the Programmer Reference for more information. The Programmer Reference

requires an NDA with Lattice Semiconductor.

4.8.5. Standby and HDMI Port Power Supplies

The receiver device incorporates a power island that continues to supply power to the EDID memory, the DDC ports, and the CEC bus when power is removed from the VCC pins, as long as power continues to be provided through at least

one connected HDMI cable or by system standby power. Refer to Figure 4.8

. The internal power multiplexer selects

power from either SBVCC5 (if it available) or from one of the RnPWR5V pins.

The power island results in an extremely low power standby mode, but allows the EDID to be readable and the CEC controller to be functional. No damage will occur to the device when in this mode.

System Main 5 V

System Standby 5 V

HDMI Port

Regulator

RnRPWR5V SBVCC5

+3.3 V +1.2 V

Power MUX

On-Chip Regulator

+3.3 V

On-Chip Regulator

+3.3 V

+1.2 V

DDC

I

2

C

Logic

Power-On

Reset

EDID

RAM

CEC Logic

NV

Memory

OTP

ROM

Power Island

Figure 4.8. Power Island

Main Chip Logic

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

18 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5. Electrical Specifications

5.1. Absolute Maximum Conditions

Table 5.1. Absolute Maximum Conditions

Symbol

IOVCC33

AVCC12

AVCC33

APVCC12

CVCC12

XTALVCC33

SBVCC5

Parameter

I/O Pin Supply Voltage

TMDS Analog Supply Voltage

TMDS Analog Supply Voltage

Audio PLL Supply Voltage

Digital Core Supply Voltage

ACR PLL Crystal Oscillator Supply Voltage

Standby Supply Voltage

Min

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

Typ

Max

4.0

1.9

4.0

1.9

1.9

4.0

5.7

Units

V

V

V

V

V

V

V

Note

1, 2, 3

V

I

V

T

J

5V-Tolerant

Input Voltage

Input Voltage on 5 V tolerant Pins

Junction Temperature

Storage Temperature

–0.3

–0.3

IOVCC33 + 0.3

5.5

125

V

V

C

C

1, 2

5

T

STG

–65 — 150 —

Notes:

1. Permanent device damage can occur if absolute maximum conditions are exceeded.

2. Functional operation should be restricted to the conditions described under Normal Operating Conditions on the next page.

3. Voltage undershoot or overshoot cannot exceed absolute maximum conditions.

4. Refer to the SiI9233A Qualification Report for information on ESD performance.

5. All VCCs must be powered to the device. If the device is unpowered and 5 V is applied to these inputs, damage can occur.

1, 2

1, 2

1, 2

1, 2

1, 2

1, 2

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 19

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.2. Normal Operating Conditions

Table 5.2. Normal Operating Conditions

Symbol

IOVCC33

AVCC12

AVCC33

APVCC12

CVCC12

XTALVCC33

SBVCC5

RnPWR5V

Parameter

I/O Pin Supply Voltage

TMDS Analog Supply Voltage

TMDS Analog Supply Voltage

Audio PLL Supply Voltage

Digital Core Supply Voltage

ACR PLL Crystal Oscillator Supply Voltage

Standby Supply Voltage

DDC I

2

C I/O Reference Voltage

Min

3.13

1.14

3.13

1.14

1.14

3.13

4.75

4.7

Typ

3.3

1.2

3.3

1.2

1.2

3.3

5.0

5.0

Max

3.47

1.26

3.47

1.26

1.26

3.47

5.25

5.3

Units

V

V

V

V

V

V

V

V

DIFF33

DIFF12

Difference between two 3.3 V Power Pins

Difference between two 1.2 V Power Pins

1.0

1.0

V

V

4

4

DIFF3312

V

CCN

T

A

 ja

Difference between any 3.3 V and 1.2 V Pin

Supply Voltage Noise

Ambient Temperature (with power applied)

Ambient Thermal Resistance (Theta JA)

–1.0

0

25

2.6

100

70

27 mV

P-P

V

C

C/W

4, 5

7

Notes:

1. IOVCC33 and AVCC33 pins should be controlled from one power source.

2. CVCC12 should be controlled from one power source.

3. AVCC12 pin should be regulated.

4. Power supply sequencing must guarantee that power pins stay within these limits of each other; see Figure 6.2 on page 28.

5. No 1.2 V pin can be more than DIFF3312[min] higher than any 3.3 V pin. No 3.3 V pin can be more than DIFF3312[max] higher than any 1.2 V pin.

6. The HDMI Specification requires termination voltage (AVCC33) to be controlled to 3.3 V ±5%. The SiI9233A receiver tolerates a wider range of ±300 mV.

7. The supply voltage noise is measured at test point VCCTP in Figure 5.1

. The ferrite bead provides filtering of power supply noise.

The figure is representative and applies to other VCC pins as well.

8. Airflow at 0 m/s.

9.

Figure 9.4

on page 64 and Figure 9.5

on page 65 show decoupling and power supply regulation.

10. SBVCC5V should provide a stable 5 V before any other VCC is applied to the device; see the Power-on Sequencing section on page 60.

11. Maximum current draw from this source is 50 mA. There is no power-on sequence requirement for this source.

Note

1, 4

1, 6

3

2

4

10

11

VCCTP

Parasitic

Resistor

0.56

0.1

F

Ferrite

0. 82

H,

150 mA

+

10

F

0.1

F 1 nF

AVCC12

SiI9233A

GND

Figure 5.1. Test Point VCCTP for VCC Noise Tolerance Spec

Notes:

1. The Ferrite (0.82

H, 150 mA) attenuates the PLL power supply noise at 10 kHz and above.

2. The optional parasitic resistor minimizes the peaking. The typical value used here is 0.56

. 1

is the maximum.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

20 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.3. DC Specifications

Table 5.3. Digital I/O Specifications

Symbol

V

V

V

V

IH

IL

TH+

TH-

DDC V

DDC V

Local I

2

TH+

TH-

C V

TH+

Parameter

HIGH-level Input Voltage

LOW-level Input Voltage

LOW to HIGH Threshold

RESET # Pin

HIGH to LOW Threshold

RESET# Pin

LOW to HIGH Threshold

DSDA0, DSDA1, DSCL0 and

DSCL1 pins.

HIGH to LOW Threshold

DSDA0, DSDA1, DSCL0 and

DSCL1 pins.

LOW to HIGH Threshold

CSCL and CSDA pins

Pin Type

LVTTL

LVTTL

Schmitt

Schmitt

Schmitt

Schmitt

Schmitt

3

Conditions

2

Min

2.0

1.46

3.0

2.1

Typ

Max

0.8

0.96

1.5

Units

V

V

V

V

V

V

V

Note

5

5

11, 13

Local I

V

OH

V

OL

I

OL

V

ID

2

C V

TH-

HIGH to LOW Threshold

CSCL and CSDA pins

HIGH-level Output Voltage

LOW-level Output Voltage

Output Leakage Current

Differential Input Voltage

Schmitt

LVTTL

LVTTL

High Impedance

2.4

–10

75

250

0.86

0.4

10

780

V

V

V

A mV

11, 13

10

10

4

I

I

OD4

I

OD8

I

OD12

R

PD

OPD

4 mA Digital Output Drive

8 mA Digital Output Drive

12 mA Digital Output Drive

Internal Pull Down Resistor

Output Pull Down Current

Output

Output

Output

Outputs

Outputs

V

OUT

= 2.4 V

V

OUT

= 0.4 V

V

OUT

= 2.4 V

V

OUT

= 0.4 V

V

OUT

= 2.4 V

V

OUT

= 0.4 V

IOVCC33 = 3.3 V

IOVCC33 = 3.6 V

4

4

8

8

12

12

25

50

60

110

90 mA mA mA mA mA mA kΩ

A

A

1, 6, 7

1, 6, 7

1, 6, 8

1, 6, 8

1, 6, 9

1, 6, 9

1, 12

1, 12

I

IPD

Input Pull Down Current Input IOVCC33 = 3.6 V — 60 90 1

Notes:

1. These limits are guaranteed by design.

2. Under normal operating conditions unless otherwise specified, including output pin loading C

L

= 10 pF.

3. Refer to the Pin Diagram and Descriptions section beginning on page 34 for pin type designations for all package pins.

4. Differential input voltage is a single-ended measurement, according to DVI Specification.

5. Schmitt trigger input pin thresholds V

TH+

and V

TH-

correspond to V

IH

and V

IL

, respectively.

6. Minimum output drive specified at ambient = 70

C and IOVCC33 = 3.0 V. Typical output drive specified at ambient = 25

C and

IOVCC33 = 3.3 V. Maximum output drive specified at ambient = 0

C and IOVCC33 = 3.6 V.

7. I

OD4

Output applies to pins SPDIF, SCK, WS, SD[3:0], DCLK, INT, and CSDA.

8. I

OD8

Output applies to pins DE, HSYNC, VSYNC, Q[35:0].and MCLK.

9. I

OD12

Output applies to pin ODCK.

10. Note that the SPDIF output drives LVTTL levels, not the low-swing levels defined by IEC958.

11. The SCL and SDA pins are not true open-drain buffers. When no VCC is applied to the chip, these pins can continue to draw a small current, and prevent the master IC from communicating with other devices on the I

2

C bus. Therefore, do not power-down the receiver (remove VCC) unless the attached I

2

C bus is completely idle.

12. The chip includes an internal pull-down resistor on many of the output pins. When in the high-impedance state, these pins draw a pull down current according to this specification when the signal is driven HIGH by another source device.

13. With –10% IOVCC33 supply, the HIGH-to-LOW threshold on DDC and I

2

C bus is marginal. A –5% tolerance on the IOVCC33 power supply is recommended.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 21

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.3.1. DC Power Supply Pin Specifications

Table 5.4. Total Power versus Power-Down Modes

Symbol Parameter

I

PDQ3

Mode Frequency

A —

Typ

3

Max

4

3.3 V 1.2 V SBVCC5 3.3 V 1.2 V SBVCC5

63 3 8

I

PDS

Complete

Power-Down

Current

Sleep Powerdown Current

B 27 MHz

74.25 MHz

67

90

21

25

8

8

Units Notes

mA 1, 6

150 MHz

225 MHz

27 MHz

74

74

0

25

25

0

8

8

8 mA mA mA mA mA

2, 7

I

STBY

Standby

Current

C

74.25 MHz

150 MHz

225 MHz

27 MHz 67 112 8

0

0

0

68

0

0

0

147

8

8

8

8 mA mA mA mA

2, 8

I

UNS

Unselected

Current

D

74.25 MHz

150 MHz

225 MHz

27 MHz

70

75

77

98

172

289

310

112

8

8

8

8

72

78

193

302

78 322

115 148

8

8

8

8 mA mA mA mA

2, 8

I

CCTD

Full Power

Digital Out

Current

E

74.25 MHz

150 MHz

167

266

175

289

8

8

179 185

289 296

8

8 mA mA

2, 10

225 MHz 345 313 8 377 319 8 mA

Notes:

1. Power is not related to input TMDS clock (RxC) frequency because the selected TMDS port is powered down.

2. Power is related to input TMDS clock (RxC) frequency at the selected TMDS port. Only one port can be selected.

3. Typical power specifications measured with supplies at typical normal operating conditions; and a video pattern that combines gray scale, checkerboard and text.

4. Maximum power limits measured with supplies at maximum normal operating conditions, minimum normal operating ambient temperature, and a video pattern with single-pixel vertical lines.

5. Registers are always accessible on local I2C (CSDA/CSCL) without active link clock.

6. Power Down Mode A: Minimum power. Everything is powered off. Host sees no termination of TMDS signals on any of the four

TMDS ports. I2C access is still available.

7. Power Down Mode B: Powers down TMDS core. CKDT remains enabled and state can be polled in register. Host device can sense TMDS termination.

8. Power Down Mode C: Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby supply.

9. Power Down Mode D: Monitor SCDT on selected TMDS port with outputs in the high-impedance state. HDCP continues in the selected port, but the output of the receiver can be connected to a shared bus.

10. Digital Functional Mode E: Full Operation on one port with digital outputs

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

22 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Table 5.5. Power-down Mode Definitions

B

C

E

Mode

A Power

Down

Sleep

Mode

Power

Standby

Power

D Unselected

Power

Digital

3.3 V

Supply

ON

ON

OFF

ON

ON

1.2 V

Supply

ON

ON

OFF

ON

ON

SBVCC5

ON

ON

ON

ON

ON

Register Bit States

PDTOT# PD_TMDS# PD_AO# PD_VO#

0 1 1 1

1

1

1

1

0

1

1

1

1

1

0

1

1

1

0

1

Description

Minimum power.

Everything is powered off.

Host sees no termination of TMDS signals on any of the four TMDS ports. I

2

C access is still available.

Powers down TMDS core.

CKDT remains enabled and state can be polled in register. Host device can sense TMDS termination.

Power off to 3.3 V and

1.2 V supplies. Power on to SBVCC5 standby supply.

Monitor SCDT on selected

TMDS port with outputs in the high-impedance state. HDCP continues in the selected port, but the output of the receiver can be connected to a shared bus.

Full operation on one port with digital outputs.

Notes:

1. PD Clks include PD_MCLK#, PD_XTAL#, PD_APLL#, and PD_PCLK# all set to zero.

2. PD Outs include PD_AO#, and PD_VO# all set to zero.

3. Refer to the Programmer Reference for register bit descriptions.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 23

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.4. AC Specifications

Table 5.6. TMDS Input Timings

Symbol

T

T

DPS

CCS

Parameter

Intra-Pair Differential Input Skew

Channel to Channel Differential

Input Skew

Conditions

Min

Typ

Max

T

T

BIT

CIP

Units

ps ns

Figure

Figure 6.1

Notes

2, 4

2, 3

F

RXC

T

T

RXC

IJIT

Differential Input Clock Frequency

Differential Input Clock Period

Differential Input Clock Jitter tolerance (0.3Tbit)

74.25 MHz

25

4.44

225

40

400

MHz ns ps

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

= 10 pF.

2. Guaranteed by design.

3. IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).

4. 1/10 of IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).

5. Jitter defined per HDMI Specification.

6. Jitter measured with Clock Recovery Unit per HDMI Specification. Actual jitter tolerance can be higher depending on the frequency of the jitter.

2, 5, 6

Refer to the Programmer Reference (see the References section on page 72) for more details on controlling timing

modes.

5.4.1. Video Output Timings

Table 5.7. 12/15/18-Bit Data Output Timings

Symbol Parameter

D

LHT

D

HLT

R

CIP

F

CIP

T

DUTY

T

CK2OUT

LOW-to-HIGH Rise Time Transition

HIGH-to-LOW Fall Time Transition

ODCK Cycle Time

ODCK Frequency

ODCK Duty Cycle

ODCK-to-Output Delay

Conditions

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

Min Typ Max Units

— — 1.5 ns

— —

12.12 —

25

40%

0.4

1.5

40

82.5

60%

2.5 ns ns

MHz

R

CIP ns

Figure

Figure 6.4

Figure 6.4

Figure 6.5

Figure 6.5

Figure 6.5

Table 5.8. 16/20/24/30/36-Bit Data Output Timings

Symbol Parameter

D

LHT

D

HLT

LOW-to-HIGH Rise Time Transition

HIGH-to-LOW Fall Time Transition

Conditions

C

L

= 10 pF

C

L

= 10 pF

Min Typ Max Units

— — 1.5 ns

— — 1.5 ns

Figure

Figure 6.4

Figure 6.4

Notes

2

2

R

CIP

ODCK Cycle Time C

L

= 10 pF 6.06 — 40 ns

Figure 6.5

5, 8

F

CIP

T

DUTY

ODCK Frequency

ODCK Duty Cycle

C

C

L

L

= 10 pF

= 10 pF

25

40%

165

60%

MHz

R

CIP

Figure 6.5

5

3

T

CK2OUT

ODCK-to-Output Delay C

L

= 10 pF 0.4 — 2.5 ns

Figure 6.5

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

=10 pF.

2. Rise time and fall time specifications apply to HSYNC, VSYNC, DE, ODCK, EVNODD and Q[35:0].

3. Output clock duty cycle is independent of the differential input clock duty cycle. Duty cycle is a component of output setup and hold times.

4. See Table 6.2

on page 32 for calculation of worst case output setup and hold times.

5. All output timings are defined at the maximum operating ODCK frequency, F

CIP

, unless otherwise specified.

6. F

CIP

can be the same as F

RXC

or one-half of F

RXC

, depending on OCLKDIV setting. F

CIP can also be F

RXC

/1.25 or F

RXC

/1.5 if Deep

Color mode is being transmitted.

7. R

CIP is the inverse of F

CIP

and is not a controlling specification.

8. Output skew specified when ODCK is programmed to divide-by-two mode.

Notes

2

5

3

2

8

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

24 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.4.2. Audio Output Timings

Table 5.9. I

2

S Output Port Timings

Symbol Parameter Conditions Min

T tr

T

HC

SCK Clock Period (TX)

SCK Clock HIGH Time

C

L

= 10 pF

C

L

= 10 pF

1.00

0.35

T

LC

T

SU

T

HD

T

SCKDUTY

T

SCK2SD

SCK Clock LOW Time

Setup Time, SCK to SD/WS

Hold Time, SCK to SD/WS

SCK Duty Cycle

C

C

C

C

L

L

L

L

= 10 pF

= 10 pF

= 10 pF

= 10 pF

0.35

0.4T

TR

0.4T

TR

– 5

– 5

40%

T

AUDDLY

SCK to SD or WS Delay

Audio Pipeline Delay

C

L

= 10 pF

–5

Notes:

1. Refer to Figure 6.6

on page 30. Meets timings in Philips I

2

S Specification.

2. Applies also to SDC-to-WS delay.

Typ Max Units

T

T

T tr tr tr ns ns

40

60%

+5

80

T tr ns

µs

Figure

Figure 6.6

Table 5.10. S/PDIF Output Port Timings

Symbol Parameter Conditions Min Typ Max Units Figure Notes

T

SPCYC

F

SPDIF

T

T

SPDUTY

MCLKCYC

SPDIF Cycle Time

SPDIF Frequency

SPDIF Duty Cycle

MCLK Cycle Time

C

L

= 10 pF

C

L

= 10 pF

C

L

= 10 pF

4

90%

20

1.0

24

110%

250

UI

MHz

UI ns

Figure 6.7

1, 2

3

2, 5

1, 2, 4

F

MCLK

T

MCLKDUTY

T

AUDDLY

MCLK Frequency

MCLK Duty Cycle

Audio Pipeline Delay

C

C

L

L

= 10 pF

= 10 pF

4

40%

40

50

60%

80

T

MHz

MCLKCYC

µs

Figure 6.8

1, 2, 4

2, 4

Notes:

1. Guaranteed by design.

2. Proportional to unit time (UI), according to sample rate.

3. SPDIF is not a true clock, but is generated from the internal 128Fs clock, for Fs from 128 to 512 kHz.

4. MCLK refers to MCLKOUT.

5. Intrinsic jitter on S/PDIF output can limit its use as an S/PDIF transmitter. The S/PDIF intrinsic jitter is approximately 0.1 UI.

Table 5.11. Audio Crystal Timings

Symbol

F

XTAL

Parameter

External Crystal Freq.

Conditions

Min

26

Typ

27

Max

28.5

Units

MHz

Figure

Figure 5.2

Notes

1, 2

Notes

1

1

1

1

1

1

2

3.3 V

18 pF

27MHz

1 M

3

XTALVCC

5

XTALIN

SiI9233A

4

XTALOUT

18 pF

Figure 5.2. Audio Crystal Schematic

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 25

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.4.3. Miscellaneous Timings

Table 5.12. Miscellaneous Timings

Symbol Parameter Conditions Min Typ Max Units Figure Notes

T

I2CDVD

F

DDC

F

I

2

C

SDA Data Valid delay from SCL falling edge

Speed on TMDS DDC Ports

Speed on Local I

2

C Port

T

RESET

RESET# Signal LOW Time for valid reset

T

STARTUP

Startup time from power supplies valid

C

L

C

L

C

L

= 400 pF

= 400 pF

= 400 pF

50

700

100

400

100 ns kHz kHz

µs ms

Figure 6.3

2

3

5

T

BKSVINIT

HDCP BKSV Load Time — — — 2.2 ms — 4

Notes:

1. Under normal operating conditions unless otherwise specified, including output pin loading of C

L

= 10 pF.

2. DDC ports are limited to 100 kHz by the HDMI Specification, and meet I

2

C standard mode timings.

3. Local I

2

C port (CSCL/CSDA) meets standard mode I

2

C timing requirements to 400 kHz.

4. The time required to load the KSV values internal to the receiver after a RESET# and the start of an active TMDS clock. An attached HDCP host device should not attempt to read the receiver BKSV values until after this time. The T

BKSVINIT

Min and Max values are based on the maximum and minimum allowable XCLK frequencies. The loading of the BKSV values requires a valid

XCLK and TMDS clock.

5. T

STARTUP is the startup time required for the device to be operational once power is stable. This startup time is due to the on board voltage regulator for the EDID and CEC and a power on reset circuit.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

26 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

5.4.4. Interrupt Timings

Table 5.13. Interrupt Output Pin Timings

Symbol

T

FSC

Parameter

Link disabled (DE inactive) to SCDT LOW

Conditions Min Typ Max Units

— — 0.15 40 ms

Figure

Figure 5.3

Notes

1, 2, 3, 8

T

HSC

T

CICD

T

CACD

T

INT

T

CIOD

T

CAOD

T

SRRF

Link enabled (DE active) to SCDT HIGH

RXC inactive to CKDT LOW

RXC active to CKDT HIGH

Response Time for INT from Input Change

RXC inactive to ODCK inactive

RXC active to ODCK active and stable

Delay from SCDT rising edge to Software

Reset falling edge

4

100

10

100

100

10

100

DE

µs

µs

µs ns ms ms

Figure 5.3

Figure 5.3

Figure 5.3

Figure 6.3

1, 2, 4, 8

1, 2, 8

1, 2, 8

1, 5, 8

1, 8

1, 6, 8

7

Notes:

1. Guaranteed by design.

2. SCDT and CKDT are register bits in this device.

3. SCDT changes to LOW after DE is HIGH for approximately 4096 pixel clock cycles, or after DE is LOW for approximately

1,000,000 clock cycles. At 27 MHz pixel clock, this delay for DE HIGH is approximately 150 µs, and the delay for DE LOW is approximately 40 ms.

4. SCDT changes to HIGH when clock is active (TCACD) and at least 4 DE edges have been recognized. At 720p, the DE period is 22

µs, so SCDT responds approximately 50 µs after TCACD.

5. The INT pin changes state after a change in input condition when the corresponding interrupt is enabled.

6. Output clock (ODCK) becomes active before it becomes stable. Use the SCDT signal as the indicator of stable video output timings, as this depends on decoding of DE signals with active RXC (see TFSC).

7. Software Reset must be asserted and then de-asserted within the specified maximum time after rising edge of Sync Detect

(SCDT). Access to both SWRST and SCDT can be limited by the speed of the I2C connection.

8. SCDT is HIGH only when CKDT is also HIGH. When the receiver is in a powered-down mode, the INT output pin indicates the current state of SCDT. Thus, a power-down receiver signals a microcontroller connected to the INT pin whenever SCDT changes from LOW to HIGH or HIGH to LOW.

RXC

link clock active link clock inactive link clock active

CKDT

T

CICD

T

CACD

DE

Do not Care

T

FSC

T

HSC

SCDT

Figure 5.3. SCDT and CKDT Timing from DE or RXC Inactive/Active

Notes:

1. The SCDT shown in Figure 5.3

is a register bit. SCDT remains HIGH if DE is stuck in LOW while RXC remains active, but SCDT

changes to LOW if DE is stuck HIGH while RXC remains active.

2. The CKDT shown in Figure 5.3

is a register bit. CKDT changes to LOW whenever RXC stops, and changes to HIGH when RXC

starts. SCDT changes to LOW when CKDT changes to LOW.

3. SCDT changes to LOW when CKDT changes to LOW. SCDT changes to HIGH at T

HSC

after CKDT changes to HIGH.

4. The INT output pin changes state after the SCDT or CKDT register bit is set or cleared if those interrupts are enabled.

Refer to the Programmer Reference for more details on controlling timing modes.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 27

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

6. Timing Diagrams

6.1. TMDS Input Timing Diagrams

RX0

RX1

RX2

T

CCS

V

DIFF

= 0V

Figure 6.1. TMDS Channel-to-Channel Skew Timing

6.2. Power Supply Control Timings

Figure 6.2

illustrates the power supply sequencing.

Power On Sequence maximum 3.3 V excursion

IOVCC33

AVCC33

XTALVCC33

Power Off Sequence

DIFF33 max minimum 3.3 V excursion

DIFF3312 max maximum 3.3 V excursion

IOVCC33

AVCC33

XTALVCC33 minimum 3.3 V excursion

DIFF33 max maximum 1.2 V excursion

AVCC12

CVCC12

AVPCC12 minimum 1.2 V excursion

DIFF12 max

AVCC12

CVCC12

AVPCC12

To ensure proper power-on reset, 5 V should be provided to the SBVCC5 pin before the power-on sequence shown here begins.

minimum 1.2 V excursion

Figure 6.2. Power Supply Sequencing

maximum 1.2 V excursion

DIFF3312 max

DIFF12 max

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

28 SiI-DS-1061-C

6.3. Reset Timings

VCC max

VCC min

VCC

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

RESET#

T

RESET

RESET#

T

RESET

Note that VCC must be stable between its limits for Normal

Operating Conditions for T

RESET

before RESET# is HIGH.

RESET# must be pulled LOW for T

RESET

before accessing registers. This can be done by holding RESET# LOW until T

RESET after stable power (at left); OR by pulling RESET# LOW from a

HIGH state (at right) for at least T

RESET

.

Figure 6.3. RESET# Minimum Timings

6.4. Digital Video Output Timing Diagrams

6.4.1. Output Transition Times

2.0 V 2.0 V

0.8 V 0.8 V

D

LHT

D

HLT

Figure 6.4. Video Digital Output Transition Times

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SiI-DS-1061-C 29

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

6.4.2. Output Clock to Output Data Delay

T

CYC

T

H

T

L

OCKINV = 0

ODCK

OCKINV = 1

ODCK

T

CKO(max)

T

CKO(min)

Q[35:0]

T

CKO(max)

T

CKO(min)

DE

HSYNC

VSYNC

Figure 6.5. Receiver Clock-to-Output Delay and Duty Cycle Limits

6.5. Digital Audio Output Timings

T

TR

T

SCKDUTY

SCK

WS

SD

Data Valid

T

SCK2SD_MAX

T

SU

T

HD

Data Valid

Figure 6.6. I

2

S Output Timings

T

SCK2SD_MIN

Data Valid

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30 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

T

SPCYC

T

SPDUTY

50%

SPDIF

MCLK

T

MCLKDUTY

Figure 6.7. S/PDIF Output Timings

T

MCLKCYC

50% 50%

Figure 6.8. MCLK Timings

6.6. Calculating Setup and Hold Times for Video Bus

6.6.1. 24/30/36-Bit Mode

Output data is clocked out on one rising (or falling) edge of ODCK, and is then captured downstream using the same polarity ODCK edge one clock period later. The setup time of data to ODCK and hold time of ODCK to data are therefore

a function of the worst case ODCK to output delay, as shown in Figure 6.9

. The active rising ODCK edge is shown with

an arrowhead. For OCKINV=1, reverse the logic.

T

CK2OUT

{max} T

SU

T

HD

T

CK2OUT

{min}

ODCK

Longest

Clk-to-Out

Shortest

Clk-to-Out

Q

DE

VSYNC

HSYNC

Data Valid Data Valid

Figure 6.9. 24/30/36-Bit Mode Receiver Output Setup and Hold Times

Table 6.1

on the next page shows minimum calculated setup and hold times for commonly used ODCK frequencies. The

setup and hold times apply to DE, VSYNC, HSYNC and Data output pins, with output load of 10pF. These are approximations. Hold time is not related to ODCK frequency.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 31

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Table 6.1. Calculation of 24/30/36-Bit Output Setup and Hold Times

24/30/36-Bit Mode

Symbol

T

SU

Parameter

Setup Time to ODCK = T

ODCK

– T

CK2OUT

{max} 27 MHz

74.25 MHz

T

ODCK

27 MHz

37.0 ns

13.5 ns

37.0 ns

Min

34.5 ns

11 ns

0.4 ns T

HD

Hold Time from ODCK = T

CK2OUT

{min}

6.6.2. 12/15/18-Bit Dual-Edge Mode

Output data is clocked out on each edge of ODCK (both rising and falling), and is then captured downstream using the

opposite ODCK edge. This is shown in Figure 6.10

. The setup time of data to ODCK is a function of the shortest duty

cycle and the longest ODCK to output delay. The hold time does not depend on duty cycle (since every edge is used), and is a function only of the shortest ODCK to output delay.

T

SU

T

HD

ODCK

T

DUTY

{min}

T

CK2OUT

{max}

T

CK2OUT

{min}

Q

DE

VSYNC

HSYNC

Data Valid Data Valid

Figure 6.10. 12/15/18-Bit Mode Receiver Output Setup and Hold Times

Table 6.2

shows minimum calculated setup and hold times for commonly used ODCK frequencies, up to the maximum

allowed for 12/15/18-bit mode. The setup and hold times apply to DE, VSYNC, HSYNC and Data output pins, with output load of 10 pF. These are approximations. Hold time is not related to ODCK frequency.

Table 6.2. Calculation of 12/15/18-Bit Output Setup and Hold Times

12/15/18-Bit Mode

Symbol

T

SU

Parameter

Setup Time to ODCK

= T

ODCK

• T

DUTY

{min} – T

CK2OUT

{max}

T

HD

Hold Time from ODCK = T

CK2OUT

{min}

T

ODCK

27 MHz

74.25 MHz

27 MHz

37.0 ns

13.5 ns

37.0 ns

Min

12.3 ns

2.9 ns

0.4 ns

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32 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

6.7. Calculating Setup and Hold Times for I

2

S Audio Bus

Valid serial data is available at T sck2sd

after the falling edge of the first SCK cycle, and then captured downstream using the active rising edge of SCK one clock period later. The setup time of data to SCK (T

SU

) and hold time of SCK to data

(T

HD

) are therefore a function of the worst case SCK-to-output data delay (Tsck2sd). Figure 6.6

on page 30 illustrates

this timing relationship. Note that the active SCK edge (rising edge) is shown with an arrowhead. For a falling edge sampling clock, the logic is reversed.

Table 6.3

shows the setup and hold time calculation examples for various audio sample frequencies. The formula used

in these examples also applies when calculating the setup and hold times for other audio sampling frequencies.

Table 6.3. I

2

S Setup and Hold Time Calculations

Symbol

T

T

SU

HD

Parameter

Setup Time, SCK to SD/WS

= T

TR

– ( T

SCKDUTY

_

WORST

+ T

SCK

2

SD

_

MAX

)

= T

TR

– (0.6T

TR

+ 5ns )

= 0.4T

TR

– 5ns

Hold Time, SCK to SD/WS

= ( T

SCKDUTY

_

WORST

– T

SCK

= 0.4T

TR

– 5ns

2

SD

_

MIN

)

FWS (kHz)

32 kHz

44.1 kHz

48 kHz

96 kHz

192 kHz

32 kHz

44.1 kHz

48 kHz

96 kHz

192 kHz

Note: The sample calculations shown are based on WS = 64 SCLK rising edges.

FSCLK (MHz)

2.048

2.822

3.072

6.144

12.288

2.048

2.822

3.072

6.144

12.288

Ttr

488 ns

354 ns

326 ns

163 ns

81 ns

488 ns

354 ns

326 ns

163 ns

81 ns

Min

190 ns

136 ns

125 ns

60 ns

27 ns

190 ns

136 ns

125 ns

60 ns

27 ns

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SiI-DS-1061-C 33

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

7. Pin Diagram and Descriptions

7.1. Pin Diagram

Figure 7.1

shows the pin assignments of the SiI9233A receiver device. Individual pin functions are described in the Pin

Descriptions section on the next page. The package is a 20 mm × 20 mm 144-pin TQFP with an ePad, which must be

connected to ground.

4

5

6

1

2

3

7

8

9

10

11

12

13

25

26

27

28

21

22

23

24

18

19

20

14

15

16

17

32

33

34

35

29

30

31

36

RSVDNC

APVCC12

XTALVCC33

XTALOUT

XTALIN

XTALGND

IOVCC33

CVCC12

RSVDNC

RSVDNC

RSVDL

GPIO0/XCLKOUT

GPIO 1/SCDT

GPIO2/EVNODD

RSVDNC

GPIO4

GPIO5

RSVDNC

GPIO6/DL3

GPIO7/DR3

RESET#

INT

CSCL

CSDA

CI 2CA

CEC_ A

CEC_D

SBVCC5

R0PWR 5V

HPD0

DSCL0

DSDA0

R1 PWR5V

HPD1

DSCL1

DSDA1

SiI9233A

(Top View )

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

97

96

95

94

93

92

91

101

100

99

98

108

107

106

105

104

103

102

Q13

Q14

Q15

Q16

Q17

ODCK

HSYNC

VSYNC

DE

Q3

Q4

Q5

Q6

CVCC 12

Q0

Q1

Q2

Q7

Q8

IOVCC 33

CVCC 12

Q9

Q10

Q11

Q12

AVCC33

GPIO3 / MUTEOUT

SPDIF/DL2

MCLK

SD3/DR2

SD2/DL1

SD1/DR1

SD0/DL0

SCK/DCLK

WS/DR0

IOVCC 33

Figure 7.1. Pin Diagram

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

34 SiI-DS-1061-C

7.2. Pin Descriptions

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

R2XC+

R2XC-

R3X0+

R3X0-

R3X1+

R3X1-

R3X2+

R3X2-

R3XC+

R3XC-

R1X0+

R1X0-

R1X1+

R1X1-

R1X2+

R1X2-

R1XC+

R1XC-

Pin Name

R0X0+

R0X0-

R0X1+

R0X1-

R0X2+

R0X2-

R0XC+

R0XC-

R2X0+

R2X0-

R2X1+

R2X1-

R2X2+

R2X2-

7.2.1. Differential Signal Data Pins

121

120

123

122

125

124

119

118

130

129

132

131

134

133

Pin

112

111

114

113

116

115

110

109

128

127

139

138

141

140

143

142

137

136

Type Dir Description

TMDS analog Input HDMI Port 0 TMDS input data pairs.

TMDS analog Input HDMI Port 0 TMDS input clock pair.

TMDS analog Input HDMI Port 1 TMDS input data pairs.

TMDS analog Input HDMI Port 1TMDS input clock pair.

TMDS analog Input HDMI Port 2 TMDS input data pairs.

TMDS analog Input HDMI Port 2 TMDS input clock pair.

TMDS analog Input HDMI Port 3 TMDS input data pairs.

TMDS analog Input HDMI Port 3 TMDS input clock pair.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 35

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

7.2.2. Digital Video Output Data Pins

Pin Name

Q0

Q1

Q2

Q3

Pin

96

95

94

93

Type

LVTTL

2 mA to 14 mA

Dir Description

Output 36-Bit Output Pixel Data Bus.

Q[35:0] is highly configurable using the various video configuration registers. It supports a wide array of output formats, including multiple RGB and YCbCr bus formats. Using the appropriate bits in the PD_SYS2 register, the output drivers can be put into a high impedance state.

Q4

92

Q5

91

Q6

90

Q7

89

Q8

88

Q9

85

Q10

84

Q11

83

Q12

82

Q13

81

Q14

80

Q15

79

Q16

78

Q17

77

Q18

70

Q19

69

Q20

68

Q21

67

Q22

66

Q23

65

Q24

64

Q25

63

Q26

62

Q27

59

Q28

58

Q29

57

Q30

56

Q31

55

Q32

54

Q33

53

Q34

52

Q35

51

Notes:

1. When transporting video data that uses fewer than 36 bits, the unused bits on the Q[] bus can still carry switching pixel data signals. Unused Q[35:0] bus pins should be unconnected, masked or ignored by downstream devices. For example, carrying

YCbCr 4:2:2 data with 16-bit width (see the YC 4:2:2 Formats with Separate Syncs section on page 47), the bits Q[0] through

Q[7] output switching signals.

2. The output data bus, Q[0:35], can be wire-ORed to another device so one device is always in the high-impedance state.

However, these pins do not have internal pull-up or pull-down resistors, and so cannot pull the bus HIGH or LOW when all connected devices are in the high impedance state.

3. The drive strength of Q[0:35] can be programmed in 2-mA steps between 2 mA and 14 mA.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

36 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

7.2.3. Digital Video Output Control Pins

Pin Name Pin Type Dir Description

DE 73 Output Data Enable.

HSYNC 75

LVTTL

2 mA to 14 mA

LVTTL

2 mA to 14 mA

Output Horizontal Sync Output.

VSYNC

GPIO2/

EVNODD

GPIO2/

EVNODD

74

14

LVTTL

2 mA to 14 mA

LVTTL

8 mA

Output Vertical Sync Output.

Input

Output

Programmable GPIO2.

Output Indicates Even or Odd Field for Interlaced Formats.

ODCK 76 LVTTL

2 mA to 14 mA

Output Output Data Clock.

Notes:

1. HSYNC and VSYNC outputs carry sync signals for both embedded and separate sync configurations.

2. The drive strength of DE, HSYNC, VSYNC, and ODCK can be programmed in 2-mA steps between 2 mA and 14 mA.

7.2.4. HDMI Control Signal Pins

Pin Name

DSCL0

DSCL1

DSCL2

DSCL3

DSDA0

DSDA1

DSDA2

DSDA3

HPD0

HPD1

HPD2

HPD3

R0PWR5V

R1PWR5V

R2PWR5V

R3PWR5V

Pin

31

35

39

43

32

36

40

44

29

33

37

41

30

34

38

42

Type

Schmitt

Open drain

5 V tolerant

Schmitt

Open drain

5 V tolerant

3 mA

LVTTL

4 mA

LVTTL

5 V tolerant

Dir Description

Input DDC I

2

C Clock for respective port.

HDCP KSV, An, and Ri values are exchanged over an I

2

C port during authentication. True open drain, so does not pull to GND if power is not applied.

Input

Output

Input

Output

DDC I

2

C Data for respective port.

HDCP KSV, An, and Ri values are exchanged over an I

2

C port during authentication. True open drain, so does not pull to GND if power is not applied.

Hotplug output signal to HDMI connector for respective port

Indicates EDID is readable..

Input 5 V power and port detection input for respective port.

Used to power internal EDID when device is not powered.

CEC_A

CEC_D

26 CEC compliant

5 V tolerant

27 LVTTL

Schmitt

Input

Output

Input

Output

HDMI compliant CEC I/O used to interface to CEC devices.

This pin connects to the CEC signal of all HDMI connectors in the system.

This pin has an internal pull-up resistor.

CEC interface to local system. True open-drain. An external pull-up is required.

This pin typically connects to the local CPU.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 37

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

SD3/DR2

SD2/DL1

SD1/DR1

SD0/DL0

SD3/DR2

SD2/DL1

SD1/DR1

SD0/DL0

WS/

DR0

WS/

DR0

SPDIF/

DL2

SPDIF/

DL2

GPIO6/

DL3

GPIO6/

DL3

GPIO7/

DR3

GPIO7/

DR3

7.2.5. Digital Audio Output Pins

Pin Name Pin Type Dir Description

XTALIN

XTALOUT

5

4

5 V tolerant

LVTTL

Input Crystal Clock Input.

Also allows LVTTL input. Frequency required: 26 MHz – 28.5 MHz.

Output Crystal Clock Output.

GPIO0/

XCLKOUT

GPIO0/

XCLKOUT

12

LVTTL

4 mA

LVTTL

4 mA

Input

Output

Programmable GPIO0.

Output Additional Clock Output from crystal oscillator circuit.

MCLK

SCK/

DCLK

SCK/

DCLK

105

100

LVTTL

8 mA

LVTTL

4 mA

Output Audio Master Clock Output.

Output I

2

S Serial Clock Output.

DSD Clock Output.

104

103

102

101

LVTTL

4 mA

Output I

2

S Serial Data Output.

99

106

19

20

LVTTL

4 mA

LVTTL

4 mA

LVTTL

4 mA

LVTTL

4 mA

DSD Serial Right Ch2 Data Output.

DSD Serial Left Ch1 Data Output.

DSD Serial Right Ch1 Data Output.

DSD Serial Left Ch0 Data Output.

Output I

2

S Word Select Output.

Output S/PDIF Audio Output.

Input/

Output

DSD Serial Right Ch0 Data Output.

DSD Serial Left Channel 2 data output.

Programmable GPIO6.

Output DSD Serial Left Channel 3 data output.

Input/

Output

Programmable GPIO7.

Output DSD Serial Right Channel 3 data output.

GPIO3/

MUTEOUT

GPIO3/

MUTEOUT

107 LVTTL

4 mA

Input

Output

Programmable GPIO3 or Mute Audio Output.

Output Mute Audio Output.

Signal to the external downstream audio device, audio DAC, and so on to mute audio output.

Note: The XTALIN pin can either be driven at LVTTL levels by a clock (leaving XTALOUT unconnected), or connected through a crystal

to XTALOUT; see Figure 9.7

on page 67.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

38 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

7.2.6. Configuration/Programming Pins

Pin Name Pin Type Dir Description

INT

RESET#

CSCL

22

21

23

LVTTL

4 mA

Schmitt

5 V tolerant

Schmitt

5 V tolerant

Output Interrupt Output.

Configurable polarity and push-pull output. Multiple sources of interrupt can be enabled through the INT_EN register.

See note below.

Input Reset Pin.

Active LOW.

Input Configuration/Status I

2

C Clock.

Chip configuration/status, CEA-861 support and downstream HDCP registers are accessed via this I

2

C port.

CSDA 24 Schmitt

5 V tolerant

3 mA

Input

Output

Configuration/Status I

2

C Data.

Chip configuration/status, CEA-861 support and downstream HDCP registers are accessed via this I

2

C port.

CI2CA

GPIO1/SCDT

GPIO1/SCDT

GPIO4

GPIO5

25

13

16

17

LVTTL

5 V tolerant

LVTTL

4 mA

LVTTL

4 mA

LVTTL

4 mA

Input Local I

2

C Address Select.

LOW = Addresses 0x60/0x68

HIGH = Addresses 0x62/0x6A

Input

Output

Output Sync Detection Indicator.

Indicates Active Video at HDMI Input Port.

Input

Output

Input

Output

Programmable GPIO1.

Programmable GPIO4.

Programmable GPIO5.

Note: The INT pin can be programmed to be either a push-pull LVTTL output or an open-drain output.

7.2.7. Power and Ground Pins

Pin Name

CVCC12

IOVCC33

AVCC33

AVCC12

APVCC12

XTALVCC33

XTALGND

SBVCC5

GND

Pin

8, 60, 71, 86, 97

7, 61, 72, 87, 98

108, 126, 144

117, 135

Type

Power

Power

Power

Power

Description

Digital Logic VCC.

Input/Output Pin VCC.

TMDS Analog VCC 3.3 V.

TMDS Analog VCC 1.2 V.

2

3

Power Audio Clock Regeneration PLL Analog VCC.

Must be connected to 1.2 V.

Power Audio Clock Regeneration PLL crystal oscillator power.

Must be connected to 3.3 V.

6

28

Ground Audio Clock Regeneration ground.

Power Standby power supply.

All other supplies can be off with SBVCC5 on.

50, ePad (bottom of package) Ground Ground. The ePad must be soldered to ground.

7.2.8. Reserved and Not Connected Pins

Pin Name

RSVDNC

Pin

1, 9, 10, 15, 18, 45–49

Type Description

Reserved Reserved, must be left unconnected

RSVDL 11 Reserved Reserved, must be tied to ground

Supply

1.2 V

3.3 V

3.3 V

1.2 V

1.2 V

3.3 V

Ground

5 V

Ground

Supply

No connection

Ground

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 39

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8. Feature Information

8.1. Video Path

The SiI9233A receiver accepts all valid HDMI input formats and can transform that video in a variety of ways to produce the proper video output format. The following pages describe how to control the video path formatting and how to

assign output pins for each video output format. The processing blocks shown in Figure 8.1

correspond to those shown

in Figure 8.2

through Figure 8.4 on pages 41 through 43.

TMDS HDCP

Widen to

14-Bits

InfoFrame

Packet

Processing

Audio

Processing

I2S Outputs

MCLK

SPDIF

SCK

WS

SD[3:0]

RGB to

YCbCr bypass

YCbCr

Range

Reduce bypass

Down

Sample

4:4:4 to

4:2:2 bypass

DSD Outputs

Note: DSD outputs are shared with SPDIF and

I2S signals

DCLK

DR[3:0]

DL[3:0]

Upsample

4:2:2 to

4:4:4 bypass xvYCC/

YCbCr to

RGB bypass

RGB

Range

Expand bypass

Dither

Module

Mux

656

Video

Timing

DE

HSYNC

VSYNC

ODCK

Q[35:0]

Figure 8.1. Receiver Video and Audio Data Processing Paths

8.1.1. HDMI Input Modes to SiI9233A Receiver Output Modes

The HDMI link supports transport of video in any of three modes: RGB 4:4:4, YCbCr 4:4:4 or YCbCr 4:2:2. The flexible

video path in the SiI9233A receiver allows reformatting of video data to a set of output modes. Table 8.1

lists the

supported transformations and points to the figure for each. In every case, the HDMI link itself carries separate syncs.

Table 8.1. Translating HDMI Formats to Output Formats

HDMI Input Mode

RGB 4:4:4

Digital Output Format

RGB 4:4:4

Separate Sync

Figure 8.2A

YCbCr 4:4:4

Separate Sync

Figure 8.2B

YCbCr 4:2:2

Separate Sync

Figure 8.2C

YCbCr/xvYCC 4:4:4

YCbCr/xvYCC 4:2:2

Figure 8.3A

Figure 8.4A

Figure 8.3B

Figure 8.4B

Figure 8.3C

Figure 8.4C

YCbCr 4:2:2

Embedded Sync

Figure 8.2D

Figure 8.3D

Figure 8.4D

YC Mux

Separate Sync

Figure 8.2E

Figure 8.3E

Figure 8.4E

YC Mux

Embedded Sync

Figure 8.2F

Figure 8.3F

Figure 8.4F

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

40 SiI-DS-1061-C

8.1.1.1. HDMI RGB 4:4:4 Input Processing

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Digital Out

TMDS and

HDCP

Decoding

A

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

B

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

DownSampling

C

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

DownSampling

Embedded

Syncs

D

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

DownSampling MUX YC

E

Digital Out

TMDS and

HDCP

Decoding

RGBtoYCbCr

Color Range

Scaling

Down

Sampling

Embedded

Syncs

MUX YC

F

Figure 8.2. HDMI RGB 4:4:4 Input to Video Output Transformations

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 41

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.1.2. HDMI YCbCr/xvYCC 4:4:4 Input Processing

TMDS and

HDCP

Decoding

YCbCr/xvYCC to RGB

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

TMDS and

HDCP

Decoding

Digital Out

A

Digital Out

B

Digital Out

DownSampling

C

Digital Out

DownSampling

Embedded

Syncs

D

Digital Out

DownSampling MUX YC

E

Digital Out

DownSampling

Embedded

Syncs

MUX YC

Figure 8.3. HDMI YCbCr/xvYCC 4:4:4 Input to Video Output Transformations

F

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

42 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.1.3. HDMI YCbCr/xvYCC 4:2:2 Input Processing

Digital Out

TMDS and

HDCP

Decoding

Upsampling

YCbCr/xvYCC to RGB

A

Digital Out

TMDS and

HDCP

Decoding

UpSampling

B

Digital Out

TMDS and

HDCP

Decoding

C

Digital Out

TMDS and

HDCP

Decoding

Embedded

Syncs

D

Digital Out

TMDS and

HDCP

Decoding

MUX YC

E

Digital Out

TMDS and

HDCP

Decoding

Embedded

Syncs

MUX YC

F

Figure 8.4. HDMI YCbCr/xvYCC 4:2:2 Input to Video Output Transformations

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 43

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.2. Output Mode Configuration

The SiI9233A receiver supports multiple output data mappings. Some have separate control signals while some have embedded control signals. The selection of data mapping mode should be consistent at the pins and in the corresponding register settings. Refer to the Programmer Reference for more details.

Table 8.2. Output Video Formats

Output Mode Data Widths

RGB 4:4:4 24, 30, 36

YCbCr 4:4:4 24, 30, 36

Pixel Replication

1x

Syncs

Separate

Separate

Page

45

45

Notes

3, 7

1. 3. 7

1x

YC 4:2:2 Sep. Syncs 16, 20, 24

1x

Separate

47

2, 3

YC 4:2:2 Sep. Syncs 16, 20, 24

2x

Separate

47

2, 3, 8

YC 4:2:2 Emb. Syncs 16, 20, 24

1x

Embedded

50

2, 5

YC MUX 4:2:2

YC MUX 4:2:2 Emb. Syncs

8, 10, 12

8, 10, 12

2x

2x

Separate

Embedded

53

55

2, 4, 8

2, 5, 6, 8, 9

Notes:

1. YC 4:4:4 data contains one Cr, one Cb and one Y value for every pixel.

2. YC 4:2:2 data contains one Cr and one Cb value for every two pixels; and one Y value for every pixel.

3. These formats can be carried across the HDMI link. Refer to the HDMI Specification, Section 6.2.3. The link clock must be within the specified range of the receiver.

4. In YC MUX mode data is sent to one or two 8/10/12-bit channels.

5. YC MUX with embedded SAV/EAV signal.

6. Syncs are embedded using SAV/EAV codes.

7. A 2x clock can also be sent with 4:4:4 data.

8. When sending a 2x clock the HDMI source must also send AVI InfoFrames with an accurate pixel replication field. Refer to HDMI Spec 1.3, Section 6.4.

9. 2x clocking does not support YC 4:2:2 embedded Sync timings for 720p or 1080i, as the output clock frequency would exceed the range allowed for the receiver.

The SiI9233A receiver can output video in various formats on its parallel digital output bus. Some transformation of the data received over HDMI is necessary in some modes. Digital output is used with either 4:4:4 or 4:2:2 data.

The diagrams do not include separation of the audio and InfoFrame packets from the HDMI stream, which occurs immediately after the TMDS and (optional) HDCP decoding. The HDMI link always carries separate HSYNC and VSYNC and DE. Therefore the SAV/EAV sync encoder must be used whenever the output mode includes embedded sync.

The timing diagrams in Figure 8.5

through Figure 8.9 on pages 46 through 56 show only a representation of the DE,

HSYNC and VSYNC timings. These timings are specific to the video resolution, as defined by EIA/CEA-861B and other specs. The number of pixels shown per DE HIGH time is representative, to show the data formatting.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

44 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.2.1. RGB and YCbCr 4:4:4 Formats with Separate Syncs

The pixel clock runs at the pixel rate and a complete definition of each pixel is output on each clock. Figure 8.5

on the

next page shows RGB data. The same timing format is used for YCbCr 4:4:4 as listed in Table 8.3

.

Figure 8.5

also shows

timings with OCLKDIV = 0 and OCKINV = 1.

Table 8.3. 4:4:4 Mappings

Pin Name

R4

R5

R6

R7

R8

R0

R1

R2

R3

G8

G9

G10

G11

G3

G4

G5

G6

G7

R9

R10

R11

B7

B8

B9

B10

B11

G0

G1

G2

36-bit

RGB

B0

B1

B2

B3

B4

B5

B6

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q31

Q32

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q23

Q33

Q34

Q35

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q0

Q1

Q2

Q3

Q4

Q5

Q6

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

Cr2

Cr3

Cr4

Cr5

Cr6

NC

NC

Cr0

Cr1

Y6

Y7

Y8

Y9

Y1

Y2

Y3

Y4

Y5

Cr7

Cr8

Cr9

Cb5

Cb6

Cb7

Cb8

Cb9

NC

NC

Y0

30-bit

YCbCr

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

HSYNC

VSYNC

DE

R2

R3

R4

R5

R6

NC

NC

R0

R1

G6

G7

G8

G9

G1

G2

G3

G4

G5

R7

R8

R9

B9

NC

NC

G0

B5

B6

B7

B8

30-bit

RGB

NC

NC

B0

B1

B2

B3

B4

HSYNC

VSYNC

DE

Cr4

Cr5

Cr6

Cr7

Cr8

Cr0

Cr1

Cr2

Cr3

Y8

Y9

Y10

Y11

Y3

Y4

Y5

Y6

Y7

Cr9

Cr10

Cr11

Cb7

Cb8

Cb9

Cb10

Cb11

Y0

Y1

Y2

36-bit

YCbCr

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

HSYNC

VSYNC

DE

R0

R1

R2

R3

R4

NC

NC

NC

NC

G4

G5

G6

G7

NC

G0

G1

G2

G3

R5

R6

R7

B7

NC

NC

NC

B3

B4

B5

B6

24-bit

RGB

NC

NC

NC

NC

B0

B1

B2

HSYNC

VSYNC

DE

Cr0

Cr1

Cr2

Cr3

Cr4

NC

NC

NC

NC

Y4

Y5

Y6

Y7

NC

Y0

Y1

Y2

Y3

Cr5

Cr6

Cr7

Cb3

Cb4

Cb5

Cb6

Cb7

NC

NC

NC

24-bit

YCbCr

NC

NC

NC

NC

Cb0

Cb1

Cb2

HSYNC

VSYNC

DE

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 45

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

blank Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel n blank blank

Q[35:24] val R0 R1 R2 R3 R4 Rn val val blank val

Q[23:12] val G0 G1 G2 G3 G4 Gn val val val

Q[11:0]

ODCK val B0 B1 B2 B3 B4 Bn val val val

DE

HSYNC,

VSYNC

Figure 8.5. 4:4:4 Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233A registers, because no pixel data is carried on HDMI during blanking.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

46 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.2.2. YC 4:2:2 Formats with Separate Syncs

The YC 4:2:2 formats output one pixel for every pixel clock period. A luminance (Y) value is sent for every pixel, but the chrominance values (Cb and Cr) are sent over two pixels. Pixel data can be 24-bit, 20-bit or 16-bit. HSYNC and VSYNC

are output separately on their own pins. The DE HIGH time must contain an even number of pixel clocks. Figure 8.6

on page 49 shows timings with OCLKDIV = 0 and OCKINV = 1.

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q31

Q32

Q33

Q34

Q35

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q0

Q1

Q2

Q3

Q4

Table 8.4. YC 4:2:2 Separate Sync Pin Mappings

Pin Name

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Pixel #0

NC

16-bit YC

Pixel #1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Cr3

Cr4

Cr5

Cr6

NC

Cr0

Cr1

Cr2

Cr7

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

HSYNC

VSYNC

DE

Y9

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Y4

Y5

Y6

Y7

Y8

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #0

NC

NC

NC

NC

NC

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

VSYNC

DE

20-bit YC

Cr1

Cr2

Cr3

Cr4

Y9

NC

NC

Cr0

Y4

Y5

Y6

Y7

Y8

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

VSYNC

DE

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y6

Y7

Y8

Y9

Y10

Y2

Y3

Y4

Y5

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

Pixel #0

NC

NC

NC

NC

NC

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

24-bit YC

Cr3

Cr4

Cr5

Cr6

Y11

Cr0

Cr1

Cr2

Y6

Y7

Y8

Y9

Y10

Y2

Y3

Y4

Y5

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 47

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q31

Q32

Q33

Q34

Q35

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q0

Q1

Q2

Q3

Q4

Q5

Table 8.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping

20-bit YC

Pin Name

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Pixel #0

NC

NC

16-bit YC

Pixel #1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Cr3

Cr4

Cr5

Cr6

NC

Cr0

Cr1

Cr2

Cr7

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

Cb2

Cb3

Cb4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cb0

Cb1

NC

NC

Y0

Y1

NC

NC

Pixel #0

NC

NC

NC

NC

NC

NC

Cb5

Cb6

Cb7

Cb8

Cb9

NC

Cr2

Cr3

Cr4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cr0

Cr1

NC

NC

Y0

Y1

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC HSYNC HSYNC HSYNC HSYNC

VSYNC

DE

VSYNC

DE

VSYNC

DE

VSYNC

DE

VSYNC

DE

Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video processing block should be enabled when this pin mapping is used.

Y11

NC

NC

NC

NC

Cb4

Cb5

Cb6

Y6

Y7

Y8

Y9

Y10

NC

NC

Y4

Y5

Y2

Y3

Cb0

Cb1

Cb2

Cb3

NC

NC

Pixel #0

NC

NC

NC

NC

Y0

Y1

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

24-bit YC

NC

Cr4

Cr5

Cr6

Y11

NC

NC

NC

Y6

Y7

Y8

Y9

Y10

NC

NC

Y4

Y5

Cr2

Cr3

NC

NC

Y2

Y3

Cr0

Cr1

Pixel #1

NC

NC

NC

NC

Y0

Y1

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

48 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q[35:28] blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel n-1 Pixeln val Cb0[ 11:4] Cr0[ 11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11: 4] Crn-1[ 11: 4]

Q[23:16] val Y0[ 11: 4] Y1[ 11:4] Y2[ 11:4] Y3[11: 4] Yn-1[11:4] Yn[ 11: 4] val val

Q[27:24]

Q[15:12]

ODCK val val

Cb0[3:0] Cr0[3:0] Cb2[3:0] Cr2[3:0] Cbn-1[3:0] Crn-1 [3:0]

Y0[3: 0] Y1[3: 0] Y2[ 3: 0] Y3[ 3:0] Yn-1[3:0] Yn[ 3:0] val val val val val val

DE

HSYNC,

VSYNC

Figure 8.6. YC Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233A registers, because no pixel data is carried on HDMI during blanking.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 49

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.2.3. YC 4:2:2 Formats with Embedded Syncs

The YC 4:2:2 embedded sync format is identical to the previous format (YC 4:2:2), except that the syncs are embedded and

not separate. Pixel data can be 24-bit, 20-bit or 16-bit. DE is always output. Figure 8.7

on page 52 shows the Start of Active

Video (SAV) preamble, the End of Active Video” (EAV) suffix, and shows timings with OCLKDIV = 0 and OCKINV = 1.

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q31

Q32

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q23

Q33

Q34

Q35

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Table 8.6. YC 4:2:2 Embedded Sync Pin Mappings

Pin Name

NC

NC

NC

NC

Y4

Y5

Y6

Y7

NC

Y0

Y1

Y2

Y3

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Pixel #0

NC

NC

16-bit YC

Pixel #1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

NC

NC

NC

NC

Y4

Y5

Y6

Y7

NC

Y0

Y1

Y2

Y3

NC

NC

NC

NC

HSYNC

VSYNC

DE

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y6

Y7

Y8

Y9

Y1

Y2

Y3

Y4

Y5

Cb7

Cb8

Cb9

NC

NC

NC

Y0

NC

NC

NC

NC

Pixel #0

NC

NC

NC

NC

NC

NC

NC

20-bit YC

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Cr2

Cr3

Cr4

Cr5

Cr6

NC

NC

Cr0

Cr1

Y6

Y7

Y8

Y9

Y1

Y2

Y3

Y4

Y5

Cr7

Cr8

Cr9

NC

NC

NC

Y0

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Cb8

Y8

Y9

Y10

Y11

Y3

Y4

Y5

Y6

Y7

Cb9

Cb10

Cb11

NC

Y0

Y1

Y2

NC

NC

NC

NC

Pixel #0

NC

NC

NC

NC

NC

NC

NC

Embedded

Embedded

Embedded

24-bit YC

Embedded

Embedded

Embedded

Cr4

Cr5

Cr6

Cr7

Cr8

Cr0

Cr1

Cr2

Cr3

Y8

Y9

Y10

Y11

Y3

Y4

Y5

Y6

Y7

Cr9

Cr10

Cr11

NC

Y0

Y1

Y2

NC

NC

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

NC

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

50 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Table 8.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping

Pin Name

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q31

Q32

Q33

Q34

Q35

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q0

Q1

Q2

Q3

Q4

Q5

Pixel #0

NC

NC

16-bit YC

Pixel #1

NC

NC

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y7

NC

NC

NC

Y2

Y3

Y4

Y5

Y6

NC

NC

Y0

Y1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

NC

Cr2

Cr3

Cr4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cr0

Cr1

NC

NC

Y0

Y1

NC

NC

Pixel #1

NC

NC

NC

NC

NC

NC

Cr5

Cr6

Cr7

Cr8

Cr9

NC

Cb2

Cb3

Cb4

Y9

NC

NC

NC

Y4

Y5

Y6

Y7

Y8

NC

NC

Y2

Y3

Cb0

Cb1

NC

NC

Y0

Y1

NC

NC

Pixel #0

NC

NC

NC

NC

NC

NC

Cb5

Cb6

Cb7

Cb8

Cb9

20-bit YC

Y11

NC

NC

NC

NC

Cb4

Cb5

Cb6

Y6

Y7

Y8

Y9

Y10

NC

NC

Y4

Y5

Y2

Y3

Cb0

Cb1

Cb2

Cb3

NC

NC

Pixel #0

NC

NC

NC

NC

Y0

Y1

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC Embedded Embedded Embedded Embedded Embedded

VSYNC

DE

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Embedded

Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video processing block should be enabled when this pin mapping is used.

Embedded

Embedded

24-bit YC

Embedded

Embedded

Embedded

NC

Cr4

Cr5

Cr6

Y11

NC

NC

NC

Y6

Y7

Y8

Y9

Y10

NC

NC

Y4

Y5

Cr2

Cr3

NC

NC

Y2

Y3

Cr0

Cr1

Pixel #1

NC

NC

NC

NC

Y0

Y1

Cr7

Cr8

Cr9

Cr10

Cr11

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 51

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

SAV val FF 00 00 XY

Pixel0 Pixel1 Pixel2 Pixel3 Pixel n-1 Pixel n

Cb0[11:4] Cr0[11:4] Cb2[11:4] Cr2[11:4] Cbn-1[11:4] Crn-1[11:4] FF

Q[35:28]

Q[23:16]

Q[27:24]

Q[15:12]

ODCK

Active

Video val val val

FF

X

X

00

X

X

00

X

X

XY Y0[ 11: 4] Y1[ 11:4] Y2[11: 4] Y3[11: 4] Yn-1[11:4] Yn[ 11:4]

X

X

Cb0[3: 0] Cr0[3:0] Cb2[3: 0] Cr2[3:0] Cbn-1[3:0] Crn-1[ 3:0] X

Y0[ 3:0] Y1[3:0] Y2[3:0] Y3[ 3:0] Yn-1[3: 0] Yn[3:0]

FF

X

Figure 8.7. YC 4:2:2 Embedded Sync Timing Diagram

00

00

X

X

EAV

00

00

X

X

X

X

XY

XY val val val val

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233A registers, because no pixel data is carried on HDMI during blanking. SAV/EAV codes appear as an

8-bit field on both Q[35:28] (per SMPTE) and Q[23:16].

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

52 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q23

Q24

Q25

Q26

Q27

Q28

Q29

Q30

Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22

Q31

Q32

Q33

Q34

Q35

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q0

Q1

Q2

Q3

Q4

HSYNC

VSYNC

DE

8.1.2.4. YC Mux (4:2:2) Formats with Separate Syncs

The video data is multiplexed onto fewer pins than the mapping in Table 8.8

, but complete luminance (Y) and

chrominance (Cb and Cr) data is still provided for each pixel because the output pixel clock runs at twice the pixel rate.

Figure 8.8

on the next page shows the 24-bit mode. The 16- and 20-bit mappings use fewer output pins for the pixel data. Note the separate syncs. Figure 8.8

also shows OCLKDIV = 0 and OCKINV = 1.

Table 8.8. YC Mux 4:2:2 Mappings

Pin Name

NC

NC

NC

NC

D7

NC

NC

NC

D2

D3

D4

D5

D6

NC

NC

D0

D1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

8-bit

YCbCr

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

NC

NC

NC

NC

D9

NC

NC

NC

D4

D5

D6

D7

D8

D0

D1

D2

D3

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

10-bit

YCbCr

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

NC

NC

NC

NC

D11

NC

NC

NC

D6

D7

D8

D9

D10

D2

D3

D4

D5

NC

NC

NC

NC

NC

NC

NC

D0

D1

NC

NC

NC

NC

NC

12-bit

YCbCr

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 53

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q[35:24]

Q[11:0]

Q[23:16]

X val

X val

X val

X val

X val

X

Pixel 0

X X

Pixel 1

X X

Pixel 2

X X

Pixel 3

X

Cb0[11:4] Y0[11:4] Cr0[11:4] Y1[11:4] Cb2[11: 4] Y2[11:4] Cr2[11:4] Y3[11:4]

Q[15:12]

ODCK val val val val val

Cb0[3:0] Y0[3:0] Cr0[3:0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[3:0] Y3[3:0]

DE

HSYNC

VSYNC

Figure 8.8. YC Mux 4:2:2 Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233A registers, because no pixel data is carried on HDMI during blanking.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

54 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.1.2.5. YC Mux 4:2:2 Formats with Embedded Syncs

This mode is similar to that shown in Figure 8.7

on page 53, but with embedded syncs. It is similar to YC 4:2:2 with

embedded syncs, but also multiplexes the luminance (Y) and chrominance (Cb and Cr) onto the same pins on alternating pixel clock cycles. Normally this mode is used only for 480i, 480p, 576i and 576p modes. Output clock rate is half the pixel clock rate on the link. SAV code is shown before rise of DE. EAV follows the falling edge of DE. See the ITU-

R BT.656 Specification. 480p, 54-MHz output can be achieved if the input differential clock is 54 MHz. Figure 8.9

on the

next page shows OCLKDIV = 0 and OCKINV = 1.

Table 8.9. YC Mux 4:2:2 Embedded Sync Pin Mapping

8-bit

Pin Name

Q0

Q1

Q2

YCbCr

NC

NC

NC

Q28

Q29

Q30

Q31

Q32

Q33

Q34

Q35

Q20

Q21

Q22

Q23

Q24

Q25

Q26

Q27

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q18

Q19

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

D4

D5

D6

D7

NC

D0

D1

D2

D3

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

HSYNC

VSYNC

DE

Embedded

Embedded

Embedded

NC

NC

NC

NC

D6

D7

D8

D9

D1

D2

D3

D4

D5

NC

NC

NC

D0

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

10-bit

YCbCr

NC

NC

NC

Embedded

Embedded

Embedded

NC

NC

NC

NC

D8

D9

D10

D11

D3

D4

D5

D6

D7

NC

D0

D1

D2

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

12-bit

YCbCr

NC

NC

NC

Embedded

Embedded

Embedded

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 55

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q[35:24]

Q[11:0]

Q[23:16] val val

X

FF

X

SAV

X

00 00

X

XY

X

Pixel 0

X X

Pixel 1

X X

Pixel 2

X X

Pixel 3

X

Cb0[11:4] Y0[ 11:4] Cr0[11: 4] Y1[11:4] Cb2[11:4] Y2[11:4] Cr2[11:4] Y3[11:4]

Q[15:12]

ODCK

Active

Video val X X X X

Cb0[3:0] Y0[3:0]

Cr0[3: 0] Y1[3:0] Cb2[3:0] Y2[3:0] Cr2[ 3:0] Y3[3:0]

Figure 8.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram

Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate SiI9233A registers, because no pixel data is carried on HDMI during blanking. Refer to the Programmer

Reference for details.

8.1.2.6. 12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs

The output clock runs at the pixel rate and a complete definition of each pixel is output on each clock. One clock edge drives out half the pixel data on 12/15/18 pins. The opposite clock edge drives out the remaining half of the pixel data

on the same 12/15/18 pins. Figure 8.10

below shows RGB data. The same timing format is used for YCbCr 4:4:4 as listed

in the columns of Table 8.10

. Control signals (DE, HSYNC and VSYNC) change state with respect to the first edge of

ODCK.

Q7

Q8

Q9

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Table 8.10. 12/15/18-Bit Output 4:4:4 Mappings

24-bit

Pin

Name

RGB YCbCr

First

Edge

B6

B7

G0

G1

B1

B2

B3

B4

B5

G2

G3

NC

NC

NC

NC

NC

NC

B0

Second

Edge

R2

R3

R4

R5

G5

G6

G7

R0

R1

R6

R7

NC

NC

NC

NC

NC

NC

G4

First

Edge

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Y3

NC

NC

NC

NC

NC

NC

Cb0

Second

Edge

Cr2

Cr3

Cr4

Cr5

Y5

Y6

Y7

Cr0

Cr1

Cr6

Cr7

NC

NC

NC

NC

NC

NC

Y4

First

Edge

B9

G0

G1

G2

B4

B5

B6

B7

B8

G3

G4

NC

NC

NC

B0

B1

B2

B3

RGB

30-bit

YCbCr

Second

Edge

Cr4

Cr5

Cr6

Cr7

Y9

Cr0

Cr1

Cr2

Cr3

Cr8

Cr9

NC

NC

NC

Y5

Y6

Y7

Y8

First

Edge

Cb4

Cb5

Cb6

Cb7

Cb8

Cb9

Y0

Y1

Y2

Y3

Y4

NC

NC

NC

Cb0

Cb1

Cb2

Cb3

Second

Edge

R4

R5

R6

R7

G9

R0

R1

R2

R3

R8

R9

NC

NC

NC

G5

G6

G7

G8

36-bit

RGB

Second

Edge

R6

R7

R8

R9

R1

R2

R3

R4

R5

R10

R11

G6

G7

G8

G9

G10

G11

R0

First

Edge

G0

G1

G2

G3

B7

B8

B9

B10

B11

G4

G5

B0

B1

B2

B3

B4

B5

B6

YCbCr

First

Edge

Cb7

Cb8

Cb9

Cb10

Cb11

Y0

Y1

Y2

Y3

Y4

Y5

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Second

Edge

Cr6

Cr7

Cr8

Cr9

Cr1

Cr2

Cr3

Cr4

Cr5

Cr10

Cr11

Y6

Y7

Y8

Y9

Y10

Y11

Cr0

HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC

VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC

DE DE DE DE DE DE DE DE DE DE DE DE DE

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

56 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Q[17:12] blank val

Pixel 0 Pixel 1 Pixel 2 Pixel 3

G0[5:0] R0[11:6] G1[5:0] R1[11:6] G2[5:0] R2[11:6] G3[5:0] R3[11:6]

Q[11:6]

Q[5:0]

ODCK val B0[11:6] R0[5:0] B1[11:6] R1[5:0] B2[11:6] R2[5:0] B3[11:6] R3[5:0] val val

B0[5:0] G0[11:6] B1[5:0] G1[11:6] B2[5:0] G2[11:6] B3[5:0] G3[11:6] val val blank val val val val blank val val val val val val blank val val val val val

DE

HSYNC,

VSYNC

Figure 8.10. 18-Bit Output 4:4:4 Timing Diagram

Q[17:13] blank val

Pixel 0

G0[4:0]

Pixel 1

R0[9:5] G1[4:0]

Pixel 2

R1[9:5] G2[4:0]

Pixel 3

R2[9:5] G3[4:0] R3[9:5]

Q[12:8]

Q[7:3] val val

B0[9:5] R0[4:0] B1[9:5] R1[4:0] B2[9:5] R2[4:0] B3[9:5] R3[4:0]

B0[4:0] G0[9:5] B1[4:0] G1[9:5] B2[4:0] G2[9:5] B3[4:0] G3[9:5]

ODCK

DE

HSYNC,

VSYNC val blank val val val

Figure 8.11. 15-Bit Output 4:4:4 Timing Diagram

val val

Q[17:14] blank val

Pixel 0 Pixel 1 Pixel 2 Pixel 3

G0[3:0] R0[7:4] G1[3:0] R1[7:4] G2[3:0] R2[7:4] G3[3:0] R3[7:4]

Q[13:10] val B0[7:4] R0[3:0] B1[7:4] R1[3:0] B2[7:4] R2[3:0] B3[7:4] R3[3:0] val val blank val val

Q[9:6]

ODCK

DE

HSYNC,

VSYNC val B0[3:0] G0[7:4] B1[3:0] G1[7:4] B2[3:0] G2[7:4] B3[3:0] G3[7:4] val val

Figure 8.12. 12-Bit Output 4:4:4 Timing Diagram

val blank val val val val val val blank val val val val val val blank val val val val blank val val val val val val val

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 57

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.2. I

2

C Interfaces

8.2.1. HDCP E-DDC / I

2

C Interface

The HDCP protocol requires values to be exchanged between the video transmitter and video receiver. These values are exchanged over the DDC channel of the DVI interface. The E-DDC channel follows the I

2

C serial protocol. The

SiI9233A device is the video receiver in a system design using an SiI9233A receiver, and it has a connection to the

E-DDC bus with a slave address of 0x74. The I

2

C read operation is shown in Figure 8.13

, and the write operation in

Figure 8.14

.

Bus Activity :

Master

Slave Address Register Address Slave Address

DSDA Line S S

A

C

K

A

C

K

Figure 8.13. I

2

C Byte Read

Slave Address Register Address

A

C

K

Data

No

A

C

K

P

Bus Activity :

Master

Data

DSDA Line S P

A

C

K

Figure 8.14. I

2

C Byte Write

A

C

K

A

C

K

Multiple bytes can be transferred in each transaction, regardless of whether they are reads or writes. The operations

are similar to those in Figure 8.13

and Figure 8.14

except that there is more than one data phase. An ACK follow each

byte except the last byte in a read operation. Byte addresses increment, with the least significant byte transferred first, and the most significant byte last. See the I

2

C specification for more information.

There is also a “Short Read” format, designed to improve the efficiency of Ri register reads (which must be done every

two seconds while encryption is enabled). This transaction is shown in Figure 8.15

. Note that there is no register

address phase (only the slave address phase), because the register address is reset to 0x08 (Ri) after a hardware or software reset, and after the STOP condition on any preceding I

2

C transaction.

Ri Msb

Bus Activity:

Master

DSDA Line

S

Slave Address Ri Lsb

A

C

K

Figure 8.15. Short Read Sequence

A

C

K

No

A

C

K

P

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

58 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

8.2.2. Local I

2

C Interface

The SiI9233A receiver has a second I

2

C port accessible only to the controller in the display device. It is separate from the E-DDC bus. The SiI9233A receiver is a slave device that responds to six binary I

2

C device addresses of seven bits each. This I

2

C interface only supports the read operation shown in Figure 8.13

on the previous page, and the write

operation shown in Figure 8.14 on the previous page. It does not support the short read operation shown in Figure 8.15

on the previous page. Note that the I

2

C data pin for the local I

2

C bus is CSDA, instead of the DSDA pin shown in these figures.

The local I

2

C interface on SiI9233A pins CSCL and CSDA is a slave interface that can run up to 400 kHz. This bus is used to configure and control the receiver by reading/writing to necessary registers.

The local I

2

C interface consists of 5 separate I

2

C slave addresses. Therefore, it appears as 5 separate devices on the I

2

C local bus. The first two of these addresses, used for HDMI Control and general low level register control, are fixed, and can only be set to one of two values by using the CI2CA pin.

Table 8.11

shows the address selected for each state of the

CI2CA pin at reset. The other 3 addresses (used for CEC, EDID, and xvYCC) have an I

2

C register programmable address mapped into the HDMI Control register space, so the default value can be changed if there is a bus conflict with another device.

Table 8.11. Control of the Default I

2

C Addresses with the CI2CA Pin

Register Group

HDMI Control and low level registers (fixed)

CI2CA = LOW

0x60 & 0x68

CI2CA = HIGH

0x62 & 0x6A

The HDMI Control and low level registers are fixed after reset based on CI2CA pin and cannot be changed. The I

2

C slave address for the xvYCC registers, EDID Control registers, and the CEC Control registers each have a register associated with them that allows the address to be changed. See the Programmer Reference for more information.

8.2.3. Video Requirement for I

2

C Access

The SiI9233A receiver does not require an active video clock to access its registers from either the E-DDC port or the local I

2

C port. Read-Write registers can be written and then read back. Read-only registers that provide values for an active video or audio stream return indeterminate values if there is no video clock and no active syncs.

Use the SCDT and CKDT register bits to determine when active video is being received by the chip.

8.2.4. I

2

C Registers

The register values that are exchanged over the HDMI DDC I

2

C serial interface with the receiver for HDCP are described in the HDCP 1.3 Specification in Section 2.6 – HDCP Port. Refer to the Programmer Reference for details on these and all other SiI9233A registers.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 59

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9. Design Recommendations

The following information is provided as recommendations that are based on the experience of Lattice Semiconductor engineers and customers. If you choose to deviate from these recommendations for a particular application, Lattice

Semiconductor strongly suggests that you contact one of its technical representatives for an evaluation of the change.

9.1. Power Control

The low-power standby state feature of the SiI9233A receiver provides a design option of leaving the chip always powered, as opposed to powering it on and off. Leaving the chip powered and using the PD# register bit to put it in a lower power state can result in faster system response time, depending on the system Vcc supply ramp-up delay.

9.2. Power-on Sequencing

Due to timing considerations with the power-on reset circuits within the chip, Lattice Semiconductor recommends that

5 V power be available to the device before the 3.3 V and 1.2 V VCC supplies are enabled. If the 3.3 V and 1.2 V supplies reach their operating levels before the 5 V power supply to the power island, the chip may not reset properly.

9.3. Power Pin Current Demands

The limits shown in Table 9.1

indicate the current demanded by each group of power pins on the SiI9233A device.

These limits were characterized at maximum VCC, 0 °C ambient temperature and for fast-fast silicon. Actual application current demands can be lower than these figures, and varies with video resolution and audio clock frequency.

Table 9.1. Maximum Power Domain Current versus Video Mode

Mode

480p

1080i

1080p

[email protected]

1

ODCK (MHz)

27.0

74.25

148.5

225

IOVCC33

52

116

226

314

3.3 V Power Domain Currents (mA)

AVCC33

62

62

62

62

XTALVCC33

2

2

2

2

Mode

480p

1080i

ODCK (MHz)

27.0

74.25

AVCC12

93

91

1.2 V Power Domain Currents (mA)

CVCC12 APVCC12

53

92

3

3

1080p

[email protected]

1

148.5

225

126

107

167

210

3

3

Notes:

1. Measured with 12-bits/pixel video data.

2. Measured with 192 kHz, 8-channel audio, except for 480p mode which used 48 kHz, 8-channel audio.

3. Measured with RGB input, vertical black-white/1-pixel stripe (Moire2) pattern, converting to YCbCr output (digital for IOVCC33).

4. Only one core can be selected at a time. The TMDSxSEL register bit turns off the unselected core, except for the termination to

AVCC33.

AVCC33 current includes 40 mA for the unselected TMDS core. Only 5 mA of this current is dissipated as power in the receiver; the remainder is dissipated in the HDMI transmitter. The AVCC33 current on the unselected core can be reduced to 5 mA by asserting the corresponding PD_TERMx# register bit.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

60 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.4. HDMI Receiver DDC Bus Protection

The VESA DDC Specification (see the References section on page 72) defines the DDC I

signaling path. The I

2

2

C interconnect bus to be a 5 V

C pins on the SiI9233A chip are 5 V tolerant. And these pins are true open-drain I/O. The pull-up

resistors on the DDC bus should be pulled up using the 5 V supply from the HDMI connector. Refer to Figure 9.9

on page 68.

9.5. Decoupling Capacitors

Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown

schematically in Figure 9.4

on page 64. Place these components as closely as possible to the SiI9233A pins and avoid

routing through vias. Figure 9.1

shows the various types of power pins on the receiver.

VCC

C1 C2

L1

VCC

Ferrite

GND

C3

Via to GND

Figure 9.1. Decoupling and Bypass Capacitor Placement

9.6. ESD Protection

The SiI9233A chip is designed to withstand electrostatic discharge to 2 kV. In applications where higher protection levels are required, ESD limiting components can be placed on the differential lines coming into the chip. These components typically have a capacitive effect, reducing the signal quality at higher clock frequencies on the link. Use of the lowest capacitance devices is suggested; in no case should the capacitance value exceed 5 pF.

Series resistors can be included on the TMDS lines (see Figure 9.9

on page 68) to counteract the impedance effects of

ESD protection diodes. The diodes typically lower the impedance because of their capacitance. The resistors raise the impedance to stay within the HDMI specification centered on a 100-Ω differential.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 61

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.7. HDMI Receiver Layout

The SiI9233A chip should be placed as closely as possible to the input connectors that carry the TMDS signals. For a

system using industry-standard HDMI connectors (see Table 10.1 on page 71), the differential lines should be routed as

directly as possible from connector to receiver. Lattice Semiconductor receivers are tolerant of skews between differential pairs, so spiral skew compensation for path length differences is not required. Each differential pair should be routed together, minimizing the number of vias through which the signal lines are routed. The distance separating the two traces of the differential pair should be kept to a minimum.

Follow these layout guidelines to achieve the optimal input TMDS signal quality:

1.

Lay out all differential pairs with controlled impedance of 100

differential.

2.

3.

Cut out all copper planes (ground and power) that are less than 45 mils underneath the TMDS traces near the

receiver with dimensions as shown as shown in Figure 9.2

.

If ESD suppression devices or common mode chokes are used, place them near the HDMI connector, away from the

SiI9233A IC. Do not place them over the ground and power plane cutout near the receiver.

0.3 inch

> 0.1 inch

HDMI Receiver

> 0.1 inch

Ground and Power plane cut-out for copper planes <45 mil separation from TMDS traces

Figure 9.2. Cut-out Reference Plane Dimensions

In Figure 9.3 on the next page, which is a representation of a PCB containing HDMI connectors and the receiver, note

the sixteen TMDS traces connected directly from the HDMI connectors (left) to the SiI9233A pins (right). Trace impedance should be 100

differential in each pair and 50

single-ended if possible. Trace width and pitch depends on the PCB construction. Not all connections are shown; the drawing demonstrates routing of TMDS lines without

crossovers, vias, or ESD protection. Refer also to Figure 9.9

on page 68.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

62 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

DDC#0 DDC#1

+5V

PIN 19

PIN 1

HDMI Port

#0

Connector

HDMI Port

#1

Connector

PIN 19 text text text

10 text text text text text text text text text text text text text text

19

+5V

DDC#1

R1PWR5V

R0PWR5V text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text

SiI9233A text

10 text text text text text text text text text

19 text text text text text text text

PIN 1

Drawing is not to exact scale. Refer to

HDMI connector specification for exact dimensions.

Figure 9.3. HDMI to Receiver Routing – Top View

9.8. EMI Considerations

Electromagnetic interference is a function of board layout, shielding, receiver component operating voltage, and frequency of operation, among other factors. When attempting to control emissions, do not place any passive components on the differential signal lines (aside from any essential ESD protection as described earlier). The differential signaling used in HDMI is inherently low in EMI as long as the routing recommendations noted in the

Receiver Layout section are followed.

The PCB ground plane should extend unbroken under as much of the SiI9233A chip and associated circuitry as possible, with all ground pins of the chip using a common ground.

9.9. Typical Circuit

Representative circuits for application of the SiI9233A chip are shown in Figure 9.4

through Figure 9.8

on pages 64

through 67. For a detailed review of your intended circuit implementation, contact your Lattice Semiconductor

representative.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 63

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.9.1. Power Supply Decoupling

AVCC_3. 3V

Ferrite

220 @100MHz

+3.3 V

+1.2 V

AVCC33

0.1

F

10

F

0.1

F 0.1

F 0.1

F 1 nF 1 nF 1 nF

GND

Place ceramic capacitors close to VCC pins .

IOVCC33

10

F 10

F

0.1

F 0.1

F 0.1

F 0.1

F 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF

GND

Place ceramic capacitors close to VCC pins .

CVCC 12

10

F 10

F

0.1

F 0.1

F 0.1

F 0.1

F 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF

1 nF

GND

SiI9233A

+1.2 V

0.56

1% 0.82

Ferrite

H, 150 mA

AVCC12

10

F

0.1

F 0.1

F 0.1

F

1 nF 1 nF 1 nF

+1.2 V

+3.3 V

AGND

Ferrite

[email protected] MHz

Ferrite

[email protected] MHz

APVCC12

XTALVCC33

+5 V

SBVCC 5

Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic

The ferrite on AVCC33 attenuates noise above 10 kHz. A parasitic resistor helps to minimize the peaking. An example of a surface-mount device is the MLF2012 Series SMD inductors from TDK.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

64 SiI-DS-1061-C

9.9.2. HDMI Port Connections

RX2+ n

RX2- n

RX1+ n

RX1- n

RX0+ n

RX0- n

RXC+ n

RXC- n

HDMI

Connector

Port n

CEC n

HPD n

+5V n

47 k

47 k

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

RnX2+

RnX2-

RnX1+

RnX1-

RnX0+

RnX0-

RnXC+

RnXC-

CEC_A

HPDn

SiI9233A

SCL n

SDA n

Figure 9.5. HDMI Port Connections Schematic

Note: Repeat the schematic for each HDMI input port on the SiI9233A receiver.

DSCLn

DSDAn

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 65

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.9.3. Digital Video Output Connections

SiI9233A

INT

22

Q 0

Q 1

73

DE

HSYNC

VSYNC

ODCK

75

74

76

96

95

94

Q 2

Q 3

93

92

Q 4

Q 5

91

90

Q 6

Q 7

89

88

Q 8

Q 9

85

84

Q10

Q11

83

Q12

82

81

Q13

Q14

Q15

Q16

Q17

Q18

Q19

70

69

Q20

Q21

Q22

Q23

80

79

78

77

68

67

66

65

64

Q24

Q25

63

62

Q26

Q27

59

58

Q28

Q29

Q30

57

56

Q31

Q32

55

54

Q33

Q34

53

52

Q35

51

33

33

33

33

33

Microcontroller

33

33

33

33

33

Figure 9.6. Digital Display Schematic

The 3.3 V to the level-shifters and pull-up resistors should be powered-down whenever the 3.3 V is powered-down on the receiver itself.

The receiver INT output can be connected as an interrupt to the microcontroller, or the microcontroller can poll register 0x70 (INTR_STATE) to determine if any of the enabled interrupts have occurred. Refer to the Programmer

Reference for details. The receiver VSYNC output can be connected to the microcontroller if it is necessary to monitor the vertical refresh rate of the incoming video.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

66 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.9.4. Digital Audio Output Connections

+3.3V

Ferrite

0.1

F 0.01

F

18 pF

SiI9233A

XTALVCC

XTALIN

SCK

WS

SD[3:0]

SPDIF

DCLK

DR[ 2:0]

DL[ 2:0]

MCLKOUT

MUTEOUT

33

1 M

 27.00

MHz

18 pF

Place crystal circuit as closely to package as possible.

XTALOUT

9.9.5. Control Signal Connections

Figure 9.7. Audio Output Schematic

+3.3V

SiI9233A

CSDA

CSCL

EVEN/ODD Field

4.7

k

4.7

k

CSDA

CSCL

EVNODD

RSVDL

4.7 k

Microcontroller

GPIO

GPIO

GPIO

Sync status and interrupt bits may be polled through CSDA/CSCL I

2

C port.

RESET#

SCDT

INT

GPIO

Firmware monitors Hot Plug Detect signal to trigger EDID re-read and inhibit HDCP authentication attempts.

Figure 9.8. Controller Connections Schematic

HPD

HDMI

Connector

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 67

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

9.10. Layout—TMDS Input Port Connections

Figure 9.9

shows an example of routing TMDS lines between the SiI9233A device and the HDMI connector.

DDC SCL

DDC SDA

Hot Plug

Detect

Connector

Shell

+5V Power

DDC Ground

Reserved NC

CEC

TMDS Clock-

TMDS Clock

Shield

TMDS

Clock+

Figure 9.9. TMDS Input Signal Assignments

TMDS Data 2+

TMDS Data 2-

TMDS Data 1+

TMDS Data 1-

TMDS Data 0+

TMDS Data 0-

TMDS Data Shield

TMDS Data Shield

TMDS Data Shield

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

68 SiI-DS-1061-C

10. Package Information

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

10.1. ePad Requirements

The SiI9233A receiver is packaged in a 144-pin, 20 mm × 20 mm TQFP package with an exposed pad (ePad) that is used for the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are

4.445 mm × 4.0604 mm ±0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground.

A clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid the possibility of electrical shorts.

The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.

Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately

0.1 mm the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal land.

Figure 10.1

on the next page shows the package dimensions of the SiI9233A receiver device.

10.2. PCB Layout Guidelines

Refer to Lattice Semiconductor document PCB Layout Guidelines: Designing with Exposed Pads (see the References

section

on page 72) for basic PCB design guidelines when designing with thermally enhanced packages using the

exposed pad. This application note is intended for use by PCB layout designers.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 69

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

10.3. Package Dimensions

These drawings are not to scale.

D

D

1

4.064 ± 0.15

D

108 73

109 72

E

2

A B

E

1

E

H

R

1

R

2

S

L

1

L

SECTION A-A

.25

GAGE PLANE

A A

144

Pin 1

Identifier 1

0.05

A

A

2

A

1

Item Description

A Thickness

A1 Stand-off

A2 Body thickness

D

E

Footprint

Footprint

D

1

Body size

E

1

Body size

D

2

Lead Row Width

E

2

Lead Row Width

Dimensions in millimeters.

Overall thickness A = A1 + A2.

37 e b

D

2

TOP VIEW

0.08

M

C A B D

36

0.20

C A B

0.20

H A B D

D

C

0.08

C

SIDE VIEW

JEDEC Package Code MS-026-AFB

Seating Plane

Min

1.00

0.05

0.95

Typ

1.10

0.10

1.00

22.00 BSC

22.00 BSC

20.00 BSC

20.00 BSC

17.5 BSC

17.5 BSC

Max Item Description

1.20 b Lead width

0.15

1.05

C e

Lead thickness

Lead pitch

L

L

1

R

1

R

2

S

Lead foot length

Total lead length

Lead radius, inside

Lead radius, outside

Lead horizontal run

Figure 10.1. 144-Pin TQFP Package Diagram

Min

0.17

0.09

0.45

0.08

0.08

0.20

Typ

0.22

0.50 BSC

0.60

1.00 REF

Max

0.27

0.20

0.75

0.20

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

70 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

10.4. Marking Diagram

Figure 10.2

shows the markings of the SiI9233A package. Figure 10.1

on the previous page shows the package and

dimension details.

SiI9233ACTU

LLLLLL.LL-L

YYWW

AH12 X D2

Logo

Product Line

Silicon Image Part Number

Lot # (= Job#)

Date code

Trace code

Pin 1 location

Legend

LLLLLLL

YY

WW

AH12 X D 2

Universal Packages

SiI9233ACTU

Description

Lot Number

Year of Mfr

Week of Mfr

Trace Code:

X

Bond wire

K gold

A gold

N copper

P copper

Figure 10.2. Marking Diagram

10.5. Ordering Information

Table 10.1

gives ordering information for the SiI9233A HDMI receiver device.

Table 10.1. SiI9233A HDMI Receiver Device Ordering Information

Part Number Pixel Clock Range Interface Bond Wire

Resolution/

Refresh Rate

SiI9233ACTU 25 MHz – 225 MHz HDMI Gold 1080p/60 Hz

SiI9233ACTU-C 25 MHz – 225 MHz HDMI Copper 1080p/60 Hz

The universal package may be used in lead-free and ordinary process lines.

Package

144-pin

TQFP ePad

144-pin

TQFP ePad

Temperature Grade

Extended (–30 °C to +85 °C)

Extended (–30 °C to +85 °C)

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 71

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

References

Standards Documents

This is a list of the standards abbreviations appearing in this document.

Abbreviation Standards publication, organization, and date

HDMI

HCTS

HDCP

E-EDID

E-DID IG

CEA-861

CEA-861-B

CEA-861-D

EDDC

High Definition Multimedia Interface, Revision 1.3, HDMI Consortium; June 2006

HDMI Compliance Test Specification, Revision 1.3c, HDMI Consortium; July 2008.

High-bandwidth Digital Content Protection, Revision 1.3, Digital-Content Protection, LLC; December 2006.

Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000.

VESA EDID Implementation Guide, VESA; June 2001.

A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; January 2001.

A DTV Profile for Uncompressed High Speed Digital Interfaces, Draft 020328, EIA/CEA; March 2002.

A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; July 2006.

Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004.

For information on the specifications that apply to this document, contact the responsible standards groups appearing on this list.

Standards Group

ANSI/EIA/CEA

VESA

DVI

Web URL

http://global.ihs.com

http://www.vesa.org

http://www.ddwg.org

HDCP

HDMI http://www.digital-cp.com

http://www.hdmi.org

Lattice Semiconductor Documents

This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The

Programmer Reference requires an NDA with Lattice Semiconductor.

Document

SiI-PR-1033

SiI-PR-0041

SiI-AN-0129

Title

SiI9223A/9233A/9127A HDMI Receivers Programmer Reference

CEC Programming Interface (CPI) Programmer Reference

PCB Layout Guidelines: Designing with Exposed Pads

Technical Support

For assistance, submit a technical support case at www.latticesemi.com/techsupport .

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

72 SiI-DS-1061-C

SiI9233A HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color

Data Sheet

Revision History

Revision C, March 2016

Formatted to latest template.

Revision C, November 2013

1.

2.

Updated Figure 10.2. Marking Diagram to show trace code information.

Added

Table 10.1. SiI9233A HDMI Receiver Device Ordering Information

3.

Updated layout by repositioning the Revision History section .

Revision B, December 2012

Added local I

2

C device addresses.

.

Revision A07, August 2010

Removed Patent information from DB, rolled the revision.

Revision A06, April 2010

Update to create Data Brief.

Revision A05, September 2009

Minor corrections; updated with 3D information.

Revision A04, June 2009

Update T

CK2OUT

and related values; update additional content.

Revision A03, February 2009

Removed audio downsampling, output delay control, and video output pull-down information.

Revision A02, January 2009

Clarify POR requirement; provided RnPWR5V power requirement; minor corrections.

Revision A01, October 2008

Removed references to Mobile HD.

Revision A, October 2008

Initial production release.

© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1061-C 73

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T 503.268.8000 www.latticesemi.com

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