Digital Audio Delay

Digital Audio Delay
NJU26904
Digital Audio Delay
■ General Description
■Package
The NJU26904 offers digital audio delay.
The NJU26904 has internal delay memory. Delay function can adjust output
time of a six-channel signal.
This delay functions are suitable for delay time adjustment such as Audio
products and time alignment such as Car Audio.
■ FEATURES
NJU26904V-C2
• 6-channel Digital Audio Delay
Delay Time 84msec for monaural channel, 42msec for stereo channel at Fs=96kHz
Delay Time 169msec for monaural channel, 85msec for stereo channel at Fs=48kHz
Delay Time 254msec for monaural channel, 127msec for stereo channel at Fs=32kHz
• Delay data width is 24 bits.
Digital Audio Format: I2S 24bit, Left-Justified, Right-Justified, BCK: 32/64fs
• Adjustable Delay Time with 1sample units for 8,121 samples at maximum.
• Selectable input sources for each channel output freely.
• To make long delay time, the NJU26904 can be connected serially.
• Non-Audio Format is possible.
- Hardware
• Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Digital Audio Format
: I2S 24bit, Left- Justified, Right-Justified, BCK : 32/64fs
• Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
• Host Interface
: I2C bus (Fast-mode/400kbps)
• Power Supply
: 3.3V
• Input terminal
: 5V Input tolerant
• Package
: SSOP24-C2 (Pb-Free)
Ver.2008-12-02
-1-
NJU26904
■ Function Block Diagram
SCL
SDI0-2
I2C INTERFACE
SDA
SDO0-2
HOST CONTROL
BCK
RESETb
SERIAL AUDIO
INTERFACE
MCK
CLKOUT
TIMING
GENERATOR /
PLL
CLK
LR
ADDRESS GENERATION UNIT
SLAVEb
Internal Pow er
(1.8V)
Built-in LDO
WDC
Delay RAM
VREGO
External
Low -ESR
Capacitors
Required
GPIO
INTERFACE
AD2
AD1
1.8V level terminal
Fig. 1 NJU26904 Block Diagram
-2-
Ver.2008-12-02
NJU26904
■ DSP Block Diagram
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO0_L
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO0_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
Delay Memory
SDO1_L
Free dividing
SDO1_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO2_L
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO2_R
Fig. 2 NJU26904 Function Diagram
Ver.2008-12-02
-3-
NJU26904
■ Pin Configuration
RESETb
1
24
TEST
LR
2
23
SCL
BCK
3
22
SDA
SDI2
4
21
SDO2
SDI1
5
20
SDO1
19
SDO0
18
WDC
NJU26904
SDI0
6
MCK
7
VDD
8
17
AD2
VSS
9
16
AD1
STBYb
10
15
SLAVEb
VSS
11
14
CLK
VREGO
12
13
CLKOUT
SSOP24-C2
Fig. 3 NJU26904 Pin Configuration
■ Pin Description
Table 1 Pin Description
No. Symbol
I/O Description
No. Symbol
I/O Description
1
RESETb I
RESET (active Low)
13
CLKOUT
O
OSC Output
2
LR
I/O LR Clock
14
CLK
I
OSC Clock Input
3
BCK
I/O Bit Clock
15
SLAVEb
I
Slave select
4
SDI2
I
Audio Data Input 2 L/R
16
AD1
I
I2C Address 1
5
SDI1
I
Audio Data Input 1 L/R
17
AD2
I
I2C Address 2
6
SDI0
I
Audio Data Input 0 L/R
18
WDC
OD Clock for Watch Dog Timer
7
MCK
I/O Master Clock
19
SDO0
O
Audio Data Output 0 L/R
8
VDD
Power Supply +3.3V
20
SDO1
O
Audio Data Output 1 L/R
9
VSS
GND
21
SDO2
O
Audio Data Output 2 L/R
10
STBYb
I
For TEST (Connected to VDD)
22
SDA
OD I2C I/O
11
VSS
GND
23
SCL
I
I2C Clock
12
VREGO PI
Built-in Power Supply Bypass
24
TEST
I
For TEST(Connected to VSS)
* I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass
AD1 (No.16) pin and AD2 (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance. However,
these pins operate as bi-directional pins. No.11pin and No.12pin connect with VDD or VSS through 3.3kΩ resistance.
No.18pin do not connect or connect with VDD through 3.3kΩ resistance when unused.
VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel
between VSS (No.11) pin. A built-in power supply is used only for NJU26904 operation. Be not short-circuited of this pin.
Do not take out the current, and connect other power supplies.
-4-
Ver.2008-12-02
NJU26904
■
Absolute Maximum Ratings
( VSS=0V=GND, Ta=25°°C )
Rating
Units
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage *
Supply Voltage Bypass *
VDD
VREGO
-0.3 to 4.2
-0.3 to 2.3
In
Vx(IN)
I/O, OD
Vx(I/O) ,Vx(OD)
-0.3 to 5.5 (VDD ≥ 3.0V)
-0.3 to 4.2 (VDD < 3.0V)
Out
Vx(OUT)
-0.3 to 4.2
CLK
Vx(CLK)
CLKOUT
Vx(CLKOUT)
Pin Voltage *
V
V
V
-0.3 to 4.2
Power Dissipation
Operating Voltage
Storage Temperature
565
mW
PD
-40 to 85
TOPR
°C
TSTR
-40 to 125
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* VDD
: 8 pin
* VREGO
: 12 pin
* Vx(IN)
: 1, 4, 5, 6, 10, 15, 23, 24 pin
* Vx(OD)
: 22 pin
* Vx(I/O)
: 2, 3, 7, 16, 17, 18 pin
* Vx(OUT)
: 19, 20, 21 pin
* Vx(CLK)
: 14 pin
* Vx(CLKOUT)
: 13 pin
■ Terminal equivalent circuit diagram
VDD
VDD(1.8V)
CLK
CLKOUT
VDD
VDD(1.8V)
PAD
RPD
VSS
V
SS
Input, I/O (Input part)
(1 to 7, 22, 23pin)
(With RPU: 18pin With RPD: 15, 16, 17, 24pin)
CLK/CLKOUT
(13, 14pin)
VDD
RPU
VDD
PAD
PAD
Output Disable
VSS
Output, I/O (Output part)
(2, 3, 7, 16, 17, 19, 20, 21pin )
( Open Drain Output with RPU : 18pin)
( Open Drain Output: 22pin )
VSS
STBYb
(10pin)
Fig.4 NJU26904 Terminal equivalent circuit diagram
Ver.2008-12-02
-5-
NJU26904
■ Electric Characteristics
( VDD=3.3V, fOSC=12.288MHz, Ta=25°°C )
Table 3 Electric Characteristics
Parameter
Operating Voltage
Symbol
*1
Test Condition
Min.
Typ.
Max.
Units
3.0
3.3
3.6
V
-
20
35
mA
VDD
VDD pin
Operating Current
IDD
At no load
High Level Input Voltage
VIH
VDD x 0.7
-
VDD
Low Level Input Voltage
VIL
0
-
VDD x 0.3
High Level Output Voltage
Low Level Output Voltage
*3
Clock Frequency
Clock Jitter
*5
Clock Duty Cycle
*4
V
VOH
(IOH= -1mA)
VDD x 0.8
-
VDD
VOL
(IOL= 1mA)
0
-
VDD x 0.2
-10
-
10
-120
-
10
IIN(PD)
-10
-
120
fOSC
10
12.288
13
MHz
0
-
3.0
ns
45
50
55
%
IIN
Leakage Current
*2
IIN(PU)
fJIT(CC)
rEC
VIN = VSS to VDD
CLK, MCK
*6
µA
*1 Supply voltage must be within recommended operating voltage. Furthermore supplying power voltage must be
linear, quick and smooth to prevent abnormal operation. Once the power supply is set up, supply voltage must be kept
within the operating voltage range. After setting up the power supply, even if the supply voltage dropped off and
recovered to normal range, reset function and the all following operations can not be guaranteed. After using this
DSP, power supply must be dropped to VSS level.
*2
*3
*4
*5
*6
Input pin, Output pin and Open-Drain input/output pin are +5.0V tolerant except CLK input pin.
Except No.18pin: WDC (Open-Drain output) and No.22: SDA (Open-Drain input/output).
I IN(PU) : 18pin, I IN(PD) : 15, 16, 17, 24 pin
Clock Jitter shows Cycle-to-cycle period jitter (JEDEC JESD65).
Provide clock frequency for fOSC spec. NJU26904 needs clock frequency 12.288MHz when sampling rate is 48kHz.
-6-
Ver.2008-12-02
NJU26904
1. Power Supply, Input/Output terminal, Clock, Reset
1.1 Power Supply
The NJU26904 has a power supply VDD. To setup good power supply condition, the decoupling capacitors
should be implemented at the all power supply terminals.
The NJU26904 include a built-in power supply (LDO) for internal logic. A built-in power supply generates
1.8V (-10% to +10%). VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR
capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin.
A built-in power supply is used only for NJU26904 operation. Be not short-circuited of this pin. Do not take
out the current, and connect other power supplies.
1.2 Input/Output terminal
It restricts, when the input terminals (AD1, AD2, RESETb, SDI0, SDI1, SDI2, STBYb, SLAVEb, SCL,
TEST pins), the input/output terminals (LR, BCK, MCK pins) and the bi-directional Open-drain terminal
(SDA pin) of NJU26904, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input
tolerant.
1.3 Clock
The NJU26904 CLK pin requires the system clock. The system clock is usually 12.288MHz into CLK pin.
It is possible to be generated the system clock by connecting a crystal oscillator between CLK and
CLKOUT. CLK/CLKOUT pins are not 5V tolerant, so check the voltage level of these pins.
When SLAVEb pin is fixed on Low level, NJU26904 supplies the system clock from MCK pin. Fix the clock
input pin not used to Low level because either the CLK pin or the MCK pin is supplied in NJU26904.
The frequency divider for Master mode matched to the clock 256 times of Fs is installed in NJU26904.
When clock except 256 times of Fs is used by Master mode, be careful to use because a dividing
frequency of Master mode changes. Please check enough and decide parameter.
Ver.2008-12-02
-7-
NJU26904
1.4 Reset
To initialize the NJU26904, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26904. After
the power supply and the oscillation of the NJU26904 becomes stable, RESETb pin must be kept
Low-level more than tRESETb period. (Fig.5)
After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial
Host Interface completes NJU26904 within 10msec. Then, it will be in the state which can communicate.
VDD
tVREGO
VREGO
CLK
OSC unstable
OSC stable
tRESETb
RESETb
Fig.5 Reset Timing
Table 4 Reset Time
Symbol
Time
tVREGO
≥ 10msec
tRESETb
≥ 1.0msec
Note :
Don’t stop the supply of a clock while operating. NJU26904 installs PLL circuit internally. If the supply of a
clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26904 does not operate normally.
If supply of a clock is stopped or the NJU26904 is reset again, putting a normal clock into CLK terminal, the
period RESETb terminal of tRESETb is kept “Low” level.(Table 4) Next, the NJU26904 is reset. Then redo
from initial setting.
-8-
Ver.2008-12-02
NJU26904
2. Digital Audio Clock
Digital audio data needs to synchronize and transmit between digital audio systems.
The NJU26904 - master mode / slave mode - both of the modes are supported.
- In Master mode;
Use the clock of BCKO and a LRO pin output clock for digital audio data transfer.
- In Slave mode;
The clock output from a master device is needed for the input terminal of BCKI and LRI.
A device in the system generates the transmitted clock become a standard. The other devices are set
according to the transmitted clock. The device generating transmitted clock is called Master Device. The
device according to the transmitted clock is called Slave Device. NJU26904 usually operates Slave Device.
However, NJU26904 becomes Master Device in case of SLAVEb set the High level and NJU26904 is set
Master mode by firmware command. In Slave mode, clock inputted to the BCK pin and the LR pin is used
to digital audio signal transmission. In Master mode, clock outputted to the BCK pin and the LR pin is used
to digital audio signal transmission.
2.1 Audio Clock
Three kinds of clocks are needed for digital audio data transfer.
(1) LR clock (LR) is needed by serial-data transmission. It is the same as the sampling
frequency of a digital audio signal.
(2) Bit clock (BCK) is needed by serial-data transmission. It becomes the multiple of LR clock.
(3) Master clock (MCK) is needed by A/D, D/A converter, etc. It becomes the multiple of LR
clock. It is not related to serial audio data transmission.
In SLAVEb is High level, the MCK pin becomes buffer output pin for input clock to the CLK pin after
NJU26904 resets. The MCK output is able to be stopped by firmware command.
In SLAVEb is Low level, MCK pin becomes system clock input pin. It is not insure to change the logical
switch of SLAVEb pin during operating. If it is necessary to change SLAVEb pin setting, reset NJU26904
every time.
Table 5 SLAVEb, BCK, LR, MCK
SLAVEb and firmware
LR pin
setting
SLAVEb=”Low”
LR clock input
Firmware: each
DSP
slave operating
SLAVEb=”High”
Firmware: Slave
SLAVEb=”High”
Firmware: Master
LR clock output
DSP Master operating
BCK pin
Bit clock input
DSP slave operating
Bit clock output
DSP Master
operating
MCK pin
NJU26904 operating clock input
(MCK or CLK)
Master clock output
(Buffer of CLK)
In NJU26904 is used by 256 times of Maximum sampling frequency, NJU26904 is able to output LR clock
of same sampling rate and two-third times of sampling rate, and output BCK clock of 32 times sampling
rate and 64 times sampling rate in Master mode.
Ver.2008-12-02
-9-
NJU26904
Table 6 Input clock (In Slave mode at fosc=12.288MHz)
Multiple
Mode
Clock Signal
32kHz
44.1kHz
48kHz
96kHz
Frequency
LR
1fs
32kHz
44.1kHz
48kHz
96kHz
BCK (32fs)
32fs
1.024MHz 1.4112MHz 1.536MHz 3.072MHz
BCK
(64fs)
64fs
2.048MHz
2.822MHz 3.072MHz 6.144MHz
DSP
MCK
Slave
Input terminal: Clock is generated by MCK or CLK
(SLAVEb=”L”)
MCK
Buffer output of
12.288MHz
(SLAVEb=”H”)
CLK
Table 7 Output clock (In Master mode at fosc=12.288MHz)
Output from BCK/LR
Multiple
Mode
Clock Signal
Frequency
32kHz
48kHz
64kHz
LR
1fs
32kHz
48kHz
64kHz
DSP
BCK (32fs)
32fs
1.024MHz
1.536MHz
2.048MHz
Master
BCK (64fs)
64fs
2.048MHz
3.072MHz
4.096MHz
MCK
12.288MHz
- 10 -
192kHz
192kHz
6.144MHz
12.288MHz
96kHz
96kHz
3.072MHz
6.144MHz
Ver.2008-12-02
NJU26904
3. Digital Audio Interface
3.1 Digital Audio Data Format
The NJU26904 can use three kinds of formats hereafter as industry-standard digital audio data format.
: MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing)
(1) I2S
(2) Left-Justified : LR clock -- MSB is placed for changing.
(3) Right-Justified: LSB is placed just before LR clock change rate.
The main differences among three kinds of formats are in the position relation between LR clock (LR) and
an audio data (SDI, SDO).
- In every format:
: a left channel is transmitted previously.
- In Right/Left-Justified : LR clock ='High' shows a left channel.
- I2S
: LR clock=”Low” shows a left channel.
- The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than
the number of sum total transmission bits of a L/R channel is needed at least.
- One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes
equal to a sample rate (Fs).
- The NJU26904 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks.
This serial data format is applied to both MASTER and SLAVE mode.
3.2 Serial Audio Data Input/output
The NJU26904 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output
lines: SDO0, SDO1 and SDO2. (Table 9).
Table 8 Serial Audio Input Pin Description
Pin No. Symbol
Description
6
SDI0
Audio Data Input 0 L/R
5
SDI1
Audio Data Input 1 L/R
4
SDI2
Audio Data Input 2 L/R
Table 9 Serial Audio Output Pin Description
Pin No. Symbol
Description
19
SDO0
Audio Data Output 0 L/R
20
SDO1
Audio Data Output 1 L/R
21
SDO2
Audio Data Output 2 L/R
The input terminal is selectable for the output terminal freely.
Refer to Figure 2 NJU26904 Function Diagram.
Ver.2008-12-02
- 11 -
NJU26904
The NJU26904 can use three kinds of formats hereafter as industry-standard digital audio data format; (1)
I2S (2) Left-Justified (3) Right-Justified and 24 / 20 / 18 / 16bits data length. (Fig.6-1 to Fig6-12)
An audio interface input and output data format become the same data format.
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
LSB
MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI, SDO
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-1 I2S Data Format 64fs, 24bit Data
LRI, LRO
Left Channel
Right Channel
BCKI, BCKO
MSB
LSB
MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI, SDO
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
23
32 Clocks
Fig.6-2 Left-Justified Data Format 64fs, 24bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO 2 1 0
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-3 Right-Justified Data Format 64fs, 24bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
LSB
MSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI, SDO
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
2
Fig.6-4 I S Data Format 64fs, 20bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
19
32 Clocks
Fig.6-5 Left-Justified Data Format 64fs, 20bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO 2 1 0
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
MSB
LSB
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
Fig.6-6 Right-Justified Data Format 64fs, 20bit Data
- 12 -
Ver.2008-12-02
NJU26904
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
LSB
MSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI, SDO
LSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-7 I2S Data Format 64fs, 18bit Data
LRI, LRO
Left Channel
Right Channel
BCKI, BCKO
MSB
SDI, SDO
LSB
MSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
17
32 Clocks
Fig.6-8 Left-Justified Data Format 64fs, 18bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO 2 1 0
LSB
MSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 Clocks
32 Clocks
Fig.6-9 Right-Justified Data Format 64fs, 18bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks
16 Clocks
2
Fig.6-10 I S Data Format 32fs, 16bit Data
LRI, LRO
Left Channel
Right Channel
BCKI, BCKO
MSB
SDI, SDO
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks
16 Clocks
Fig.6-11 Left-Justified Data Format 32fs, 16bit Data
Left Channel
LRI, LRO
Right Channel
BCKI, BCKO
MSB
SDI, SDO
LSB MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 Clocks
16 Clocks
Fig.6-12 Right-Justified Data Format 32fs, 16bit Data
Ver.2008-12-02
- 13 -
NJU26904
3.3 Serial Audio Input Timing
Table 10 Serial Audio Input Timing Parameters
Parameter
Symbol
Test Condition
( VDD=3.3V, fosc=12.288MHz, Ta=25°°C )
Min
Typ.
Max
Units
BCK Frequency *
BCK Period
*
Low Pulse Width
High Pulse Width
BCK to LR Time **
fBCKI
-
-
13
MHz
tSIL
tSIH
tSLI
35
35
15
-
-
ns
-
-
ns
LR to BCK Time **
tLSI
15
-
-
ns
Data Setup Time
tDS
15
-
-
ns
Data Hold Time
tDH
15
-
-
ns
* It is the regulation of absolute maximum ratings. Maximum frequency of BCK is limited.
** It is the regulation in slave mode.
LR
tSIH
tSIL
tSLI
tDS
tDH
tLSI
BCK
SDI
Fig.7 Serial Audio Input Timing
Table 11 Serial Audio Output Timing Parameters
Parameter
Symbol
Test Condition
BCK to LR Time *
tSLO
Data Output Delay
tDOD
CL=25pF
Min
( VDD=3.3V, Ta=25°°C )
Typ.
Max
Units
-15
-
15
ns
-
-
15
ns
* It is the regulation in Master mode.
LR
tSLO
BCK
tDOD
SDO
Fig.8 Serial Audio Input Timing
- 14 -
Ver.2008-12-02
NJU26904
■ Host Interface
The NJU26904 can be controlled via Serial Host Interface (SHI) using I2C bus. Data transfers are in 8 bit
packets (1 byte) when using either format. Refer to serial Host Interface Pin Description.(Table 12)
Table 12 Serial Host Interface Pin Description
Symbol
Pin No.
I2C bus Format
(I2C bus)
16
AD1
I2C bus address Bit 1
17
AD2
I2C bus address Bit 2
Serial Data Input/Output
22
SDA
(Open Drain Input/Output)
23
SCL
Serial Clock
Note : SDA pin (No.22) is a bi-directional open drain terminal. This pin requires a pull-up resister.
AD1 (No.16) pin and AD2 (No.17) pin are input pins with pull-down. AD1 (No.16) pin and AD2 (No.17) pin are
connected with VDD or VSS through 3.3kΩ resistance.
When NJU26904 is stopped by power supply VDD, SDA pin and SCL pin become Hi-Z. But these pins are not
5V tolerant when VDD stops.
■ I2C bus
I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. SDA pin is a bi-directional open
drain and requires a pull-up resister.
AD1 pin and AD2 pin are used to configure the seven-bit SLAVE address of the serial host interface. (Table 13)
This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26904. An
address can be arbitrarily set up by the AD1 pin and AD2 pin. The I2C address of AD1 and AD2 pin are decided
by connection of AD1 pin and AD2 pin.
Table 13 I2C bus SLAVE Address
bit7
0
0
0
0
bit6
0
0
0
0
Start
bit
bit5
1
1
1
1
bit4
1
1
1
1
bit3
1
1
1
1
Slave Address ( 7bit )
AD2
bit2
0
0
1
1
AD1
bit1
0
1
0
1
R/W
bit
R/W
bit0
RW
ACK
* SLAVE address is 0 when AD1 and AD2 are “Low”.
SLAVE address is 1 when AD1 and AD2 are “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
Ver.2008-12-02
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NJU26904
( VDD=3.3V, fOSC=12.288MHz, Ta=25°°C )
Table 14 I2C bus Interface Timing Parameters
Parameter
Symbol
Min
Max
Units
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tBUF
0
0.6
1.3
0.6
0.6
0
250
0.6
1.3
400
0.9
1000
300
-
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
SCL Clock Frequency
Start Condition Hold Time
SCL “Low” Duration
SCL “High” Duration
Start Condition Setup Time
Data Hole Time *1
Data Setup Time
Rising Time
Falling Time
Stop Condition Setup Time
Bus Release Time *2
SDA
tR
tBUF
tF
tHD:STA
SCL
tHD:STA t LOW
P
tHD:DAT
tHIGH
tSU:STA
tSU:DAT
tSU:STO
Sr
S
P
2
Fig.9 I C bus Timing
Note :
*1 tHD:DAT: Keep data 100ns hold time to avoid indefinite state by SCL falling edge.
*2 This item shows the interface specification. The interval of a continuous command is
specified separately.
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Ver.2008-12-02
NJU26904
■ WatchDog Clock
The NJU26904 outputs clock pulse through WDC (No.18) pin during normal operation.
The NJU26904 generates a clock pulse through the WDC terminal after resetting the NJU26904. The WDC
clock is useful to check the status of the NJU26904 operation. For example, a microcomputer monitors the
WDC clock and checks the status of the NJU26904. When the WDC clock pulse is lost or not normal clock cycle,
the NJU26904 does not operate correctly. Then reset the NJU26904 and set up the NJU26904 again.
Watchdog clock output cycle is set by a command.
Note: If input and output of an audio signal stop and an audio interface stops, WDC can’t output.
That is because it has controlled based on the signal of an audio interface.
■ NJU26904 Command Table
Table 15 NJU26904 Command
No.
1
2
3
Command
System State Config
( MCK, BCK, CLK, Data width etc. )
I/O Config
( SDO Source Select, Setup SDO )
Delay Setup
( 8,121 samples, 1 sample step, Setup SDO )
No.
Command
8
SDO Input Select Config Read
9
SDO Delay Setup Read
10
Watchdog Setup Read
4
Watchdog Setup
11
Version Number
5
Re-Initialize Command
12
Software Reset
6
Task State Read
13
Auto Buffer Clear Disable / enable
7
System State Config Read
14
Start / Stop
.
Ver.2008-12-02
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NJU26904
■ Package
SSOP24-C2, Pb-Free
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 18 -
Ver.2008-12-02
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