Colibri iMX7 Datasheet

Colibri iMX7 Datasheet
Colibri iMX7
Datasheet
Colibri iMX7 Datasheet
Revision History
Date
Doc. Rev.
Colibri iMX7 Version
Changes
16-Feb-2016
Rev. 0.9
V1.1
Initial Release
15-Jun-2016
Rev. 1.0
V1.1
Minor changes and corrections
Remove SODIMM pin 157 and 163
Update maximum UART speed (section 5.10)
21-Dec-2016
Rev. 1.1
V1.1
Update maximum pixel clock frequency of Camera input
(section 5.21)
Information added that EPDC is currently not supported
(section 5.5.6)
13-Feb-2017
Rev. 1.2
V1.1
Changed heading to “Colibri Carrier Board Schematics”
(Section 1.4.6)
Updated web-links (section 1.3, 1.4, and 9.3.1)
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Colibri iMX7 Datasheet
Contents
1.
Introduction ................................................................................................................................................. 5
1.1
Hardware ....................................................................................................................... 5
1.2
Main Features ................................................................................................................ 6
1.3
1.4
1.2.1
CPU ....................................................................................................................... 6
1.2.2
Memory .................................................................................................................. 6
1.2.3
Interfaces ................................................................................................................ 6
1.2.4
Supported Operating Systems ................................................................................... 7
Interface Overview .......................................................................................................... 8
Reference Documents ..................................................................................................... 9
1.4.1
NXP (Freescale) i.MX 7 ............................................................................................ 9
1.4.2
Ethernet Transceiver ................................................................................................ 9
1.4.3
Audio Codec ........................................................................................................... 9
1.4.4
Touch Screen Controller / ADC .................................................................................. 9
1.4.5
Toradex Developer Center ........................................................................................ 9
1.4.6
Colibri Carrier Board Schematics ............................................................................... 9
1.4.7
Toradex Pinout Designer .......................................................................................... 9
2.
Architecture Overview ............................................................................................................................. 10
2.1
Block Diagram .............................................................................................................. 10
3.
Colibri iMX7 Connectors ......................................................................................................................... 11
4.
I/O Pins ...................................................................................................................................................... 17
4.1
Function Multiplexing ..................................................................................................... 17
4.2
Pin Control ................................................................................................................... 18
4.3
Pin Reset Status ........................................................................................................... 20
4.4
Functions List ............................................................................................................... 20
4.4.1
SODIMM 200 ........................................................................................................ 21
5.
Interface Description................................................................................................................................ 24
5.1
Power Signals .............................................................................................................. 24
5.2
5.1.1
Digital Supply ........................................................................................................ 24
5.1.2
Analogue Supply.................................................................................................... 24
5.1.3
Power Management Signals .................................................................................... 24
GPIOs ......................................................................................................................... 25
5.2.1
Wakeup Source ..................................................................................................... 25
5.3
Ethernet ....................................................................................................................... 26
5.4
USB ............................................................................................................................ 28
5.5
5.4.1
USB Data Signal .................................................................................................... 28
5.4.2
USB Control Signals............................................................................................... 28
Display ........................................................................................................................ 30
5.5.1
Parallel RGB LCD interface ..................................................................................... 30
5.5.2
LVDS ................................................................................................................... 33
5.5.3
HDMI.................................................................................................................... 33
5.5.4
Analogue VGA....................................................................................................... 33
5.5.5
Display Serial Interface (DSI) .................................................................................. 33
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Colibri iMX7 Datasheet
5.5.6
Electrophoretic Display Controller (EPDC) ................................................................ 33
5.6
PCI Express ................................................................................................................. 33
5.7
IDE.............................................................................................................................. 33
5.8
External Memory Bus .................................................................................................... 33
5.9
5.8.1
Non-Multiplexed Mode ............................................................................................ 34
5.8.2
Multiplexed Mode ................................................................................................... 34
5.8.3
Memory Bus Signals .............................................................................................. 35
I C............................................................................................................................... 37
2
5.9.1
Real-Time Clock (RTC) recommendation .................................................................. 38
5.10 UART .......................................................................................................................... 39
5.11 SPI .............................................................................................................................. 42
5.12 PWM (Pulse Width Modulation) ...................................................................................... 45
5.13 OWR (One Wire)........................................................................................................... 47
5.14 SD/MMC ...................................................................................................................... 47
5.15 Analogue Audio ............................................................................................................ 50
5.16 Audio Codec Interface ................................................................................................... 50
5.16.1
Digital Audio Port used as I S ............................................................................... 51
5.16.2
Digital Audio Port used as AC’97 .......................................................................... 52
2
5.17 Medium Quality Sound (MQS) ........................................................................................ 52
5.18 S/PDIF (Sony-Philips Digital Interface I/O) ....................................................................... 53
5.19 Touch Panel Interface.................................................................................................... 53
5.20 Analogue Inputs ............................................................................................................ 53
5.21 Camera Interface .......................................................................................................... 54
5.22 Clock Output ................................................................................................................ 57
5.23 Keypad ........................................................................................................................ 57
5.24 Controller Area Network (CAN) ....................................................................................... 59
5.25 Quad Serial Peripheral Interface (QuadSPI) ..................................................................... 60
5.26 JTAG ........................................................................................................................... 61
6.
Power Management ................................................................................................................................ 62
6.1
No Supply .................................................................................................................... 63
6.2
RTC Only ..................................................................................................................... 63
6.3
Shut Down ................................................................................................................... 63
6.4
RUN ............................................................................................................................ 63
6.5
Low Power ................................................................................................................... 63
6.6
LPSR........................................................................................................................... 64
7.
Recovery Mode ........................................................................................................................................ 65
8.
Known Issues ........................................................................................................................................... 66
9.
Technical Specifications ......................................................................................................................... 67
9.1
Absolute Maximum Ratings ............................................................................................ 67
9.2
Electrical Characteristics ................................................................................................ 67
9.3
Mechanical Characteristics ............................................................................................. 68
9.3.1
Sockets for the Colibri Modules ............................................................................... 68
9.4
Thermal Specification .................................................................................................... 68
9.5
Product Compliance ...................................................................................................... 69
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Colibri iMX7 Datasheet
1. Introduction
1.1 Hardware
The Colibri iMX7 is a computer module based on the NXP /Freescale i.MX 7 embedded System
®
on Chip (SoC). The SoC features a single or dual-core ARM Cortex A7 processor with an
®
®
additional ARM Cortex M4 processor. This heterogeneous dual-core system allows for running
a second real-time operating system on the M4 core for time and security critical tasks.
Despite the relative high computing performance, the Colibri iMX7 is designed for extremely
low-power consumption. The module features several low-power modes that reduce the
consumption in idle and sleep states.
The module targets a wide range of applications, including: medical devices, navigation,
industrial automation, HMIs, avionics, POS, data acquisition, robotics and much more.
It offers a wide range of interfaces from simple GPIOs, industry standard I2C, SPI, CAN, and
UART buses to high-speed USB 2.0 interfaces and a 16-bit external memory bus (multiplexed
parallel bus). Both Colibri iMX7 modules feature a Fast Ethernet PHY with IEEE1588 time
stamping on the module. Additionally, the Colibri iMX7D allows connecting an additional
(gigabit) Ethernet PHY on the customer carrier board by using the RGMII, RMII, or MII interface.
The Colibri iMX7 module encapsulates the complexity associated with modern day electronic
design, such as high-speed impedance controlled layouts with high component density
utilising blind and buried via technology. This allows the customer to create a simple carrier
board which provides his application-specific electronics. The module is compatible with a
wide range of other computer modules within the Colibri family. This allows the customer to
scale their product without the need to build different carrier boards for each project.
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Colibri iMX7 Datasheet
1.2 Main Features
1.2.1
CPU
Colibri iMX7D 512MB
Colibri iMX7S 256MB
NXP SoC
MCIMX7D5EVM10S
MCIMX7S5EVM08S
SoC Family
i.MX 7 Dual
i.MX 7 Solo
ARM Cortex-A7 CPU Cores
2
1
ARM Cortex-M4 CPU Cores
1
1
32KByte (A7)
32KByte (A7)
16KByte (M4)
16KByte (M4)
32KByte (A7)
32KByte (A7)
L1 Instruction Cache (each core)
L1 Data Cache (each core)
16KByte (M4)
16KByte (M4)
L2 Cache (shared by A7 cores)
512KByte (A7)
512KByte (A7)
Tightly-Coupled Memory for M4 Core
64KByte (M4)
64KByte (M4)
NEON MPE


1GHz (A7)
800MHz (A7)
200MHz (M4)
200MHz (M4)
ARM TrustZone


Advanced High Assurance Boot


Cryptographic Acceleration and Assurance Module


Secure Real-Time Clock


Secure JTAG Controller


Colibri iMX7D 512MB
Colibri iMX7S 256MB
DDR3L RAM Size
512MByte
256MByte
DDR3L RAM Speed
1066MT/s
1066MT/s
DDR3L RAM Memory Width
32bit
32bit
SLC NAND Flash (8bit)
512MByte
512MByte
Colibri iMX7D 512MB
Colibri iMX7S 256MB
LCD RGB (24bit, 150MHz)
1
1
Resistive Touch Screen
4 Wire
4 Wire
Analogue Audio Headphone out
1 (Stereo)
1 (Stereo)
Analogue Audio Line in
1 (Stereo)
1 (Stereo)
Analogue Audio Mic in
1 (Mono)
1 (Mono)
SAI (AC97/I S)
2* (Stereo)
2* (Stereo)
Medium Quality Sound (MQS)
1*
1*
Parallel Camera Interface
1
1
I2C
1+2*
1+2*
SPI
1+3*
1+3*
UART
3+4*
3+4*
SD/SDIO/MMC
1+1*
1+1*
Maximum CPU frequency
1.2.2
1.2.3
Memory
Interfaces
2
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Colibri iMX7 Datasheet
Colibri iMX7D 512MB
Colibri iMX7S 256MB
GPIO
Up to 124
Up to 124
USB 2.0 OTG (host/device)
1
1
USB 2.0 host
1
-
1
1
RGMII/RMII/MII interface for 2 Ethernet PHY on Baseboard 1
-
PWM
4+16*
4+16*
Analogue Inputs (maximum 1.8V)
4
4
CAN
2*
2*
External Memory Bus
16bit Multiplexed*
16bit Multiplexed*
QSPI
2*
2*
SIM
4*
4*
10/100 MBit/s Ethernet
nd
*These additional interfaces are available on pins that are not defined as standard interfaces in
the Colibri architecture. They are alternate functions for pins which provide primary interfaces.
There are restrictions on using different interfaces simultaneously. Please check the available
alternate functions to understand any constraints. For more information, please also check the
list in section 4.4.1 and the description of the associated interface in section 5.
1.2.4
Supported Operating Systems

Windows Embedded Compact 7 (Q4 2016)

Windows Embedded Compact 2013 (Q4 2016)

Embedded Linux

Green Hills Integrity available through Toradex partners

For other operating systems, please contact Toradex
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Colibri iMX7 Datasheet
1.3 Interface Overview
The table in Figure 1 shows the interfaces that are supported on the Colibri iMX7 module, and
whether an interface is provided as a standard (primary) function or as an alternate function.
The UART interface is an example of an interface that makes use of standard and alternate
functions – three UART interfaces are provided as standard functions which are compatible
with other Colibri modules while four additional interfaces are available as alternate functions.
Using alternate function UART interfaces limits the compatibility of the Colibri iMX7 module
with other Colibri modules. The alternate function of a pin can only be used if the standard
function is not used. Check section 4.4 for a list of all alternate functions of the SODIMM pins.
The Toradex Pinout Designer is a powerful tool for configuring the pin muxing of the Colibri
iMX7 Module. The tool allows comparing the interfaces of different Colibri modules. More
information to this tool can be found here:
http://developer.toradex.com/carrier-board-design/pinout-designer-tool
Feature
Total
Standard
Alternate Function
4 Wire Resistive Touch
1
1
Analogue Inputs
4
4 (limited to 1.8V)
Analogue Audio (Line in/out, Mic in)
1
1
Medium Quality Sound (MQS)
1
CAN
2
Fast Ethernet
1
RGMII/RMII/MII interface
1*
1*
GPIO
1
2
1
126
126
SAI (AC97/I2S)
2
2
I2C
3
1
Parallel Camera
1
1
Parallel LCD
1
1
PWM
20
4
16
SD/SDIO/MMC
2
1
1
SPI
4
1
3
UART
7
3
4
USB 2.0 OTG (host/device)
1
1
USB 2.0 host
1*
1*
External Memory Bus 16 bit multiplexed
1
1
QSPI
2
2
SIM
4
4
2
Figure 1: Colibri iMX7 Module Interfaces
*These interfaces are not available on all versions of the Colibri iMX7 module. Please see section 1.2.3
for more information.
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Colibri iMX7 Datasheet
1.4 Reference Documents
1.4.1
NXP (Freescale) i.MX 7
You will find the details about i.MX 7 SoC in the Datasheet and Reference Manual provided by
NXP.
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mxapplications-processors-based-on-arm-cores/i.mx-7-processors:IMX7-SERIES
1.4.2
Ethernet Transceiver
Colibri iMX7 uses the Microchip/Micrel KSZ8041NL Ethernet PHY:
http://www.microchip.com/wwwproducts/en/KSZ8041
1.4.3
Audio Codec
Colibri iMX7 uses the NXP SGTL5000 Audio Codec.
http://www.nxp.com/products/interface-and-connectivity/interface-and-systemmanagement/switch-monitoring-ics/ultra-low-power-audio-codec:SGTL5000
1.4.4
Touch Screen Controller / ADC
Colibri iMX7 uses the Analog Device AD7879-1 Touchscreen Controller.
http://www.analog.com/en/products/analog-to-digital-converters/integrated-specialpurpose-converters/capacitive-to-digital-and-touch-screen-controllers/ad7879.html
1.4.5
Toradex Developer Center
You can find a lot of additional information on the Toradex Developer Center, which is
regularly updated with the latest product support information.
Please note that the Developer Center is common for all Toradex products. You should always
check to ensure if information is valid or relevant for the Colibri iMX7.
http://developer.toradex.com
1.4.6
Colibri Carrier Board Schematics
We provide the complete schematics and the Altium project file (which includes library
symbols and IPC-7351 compliant footprints for the Colibri Evaluation Board and other Carrier
Boards free of charge. This is a great help when designing your own Carrier Board.
http://developer.toradex.com/carrier-board-design/reference-designs
1.4.7
Toradex Pinout Designer
The Toradex Pinout Designer is a powerful tool for configuring the pin muxing of the Apalis
and Colibri Modules. The tool allows comparing the interfaces of different modules.
http://developer.toradex.com/carrier-board-design/pinout-designer-tool
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Colibri iMX7 Datasheet
2. Architecture Overview
2.1 Block Diagram
Max.
2GByte DDR3L
50MHz Ref CLK
DDR3
DDR3L
2x16bit
2x16bit
5x Audio
4x Touch (res)
1x DDR3L 32bit
RMII
Micrel
KSZ8041
LAN
I2S
Freescale
SGTL5000
Analog
AD7879-1
I2C
1x USB OTG (High Speed 2.0)
I2C
1x USB Host (High Speed 2.0)
1x 4bit SDIO
4xADC (1.8V)
System
Control
NXP
i.MX 7
I2C2
X1 SODIMM
X1 SODIMM
1x 24bit RGB
1x I2C
1x SPI
3.3V
Ricoh
RN5T567
Dual/
Solo
SoC Voltage Rails
VBat
Peripheral
Supplies
XTAL
XTAL
3x Uart
8 bit Camera Input
24MHz
4x PWM
32.768kHz
1x16bit multiplexed parallel bus
2xCAN
1x 8bit NAND
SLC
NAND
Figure 2 Colibri iMX7 Block Diagram
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Colibri iMX7 Datasheet
3. Colibri iMX7 Connectors
The Colibri iMX7 is equipped with a 200-Pin SODIMM edge connector (X1). The table below
details the SODIMM 200-way connector pin functionality.
It should be noted that some of the pins are multiplexed; that is, there is more than one i.MX
7 SoC pin connected to one SODIMM pin. For example, ECSPI2_SCLK and GPIO1_IO11 are both
connected to SODIMM pin 67. Care should be taken to ensure that multiplexed pins are tristated when they are not being used (e.g. if i.MX 7 pin A and pin B are tied to SODIMM pin 1,
then if i.MX 7 pin A is being driven, pin B should be tri-stated). Additional information can be
found in chapter 4.1: Function Multiplexing.
Please note, the maximum voltage of the ADC input (Pin 2, 4, 6, and 8) is only 1.8V. Other
Colibri modules allow input voltages up to 3.3V.
- X1 Pin:
Pin number on the SODIMM connector (X1).
- Compatible function: The default function which is compatible with all Colibri modules.
IMPORTANT: There are a few limitations. You can find more
information about pin compatibility in the “Colibri Compatibility
Guide”.
- i.MX 7 CPU Ball:
The name of the ball (a.k.a. pin) of the i.MX 7 SoC.
- Non i.MX 7 CPU Ball:
Peripheral functions which are not directly provided by the i.MX 7
SoC.
- Note:
Additional information. Some pins are noted as “no standard
function”. These pins can provide only the GPIO functionality and the
listed alternate function, but not the Colibri compatible function.
Some of the Colibri compatible functions might be emulated by
programmatically manipulating the GPIO.
Table 3-1 X1 Connector
X1
Pin
Compatible Function
1
i.MX 7 Ball
Non i.MX 7 Ball
Note
Audio Analogue Microphone
Input
MIC_IN
SGTL5000 Pin 10
3
Audio Analogue Microphone
GND
MIC_GND
GND switched, controlled
with GPIO6_IO21
5
Audio Analogue Line-In Left
LINEIN_L
SGTL5000 Pin 9
7
Audio Analogue Line-In Right
LINEIN_R
SGTL5000 Pin 8
9
Audio_Analogue GND
VSS_AUDIO
GND
11
Audio_Analogue GND
VSS_AUDIO
GND
13
Audio Analogue Headphone
GND
HEADPHONE_GND
Virtual GND, do not connect
to normal GND
15
Audio Analogue Headphone
Left
HEADPHONE_L
SGTL5000 Pin 4
17
Audio Analogue Headphone
Right
HEADPHONE_R
SGTL5000 Pin 1
19
UART_C RXD
UART3_TXD
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Colibri iMX7 Datasheet
X1
Pin
Compatible Function
i.MX 7 Ball
21
UART_C TXD
UART3_RXD
23
UART_A DTR
SD2_DATA0
25
UART_A CTS, Keypad_In<0>
SAI2_TXFS
27
UART_A RTS
SAI2_TXC
29
UART_A DSR
GPIO1_IO07
no standard function
31
UART_A DCD
SD2_DATA1
no standard function
33
UART_A RXD
UART1_TXD
35
UART_A TXD
UART1_RXD
37
UART_A RI, Keypad_In<4>
GPIO1_IO06
39
GND
GND
41
GND
GND
43
WAKEUP Source<0>,
SDCard CardDetect
GPIO1_IO00
no standard function
45
WAKEUP Source<1>
GPIO1_IO01
no standard function
47
SDCard CLK
SD1_CLK
IO voltage 3.3V/1.8V
(see also section 5.14)*
49
SDCard DAT<1>
SD1_DATA1
IO voltage 3.3V/1.8V
(see also section 5.14)*
51
SDCard DAT<2>
SD1_DATA2
IO voltage 3.3V/1.8V
(see also section 5.14)*
53
SDCard DAT<3>
SD1_DATA3
IO voltage 3.3V/1.8V
(see also section 5.14)*
55
PS2 SDA1
ENET1_RD3
no standard function
57
LCD RGB Data<16>
LCD_DAT16
59
PWM<A>,
Camera Input Data<7>
ECSPI2_MOSI/
GPIO1_IO08
61
LCD RGB Data<17>
LCD_DAT17
63
PS2 SCL1
ENET1_RD2
no standard function
65
Camera Input Data<9>,
Keypad_Out<3>,
PS2 SDA2
ECSPI2_SS0
Only camera input
supported
67
PWM<D>,
Camera Input Data<6>
ECSPI2_SCLK/
GPIO1_IO11
Multiplexed (Two i.MX 7
Pins)
69
PS2 SCL2
SD1_CD_B
no standard function,
IO voltage 3.3V/1.8V
(see also section 5.14)*
71
Camera Input Data<0>,
LCD Back-Light GPIO
SD1_WP
no standard function, ,
IO voltage 3.3V/1.8V
(see also section 5.14)*
SD1_RESET_B
IO voltage 3.3V/1.8V
(see also section 5.14)*
73
75
Camera Input MCLK
77
Non i.MX 7 Ball
Note
no standard function
no standard function
Multiplexed (Two i.MX 7
Pins)
I2C4_SDA
SAI1_RXFS
79
Camera Input Data<4>
ECSPI1_MISO
81
Camera Input VSYNC
I2C3_SCL
83
GND
85
Camera Input Data<8>,
Keypad_Out<4>
87
nReset Out
GND
Only camera input
supported
ECSPI2_MISO
PMIC Reset Out
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Colibri iMX7 Datasheet
X1
Pin
Compatible Function
i.MX 7 Ball
89
nWE
EPDC_D9
91
nOE
EPDC_D8
93
RDnWR
LCD_RESET
95
RDY
EPDC_D13
97
Camera Input Data<5>
ECSPI1_SS0
99
nPWE
ENET1_TXC
101
Camera Input Data<2>
ECSPI1_SCLK
103
Camera Input Data<3>
ECSPI1_MOSI
105
nCS0
EPDC_D10
107
nCS1
EPDC_D15
109
GND
111
ADDRESS0
EPDC_D0
113
ADDRESS1
EPDC_D1
115
ADDRESS2
EPDC_D2
117
ADDRESS3
EPDC_D3
119
ADDRESS4
EPDC_D4
121
ADDRESS5
EPDC_D5
123
ADDRESS6
EPDC_D6
125
ADDRESS7
EPDC_D7
127
Non i.MX 7 Ball
Note
Recovery glue logic
Pull to GND while releasing
reset for entering the Serial
loader
no standard function
no standard function
GND
EPDC_SDCE2
129
USB Host Power Enable
UART3_CTS
131
Usb Host Over-Current Detect
UART3_RTS
133
EPDC_GDRL
135
SPDIF_IN
GPIO1_IO02
no standard function
137
USB Client Cable Detect,
SPDIF_OUT
USB_OTG1_VBUS/
ENET1_CRS
Multiplexed (Two i.MX 7
Pins), only USB VBUS
function supported
139
USB Host DP
USB_OTG2_DP
Not available on Solo
141
USB Host DM
USB_OTG2_DN
Not available on Solo
143
USB Client DP
USB_OTG1_DP
145
USB Client DM
USB_OTG1_DN
147
GND
149
DATA0
no connection
151
DATA1
no connection
153
DATA2
no connection
155
DATA3
no connection
157
DATA4
no connection
159
DATA5
no connection
161
DATA6
no connection
163
DATA7
no connection
165
DATA8
no connection
167
DATA9
no connection
GND
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Colibri iMX7 Datasheet
X1
Pin
Compatible Function
i.MX 7 Ball
169
DATA10
SAI1_RXD
171
DATA11
no connection
173
DATA12
no connection
175
DATA13
no connection
177
DATA14
no connection
179
DATA15
no connection
181
GND
GND
183
Ethernet Link/Activity Status
LINK_AKT
KSZ8041 LED0
185
Ethernet Speed Status
SPEED100
KSZ8041 LED1
187
Ethernet TXO-
TXO-
KSZ8041 Pin 6
189
Ethernet TXO+
TXO+
KSZ8041 Pin 7
191
Ethernet GND
AGND_LAN
193
Ethernet RXI-
RXI-
KSZ8041 Pin 4
195
Ethernet RXI+
RXI+
KSZ8041 Pin 5
197
GND
GND
199
GND
GND
2
Analogue Input <3>
ADC1_IN3
Maximum input voltage
1.8V
4
Analogue Input <2>
ADC1_IN2
Maximum input voltage
1.8V
6
Analogue Input <1>
ADC1_IN1
Maximum input voltage
1.8V
8
Analogue Input <0>
ADC1_IN0
Maximum input voltage
1.8V
10
Audio_Analogue VDD
AVDD_AUDIO
3.3V Supply
12
Audio_Analogue VDD
AVDD_AUDIO
3.3V Supply
14
Resistive Touch PX
TSPX
AD7819 Ball A3
16
Resistive Touch MX
TSMX
AD7819 Ball C3
18
Resistive Touch PY
TSPY
AD7819 Ball B3
20
Resistive Touch MY
TSMY
AD7819 Ball D3
22
VDD Fault Detect
GPIO1_IO03
no standard function
24
Battery Fault Detect
SAI1_RXC
no standard function
26
nReset In
28
PWM<B>
GPIO1_IO09
30
PWM<C>
GPIO1_IO10
32
UART_B CTS
SAI2_RXD
34
UART_B RTS
SAI2_TXD
36
UART_B RXD
UART2_TXD
38
UART_B TXD
UART2_RXD
40
VCC_BATT
VCC_BATT
42
3V3
3V3
44
LCD RGB DE
LCD_ENABLE
46
LCD RGB Data<7>
LCD_DAT7
48
LCD RGB Data<9>
LCD_DAT9
Non i.MX 7 Ball
Note
no standard function
Reset input
RTC supply
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 14
Colibri iMX7 Datasheet
X1
Pin
Compatible Function
i.MX 7 Ball
50
LCD RGB Data<11>
LCD_DAT11
52
LCD RGB Data<12>
LCD_DAT12
54
LCD RGB Data<13>
LCD_DAT13
56
LCD RGB PCLK
LCD_CLK
58
LCD RGB Data<3>
LCD_DAT3
60
LCD RGB Data<2>
LCD_DAT2
62
LCD RGB Data<8>
LCD_DAT8
64
LCD RGB Data<15>
LCD_DAT15
66
LCD RGB Data<14>
LCD_DAT14
68
LCD RGB HSYNC
LCD_HSYNC
70
LCD RGB Data<1>
LCD_DAT1
72
LCD RGB Data<5>
LCD_DAT5
74
LCD RGB Data<10>
LCD_DAT10
76
LCD RGB Data<0>
LCD_DAT0
78
LCD RGB Data<4>
LCD_DAT4
80
LCD RGB Data<6>
LCD_DAT6
82
LCD RGB VSYNC
LCD_VSYNC
84
3V3
86
SPI CS
I2C2_SDA
88
SPI CLK
I2C2_SCL
90
SPI RXD
I2C1_SCL
92
SPI TXD
I2C1_SDA
94
Camera Input HSYNC
I2C3_SDA
96
Camera Input PCLK
I2C4_SCL
98
Camera Input Data<1>
SD2_RESET_B
no standard function
100
Keypad_Out<1>
SD2_DATA2
no standard function
102
SD2_DATA3
no standard function
104
EPDC_GDSP
no standard function
EPDC_BDR0
no standard function
Non i.MX 7 Ball
Note
3V3
106
nCS2
108
3V3
110
ADDRESS8
EPDC_BDR1
112
ADDRESS9
EPDC_PWRCOM
114
ADDRESS10
EPDC_SDCLK
116
ADDRESS11
EPDC_SDLE
118
ADDRESS12
EPDC_SDOE
120
ADDRESS13
EPDC_SDSHR
122
ADDRESS14
EPDC_SDCE0
124
ADDRESS15
EPDC_SDCE1
126
DQM0
EPDC_D14
128
DQM1
EPDC_PWRSTAT
130
DQM2
EPDC_SDCE3
no standard function
132
DQM3
EPDC_GDCLK
no standard function
134
ADDRESS25
EPDC_GDOE
no standard function
3V3
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Page | 15
Colibri iMX7 Datasheet
X1
Pin
Compatible Function
i.MX 7 Ball
136
ADDRESS24
LCD_DAT18
no standard function
138
ADDRESS23
LCD_DAT19
no standard function
140
ADDRESS22
LCD_DAT20
no standard function
142
ADDRESS21
LCD_DAT21
no standard function
144
ADDRESS20
LCD_DAT22
no standard function
146
ADDRESS19
LCD_DAT23
no standard function
148
3V3
150
DATA16
EPDC_D12
152
DATA17
EPDC_D11
154
DATA18
no connection
156
DATA19
no connection
158
DATA20
no connection
160
DATA21
no connection
162
DATA22
no connection
164
DATA23
no connection
166
DATA24
no connection
168
DATA25
no connection
170
DATA26
no connection
172
DATA27
no connection
174
DATA28
no connection
176
DATA29
no connection
178
DATA30
180
DATA31
182
3V3
184
ADDRESS18
SD2_CLK
no standard function
186
ADDRESS17
SD2_CMD
no standard function
188
ADDRESS16
GPIO1_IO14
no standard function
190
SDCard CMD
SD1_CMD
IO voltage 3.3V/1.8V
(see also section 5.14)*
192
SDCard DAT<0>
SD1_DATA0
IO voltage 3.3V/1.8V
(see also section 5.14)*
194
I2C SDA
ENET1_TD3
196
I2C SCL
ENET1_TD2
198
3V3
3V3
200
3V3
3V3
Non i.MX 7 Ball
Note
3V3
GPIO1_IO15
no standard function
no connection
3V3
*It is possible to change the IO voltage of the main SD interface from 3.3V (default) to 1.8V in order to
support SD UHS-I speeds. Please note that the voltage can only be changed for all the pins
simultaneously, and not individually. Therefore, use these pins with care. More information can be found
in section 5.14.
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 16
Colibri iMX7 Datasheet
4. I/O Pins
4.1 Function Multiplexing
Each NXP i.MX 7 SoC I/O pin can be configured to one of the up to nine alternate functions.
Most of the pins can also be used as “normal” GPIOs (General Purpose I/O, sometimes also
referred to as Digital I/O). For example the i.MX7 signal pin on the SODIMM pin 33 has the
primary function uart1.TX (Colibri standard function UART_A_RXD), but can also provide the
following alternate functions: gpio4.IO[1] (GPIO), i2c1.SDA (I2C interface), sai3.MCLK (digital
audio interface), ecspi1.SS2 (SPI interface), or enet2.1588_EVENT0_OUT (Ethernet interface).
The default setting for this pin is the primary function uart1.TX. It is strongly recommended
that whenever it’s possible to use the primary interfaces before using any alternate interfaces.
This ensures the best compatibility between the Toradex standard software, operating
systems/BSPs, and other modules in the Colibri family.
Most of the alternate functions are available on more than one pin. Care should be taken to
ensure that two pins are not configured with the same function. This could lead to system
instability and undefined behaviour.
In the table in chapter 4.4 you will find a list of all pins which have alternate functions. There
you can find which alternate functions are available for each individual pin.
Some of the i.MX 7 pins are paired and share the same SODIMM pin. When using one of these
pins, make sure that the unused pin of each multiplexed pair is tri-stated or configured as
input to avoid undesired behaviour and/or hardware damage. The following table lists all
SODIMM pins that have more than one i.MX 7 pin connected:
Table 4-1 Multiplexed pins
X1 Pin #
i.MX 7 Pin 1
i.MX 7 Pin 2
Remarks
59
ECSPI2_MOSI
GPIO1_IO08
67
ECSPI2_SCLK
GPIO1_IO11
137
USB_OTG1_VBUS
ENET1_CRS
USB_OTG1_VBUS is always an input and cannot be used as
GPIO. ENET1_CRS is placed in order to provide the GPIO
functionality to pin 137
91
EPDC_D8
BOOT_MODE0
(Recovery glue logic)
The glue logic allows entering the serial loader by pulling down
pin 91 while releasing the reset.
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Page | 17
Colibri iMX7 Datasheet
3.3V
100k
EPDC_D08
SODIMM Pin 91
(nOE/RECOVERY)
i.MX 7
BOOT_MODE0
Inverter
Figure 3: Recovery Glue Logic
4.2 Pin Control
The alternate function of each pin can be changed independently. Every pin has a Pad Mux
Register in which the following settings can be configured (some settings might not be
available for certain pins). The register is called IOMUXC_SW_MUX_CTL_PAD_x where x is the
name of the i.MX 7 pin. More information about the available register settings can be found in
the i.MX 7 Reference Manual.
Table 4-2 Pad Mux Registor
Bit
Field
31-5
Reserved
4
SION
0 Software Input On Field disabled
1 Software Input On Field enabled
Force the selected mux mode
input path
MUX_MODE
0000 Select mux mode: ALT0 mux port
0001 Select mux mode: ALT1 mux port
0010 Select mux mode: ALT2 mux port
0011 Select mux mode: ALT3 mux port
0100 Select mux mode: ALT4 mux port
0101 Select mux mode: ALT5 mux port (GPIO)
0110 Select mux mode: ALT6 mux port
0111 Select mux mode: ALT7 mux port
1000 Select mux mode: ALT8 mux port
Check chapter 4.4 for the
available alternate function of
the pin
3-0
Description
Remarks
The pins have an additional register which allows configuration of pull up/down resistors,
drive strength, and other settings. The register is called IOMUXC_SW_PAD_CTL_PAD_x where x
is the name of the i.MX 7 pin. Some settings might not be available on certain pins. More
information about the available register settings can be found in the i.MX 7 Reference Manual.
Table 4-3 Pad Control Registor
Bit
Field
31-7
Reserved
Description
6-5
PS
00 100 kOhm Pull Down
01 5 kOhm Pull Up
10 47 kOhm Pull Up
11 100 kOhm Pull Up
4
PE
0 Pull Disabled
1 Pull Enabled
Remarks
Enable pull up/down function
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Page | 18
Colibri iMX7 Datasheet
Bit
Field
Description
3
HYS
0 Hysteris Disabled (CMOS input)
1 Hysteris Enabled (Schmitt trigger input)
Remarks
2
SRE
0 Fast Slew Rate
1 Slow Slew Rate
Use slow slew rate if possible
for reducing EMC problems
1-0
DSE
Drive strength Field
If possible decrease the drive
strength by increasing the
resistance in order to reduce
EMC problems
Input functions that are available at more than one physical pin require an additional input
multiplexer. This multiplexer is configured by a register called IOMUXC_x_SELECT_INPUT
where x is the name of the input function. More information about this register can be found
in the i.MX 7 Reference Manual.
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 19
Colibri iMX7 Datasheet
4.3
Pin Reset Status
After a reset, the pins can be at any of the different modes. Most of them are configured as
GPIO input with a 100k pull down resistor enabled. Please check the table in chapter 4.4 for
the reset states for each of the pins. For pins that are not configured as GPIO by default,
please check the i.MX 7 Reference Manual for the corresponding default configuration state.
As soon as the bootloader is executing, it is possible to reconfigure the pins and their states.
Please be aware, the pin reset status is only guaranteed during the release of the reset signal.
During the power up sequence, the states of the pins might be undefined until the IO bank
voltage is enabled on the module.
4.4
Functions List
Below is a list of all the i.MX7 pins which are available on the SODIMM connector. It shows the
alternate functions that are available for each pin. For most of the pins, the GPIO functionality
is defined as the ALT5 function. The alternate functions which are used to provide the primary
interfaces to ensure best compatibility with other Colibri modules are highlighted.
Function Short Forms
CAN:
Controller Area Network
CCM:
Clock Control Module
CSI:
Camera Sensor Interface
ECSPI:
Enhanced Configurable Serial Peripheral Interface Bus
ENET:
Ethernet MAC interface
EPDC:
Electrophoretic Display Controller (Electronic Paper Display)
FLEXTIMER:
Flexible Timer Module
GPIO:
General Purpose Input Output
GPT:
General Purpose Timer
I2C:
Inter Integrated Circuit
KPP:
Keypad Port
LCDIF:
LCD Interface
MQS:
Medium Quality Sound
PWM:
Pulse Width Modulation output
QSPI:
Quad Serial Peripheral Interface
RAWNAND:
Interface for NAND Flash
SAI:
Serial Interface for Audio (I2S and AC97)
SIM:
Subscriber Identification Module
UART:
Universal Asynchronous Receiver/Transmitter
USB:
Universal Serial Bus
USDHC:
Ultra-Secured Digital Host Controller (interface for SD and MMC cards)
WDOG:
Watchdog Timer
WEIM:
External Interface Module (External Memory Bus)
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 20
Colibri iMX7 Datasheet
4.4.1
SODIMM 200
X1
Pin
i.MX7
Ball Name
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
19
21
23
25
27
29
31
33
35
37
43
UART3_TXD
UART3_RXD
SD2_DATA0
SAI2_TXFS
SAI2_TXC
GPIO1_IO07
SD2_DATA1
UART1_TXD
UART1_RXD
GPIO1_IO06
GPIO1_IO00
uart3.TX
uart3.RX
usdhc2.DATA0
sai2.TX_SYNC
sai2.TX_BCLK
gpio1.IO[7]
usdhc2.DATA1
uart1.TX
uart1.RX
gpio1.IO[6]
gpio1.IO[0]
usb.OTG1_PWR
usb.OTG1_OC
sai2.RX_DATA[0]
ecspi3.MISO
ecspi3.MOSI
usb.OTG2_PWR*
sai2.TX_BCLK
i2c1.SDA
i2c1.SCL
usb.OTG2_OC*
pwm4.OUT
ecspi1.MOSI
ecspi1.MISO
gpt4.CAPTURE2
uart1.CTS_B
uart1.RTS_B
uart5.TX
gpt4.COMPARE1
ecspi1.SS2
ecspi1.SS1
uart5.RX
wdog1.WDOG_B
enet1.1588_EVENT0_OUT
enet1.1588_EVENT0_IN
sim2.PORT1_CLK
flextimer2.CH[4]
flextimer2.CH[5]
i2c2.SDA
sim2.PORT1_RST_B
enet2.1588_EVENT0_OUT*
enet2.1588_EVENT0_IN*
i2c2.SCL
wdog1.WDOG_RST_B_DEB
gpio4.IO[5]
gpio4.IO[4]
gpio5.IO[14]
gpio6.IO[19]
gpio6.IO[20]
usdhc2.LCTL
usdhc1.LCTL
45
GPIO1_IO01
gpio1.IO[1]
pwm1.OUT
sai1.MCLK
anatop.24M_OUT
47
49
51
53
55
SD1_CLK
SD1_DATA1
SD1_DATA2
SD1_DATA3
ENET1_RD3
usdhc1.CLK
usdhc1.DATA1
usdhc1.DATA2
usdhc1.DATA3
enet1.RGMII_RD3
sai3.RX_SYNC
sai3.TX_BCLK
sai3.TX_SYNC
sai3.TX_DATA[0]
can1.TX
ecspi4.SS0
ecspi4.SS3
ecspi4.RDY
ecspi3.SS1
uart1.TX
flextimer1.CH[3]
flextimer2.CH[2]
flextimer2.CH[3]
flextimer1.PHA
epdc.SDCE[5]*
gpio5.IO[3]
gpio5.IO[6]
gpio5.IO[7]
gpio5.IO[8]
gpio7.IO[3]
57
LCD_DAT16
lcdif.DATA[16]
flextimer1.CH[4]
csi1.DATA[1]
weim.CRE
59
ECSPI2_MOSI
GPIO1_IO08
ecspi2.MOSI
gpio1.IO[8]
uart7.TX
usdhc1.VSELECT
csi1.DATA[7]
uart3.RX
lcdif.DATA[14]
i2c3.SCL
61
LCD_DAT17
lcdif.DATA[17]
flextimer1.CH[5]
csi1.DATA[0]
weim.ACLK_FREERUN
gpio3.IO[22]
63
65
enet1.RGMII_RD2
ecspi2.SS0
ecspi2.SCLK
gpio1.IO[11]
usdhc1.CD_B
usdhc1.WP
usdhc1.RESET_B
can1.RX
uart7.CTS_B
uart7.RX
usdhc3.LCTL
69
71
73
ENET1_RD2
ECSPI2_SS0
ECSPI2_SCLK
GPIO1_IO11
SD1_CD_B
SD1_WP
SD1_RESET_B
uart1.RX
csi1.DATA[9]
csi1.DATA[6]
uart3.CTS_B
ecspi4.MISO
ecspi4.MOSI
ecspi4.SCLK
epdc.SDCE[4]*
lcdif.RESET
lcdif.DATA[13]
i2c4.SDA
flextimer1.CH[0]
flextimer1.CH[1]
flextimer1.CH[2]
gpio7.IO[2]
gpio4.IO[23]
gpio4.IO[20]
flextimer1.PHB
gpio5.IO[0]
gpio5.IO[1]
gpio5.IO[2]
75
I2C4_SDA
i2c4.SDA
uart5.TX
csi1.MCLK
usb.OTG2_ID*
gpio4.IO[15]
77
79
81
85
89
91
93
95
97
99
101
103
105
SAI1_RXFS
ECSPI1_MISO
I2C3_SCL
ECSPI2_MISO
EPDC_D9
EPDC_D8
LCD_RESET
EPDC_D13
ECSPI1_SS0
ENET1_TXC
ECSPI1_SCLK
ECSPI1_MOSI
EPDC_D10
sai1.RX_SYNC
ecspi1.MISO
i2c3.SCL
ecspi2.MISO
epdc.SDDO[9]*
epdc.SDDO[8]*
lcdif.RESET
epdc.SDDO[13]*
ecspi1.SS0
enet1.RGMII_TXC
ecspi1.SCLK
ecspi1.MOSI
epdc.SDDO[10]*
rawnand.CE2_B
uart6.RTS_B
uart5.CTS_B
uart7.RTS_B
sim1.PORT1_CLK
sim1.PORT1_TRXD
gpt1.COMPARE1
sim2.PORT1_TRXD
uart6.CTS_B
enet1.TX_ER
uart6.RX
uart6.TX
sim1.PORT1_RST_B
sai3.TX_BCLK
sai3.RX_SYNC
uart4.RX
uart4.RX
uart4.TX
flextimer1.CH[7]
uart4.TX
sai3.MCLK
gpc.PMIC_RDY
flextimer1.CH[6]
global wdog
ccm.ENET3_REF_CL
K_ROOT
uart6.CTS_B
uart7.TX
uart7.CTS_B
uart7.RTS_B
ecspi2.MOSI
coresight.TRACE_CL
K
usdhc1.DATA5
wdog1.WDOG_B
coresight.TRACE_CT
L
ecspi2.SCLK
usdhc1.DATA7
usdhc1.DATA4
enet1.MDC
uart6.RX
uart6.TX
uart6.RTS_B
wdog4.WDOG_RST_
B_DEB
sai2.RX_SYNC
usdhc2.DATA6
can2.RX
usdhc1.DATA6
qspi.B_DATA[1]
qspi.B_DATA[0]
coresight.EVENTI
qspi.B_SCLK
usdhc2.DATA7
sai1.RX_BCLK
usdhc2.DATA4
usdhc2.DATA5
qspi.B_DATA[2]
i2c4.SCL
csi1.DATA[4]
csi1.VSYNC
csi1.DATA[8]
uart6.TX
uart6.RX
csi1.FIELD
uart7.TX
csi1.DATA[5]
gpt2.COMPARE2
csi1.DATA[2]
csi1.DATA[3]
uart6.RTS_B
sim1.PORT1_PD
weim.CS0_B
gpio6.IO[16]
gpio4.IO[18]
gpio4.IO[12]
gpio4.IO[22]
gpio2.IO[9]
gpio2.IO[8]
gpio3.IO[4]
gpio2.IO[13]
gpio4.IO[19]
gpio7.IO[11]
gpio4.IO[16]
gpio4.IO[17]
gpio2.IO[10]
107
EPDC_D15
epdc.SDDO[15]*
sim2.PORT1_RST_B
qspi.B_SS1_B
uart7.CTS_B
weim.CS1_B
111
113
115
EPDC_D0
EPDC_D1
EPDC_D2
epdc.SDDO[0]*
epdc.SDDO[1]*
epdc.SDDO[2]*
sim1.PORT2_TRXD
sim1.PORT2_CLK
sim1.PORT2_RST_B
qspi.A_DATA[0]
qspi.A_DATA[1]
qspi.A_DATA[2]
kpp.ROW[3]
kpp.COL[3]
kpp.ROW[2]
weim.AD[0]
weim.AD[1]
weim.AD[2]
67
sai3.MCLK
sdma.EXT_EVENT[0]
lcdif.DATA[15]
weim.RW
weim.OE
weim.DTACK_B
weim.WAIT
epdc.PWRCTRL[3]*
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Reset
State
Pull
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT5
ALT5
ALT5
ALT0
ALT0
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PU
ALT0
100k PD
ccm.EXT_CLK2
ccm.EXT_CLK3
ccm.EXT_CLK4
kpp.COL[2]
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
gpio3.IO[21]
src.BT_CFG[16]
ALT5
100k PD
gpio4.IO[21]
epdc.PWRCTRL[1]
kpp.COL[5]
ALT5
ALT0
100k PD
100k PD
src.BT_CFG[17]
ALT5
100k PD
kpp.ROW[2]
epdc.PWRWAKE*
epdc.PWRCTRL[0]
kpp.ROW[6]
ALT5
ALT5
ALT5
ALT0
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
epdc.VCOM[1]*
ALT5
100k PD
mqs.RIGHT
epdc.PWRIRQ*
epdc.BDR[0]*
epdc.PWRCTRL[2]*
lcdif.DATA[9]
lcdif.DATA[8]
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
ALT5
100k PD
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
ALT7
ALT8
kpp.COL[4]
gpio5.IO[15]
gpio4.IO[1]
gpio4.IO[0]
enet1.MDC
enet1.MDIO
kpp.ROW[4]
pwm1.OUT
pwm4.OUT
lcdif.DATA[0]
lcdif.BUSY
EPDC_SDLE*
EPDC_SDCLK*
lcdif.CS
EPDC_GDOE*
epdc.PWRCOM
epdc.PWRSTAT*
lcdif.DATA[10]
lcdif.DATA[9]
gpio2.IO[15]
lcdif.DATA[15]
lcdif.WR_RWN
EPDC_SDOE*
EPDC_PWRC*
OM*
gpio2.IO[0]
gpio2.IO[1]
gpio2.IO[2]
lcdif.DATA[0]
lcdif.DATA[1]
lcdif.DATA[2]
lcdif.CLK
lcdif.ENABLE
lcdif.VSYNC
lcdif.DATA[13]
epdc.PWRCTRL[3]**
Page | 21
Colibri iMX7 Datasheet
X1
Pin
i.MX7
Ball Name
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
117
119
121
123
125
127
129
131
EPDC_D3
EPDC_D4
EPDC_D5
EPDC_D6
EPDC_D7
EPDC_SDCE2
UART3_CTS
UART3_RTS
epdc.SDDO[3]*
epdc.SDDO[4]*
epdc.SDDO[5]*
epdc.SDDO[6]*
epdc.SDDO[7]*
epdc.SDCE[2]*
uart3.CTS_B
uart3.RTS_B
sim1.PORT2_SVEN
sim1.PORT2_PD
sim2.PORT2_TRXD
sim2.PORT2_CLK
sim2.PORT2_RST_B
sim2.PORT1_SVEN
usb.OTG2_PWR*
usb.OTG2_OC*
kpp.COL[2]
kpp.ROW[1]
kpp.COL[1]
kpp.ROW[0]
kpp.COL[0]
kpp.COL[6]
ecspi1.SS0
ecspi1.SCLK
weim.AD[3]
weim.AD[4]
weim.AD[5]
weim.AD[6]
weim.AD[7]
weim.ADDR[16]
enet1.1588_EVENT1_OUT
enet1.1588_EVENT1_IN
gpio2.IO[3]
gpio2.IO[4]
gpio2.IO[5]
gpio2.IO[6]
gpio2.IO[7]
gpio2.IO[22]
gpio4.IO[7]
gpio4.IO[6]
lcdif.DATA[3]
lcdif.DATA[4]
lcdif.DATA[5]
lcdif.DATA[6]
lcdif.DATA[7]
lcdif.DATA[21]
usdhc1.VSELECT
usdhc3.LCTL*
lcdif.HSYNC
133
EPDC_GDRL
epdc.GDRL*
flextimer2.CH[2]
enet2.TX_EN*
weim.ADDR[20]
gpio2.IO[26]
lcdif.RD_E
135
GPIO1_IO02
gpio1.IO[2]
pwm2.OUT
qspi.A_DATA[3]
qspi.A_DQS
qspi.A_SCLK
qspi.A_SS0_B
qspi.A_SS1_B
enet2.RGMII_TD0*
sai3.TX_SYNC
sai3.TX_DATA[0]
enet2.RGMII_TX_CT
L*
ccm.ENET1_REF_CL
K_ROOT
sai2.MCLK
anatop.32K_OUT
137
ENET1_CRS
enet1.CRS
sai1.TX_SYNC
gpt2.CAPTURE1
epdc.PWRCTRL[0]*
gpio7.IO[14]
ccm.EXT_CLK3
169
SAI1_RXD
sai1.RX_DATA[0]
wdog2.WDOG_RST_
B_DEB
rawnand.CE1_B
can1.RX
sim1.PORT1_TRXD
gpio6.IO[12]
22
GPIO1_IO03
gpio1.IO[3]
pwm3.OUT
sai3.MCLK
osc32k.32K_OUT
24
SAI1_RXC
sai1.RX_BCLK
rawnand.CE3_B
i2c4.SDA
flextimer2.PHA
gpio6.IO[17]
mqs.LEFT
28
GPIO1_IO09
gpio1.IO[9]
usdhc1.LCTL
uart3.TX
i2c3.SDA
gpc.PMIC_RDY
kpp.ROW[5]
30
32
34
36
38
GPIO1_IO10
SAI2_RXD
SAI2_TXD
UART2_TXD
UART2_RXD
gpio1.IO[10]
sai2.RX_DATA[0]
sai2.TX_DATA[0]
uart2.TX
uart2.RX
usdhc2.LCTL
ecspi3.SCLK
ecspi3.SS0
i2c2.SDA
i2c2.SCL
uart3.RTS_B
uart2.CTS_B
uart2.RTS_B
ecspi1.RDY
ecspi1.SS3
i2c4.SCL
flextimer2.CH[6]
flextimer2.CH[7]
enet2.1588_EVENT1_OUT*
enet2.1588_EVENT1_IN*
flextimer1.PHA
gpio6.IO[21]
gpio6.IO[22]
gpio4.IO[3]
gpio4.IO[2]
kpp.COL[6]
kpp.COL[7]
kpp.ROW[7]
enet2.MDC*
enet2.MDIO*
44
LCD_ENABLE
lcdif.ENABLE
ecspi4.MOSI
csi1.DATA[17]
uart2.TX
gpio3.IO[1]
46
48
50
52
54
LCD_DAT7
LCD_DAT9
LCD_DAT11
LCD_DAT12
LCD_DAT13
lcdif.DATA[7]
lcdif.DATA[9]
lcdif.DATA[11]
lcdif.DATA[12]
lcdif.DATA[13]
csi1.MCLK
csi1.DATA[8]
csi1.DATA[6]
csi1.DATA[5]
csi1.DATA[4]
weim.DATA[7]
weim.DATA[9]
weim.DATA[11]
weim.DATA[12]
weim.DATA[13]
gpio3.IO[12]
gpio3.IO[14]
gpio3.IO[16]
gpio3.IO[17]
gpio3.IO[18]
56
LCD_CLK
lcdif.CLK
ecspi4.MISO
csi1.DATA[16]
uart2.RX
gpio3.IO[0]
58
60
62
64
66
LCD_DAT3
LCD_DAT2
LCD_DAT8
LCD_DAT15
LCD_DAT14
lcdif.DATA[3]
lcdif.DATA[2]
lcdif.DATA[8]
lcdif.DATA[15]
lcdif.DATA[14]
gpt1.CAPTURE1
gpt1.CLK
csi1.DATA[23]
csi1.DATA[22]
csi1.DATA[9]
csi1.DATA[2]
csi1.DATA[3]
weim.DATA[3]
weim.DATA[2]
weim.DATA[8]
weim.DATA[15]
weim.DATA[14]
gpio3.IO[8]
gpio3.IO[7]
gpio3.IO[13]
gpio3.IO[20]
gpio3.IO[19]
68
LCD_HSYNC
lcdif.HSYNC
ecspi4.SCLK
csi1.DATA[18]
uart2.RTS_B
gpio3.IO[2]
70
72
74
76
78
80
LCD_DAT1
LCD_DAT5
LCD_DAT10
LCD_DAT0
LCD_DAT4
LCD_DAT6
lcdif.DATA[1]
lcdif.DATA[5]
lcdif.DATA[10]
lcdif.DATA[0]
lcdif.DATA[4]
lcdif.DATA[6]
gpt1.COMPARE3
csi1.DATA[21]
csi1.HSYNC
csi1.DATA[7]
csi1.DATA[20]
csi1.VSYNC
csi1.PIXCLK
weim.DATA[1]
weim.DATA[5]
weim.DATA[10]
weim.DATA[0]
weim.DATA[4]
weim.DATA[6]
gpio3.IO[6]
gpio3.IO[10]
gpio3.IO[15]
gpio3.IO[5]
gpio3.IO[9]
gpio3.IO[11]
82
LCD_VSYNC
lcdif.VSYNC
ecspi4.SS0
uart5.RX
ccm.ENET2_REF_CL
K_ROOT*
sai2.RX_BCLK
ccm.ENET3_REF_CL
K_ROOT
enet1.MDIO
uart4.CTS_B
uart4.RTS_B
sai3.RX_DATA[0]
sai3.RX_BCLK
enet1.1588_EVENT3
_IN
coresight.TRACE[7]
coresight.TRACE[9]
coresight.TRACE[11]
coresight.TRACE[12]
coresight.TRACE[13]
enet1.1588_EVENT2
_IN
coresight.TRACE[3]
coresight.TRACE[2]
coresight.TRACE[8]
coresight.TRACE[15]
coresight.TRACE[14]
enet2.1588_EVENT2
_IN*
coresight.TRACE[1]
coresight.TRACE[5]
coresight.TRACE[10]
coresight.TRACE[0]
coresight.TRACE[4]
coresight.TRACE[6]
enet2.1588_EVENT3
_IN*
wdog3.WDOG_RST_
B_DEB
csi1.DATA[19]
uart2.CTS_B
gpio3.IO[3]
gpt1.COMPARE2
gpt1.CAPTURE2
86
I2C2_SDA
i2c2.SDA
uart4.TX
88
I2C2_SCL
i2c2.SCL
uart4.RX
wdog3.WDOG_B
ecspi3.SS0
ecspi3.SCLK
90
I2C1_SCL
i2c1.SCL
uart4.CTS_B
can1.RX
ecspi3.MISO
92
I2C1_SDA
i2c1.SDA
uart4.RTS_B
can1.TX
ecspi3.MOSI
ccm.ENET3_REF_CLK_RO
OT
ccm.ENET2_REF_CLK_RO
OT
anatop.24M_OUT
ccm.ENET1_REF_CLK_RO
OT*
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Reset
State
Pull
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
lcdif.DATA[19]
ALT5
100k PD
usb.OTG1_ID
ALT0
100k PD
ALT5
100k PD
ALT5
100k PD
ALT0
100k PD
ALT5
100k PD
pwm2.OUT
ALT0
100k PD
pwm3.OUT
ALT0
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
ALT5
100k PD
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
ALT5
100k PD
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
ALT5
100k PD
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
ALT5
100k PD
lcdif.DATA[3]
usb.OTG2_ID*
src.BT_CFG[7]
src.BT_CFG[9]
src.BT_CFG[11]
src.BT_CFG[12]
src.BT_CFG[13]
src.BT_CFG[3]
src.BT_CFG[2]
src.BT_CFG[8]
src.BT_CFG[15]
src.BT_CFG[14]
src.BT_CFG[1]
src.BT_CFG[5]
src.BT_CFG[10]
src.BT_CFG[0]
src.BT_CFG[4]
src.BT_CFG[6]
ALT8
gpio4.IO[11]
usdhc3.WP*
ALT5
100k PD
gpio4.IO[10]
usdhc3.CD_B*
ALT5
100k PD
gpio4.IO[8]
usdhc2.VSELECT
ALT5
100k PD
gpio4.IO[9]
usdhc3.VSELECT*
ALT5
100k PD
Page | 22
Colibri iMX7 Datasheet
X1
Pin
i.MX7
Ball Name
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
94
96
98
100
102
104
I2C3_SDA
I2C4_SCL
SD2_RESET_B
SD2_DATA2
SD2_DATA3
EPDC_GDSP
i2c3.SDA
i2c4.SCL
usdhc2.RESET_B
usdhc2.DATA2
usdhc2.DATA3
epdc.GDSP*
uart5.RTS_B
uart5.RX
sai2.MCLK
sai2.TX_SYNC
sai2.TX_DATA[0]
flextimer2.CH[3]
can2.TX
wdog4.WDOG_B
usdhc2.RESET
uart4.CTS_B
uart4.RTS_B
enet2.RGMII_TXC
sdma.EXT_EVENT[1]
usb.OTG1_ID
usb.OTG2_ID*
sim2.PORT1_SVEN
sim2.PORT1_PD
weim.ADDR[21]
gpio4.IO[13]
gpio4.IO[14]
gpio5.IO[11]
gpio5.IO[16]
gpio5.IO[17]
gpio2.IO[27]
epdc.BDR[1]*
epdc.VCOM[0]*
lcdif.BUSY
106
EPDC_BDR0
epdc.BDR[0]*
csi1.HSYNC
csi1.PIXCLK
ecspi3.RDY
gpt4.COMPARE2
gpt4.COMPARE3
enet2.TX_ER*
ccm.ENET2_REF_CL
K_ROOT*
weim.ADDR[22]
gpio2.IO[28]
lcdif.CS
110
112
114
116
118
120
EPDC_BDR1
EPDC_PWRCOM
EPDC_SDCLK
EPDC_SDLE
EPDC_SDOE
EPDC_SDSHR
epdc.BDR[1]*
epdc.PWRCOM*
epdc.SDCLK*
epdc.SDLE*
epdc.SDOE*
epdc.SDSHR*
epdc.SDCLKN*
flextimer2.PHA
sim2.PORT2_SVEN
sim2.PORT2_PD
flextimer1.CH[0]
flextimer1.CH[1]
kpp.ROW[4]
kpp.COL[4]
kpp.COL[5]
kpp.ROW[5]
weim.AD[8]
weim.AD[9]
weim.AD[10]
weim.AD[11]
weim.AD[12]
weim.AD[13]
gpio2.IO[29]
gpio2.IO[30]
gpio2.IO[16]
gpio2.IO[17]
gpio2.IO[18]
gpio2.IO[19]
lcdif.ENABLE
lcdif.HSYNC
lcdif.CLK
lcdif.DATA[16]
lcdif.DATA[17]
lcdif.DATA[18]
122
EPDC_SDCE0
epdc.SDCE[0]*
flextimer1.CH[2]
enet2.RX_EN*
weim.AD[14]
gpio2.IO[20]
124
126
128
130
132
134
136
138
EPDC_SDCE1
EPDC_D14
EPDC_PWRSTAT
EPDC_SDCE3
EPDC_GDCLK
EPDC_GDOE
LCD_DAT18
LCD_DAT19
epdc.SDCE[1]*
epdc.SDDO[14]*
epdc.PWRSTAT*
epdc.SDCE[3]*
epdc.GDCLK*
epdc.GDOE*
lcdif.DATA[18]
lcdif.DATA[19]
flextimer1.CH[3]
sim2.PORT1_CLK
flextimer2.PHB
sim2.PORT1_PD
flextimer2.CH[0]
flextimer2.CH[1]
flextimer1.CH[6]
flextimer1.CH[7]
enet2.RX_ER*
uart7.RTS_B
kpp.ROW[6]
kpp.COL[7]
kpp.ROW[7]
csi1.DATA[15]
csi1.DATA[14]
weim.AD[15]
weim.EB_B[0]
weim.EB_B[1]
weim.ADDR[17]
weim.ADDR[18]
weim.ADDR[19]
weim.CS2_B
weim.CS3_B
gpio2.IO[21]
gpio2.IO[14]
gpio2.IO[31]
gpio2.IO[23]
gpio2.IO[24]
gpio2.IO[25]
gpio3.IO[23]
gpio3.IO[24]
140
LCD_DAT20
lcdif.DATA[20]
flextimer2.CH[4]
csi1.DATA[13]
weim.ADDR[23]
gpio3.IO[25]
142
LCD_DAT21
lcdif.DATA[21]
flextimer2.CH[5]
csi1.DATA[12]
weim.ADDR[24]
144
LCD_DAT22
lcdif.DATA[22]
flextimer2.CH[6]
csi1.DATA[11]
146
LCD_DAT23
lcdif.DATA[23]
flextimer2.CH[7]
csi1.DATA[10]
enet2.TX_CLK*
enet2.RX_CLK*
enet2.CRS*
enet2.RGMII_RD0*
enet2.RGMII_RD1*
enet2.RGMII_RD2*
enet2.RGMII_RD3*
enet2.RGMII_RX_CT
L*
enet2.RGMII_RXC*
qspi.B_SS0_B
enet2.COL*
enet2.RGMII_TD1*
enet2.RGMII_TD2*
enet2.RGMII_TD3*
coresight.EVENTO
enet1.1588_EVENT2
_OUT
enet1.1588_EVENT3
_OUT
enet2.1588_EVENT2
_OUT*
enet2.1588_EVENT3
_OUT*
Reset
State
Pull
lcdif.DATA[17]
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
lcdif.DATA[7]
ALT5
100k PD
lcdif.DATA[6]
lcdif.DATA[11]
lcdif.DATA[20]
lcdif.DATA[8]
lcdif.DATA[23]
lcdif.DATA[10]
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
lcdif.DATA[19]
lcdif.DATA[5]
ALT5
100k PD
lcdif.DATA[20]
lcdif.DATA[14]
lcdif.VSYNC
lcdif.DATA[22]
lcdif.DATA[23]
lcdif.WR_RWN
src.BT_CFG[18]
src.BT_CFG[19]
lcdif.DATA[4]
lcdif.DATA[22]
lcdif.DATA[12]
lcdif.DATA[2]
lcdif.DATA[16]
lcdif.DATA[18]
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
100k PD
I2C3_SCL
ALT5
100k PD
gpio3.IO[26]
I2C3_SDA
ALT5
100k PD
weim.ADDR[25]
gpio3.IO[27]
I2C4_SCL
ALT5
100k PD
weim.ADDR[26]
gpio3.IO[28]
I2C4_SDA
ALT5
100k PD
ALT5
100k PD
ALT5
100k PD
ALT0
100k PD
ALT5
ALT5
100k PD
100k PD
ALT0
100k PD
ALT5
ALT5
ALT5
ALT5
100k PD
100k PD
100k PD
100k PD
ALT7
150
EPDC_D12
epdc.SDDO[12]*
sim1.PORT1_PD
qspi.B_DQS
uart7.RX
weim.LBA_B
gpio2.IO[12]
lcdif.DATA[12]
lcdif.DATA[21]
152
EPDC_D11
epdc.SDDO[11]*
sim1.PORT1_SVEN
qspi.B_DATA[3]
uart6.CTS_B
weim.BCLK
GPIO1_IO15
gpio1.IO[15]
usdhc3.WP
enet2.MDC*
can2.TX
wdog4.WDOG_B
lcdif.DATA[11]
sdma.EXT_EVENT[1
]
lcdif.DATA[1]
178
184
186
SD2_CLK
SD2_CMD
usdhc2.CLK
usdhc2.CMD
sai2.RX_SYNC
sai2.RX_BCLK
mqs.RIGHT
mqs.LEFT
gpt4.CLK
gpt4.CAPTURE1
sim2.PORT1_TRXD
188
GPIO1_IO14
gpio1.IO[14]
usdhc3.CD_B
enet2.MDIO*
can2.RX
wdog3.WDOG_B
190
192
194
196
SD1_CMD
SD1_DATA0
ENET1_TD3
ENET1_TD2
usdhc1.CMD
usdhc1.DATA0
enet1.RGMII_TD3
enet1.RGMII_TD2
sai3.RX_BCLK
sai3.RX_DATA[0]
can2.TX
can2.RX
uart7.RX
ecspi2.SS0
ecspi2.MISO
ecspi4.SS1
ecspi4.SS2
i2c4.SDA
i2c4.SCL
flextimer2.CH[0]
flextimer2.CH[1]
epdc.SDOEZ*
epdc.SDOED*
gpio2.IO[11]
ccm.EXT_CLK
4
gpio5.IO[12]
gpio5.IO[13]
ccm.EXT_CLK
3
gpio5.IO[4]
gpio5.IO[5]
gpio7.IO[9]
gpio7.IO[8]
sdma.EXT_EVENT[0
]
ccm.EXT_CLK1
ALT8
EPDC_GDSP*
EPDC_GDCLK
*
EPDC_SDCE0*
*This function is only available on the Colibri iMX7D and not on iMX7S.
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 23
Colibri iMX7 Datasheet
5. Interface Description
5.1
Power Signals
5.1.1
Digital Supply
Table 5-1 Digital Supply Pins
X1 Pin #
Colibri
Signal Name
I/O
Description
Remarks
42, 84,108, 148,182,198,
200
3V3
I
3.3V main power supply
Use decoupling capacitors on all pins.
39, 41, 83, 109,147, 181,
197, 199
GND
I
Digital Ground
40
VCC_BATT
I
RTC Power supply can be
connected to a backup battery.
5.1.2
Connect this pin to 3.3V even if the
internal RTC is not used.
Analogue Supply
Table 5-2 Analogue Supply Pins
X1 Pin #
10, 12
Colibri
Signal Name
AVDD_AUDIO
I/O
I
Description
Remarks
3.3V Analogue supply
Connect this pin to a 3.3V supply. For better
Audio accuracy we recommend filtering this
supply separately from the digital supply. This pin
is only connected to the Audio Codec.
If audio is not used, connect these pins to the
3V3 input supply.
9, 11
5.1.3
VSS_AUDIO
I
Analogue Ground
Connect this pin to GND. This pin is connected
with Digital GND on the Colibri iMX7. For better
Audio accuracy, use the module connector as
star point and route the grounds individual for the
audio.
Power Management Signals
Table 5-3 Power Management Pins
X1 Pin #
Colibri
Signal Name
I/O
26
nRESET_EXT
I
Reset Input
This pin is active low and resets the Colibri
module. There is a 100k Ohm pull-up on this pin.
87
nRESET_OUT
O
Reset Output
This pin is active low. This pin is driven low at
boot up. This signal is a push/pull output.
Description
Remarks
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 24
Colibri iMX7 Datasheet
5.2
GPIOs
Most of the pins have a GPIO (General Purpose Input/Output) function. The GPIO
functionality is configured by selecting the correct alternate function. For most of the pins,
this is ALT5, while some have the GPIO function on the alternative function ALT0. All GPIO
pins can be used as an interrupt source.
5.2.1
Wakeup Source
The Colibri iMX7 uses different sleep modes. In principle, all GPIOs can be used to wake up
the Colibri module from the System Idle, Low Power Idle, and Deep Sleep state. The
exception is the LPSR mode. In this mode, only the following IO pins are retained and
therefore only these pins can be used as the wakeup source from the LPSR mode. More
information about the different sleep modes can be found in section 6.
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
29
UART_A DSR
GPIO1_IO07
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
43
WAKEUP Source<0>,
SDCard CardDetect
GPIO1_IO00
Preferred wakeup source
45
WAKEUP Source<1>
GPIO1_IO01
Preferred wakeup source
59
PWM<A>,
Camera Input Data<7>
GPIO1_IO08
This pin is multiplexed with a non-LPSR capable pin. Therefore,
do not use this pin in LPSR mode.
67
PWM<D>,
Camera Input Data<6>
GPIO1_IO11
This pin is multiplexed with a non-LPSR capable pin. Therefore,
do not use this pin in LPSR mode.
135
SPDIF_IN
GPIO1_IO02
22
VDD Fault Detect
GPIO1_IO03
28
PWM<B>
GPIO1_IO09
30
PWM<C>
GPIO1_IO10
178
DATA30
GPIO1_IO15
188
ADDRESS16
GPIO1_IO14
29
UART_A DSR
GPIO1_IO07
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
Remarks
Even though, there are many pins available with the wake functionally, it is recommended
that, whenever possible, use pin 43 (WAKEUP Source<0>) and 45 (WAKEUP Source<1>). This
ensures that the design is compatible with other Colibri modules.
The touch pen down interrupt signal from the touch controller is shared with the power
management interrupt signal. This interrupt signal is connected to the GPIO1_IO13 ball of
the SoC. Even though this pin is also LPSR capable, it is not possible to wake up the system
from the LPSR mode by using the touch interrupt since the resistive touch controller is not
running in LPSR mode.
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Page | 25
Colibri iMX7 Datasheet
5.3
Ethernet
The Colibri iMX7D as well as the iMX7S feature both a 10/100 Mbit/s Ethernet interface with
Medium Dependent Interface (MDI). The PHY of this interface is located on the module.
Therefore, only the magnetics and the connector are needed on the carrier board. The
module features the Micrel KSZ8041 Fast Ethernet Transceiver as PHY which is connected
over RMII with the MAC in the NXP i.MX 7. The MAC in the SoC features an accurate IEEE
1588 compliant timer for clock synchronisation which is commonly used in industrial
automation applications.
Table 5-4 Ethernet Pins
X1 Pin#
Colibri
STD Function
PHY
Signal Name
I/O
Description
189
TXO+
TX+
O
100BASE-TX: Transmit + (Auto MDIX: Receive +)
187
TXO-
TX-
O
100BASE-TX: Transmit - (Auto MDIX: Receive -)
195
RXI+
RX+
I
100BASE-TX: Receive + (Auto MDIX: Transmit +)
193
RXI-
RX-
I
100BASE-TX: Receive - (Auto MDIX: Transmit -)
191
AGND_LAN
GND
183
LINK_AKT
LED0
O
Link activity indication LED
185
SPEED100
LED1
O
100Mbit/s indication LED
Ethernet ground, on the module connected to common GND
The Colibri iMX7D features a second Ethernet port (not available on Colibri iMX7S). If this
port is required, an additional PHY needs to be implemented on the carrier board. The
second MAC in the SoC is able to provide three different interface standards for the
connection with the PHY:

RGMII: Reduced Gigabit Media Independent Interface. This interface allows
connecting a Gigabit Ethernet PHY.

RMII: Reduced Media Independent Interface. This is the preferred mode for
interfacing a 10/100 Mbit/s Ethernet PHY such as the KSZ8041.

MII: Media Independent Interface. This is second option for interfacing a 10/100
Mbit/s Ethernet PHY. This mode requires more data pins than the RMII, with the
advantage of a more relaxed routing of the interface due to lower operation
frequency.
Table 5-5 RGMII signals (incompatible with other modules, only available on iMX7D)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Function
I/O
Description
122
ADDRESS14
EPDC_SDCE0
enet2.RGMII_RX_CTL
I
RGMII_RX_CTL
124
ADDRESS15
EPDC_SDCE1
enet2.RGMII_RXC
I
RGMII_RXC
114
ADDRESS10
EPDC_SDCLK
enet2.RGMII_RD0
I
RGMII_RXD0
116
ADDRESS11
EPDC_SDLE
enet2.RGMII_RD1
I
RGMII_RXD1
118
ADDRESS12
EPDC_SDOE
enet2.RGMII_RD2
I
RGMII_RXD2
120
ADDRESS13
EPDC_SDSHR
enet2.RGMII_RD3
I
RGMII_RXD3
EPDC_GDRL
enet2.RGMII_TX_CTL
O
RGMII_TX_CTL
133
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l [email protected]
Page | 26
Colibri iMX7 Datasheet
iMX7
Ball Name
iMX7
Function
I/O
Description
104
EPDC_GDSP
enet2.RGMII_TXC
O
RGMII_TXC
127
EPDC_SDCE2
enet2.RGMII_TD0
O
RGMII_TXD0
X1 Pin#
Colibri
STD Function
130
DQM2
EPDC_SDCE3
enet2.RGMII_TD1
O
RGMII_TXD1
132
DQM3
EPDC_GDCLK
enet2.RGMII_TD2
O
RGMII_TXD2
134
ADDRESS25
EPDC_GDOE
enet2.RGMII_TD3
O
RGMII_TXD3
178
DATA30
GPIO1_IO15
enet2.MDC
O
RGMII_MDC
36
UART_B RXD
UART2_TXD
188
ADDRESS16
GPIO1_IO14
enet2.MDIO
I/O
RGMII_MDIO
38
UART_B TXD
UART2_RXD
Table 5-6 RMII signals (incompatible with other modules and only available on iMX7D)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Function
I/O
Description
114
ADDRESS10
EPDC_SDCLK
enet2.RGMII_RD0
I
RMII_RXD0
116
ADDRESS11
EPDC_SDLE
enet2.RGMII_RD1
I
RMII_RXD1
124
ADDRESS15
EPDC_SDCE1
enet2.RX_ER
I
RMII_RXER
EPDC_SDCE2
enet2.RGMII_TD0
O
RMII_TXD0
EPDC_SDCE3
enet2.RGMII_TD1
O
RMII_TXD1
EPDC_GDRL
enet2.TX_EN
O
RMII_TXEN
enet2.RGMII_RX_CTL
I
RMII_CRS_DV
enet2.MDC
O
RMII_MDC
enet2.MDIO
I/O
RMII_MDIO
127
130
DQM2
133
122
ADDRESS14
EPDC_SDCE0
178
DATA30
GPIO1_IO15
36
UART_B RXD
UART2_TXD
38
UART_B TXD
UART2_RXD
188
ADDRESS16
GPIO1_IO14
22
VDD Fault
Detect
GPIO1_IO03
106
nCS2
EPDC_BDR0
88
SPI CLK
I2C2_SCL
ccm.ENET2_REF_CLK_ROOT I/O
50MHz Reference clock that is provided
from the MAC to the PHY or from the
PHY to the MAC
Table 5-7 MII signals (incompatible with other modules and only available on iMX7D)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
128
DQM1
112
iMX7
Function
I/O
Description
EPDC_PWRSTAT enet2.COL
I
MII_COL
ADDRESS9
EPDC_PWRCOM
enet2.CRS
I
MII_CRS
114
ADDRESS10
EPDC_SDCLK
enet2.RGMII_RD0
I
MII_RD0
116
ADDRESS11
EPDC_SDLE
enet2.RGMII_RD1
I
MII_RD1
118
ADDRESS12
EPDC_SDOE
enet2.RGMII_RD2
I
MII_RD2
120
ADDRESS13
EPDC_SDSHR
enet2.RGMII_RD3
I
MII_RD3
110
ADDRESS8
EPDC_BDR1
enet2.RX_CLK
I
MII_RX_CLK
122
ADDRESS14
EPDC_SDCE0
enet2.RX_EN
I
MII_RX_DV
124
ADDRESS15
EPDC_SDCE1
enet2.RX_ER
I
MII_RX_ER
EPDC_SDCE2
enet2.RGMII_TD0
O
MII_TD0
EPDC_SDCE3
enet2.RGMII_TD1
O
MII_TD1
127
130
DQM2
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Page | 27
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Function
I/O
Description
132
DQM3
EPDC_GDCLK
enet2.RGMII_TD2
O
MII_TD2
134
ADDRESS25
EPDC_GDOE
enet2.RGMII_TD3
O
MII_TD3
106
nCS2
EPDC_BDR0
enet2.TX_CLK
O
MII_TX_CLK
133
EPDC_GDRL
enet2.TX_EN
O
MII_TX_EN
104
EPDC_GDSP
enet2.TX_ER
O
MII_TX_ER
enet2.MDC
O
MII_MDC
enet2.MDIO
I/O
MII_MDIO
178
DATA30
GPIO1_IO15
36
UART_B RXD
UART2_TXD
38
UART_B TXD
UART2_RXD
188
ADDRESS16
GPIO1_IO14
5.4
USB
The Colibri iMX7D provides two USB 2.0 High-Speed (480 Mbit/s) ports while the Colibri
iMX7S provides only one. The port available on both modules is the USBC interface. This port
is a dual use USB interface that can be configured as host or client. The port cannot be used
as a true OTG controller. The USBC controller is also used for the serial loader mode
(recovery mode). For more information, see chapter 6. The second USB 2.0 High-Speed port
is only supported on the Colibri iMX7D. Even though this port is also a dual use interface,
the Colibri standard intents to use this port (USBH) as host only.
5.4.1
USB Data Signal
Table 5-8 USB Data Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
I/O
Description
143
USBC_P
USB_OTG1_DP
I/O
145
USBC_N
USB_OTG1_DN
I/O
Differential Signal for the shared USB Host / Client port
Available on Colibri iMX7D as well as iMX7S
139
USBH_P
USB_OTG2_DP
I/O
141
USBH_N
USB_OTG2_DN
I/O
5.4.2
Differential Signal for USB Host port
Only available on Colibri iMX7D
USB Control Signals
Table 5-9 USB OTG Pins
X1
Pin#
Colibri
STD Function
iMX7
Ball Name
135
SPDIF_IN
GPIO1_IO02
96
Camera Input
PCLK
137
iMX7
Function
I/O
usb.OTG1_ID
I
Description
USB OTG ID
I2C4_SCL
USB Client Cable
USB_OTG1_VBUS USB_OTG1_VBUS
Detect,SPDIF_OUT
I
Alternative instance of ID pin, incompatible
with other Colibri modules.
Use this pin to detect if VBUS is present (5V
USB supply). Please note that this pin is only
3.3V tolerant
This signal is connected to two pins of the
i.MX 7 SoC. For more information about the
configuration, see section 4.1.
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Page | 28
Colibri iMX7 Datasheet
The Colibri iMX7 module does not support true OTG, but the interface can be configured as
host or client. Due to compatibility with other Colibri modules, the current evaluation board
as well as the other Toradex carrier board do not use the USB OTG ID pin for detecting
whether a Type A or Type B cable is plugged in. Instead, the VBUS is used for detecting the
Host or Client mode. We recommend implementing the same circuit as on the evaluation
board for making sure the design is compatible with the provided Toradex OS images.
If you use the USB Host function, you need to generate the 5V USB supply voltage on your
carrier board. The Colibri iMX7 provides two optional signals for USB power supply control.
We recommend using the following pins to ensure best possible compatibility, however, use
of these signals is not mandatory and maybe other GPIOs can be used instead. The USB OTG
jack features an ID pin which allows detecting whether a type A or type B plug is plugged in.
The Colibri iMX7 module does not support true OTG, but the interface can be configured as
host or client.
Table 5-10 USB Power Control Pins
X1
Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Function
129
USB Host Power
Enable
UART3_CTS
29
UART_A DSR
GPIO1_IO07
Alternative instance of PWR enable pin,
incompatible with other Colibri modules.
131
Usb Host OverCurrent Detect
UART3_RTS
USB overcurrent, this pin can Signal an over
current condition in the USB supply
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
I/O
Description
This pin enables the external USB voltage
supply.
usb.OTG2_PWR
usb.OTG2_OC
O
I
Alternative instance of over current pin,
incompatible with other Colibri modules.
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Page | 29
Colibri iMX7 Datasheet
5.5
Display
The NXP i.MX 7 features a dedicated image processing unit with hardware accelerators. Even
though the SoC itself provides an MIPI DSI interface, only the parallel LCD interface can be
used. Some of the required pins for the DSI interface are missing on the SODIMM edge
connector.
5.5.1
Parallel RGB LCD interface
The Colibri iMX7 provides one parallel LCD interface on the SODIMM connector. It supports
up to 24-bit colour per pixel. The 24-bit colour mapping is compatible with the Colibri iMX6
but not with other Colibri modules. Therefore, only the 18-bit mode is ensured to be
compatible with the other modules.
Features
- Up to 1920x1080 resolution at 60Hz
- Up to 24-bit colour
- Supports parallel TTL displays and smart displays
- Max pixel clock 150MHz
Table 5-11 Standard Parallel RGB LCD Interface Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
I/O
24bit RGB
Interface
18bit RGB
Interface
16bit RGB
Interface
76
LCD RGB Data<0>
LCD_DAT0
O
B0
B0
B0
70
LCD RGB Data<1>
LCD_DAT1
O
B1
B1
B1
60
LCD RGB Data<2>
LCD_DAT2
O
B2
B2
B2
58
LCD RGB Data<3>
LCD_DAT3
O
B3
B3
B3
78
LCD RGB Data<4>
LCD_DAT4
O
B4
B4
B4
72
LCD RGB Data<5>
LCD_DAT5
O
B5
B5
G0
80
LCD RGB Data<6>
LCD_DAT6
O
B6
G0
G1
46
LCD RGB Data<7>
LCD_DAT7
O
B7
G1
G2
62
LCD RGB Data<8>
LCD_DAT8
O
G0
G2
G3
48
LCD RGB Data<9>
LCD_DAT9
O
G1
G3
G4
74
LCD RGB Data<10>
LCD_DAT10
O
G2
G4
G5
50
LCD RGB Data<11>
LCD_DAT11
O
G3
G5
R0
52
LCD RGB Data<12>
LCD_DAT12
O
G4
R0
R1
54
LCD RGB Data<13>
LCD_DAT13
O
G5
R1
R2
66
LCD RGB Data<14>
LCD_DAT14
O
G6
R2
R3
64
LCD RGB Data<15>
LCD_DAT15
O
G7
R3
R4
57
LCD RGB Data<16>
LCD_DAT16
O
R0
R4
61
LCD RGB Data<17>
LCD_DAT17
O
R1
R5
136
ADDRESS24
LCD_DAT18
O
R2
138
ADDRESS23
LCD_DAT19
O
R3
140
ADDRESS22
LCD_DAT20
O
R4
142
ADDRESS21
LCD_DAT21
O
R5
144
ADDRESS20
LCD_DAT22
O
R6
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Page | 30
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
I/O
24bit RGB
Interface
18bit RGB
Interface
16bit RGB
Interface
146
ADDRESS19
LCD_DAT23
O
R7
44
LCD RGB DE
LCD_ENABLE
O
Data Enable (other names: Output Enable, L_BIAS)
68
LCD RGB HSYNC
LCD_HSYNC
O
Horizontal Sync (other names: Line Clock, L_LCKL)
82
LCD RGB VSYNC
LCD_VSYNC
O
Vertical Sync (other names: Frame Clock, L_FCLK)
56
LCD RGB PCLK
LCD_CLK
O
Pixel Clock (other names: Dot Clock, L_PCLK_WR)
Many applications will also require some signals to control the backlight and/or display
enabling. You can use any of the free GPIOs for these functions but we recommend using the
same signals as used on our standard carrier boards to ensure minimal software
configuration overhead. PWM capable signals can be used to control the backlight brightness
on many display panels - see section 5.12.
Some of the LCD interface signals are available on alternative pins. Use this pins with care
since the location is incompatible with other Colibri modules.
Table 5-12 Alternative location of Parallel RGB LCD Interface Pins
X1
Pin#
Colibri
STD Function
iMX7
Ball Name
89
nWE
EPDC_D9
111
ADDRESS0
EPDC_D0
113
ADDRESS1
EPDC_D1
152
DATA17
EPDC_D11
115
ADDRESS2
EPDC_D2
130
DQM2
EPDC_SDCE3
117
ADDRESS3
EPDC_D3
127
iMX7
Function
I/O
Description
lcdif.DATA[0]
O
Alternative location of LCD_DAT0
lcdif.DATA[1]
O
Alternative location of LCD_DAT1
lcdif.DATA[2]
O
Alternative location of LCD_DAT2
lcdif.DATA[3]
O
Alternative location of LCD_DAT3
lcdif.DATA[4]
O
Alternative location of LCD_DAT4
lcdif.DATA[5]
O
Alternative location of LCD_DAT5
lcdif.DATA[6]
O
Alternative location of LCD_DAT6
lcdif.DATA[7]
O
Alternative location of LCD_DAT7
lcdif.DATA[8]
O
Alternative location of LCD_DAT8
lcdif.DATA[9]
O
Alternative location of LCD_DAT9
lcdif.DATA[10]
O
Alternative location of LCD_DAT10
lcdif.DATA[11]
O
Alternative location of LCD_DAT11
lcdif.DATA[12]
O
Alternative location of LCD_DAT12
EPDC_SDCE2
119
ADDRESS4
EPDC_D4
124
ADDRESS15
EPDC_SDCE1
121
ADDRESS5
EPDC_D5
122
ADDRESS14
EPDC_SDCE0
110
ADDRESS8
EPDC_BDR1
123
ADDRESS6
EPDC_D6
106
nCS2
EPDC_BDR0
125
ADDRESS7
EPDC_D7
91
nOE,Recovery
Mode
EPDC_D8
116
ADDRESS11
EPDC_SDLE
89
nWE
EPDC_D9
105
nCS0
EPDC_D10
105
nCS0
EPDC_D10
120
ADDRESS13
EPDC_SDSHR
112
ADDRESS9
EPDC_PWRCOM
152
DATA17
EPDC_D11
128
DQM1
EPDC_PWRSTAT
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Page | 31
Colibri iMX7 Datasheet
X1
Pin#
Colibri
STD Function
iMX7
Ball Name
150
DATA16
EPDC_D12
67
PWM<D>,Camera
Input Data<6>
ECSPI2_SCLK
95
RDY
EPDC_D13
59
PWM<A>,Camera
Input Data<7>
ECSPI2_MOSI
126
DQM0
EPDC_D14
85
Camera Input
Data<8>,
Keypad_Out<4>
ECSPI2_MISO
107
nCS1
EPDC_D15
116
ADDRESS11
EPDC_SDLE
132
DQM3
EPDC_GDCLK
104
iMX7
Function
I/O
Description
lcdif.DATA[13]
O
Alternative location of LCD_DAT13
lcdif.DATA[14]
O
Alternative location of LCD_DAT14
lcdif.DATA[15]
O
Alternative location of LCD_DAT15
lcdif.DATA[16]
O
Alternative location of LCD_DAT16
lcdif.DATA[17]
O
Alternative location of LCD_DAT17
lcdif.DATA[18]
O
Alternative location of LCD_DAT18
lcdif.DATA[19]
O
Alternative location of LCD_DAT19
lcdif.DATA[20]
O
Alternative location of LCD_DAT20
lcdif.DATA[21]
O
Alternative location of LCD_DAT21
lcdif.DATA[22]
O
Alternative location of LCD_DAT22
lcdif.DATA[23]
O
Alternative location of LCD_DAT23
lcdif.ENABLE
O
Alternative location of LCD_ENABLE
lcdif.HSYNC
O
Alternative location of LCD_HSYNC
lcdif.VSYNC
O
Alternative location of LCD_VSYNC
lcdif.CLK
O
Alternative location of LCD_CLK
EPDC_GDSP
118
ADDRESS12
EPDC_SDOE
120
ADDRESS13
EPDC_SDSHR
134
ADDRESS25
EPDC_GDOE
122
ADDRESS14
EPDC_SDCE0
133
EPDC_GDRL
114
ADDRESS10
EPDC_SDCLK
124
ADDRESS15
EPDC_SDCE1
127
EPDC_SDCE2
150
DATA16
EPDC_D12
126
DQM0
EPDC_D14
130
DQM2
EPDC_SDCE3
118
ADDRESS12
EPDC_SDOE
132
DQM3
EPDC_GDCLK
110
ADDRESS8
EPDC_BDR1
113
ADDRESS1
EPDC_D1
112
ADDRESS9
EPDC_PWRCOM
117
ADDRESS3
EPDC_D3
115
ADDRESS2
EPDC_D2
128
DQM1
EPDC_PWRSTAT
111
ADDRESS0
EPDC_D0
114
ADDRESS10
EPDC_SDCLK
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Page | 32
Colibri iMX7 Datasheet
5.5.2
LVDS
The Colibri iMX7 does not have a native LVDS interface. However, it is possible to use the
parallel LCD port with a LVDS transmitter. The Colibri Evaluation board provides a reference
design for a LVDS interface implementation.
5.5.3
HDMI
The Colibri iMX7 does not have a native HDMI interface. However, it is possible to implement
a parallel RGB to HDMI converter on the carrier board.
5.5.4
Analogue VGA
The Colibri iMX7 does not have a native Analogue VGA interface. However, it is possible to
implement a VGA interface on the carrier board using a VGA DAC. The Colibri Evaluation
board features a reference design for such a VGA DAC.
5.5.5
Display Serial Interface (DSI)
The Colibri iMX7 does not support the Display Serial Interface that is available on the NXP
i.MX 7 SoC.
5.5.6
Electrophoretic Display Controller (EPDC)
The standard Colibri iMX7 modules do not support the EDPC interface.
5.6
PCI Express
The Colibri iMX7 does not support the PCI Express Interface that is available on the NXP i.MX
7 SoC.
5.7
IDE
The Colibri iMX7 does not support the Integrated Drive Electronics interface (IDE).
5.8
External Memory Bus
The Colibri iMX7 features an external memory bus. NXP refers to this bus in its
documentation as the “External Interface Module” EIM. No internal devices are connected to
the external memory bus; hence, the memory bus configuration can be optimized for any
application-specific requirement without restrictions. The external memory bus is typically
used to connect high-speed devices like FPGAs, DSPs, secondary Ethernet controllers, CAN
controllers, etc.
The compatibility of the External Memory Bus with other Colibri modules is very limited. The
data pins for the non-multiplexed mode are not located at the position that is compatible
with other modules. Only the major signals of the multiplexed 16-bit interface is compatible
with the Colibri iMX6 module, but not with any other currently available modules. Therefore,
use the interface with care and check for conflicts with other pins.
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Page | 33
Colibri iMX7 Datasheet
Features
- Non-multiplexed mode: 16-bit data bus width (incompatible with other Colibri modules)
- Multiplexed mode up to 16-bit data bus width (limited compatibility with Colibri iMX6
modules)
- Up to 27-bit address bus width
- Asynchronous and burst mode
- Multiplexed and de-multiplexed address/data mode
- Maximum main clock frequency of 132 MHz
- Up to four chip select signals
5.8.1
Non-Multiplexed Mode
This mode uses different pins for the addresses and data signals. The interface is
incompatible with any other Colibri modules. The following configurations can be used in
the non-multiplexed mode:
Table 5-13 Non-Multiplexed Signal Mapping
8bit
16Bit
Peripheral Signals
MUM = 0,
DSZ = 100
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 001
A[15:0]
EIM_AD[15:0]
EIM_AD[15:0]
EIM_AD[15:0]
A[26:16]
EIM_ADDR[26:16]
EIM_ADDR [26:16]
EIM_ADDR [26:16]
D[7:0]
EIM_DATA[7:0]
EIM_DATA [15:8]
EIM_DATA [7:0]
DQM0
EIM_EB0
EIM_EB1
EIM_EB0
D[15:8]
EIM_DATA[15:8]
DQM1
EIM_EB1
5.8.2
Multiplexed Mode
In multiplexed mode, AD[15:0] is used for both the data and address signals. This reduces
the number of signals required to connect to a device. The multiplexed mode is compatible
with the Colibri iMX6 module with some limitation (not all signals are located at the same
place). The EIM_LBA signal (X1 pin 150) is used for selecting between address and data.
Table 5-14 Multiplexed Signal Mapping
16Bit
Peripheral Signals
(demultiplexed)
MUM = 1,
DSZ = 001
A[15:0]
EIM_AD[15:0]
A[25:16]
EIM_ADDR[25:16]
D[7:0]
EIM_AD[7:0]
DQM0
EIM_EB0
D[15:8]
EIM_AD[15:8]
DQM1
EIM_EB1
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Page | 34
Colibri iMX7 Datasheet
5.8.3
Memory Bus Signals
Table 5-15 Memory Bus Signals
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
111
ADDRESS0
EPDC_D0
weim.AD[0]
I/O
113
ADDRESS1
EPDC_D1
weim.AD[1]
I/O
115
ADDRESS2
EPDC_D2
weim.AD[2]
I/O
117
ADDRESS3
EPDC_D3
weim.AD[3]
I/O
119
ADDRESS4
EPDC_D4
weim.AD[4]
I/O
121
ADDRESS5
EPDC_D5
weim.AD[5]
I/O
123
ADDRESS6
EPDC_D6
weim.AD[6]
I/O
125
ADDRESS7
EPDC_D7
weim.AD[7]
I/O
Non-multiplexed mode: address bits 15 to 0
110
ADDRESS8
EPDC_BDR1
weim.AD[8]
I/O
Multiplexed mode: address and data bits 15 to 0
112
ADDRESS9
EPDC_PWRCOM
weim.AD[9]
I/O
114
ADDRESS10
EPDC_SDCLK
weim.AD[10]
I/O
116
ADDRESS11
EPDC_SDLE
weim.AD[11]
I/O
118
ADDRESS12
EPDC_SDOE
weim.AD[12]
I/O
120
ADDRESS13
EPDC_SDSHR
weim.AD[13]
I/O
122
ADDRESS14
EPDC_SDCE0
weim.AD[14]
I/O
124
ADDRESS15
EPDC_SDCE1
weim.AD[15]
I/O
76
LCD RGB
Data<0>
LCD_DAT0
weim.DATA[0]
I/O
70
LCD RGB
Data<1>
LCD_DAT1
weim.DATA[1]
I/O
60
LCD RGB
Data<2>
LCD_DAT2
weim.DATA[2]
I/O
58
LCD RGB
Data<3>
LCD_DAT3
weim.DATA[3]
I/O
78
LCD RGB
Data<4>
LCD_DAT4
weim.DATA[4]
I/O
72
LCD RGB
Data<5>
LCD_DAT5
weim.DATA[5]
I/O
80
LCD RGB
Data<6>
LCD_DAT6
weim.DATA[6]
I/O
46
LCD RGB
Data<7>
LCD_DAT7
weim.DATA[7]
I/O
62
LCD RGB
Data<8>
LCD_DAT8
weim.DATA[8]
I/O
48
LCD RGB
Data<9>
LCD_DAT9
weim.DATA[9]
I/O
74
LCD RGB
Data<10>
LCD_DAT10
weim.DATA[10]
I/O
50
LCD RGB
Data<11>
LCD_DAT11
weim.DATA[11]
I/O
52
LCD RGB
Data<12>
LCD_DAT12
weim.DATA[12]
I/O
54
LCD RGB
Data<13>
LCD_DAT13
weim.DATA[13]
I/O
66
LCD RGB
Data<14>
LCD_DAT14
weim.DATA[14]
I/O
Description
Non-multiplexed mode: data bits 15 to 0
Multiplexed mode: not used
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Page | 35
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
64
LCD RGB
Data<15>
LCD_DAT15
weim.DATA[15]
I/O
EPDC_SDCE2
weim.ADDR[16]
O
127
130
DQM2
EPDC_SDCE3
weim.ADDR[17]
O
132
DQM3
EPDC_GDCLK
weim.ADDR[18]
O
134
ADDRESS25
EPDC_GDOE
weim.ADDR[19]
O
133
EPDC_GDRL
weim.ADDR[20]
O
104
EPDC_GDSP
weim.ADDR[21]
O
Description
Additional address bits 26 to 16,
can be used for multiplexed and non-multiplexed
mode
106
nCS2
EPDC_BDR0
weim.ADDR[22]
O
140
ADDRESS22
LCD_DAT20
weim.ADDR[23]
O
142
ADDRESS21
LCD_DAT21
weim.ADDR[24]
O
144
ADDRESS20
LCD_DAT22
weim.ADDR[25]
O
146
ADDRESS19
LCD_DAT23
weim.ADDR[26]
O
61
LCD RGB
Data<17>
LCD_DAT17
weim.ACLK_FREERUN I
AXI clock signal
152
DATA17
EPDC_D11
weim.BCLK
O
Burst Clock
57
LCD RGB
Data<16>
LCD_DAT16
weim.CRE
O
CRE/PS signal for CellularRam memory
93
RDnWR
LCD_RESET
weim.DTACK_B
I
Data Acknowledge
126
DQM0
EPDC_D14
weim.EB_B[0]
O
Byte Enable Mask, corresponds to D[7:0]
128
DQM1
EPDC_PWRSTAT weim.EB_B[1]
O
Byte Enable Mask, corresponds to D[15:8]
105
nCS0
EPDC_D10
weim.CS0_B
O
107
nCS1
EPDC_D15
weim.CS1_B
O
136
ADDRESS24
LCD_DAT18
weim.CS2_B
O
138
ADDRESS23
LCD_DAT19
weim.CS3_B
O
91
nOE,Recovery
Mode
EPDC_D8
weim.OE
O
Output Enable
89
nWE
EPDC_D9
weim.RW
O
Write Enable
95
RDY
EPDC_D13
weim.WAIT
I
Ready/Busy/Wait signal
150
DATA16
EPDC_D12
weim.LBA_B
O
Address Valid, used for multiplexed bus only
Chip select signals
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Colibri iMX7 Datasheet
5.9
I2C
The NXP i.MX 7 SoC features four I2C controllers; up to three of which can be used
externally. They implement the I2C V2.1 specification. All of them can be used in master or
slave mode. The port I2C1 is used for power management and is not available externally.
Port I2C4 is available as standard I2C on the module connector. The ports I2C2 and I2C3 are
only available as alternate function.
Features:
- Supports 100kbit/s and fast mode 400kbit/s data transfer
- Multi-master operation
- Software-selectable acknowledge bit
- Interrupt driven, byte-by-byte data transfer
- Start and stop signal generation and detection
- Repeated start signal generation
- Acknowledge bit generation and detection
- Bus-busy detection
- Calling address identification interrupts
There are a lot of low-speed devices which use I2C interfaces such as RTCs and sensors, but
it is also commonly used to configure other devices such as cameras or displays. The I2C Bus
can also be used to communicate with SMB (System Management Bus) devices.
2
Table 5-16 I C Signals (Colibri family compatible interface)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
194
I2C SDA
ENET1_TD3
i2c4.SDA
I/O
Open Drain Data Signal Port 4
196
I2C SCL
ENET1_TD2
i2c4.SCL
I/O
Clock Signal Port 4
2
Table 5-17 Alternate I C Signals (additional and incompatible with other Colibri family modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
146
ADDRESS19
LCD_DAT23
24
Battery Fault Detect
SAI1_RXC
67
PWM<D>,Camera
Input Data<6>
GPIO1_IO11
75
Camera Input MCLK
I2C4_SDA
144
ADDRESS20
LCD_DAT22
30
PWM<C>
GPIO1_IO10
77
iMX7
Port Name
I/O
Description
i2c4.SDA
I/O
Alternate Open Drain Data Signal Port 4
i2c4.SCL
I/O
Alternate Clock Signal Port 4
i2c2.SDA
I/O
Open Drain Data Signal Port 2
i2c2.SCL
I/O
Clock Signal Port 2
SAI1_RXFS
96
Camera Input PCLK
I2C4_SCL
29
UART_A DSR
GPIO1_IO07
36
UART_B RXD
UART2_TXD
86
SPI CS
I2C2_SDA
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
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Page | 37
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
38
UART_B TXD
UART2_RXD
88
SPI CLK
I2C2_SCL
142
ADDRESS21
LCD_DAT21
28
PWM<B>
GPIO1_IO09
94
Camera Input
HSYNC
i2c3.SDA
I/O
Open Drain Data Signal Port 3
I2C3_SDA
140
ADDRESS22
LCD_DAT20
59
PWM<A>,Camera
Input Data<7>
GPIO1_IO08
i2c3.SCL
I/O
Clock Signal Port 3
81
Camera Input
VSYNC
I2C3_SCL
5.9.1
Real-Time Clock (RTC) recommendation
The Colibri iMX7 module features a RTC circuit which is located inside the SoC. The RTC is
equipped with an accurate 32.768 kHz quartz crystal and can be used for time keeping. The
RTC is sourced from the VCC_BATT (pin 40) supply pin.
The RTC on the module is not designed for ultra-low power consumption (typical current
consumption can be found in section 9.2). Therefore, a standard lithium coin cell battery can
be drained faster than required for certain designs. If a rechargeable RTC battery is not the
solution, it is recommended to use an external ultra-low power RTC IC on the carrier board
instead. In this case, add the external RTC to the standard interface (pin 194/196) of the
module and source the VCC_BACKUP pin from the 3.3V rail that sources also the main
module rail. A suitable reference schematic can be found in the schematic diagram of the
Colibri evaluation board. See also section 6.2.
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Page | 38
Colibri iMX7 Datasheet
5.10 UART
The Colibri iMX7 provides up to seven serial UART interfaces. Three of them are available on
dedicated UART pins which are compatible with other Colibri modules. The other four UARTs
are only available as an alternate function. These UARTs are incompatible with other Colibri
modules. Therefore, the additional four UART should only be used if compatibility with other
Colibri modules is not required and more than the three UARTs are required.
The UART_A interface of the Colibri is defined as a full featured UART. Unfortunately, the
NXP i.MX 7 SoC does not feature the DTR, DSR, DCD, and RI as dedicated signals. However,
these signals can be emulated by using GPIOs which are located on these SODIMM pins.
The UART_A is used as standard debug interface for the Toradex Embedded Linux and
Windows Embedded Compact operating systems. It is recommended that at least the RXD
and TXD lines of this port are kept accessible for system debugging.
The UARTs of the i.MX 7 can be configured either in the DTE (Data Terminal Equipment) or
DCE (Data Communication Equipment) mode. Changing the mode will change the direction
of all UART pins (data and all control signals). To ensure compatibility with the entire Colibri
family, UARTs need to be configured in DTE mode.
Particular attention should be paid to the names of the i.MX 7 data signals. In DTE mode, the
UARTx_RX_DATA port is transmitting data from the SoC while the UARTx_TX_DATA port is
receiving it. Therefore, the RX and TX signals need to be swapped. In the following signal
descriptions, the port direction is always described for DTE mode.
UART Features
- High-speed TIA/EIA-232F compatible (up to 4 Mbit/s)
- IrDA-compatible (up to 115.2kbit/s)
- 7 or 8 data bits (9 bit for RS485)
- 1 or 2 stop bits
- Optional parity bit (even or odd)
- Hardware flow control
- Auto detect baud rate
- 32 entries FIFO for receive and transmit
Table 5-18 UART_A Signal Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
33
UART_A RXD
UART1_TXD
uart1.TX
I
Received Data
35
UART_A TXD
UART1_RXD
uart1.RX
O
Transmitted Data
27
UART_A RTS
SAI2_TXC
uart1.RTS_B
O
Request to Send
25
UART_A CTS,
Keypad_In<0>
SAI2_TXFS
uart1.CTS_B
I
Clear to Send
23
UART_A DTR
SD2_DATA0
gpio5.IO[14]
O
GPIO only, DTR need to be emulated
29
UART_A DSR
GPIO1_IO07
gpio1.IO[7]
I
GPIO only, DSR need to be emulated
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Page | 39
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
31
UART_A DCD
SD2_DATA1
gpio5.IO[15]
I
GPIO only, DCD need to be emulated
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
gpio1.IO[6]
I
GPIO only, RI need to be emulated
Table 5-19 UART_B Signal Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
36
UART_B RXD
UART2_TXD
uart2.TX
I
Received Data
38
UART_B TXD
UART2_RXD
uart2.RX
O
Transmitted Data
34
UART_B RTS
SAI2_TXD
uart2.RTS_B
O
Request to Send
32
UART_B CTS
SAI2_RXD
uart2.CTS_B
I
Clear to Send
Table 5-20 UART_C Signal Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
19
UART_C RXD
UART3_TXD
uart3.TX
I
Received Data
21
UART_C TXD
UART3_RXD
uart3.RX
O
Transmitted Data
Table 5-21 Signal Pins of additional UART Ports
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
27
UART_A RTS
SAI2_TXC
31
UART_A DCD
SD2_DATA1
86
SPI CS
I2C2_SDA
23
UART_A DTR
SD2_DATA0
25
UART_A CTS,
Keypad_In<0>
SAI2_TXFS
88
SPI CLK
I2C2_SCL
34
UART_B RTS
SAI2_TXD
92
SPI TXD
I2C1_SDA
102
iMX7
Port Name
I/O
Description
uart4.TX
I
Received Data
uart4.RX
O
Transmitted Data
uart4.RTS_B
O
Request to Send
uart4.CTS_B
I
Clear to Send
uart5.TX
I
Received Data
uart5.RX
O
Transmitted Data
SD2_DATA3
32
UART_B CTS
SAI2_RXD
90
SPI RXD
I2C1_SCL
100
Keypad_Out<1>
SD2_DATA2
29
UART_A DSR
GPIO1_IO07
75
Camera Input MCLK
I2C4_SDA
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
96
Camera Input PCLK
I2C4_SCL
169
DATA10
SAI1_RXD
94
Camera Input
HSYNC
I2C3_SDA
uart5.RTS_B
O
Request to Send
81
Camera Input
VSYNC
I2C3_SCL
uart5.CTS_B
I
Clear to Send
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Page | 40
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
71
Camera Input
Data<0>,LCD BackLight GPIO
SD1_WP
89
nWE
EPDC_D9
103
Camera Input
Data<3>
ECSPI1_MOSI
69
PS2 SCL2
SD1_CD_B
91
nOE,Recovery Mode
EPDC_D8
101
Camera Input
Data<2>
ECSPI1_SCLK
73
iMX7
Port Name
I/O
Description
uart6.TX
I
Received Data
uart6.RX
O
Transmitted Data
uart6.RTS_B
O
Request to Send
uart6.CTS_B
I
Clear to Send
uart7.TX
I
Received Data
uart7.RX
O
Transmitted Data
uart7.RTS_B
O
Request to Send
uart7.CTS_B
I
Clear to Send
SD1_RESET_B
79
Camera Input
Data<4>
ECSPI1_MISO
105
nCS0
EPDC_D10
47
SDCard CLK
SD1_CLK
97
Camera Input
Data<5>
ECSPI1_SS0
152
DATA17
EPDC_D11
49
SDCard DAT<1>
SD1_DATA1
59
PWM<A>,Camera
Input Data<7>
ECSPI2_MOSI
95
RDY
EPDC_D13
67
PWM<D>,Camera
Input Data<6>
ECSPI2_SCLK
150
DATA16
EPDC_D12
192
SDCard DAT<0>
SD1_DATA0
53
SDCard DAT<3>
SD1_DATA3
85
Camera Input
Data<8>,
Keypad_Out<4>
ECSPI2_MISO
126
DQM0
EPDC_D14
51
SDCard DAT<2>
SD1_DATA2
65
Camera Input
Data<9>,
ECSPI2_SS0
Keypad_Out<3>,PS2
SDA2
107
nCS1
EPDC_D15
These UART ports are only available as alternate functions. Compatibility with other Colibri
modules cannot be guaranteed, as they are not standard Colibri module interfaces.
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Page | 41
Colibri iMX7 Datasheet
Table 5-22 Alternate UART Signals (additional and incompatible with other Colibri family modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
55
PS2 SDA1
ENET1_RD3
uart1.TX
I
Alternate Received Data for UART_A
63
PS2 SCL1
ENET1_RD2
uart1.RX
O
Alternate Transmitted Data for UART_A
44
LCD RGB DE
LCD_ENABLE
uart2.TX
I
Alternate Received Data for UART_B
56
LCD RGB PCLK
LCD_CLK
uart2.RX
O
Alternate Transmitted Data for UART_B
68
LCD RGB
HSYNC
LCD_HSYNC
uart2.RTS_B
O
Alternate Request to Send for UART_B
82
LCD RGB VSYNC LCD_VSYNC
uart2.CTS_B
I
Alternate Clear to Send for UART_B
28
PWM<B>
GPIO1_IO09
uart3.TX
I
Alternate Received Data for UART_C
59
PWM<A>,Camera
GPIO1_IO08
Input Data<7>
uart3.RX
O
Alternate Transmitted Data for UART_C
30
PWM<C>
GPIO1_IO10
Usb Host OverCurrent Detect
uart3.RTS_B
O
Request to Send for UART_C
131
UART3_RTS
67
PWM<D>,Camera
GPIO1_IO11
Input Data<6>
uart3.CTS_B
I
Clear to Send for UART_C
129
USB Host Power
Enable
UART3_CTS
5.11 SPI
The i.MX 7 provides 4 SPI controllers (which are called Enhanced Configurable SPI, ECSPI in
the reference manual) all of which are available on the module edge connector. One SPI
interface is available as the standard Colibri module interface. This interface is compatible
with other Colibri modules. The other SPI interfaces are available as alternate functions.
These interfaces are incompatible with other Colibri modules. Please use the standard Colibri
SPI interface first before using others.
The SPI ports operate at up to 52 Mbps and provide full duplex, synchronous, serial
communication between the Colibri module and internal or external peripheral devices. Each
SPI port consists of four signals; clock, chip select (frame), data in, and data out. There are
additional chip select signals available as alternate functions to support multiple peripherals.
Features:
- Up to 52 Mbps
- 32bit x 64 deep FIFO (RX and TX)
- Master/Slave configurable
- Simultaneous receive and transmit
- Low power mode
- DMA support
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Page | 42
Colibri iMX7 Datasheet
Each SPI channel supports four different modes of the SPI protocol:
Table 5-23 SPI Modes
SPI Mode
Clock
Polarity
Clock
Phase
Description
0
0
0
Clock is positive polarity and the data is latched on the positive edge of SCK
1
0
1
Clock is positive polarity and the data is latched on the negative edge of SCK
2
1
0
Clock is negative polarity and the data is latched on the positive edge of SCK
4
1
1
Clock is negative polarity and the data is latched on the negative edge of SCK
SPI can be used as a fast interface for ADCs, DACs, FPGAs, etc. Some LCD displays require
configuration over SPI prior to being driven via the RGB or LVDS interface.
Table 5-24 SPI Signals (Colibri family compatible interface)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
92
SPI TXD
I2C1_SDA
ecspi3.MOSI
O
Master Output, Slave Input
90
SPI RXD
I2C1_SCL
ecspi3.MISO
I
Master Input, Slave Output
86
SPI CS
I2C2_SDA
ecspi3.SS0
O
Slave Select
88
SPI CLK
I2C2_SCL
ecspi3.SCLK
O
Serial Clock
Table 5-25 SPI Signals (additional and incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
19
UART_C RXD
UART3_TXD
103
Camera Input
Data<3>
ECSPI1_MOSI
ecspi1.MOSI
O
Master Output, Slave Input
21
UART_C TXD
UART3_RXD
79
Camera Input
Data<4>
ECSPI1_MISO
ecspi1.MISO
I
Master Input, Slave Output
97
Camera Input
Data<5>
ECSPI1_SS0
129
USB Host Power
Enable
UART3_CTS
ecspi1.SS0
O
Slave Select 0
35
UART_A TXD
UART1_RXD
ecspi1.SS1
O
Slave Select 1
33
UART_A RXD
UART1_TXD
ecspi1.SS2
O
Slave Select 2
38
UART_B TXD
UART2_RXD
ecspi1.SS3
O
Slave Select 3
101
Camera Input
Data<2>
ECSPI1_SCLK
ecspi1.SCLK
O
Serial Clock
131
Usb Host OverCurrent Detect
UART3_RTS
36
UART_B RXD
UART2_TXD
ecspi1.RDY
I
Data ready signal
55
PS2 SDA1
ENET1_RD3
PWM<A>,Camera
Input Data<7>
ecspi2.MOSI
O
Master Output, Slave Input
59
ECSPI2_MOSI
85
Camera Input
Data<8>,
Keypad_Out<4>
ECSPI2_MISO
ecspi2.MISO
I
Master Input, Slave Output
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Page | 43
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
196
I2C SCL
ENET1_TD2
63
PS2 SCL1
ENET1_RD2
67
PWM<D>,Camera
Input Data<6>
ECSPI2_SCLK
65
Camera Input
Data<9>,
ECSPI2_SS0
Keypad_Out<3>,PS2
SDA2
194
I2C SDA
ENET1_TD3
44
LCD RGB DE
LCD_ENABLE
71
Camera Input
Data<0>,LCD BackLight GPIO
SD1_WP
56
LCD RGB PCLK
LCD_CLK
69
PS2 SCL2
SD1_CD_B
68
LCD RGB HSYNC
LCD_HSYNC
73
iMX7
Port Name
I/O
Description
ecspi2.SCLK
O
Serial Clock
ecspi2.SS0
O
Slave Select 0
ecspi4.MOSI
O
Master Output, Slave Input
ecspi4.MISO
I
Master Input, Slave Output
ecspi4.SCLK
O
Serial Clock
ecspi4.SS0
O
Slave Select 0
SD1_RESET_B
47
SDCard CLK
SD1_CLK
82
LCD RGB VSYNC
LCD_VSYNC
190
SDCard CMD
SD1_CMD
ecspi4.SS1
O
Slave Select 1
192
SDCard DAT<0>
SD1_DATA0
ecspi4.SS2
O
Slave Select 2
49
SDCard DAT<1>
SD1_DATA1
ecspi4.SS3
O
Slave Select 3
51
SDCard DAT<2>
SD1_DATA2
ecspi4.RDY
I
Data ready signal
Table 5-26 Alternate Signals of main SPI (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
27
UART_A RTS
SAI2_TXC
ecspi3.MOSI
O
Alternate Master Output, Slave Input
25
UART_A CTS,
Keypad_In<0>
SAI2_TXFS
ecspi3.MISO
I
Alternate Master Input, Slave Output
34
UART_B RTS
SAI2_TXD
ecspi3.SS0
O
Alternate Slave Select 0
53
SDCard DAT<3>
SD1_DATA3
ecspi3.SS1
O
Additional Slave Select 1
32
UART_B CTS
SAI2_RXD
ecspi3.SCLK
O
Alternate Serial Clock
98
Camera Input
Data<1>
SD2_RESET_B
ecspi3.RDY
I
Additional Data ready signal
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Page | 44
Colibri iMX7 Datasheet
5.12 PWM (Pulse Width Modulation)
The Colibri iMX7 features a dedicated Pulse Width Modulator (PWM) with four channels. Each
PWM channel features a 16 bit up-counter with clock source selection. There is a 16 bit 4
level deep FIFO available in order to minimize the interrupt overhead. There is a 12 bit
prescaler available for dividing the clock.
Additional to the dedicated PWM, the i.MX 7 SoC features a FlexTimer Module (FTM). This
module features two eight-channel timers that support input capture, output compare, and
the generation of PWM signals. This means that additional 16 PWM outputs are available to
the four dedicated PWM channels. These additional PWM channels are only available at
alternative functions of the module edge pins and therefore are incompatible with other
Colibri modules.
The PWM interface can be used as an easy way to emulate a DAC and generate a variable DC
voltage if used with a suitable RC circuit. Other uses include control of LED brightness,
display backlights, or servo motors.
Table 5-27 PWM Interface Signals
X1 Pin#
Colibri
STD Function
59
iMX7
Ball Name
iMX7
Port Name
I/O
Remarks
PWM<A>,Camera
GPIO1_IO08
Input Data<7>
pwm1.OUT
O
PWM Output 1
28
PWM<B>
GPIO1_IO09
pwm2.OUT
O
PWM Output 2
30
PWM<C>
GPIO1_IO10
pwm3.OUT
O
PWM Output 3
67
PWM<D>,Camera
GPIO1_IO11
Input Data<6>
pwm4.OUT
O
PWM Output 4
Table 5-28 Locations of FlexTimer Interface Signals (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
71
Camera Input
Data<0>,LCD
Back-Light GPIO
SD1_WP
ADDRESS13
EPDC_SDSHR
120
73
iMX7
Port Name
I/O
Remarks
flextimer1.CH[1]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer1.CH[2]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer1.CH[3]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
SD1_RESET_B
122
ADDRESS14
EPDC_SDCE0
47
SDCard CLK
SD1_CLK
124
ADDRESS15
EPDC_SDCE1
57
LCD RGB
Data<16>
LCD_DAT16
flextimer1.CH[4]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
61
LCD RGB
Data<17>
LCD_DAT17
flextimer1.CH[5]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
flextimer1.CH[6]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
136
ADDRESS24
LCD_DAT18
29
UART_A DSR
GPIO1_IO07
flextimer1.CH[7]
I/O
138
ADDRESS23
LCD_DAT19
FTM channel (PWM Output/ input capture/ output
compare)
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Page | 45
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
69
PS2 SCL2
SD1_CD_B
118
ADDRESS12
EPDC_SDOE
132
DQM3
EPDC_GDCLK
190
SDCard CMD
SD1_CMD
51
SDCard DAT<2>
SD1_DATA2
104
I/O
Remarks
flextimer1.CH[0]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[0]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[3]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[1]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[2]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[4]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[5]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[6]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
flextimer2.CH[7]
I/O
FTM channel (PWM Output/ input capture/ output
compare)
EPDC_GDSP
134
ADDRESS25
EPDC_GDOE
192
SDCard DAT<0>
SD1_DATA0
49
SDCard DAT<1>
SD1_DATA1
133
EPDC_GDRL
UART_A CTS,
Keypad_In<0>
SAI2_TXFS
140
ADDRESS22
LCD_DAT20
27
UART_A RTS
SAI2_TXC
142
ADDRESS21
LCD_DAT21
32
UART_B CTS
SAI2_RXD
144
ADDRESS20
LCD_DAT22
34
UART_B RTS
SAI2_TXD
146
ADDRESS19
LCD_DAT23
25
iMX7
Port Name
Table 5-29 Alternate Locations of main PWM Interface Signals (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Remarks
45
WAKEUP
Source<1>
GPIO1_IO01
pwm1.OUT
O
Alternate Pin for PWM Output 1
135
SPDIF_IN
GPIO1_IO02
pwm2.OUT
O
Alternate Pin for PWM Output 2
22
VDD Fault Detect
GPIO1_IO03
pwm3.OUT
O
Alternate Pin for PWM Output 3
43
WAKEUP
Source<0>,SDCard GPIO1_IO00
CardDetect
pwm4.OUT
O
Alternate Pin for PWM Output 4
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Page | 46
Colibri iMX7 Datasheet
5.13 OWR (One Wire)
The Colibri iMX7 does not feature a One Wire interface.
5.14 SD/MMC
The i.MX 7 SoC Dual as well as Solo provides two SDIO interfaces that are available on the
module edge connector. The i.MX 7 Dual features an additional third SDIO interface which is
not available externally since the pins are shared with the internal NAND interface. To ensure
carrier board design compatibility with other Colibri modules, only the standard Colibri
SD/MMC interface should be used. The second SD/MMC interface is available as alternate
functions.
The interfaces are capable of interfacing with SD Memory Cards, SDIO, MMC, CE-ATA cards,
and eMMC devices. The controllers can acts as both master and slave simultaneously.
The Colibri iMX7 supports UHS-I which allows up to 104 Mbyte/s transfer speed on its
standard SD card interface. But UHS-I requires 1.8V IO level which is not in the Colibri
module specification. Since the 1.8V capability is not mandatory in the Colibri module
specification, other modules may support only 3.3V logic level. Pay attention to the SD card
signal pull-up resistors on the carrier board. If the interface is used in the 1.8V mode, it is
recommended to remove the pull-up resistors on the carrier board. The i.MX 7 features
internal pull-up resistors which can be used instead.
Bus Speed Mode
Max. Clock Frequency
Max. Bus Speed
Signal Voltage
Remarks
Default Speed
25 MHz
12.5 MByte/s
3.3V
High Speed
50 MHz
25 MByte/s
3.3V
Colibri
Standard
SDR12
25 MHz
12.5 MByte/s
1.8V
SDR25
50 MHz
25 MByte/s
1.8V
DDR50
50 MHz
50 MByte/s
1.8V
SDR50
100 MHz
50 MByte/s
1.8V
SDR104
208 MHz
104 MByte/s
1.8V
UHS-I
May not
compatible with
other modules
Since the SODIMM pin 69, 71, and 73 are connected to SoC balls that share in the same
voltage bank as the main SD interface, these pins will also change their voltage level to 1.8V
if the SD card IO voltage is changed. Therefore, use pin 69, 71, and 73 with special care.
Only the CLK, CMD, and DATA[0..3] signals of the standard SD interface can change the
voltage to 1.8V. The additional DATA[4..7] support only 3.3V. Therefore, it is not possible to
use the 8bit eMMC with the reduced signal voltage.
Features
- Supports SD Memory Card Specification 3.0
- Supports SDIO Card Specification Version 3.0
- Supports MMC System Specification Version 4.2, 4.3, 4.4, 4.41, 4.5, and 5.0
- Supports addressing larger capacity SD 3.0 or SD-XC cards up to 2 TByte
- Supports SPI mode
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Colibri iMX7 Datasheet
- Up to 8 bit interface (only 4 bit compatible with other modules)
- Supports SD UHS-I mode (up to 208MHz) with 1.8V IO voltage level (only standard SD
port).
i.MX 7 SDIO
interface
Max Bus Width
Description
USDHC1
4bit (8bit)
Colibri Standard SD/MMC interface, additional data bits for 8 bit interface available as
alternate function
USDHC2
8bit
Available as an alternate function incompatible with Colibri standard
USDHC3
-
Unavailable at the module edge connector
Table 5-30 Colibri SD/MMC Signal Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
190
SDCard CMD
SD1_CMD
usdhc1.CMD
I/O
Command
192
SDCard DAT<0>
SD1_DATA0
usdhc1.DATA0
I/O
Serial Data 0
49
SDCard DAT<1>
SD1_DATA1
usdhc1.DATA1
I/O
Serial Data 1
51
SDCard DAT<2>
SD1_DATA2
usdhc1.DATA2
I/O
Serial Data 2
53
SDCard DAT<3>
SD1_DATA3
usdhc1.DATA3
I/O
Serial Data 3
47
SDCard CLK
SD1_CLK
usdhc1.CLK
O
Serial Clock
43
WAKEUP
Source<0>,SDCard GPIO1_IO00
CardDetect
gpio1.IO[0]
I
Card Detect (regular GPIO)
Table 5-31 Additional SD/MMC Signals (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
67
PWM<D>,Camera
Input Data<6>
ECSPI2_SCLK
usdhc1.DATA4
I/O
Serial Data 4 (only for 8bit MMC)
59
PWM<A>,Camera
Input Data<7>
ECSPI2_MOSI
usdhc1.DATA5
I/O
Serial Data 5 (only for 8bit MMC)
85
Camera Input
Data<8>,
Keypad_Out<4>
ECSPI2_MISO
usdhc1.DATA6
I/O
Serial Data 6 (only for 8bit MMC)
65
Camera Input
Data<9>,
ECSPI2_SS0
Keypad_Out<3>,PS2
SDA2
usdhc1.DATA7
I/O
Serial Data 7 (only for 8bit MMC)
SD1_RESET_B
usdhc1.RESET_B
O
Dedicated Card Reset (usually not needed)
SD1_WP
usdhc1.WP
I
Dedicated Write Protect
73
71
Camera Input
Data<0>,LCD BackLight GPIO
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Page | 48
Colibri iMX7 Datasheet
The additional SD/MMC signals allow the SD/MMC interface to be used as an 8 bit interface.
The pins are incompatible with other Colibri modules, as it is not part of the Colibri module
specification.
Table 5-32 Additional SD/MMC interface (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
186
ADDRESS17
SD2_CMD
usdhc2.CMD
I/O
Command
23
UART_A DTR
SD2_DATA0
usdhc2.DATA0
I/O
Serial Data 0
31
UART_A DCD
SD2_DATA1
usdhc2.DATA1
I/O
Serial Data 1
100
Keypad_Out<1>
SD2_DATA2
usdhc2.DATA2
I/O
Serial Data 2
SD2_DATA3
usdhc2.DATA3
I/O
Serial Data 3
102
101
Camera Input
Data<2>
ECSPI1_SCLK
usdhc2.DATA4
I/O
Serial Data 4 (only for 8bit MMC)
103
Camera Input
Data<3>
ECSPI1_MOSI
usdhc2.DATA5
I/O
Serial Data 5 (only for 8bit MMC)
79
Camera Input
Data<4>
ECSPI1_MISO
usdhc2.DATA6
I/O
Serial Data 6 (only for 8bit MMC)
97
Camera Input
Data<5>
ECSPI1_SS0
usdhc2.DATA7
I/O
Serial Data 7 (only for 8bit MMC)
184
ADDRESS18
SD2_CLK
usdhc2.CLK
O
Serial Clock
98
Camera Input
Data<1>
SD2_RESET_B
usdhc2.RESET_B
O
Dedicated Card Reset (usually not needed)
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Page | 49
Colibri iMX7 Datasheet
5.15 Analogue Audio
The Colibri iMX7 offers analogue audio input and output channels. The module features a
NXP SGTL5000 chip to provide the analogue audio interface. The SGTL5000 is connected
over I2S (SAI1) with the i.MX 7 SoC. Please consult the NXP SGTL5000 datasheet for more
information.
Table 5-33 Analogue Audio Interface Pins
X1 Pin #
Colibri
STD Function
I/O
Description
Pin on the SGTL5000
(20pin QFN)
1
MIC_IN
I
Microphone input
10
3
MIC_GND
5
LINEIN_L
I
Left Line Input
9
7
LINEIN_R
I
Right Line Input
8
15
HEADPHONE_L
O
Headphone Left Output
4
17
HEADPHONE_R
O
Headphone Right Output
1
13
HEADPHONE_GND
Headphone pseudo-ground (do not connect to ground!)
2
Microphone pseudo-ground. Possible to connect to GND.
Controlled by GPIO6_IO21 (ball RGMII_TD1)
5.16 Audio Codec Interface
The Colibri module does not feature an audio codec interface as standard. Nevertheless, it is
possible to access two of the internal three synchronous audio interfaces (SAI) of the i.MX 7
SoC at the module edge connector as alternate functions. The interfaces can be used as
Intel® Audio Codec ’97 (also known as AC’97 or AC97) or as I2S (also known as Inter-IC
Sound, Integrated Interchip Sound, or IIS). The interfaces can be used to connect an
additional external audio codec that can provide up to 5.1 channel audio.
The audio codec on the module which provides the analogue audio interface is connected to
the SAI1 interface of the digital audio multiplexer and is used in the I2S mode.
Table 5-34 Synchronous Serial Interface (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
19
UART_C RXD
UART3_TXD
49
SDCard
DAT<1>
SD1_DATA1
51
SDCard
DAT<2>
SD1_DATA2
129
USB Host
Power Enable
UART3_CTS
53
SDCard
DAT<3>
SD1_DATA3
131
Usb Host OverCurrent Detect
UART3_RTS
38
UART_B TXD
UART2_RXD
190
SDCard CMD
SD1_CMD
21
UART_C TXD
UART3_RXD
iMX7
Port Name
I/O
Description
sai3.TX_BCLK
I/O
Transmit Clock
sai3.TX_SYNC
I/O
Transmit Frame Sync
sai3.TX_DATA[0]
O
Data Transmit
sai3.RX_BCLK
I/O
Receive Clock
sai3.RX_SYNC
I/O
Receive Frame Sync
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Page | 50
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
47
SDCard CLK
SD1_CLK
36
UART_B RXD
UART2_TXD
192
SDCard
DAT<0>
SD1_DATA0
22
VDD Fault
Detect
GPIO1_IO03
33
UART_A RXD
UART1_TXD
73
iMX7
Port Name
I/O
Description
sai3.RX_DATA[0]
I
Data Receive
sai3.MCLK
I/O
Master Clock
sai2.TX_BCLK
I/O
Transmit Clock
sai2.TX_SYNC
I/O
Transmit Frame Sync
sai2.TX_DATA[0]
O
Data Transmit
sai2.RX_BCLK
I/O
Receive Clock
sai2.RX_SYNC
I/O
Receive Frame Sync
sai2.RX_DATA[0]
I
Data Receive
sai2.MCLK
I/O
Master Clock
SD1_RESET_B
27
UART_A RTS
SAI2_TXC
31
UART_A DCD
SD2_DATA1
25
UART_A CTS,
Keypad_In<0>
SAI2_TXFS
100
Keypad_Out<1> SD2_DATA2
34
UART_B RTS
102
SAI2_TXD
SD2_DATA3
24
Battery Fault
Detect
SAI1_RXC
186
ADDRESS17
SD2_CMD
77
SAI1_RXFS
184
ADDRESS18
SD2_CLK
23
UART_A DTR
SD2_DATA0
32
UART_B CTS
SAI2_RXD
98
Camera Input
Data<1>
SD2_RESET_B
135
SPDIF_IN
GPIO1_IO02
2
5.16.1 Digital Audio Port used as I S
The following signals are used for the I2S interface:
2
Table 5-35 Digital Audio port used as Maser I S
iMX7 Port Name
I2S Signal Name
(Names at Codec)
I/O
(at iMX7)
Description
TX_DATA[0]
SDIN
O
Serial Data Output from i.MX 7 SoC
RX_DATA[0]
SDOUT
I
Serial Data Input to i.MX 7 SoC
TX_SYNC
WS
O
Word Select, also known as Field Select or LRCLK
TX_BCLK
SCK
O
Serial Continuous Clock
2
Table 5-36 Digital Audio port used as Slave I S
iMX7 Port Name
I2S Signal Name
(Names at Codec)
I/O
(at iMX7)
Description
RX_DATA[0]
SDOUT
I
Serial Data Input to i.MX 7 SoC
TX_DATA[0]
SDIN
O
Serial Data Output from i.MX 7 SoC
RX_SYNC
WS
I
Word Select, also known as Field Select or LRCLK
RX_BCLK
SCK
I
Serial Continuous Clock
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Page | 51
Colibri iMX7 Datasheet
The audio codecs require a master clock input and often an I2C interface for control. Any of
the available I2C interfaces can be used (see section 5.9). Every SAI channel has a dedicated
master clock signal that can be configured as input or output according to the need of the
codec.
5.16.2 Digital Audio Port used as AC’97
The SAI interface can be configured as an AC’97 compatible interface. The AC’97 Audio
interface does not require an additional I2C for the control communication. The codec is
controlled directly through the AC’97 Audio interface. The AC’97 Audio codec requires a
master reference clock. Since every SAI has a dedicated master clock output, this clock signal
can be used. However, it is also possible to use a separate crystal/oscillator. Please take care
with the pin naming of some codecs. Some devices name their data input pin as SDATA_OUT
and the data output pin as SDATA_IN. The names refer to the signals they should be
connected to on the host (e.g. i.MX 7 SoC), and not to the signal direction.
Table 5-37 Digital Audio port used as AC’97
iMX7 Port Name
I2S Signal Name
(Names at Codec)
I/O
(at iMX7)
Description
RX_DATA[0]
SDATA_IN
I
AC’97 Audio Serial Input to i.MX 7
TX_DATA[0]
SDATA_OUT
O
AC’97 Audio Serial Output from i.MX 7
TX_SYNC
SYNC
O
AC’97 Audio Sync
TX_BCLK
BIT_CLK
I
AC’97 Audio Bit Clock
GPIOx
RESET#
O
AC’97 Master H/W Reset (use any GPIO)
5.17 Medium Quality Sound (MQS)
The medium quality sound interface can be used to generate medium quality audio via a
standard GPIO. The PWM output signal does not require an external DAC or codec chip. The
advantage over using the high quality analogue audio output of the on module SGTL5000 is
the option to use a simple switching power amplifier circuit (Class-D amplifier).
The MQS is sourced by SAI1 with a 2 channel 16 bit 44.1 kHz or 48 kHz audio signals which
is basically an I2S signal. Since this is the same SAI channel that is used by the on module
audio codec, it is not possible to use MQS simultaneous with the analogue audio output. The
signal to noise ratio (SNR) is expected to be no more than 20 dB for signals below 10 kHz.
For signals with higher frequencies, the SNR is even worse.
Table 5-38 MQS Interface Signals (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
186
ADDRESS17
SD2_CMD
24
Battery Fault Detect
SAI1_RXC
77
184
iMX7
Port Name
I/O
Description
mqs.LEFT
O
Left MQS Channel
mqs.RIGHT
O
Right MQS Channel
SAI1_RXFS
ADDRESS18
SD2_CLK
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Page | 52
Colibri iMX7 Datasheet
5.18 S/PDIF (Sony-Philips Digital Interface I/O)
The Colibri iMX7 does not features an S/PDIF interface.
5.19 Touch Panel Interface
The Colibri iMX7 provides a 4-wire resistive touch interface using the Analog Device
AD7879-1 Touchscreen Controller. It is connected with the i.MX 7 SoC via the power
management I2C interface (I2C1). The AD7879-1 does not support 5-wire operation mode.
Please consult the Analog Device AD7879-1 documentation for more information.
Table 5-39 Touch Interface Pins
X1
Colibri
Pin# STD Function
AD7879
Pin#
AD7879
Pin Name
I/O
Description
14
TSPX
A3
X+
I/O
X+ (4-wire)
16
TSMX
C3
X-
I/O
X- (4-wire)
18
TSPY
B3
Y+
I/O
Y+ (4-wire)
20
TSMY
D3
Y-
I/O
Y- (4-wire)
5.20 Analogue Inputs
The analogue inputs are provided by the NXP i.MX 7 SoC itself. The SoC features two ADCs
with both 4 channel inputs. Only ADC1 is available on the SODIMM connector and therefore
can be used. Pay attention, the input voltage range is only 1.8V and not 3.3V as on other
Colibri modules. On the module, there are 10k series resistors placed in the ADC lines in
order to protect the SoC input.
Features
- 12-bit ADC
- 0 to 1.8V (full scale)
- Sample rate up to 1MHz
- DMA support
- Conversion complete, hardware average complete, and compare interrupt
- Automatic compare for less than, greater than, equal to, within range, or out of range
Table 5-40 Analogue Inputs Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Function
I/O
Description
8
Analogue Input <0>
ADC1_IN0
ADC1_IN0
I
Analog input 1 (1.8V max)
6
Analogue Input <1>
ADC1_IN1
ADC1_IN1
I
Analog input 1 (1.8V max)
4
Analogue Input <2>
ADC1_IN2
ADC1_IN2
I
Analog input 1 (1.8V max)
2
Analogue Input <3>
ADC1_IN3
ADC1_IN3
I
Analog input 1 (1.8V max)
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Page | 53
Colibri iMX7 Datasheet
5.21 Camera Interface
The i.MX 7 SoC itself has two camera inputs; a parallel camera interface that is called camera
sensor interface (CSI) and a two data lane MIPI/CSI-2. It is important not to confuse these
two interfaces since their names are quite similar. CSI is the parallel camera interface while
MIPI/CSI-2 is the serial one. Since the Colibri module standard does not contain the serial
MIPI/CSI-2 interface, this camera is not available on the module edge connector. Only the
parallel interface is available.
The Colibri iMX7 features up to one 24 bit parallel camera interfaces. Only 8 bits of the
camera interface are available on pins that are compatible with other Colibri modules. The
remaining bits of the interface are only available as alternate functions. These pins are not
guaranteed to be compatible with other Colibri modules.
Features
- Raw (Bayer), RGB, YUV input
- Maximum pixel clock frequency 133 MHz
- 8/10/16/24bit parallel video interface
- Dedicated synchronisation signals (VSYNC, HSYNC) or embedded in data stream (BT.656)
Although the location for the 8 bits of the camera interface is equal to other modules, the
colour mapping might be different. Please carefully read the datasheets of the other Colibri
modules for more information regarding available colour modes.
Table 5-41 Parallel Camera Interface Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
101
Camera Input
Data<2>
ECSPI1_SCLK
csi1.DATA[2]
I
Camera pixel data
103
Camera Input
Data<3>
ECSPI1_MOSI
csi1.DATA[3]
I
Camera pixel data
79
Camera Input
Data<4>
ECSPI1_MISO
csi1.DATA[4]
I
Camera pixel data
97
Camera Input
Data<5>
ECSPI1_SS0
csi1.DATA[5]
I
Camera pixel data
67
PWM<D>,Camera
Input Data<6>
ECSPI2_SCLK
csi1.DATA[6]
I
Camera pixel data
59
PWM<A>,Camera
Input Data<7>
ECSPI2_MOSI
csi1.DATA[7]
I
Camera pixel data
85
Camera Input
Data<8>,
Keypad_Out<4>
ECSPI2_MISO
csi1.DATA[8]
I
Camera pixel data
65
Camera Input
Data<9>,
ECSPI2_SS0
Keypad_Out<3>,PS2
SDA2
csi1.DATA[9]
I
Camera pixel data
96
Camera Input PCLK
I2C4_SCL
csi1.PIXCLK
I
Camera pixel clock
94
Camera Input
HSYNC
I2C3_SDA
csi1.HSYNC
I
Camera horizontal sync
81
Camera Input
I2C3_SCL
csi1.VSYNC
I
Camera vertical sync
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Page | 54
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
I2C4_SDA
csi1.MCLK
O
Camera reference clock output
VSYNC
75
Camera Input MCLK
The camera modules often require an additional I 2C interface for control purposes. Any
available I2C interface can be used (see section 5.9). The following table shows the additional
signals for the CSI camera interface for up to 24 bit connections. Please be aware that these
signals are alternate functions and are incompatible with other modules.
Table 5-42 Additional Camera Input Signals for 20-bit Interface on non-standard Colibri Pin
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
61
LCD RGB
Data<17>
LCD_DAT17
csi1.DATA[0]
I
57
LCD RGB
Data<16>
LCD_DAT16
csi1.DATA[1]
I
64
LCD RGB
Data<15>
LCD_DAT15
csi1.DATA[2]
I
66
LCD RGB
Data<14>
LCD_DAT14
csi1.DATA[3]
I
54
LCD RGB
Data<13>
LCD_DAT13
csi1.DATA[4]
I
52
LCD RGB
Data<12>
LCD_DAT12
csi1.DATA[5]
I
50
LCD RGB
Data<11>
LCD_DAT11
csi1.DATA[6]
I
74
LCD RGB
Data<10>
LCD_DAT10
csi1.DATA[7]
I
48
LCD RGB
Data<9>
LCD_DAT9
csi1.DATA[8]
I
62
LCD RGB
Data<8>
LCD_DAT8
csi1.DATA[9]
I
146
ADDRESS19
LCD_DAT23
csi1.DATA[10]
I
144
ADDRESS20
LCD_DAT22
csi1.DATA[11]
I
142
ADDRESS21
LCD_DAT21
csi1.DATA[12]
I
140
ADDRESS22
LCD_DAT20
csi1.DATA[13]
I
138
ADDRESS23
LCD_DAT19
csi1.DATA[14]
I
136
ADDRESS24
LCD_DAT18
csi1.DATA[15]
I
56
LCD RGB
PCLK
LCD_CLK
csi1.DATA[16]
I
44
LCD RGB DE
LCD_ENABLE
csi1.DATA[17]
I
68
LCD RGB
HSYNC
LCD_HSYNC
csi1.DATA[18]
I
82
LCD RGB
VSYNC
LCD_VSYNC
csi1.DATA[19]
I
76
LCD RGB
Data<0>
LCD_DAT0
csi1.DATA[20]
I
70
LCD RGB
Data<1>
LCD_DAT1
csi1.DATA[21]
I
60
LCD RGB
LCD_DAT2
csi1.DATA[22]
I
Description
Additional camera pixel data [0..1]
Alternate pin for camera pixel data [2..9]
Additional camera pixel data [10..23]
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Page | 55
Colibri iMX7 Datasheet
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
Data<2>
58
LCD RGB
Data<3>
LCD_DAT3
csi1.DATA[23]
I
80
LCD RGB
Data<6>
LCD_DAT6
csi1.PIXCLK
I
Alternate pin for pixel clock
72
LCD RGB
Data<5>
LCD_DAT5
csi1.HSYNC
I
Alternate pin for horizontal sync
78
LCD RGB
Data<4>
LCD_DAT4
csi1.VSYNC
I
Alternate pin for vertical sync
46
LCD RGB
Data<7>
LCD_DAT7
csi1.MCLK
O
Alternate pin for master clock
93
RDnWR
LCD_RESET
csi1.FIELD
I
Field Identification (optional, identification of the
upper or lower field for interlaced input formats)
Table 5-43 Camera Interface Colour Pin Mapping
iMX7
Port Name
Bayer
10bit
Generic
BT656/
RGB888
YUV 8bit/ 8bit
CCIR656 3 cycle
YCbCr
8bit
2 cycle
RGB565
16bit
1 cycle
YCbCr
16bit
1 cycle
RGB666
18bit
1 cycle
RGB888
24bit
1 cycle
YCbCr
24bit
1 cycle
csi1.DATA[0]
D0
B0
C0
B4
B0
Cr0
csi1.DATA[1]
D1
B1
C1
B5
B1
Cr1
csi1.DATA[2]
D2
Y/C0
R/G/B0
Y/C0
B2
C2
B0
B2
Cr2
csi1.DATA[3]
D3
Y/C1
R/G/B1
Y/C1
B3
C3
B1
B3
Cr3
csi1.DATA[4]
D4
Y/C2
R/G/B2
Y/C2
B4
C4
B2
B4
Cr4
csi1.DATA[5]
D5
Y/C3
R/G/B3
Y/C3
G0
C5
B3
B5
Cr5
csi1.DATA[6]
D6
Y/C4
R/G/B4
Y/C4
G1
C6
B4
B6
Cr6
csi1.DATA[7]
D7
Y/C5
R/G/B5
Y/C5
G2
C7
B5
B7
Cr7
csi1.DATA[8]
D8
Y/C6
R/G/B6
Y/C6
G3
Y0
G4
G0
Cb0
csi1.DATA[9]
D9
Y/C7
R/G/B7
Y/C7
G4
Y1
G5
G1
Cb1
csi1.DATA[10]
G5
Y2
G0
G2
Cb2
csi1.DATA[11]
R0
Y3
G1
G3
Cb3
csi1.DATA[12]
R1
Y4
G2
G4
Cb4
csi1.DATA[13]
R2
Y5
G3
G5
Cb5
csi1.DATA[14]
R3
Y6
G4
G6
Cb6
csi1.DATA[15]
R4
Y7
G5
G7
Cb7
csi1.DATA[16]
R4
R0
Y0
csi1.DATA[17]
R5
R1
Y1
csi1.DATA[18]
R0
R2
Y2
csi1.DATA[19]
R1
R3
Y3
csi1.DATA[20]
R2
R4
Y4
csi1.DATA[21]
R3
R5
Y5
csi1.DATA[22]
R4
R6
Y6
csi1.DATA[23]
R5
R7
Y7
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Page | 56
Colibri iMX7 Datasheet
5.22 Clock Output
The i.MX 7 SoC has two general purpose clock output channels (CLKO1 and CLKO2) which
are available on different SoC pins. Since the SAI (audio), CSI (camera), as well as RMII
(Ethernet) interfaces feature dedicated reference clock outputs, the general purpose clock
outputs are not reserved for the internal audio codec or the Ethernet PHY.
Additionally to the two general purpose clock outputs, the i.MX 7 features four external
clock inputs. The clock control module (CCM) of the SoC allows routing these clock inputs to
different peripheral clocks. Further information can be found in the NXP i.MX 7 reference
manual.
Table 5-44 External Clock Signal Pins (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
69
PS2 SCL2
SD1_CD_B
135
SPDIF_IN
GPIO1_IO02
ccm.CLKO1
O
General Purpose Clock Output 1
22
VDD Fault Detect
GPIO1_IO03
71
Camera Input
Data<0>,LCD
Back-Light GPIO
SD1_WP
ccm.CLKO2
O
General Purpose Clock Output 2
192
SDCard DAT<0>
SD1_DATA0
ccm.EXT_CLK1
I
External Clock Input 1
49
SDCard DAT<1>
SD1_DATA1
ccm.EXT_CLK2
I
External Clock Input 2
51
SDCard DAT<2>
SD1_DATA2
137
USB Client Cable
ENET1_CRS
Detect,SPDIF_OUT
ccm.EXT_CLK3
I
External Clock Input 3
188
ADDRESS16
GPIO1_IO14
53
SDCard DAT<3>
SD1_DATA3
ccm.EXT_CLK4
I
External Clock Input 4
178
DATA30
GPIO1_IO15
5.23 Keypad
You can use any free GPIOs to realize a matrix keypad interface. Such a software solution
does not come with any additional hardware support. This is the preferred solution if a
carrier board needs to be compatible with different Colibri modules.
Additionally, the i.MX 7 SoC features a keyboard controller with hardware support. As the
keyboard controller is only available as an alternate function, this interface is incompatible
with other Colibri modules and can only be used if the required pins are being used for their
primary function.
The keyboard controller eliminates the requirement for de-bounce capacitors and pull-up
resistors. It can handle up to two buttons being pressed without the need for de-ghosting
diodes. If the diodes are available, any combination of pressed keys can be detected. The
row and column pins can be configured for a keyboard matrix of up to 8 by 8.
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Page | 57
Colibri iMX7 Datasheet
Features
- Open drain design
- Glitch suppression circuit
- Multiple-key detection
- Long key-press detection
- Standby key-press detection
- 2-point as well as 3-point key matrix supported
Table 5-45 Keyboard Matrix Interface Signals
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
125
ADDRESS7
EPDC_D7
kpp.COL[0]
O
Keyboard column 0
121
ADDRESS5
EPDC_D5
kpp.COL[1]
O
Keyboard column 1
55
PS2 SDA1
ENET1_RD3
kpp.COL[2]
O
Keyboard column 2
117
ADDRESS3
EPDC_D3
113
ADDRESS1
EPDC_D1
kpp.COL[3]
O
Keyboard column 3
29
UART_A DSR
GPIO1_IO07
kpp.COL[4]
O
Keyboard column 4
116
ADDRESS11
EPDC_SDLE
59
PWM<A>,Camera
GPIO1_IO08
Input Data<7>
kpp.COL[5]
O
Keyboard column 5
118
ADDRESS12
EPDC_SDOE
30
PWM<C>
GPIO1_IO10
kpp.COL[6]
O
Keyboard column 6
kpp.COL[7]
O
Keyboard column 7
127
EPDC_SDCE2
32
UART_B CTS
SAI2_RXD
132
DQM3
EPDC_GDCLK
123
ADDRESS6
EPDC_D6
kpp.ROW[0]
I
Keyboard row 0
119
ADDRESS4
EPDC_D4
kpp.ROW[1]
I
Keyboard row 1
63
PS2 SCL1
ENET1_RD2
kpp.ROW[2]
I
Keyboard row 2
115
ADDRESS2
EPDC_D2
111
ADDRESS0
EPDC_D0
kpp.ROW[3]
I
Keyboard row 3
37
UART_A RI,
Keypad_In<4>
GPIO1_IO06
kpp.ROW[4]
I
Keyboard row 4
114
ADDRESS10
EPDC_SDCLK
28
PWM<B>
GPIO1_IO09
kpp.ROW[5]
I
Keyboard row 5
120
ADDRESS13
EPDC_SDSHR
67
PWM<D>,Camera
GPIO1_IO11
Input Data<6>
kpp.ROW[6]
I
Keyboard row 6
kpp.ROW[7]
I
Keyboard row 7
130
DQM2
EPDC_SDCE3
34
UART_B RTS
SAI2_TXD
134
ADDRESS25
EPDC_GDOE
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Page | 58
Colibri iMX7 Datasheet
5.24 Controller Area Network (CAN)
The NXP i.MX 7 SoC Flexible Controller Area Network (FlexCAN) peripheral implements the
CAN protocol according to the CAN 2.0B specifications. It features a buffer for up to 64
messages and supports both standard and extended message frames. The CAN interface is
not part of the standard Colibri interfaces and therefore, it is incompatible with the complete
Colibri module family. However, the CAN interface that is located at pin 63/55 is compatible
with the Colibri iMX6 as well as Colibri VFxx modules. Therefore, whenever only one CAN
interface is required, it is recommended to use the one available at pin 63/55.
Additionally, the CAN interface on pin 178/188 is compatible with the Colibri iMX6 but not
with the VFxx. On the other hand, the CAN interface on pin 194/196 is compatible with the
VFxx modules but not with the iMX6. For more information, check the Toradex Pinout
Designer Tool.
Features
- Bit rate up to 1Mb/s
- Content-related addressing
- Flexible mailboxes of eight bytes data length (configurable as RX or TX)
- Powerful Rx FIFO ID filtering
- Listen-only mode
- Loop-back mode
- Time stamp based on 16bit free running timer
- Low power modes, wake up on bus activity
- Maskable interrupts
Table 5-46 CAN Signal Pins
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
63
PS2 SCL1
ENET1_RD2
90
SPI RXD
I2C1_SCL
169
DATA10
SAI1_RXD
55
PS2 SDA1
ENET1_RD3
iMX7
Port Name
I/O
Description
CAN receive pin, compatible with Colibri iMX6 and
VFxx
can1.RX
I
Alternate CAN receive pin
can1.TX
O
CAN transmit pin, compatible with Colibri iMX6 and
VFxx
92
SPI TXD
I2C1_SDA
Alternate CAN transmit pin
188
ADDRESS16
GPIO1_IO14
CAN receive pin, compatible with Colibri iMX6
196
I2C SCL
ENET1_TD2
81
Camera Input
VSYNC
I2C3_SCL
Alternate CAN receive pin
178
DATA30
GPIO1_IO15
CAN transmit pin, compatible with Colibri iMX6
194
I2C SDA
ENET1_TD3
94
Camera Input
HSYNC
I2C3_SDA
can2.RX
can2.TX
I
O
CAN receive pin, compatible with Colibri VFxx
CAN transmit pin, compatible with Colibri VFxx
Alternate CAN transmit pin
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Page | 59
Colibri iMX7 Datasheet
5.25 Quad Serial Peripheral Interface (QuadSPI)
The Quad Serial Peripheral Interface is an SPI interface with four bidirectional data lines
instead of one transmit and one receive data line. The interface is mainly used for
connecting to flash devices. The QuadSPI is incompatible with the Colibri family. The pins are
located on the SODIMM connector as secondary functions.
Features
-
Various flash vendor devices supported
-
Double Data Rate (DDR) and Single Data Rate (SDR) supported
-
Two identical serial flash devices can be connected and accessed in parallel for data
read operations with doubled readout bandwidth
-
DMA support
-
Memory mapped read assess to connected flash devices
-
Execute in place (XiP) possible
Table 5-47 QuadSPI Signals (incompatible with other modules)
X1 Pin#
Colibri
STD Function
iMX7
Ball Name
iMX7
Port Name
I/O
Description
123
ADDRESS6
EPDC_D6
qspi.A_SS0_B
O
Chip Select 0
125
ADDRESS7
EPDC_D7
qspi.A_SS1_B
O
Chip Select 1, used to select second instance of
QuadSPI device (dual die flash require CS0 and
CS1)
121
ADDRESS5
EPDC_D5
qspi.A_SCLK
O
Serial Clock
111
ADDRESS0
EPDC_D0
qspi.A_DATA[0]
I/O
Serial I/O for command, address, and data
113
ADDRESS1
EPDC_D1
qspi.A_DATA[1]
I/O
Serial I/O for command, address, and data
115
ADDRESS2
EPDC_D2
qspi.A_DATA[2]
I/O
Serial I/O for command, address, and data
117
ADDRESS3
EPDC_D3
qspi.A_DATA[3]
I/O
Serial I/O for command, address, and data
119
ADDRESS4
EPDC_D4
qspi.A_DQS
I
Data Strobe signal, required on some high speed
DDR devices
126
DQM0
EPDC_D14
qspi.B_SS0_B
O
Chip Select 0
107
nCS1
EPDC_D15
qspi.B_SS1_B
O
Chip Select 1, used to select second instance of
QuadSPI device (dual die flash require CS0 and
CS1)
95
RDY
EPDC_D13
qspi.B_SCLK
O
Serial Clock
91
nOE,Recovery
Mode
EPDC_D8
qspi.B_DATA[0]
I/O
Serial I/O for command, address, and data
89
nWE
EPDC_D9
qspi.B_DATA[1]
I/O
Serial I/O for command, address, and data
105
nCS0
EPDC_D10
qspi.B_DATA[2]
I/O
Serial I/O for command, address, and data
152
DATA17
EPDC_D11
qspi.B_DATA[3]
I/O
Serial I/O for command, address, and data
150
DATA16
EPDC_D12
qspi.B_DQS
I
Data Strobe signal, required on some high-speed
DDR devices
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Page | 60
Colibri iMX7 Datasheet
5.26 JTAG
The JTAG interface is not normally required for software development with the Colibri iMX7.
There is always the possibility of reprogramming the module using the Recovery Mode over
USB. To flash the module in recovery mode and for debug reasons, it is strongly
recommended that the USBC (USB_OTG1) interface is accessible even if not needed in the
production system. Additionally, UART1 should also be accessible.
The JTAG interface is located on test points on the underside of the module. The location is
the same for all modules in the Colibri family. On the Evaluation Board 3.1 the signals are
accessible through pogo pins. The interface voltage is 3.3V. Hence jumper JP 29 must be in
position 2-3.
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Page | 61
Colibri iMX7 Datasheet
6. Power Management
The Colibri iMX7 has been designed for low power consumption. In order to achieve a
minimum consumption, the module features different run and sleep states. Depending on
the operating system, maybe the software support of some of the sleep states that are
presented in this section is limited. Please check the latest state of the provided OS images
at the developer website.
Main Supply attached
Low power request
No
Supplies
RUN
GPIO Wake event/
IRQ/RTC event
Remove all Supplies
LP
SR
GP
IO
Remove RTC supply
m
Re
eM
ov
ai
u
nS
ly
pp
W
ak
nRESET_EXT Shut down request
ee
ve
nt
sle
e
/R
pr
eq
u
Low
Power
es
t
TC
ev
en
t
LPSR
RTC
only
Shut
Down
Remove Main Supply
Figure 4: Run and Sleep States
Table 6-1 1.1
Power States
Power Rail
No Supply
RTC Only
Shut Down
RUN
Low Power
LPSR
VCC_BATT (RTC Supply)
OFF
ON
ON
ON
ON
ON
3V3 (Module Main Supply)
OFF
OFF
ON
ON
ON
ON
VDD_ARM (CPU Cores)
OFF
OFF
OFF
ON
ON/OFF
OFF
VDD_SOC
OFF
OFF
OFF
ON
ON
OFF
VDD_DRAM
OFF
OFF
OFF
ON
ON
ON/OFF
On module Peripheral 3.3V
OFF
OFF
OFF
ON
ON
OFF
LPSR IO pins
OFF
OFF
OFF
ON
ON
ON
Ethernet
OFF
OFF
OFF
ON/OFF
ON/OFF
OFF
nRESET_OUT
Undefined
Undefined
LOW
HIGH
HIGH
HIGH
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Colibri iMX7 Datasheet
6.1
No Supply
All power rails are removed from the module.
6.2
RTC Only
All power rails are removed from the module, except the VCC_BATT is provided to the
module. The RTC on the module is kept running for keeping the time. The RTC on the
module is not designed for ultra-low power consumption (typical current consumption can
be found in section 9.2). Therefore, a standard lithium coin cell battery can drain faster than
required for certain designs. If a rechargeable RTC battery is not the solution, it is
recommended to use an external ultra-low power RTC IC on the carrier board instead. In this
case, do not provide the VCC_BATT voltage rail at pin 40 during the RTC state. Nevertheless,
the VCC_BATT voltage is required in RUN, Low Power, and LPSR states, but can be sourced
from the same rail as the 3V3 main supply of the module. A suitable reference schematic can
be found in the schematic diagram of the Colibri evaluation board.
6.3
Shut Down
The module has been shut down. Only the software is able to put the module in shut down
state. All ‘On’ module rails are switched ‘Off’, but the carrier board still provides the 3V3
main supply as well as the VCC_BATT. The ‘On’ module RTC is kept running in order to keep
the time. The system can be reactivated from the Shut Down state by pressing the reset
button (this option is not available on all Colibri modules) or by removing and reapplying the
3V3 main supply voltage rail.
6.4
RUN
The system is up and running. The CPU(s) are active and the peripheral modules are enabled.
In this mode, the VDD_ARM voltage might be adjusted according to the CPU frequency in
order to save energy. If the Ethernet port is not required, the PMIC is able to switch off the
supply rails of the PHY in order to reduce the consumption.
6.5
Low Power
When the CPU is not running, the processor can enter the low power mode (sleep mode). The
Colibri iMX7 supports different level of low power modes:

System Idle: The CPU can enter this mode automatically if there is no thread running
anymore. All peripherals can be kept working. The CPU state is retained, so the
interrupt response can be very short.

Low Power Idle: Some of the peripherals are kept still alive while others are shut off.
The interrupt response in this state is longer than in the System Idle, but the power
consumption is much lower.

Suspend: All clocks, unused peripherals and PHYs are off. The DDR3L RAM stays in
Self-Refresh mode. The exit time from this mode is much longer. The SoC can
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Colibri iMX7 Datasheet
request the PMIC to switch off the VDD_ARM rail if L2 Cache does not need to be
retained. All other rails are still available.
6.6
LPSR
The LPSR is considered as an extension of the RTC Only state. In this state, all CPUs,
peripherals, and IO rails are switched off except for the special LPSR IO pins. The DDR3L
RAM can be kept in Self-Refresh mode or switched off. A number of LPSR pins will keep their
state in the LPSR mode and can be configured for waking up the system. The list of these
pins can be found in section 5.2.1.
In order to prevent backfeeding, the carrier board is not allowed to provide any voltage on all
other SODIMM pins (USB OTG data pins can be left connected to a host device). Use one of
the LPSR capable GPIO pins for switching off peripherals on the carrier board that would
backfeed to the regular GPIO pins.
The supported wake up sources from the LPSR mode is RTC alarm as well as any configured
wake event of the LPSR capable GPIO pins.
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Colibri iMX7 Datasheet
7. Recovery Mode
The recovery mode (USB serial loader) can be used to download new software to the Colibri
iMX7 even if the bootloader is no longer capable of booting the module. In the normal
development process, this mode is not needed. When the module is in the recovery mode,
the USBC (USB_OTG1) interface is used to connect it to a host computer. You will find
additional information at our Developer Center: http://developer.toradex.com.
To enter the recovery mode, either connect the recovery mode pads on the front of the
module together (see picture below) or pull SODIMM pin 91 to GND with a 10 KOhm resistor
while power up the module. If the Colibri Evaluation Board V3.x is used, the SW9 button can
be pressed during switching on the power supply for the module.
Important: make sure that there is no bootable SD card plugged into the slot. Otherwise, the
module will try to boot from the external SD card instead of the USB serial loader.
Figure 5: Location of recovery mode pads
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Colibri iMX7 Datasheet
8. Known Issues
Up-to-date information about all known hardware issues. can be found in the errata
document which can be downloaded on our website at:
http://developer.toradex.com/products/colibri-imx7#errata
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Colibri iMX7 Datasheet
9. Technical Specifications
9.1
Absolute Maximum Ratings
Table 9-1 Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
Vmax_3V3
Main power supply
-0.3
3.6
V
Vmax_AVDD
Analogue power supply
-0.3
3.6
V
Vmax_VCC_BATT
RTC power supply
-0.3
3.6
V
Vmax_IO
IO pins with GPIO function
-0.5
3.6
V
Vmax_AN1
ADC and touch analogue input
-0.3
2.1
V
9.2
Electrical Characteristics
Table 9-2 Recommended Operation Conditions
Symbol
Description
Min
Typical
Max
Unit
3V3
Main power supply
3.135
3.3
3.465
V
AVDD
Analogue power supply
3.0
3.3
3.6
V
VCC_BATT
RTC power supply
2.4
3.3
3.6
V
Table 9-3 Typical Power Consumption Colibri iMX7D
Symbol
Description (VCC = 3.3V)
Typical
Unit
IDD_HIGHCPU
Maximal CPU Load
TBD
mA
IDD_IDL
CPU Idle
TBD
mA
IDD_LP_IDL
CPU in Low Power Idle
TBD
mA
IDD_SUSPEND
Module in Suspend State
TBD
mA
IDD_LPSR
Module in LPSR State
TBD
mA
IDD_BATT
Current consumption of internal RTC
TBD
µA
Table 9-4 Typical Power Consumption Colibri iMX7S
Symbol
Description (VCC = 3.3V)
Typical
Unit
IDD_HIGHCPU
Maximal CPU Load
TBD
mA
IDD_IDL
CPU Idle
TBD
mA
IDD_LP_IDL
CPU in Low Power Idle
TBD
mA
IDD_SUSPEND
Module in Suspend State
TBD
mA
IDD_LPSR
Module in LPSR State
TBD
mA
IDD_BATT
Current consumption of internal RTC
TBD
µA
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Colibri iMX7 Datasheet
9.3
Mechanical Characteristics
Figure 6 Mechanical dimensions of the Colibri module (top view)
Tolerance for all measures: +/- 0.1mm
9.3.1
Sockets for the Colibri Modules
The Colibri modules fit into a regular 2.5V (DDR1) SODIMM200 memory socket.
A selection of SODIMM200 socket manufacturers is detailed below:
AUK Connectors:
http://www.aukconnector.com/
CONCRAFT:
http://www.concraft.com.tw/connector_products_ddr.html
Morethanall Co Ltd.:
http://www.morethanall.com/
Tyco Electronics (AMP):
http://www.te.com/usa-en/home.html
NEXUS COMPONENTS GmbH
https://www.nexus-de.com/en
9.4
Thermal Specification
The Colibri iMX7 incorporates DVFS (Dynamic Voltage and Frequency Scaling) and Thermal
Throttling which enables the system to continuously adjust operating frequency and voltage
in response to changes in workload and temperature. This allows the Colibri iMX7 to deliver
higher performance at lower average power consumption compared to other solutions. The
NXP i.MX 7 SoC has an integrated temperature sensor for monitoring the temperature of the
CPU.
Here some general considerations:

If you only use the peak performance for a short time period, heat dissipation is less
of a problem because the advanced power management reduces power consumption
when full performance is not required.

A lower die temperature will also lower the power consumption due to smaller
leakage currents.
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Colibri iMX7 Datasheet
Since the overall power consumption of the Colibri iMX7 is dramatically lower than for
example the Colibri iMX6, for most of the application there is no need for a cooling solution.
Table 9-5 1.1
Module
Thermal Specification
Description
Min
Typ
Max
1
Unit
Colibri iMX7x
Operating temperature range
-20
85
°C
Colibri iMX7x
Storage Temperature
-40
100
°C
Colibri iMX7x
Junction temperature SoC
-20
105
°C
Colibri iMX7x
Thermal Resistance Junction-to-Ambient, i.MX 7 only.
(Theta-JA)2
30.2
°C/W
Colibri iMX7x
Thermal Resistance Junction-to-Top of i.MX 7 chip case.
(Psi-JCtop)2
0.2
°C/W
1
Depending on cooling solution.
A High K JEDEC four layer Board as defined by JEDEC Standard JESD51-6, board mounted horizontal, natural
convection.
2
9.5
Product Compliance
Up-to-date information about product compliance such as RoHS, CE, UL-94, Conflict
Mineral, REACH etc. can be found on our website at:
http://www.toradex.com/support/product-compliance
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Page | 69
Colibri iMX7 Datasheet
DISCLAIMER:
Copyright © Toradex AG. All rights reserved. All data is for information purposes only and not
guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate;
however, no responsibility is assumed for inaccuracies.
Brand and product names are trademarks or registered trademarks of their respective owners.
Specifications are subject to change without notice.
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