Configuration Handbook, Volume 2, Section II.Software Settings

Configuration Handbook, Volume 2, Section II.Software Settings
Section II. Software
Settings
Configuration options can be set in the Quartus® II and MAX+PLUS® II
development software. You can also specify which configuration file
formats Quartus II or MAX+PLUS II generates. This section discusses the
configuration options available, how to set these options in the software,
and how to generate programming files.
This section includes the following chapters:
Revision History
Altera Corporation
■
Chapter 6. Device Configuration Options
■
Chapter 7. Configuration File Formats
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Section II–1
Preliminary
Revision History
Section II–2
Preliminary
Configuration Handbook
Altera Corporation
6. Device Configuration
Options
CF52006-2.2
Introduction
Device configuration options can be set in the Device & Pin Options
dialog box. To open this dialog box, choose Device (Assignments menu),
then click on the Device & Pin Options… radio button. You can specify
your configuration scheme, configuration mode, and your configuration
device used (if applicable) in the Configuration tab of the Device & Pin
Options dialog box (Figure 6–1).
Figure 6–1. Configuration Dialog Box
Altera Corporation
April 2007
6–1
Introduction
The Configuration scheme drop-down list will change with the chosen
device family to only show the configuration schemes supported by that
device family. The Configuration mode selection is only available for
devices that support remote and local update, such as Stratix® and
Stratix GX devices. If you are not using remote or local update, you
should select Standard as your configuration mode. For devices that do
not support remote or local update, the Configuration mode selection
will be greyed out.
If you are using a configuration device, turn on Use configuration device
and specify which configuration device you are using. Choosing the
configuration device will direct the Quartus® II compiler to generate the
appropriate programming object file (.pof). The Use configuration
device drop-down list will change with the chosen device family to only
show the configuration devices that can be used to configure the target
device family. If you choose Auto as the configuration device, the
compiler will automatically choose the smallest density configuration
device that fits your design and the Configuration Device Options…
radio button will be greyed out.
f
For more information about configuration device options, refer to the
appropriate configuration device data sheet.
You can specify how dual-purpose pins should be used after FPGA
configuration is complete through the Dual-Purpose Pins tab of the
Device & Pin Options dialog box. Figure 6–2 shows the Dual-Purpose
Pins tab for a design that targets a Stratix device and is being configured
through PS mode.
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Altera Corporation
April 2007
Device Configuration Options
Figure 6–2. Dual-Purpose Pins Dialog Box
The drop-down lists will be greyed-out if the pins are not available in the
target device family. For the pins that are available, they can be used in
one of four states after configuration: as a regular I/O pin, as inputs that
are tri-stated, as outputs that drive ground, or as outputs that drive an
unspecified signal. If the pin is not used in the mode, the drop-down list
will default to the Use as regular IO choice. For example, in PS mode,
DATA[7..1] are not used, therefore the default usage after configuration
for these pins is as a regular I/O pin. If the pin is reserved as a regular
I/O, the pin can be used as a regular user I/O after configuration.
You can set device options in the Quartus II software from the General
tab of the Device & Pin Options dialog box (see Figure 6–3).
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April 2007
6–3
Configuration Handbook, Volume 2
Introduction
Figure 6–3. Configuration Options Dialog Box
6–4
Configuration Handbook, Volume 2
Altera Corporation
April 2007
Device Configuration Options
You can set device options in the MAX+PLUS® II development software
by choosing Global Project Device Options (Assign menu). Table 6–1
summarizes each of these options.
Table 6–1. Configuration Options (Part 1 of 5)
Device Option
Option Usage
Auto-restart
configuration after
error
When a configuration error
occurs, the FPGA drives
nSTATUS low, which resets
itself internally. The FPGA
will release its nSTATUS pin
after a reset time-out period.
The nSTATUS pin is then
pulled to VCC by a pull-up
resistor, indicating that
reconfiguration can begin.
Default Configuration
(Option Off)
Reconfiguration starts
automatically and the system
does not need to pulse
nCONFIG. After the FPGA
releases nSTATUS and it is
pulled to VCC by a pull-up
resistor, reconfiguration can
begin.
Modified Configuration
(Option On)
The configuration process
stops and to start
reconfiguration the system
must pulse nCONFIG from
high-to-low and back high.
In passive configuration
schemes that use a
configuration device, the
You can choose whether
FPGA’s nSTATUS pin is tied
reconfiguration is started
automatically or manually (by to the configuration device's
OE pin. Hence, the nSTATUS
toggling the nCONFIG pin).
reset pulse also resets the
configuration device
automatically. Once the
FPGA releases nSTATUS
and the configuration device
releases its OE pin (which is
pulled high), reconfiguration
begins.
For more information on how
long the reset time-out period
is, see the appropriate
device family chapters.
Release clears
before tri-states
Altera Corporation
April 2007
During configuration, the
device I/O pins are tri-stated.
During initialization, you can
choose the order for
releasing the tri-states and
clearing the registers.
The device releases the tristates on its I/O pins before
releasing the clear signal on
its registers.
The device releases the
clear signals on its registers
before releasing the tristates. This option allows the
design to operate before the
device drives out, so all
outputs do not start up low.
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Configuration Handbook, Volume 2
Introduction
Table 6–1. Configuration Options (Part 2 of 5)
Device Option
Option Usage
Enable usersupplied start-up
clock (CLKUSR)
(Stratix series,
Cyclone® series,
APEXTM II,
APEX 20K, and
MercuryTM devices
only).
This option allows you to
select which clock source is
used for initialization, either
the internal oscillator or
external clocks provided on
the CLKUSR pin.
Default Configuration
(Option Off)
Modified Configuration
(Option On)
The device’s internal
oscillator (typically 10 MHz)
supplies the initialization
clock and the FPGA will take
care to provide itself with
enough clock cycles for
proper initialization.
The initialization clock must
be provided on the CLKUSR
pin. This clock can
synchronize the initialization
of multiple devices. The
clock should be supplied
when the last data byte is
transferred. Supplying a
clock on CLKUSR will not
affect the configuration
process.
The CLKUSR pin is available
as a user I/O pin.
For more information on how
many clock cycles are
needed to properly initialize a
device, see the appropriate
device family chapters.
Enable usersupplied start-up
clock (CLKUSR)
(ACEX 1K, FLEX
10K, and FLEX
6000 devices
only.)
This option allows you to
select which clock source is
used for initialization, either
external clocks provided on
the CLKUSR pin or on the
DCLK pin.
In PS and PPS schemes, the
internal oscillator is disabled.
Thus, external circuitry, such
as a configuration device or
microprocessor, must
provide the initialization clock
on the DCLK pin.
Programming files generated
by the Quartus II or
MAX+PLUS II software
already have these
initialization clock cycles
included in the file.
In the PPA and PSA
configuration schemes, the
device’s internal oscillator
(typically 10 MHz) supplies
the initialization clock and the
FPGA will take care to
provide itself with enough
clock cycles for proper
initialization.
The initialization clock must
be provided on the CLKUSR
pin. This clock can
synchronize the initialization
of multiple devices. The
clock should be supplied
when the last data byte is
transferred. Supplying a
clock on CLKUSR will not
affect the configuration
process.
For more information on how
many clock cycles are
needed to properly initialize a
device, see the appropriate
device family chapters.
The CLKUSR pin is available
as a user I/O pin.
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Configuration Handbook, Volume 2
Altera Corporation
April 2007
Device Configuration Options
Table 6–1. Configuration Options (Part 3 of 5)
Device Option
Enable devicewide reset
(DEV_CLRn)
Option Usage
Enables a single pin,
DEV_CLRn, to reset all
device registers.
Default Configuration
(Option Off)
Modified Configuration
(Option On)
Chip-wide reset is enabled
Chip-wide reset is not
enabled. The DEV_CLRn pin for all registers in the device.
is available as a user I/O pin. All registers are cleared
when the DEV_CLRn pin is
driven low.
The DEV_CLRn pin cannot
be used to clear only some of
the registers; every device
register is affected by this
global signal.
Enable devicewide output
enable (DEV_OE)
Chip-wide output enable is
Chip-wide output enable is
Enables a single pin,
DEV_OE, to control all device not enabled. The DEV_OE pin enabled for all device triis available as a user I/O pin. states. After configuration, all
tri-states.
user I/O pins are tri-stated
when DEV_OE is low.
The DEV_OE pin cannot be
used to tri-state only some of
the output pins; every output
pin is affected by this global
signal.
Altera Corporation
April 2007
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Configuration Handbook, Volume 2
Introduction
Table 6–1. Configuration Options (Part 4 of 5)
Device Option
Enable
INIT_DONE
output
Option Usage
Enables the INIT_DONE pin,
which signals the end of
initialization and the start of
user-mode with a low-to-high
transition.
Default Configuration
(Option Off)
Modified Configuration
(Option On)
The INIT_DONE signal is not
available. The INIT_DONE
pin is available as a user I/O
pin.
The INIT_DONE signal is
available on the open-drain
INIT_DONE pin. When
nCONFIG is low and during
the beginning of
configuration, the
INIT_DONE pin will be high
due to an external pull-up.
Once the option bit to enable
INIT_DONE is programmed
into the device (during the
first frame of configuration
data), the INIT_DONE pin
will go low. When
initialization is complete, the
INIT_DONE pin will be
released and pulled high.
This low-to-high transition
signals the FPGA has
entered user mode.
For more information on the
value of the external pull-up
resistor, see the appropriate
device family chapters.
Enable JTAG BST
support (FLEX
6000 devices
only.)
Enables post-configuration
JTAG boundary-scan testing
(BST) support in FLEX®
6000 devices.
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Configuration Handbook, Volume 2
JTAG BST can be performed
before configuration;
however, it cannot be
performed during or after
configuration. During JTAG
BST, nCONFIG must be held
low.
JTAG BST can be performed
before or after device
configuration via the four
JTAG pins (TDI, TDO, TMS,
and TCK); however, it cannot
be performed during
configuration. When JTAG
boundary-scan testing is
performed before device
configuration, nCONFIG
must be held low.
Altera Corporation
April 2007
Device Configuration Options
Table 6–1. Configuration Options (Part 5 of 5)
Device Option
Option Usage
Default Configuration
(Option Off)
Modified Configuration
(Option On)
Generate
compressed
bitstreams
(Stratix II and
Cyclone series
devices only)
Enables Stratix II and
Cyclone series FPGAs to
receive compressed
configuration bitstreams in
AS and PS configuration
schemes.
The Quartus II software
generates uncompressed
programming files and
Stratix II and Cyclone series
FPGAs do not decompress
the configuration data.
The Quartus II software
generates compressed
programming files and
Stratix II and Cyclone series
FPGAs decompress the
bitstream during
configuration.
Auto usercode
(Not available in
FLEX 6000
devices.)
Allows you to program a 32bit user electronic signature
into the device during
programming (typically for
design version control).
When the USERCODE
instruction is loaded into the
device, you can shift the
signature out of the device.
If this option is off, the JTAG
user code option is available
and you can specify a 32-bit
hexadecimal number for the
target device. The JTAG
user code is an extension of
the option register. This data
can be read with the JTAG
USERCODE instruction.
Uses the checksum value
from the SRAM Object File
(.sof) as the JTAG user
code. If this option is on, the
JTAG user code option is
dimmed to indicate that it is
not available.
After enhanced configuration and EPC2 device programming you can
choose to automatically configure the targeted FPGAs on board. This can
be done by selecting the Initiate Configuration After Programming
option under the Programmer section of the Options window (Tools
menu). This option is similar to issuing the INIT_CONF JTAG
instruction, which means nINIT_CONF of the enhanced configuration or
EPC2 devices must be connected to the nCONFIG of the FPGA.
f
Altera Corporation
April 2007
For more information on the INIT_CONF JTAG instruction, refer to the
Enhanced Configuration devices Data Sheet or the Configuration Devices for
SRAM-Based LUT Devices Data Sheet.
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Configuration Handbook, Volume 2
Document Revision History
Document
Revision History
Table 6–2 shows the revision history for this document.
Table 6–2. Document Revision History
Date &
Document
Version
Changes Made
April 2007 v2.2
Added document revision history.
August 2005
v2.1
●
Removed active cross references refering to document
outside Chapter 6.
July 2004 v2.0
●
Added Stratix II and Cyclone II device information throughout
chapter.
Updated Default Configuration and Modified Configuration of
“auto-restart configuration after error” option in Table 6–1.
Added paragraph regarding Initiate Configuration After
Programming option on page 6–9.
●
●
September
2003 v1.0
Summary of Changes
Initial Release.
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Configuration Handbook, Volume 2
Altera Corporation
April 2007
7. Configuration File Formats
CF52007-2.2
Introduction
Altera’s Quartus® II and MAX+PLUS® II development tools can create
one or more configuration and programming files to support the
configuration schemes discussed in Volume I. When you compile a
design in the Quartus II and MAX+PLUS II software for a device that has
programming file support, the software will automatically generate a
SRAM Object File (.sof) and a Programmer Object File (.pof) for a
configuration device.
Generating
Configuration
Files
To instruct Quartus II to generate other configuration file formats during
compilation, go to Programming Files tab of the Device & Pin Options
dialog box (see Figure 7–1).
Figure 7–1. Programming Files Dialog Box
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April 2007
7–1
Generating Configuration Files
You can also convert SOF and POF files through the Convert
Programming Files window (File menu). Figure 7–2 shows an example
of the Convert Programming Files dialog box set-up to convert an SOF to
a Raw Binary File (.rbf).
Figure 7–2. Convert Programming Files Dialog Box
When performing multi-device configuration using a configuration
device, you must generate the configuration device’s POF from each
project’s SOF. You can combine multiple SOFs using the Convert
Programming Files dialog box in the Quartus II software. The following
steps explain how to combine multiple SOF files into a POF file(s).
1.
Choose Convert Programming Files... command (File menu).
2.
In the Programming file type list, choose Programming Object File
(.pof).
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April 2007
Configuration File Formats
3.
In the Configuration device list, choose the appropriate
configuration device.
4.
In the Mode list, choose the appropriate configuration scheme.
5.
You can set configuration devices options by selecting the Options...
radio button.
6.
Specify the name of the output file in the File name box.
7.
In the Input files to convert box, click on SOF Data, so that the Add
File… button becomes active.
8.
Click on the Add File… button and select the SOF file to be
converted. This step can be repeated to combine multiple SOF files
into a POF file(s). The order of the SOF files should match the order
of the devices in the chain.
9.
Click OK.
10. When generating multiple POFs for EPC2 or EPC1 devices, the first
device’s POF file name will be as specified, while the second
device’s POF file name will have a “_1” extension (e.g., top_1.pof)
When performing multi-device configuration using an external host,
such as a microprocessor or CPLD, you should generate one combined
configuration file from each project’s SOF. You can combine multiple
SOFs using the Convert Programming Files dialog box in the Quartus II
software. The following steps explain how to combine multiple SOF files
into one configuration file.
Altera Corporation
April 2007
1.
Choose the Convert Programming Files... command (File menu).
2.
In the Programming file type list, choose the appropriate file format
(Hexadecimal (Intel-Format) Output File for SRAM (.hexout), RBF,
or Tabular Text File (.ttf)).
3.
In the Mode list, choose the appropriate configuration scheme.
4.
Specify the name of the output file in the File name box.
5.
In the Input files to convert box, click on SOF Data, so that the Add
File… button becomes active.
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Configuration Handbook, Volume 2
SRAM Object File (.sof)
6.
Click on the Add File… button and select the SOF file to be
converted. This step can be repeated to combine multiple SOF files
into one configuration file. The order of the SOF files (from top to
bottom) should match the order of the devices in the chain.
7.
Click OK.
The following steps explain how to convert a SOF for ACEX® 1K,
FLEX® 10K or FLEX 6000 devices using the MAX+PLUS II software.
1.
In the MAX+PLUS II Compiler or Programmer, choose the Convert
SRAM Object Files command (File menu.)
2.
In the Convert SRAM Object Files dialog box, click on the Select
Programming File… radio button to specify which SOF file to
convert. This step can be repeated to combine multiple SOF files
into one configuration file. The order of the SOF files (from top to
bottom) should match the order of the devices in the chain.
3.
Specify the name of the output file in the File Name box.
4.
Choose the appropriate configuration file format through the File
Format pull-down list.
5.
Click OK.
The following sections give a description of the supported configuration
file formats.
SRAM Object
File (.sof)
You should use a SOF during PS configuration when the configuration
data is downloaded directly to the FPGA using the Quartus II or
MAX+PLUS II software with a USB Blaster, MasterBlasterTM,
ByteBlasterTM II, EthernetBlasterTM or ByteBlasterMVTM cable. The Quartus
II and MAX+PLUS II compiler automatically generates the SOF for your
design. When using a SOF, the Quartus II or MAX+PLUS II software
controls the configuration sequence and automatically inserts the
appropriate headers into the configuration data stream. All other
configuration files are created from the SOF.
Programmer
Object File
(.pof)
A POF is used by the Altera® programming hardware to program a
configuration device. The Quartus II and MAX+PLUS II compiler
automatically generate a POF for your design. For smaller devices (e.g.,
EPF10K20 devices), multiple SOFs can fit into one configuration device;
for larger devices (e.g., APEX 20K devices), multiple configuration
devices may be required to hold the configuration data.
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April 2007
Configuration File Formats
Raw Binary File
(.rbf)
The RBF is a binary file containing the configuration data. The RBF does
not contain byte separators (e.g. commas or carriage returns); it is literally
a raw binary file that contains a binary bitstream of configuration data.
For example, one byte of RBF data is 8 configured bits 10000101
(85 Hex). Data must be stored so that the least significant bit (LSB) of each
data byte is loaded first. The converted image can be stored on a mass
storage device. The microprocessor can then read data from the binary
file and load it into the FPGA. You can also use the microprocessor to
perform real-time conversion during configuration. In the PS
configuration schemes, each byte of data should be sent with LSB first. In
the FPP, PPS, and PPA configuration schemes, the target device receives
its information in parallel from the data bus, a data port on the
microprocessor, or some other byte-wide channel.
f
For more information on creating RBFs, search for “RBF” in Quartus II or
MAX+PLUS II Help.
Raw
Programming
Data File (.rpd)
The RPD File is a binary file containing a binary bitstream of Cyclone®
configuration data. This file is stored in the serial configuration devices in
an embedded environment outside the Quartus II software. The Cyclone
FPGA can then be configured by using the Active Serial (AS)
configuration scheme where the Cyclone FPGA loads the RPD file stored
in the serial configuration device. The RPD file size is equal to the
memory size of the targeted serial configuration device. A RPD file can
only be generated from a POF in the Convert Programming Files dialog
box (File menu).
The RPD file is different from the RBF file, even for a single device
configuration file. In multi-device chains, the RPD file is not the
concatenation of the corresponding RBF files. The LSB of each byte in the
RPD file should be written to the serial configuration device first.
f
Hexadecimal
(Intel-Format)
File (.hex) or
(.hexout)
f
Altera Corporation
April 2007
For more information on creating RPDs, search for “RPD” in Quartus II
Help or refer to the SRunner: An embedded Solution for Serial Configuration
Device Programming White Paper.
A HEX File is an ASCII file in the Intel HEX format. Microprocessors or
external hosts can use the HEX file to store and transmit configuration
data using the configuration schemes supported by microprocessors.
This file can also be used by third-party programmers to program
Altera’s configuration devices.
For more information on creating Hex Files, search for “Hex File” in
Quartus II or MAX+PLUS II Help.
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Configuration Handbook, Volume 2
Tabular Text File (.ttf)
Tabular Text File
(.ttf)
f
Serial Bitstream
File (.sbf)
The TTF is a tabular ASCII file that provides a comma-separated version
of the configuration data for the FPP, PPS, PPA, and bit-wide PS
configuration schemes. In some applications, the storage device
containing the configuration data is neither dedicated to nor connected
directly to the target device. For example, a configuration device can also
contain executable code for a system (e.g., BIOS routines) and other data.
The TTF allows you to include the configuration data as part of the
microprocessor's source code using the include or source commands. The
microprocessor can access this data from a configuration device or massstorage device and load it into the target device. A TTF can be imported
into nearly any assembly language or high-level language compiler.
For more information on creating TTFs, search for “TTF” in Quartus II or
MAX+PLUS II Help.
An SBF is used in PS schemes to configure FLEX 10K and FLEX 6000
devices in-system with the BitBlasterTM cable.
1
f
Jam File (.jam)
f
Jam Byte-Code
File (.jbc)
f
The BitBlaster is obsolete. SBFs are supported by the
MAX+PLUS II software only.
For more information on creating SBFs, search for “SBF” in
MAX+PLUS II Help.
A JamTM File is an ASCII text file in the Jam device programming
language that stores device programming information. These files are
used to program, verify, and blank-check one or more devices in the
Quartus II or MAX+PLUS II Programmer or in an embedded processor
environment.
For more information on creating Jam Files, search for “Jam” in
Quartus II or MAX+PLUS II Help.
A JBC File is a binary file of a Jam File in a byte-code representation. JBC
files store device programming information used to program, verify, and
blank-check one or more devices in the Quartus II or MAX+PLUS II
Programmer or in an embedded processor environment.
For more information on creating JBC Files, search for “JBC” in
Quartus II or MAX+PLUS II Help.
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Configuration Handbook, Volume 2
Altera Corporation
April 2007
Configuration File Formats
Document
Revision History
Table 7–1 shows the revision history for this document.
Table 7–1. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
April 2007 v2.2
Added document revision history.
August 2005
v2.1
Removed active cross references refering to document outside
Chapter 7.
July 2004 v2.0
Added paragraph regarding difference of .rpd from .rbf in the
“Raw Programming Data File (.rpd)” section.
September
2003 v1.0
Initial Release.
Altera Corporation
April 2007
7–7
Configuration Handbook, Volume 2
Document Revision History
7–8
Configuration Handbook, Volume 2
Altera Corporation
April 2007
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