Configuration Handbook

Configuration Handbook
Configuration Handbook, Volume 1
Preliminary Information
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
CF5V1-2.0
Copyright © 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Printed on recycled paper
ii
Preliminary
Altera Corporation
Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ............................................................................... ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ....................................................................................................................... ix
Section I. Altera FPGAs
Revision History ....................................................................................................................... Section I–1
Chapter 1. Configuring Altera FPGAs
Introduction ............................................................................................................................................ 1–1
Device Configuration Overview for Passive Schemes ..................................................................... 1–3
Selecting a Configuration Scheme ....................................................................................................... 1–6
Passive Serial Configuration ........................................................................................................... 1–6
Active Serial Configuration ............................................................................................................ 1–7
Passive Parallel Synchronous Configuration ............................................................................... 1–7
Fast Passive Parallel Configuration ............................................................................................... 1–7
Passive Parallel Asynchronous Configuration ............................................................................ 1–7
Passive Serial Asynchronous Configuration ................................................................................ 1–8
JTAG Configuration ......................................................................................................................... 1–8
Chapter 2. Configuring Stratix II Devices
Introduction ............................................................................................................................................ 2–1
Configuration Devices ..................................................................................................................... 2–1
Configuration Features ......................................................................................................................... 2–4
Configuration Data Decompression .............................................................................................. 2–4
Design Security Using Configuration Bitstream Encryption ..................................................... 2–7
Remote System Upgrade ................................................................................................................. 2–8
VCCPD Pins ......................................................................................................................................... 2–8
VCCSEL Pin ...................................................................................................................................... 2–8
Fast Passive Parallel Configuration .................................................................................................. 2–10
FPP Configuration Using a MAX II Device as an External Host ............................................ 2–11
FPP Configuration Using a Microprocessor ............................................................................... 2–21
FPP Configuration Using an Enhanced Configuration Device ............................................... 2–21
Active Serial Configuration (Serial Configuration Devices) ......................................................... 2–29
Estimating Active Serial Configuration Time ............................................................................ 2–36
Programming Serial Configuration Devices .............................................................................. 2–37
Passive Serial Configuration .............................................................................................................. 2–40
Altera Corporation
iii
Preliminary
Configuration Handbook, Volume 1
PS Configuration Using a MAX II Device as an External Host ...............................................
PS Configuration Using a Microprocessor .................................................................................
PS Configuration Using a Configuration Device .......................................................................
PS Configuration Using a Download Cable ...............................................................................
Passive Parallel Asynchronous Configuration ................................................................................
JTAG Configuration ............................................................................................................................
Jam STAPL ......................................................................................................................................
Device Configuration Pins .................................................................................................................
Conclusion ............................................................................................................................................
2–40
2–48
2–48
2–60
2–65
2–74
2–82
2–83
2–93
Chapter 3. Configuring Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 3–1
Device Configuration Overview ......................................................................................................... 3–2
MSEL[2..0] Pins ................................................................................................................................. 3–3
VCCSEL Pins ........................................................................................................................................ 3–3
PORSEL Pins ..................................................................................................................................... 3–5
nIO_PULLUP Pins ........................................................................................................................... 3–5
TDO & nCEO Pins ............................................................................................................................ 3–6
Configuration File Size ......................................................................................................................... 3–6
Altera Configuration Devices .............................................................................................................. 3–7
Configuration Schemes ......................................................................................................................... 3–7
PS Configuration .............................................................................................................................. 3–7
FPP Configuration .......................................................................................................................... 3–21
PPA Configuration ......................................................................................................................... 3–30
JTAG Programming & Configuration ......................................................................................... 3–36
JTAG Programming & Configuration of Multiple Devices ..................................................... 3–39
Configuration with JRunner Software Driver ............................................................................ 3–41
Jam STAPL Programming & Test Language .............................................................................. 3–42
Configuring Using the MicroBlaster Driver .................................................................................... 3–51
Device Configuration Pins ................................................................................................................. 3–51
Chapter 4. Configuring Cyclone II Devices
Introduction ............................................................................................................................................ 4–1
Cyclone II Configuration Overview ................................................................................................... 4–1
Configuration File Format .................................................................................................................... 4–3
Configuration Data Compression ....................................................................................................... 4–3
Active Serial Configuration (Serial Configuration Devices) ........................................................... 4–6
Single Device AS Configuration ..................................................................................................... 4–7
Multiple Device AS Configuration .............................................................................................. 4–12
Configuring Multiple Cyclone II Devices with the Same Design ........................................... 4–15
Estimating AS Configuration Time ............................................................................................. 4–18
Programming Serial Configuration Devices .............................................................................. 4–18
PS Configuration .................................................................................................................................. 4–21
Single Device PS Configuration Using a MAX II Device as an External Host ...................... 4–22
Multiple Device PS Configuration Using a MAX II Device as an External Host .................. 4–25
PS Configuration Using a Microprocessor ................................................................................. 4–30
Single Device PS Configuration Using a Configuration Device .............................................. 4–31
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Preliminary
Altera Corporation
Contents
Multiple Device PS Configuration Using a Configuration Device .........................................
PS Configuration Using a Download Cable ...............................................................................
JTAG Configuration ............................................................................................................................
Single Device JTAG Configuration ..............................................................................................
JTAG Configuration of Multiple Devices ...................................................................................
Jam STAPL ......................................................................................................................................
Configuring Cyclone II FPGAs with JRunner ............................................................................
Programming Serial Configuration Devices In-System Using the JTAG Interface ..............
Device Configuration Pins .................................................................................................................
Conclusion ............................................................................................................................................
4–36
4–47
4–52
4–54
4–57
4–59
4–59
4–60
4–62
4–68
Chapter 5. Configuring Cyclone FPGAs
Introduction ............................................................................................................................................ 5–1
Device Configuration Overview ......................................................................................................... 5–1
Data Compression ................................................................................................................................. 5–4
Configuration Schemes ......................................................................................................................... 5–8
Active Serial Configuration (Serial Configuration Devices) ...................................................... 5–8
Passive Serial Configuration ......................................................................................................... 5–18
JTAG-Based Configuration ........................................................................................................... 5–31
Combining Configuration Schemes .................................................................................................. 5–45
Active Serial & JTAG ..................................................................................................................... 5–45
Device Configuration Pins ................................................................................................................. 5–46
Chapter 6. Configuring APEX II Devices
Introduction ............................................................................................................................................ 6–1
Passive Serial Configuration ................................................................................................................ 6–2
PS Configuration Using a Configuration Device ......................................................................... 6–2
PS Configuration Using a Microprocessor ................................................................................. 6–17
PS Configuration Using a Download Cable ............................................................................... 6–25
Fast Passive Parallel Configuration .................................................................................................. 6–30
FPP Configuration Using an Enhanced Configuration Device ............................................... 6–30
FPP Configuration Using a Microprocessor ............................................................................... 6–38
Passive Parallel Asynchronous Configuration ................................................................................ 6–46
JTAG Configuration ............................................................................................................................ 6–56
Jam STAPL ...................................................................................................................................... 6–61
Configuring APEX II FPGAs with JRunner ............................................................................... 6–62
Device Configuration Pins ................................................................................................................. 6–62
Chapter 7. Configuring APEX 20KE & APEX 20KC Devices
Introduction ............................................................................................................................................ 7–1
Passive Serial Configuration ................................................................................................................ 7–3
PS Configuration Using a Configuration Device ......................................................................... 7–3
PS Configuration Using a Microprocessor ................................................................................. 7–20
PS Configuration Using a Download Cable ............................................................................... 7–28
Passive Parallel Synchronous Configuration .................................................................................. 7–34
Passive Parallel Asynchronous Configuration ................................................................................ 7–42
JTAG Configuration ............................................................................................................................ 7–52
Altera Corporation
v
Preliminary
Configuration Handbook, Volume 1
Jam STAPL ......................................................................................................................................
Configuring APEX 20KE & APEX 20KC FPGAs with JRunner ..............................................
Device Configuration Pins .................................................................................................................
APEX 20KE Power Sequencing .........................................................................................................
Power Sequencing Considerations ..............................................................................................
7–57
7–58
7–59
7–65
7–66
Chapter 8. Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Introduction ............................................................................................................................................ 8–1
Passive Serial Configuration ................................................................................................................ 8–4
PS Configuration Using a Configuration Device ......................................................................... 8–4
PS Configuration Using a Microprocessor ................................................................................. 8–20
PS Configuration Using a Download Cable ............................................................................... 8–29
Passive Parallel Synchronous Configuration .................................................................................. 8–35
Passive Parallel Asynchronous Configuration ................................................................................ 8–45
JTAG Configuration ............................................................................................................................ 8–57
Jam STAPL ...................................................................................................................................... 8–62
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K FPGAs with JRunner .... 8–63
Device Configuration Pins ................................................................................................................. 8–64
vi
Preliminary
Altera Corporation
Chapter Revision Dates
The chapters in this book, Configuration Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1
Configuring Altera FPGAs
Revised:
July 2004
Part number: CF51001-2.0
Chapter 2
Configuring Stratix II Devices
Revised:
July 2004
Part number: SII52007-1.1
Chapter 3
Configuring Stratix & Stratix GX Devices
Revised:
August 2004
Part number: S52013-3.1
Chapter 4
Configuring Cyclone II Devices
Revised:
June 2004
Part number: CII51013-1.0
Chapter 5
Configuring Cyclone FPGAs
Revised:
August 2004
Part number: C51013-1.2
Chapter 6
Configuring APEX II Devices
Revised:
July 2004
Part number: CF51004-2.0
Chapter 7
Configuring APEX 20KE & APEX 20KC Devices
Revised:
July 2004
Part number: CF51005-2.0
Chapter 8
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Revised:
July 2004
Part number: CF51006-2.0
Altera Corporation
vii
Preliminary
Configuration Handbook, Volume 1
viii
Preliminary
Altera Corporation
About this Handbook
This handbook provides comprehensive information about configuring
Altera® FPGAs and configuration devices.
How to Contact
Altera
Information Type
Technical support
Product literature
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.
USA & Canada
All Other Locations
www.altera.com/mysupport/
altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time)
(408) 544-7000 (1)
(7:00 a.m. to 5:00 p.m. Pacific Time)
www.altera.com
www.altera.com
Altera literature services
[email protected] (1)
[email protected] (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m. Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note to table:
(1)
You can also contact your local Altera sales office or sales representative.
Typographic
Conventions
Visual Cue
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN
75: High-Speed Board Design.
Altera Corporation
ix
Preliminary
Typographic Conventions
Visual Cue
Italic type
Configuration Handbook, Volume 1
Meaning
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
w
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
x
Preliminary
Altera Corporation
Section I. Altera FPGAs
This section provides information on how to configure Altera® FPGAs.
The following chapters contain descriptions of the supported
configuration schemes and configuration pins.
This section includes the following chapters:
Revision History
Chapter
1
■
Chapter 1, Configuring Altera FPGAs
■
Chapter 2, Configuring Stratix II Devices
■
Chapter 3, Configuring Stratix & Stratix GX Devices
■
Chapter 4, Configuring Cyclone II Devices
■
Chapter 5, Configuring Cyclone FPGAs
■
Chapter 6, Configuring APEX II Devices
■
Chapter 7, Configuring APEX 20KE & APEX 20KC Devices
■
Chapter 8, Configuring Mercury, APEX 20K (2.5 V), ACEX 1K &
FLEX 10K Devices
The table below shows the revision history for Chapters 1 through 8.
Date/Version
July 2004, v2.0
Changes Made
●
●
2
Added Stratix II and Cyclone II Device information throughout chapter.
Updated Figure 1–2.
September 2003, v1.0
Initial Release.
July 2004, v1.1
●
●
●
●
●
February 2004, v1.0
Altera Corporation
Removed reference to PLMSEPC-8 adapter from “Programming Serial
Configuration Devices” section.
Updated Tables 2–7 and 2–15.
Updated Figure 2–2.
Updated “VCCSEL Pin”, “Configuration Devices”, and “Design Security
Using Configuration Bitstream Encryption” sections.
Added timing specifications for CONF_DONE high to user mode with
CLKUSR option on.
Shared Stratix II Device Handbook, Volume 2, Chapter 7.
Section I–1
Preliminary
Configuration Handbook, Volume 1
Chapter
3
Date/Version
Changes Made
August 2004, v3.1
●
Corrected spelling error.
April 2004, v3.0
●
In the “PORSEL Pins” section and the “nIO_PULLUP Pins” section,
several pull-down resistors were changed to pull-up resistors.
Updated notes in Figure 3–3.
Two vertical VCC lines removed in Figures 3–12 to 3–14.
Three paragraphs added regarding the CONF_DONE and INIT_DONE
pins in the “PS Configuration with a Microprocessor” section.
Value in Note 1 changed in Tables 3–8 and 3–9.
Deleted reference to AS in Table 3–15 because Stratix does not
support AS mode.
Text added before callout of Figure 3–7.
●
●
●
●
●
●
July 2003, v2.0
●
●
Shared Stratix Device Handbook, Volume 2, Chapter 13.
Updated to new template layout.
4
June 2004, v1.0
Shared Cyclone II Device Handbook, Volume 1, Chapter 13.
5
August 2004, v1.2
●
●
●
●
●
●
6
July 2003, v1.1
Shared Cyclone Device Handbook, Volume 1, Chapter 13.
July 2004, v2.0
●
●
7
Section I–2
Preliminary
Updated .rbf sizes in Table 6–2.
Updated nCEO description in Table 6–8.
September 2003, v1.0
Initial Release.
July 2004, v2.0
●
●
8
Deleted sections: Programming Configuration Devices, Connecting
the JTAG Chain, Passive Serial and JTAG, Device Options, Device
Configuration Files, Configuration Reliability, and Board Layout Tips.
Deleted figures: Embedded System Block Diagram, Combining PS &
JTAG Configuration, Configuration Options Dialog Box.
Deleted table: Cyclone Configuration Option Bits.
Added: USB Blaster to cable list; new Figure 5–13; text on pages 1314, 13-29, and 13-30, and information to Table 5–6.
Changes to Figures 5–14 to 5–16, 5–19, 5–20, 5–25; numbers
changed in EP1C4 row of Table 5–3.
Added extensive descriptions of configuration methods under the
“Configuring Multiple Devices with the Same Data” section.
Updated resistor values in Figure 7–25.
Updated nCEO description in Table 7–8.
September 2003, v1.0
Initial Release.
July 2004, v2.0
Updated nCEO description in Table 8–19.
September 2003, v1.0
Initial Release.
Altera Corporation
Chapter 1. Configuring Altera
FPGAs
CF51001-2.0
Introduction
Stratix® series, Cyclone™ series, APEX™ II, APEX 20K (including
APEX 20KE and APEX 20KC), Mercury™, ACEX® 1K, FLEX® 10K
(including FLEX 10KE and FLEX 10KA), and FLEX 6000 devices can be
configured using one of seven configuration schemes. Table 1–1 shows
which device families support which configuration schemes.
Table 1–1. Configuration Scheme Device Family Support
Device Family
Configuration
Stratix,
Stratix
Cyclone
Scheme
Stratix
Cyclone APEX II
II
II
GX
Passive Serial
(PS)
v
Active Serial
(AS)
v
Fast Passive
Parallel (FPP)
v
v
v
v
v
v
v
v
v
ACEX
1K
FLEX
10K,
FLEX
10KE,
FLEX
10KA
FLEX
6000
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Passive
Parallel
Synchronous
(PPS)
Passive
Parallel
Asynchronous
(PPA)
APEX
20K,
APEX
Mercury
20KE,
APEX
20KC
v
v
v
Passive Serial
Asynchronous
(PSA)
Joint Test
Action Group
(JTAG)
v
v
v
v
v
v
v
v
v
(1)
Note to Table 1–1:
(1)
Although you cannot configure FLEX 6000 devices through the JTAG pins, you can perform JTAG boundary-scan
testing.
Altera Corporation
July 2004
Core Version a.b.c variable
1–1
Preliminary
Introduction
All configuration schemes use either an intelligent host or a configuration
device(s) (see Table 1–2).
Table 1–2. Configuration Schemes
Configuration Scheme
Typical Use
Passive Serial (PS)
Configuration with the enhanced configuration devices (EPC16, EPC8,
and EPC4), EPC2, EPC1, EPC1441 configuration devices, serial
synchronous microprocessor interface, the USB Blaster USB Port
Download Cable, MasterBlasteTMr communications cable, ByteBlasterTM
II parallel download cable or ByteBlasterMVTM parallel port download
cable.
Active Serial (AS)
Configuration with the serial configuration devices (EPCS1 and EPCS4).
Passive Parallel Synchronous (PPS) Configuration with a parallel synchronous microprocessor interface.
Fast Passive Parallel (FPP)
Configuration with an enhanced configuration device or parallel
synchronous microprocessor interface where 8 bits of configuration data
are loaded on every clock cycle. Eight times faster than PPS.
Passive Parallel Asynchronous
(PPA)
Configuration with a parallel asynchronous microprocessor interface. In
this scheme, the microprocessor treats the target device as memory.
Passive Serial Asynchronous (PSA) Configuration with a serial asynchronous microprocessor interface.
Joint Test Action Group (JTAG)
Configuration through the IEEE Std. 1149.1 (JTAG) pins. (1)
The following chapters discuss how to configure one or more Stratix
series, Cyclone series, APEX II, APEX 20K (including APEX 20KE and
APEX 20KC), Mercury, ACEX 1K, FLEX 10K (including FLEX 10KE and
FLEX 10KA), and FLEX 6000 devices. The following chapters should be
used in conjunction with the following documents:
■
■
■
■
■
■
■
■
■
■
■
■
■
Stratix II Device Handbook
Stratix Device Handbook
Stratix GX FPGA Family Data Sheet
Cyclone II Device Handbook
Cyclone Device Handbook
APEX II Programmable Logic Device Family Data Sheet
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KC Programmable Logic Device Data Sheet
Mercury Programmable Logic Device Family Data Sheet
ACEX 1K Programmable Logic Device Family Data Sheet
FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10KE Embedded Programmable Logic Family Data Sheet
FLEX 6000 Programmable Logic Device Family Data Sheet
Volume I will cover how to configure Altera FPGAs, where each chapter
covers a different device family. Each subsection describes how to
configure the devices with the following configuration schemes:
1–2
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Altera FPGAs
■
■
■
■
■
■
■
PS Configuration
●
Using a Configuration Device
●
Using a Microprocessor
●
Using a Download Cable
AS Configuration (Stratix II FPGAs and the Cyclone Series Only)
FPP Configuration (Stratix Series and APEX II Devices Only)
●
Using an enhanced Configuration Device
●
Using a Microprocessor
PPS Configuration (APEX 20K, Mercury, ACEX 1K, and FLEX 10K
Devices Only)
PPA Configuration (Stratix Series, APEX II, APEX 20K, Mercury,
ACEX 1K, and FLEX 10K Devices Only)
PSA Configuration (FLEX 6000 Devices Only)
JTAG Programming and Configuration (Stratix Series,
Cyclone Series, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX
10K Devices Only)
Volume II contains information that is relevant for all Altera FPGAs
discussed in this handbook. Information about configuration devices and
combining different Altera device families in the same configuration
chain can be found in this volume.
Device
Configuration
Overview for
Passive
Schemes
During device operation, Altera FPGAs store configuration data in
SRAM cells. Because SRAM memory is volatile, the SRAM cells must be
loaded with configuration data each time the device powers up. After the
device is configured, its registers and I/O pins must be initialized. After
initialization, the device enters user mode for in-system operation.
Figure 1–1 shows the waveform of the configuration pins during
configuration, initialization, and user-mode.
Figure 1–1. Configuration Cycle Waveform
D(N – 1)
nCONFIG
nSTATUS
CONF_DONE
DCLK
DATA High-Z
User I/Os
D0
D1
D2
D3
DN
High-Z
High-Z
User I/O
INIT_DONE
MODE
Altera Corporation
July 2004
Configuration
Configuration
Core Version a.b.c variable
Initialization
User- Mode
1–3
Configuration Handbook, Volume 1
Device Configuration Overview for Passive Schemes
The low-to-high transition of nCONFIG on the FPGA begins the
configuration cycle. The configuration cycle consists of 3 stages: reset,
configuration, and initialization. While nCONFIG is low, the device is in
reset. When the device comes out of reset, nCONFIG must be at a logic
high level in order for the device to release the open-drain nSTATUS pin.
Once nSTATUS is released, it is pulled high by a pull-up resistor and the
FPGA is ready to receive configuration data. Before and during
configuration all user I/O pins are tri-stated. Stratix series, Cyclone
series, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10KE devices
have weak pull-up resistors on the I/O pins which are on before and
during configuration.
nCONFIG and nSTATUS must be at a logic high level in order for the
configuration stage to begin. The device receives configuration data on its
DATA pin(s) and (for synchronous configuration schemes) the clock
source on the DCLK pin. Configuration data is latched into the FPGA on
the rising edge of DCLK. After the FPGA has received all configuration
data successfully it releases the CONF_DONE pin, which is pulled high by
a pull-up resistor. A low to high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode. During initialization, internal
logic, internal and I/O registers are initialized and I/O buffers are
enabled. When initialization is finished, the INIT_DONE pin is released
and pulled high by an external pull-up resistor. Once in user-mode, the
user I/O pins will no longer have a weak pull-up and will function as
assigned in your design. The DCLK, DATA (FLEX 6000), and DATA0
(Stratix series, Cyclone series, APEX II, APEX 20K, Mercury, ACEX 1K,
and FLEX 10KE) pins should not be left floating after configuration; they
should be driven high or low, whichever is convenient, on your board.
A reconfiguration is initiated by toggling the nCONFIG pin from high to
low and then back to high. When nCONFIG is pulled low, nSTATUS and
CONF_DONE are also pulled low and all I/O pins are tri-stated. Once
nCONFIG and nSTATUS return to a logic high level, configuration begins.
Figure 1–2 shows a simple state diagram of the configuration process.
1–4
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Altera FPGAs
Figure 1–2. Configuration Cycle State Machine
Power Up
Power supply not stable
nSTATUS & CONF_DONE driven low
All I/Os tri-stated
Configuration RAM bits cleared
Power supply reached
recommended operating voltage
Reset
nCONFIG or nSTATUS held low
nSTATUS & CONF_DONE driven low
All I/Os tri-stated
MSEL pins sampled
Configuration RAM bits cleared
nCONFIG at logic high &
nSTATUS released and at a logic high
Configuration
nCONFIG driven low
or CRC error occured
CONF_DONE low
Configuration data written
to device
CONF_DONE released &
pulled high by pull-up resistor
Initialization
nCONFIG pulled low
Need more initalization clocks
Internal logic and registers initialized
I/O buffers enabled
INIT_DONE released
(if option enabled)
Initialization complete
nCONFIG pulled low
Altera Corporation
July 2004
User-Mode
Core Version a.b.c variable
1–5
Configuration Handbook, Volume 1
Selecting a Configuration Scheme
Selecting a
Configuration
Scheme
The configuration data for Altera devices can be loaded using an active,
passive or JTAG configuration scheme. When using an active
configuration scheme with a serial configuration device, the target FPGA
generates the control and synchronization signals. When both devices are
ready to begin configuration, the serial configuration device sends data to
the FPGA.
When using any passive configuration scheme, the Altera device is
incorporated into a system with an Altera configuration device or an
intelligent host, such as a microprocessor, that controls the configuration
process. The configuration device or host supplies configuration data
from a storage device (a configuration device(s), a hard disk, RAM, or
other system memory). When using passive configuration, you can
change the target device's functionality while the system is in operation
by reconfiguring it.
Altera devices support a number of configuration schemes. Not all device
families support all configuration schemes. Table 1–1 and the individual
device family sections should be referenced to determine if your target
device family supports your intended configuration scheme. Once you
have decided on the appropriate configuration scheme for your system,
you will need to drive the dedicated mode select control pins, MSEL, of
the FPGA to set the configuration mode.
f
For further details on how to set the MSEL pins for your target device,
refer to the appropriate device family chapters.
Below is a brief description of each configuration scheme. For detailed
information, consult the appropriate sections.
Passive Serial Configuration
The PS configuration scheme is supported in the Stratix series, Cyclone
series, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, and
FLEX 6000 device families. PS configuration can be performed by using
an Altera download cable, an Altera enhanced configuration device or
configuration device, or an intelligent host, such as a microprocessor.
During PS configuration, configuration data is transferred from a storage
device, such as a configuration device or flash memory, to the FPGA on
the DATA (FLEX 6000) or DATA0 (Stratix series, Cyclone series, APEX II,
APEX 20K, Mercury, ACEX 1K, and FLEX 10K) pin. This configuration
data is latched into the FPGA on the rising edge of DCLK. Configuration
data is transferred one bit per clock cycle.
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Configuring Altera FPGAs
Active Serial Configuration
The AS configuration scheme is supported in the Stratix II and Cyclone
series device families. AS configuration can be performed by using an
Altera Serial Configuration device. During AS configuration, the
Stratix II or Cyclone series device is the master and the configuration
device is the slave. Configuration data is transferred to the FPGA on the
DATA0 pin. This configuration data is synchronized to the DCLK input.
Configuration data is transferred one bit per clock cycle.
Passive Parallel Synchronous Configuration
The PPS configuration scheme is supported in the APEX 20K, Mercury,
ACEX 1K and FLEX 10K device families. PPS configuration can be
performed by using an intelligent host, such as a microprocessor. During
PPS configuration, configuration data is transferred from a storage
device, such as flash memory, to the FPGA on the DATA[7..0] pins. This
configuration data is synchronized to the DCLK input. On the first rising
edge of DCLK, a byte of configuration data is latched into the FPGA. The
next 8 falling edges of DCLK are needed to internally serialize the data in
the FPGA.
Fast Passive Parallel Configuration
The FPP configuration scheme is supported in the Stratix series and
APEX II device families. FPP configuration can be performed by using an
Altera enhanced configuration device, or an intelligent host, such as a
microprocessor. During FPP configuration, configuration data is
transferred from a storage device, such as an enhanced configuration
device or flash memory, to the FPGA on the DATA[7..0] pins. This
configuration data is latched into the FPGA on the rising edge of DCLK.
Configuration data is transferred one byte per clock cycle.
Passive Parallel Asynchronous Configuration
The PPA configuration scheme is supported in the Stratix series, APEX II,
APEX 20K, Mercury, ACEX 1K and FLEX 10K device families. PPA
configuration can be performed by using an intelligent host, such as a
microprocessor. During PPA configuration, configuration data is
transferred from a storage device, such as a configuration device or flash
memory, to the FPGA on the DATA[7..0] pins. Since this configuration
scheme is asynchronous, control signals are used to regulate the
configuration cycle.
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Selecting a Configuration Scheme
Passive Serial Asynchronous Configuration
The PSA configuration scheme is supported in the FLEX 6000 device
family. PSA configuration can be performed by using an intelligent host,
such as a microprocessor. During PSA configuration, configuration data
is transferred from a storage device, such as a configuration device or
flash memory, to the FPGA on the DATA pin. Since this configuration
scheme is asynchronous, control signals are used to regulate the
configuration cycle.
JTAG Configuration
The JTAG configuration scheme is supported in the Stratix series,
Cyclone series, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K
device families. JTAG configuration uses the IEEE Std 1149.1 JTAG
interface pins and supports the JAM STAPL standard. JTAG
configuration can be performed by using an Altera download cable or an
intelligent host, such as a microprocessor.
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Chapter 2. Configuring
Stratix II Devices
SII52007-1.1
Introduction
Stratix® II devices use SRAM cells to store configuration data. Since
SRAM memory is volatile, configuration data must be downloaded to
Stratix II devices each time the device powers up. Stratix II devices can be
configured using one of five configuration schemes: the fast passive
parallel (FPP), active serial (AS), passive serial (PS), passive parallel
asynchronous (PPA), and Joint Test Action Group (JTAG) configuration
schemes. All configuration schemes use either an external controller (for
example, a MAX® II device or microprocessor) or a configuration device.
Configuration Devices
The Altera enhanced configuration devices (EPC16, EPC8, and EPC4)
support a single-device configuration solution for high-density devices
and can be used in the FPP and PS configuration schemes. They are ISPcapable through its JTAG interface. The enhanced configuration devices
are divided into two major blocks, the controller and the flash memory.
1
For information on enhanced configuration devices, see the
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
chapter and the Using Altera Enhanced Configuration Devices
chapter in the Configuration Handbook.
The Altera serial configuration devices (EPCS4 and EPCS1) support a
single-device configuration solution for Stratix II devices and are used in
the AS configuration scheme. Serial configuration devices offer a low
cost, low pin count configuration solution.
1
For information on serial configuration devices, see the Serial
Configuration Devices (EPCS1 & EPCS4) Data Sheet chapter.
The EPC2 and EPC1 configuration devices provide configuration support
for the PS configuration scheme. The EPC2 device is ISP-capable through
its JTAG interface. The EPC2 and EPC1 can be cascaded to hold large
configuration files.
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July 2004
For more information on EPC2, EPC1, and EPC1441
configuration devices, see the Configuration Devices for SRAMBased LUT Devices Data Sheet chapter.
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Preliminary
Introduction
The configuration scheme is selected by driving the Stratix II device MSEL
pins either high or low as shown in Table 2–1. The MSEL pins are powered
by the VCCPD power supply of the bank they reside in. The MSEL[3..0]
pins have 5-kΩ internal pull-down resistors that are always active.
During POR and during reconfiguration, the MSEL pins have to be at
LVTTL VIL and VIH levels to be considered a logic low and logic high.
1
To avoid any problems with detecting an incorrect
configuration scheme, hard-wire the MSEL[] pins to VCCPD and
GND, without any pull-up or pull-down resistors. Do not drive
the MSEL[] pins by a microprocessor or another device.
Table 2–1. Stratix II Configuration Schemes
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0
0
0
0
Passive parallel asynchronous (PPA)
0
0
0
1
Passive serial (PS)
0
0
1
0
Remote system upgrade FPP (1)
0
1
0
0
Remote system upgrade PPA (1)
0
1
0
1
Remote system upgrade PS (1)
0
1
1
0
Fast AS (40 MHz) (2)
1
0
0
0
Remote system upgrade fast AS (40 MHz) (2)
1
0
0
1
FPP with decompression and/or design security
feature enabled (3)
1
0
1
1
Remote system upgrade FPP with decompression
and/or design security feature enabled (1), (3)
1
1
0
0
AS (20 MHz) (2)
1
1
0
1
Remote system upgrade AS (20 MHz) (2)
1
1
1
0
(4)
(4)
(4)
(4)
JTAG-based configuration (5)
Notes to Table 2–1:
(1)
(2)
(3)
(4)
(5)
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrades in Stratix II devices, see Chapter 8, Remote System Upgrades with Stratix II
Devices in Volume 2 of the Stratix II Device Handbook.
Only the EPCS16 and EPCS64 devices support up to a 40 MHz DCLK. Other EPCS devices support up to a 20 MHz
DCLK. See the Serial Configuration Devices Data Sheet for more information.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
Do not leave the MSEL pins floating. Connect them to VCCPD or ground. These pins support the non-JTAG
configuration scheme used in production. If only JTAG configuration is used, you should connect the MSEL pins
to ground.
JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are
ignored.
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Configuring Stratix II Devices
Stratix II devices offer the design security, decompression, and remote
system upgrade features. Design security using configuration bitstream
encryption is available in Stratix II devices, which protects your designs.
Stratix II devices can receive a compressed configuration bit stream and
decompress this data in real-time, reducing storage requirements and
configuration time. You can make real-time system upgrades from
remote locations of your Stratix II designs by using the remote system
upgrade feature.
Table 2–2 shows the approximate uncompressed configuration file sizes
for Stratix II devices.
Table 2–2. Stratix II .rbf Sizes
Device
Notes (1), (2)
Data Size (MBits)
Data Size (MBytes)
EP2S15
5.0
0.625
EP2S30
10.1
1.2625
EP2S60
17.1
2.1375
EP2S90
27.5
3.4375
EP2S130
39.6
4.95
EP2S180
52.4
6.55
Notes to Table 2–2:
(1)
(2)
These values are preliminary.
.rbf: Raw Binary File.
Use the data in Table 2–2 to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II software, any design
targeted for the same device will have the same uncompressed
configuration file size. If you are using compression, the file size can vary
after each compilation since the compression ratio is dependent on the
design.
This chapter explains the Stratix II device configuration features and
describes how to configure Stratix II devices using the supported
configuration schemes. This chapter configuration pin descriptions and
the Stratix II device configuration file format. In this chapter, the generic
term device(s) includes all Stratix II devices.
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July 2004
For more information on setting device configuration options or creating
configuration files, see Software Settings in Volume 2 of the Configuration
Handbook.
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Configuration Features
Configuration
Features
Stratix II devices offer configuration data decompression to reduce
configuration file storage, design security using data encryption to
protect your designs, and remote system upgrades to allow for remotely
updating your Stratix II designs. Table 2–3 summarizes which
configuration features can be used in each configuration scheme.
Table 2–3. Stratix II Configuration Features
Configuration
Scheme
FPP
Configuration Method
MAX II device or a Microprocessor with
flash memory
Design Security Decompression
v (1)
v (1)
Remote System
Upgrade
v
v (2)
v
AS
Serial Configuration Device
v
v
v (3)
PS
MAX II device or a Microprocessor with
flash memory
v
v
v
Enhanced Configuration Device
v
v
v
Download cable
v
v
Enhanced Configuration Device
PPA
MAX II device or a Microprocessor with
flash memory
JTAG
MAX II device or a Microprocessor with
flash memory
v
Notes to Table 2–3:
(1)
(2)
(3)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Stratix II decompression feature
is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
Configuration Data Decompression
Stratix II devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store
compressed configuration data in configuration devices or other memory
and transmit this compressed bit stream to Stratix II devices. During
configuration, the Stratix II device decompresses the bit stream in real
time and programs its SRAM cells.
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Preliminary data indicates that compression typically reduces
configuration bit stream size by 35 to 55%.
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Configuring Stratix II Devices
Stratix II devices support decompression in the FPP (when using a
MAX II device/microprocessor + flash), AS, and PS configuration
schemes. Decompression is not supported in the PPA configuration
scheme nor in JTAG-based configuration.
1
When using FPP mode, the intelligent host must provide a DCLK
that is 4× the data rate. Therefore, the configuration data must
be valid for four DCLK cycles.
The decompression feature supported by Stratix II devices is different
from the decompression feature in enhanced configuration devices
(EPC16, EPC8, and EPC4 devices), although they both use the same
compression algorithm. The data decompression feature in the enhanced
configuration devices allows them to store compressed data and
decompress the bitstream before transmitting it to the target devices.
When using Stratix II devices in FPP mode with enhanced configuration
devices, the Stratix II decompression feature is not available, but the
enhanced configuration device decompression feature is.
In PS mode, you should use the Stratix II decompression feature since
sending compressed configuration data reduces configuration time. You
should not use both the Stratix II device and the enhanced configuration
device decompression features simultaneously. The compression
algorithm is not intended to be recursive and could expand the
configuration file instead of compressing it further.
When you enable compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash
memory, and decreases the time needed to transmit the bitstream to the
Stratix II device. The time required by a Stratix II device to decompress a
configuration file is less than the time needed to transmit the
configuration data to the device.
There are two methods to enable compression for Stratix II bitstreams:
before design compilation (in the Compiler Settings menu) and after
design compilation (in the Convert Programming Files window).
To enable compression in the project’s compiler settings, select Device
under the Assignments menu to bring up the Settings window. After
selecting your Stratix II device, open the Device & Pin Options window,
and in the General settings tab enable the check box for Generate
compressed bitstreams (as shown in Figure 2–1).
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Configuration Features
Figure 2–1. Enabling Compression for Stratix II Bitstreams in Compiler
Settings
Compression can also be enabled when creating programming files from
the Convert Programming Files window.
1.
Click Convert Programming Files (File menu).
2.
Select the programming file type (POF, SRAM HEXOUT, RBF, or
TTF).
3.
For POF output files, select a configuration device.
4.
In the Input files to convert box, select SOF Data.
5.
Select Add File and add a Stratix II device SOF(s).
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Configuring Stratix II Devices
6.
Select the name of the file you added to the SOF Data area and click
Properties.
7.
Check the Compression check box.
When multiple Stratix II devices are cascaded, the compression feature
can be selectively enabled for each device in the chain if you are using a
serial configuration scheme. Figure 2–2 depicts a chain of two Stratix II
devices. The first Stratix II device has compression enabled and therefore
receives a compressed bit stream from the configuration device. The
second Stratix II device has the compression feature disabled and
receives uncompressed data.
In a multi-device FPP configuration chain all Stratix II devices in the
chain must either enable of disable the decompression feature. You can
not selectively enable the compression feature for each device in the chain
because of the DATA and DCLK relationship.
Figure 2–2. Compressed and Uncompressed Configuration Data in the Same
Configuration File
Serial Configuration Data
Serial or Enhanced
Configuration
Device
Uncompressed
Configuration
Data
Compressed
Configuration
Data
Decompression
Controller
Stratix II FPGA
nCE
nCEO
Stratix II FPGA
nCE
nCEO
N.C.
GND
You can generate programming files for this setup from the Convert
Programming Files window (File menu) in the Quartus II software.
Design Security Using Configuration Bitstream Encryption
Stratix II devices are the industry's first devices with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm—the most advanced encryption algorithm available
today. When using the design security feature, a 128-bit security key is
stored in the Stratix II device. In order to successfully configure a
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Configuration Features
Stratix II device which has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.
1
An encryption configuration file is the same size as a nonencryption configuration file. When using a serial configuration
scheme such as passive serial (PS) or active serial (AS),
configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme us used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, contact Altera applications.
Remote System Upgrade
Stratix II devices feature remote and local update. For more information
about this feature, see Chapter 8, Remote System Upgrades with Stratix II
Devices in Volume 2 of the Stratix II Device Handbook.
VCCPD Pins
Stratix II devices also offer a new power supply, VCCPD, which must be
connected to 3.3-V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. VCCPD applies to all the JTAG
pins (TCK, TMS, TDI, TDO, and TRST) and the configuration pins:
nCONFIG, DCLK (when used as an input), nIO_Pullup, DATA[7..0],
RUnLU, nCE, nCEO, nWS, nRS, CS, nCS and CLKUSR.
1
VCCPD must ramp-up from 0-V to 3.3-V within 100 ms. If VCCPD
is not ramped up within this specified time, your Stratix II
device will not configure successfully. If your system does not
allow for a VCCPD ramp-up time of 100 ms or less, you must hold
nCONFIG low until all power supplies are stable.
VCCSEL Pin
The VCCSEL pin allows the VCCIO setting (of the banks where the
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting VCCIO, the VIL and VIH
levels driven to the configuration inputs are not a factor.
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Configuring Stratix II Devices
The configuration input pins (nCONFIG, DCLK (when used as an input),
nIO_Pullup, RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR) have a dual
buffer design. These pins have a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input
buffer is used during configuration. After configuration, the dualpurpose configuration pins are powered by the VCCIO pins. The
3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V
input buffer is powered by VCCIO.
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by VCCPD and has an internal 5-kΩ pull-down resistor
that is always active.
1
VCCSEL must be hardwired to VCCPD or GND.
A logic high selects the 1.8-V/1.5-V input buffer, and a logic low selects
the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the
logic levels driven out of the configuration device or MAX II device or a
microprocessor with flash memory.
If you need to support 3.3-V or 2.5-V configuration input voltages, set
VCCSEL low. You can set the bank VCCIO that contains the configuration
inputs to any supported voltage. If you need to support 1.8-V or 1.5-V
configuration input voltages, set VCCSEL to a logic high and the VCCIO of
the bank that contains the configuration inputs to 1.8 or 1.5-V.
VCCSEL also sets the POR trip point for I/O bank 8 to ensure that this I/O
bank has powered up to the appropriate voltage levels before
configuration begins. Upon power-up, the device will not release
nSTATUS until VCCINT and VCCIO of bank 8 is above its POR trip point. If
you set VCCSEL to ground (logic low), this sets the POR trip point for
bank 8 to a voltage consistent with 3.3-V/2.5-V signaling, which means
the POR trip point for these I/O banks may be as high as 1.8V. If VCCIO of
any of the configuration banks is set to 1.8-V or 1.5-V, the voltage
supplied to this I/O bank(s) may never reach the POR trip point, which
will cause the device to never begin configuration.
If the VCCIO of I/O bank 8 is set to 1.5-V or 1.8-V and the configuration
signals used require 3.3-V or 2.5-V signaling, you should set VCCSEL to
VCCPD (logic high) in order to lower the POR trip point to enable
successful configuration.
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Fast Passive Parallel Configuration
Table 2–4 shows how you should set the VCCSEL depending on the VCCIO
setting of bank 8 and your configuration input signaling voltages.
Table 2–4. VCCSEL Setting
VCCIO (bank 8)
Configuration Input Signaling Voltage
VCCSEL
3.3-V/2.5-V
3.3-V/2.5-V
GND
1.8-V/1.5-V
3.3-V/2.5-V/1.8-V/1.5-V
VCCPD
3.3-V/2.5-V
1.8-V/1.5-V
Not Supported
The VCCSEL signal does not control any of the dual-purpose pins,
including the dual-purpose configuration pins, such as the DATA[7..0]
and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration,
these dual-purpose pins will drive out voltage levels corresponding to
the VCCIO supply voltage that powers the I/O bank containing the pin.
After configuration, the dual-purpose pins inherit the I/O standards
specified in the design.
Fast Passive
Parallel
Configuration
Fast passive parallel (FPP) configuration in Stratix II devices is designed
to meet the continuously increasing demand for faster configuration
times. Stratix II devices are designed with the capability of receiving bytewide configuration data per clock cycle. Table 2–5 shows the MSEL pin
settings when using the FFP configuration scheme.
Table 2–5. Stratix II MSEL Pin Settings for FPP Configuration Schemes
Configuration Scheme
FPP when not using remote system upgrade or decompression and/or
design security feature
MSEL3 MSEL2 MSEL1 MSEL0
0
0
0
0
FPP when using remote system upgrade (1)
0
1
0
0
FPP with decompression and/or design security feature enabled (2)
1
0
1
1
FPP when using remote system upgrade and decompression and/or
design security feature (1), (2)
1
1
0
0
Notes to Table 2–5:
(1)
(2)
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrade in Stratix II devices, see the Chapter 8, Remote System Upgrades with
Stratix II Devices in Volume 2 of the Stratix II Device Handbook.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
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Configuring Stratix II Devices
FPP configuration of Stratix II devices can be performed using an
intelligent host, such as a MAX II device, or microprocessor, or an Altera
enhanced configuration device.
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using compression and an external host provides the
fastest method to configure Stratix II devices. In the FPP configuration
scheme, a MAX II device can be used as an intelligent host that controls
the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix II device. Configuration data can be stored
in RBF, HEX, or TTF format. When using the MAX II devices as an
intelligent host, a design that controls the configuration process, such as
fetching the data from flash memory and sending it to the device, must be
stored in the MAX II device.
1
If you are using the Stratix II decompression and/or design
security feature, the external host must be able to send a DCLK
frequency that is 4× the data rate.
The 4× DCLK signal does not require an additional pin and is sent on the
DCLK pin. The maximum DCLK frequency is 100 MHz, which results in a
maximum data rate of 200 Mbps. If you are not using the Stratix II
decompression nor are using the design security feature, the DCLK
frequency is the same as the data rate.
Figure 2–3 shows the configuration interface connections between the
Stratix II device and a MAX II device for single device configuration.
Figure 2–3. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Stratix II Device
MSEL[3..0]
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Note to Figure 2–3:
(1)
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July 2004
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device. VCC should be high enough to meet the VIH
specification of the I/O on the device and the external host.
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Fast Passive Parallel Configuration
Upon power-up, the Stratix II device goes through a Power-On Reset
(POR). The POR delay is dependent on the PORSEL pin setting; when
PORSEL is driven low, the POR time is approximately 100 ms, if PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS low, and tri-state all user I/O pins. Once
the device successfully exits POR, all user I/O pins continue to be tristated. If nIO_pullup is driven low during power-up and configuration,
the user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the DC & Switching
Characteristic chapter in the Stratix II Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low-to-high.
1
VCCINT, VCCIO and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data one byte at
a time on the DATA[7..0] pins.
1
The Stratix II device receives configuration data on its
DATA[7..0] pins and the clock is received on the DCLK pin.
Data is latched into the device on the rising edge of DCLK. If you
are using the Stratix II decompression and/or design security
feature, configuration data is latched on the rising edge of every
fourth DCLK cycle. After the configuration data is latched in, it is
processed during the following three DCLK cycles.
Data is continuously clocked into the target device until CONF_DONE goes
high. After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by an
external 10-kΩ pull-up resistor. A low-to-high transition on CONF_DONE
indicates configuration is complete and initialization of the device can
begin.
2–12
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July 2004
Configuring Stratix II Devices
In Stratix II devices, the initialization clock source is either the Stratix II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the Stratix II device will provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You can also synchronize initialization of multiple devices or to delay
initialization by using the CLKUSR option. The Enable user-supplied
start-up clock (CLKUSR) option can be turned on in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
Supplying a clock on CLKUSR will not affect the configuration process.
After all configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, the Stratix II devices require 299 clock cycles to initialize
properly and enter user mode. Stratix II devices support a CLKUSR fMAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme in the Quartus II software, as a default, these I/O pins are tristated in user mode and should be driven by the MAX II device. To
change this default option in the Quartus II software, select the DualPurpose Pins tab of the Device & Pin Options dialog box.
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Fast Passive Parallel Configuration
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
1
If you are using the Stratix II decompression and/or design
security feature and need to stop DCLK, it can only be stopped
three clock cycles after the last data byte was latched into the
Stratix II device.
By stopping DCLK, the configuration circuit allows enough clock cycles to
process the last byte of latched configuration data. When the clock
restarts, the MAX II device must provide data on the DATA[7..0] pins
prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options (dialog box) is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 40 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the MAX II device can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the MAX II
device must generate a low-to-high transition (with a low pulse of at least
40 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but the
CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 40 µs).
When the device is in user-mode, initiating a reconfiguration is done by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 40 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
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July 2004
Configuring Stratix II Devices
Figure 2–4 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the FPP configuration circuit for a single
device, except the Stratix II devices are cascaded for multi-device
configuration.
Figure 2–4. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
10 kΩ
10 kΩ
Stratix II Device 1
Stratix II Device 2
MSEL[3..0]
MSEL[3..0]
CONF_DONE
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
GND
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Note to Figure 2–4:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O standard on the device and the external
host.
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. The configuration signals may require buffering to ensure
signal integrity and prevent clock skew problems. Ensure that the DCLK
and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
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Fast Passive Parallel Configuration
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). After all nSTATUS pins are released and pulled high,
the MAX II device can try to reconfigure the chain without pulsing
nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 40 µs) on
nCONFIG to restart the configuration process.
In a multi-device FPP configuration chain, all Stratix II devices in the
chain must either enable or disable the decompression and/or design
security feature. You can not selectively enable the decompression
and/or design security feature for each device in the chain because of the
DATA and DCLK relationship. If the chain contains devices that do not
support design security, you should use a serial configuration scheme.
If a system has multiple devices that contain the same configuration data,
tie all device nCE inputs to GND, and leave nCEO pins floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices will start and complete configuration at the same time. Figure 2–5
shows multi-device FPP configuration when both Stratix II devices are
receiving the same configuration data.
Figure 2–5. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same
Data
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
10 kΩ
10 kΩ
Stratix II Device
Stratix II Device
MSEL[3..0]
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
MSEL[3..0]
CONF_DONE
nCEO
GND
GND
nSTATUS
nCE
N.C. (2)
nCEO
N.C. (2)
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Notes to Figure 2–5:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both Stratix II devices are left unconnected when configuring the same configuration data into
multiple devices.
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July 2004
Configuring Stratix II Devices
You can use a single configuration chain to configure Stratix II devices
with other Altera devices that support FPP configuration, such as Stratix
devices. To ensure that all devices in the chain complete configuration at
the same time or that an error flagged by one device initiates
reconfiguration in all devices, tie all of the device CONF_DONE and
nSTATUS pins together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera device Chains in the
Configuration Handbook.
FPP Configuration Timing
Figure 2–6 shows the timing waveform for FPP configuration when using
a MAX II device as an external host. This waveform shows the timing
when the decompression and the design security feature are not enabled.
Figure 2–6. FPP Configuration Timing Waveform
Notes (1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
(3) nSTATUS
tSTATUS
tCF2ST0
(4) CONF_DONE
tCF2CD
DCLK
tCL
tST2CK
tCH
1
2
3
4
1
2
3
4
(6)
1
(6)
Byte 2
(5)
4
tCLK
DATA[7..0]
Byte 0
tDSU
User I/O
tDH
Byte 1
(5)
User Mode
Byte n
tDH
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 2–6:
(1)
(2)
(3)
(4)
(5)
This timing waveform should be used when the decompression and design security feature are not used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the dualpurpose pin settings.
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Fast Passive Parallel Configuration
Table 2–6 defines the timing parameters for Stratix II devices for FPP
configuration when the decompression and the design security feature
are not enabled.
Table 2–6. FPP Timing Parameters for Stratix II Devices
Symbol
Parameter
tPOR
POR delay
Notes (1), (2)
Min
Max
Units
12
100
ms
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
tCFG
nCONFIG low pulse width
40
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge of DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
7
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK frequency
100
MHz
tR
Input rise time
40
ns
tF
Input fall time
tCD2UM
CONF_DONE high to user mode (4)
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
µs
40 (3)
µs
40 (3)
µs
40
ns
40
µs
4 × maximum
DCLK period
tC D 2 C U +(299 ×
CLKUSR period)
Notes to Table 2–6:
(1)
(2)
(3)
(4)
This information is preliminary.
These timing parameters should be used when the decompression and design security feature are not used.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
Figure 2–7 shows the timing waveform for FPP configuration when using
a MAX II device as an external host. This waveform shows the timing
when the decompression and/or the design security feature are enabled.
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July 2004
Configuring Stratix II Devices
Figure 2–7. FPP Configuration Timing Waveform With Decompression or Design Security Feature
Enabled
Notes (1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
(3) nSTATUS
tSTATUS
tCF2ST0
(4) CONF_DONE
tCF2CD
DCLK
tCL
tST2CK
tCH
1
2
3
4
1
2
3
4
(6)
1
(6)
Byte 2
(5)
4
tCLK
DATA[7..0]
Byte 0
tDSU
User I/O
tDH
Byte 1
(5)
User Mode
Byte n
tDH
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 2–7:
(1)
(2)
(3)
(4)
(5)
(6)
This timing waveform should be used when the decompression and/or design security feature are used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the dualpurpose pin settings.
If needed, DCLK can be paused by holding it low. When DCLK restarts, the external host must provide data on the
DATA[7..0] pins prior to sending the first DCLK rising edge.
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Fast Passive Parallel Configuration
Table 2–7 defines the timing parameters for Stratix II devices for FPP
configuration when the decompression and/or the design security
feature are enabled.
Table 2–7. FPP Timing Parameters for Stratix II Devices With Decompression or Design Security Feature
Enabled
Notes (1), (2)
Symbol
Parameter
tPOR
POR delay
Min
Max
Units
12
100
ms
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
tCFG
nCONFIG low pulse width
40
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
µs
40 (3)
µs
40 (3)
µs
tST2CK
nSTATUS high to first rising edge of DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
7
ns
tDH
Data hold time after rising edge on DCLK
30
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK frequency
100
MHz
tD ATA
Data rate
200
Mbps
tR
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (4)
40
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
4 × maximum
DCLK period
tC D 2 C U + (299 ×
CLKUSR period)
Notes to Table 2–7:
(1)
(2)
(3)
(4)
This information is preliminary.
These timing parameters should be used when the decompression and design security feature are used.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
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Configuring Stratix II Devices
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in the Configuration
Handbook.
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, a microprocessor can control the
transfer of configuration data from a storage device, such as flash
memory, to the target Stratix II device.
f
All information in “FPP Configuration Using a MAX II Device as an
External Host” on page 2–11 is also applicable when using a
microprocessor as an external host. Refer to that section for all
configuration and timing information.
FPP Configuration Using an Enhanced Configuration Device
In the FPP configuration scheme, an enhanced configuration device sends
a byte of configuration data every DCLK cycle to the Stratix II device.
Configuration data is stored in the configuration device.
1
When configuring your Stratix II device using FPP mode and an
enhanced configuration device, the enhanced configuration
device decompression feature is available while the Stratix II
decompression feature and design security feature are not.
Figure 2–8 shows the configuration interface connections between the
Stratix II device and the enhanced configuration device for single device
configuration.
1
f
Altera Corporation
July 2004
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the device.
For more information on the enhanced configuration device and flash
interface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8, &
EPC16) Data Sheet.
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Fast Passive Parallel Configuration
Figure 2–8. Single Device FPP Configuration Using an Enhanced Configuration
Device
VCC (1)
Stratix II Device
10 kΩ
(3) (3)
nCEO
GND
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
VCC (1)
N.C.
nCE
GND
Notes to Figure 2–8:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active. This means an external pull-up
resistor should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF
pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used, nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Enhanced Configuration Devices (EPC4, EPC8,
& EPC16) Data Sheet.
When using enhanced configuration devices, you can connect the
device’s nCONFIG pin to nINIT_CONF pin of the enhanced configuration
device, which allows the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If nINIT_CONF is not used, nCONFIG must be
pulled to VCC either directly or through a resistor. An internal pull-up
resistor on the nINIT_CONF pin is always active in the enhanced
configuration devices, which means an external pull-up resistor should
not be used if nCONFIG is tied to nINIT_CONF.
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting; when PORSEL is driven low, the
POR time is approximately 100 ms, if PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. The configuration device
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Configuring Stratix II Devices
also goes through a POR delay to allow the power supply to stabilize. The
POR time for enhanced configuration devices can be set to either 100 ms
or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin is
connected to GND, the POR delay is 100 ms. If the PORSEL pin is
connected to VCC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device's
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you use a 12-ms POR time
for the Stratix II device, and use a 100-ms POR time for the
enhanced configuration device.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Stratix II Device
Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT, VCCIO and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration devices have an optional internal pull-up resistor on the OE
pin. This option is available in the Quartus II software from the General
tab of the Device & Pin Options dialog box. If this internal pull-up
resistor is not used, an external 10-kΩ pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
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When nSTATUS is pulled high, the configuration device’s OE pin also
goes high and the configuration device clocks data out to the device using
its internal oscillator. The Stratix II device receives configuration data on
its DATA[7..0] pins and the clock is received on the DCLK pin. A byte of
data is latched into the device on each rising edge of DCLK.
After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin which is pulled high by a pullup resistor. Since CONF_DONE is tied to the configuration device's nCS
pin, the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration devices have an optional internal pull-up
resistor on the nCS pin. This option is available in the Quartus II software
from the General tab of the Device & Pin Options dialog box. If this
internal pull-up resistor is not used, an external 10-kΩ pull-up resistor on
the nCS-CONF_DONE line is required. A low to high transition on
CONF_DONE indicates configuration is complete and initialization of the
device can begin.
In Stratix II devices, the initialization clock source is either the Stratix II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the Stratix II device will provide itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices or to delay initialization
by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, the Stratix II devices require 299 clock cycles to initialize
properly and enter user mode. Stratix II devices support a CLKUSR fMAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. In user-mode, the user
I/O pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device will drive
DCLK low and DATA[7..0] high at the end of configuration.
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Configuring Stratix II Devices
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-restart configuration
after error option (available in the Quartus II software from the General
tab of the Device & Pin Options dialog box) is turned on, the device will
automatically initiate reconfiguration if an error occurs. The Stratix II
device will release its nSTATUS pin after a reset time-out period
(maximum of 40 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 40 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the device
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. In this case, the configuration device pulls its OE pin
low, which in turn drives the target device’s nSTATUS pin low. If the
Auto-restart configuration after error option is set in the software, the
target device resets and then releases its nSTATUS pin after a reset timeout period (maximum of 40 µs). When nSTATUS returns to a logic high
level, the configuration device will try to reconfigure the device.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully.
Therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, you should use the CLKUSR option to synchronize
the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain will
initialize together if their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, ensure
CLKUSR continues toggling during the time nSTATUS is low
(maximum of 40 µs).
When the device is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
40 µs. When nCONFIG is pulled low, the device also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE is
pulled low, this will activate the configuration device as it will see its nCS
pin drive low. Once nCONFIG returns to a logic high level and nSTATUS
is released by the device, reconfiguration begins.
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Fast Passive Parallel Configuration
Figure 2–9 shows how to configure multiple Stratix II devices with an
enhanced configuration device. This circuit is similar to the configuration
device circuit for a single device, except the Stratix II devices are cascaded
for multi-device configuration.
Figure 2–9. Multi-Device FPP Configuration Using an Enhanced Configuration Device
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Stratix II Device 2
N.C.
nCEO
MSEL[3..0]
DATA[7..0]
DATA[7..0]
OE (3)
nCS (3)
nSTATUS
GND
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
DCLK
DCLK
DATA[7..0]
nSTATUS
GND
Enhanced
Configuration Device
Stratix II Device 1
DCLK
MSEL[3..0]
nCEO
10 kΩ
nINIT_CONF (2)
nCE
GND
Notes to Figure 2–9:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-up resistors on configuration device option when generating programming files.
1
Enhanced configuration devices cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device’s POF from each project’s SOF. You can combine
multiple SOFs using the Convert Programming Files window in the
Quartus II software.
f
For more information on how to create configuration files for multidevice configuration chains, see Software Settings in Volume 2 of the
Configuration Handbook.
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
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Configuring Stratix II Devices
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA[7..0], and CONF_DONE) are connected to every device in the
chain. Pay special attention to the configuration signals because they may
require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all devices, which causes them to enter a reset
state. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
devices will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the Autorestart configuration after error option is turned off, the external system
must monitor nSTATUS for errors and then pulse nCONFIG low for at
least 40 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
Your system may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices will start and complete configuration at the same time.
Figure 2–10 shows multi-device FPP configuration when both Stratix II
devices are receiving the same configuration data.
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Fast Passive Parallel Configuration
Figure 2–10. Multiple-Device FPP Configuration Using an Enhanced Configuration Device When Both
devices Receive the Same Data
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Stratix II Device
(4) N.C.
nCEO
DCLK
DCLK
DATA[7..0]
MSEL[3..0]
nSTATUS
GND
Enhanced
Configuration Device
Stratix II Device
DCLK
MSEL[3..0]
DATA[7..0]
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
(4) N.C.
nCE
GND
DATA[7..0]
OE (3)
nSTATUS
GND
nCEO
10 kΩ
nCS (3)
nINIT_CONF (2)
nCE
GND
Notes to Figure 2–10:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single enhanced configuration chain to configure multiple
Stratix II devices with other Altera devices that support FPP
configuration, such as Stratix and Stratix GX devices. To ensure that all
devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera device Chains in the
Configuration Handbook.
Figure 2–11 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
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Configuring Stratix II Devices
Figure 2–11. Stratix II FPP Configuration Using an Enhanced Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tCE
tLC
DCLK
DATA[7..0]
Driven High
byte
1
byte
2
byte
n
tOE
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
tCD2UM (1)
Note to Figure 2–11:
(1)
The initialization clock can come from the Stratix II internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in of the Configuration
Handbook.
Active Serial
Configuration
(Serial
Configuration
Devices)
f
In the AS configuration scheme, Stratix II devices are configured using a
serial configuration device. These configuration devices are low cost
devices with non-volatile memory that feature a simple four-pin interface
and a small form factor. These features make serial configuration devices
an ideal low-cost configuration solution.
For more information on serial configuration devices, see the Serial
Configuration Devices Data Sheet in the Configuration Handbook.
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Stratix II devices read
configuration data via the serial interface, decompress data if necessary,
and configure their SRAM cells. This scheme is referred to as the AS
configuration scheme because the device controls the configuration
interface. This scheme contrast the PS configuration scheme where the
configuration device controls the interface.
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Active Serial Configuration (Serial Configuration Devices)
1
The Stratix II decompression and design security feature are
fully available when configuring your Stratix II device using AS
mode.
Table 2–8 shows the MSEL pin settings when using the AS configuration
scheme.
Table 2–8. Stratix II MSEL Pin Settings for AS Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
Fast AS (40 MHz) (1)
1
0
0
0
Remote system upgrade fast AS (40 MHz)
(1)
1
0
0
1
AS (20 MHz) (1)
1
1
0
1
Remote system upgrade AS (20 MHz) (1)
1
1
1
0
Note to Table 2–8:
(1)
Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz clock; other
EPCS devices support a DCLK up to 20 MHz. See the Serial Configuration Devices
Data Sheet for more information.
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an activelow chip select (nCS). This four-pin interface connects to Stratix II device
pins, as shown in Figure 2–12.
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Configuring Stratix II Devices
Figure 2–12. Single Device AS Configuration
VCC (1)
VCC (1)
10 kΩ
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Stratix II FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
VCC
GND
DATA
DATA0
(3) MSEL3
DCLK
DCLK
(3) MSEL2
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(2)
N.C.
GND
Notes to Figure 2–12:
(1)
(2)
(3)
Connect the pull-up resistors to a 3.3-V supply.
Stratix II devices use the ASDO to ASDI path to control the configuration device.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. See Table 2–8 for
more details.
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS and CONF_DONE low, and tri-state all user I/O pins. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
beforeand during configuration can be found in the Operating Conditions
table in the Stratix II Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
After POR, the Stratix II device releases nSTATUS, which is pulled high
by an external 10-kΩ pull-up resistor, and enters configuration mode.
1
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July 2004
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
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The serial clock (DCLK) generated by the Stratix II device controls the
entire configuration cycle and provides the timing for the serial interface.
Stratix II devices use an internal oscillator to generate DCLK. Using the
MSEL[] pins, you can select to use either a 40- or 20-MHz oscillator.
1
Only the EPCS16 and EPCS64 devices support a DCLK up to
40-MHz clock; other EPCS devices support a DCLK up to 20MHz. See the Serial Configuration Devices Data Sheet for more
information.
Table 2–9 shows the active serial DCLK output frequencies.
Table 2–9. Active Serial DCLK Output Frequency
Oscillator
Minimum
Typical
Note (1)
Maximum
Units
40 MHz (2)
20
26
40
MHz
20 MHz
10
13
20
MHz
Notes to Table 2–9:
(1)
(2)
These values are preliminary.
Only the EPCS16 and EPCS64 devices support a DCLK up to 40-MHz clock; other
EPCS devices support a DCLK up to 20-MHz. See the Serial Configuration Devices
Data Sheet for more information.
The serial configuration device latches input/control signals on the rising
edge of DCLK and drives out configuration data on the falling edge.
Stratix II devices drive out control signals on the falling edge of DCLK and
latch configuration data on the rising edge of DCLK.
In configuration mode, the Stratix II device enables the serial
configuration device by driving its nCSO output pin low, which connects
to the chip select (nCS) pin of the configuration device. The Stratix II
device uses the serial clock (DCLK) and serial data output (ASDO) pins to
send operation commands and/or read address signals to the serial
configuration device. The configuration device provides data on its serial
data output (DATA) pin, which connects to the DATA0 input of the
Stratix II device.
After all configuration bits are received by the Stratix II device, it releases
the open-drain CONF_DONE pin, which is pulled high by an external
10-kΩ resistor. Initialization begins only after the CONF_DONE signal
reaches a logic high level. All AS configuration pins, DATA0, DCLK, nCSO,
and ASDO, have weak internal pull-up resistors, which are always active.
Therefore, after configuration these pins will be driven high.
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Configuring Stratix II Devices
In Stratix II devices, the initialization clock source is either the Stratix II
10-MHz (typical) internal oscillator (separate from the active serial
internal oscillator) or the optional CLKUSR pin. By default, the internal
oscillator is the clock source for initialization. If the internal oscillator is
used, the Stratix II device will provide itself with enough clock cycles for
proper initialization. You also have the flexibility to synchronize
initialization of multiple devices or to delay initialization by using the
CLKUSR option. The Enable user-supplied start-up clock (CLKUSR)
option can be turned on in the Quartus II software from the General tab
of the Device & Pin Options dialog box. When you Enable the
user supplied start-up clock option, the CLKUSR pin is the initialization
clock source. Supplying a clock on CLKUSR will not affect the
configuration process. After all configuration data has been accepted and
CONF_DONE goes high, CLKUSR will be enabled after 600 ns. After this
time period elapses, the Stratix II devices require 299 clock cycles to
initialize properly and enter user mode. Stratix II devices support a
CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. This low-to-high
transition signals that the device has entered user mode. When
initialization is complete, the device enters user mode. In user-mode, the
user I/O pins will no longer have weak pull-up resistors and will
function as assigned in your design.
If an error occurs during configuration, the Stratix II device asserts the
nSTATUS signal low indicating a data frame error, and the CONF_DONE
signal will stay low. If the Auto-restart configuration after error option
(available in the Quartus II software from the General tab of the Device
& Pin Options dialog box) is turned on, the Stratix II device resets the
configuration device by pulsing nCSO, releases nSTATUS after a reset
time-out period (about 40 µs), and retries configuration. If this option is
turned off, the system must monitor nSTATUS for errors and then pulse
nCONFIG low for at least 40 µs to restart configuration.
When the Stratix II device is in user mode, you can initiate
reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin
should be low for at least 40 µs. When nCONFIG is pulled low, the device
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also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Once nCONFIG returns to a logic high level and nSTATUS is released by
the Stratix II device, reconfiguration begins.
You can configure multiple Stratix II devices using a single serial
configuration device. You can cascade multiple Stratix II devices using
the chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in
the chain must have its nCE pin connected to ground. You must connect
its nCEO pin to the nCE pin of the next device in the chain. When the first
device captures all of its configuration data from the bit stream, it drives
the nCEO pin low, enabling the next device in the chain. You must leave
the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA0 pins of each device in the chain are
connected (see Figure 2–13).
This first Stratix II device in the chain is the configuration master and
controls configuration of the entire chain. You must connect its MSEL pins
to select the AS configuration scheme. The remaining Stratix II devices
are configuration slaves and you must connect their MSEL pins to select
the PS configuration scheme. Any other Altera device that supports PS
configuration can also be part of the chain as a configuration slave.
Figure 2–13 shows the pin connections for this setup.
Figure 2–13. Multi-Device AS Configuration
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Stratix II FPGA Slave
Stratix II FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCC
(2) MSEL3
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
(2) MSEL2
DCLK
(2) MSEL1
(2) MSEL0
nCEO
N.C.
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
GND
Notes to Figure 2–13:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. See Table 2–8 for more details.
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Configuring Stratix II Devices
As shown in Figure 2–13, the nSTATUS and CONF_DONE pins on all target
devices are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the devices. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. But the subsequent devices in the chain keep this shared
CONF_DONE line low until they have received their configuration data.
When all target devices in the chain have received their configuration
data and have released CONF_DONE, the pull-up resistor drives a high
level on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is
driven low by the failing device. If you enable the Auto-restart
configuration after error option, reconfiguration of the entire chain begins
after a reset time-out period (a maximum of 40 µs). If the Auto-restart
configuration after error option is turned off, the external system must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to VCC.
1
While you can cascade Stratix II devices, serial configuration
devices cannot be cascaded or chained together.
If the configuration bit stream size exceeds the capacity of a serial
configuration device, you must select a larger configuration device
and/or enable the compression feature. When configuring multiple
devices, the size of the bitstream is the sum of the individual devices’
configuration bitstreams.
A system may have multiple devices that contain the same configuration
data. In active serial chains, this can be implemented by storing two
copies of the SOF in the serial configuration device. The first copy would
configure the master Stratix II device, and the second copy would
configure all remaining slave devices concurrently. All slave devices
must be the same density and package. The setup is similar to
Figure 2–13, where the master is setup in active serial mode and the slave
devices are setup in passive serial mode.
To configure four identical Stratix II devices with the same SOF, you
could setup the chain similar to the example shown in Figure 2–14. The
first device is the master device and its MSEL pins should be set to select
AS configuration. The other three slave devices are set up for concurrent
configuration and its MSEL pins should be set to select PS configuration.
The nCEO pin from the master device drives the nCE input pins on all
three slave devices, and the DATA and DCLK pins connect in parallel to all
four devices. During the first configuration cycle, the master device reads
its configuration data from the serial configuration device while holding
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nCEO high. After completing its configuration cycle, the master drives
nCE low and transmits the second copy of the configuration data to all
three slave devices, configuring them simultaneously.
Figure 2–14. Multi-Device AS Configuration When devices Receive the Same Data
Stratix II FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC (1)
VCC (1)
N.C.
VCC (1)
MSEL3
DATA0
10 kΩ
nCEO
10 kΩ
10 kΩ
VCC
MSEL2
DCLK
MSEL1
MSEL0
GND
Serial Configuration
Device
Stratix II FPGA Slave
Stratix II FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCC
(2) MSEL3
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC
MSEL2
DCLK
(2) MSEL1
N.C.
MSEL3
DATA0
(2) MSEL2
nCEO
MSEL1
(2) MSEL0
MSEL0
GND
GND
Stratix II FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C.
MSEL3
DATA0
VCC
MSEL2
DCLK
MSEL1
MSEL0
GND
Notes to Figure 2–14:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. See Table 2–8 for more details.
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to
transfer data from the serial configuration device to the Stratix II device.
This serial interface is clocked by the Stratix II DCLK output (generated
from an internal oscillator). As listed in Table 2–9, the DCLK minimum
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Configuring Stratix II Devices
frequency when choosing to use the 40-MHz oscillator is 20 MHz (50 ns).
Therefore, the maximum configuration time estimate for an EP2S15
device (5 MBits of uncompressed data) is:
RBF Size (minimum DCLK period / 1 bit per DCLK cycle) = estimated
maximum configuration time
5 Mbits × (50 ns / 1 bit) = 250 ms
To estimate the typical configuration time, use the typical DCLK period as
listed in Table 2–9. With a typical DCLK period of 38.46 ns, the typical
configuration time is 192 ms. Enabling compression reduces the amount
of configuration data that is transmitted to the Stratix II device, which
also reduces configuration time. On average, compression reduces
configuration time by 50%.
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based
devices. You can program these devices in-system using the USBBlaster™ or ByteBlaster™ II download cable. Alternatively, you can
program them using the Altera Programming Unit (APU), supported
third-party programmers, or a microprocessor with the SRunner
software driver.
You can perform in-system programming of serial configuration devices
via the AS programming interface. During in-system programming, the
download cable disables device access to the AS interface by driving the
nCE pin high. Stratix II devices are also held in reset by a low level on
nCONFIG. After programming is complete, the download cable releases
nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive
GND and VCC, respectively. Figure 2–15 shows the download cable
connections to the serial configuration device.
f
Altera Corporation
July 2004
For more information on the USB Blaster download cable, see the USBBlaster USB Port Download Cable Data Sheet. For more information on the
ByteBlaster II cable, see the ByteBlaster II Download Cable Data Sheet.
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Active Serial Configuration (Serial Configuration Devices)
Figure 2–15. In-System Programming of Serial Configuration Devices
VCC (1)
10 kΩ
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Stratix II FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
nCEO
N.C.
nCONFIG
nCE
10 kΩ
VCC
DATA
DATA0
(3) MSEL3
DCLK
DCLK
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(3) MSEL2
GND
Pin 1
VCC (2)
USB Blaster or ByteBlaser II
10-Pin Male Header
Notes to Figure 2–15:
(1)
(2)
(3)
Connect these pull-up resistors to 3.3-V supply.
Power up the ByteBlaster II cable's VCC with a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. See Table 2–8 for
more details.
You can program serial configuration devices by using the Quartus II
software with the Altera programming hardware (APU) and the
appropriate configuration device programming adapter. The EPCS1 and
EPCS4 devices are offered in an eight-pin small outline integrated circuit
(SOIC) package.
In production environments, serial configuration devices can be
programmed using multiple methods. Altera programming hardware or
other third-party programming hardware can be used to program blank
serial configuration devices before they are mounted onto printed circuit
boards (PCBs). Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system using C-based
software drivers provided by Altera.
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July 2004
Configuring Stratix II Devices
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming,
which can be easily customized to fit in different embedded systems.
SRunner is able to read a raw programming data (.rpd) file and write to
the serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming
time with the Quartus II software.
f
For more information about SRunner, see the SRunner: An Embedded
Solution for EPCS Programming White Paper and the source code on the
Altera web site at www.altera.com.
f
For more information on programming serial configuration devices, see
the Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet in the
Configuration Handbook.
Figure 2–16 shows the timing waveform for the AS configuration scheme
using a serial configuration device.
Figure 2–16. AS Configuration Timing
tPOR
nCONFIG
nSTATUS
CONF_DONE
nCSO
tCL
DCLK
tCH
tH
ASDO
Read Address
tSU
DATA0
bit N
bit N − 1
bit 1
bit 0
tCD2UM (1)
INIT_DONE
User Mode
User I/O
Note to Figure 2–16:
(1)
The initialization clock can come from the Stratix II internal oscillator or the CLKUSR pin.
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Passive Serial Configuration
Passive Serial
Configuration
PS configuration of Stratix II devices can be performed using an
intelligent host, such as a MAX II device or microprocessor with flash
memory, an Altera configuration device, or a download cable. In the PS
scheme, an external host (MAX II device, embedded processor,
configuration device, or host PC) controls configuration. Configuration
data is clocked into the target Stratix II devices via the DATA0 pin at each
rising edge of DCLK.
1
The Stratix II decompression and design security feature are
fully available when configuring your Stratix II device using PS
mode.
Table 2–10 shows the MSEL pin settings when using the PS configuration
scheme.
Table 2–10. Stratix II MSEL Pin Settings for PS Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
PS
0
0
1
0
PS when using Remote System Upgrade (1)
0
1
1
0
Note to Table 2–10:
(1)
This scheme requires that you drive the RUnLU pin to specify either remote
update or local update. For more information about remote system upgrade in
Stratix II devices, see Chapter 8, Remote System Upgrades with Stratix II Devices in
Volume 2 of the Stratix II Device Handbook.
PS Configuration Using a MAX II Device as an External Host
In the PS configuration scheme, a MAX II device can be used as an
intelligent host that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Stratix II device.
Configuration data can be stored in RBF, HEX, or TTF format. Figure 2–17
shows the configuration interface connections between the Stratix II
device and a MAX II device for single device configuration.
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July 2004
Configuring Stratix II Devices
Figure 2–17. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
(1) VCC
10 k Ω
VCC (1)
Stratix II Device
10 k Ω
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCEO
nCE
N.C.
MSEL3
GND
DATA0
MSEL2
nCONFIG
MSEL1
DCLK
VCC
MSEL0
GND
Note to Figure 2–17:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting; when PORSEL is driven low, the
POR time is approximately 100 ms, if PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. Once the device successfully
exits POR, all user I/O pins continue to be tri-stated. If nIO_pullup is
driven low during power-up and configuration, the user I/O pins and
dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven
high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Stratix II Device
Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the MAX II device must generate a low-to-high
transition on the nCONFIG pin.
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VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
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Passive Serial Configuration
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device should place the configuration data one
bit at a time on the DATA0 pin. The least significant bit (LSB) of each data
byte must be sent first. For example, if the RBF contains the byte sequence
02 1B EE 01 FA, the serial bitstream you should transmit to the device
is 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix II device receives configuration data on its DATA0 pin and the
clock is received on the DCLK pin. Data is latched into the device on the
rising edge of DCLK. Data is continuously clocked into the target device
until CONF_DONE goes high. After the device has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 10-kΩ pull-up resistor. A low-tohigh transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin.
In Stratix II devices, the initialization clock source is either the Stratix II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the Stratix II device will provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization by using the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data has been accepted and CONF_DONE
goes high, CLKUSR will be enabled after the time specified as tCD2CU. After
this time period elapses, the Stratix II devices require 299 clock cycles to
initialize properly and enter user mode. Stratix II devices support a
CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
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Configuring Stratix II Devices
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When the PS scheme is chosen in the
Quartus II software, as a default this I/O pin is tri-stated in user mode
and should be driven by the MAX II device. To change this default option
in the Quartus II software, select the Dual-Purpose Pins tab of the Device
& Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the Stratix II device releases nSTATUS after a reset time-out period
(maximum of 40 µs). After nSTATUS is released and pulled high by a pullup resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 40 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but CONF_DONE
or INIT_DONE have not gone high, the MAX II device must reconfigure
the target device.
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If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
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When the device is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 40 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Figure 2–18 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the PS configuration circuit for a single
device, except Stratix II devices are cascaded for multi-device
configuration.
Figure 2–18. Multi-Device PS Configuration Using an External Host
Memory
ADDR
DATA0
VCC (1)
10 k Ω
VCC (1)
10 k Ω
Stratix II Device 1
Stratix II Device 2
CONF_DONE
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
nSTATUS
nCE
nCEO
MSEL3
GND
DATA0
DATA0
VCC
MSEL2
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
GND
N.C.
MSEL3
VCC
MSEL2
nCEO
GND
Note to Figure 2–18:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
In multi-device PS configuration the first device’s nCE pin is connected to
GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device's nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and
DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
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Configuring Stratix II Devices
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). After all nSTATUS pins are released and pulled high,
the MAX II device can try to reconfigure the chain without needing to
pulse nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 40 µs) on
nCONFIG to restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. Configuration signals can
require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 2–19 shows
multi-device PS configuration when both Stratix II devices are receiving
the same configuration data.
Figure 2–19. Multiple-Device PS Configuration When Both devices Receive the Same Data
Memory
VCC (1)
ADDR
VCC (1)
DATA0
10 k Ω
10 k Ω
Stratix II Device
Stratix II Device
CONF_DONE
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
MSEL3
GND
DATA0
nSTATUS
nCE
N.C. (2)
VCC
MSEL2
nCEO
MSEL3
GND
DATA0
VCC
MSEL2
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
GND
N.C. (2)
GND
Notes to Figure 2–19:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
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Passive Serial Configuration
You can use a single configuration chain to configure Stratix II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera device Chains in the
Configuration Handbook.
PS Configuration Timing
Figure 2–20 shows the timing waveform for PS configuration when using
a MAX II device as an external host.
Figure 2–20. PS Configuration Timing Waveform
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA
Bit 0 Bit 1 Bit 2 Bit 3
Bit n
(4)
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 2–20:
(1)
(2)
(3)
(4)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[0] is available as a user I/O pin after configuration and the state of this pin depends on the dual-purpose pin
settings.
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Configuring Stratix II Devices
Table 2–11 defines the timing parameters for Stratix II devices for PS
configuration.
Table 2–11. PS Timing Parameters for Stratix II Devices
Note (1)
Symbol
Min
Max
Units
12
100
ms
800
ns
Parameter
tPOR
POR delay
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
40
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge of DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
7
ns
800
ns
µs
40 (2)
µs
40 (2)
µs
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
fMAX
tR
ns
DCLK frequency
100
MHz
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (3)
40
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
4 × maximum
DCLK period
tC D 2 C U + (299 ×
CLKUSR period)
Notes to Table 2–11:
(1)
(2)
(3)
This information is preliminary.
This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device.
f
Device configuration options and how to create configuration files are
discussed further in Software Settings in Volume 2 of the Configuration
Handbook.
An example PS design that uses a MAX II device as the external host for
configuration will be available when devices are available.
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Passive Serial Configuration
PS Configuration Using a Microprocessor
In the PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Stratix II device.
f
All information in the PS Configuration Using a MAX II Device as an
External Host section is also applicable when using a microprocessor as
an external host. Refer to that section for all configuration and timing
information.
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure Stratix II
devices using a serial configuration bitstream. Configuration data is
stored in the configuration device. Figure 2–21 shows the configuration
interface connections between the Stratix II device and a configuration
device.
1
f
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the device.
For more information on the enhanced configuration device and flash
interface pins (such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8, &
EPC16) Data Sheet.
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Configuring Stratix II Devices
Figure 2–21. Single Device PS Configuration Using an Enhanced Configuration Device
VCC (1)
VCC (1)
Stratix II Device
MSEL2
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
nCEO
MSEL0
nCE
MSEL3
VCC
10 kΩ
(3)
10 kΩ
(3)
Enhanced
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
N.C.
GND
GND
Notes to Figure 2–21:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
f
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data
Sheet or the Configuration Devices for SRAM-based LUT Devices Data Sheet.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the device can be connected to nINIT_CONF of the configuration
device, which allows the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If nINIT_CONF is not used or not available (e.g.,
on EPC1 devices), nCONFIG must be pulled to VCC either directly or
through a resistor. An internal pull-up resistor on the nINIT_CONF pin is
always active in enhanced configuration devices and EPC2 devices,
which means an external pull-up resistor should not be used if nCONFIG
is tied to nINIT_CONF.
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
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POR time for EPC2 and EPC1 devices is 200 ms (maximum). The POR
time for enhanced configuration devices can be set to either 100 ms or
2 ms, depending on its PORSEL pin setting. If the PORSEL pin is
connected to GND, the POR delay is 100 ms. If the PORSEL pin is
connected to VCC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you choose a POR time for
the Stratix II device of 12 ms, while selecting a POR time for the
enhanced configuration device of 100 ms.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the DC & Switching
Characteristics chapter in the Stratix II Device Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up resistor
on the OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pullup resistor is not used, an external 10-kΩ pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
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When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the device
using its internal oscillator. The Stratix II device receives configuration
data on its DATA0 pin and the clock is received on the DCLK pin. Data is
latched into the device on the rising edge of DCLK.
After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a pullup resistor. Since CONF_DONE is tied to the configuration device’s nCS
pin, the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration and EPC2 devices have an optional internal pullup resistor on the nCS pin. This option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If this internal pull-up resistor is not used, an external 10-kΩ pull-up
resistor on the nCS-CONF_DONE line is required. A low-to-high transition
on CONF_DONE indicates configuration is complete and initialization of
the device can begin.
In Stratix II devices, the initialization clock source is either the Stratix II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If you
are using internal oscillator, the Stratix II device will supply itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices or to delay initialization
by using the CLKUSR option. You can turn on the Enable user-supplied
start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, the Stratix II devices require 299 clock cycles to initialize
properly and enter user mode. Stratix II devices support a CLKUSR fMAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If you are using the INIT_DONE pin, it will be high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the device has entered user mode. In user-mode, the user I/O
pins will no longer have weak pull-up resistors and will function as
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assigned in your design. Enhanced configuration devices and EPC2
devices drive DCLK low and DATA0 high (EPC1 devices drive DCLK low
and tri-state DATA) at the end of configuration.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-restart configuration
after error option, available in the Quartus II software, from the General
tab of the Device & Pin Options dialog box is turned on, the device
automatically initiates reconfiguration if an error occurs. The Stratix II
device will release its nSTATUS pin after a reset time-out period
(maximum of 40 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 40 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the device
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. EPC2 devices wait for 16 DCLK cycles. In this case, the
configuration device pulls its OE pin low, driving the target device’s
nSTATUS pin low. If the Auto-restart configuration after error option is
set in the software, the target device resets and then releases its nSTATUS
pin after a reset time-out period (maximum of 40 µs). When nSTATUS
returns to a logic high level, the configuration device tries to reconfigure
the device.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully.
Therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If you are using the optional CLKUSR pin and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the device is in user-mode, pulling the nCONFIG pin low will
initiate a reconfiguration. The nCONFIG pin should be low for at least
40 µs. When nCONFIG is pulled low, the device also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE is
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Configuring Stratix II Devices
pulled low, this will activate the configuration device since it will see its
nCS pin drive low. Once nCONFIG returns to a logic high level and
nSTATUS is released by the device, reconfiguration begins.
Figure 2–22 shows how to configure multiple devices with an enhanced
configuration device. This circuit is similar to the configuration device
circuit for a single device, except Stratix II devices are cascaded for multidevice configuration.
Figure 2–22. Multi-Device PS Configuration Using an Enhanced Configuration Device
VCC (1)
10 kΩ
Stratix II Device 2
MSEL3
VCC
MSEL2
MSEL1
MSEL0
N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL2
MSEL1
MSEL0
nCEO
nCE
10 kΩ
(3)
Enhanced
Configuration
Device
Stratix II Device 1
MSEL3
VCC
(3)
VCC (1)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
nCE
GND
GND
GND
Notes to Figure 2–22:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
1
Enhanced configuration devices cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device's POF from each project’s SOF. You can combine
multiple SOFs using the Convert Programming Files window in the
Quartus II software.
f
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July 2004
For more information on how to create configuration files for multidevice configuration chains, see the Software Settings chapter of the
Configuration Handbook.
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In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, prompting the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all devices, causing them to enter a reset state.
This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
devices will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the Autorestart configuration after error option is turned off, the external system
must monitor nSTATUS for errors and then pulse nCONFIG low for at
least 40 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
The enhanced configuration devices also support parallel configuration
of up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode
allows enhanced configuration devices to concurrently configure devices
or a chain of devices. In addition, these devices do not have to be the same
device family or density as they can be any combination of Altera devices.
An individual enhanced configuration device DATA line is available for
each targeted device. Each DATA line can also feed a daisy chain of
devices. Figure 2–23 shows how to concurrently configure multiple
devices using an enhanced configuration device.
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Configuring Stratix II Devices
Figure 2–23. Concurrent PS Configuration of Multiple Devices Using an
Enhanced Configuration Device
(1) VCC
Stratix II Device 1
N.C.
(3)
(3)
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
OE (3)
nCEO
MSEL3
VCC
10 kΩ
VCC (1)
MSEL2
DATA1
DATA[2..6]
nCS (3)
GND
N.C.
VCC
Stratix II Device 2
nCEO
DCLK
DATA0
MSEL3
nSTATUS
MSEL2 CONF_DONE
nCONFIG
MSEL1
nCE
MSEL0
GND
nINIT_CONF (2)
DATA 7
GND
GND
Stratix II Device 8
N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
GND
Notes to Figure 2–23:
(1)
(2)
(3)
Altera Corporation
July 2004
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active, meaning an external pull-up resistor
should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF pin does
not need to be connected if its functionality is not used. If nINIT_CONF is not used,
nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
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The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 2–12 to
select the appropriate configuration mode for the fastest configuration
times.
Table 2–12. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 2–12:
(1)
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three devices, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the device. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus II
software. On the PCB, leave the DATA3 line from the enhanced
configuration device unconnected.
Alternatively, you can daisy chain two devices to one DATA line while the
other DATA lines drive one device each. For example, you could use the
2-bit PS mode to drive two devices with DATA Bit0 (two EP2S10 devices)
and the third device (EP2S20 device) with DATA Bit1. This 2-bit PS
configuration scheme requires less space in the configuration flash
memory, but can increase the total system configuration time.
A system may have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied
to GND, while nCEO pins are left floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to
every device in the chain. Configuration signals can require buffering to
ensure signal integrity and prevent clock skew problems. Ensure that the
DCLK and DATA lines are buffered for every fourth device. Devices must
be the same density and package. All devices will start and complete
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Configuring Stratix II Devices
configuration at the same time. Figure 2–24 shows multi-device PS
configuration when the Stratix II devices are receiving the same
configuration data.
Figure 2–24. Multiple-Device PS Configuration Using an Enhanced Configuration Device When devices
Receive the Same Data
(1) VCC
Stratix II Device 1
(4) N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
(4) N.C.
Stratix II Device 2
nCEO
MSEL3
VCC
MSEL2
MSEL1
MSEL0
10 KΩ
(3)
VCC (1)
(3)
10 KΩ
Enhanced
Configuration
Device
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
GND
Last Stratix II Device
(4) N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
GND
Notes to Figure 2–24:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
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You can cascade several EPC2 or EPC1 devices to configure multiple
Stratix II devices. The first configuration device in the chain is the master
configuration device, while the subsequent devices are the slave devices.
The master configuration device sends DCLK to the Stratix II devices and
to the slave configuration devices. The first EPC device’s nCS pin is
connected to the CONF_DONE pins of the devices, while its nCASC pin is
connected to nCS of the next configuration device in the chain. The last
device’s nCS input comes from the previous device, while its nCASC pin
is left floating. When all data from the first configuration device is sent, it
drives nCASC low, which in turn drives nCS on the next configuration
device. Since a configuration device requires less than one clock cycle to
activate a subsequent configuration device, the data stream is
uninterrupted.
1
Enhanced configuration devices cannot be cascaded.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONE going high
at the end of configuration, it resets the entire chain by pulling its OE pin
low. This low signal drives the OE pin low on the slave configuration
device(s) and drives nSTATUS low on all devices, causing them to enter a
reset state. This behavior is similar to the device detecting an error in the
configuration data.
Figure 2–25 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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Configuring Stratix II Devices
Figure 2–25. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (1)
VCC (1)
VCC (1)
(3) 10 kΩ
Stratix II Device 2
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
N.C.
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCEO
10 kΩ
MSEL3
MSEL2
MSEL1
MSEL0
nCEO
nCE
GND
10 kΩ (3)
EPC2/EPC1
Device 1
Stratix II Device 1
VCC
(2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
EPC2/EPC1
Device 2
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 2–25:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor should not be used on the nINIT_CONFnCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a
resistor.
The enhanced configuration devices' and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. External 10-kΩ pull-up resistors should be used. To turn off the internal pull-up resistors, check the
Disable nCS and OE pull-ups on configuration device option when generating programming files.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the device can be connected to nINIT_CONF of the configuration
device, allowing the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If you are not using nINIT_CONF, or if it isn’t
available(e.g. on EPC1 devices), nCONFIG must be pulled to VCC either
directly or through a resistor. An internal pull-up resistor on the
nINIT_CONF pin is always active in the enhanced configuration devices
and the EPC2 devices, which means that you shouldn’t be using an
external pull-up resistor if nCONFIG is tied to nINIT_CONF. If you are
using multiple EPC2 devices to configure a Stratix II device(s), only the
first EPC2 has its nINIT_CONF pin tied to the device’s nCONFIG pin.
You can use a single configuration chain to configure Stratix II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
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f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera device Chains
chapter in the Configuration Handbook.
Figure 2–26 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 2–26. Stratix II PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
tDSU
tCL
D0
D1
tDH
tOEZX
DATA
tCH
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
t CD2UM (1)
Note to Figure 2–26:
(1)
The initialization clock can come from the Stratix II internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet or the Configuration Devices for SRAMBased LUT Devices Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter of the Configuration
Handbook.
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB-Blaster™ universal serial bus (USB) port download cable,
MasterBlaster™ serial/USB communications cable, ByteBlaster™ II
parallel port download cable, and the ByteBlaster MV parallel port
download cable.
In PS configuration with a download cable, an intelligent host (such as a
PC) transfers data from a storage device to the device via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
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Configuring Stratix II Devices
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. Once the device successfully
exits POR, all user I/O pins continue to be tri-stated. If nIO_pullup is
driven low during power-up and configuration, the user I/O pins and
dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven
high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the DC & Switching
Characteristics chapter in the Stratix II Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high.
When using a download cable, setting the Auto-restart configuration
after error option does not affect the configuration cycle because you
must manually restart configuration in the Quartus II software when an
error occurs. Additionally, the Enable user-supplied start-up clock
(CLKUSR) option has no affect on the device initialization since this
option is disabled in the SOF when programming the device using the
Quartus II programmer and download cable. Therefore, if you turn on
the CLKUSR option, you do not need to provide a clock on CLKUSR when
you are configuring the device with the Quartus II programmer and a
download cable. Figure 2–27 shows PS configuration for Stratix II devices
using a USB Blaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV
cable.
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Figure 2–27. PS Configuration Using a USB Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV Cable
VCC (1)
VCC (1)
VCC (1)
10 kΩ
(2)
VCC (1)
10 kΩ
10 kΩ
Stratix II Device
MSEL3
VCC
MSEL2
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
MSEL1
10 kΩ
(2)
MSEL0
GND
nCE
GND
nCEO
N.C.
DCLK
DATA0
nCONFIG
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 2–27:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you
are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You can use a download cable to configure multiple Stratix II devices by
connecting each device’s nCEO pin to the subsequent device’s nCE pin.
The first device’s nCE pin is connected to GND while its nCEO pin is
connected to the nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
All other configuration pins, nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE are connected to every device in the chain. Because all
CONF_DONE pins are tied together, all devices in the chain initialize and
enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-restart
configuration after error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
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Configuring Stratix II Devices
Figure 2–28 shows how to configure multiple Stratix II devices with a
download cable.
Figure 2–28. Multi-Device PS Configuration using a USB Blaster, MasterBlaster, ByteBlaster II or
ByteBlasterMV Cable
VCC (1)
10 kΩ
VCC (1)
10 kΩ
MSEL3
MSEL2
MSEL1
MSEL0
(2)
VCC (1)
10 kΩ
Stratix II Device 1
VCC
GND
(2)
Pin 1
VCC
GND
VIO (3)
nCEO
nCE
10 kΩ
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
DCLK
GND
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
DATA0
nCONFIG
GND
Stratix II Device 2
VCC
MSEL3
MSEL2
MSEL1
MSEL0
CONF_DONE
nSTATUS
DCLK
GND
nCEO
N.C.
nCE
DATA0
nCONFIG
Notes to Figure 2–28:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
If you are using a download cable to configure device(s) on a board that
also has configuration devices, electrically isolate the configuration
device from the target device(s) and cable. One way of isolating the
configuration device is to add logic, such as a multiplexer, that can select
between the configuration device and the cable. The multiplexer chip
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allows bidirectional transfers on the nSTATUS and CONF_DONE signals.
Another option is to add switches to the five common signals (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) between the cable and the
configuration device. The last option is to remove the configuration
device from the board when configuring the device with the cable.
Figure 2–29 shows a combination of a configuration device and a
download cable to configure an device.
Figure 2–29. PS Configuration with a Download Cable & Configuration Device Circuit
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC
(4)
10 kΩ
Pin 1
CONF_DONE
nSTATUS
DCLK
VCC
GND
VIO (2)
GND
nCEO
nCE
GND
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
(5)
Stratix II Device
MSEL3
MSEL2
MSEL1
MSEL0
(5)
DATA0
nCONFIG
N.C.
(3)
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (5)
nCS (5)
(3)
nINIT_CONF (4)
Notes to Figure 2–29:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to a
Stratix II device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor should not be used on the nINIT_CONFnCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a
resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-up resistors on configuration device option when generating programming
files.
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Configuring Stratix II Devices
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following data sheets:
■
■
■
■
Passive Parallel
Asynchronous
Configuration
USB Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Passive parallel asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target Stratix II device.
Configuration data can be stored in RBF, HEX, or TTF format. The host
system outputs byte-wide data and the accompanying strobe signals to
the device. When using PPA, pull the DCLK pin high through a 10-kΩ
pull-up resistor to prevent unused configuration input pins from floating.
1
You cannot use the Stratix II decompression and design security
feature if you are configuring your Stratix II device using PPA
mode.
Table 2–13 shows the MSEL pin settings when using the PS configuration
scheme.
Table 2–13. Stratix II MSEL Pin Settings for PPA Configuration Schemes
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
PPA
0
0
0
1
Remote System Upgrade PPA (1)
0
1
0
1
Notes to Table 2–13:
(1)
This scheme requires that you drive the RUnLU pin to specify either remote
update or local update. For more information about remote system upgrade in
Stratix II devices, see the Chapter 8, Remote System Upgrades with Stratix II Devices
in Volume 2 of the Stratix II Device Handbook.
Figure 2–30 shows the configuration interface connections between the
device and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCS and CS. The address decoder allows the
microprocessor to select the Stratix II device by accessing a particular
address, which simplifies the configuration process. Hold the nCS and CS
pins active during configuration and initialization.
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Figure 2–30. Single Device PPA Configuration Using a Microprocessor
Address Decoder
ADDR
VCC (2)
Memory
10 kΩ
VCC (2)
ADDR DATA[7..0]
10 k Ω
Stratix II Device
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
nCEO
VCC
N.C.
GND
VCC (2)
10 kΩ
DCLK
Notes to Figure 2–30:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. VCC
should be high enough to meet the VIH specification of the I/O on the device and the external host.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if you are using only one chip-select input, the other must
be tied to the active state. For example, nCS can be tied to ground while
CS is toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 2–14.
Upon power-up, the Stratix II device goes through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. Once the device successfully
exits POR, all user I/O pins continue to be tri-stated. If nIO_pullup is
driven low during power-up and configuration, the user I/O pins and
dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven
high, the weak pull-up resistors are disabled.
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1
The value of the weak pull-up resistors on the I/O pins that are
on before and during configuration can be found in the DC &
Switching Characteristics chapter in the Stratix II Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the Stratix II device is processing
the byte of configuration data.
During the time RDYnBSY is low, the Stratix II device internally processes
the configuration data using its internal oscillator (typically 100 MHz).
When the device is ready for the next byte of configuration data, it will
drive RDYnBSY high. If the microprocessor senses a high signal when it
polls RDYnBSY, the microprocessor sends the next byte of configuration
data to the device.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Do not drive data onto the data bus while nRS is low because it will cause
contention on the DATA7 pin. If you are not using the nRS pin to monitor
configuration, it should be tied high.
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY (max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The tBUSY, tRDY2WS, and
tW2SB timing specifications are listed in Table 2–14.
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Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. After the device
receives all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In Stratix II devices, the initialization clock source is either the Stratix II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the Stratix II device will provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization by using the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data has been accepted and CONF_DONE
goes high, CLKUSR will be enabled after the time specified as tCD2CU. After
this time period elapses, the Stratix II devices require 299 clock cycles to
initialize properly and enter user mode. Stratix II devices support a
CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The microprocessor
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
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Configuring Stratix II Devices
To ensure DATA[7..0] is not left floating at the end of configuration, the
microprocessor must drive them either high or low, whichever is
convenient on your board. After configuration, the nCS, CS, nRS, nWS,
RDYnBSY, and DATA[7..0] pins can be used as user I/O pins. When
choosing the PPA scheme in the Quartus II software as a default, these
I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-restart
configuration after error option-available in the Quartus II software
from the General tab of the Device & Pin Options dialog box-is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 40 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the microprocessor can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the
microprocessor must generate a low-to-high transition (with a low pulse
of at least 40 µs) on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. To detect errors and determine
when programming completes, monitor the CONF_DONE pin with the
microprocessor. If the microprocessor sends all configuration data but
CONF_DONE or INIT_DONE has not gone high, the microprocessor must
reconfigure the target device.
1
If you are using the optional CLKUSR pin and nCONFIG is pulled
low to restart configuration during device initialization, ensure
CLKUSR continues toggling during the time nSTATUS is low
(maximum of 40 µs).
When the device is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should go
low for at least 40 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Figure 2–31 shows how to configure multiple Stratix II devices using a
microprocessor. This circuit is similar to the PPA configuration circuit for
a single device, except the devices are cascaded for multi-device
configuration.
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Figure 2–31. Multi-Device PPA Configuration Using a Microprocessor
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
Stratix II Device 1
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Microprocessor
Stratix II Device 2
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
VCC
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO
nCE
nWS
MSEL3
nRS
MSEL2
nCONFIG
MSEL1
RDYnBSY
MSEL0
N.C.
VCC
GND
Notes to Figure 2–31:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
In multi-device PPA configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent
to the microprocessor.
Each device’s RDYnBSY pin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSY pins can feed an AND gate and the output of the AND gate can
feed the microprocessor. For example, if you have two devices in a PPA
configuration chain, the second device’s RDYnBSY pin will be high during
the time that the first device is being configured. When the first device has
been successfully configured, it will drive nCEO low to activate the next
device in the chain and drive its RDYnBSY pin high. Therefore, since
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RDYnBSY signal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the AND gate.
The nRS signal can be used in multi-device PPA chain since the Stratix II
device will tri-state its DATA[7..0] pins before configuration and after
configuration before entering user-mode to avoid contention. Therefore,
only the device that is currently being configured will respond to the nRS
strobe by asserting DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRS and CONF_DONE) are connected to every device in the chain.
It is not necessary to tie nCS and CS together for every device in the chain,
as each device’s nCS and CS input can be driven by a separate source.
Configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DATA lines are buffered
for every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). After all nSTATUS pins are released and pulled high,
the microprocessor can try to reconfigure the chain without needing to
pulse nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 40 µs) on
nCONFIG to restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS, CS, nWS,
nRS and CONF_DONE) are connected to every device in the chain.
Configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DATA lines are buffered
for every fourth device. Devices must be the same density and package.
All devices will start and complete configuration at the same time.
Figure 2–32 shows multi-device PPA configuration when both devices
are receiving the same configuration data.
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Figure 2–32. Multiple-Device PPA Configuration Using a Microprocessor When Both devices Receive the
Same Data
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
Stratix II Device
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Stratix II Device
nCE
GND
DCLK
nCEO
Microprocessor
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
N.C. (3)
VCC
GND
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO
nCE
nWS
MSEL3
nRS
MSEL2
nCONFIG
MSEL1
RDYnBSY
MSEL0
N.C. (3)
VCC
GND
Notes to Figure 2–32:
(1)
(2)
(3)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure Stratix II devices
with other Altera devices that support PPA configuration, such as Stratix,
Mercury™, APEX™ 20K, ACEX® 1K, and FLEX® 10KE devices. To ensure
that all devices in the chain complete configuration at the same time or
that an error flagged by one device initiates reconfiguration in all devices,
all of the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera Device Chains
chapter in the Configuration Handbook.
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PPA Configuration Timing
Figure 2–33 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
Figure 2–33. Stratix II PPA Configuration Timing Waveform Using nWS
tCFG
Note (1)
tCF2ST1
nCONFIG
nSTATUS (2)
CONF_DONE (3)
Byte 0
DATA[7..0]
Byte 1
Byte n − 1
Byte n
(5)
tCSH
(5)
tDSU
(4) CS
tCF2WS
tCSSU
tDH
(5)
(4) nCS
tWSP
(5)
nWS
tRDY2WS
(5)
RDYnBSY
tWS2B
tSTATUS
tBUSY
tCF2ST0
tCF2CD
User I/Os
tCD2UM
High-Z
High-Z
User-Mode
INIT_DONE
Notes to Figure 2–33:
(1)
(2)
(3)
(4)
(5)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Figure 2–34 shows the timing waveform for the PPA configuration
scheme when using a strobed nRS and nWS signal.
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JTAG Configuration
Figure 2–34. Stratix II PPA Configuration Timing Waveform Using nRS & nWS
Note (1)
tCF2ST1
tCFG
nCONFIG
(2) nSTATUS
tSTATUS
tCF2SCD
(3) CONF_DONE
tCSSU
(5)
(4) nCS
tCSH
(5)
(4) CS
tDH
Byte 0
DATA[7..0]
Byte n
Byte 1
(5)
tDSU
(5)
nWS
tWSP
tRS2WS
tWS2RS
tCF2WS
nRS
(5)
tWS2RS
tRSD7
INIT_DONE
tRDY2WS
User I/O
High-Z
User-Mode
tWS2B
(5)
(6) DATA7/RDYnBSY
tCD2UM
tBUSY
Notes to Figure 2–34:
(1)
(2)
(3)
(4)
(5)
(6)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
DATA7 is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Table 2–14 defines the timing parameters for Stratix II devices for PPA
configuration.
f
JTAG
Configuration
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in the Configuration
Handbook.
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on PCBs with tight lead spacing. The BST architecture
can test pin connections without using physical test probes and capture
functional data while a device is operating normally. The JTAG circuitry
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Configuring Stratix II Devices
Table 2–14. PPA Timing Parameters for Stratix II Devices
Symbol
Parameter
Note (1)
Min
Max
Units
12
100
ms
800
ns
tPOR
POR delay
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
40
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge
on nWS
10
ns
tCSH
Chip select hold time after rising edge on
0
ns
µs
800
ns
µs
40 (2)
µs
40 (2)
µs
nWS
tCF2WS
nCONFIG high to first rising edge on nWS
40
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
15
ns
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
7
tRDY2WS
RDYnBSY rising edge to nWS rising edge
15
ns
tWS2RS
nWS rising edge to nRS falling edge
15
ns
tRS2WS
nRS rising edge to nWS rising edge
15
ns
tRSD7
nRS falling edge to DATA7 valid with
20
ns
45
ns
20
ns
RDYnBSY signal
tR
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (3)
40
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
40
ns
tC D 2 C U + (299 ×
CLKUSR period)
Notes to Table 2–14:
(1)
(2)
(3)
This information is preliminary.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
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JTAG Configuration
can also be used to shift configuration data into the device. The Quartus II
software automatically generates SOFs that can be used for JTAG
configuration with a download cable in the Quartus II software
programmer.
f
For more information on JTAG boundary-scan testing, see the following
documents:
■
■
Chapter 9, IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II
Devices in the Stratix II Device Handbook, Volume II
Jam Programming & Testing Language Specification
Stratix II devices are designed such that JTAG instructions have
precedence over any device configuration modes. Therefore, JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Stratix II devices during PS configuration, PS configuration will be
terminated and JTAG configuration will begin.
1
You cannot use the Stratix II decompression feature or the
design security feature if you are configuring your Stratix II
device when using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI, TMS, and TRST pins have weak
internal pull-up resistors (typically 25 kΩ). The TDO output pin and all
JTAG input pins are powered by the 3.3-V VCCPD pin. All user I/O pins
are tri-stated during JTAG configuration. Table 2–15 explains each JTAG
pin’s function.
1
The TDO output is powered by the VCCPD power supply. Since
the VCCPD is 3.3 V, the TDO pin drives out 3.3 V.
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV download cable. Configuring devices through a cable is
similar to programming devices in-system, except the TRST pin should
be connected to VCC. This ensures that the TAP controller is not reset.
Figure 2–35 shows JTAG configuration of a single Stratix II device.
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Configuring Stratix II Devices
Table 2–15. Dedicated JTAG Pins
Pin Name
Pin Type
Description
TDI
Test data input
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to VCC.
TDO
Test data output
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by leaving this pin unconnected.
TMS
Test mode select Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS
is evaluated on the rising edge of TCK. If the JTAG interface is not required on
the board, the JTAG circuitry can be disabled by connecting this pin to VC C .
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to GND.
TRST
Test reset input
(optional)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to IEEE Std. 1149.1. If the JTAG interface is not
required on the board, the JTAG circuitry can be disabled by connecting this pin
to GND.
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July 2004
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JTAG Configuration
Figure 2–35. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
10 kΩ
VCC (1)
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Stratix II Device
10 kΩ
nCE (4)
GND N.C.
(2)
(2)
(2)
TCK
TDO
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DCLK
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
VCC
TRST
Pin 1
VCC
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 2–35:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL[3..0] pins should be connected to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL[3..0] to ground. Pull DCLK either high or low,
whichever is convenient on your board.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in bypass mode. In bypass mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONE through the JTAG port. When Quartus II generates a (.jam)
file for a multi-device chain, it contains instructions so that all the devices
in the chain will be initialized at the same time. If CONF_DONE is not high,
the Quartus II software indicates that configuration has failed. If
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Configuring Stratix II Devices
CONF_DONE is high, the software indicates that configuration was
successful. After the configuration bit stream is transmitted serially via
the JTAG TDI port, the TCK port is clocked an additional 299 cycles to
perform device initialization.
Stratix II devices have dedicated JTAG pins that always function as JTAG
pins. Not only can you perform JTAG testing on Stratix II devices before
and after, but also during configuration. While other device families do
not support JTAG testing during configuration, Stratix II devices support
the bypass, idcode, and sample instructions during configuration
without interrupting configuration. All other JTAG instructions may only
be issued by first interrupting configuration and reprogramming I/O
pins using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Stratix II device or waiting for a configuration device to complete
configuration. Once configuration has been interrupted and JTAG testing
is complete, the part must be reconfigured via JTAG (PULSE_CONFIG
instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Stratix II devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins does not affect JTAG
operations (other than the usual boundary-scan operation).
When designing a board for JTAG configuration of Stratix II devices,
consider the dedicated configuration pins. Table 2–16 shows how these
pins should be connected during JTAG configuration.
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 2–36 shows multi-device JTAG configuration.
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JTAG Configuration
Table 2–16. Dedicated Configuration Pin Connections During JTAG
Configuration
Signal
Description
nCE
On all Stratix II devices in the chain, nCE should be driven low
by connecting it to ground, pulling it low via a resistor, or driving
it by some control circuitry. For devices that are also in multidevice FPP, AS, PS, or PPA configuration chains, the nCE pins
should be connected to GND during JTAG configuration or JTAG
configured in the same order as the configuration chain.
nCEO
On all Stratix II devices in the chain, nCEO can be left floating or
connected to the nCE of the previous device.
MSEL
These pins must not be left floating. These pins support
whichever non-JTAG configuration is used in production. If only
JTAG configuration is used, tie these pins to ground.
nCONFIG
Driven high by connecting to VCC, pulling up via a resistor, or
driven high by some control circuitry.
nSTATUS
Pull to VC C via a 10-kΩ resistor. When configuring multiple
devices in the same JTAG chain, each nSTATUS pin should be
pulled up to VC C individually.
CONF_DONE Pull to VC C via a 10-kΩ resistor. When configuring multiple
devices in the same JTAG chain, each CONF_DONE pin should
be pulled up to VC C individually. CONF_DONE going high at the
end of JTAG configuration indicates successful configuration.
DCLK
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Should not be left floating. Drive low or high, whichever is more
convenient on your board.
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July 2004
Configuring Stratix II Devices
Figure 2–36. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
10 kΩ
(1) VCC
Pin 1
nSTATUS
nCONFIG
(2)
DCLK
10 kΩ
(2)
VCC
(3)
(1) VCC
10 kΩ
(1) VCC
10 kΩ
Stratix II Device
(2)
nSTATUS
nCONFIG
(2)
DCLK
(2)
MSEL[3..0]
CONF_DONE
(1) VCC
VIO
Stratix II Device
(2)
10 kΩ
VCC
(1) VCC
(1) VCC
TRST
TDI
TMS
VCC
TDO
TCK
10 kΩ
(1) VCC
10 kΩ
Stratix II Device
(2)
nSTATUS
nCONFIG
(2)
DCLK
nCE (4)
(2)
MSEL[3..0]
TRST
TDI
TMS
VCC
TDO
TCK
10 kΩ
CONF_DONE
CONF_DONE
MSEL[3..0]
nCE (4)
(1) VCC
nCE (4)
TRST
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 2–36:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The nCONFIG, MSEL[3..0] pins should be connected to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL[3..0] to ground. Pull DCLK either high or low,
whichever is convenient on your board.
Pin 6 of the header is a VI O reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device FPP, AS, PS and PPA configuration chains,
the first device’s nCE pin is connected to GND while its nCEO pin is
connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device
configuration chain, its nCEO pin drives low to activate the second
device’s nCE pin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, make
sure the nCE pins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the
configuration chain. As long as the devices are JTAG configured in the
same order as the multi-device configuration chain, the nCEO of the
previous device will drive nCE of the next device low when it has
successfully been JTAG configured.
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
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July 2004
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JTAG Configuration
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera device Chains
chapter in the Configuration Handbook.
Figure 2–37 shows JTAG configuration of a Stratix II device with a
microprocessor.
Figure 2–37. JTAG Configuration of a Single Device Using a Microprocessor
VCC (1)
VCC (1)
Memory
ADDR
Stratix II Device
DATA
VCC
Microprocessor
10 kΩ
10 kΩ
TRST
TDI
TCK
TMS
TDO
nSTATUS
CONF_DONE
DCLK
nCONFIG
MSEL[3..0]
nCEO
(2)
(2)
(2)
N.C.
(3) nCE
GND
Notes to Figure 2–37:
(1)
(2)
(3)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain. VCC should be high enough to meet the VIH
specification of the I/O on the device.
The nCONFIG, MSEL[3..0] pins should be connected to support a non-JTAG
configuration scheme. If only JTAG configuration is used, connect nCONFIG to
VCC, and MSEL[3..0] to ground. Pull DCLK either high or low, whichever is
convenient on your board.
nCE must be connected to GND or driven low for successful JTAG configuration.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
f
For more information on JTAG and Jam STAPL in embedded
environments, see AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web site
at www.altera.com
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Configuring Stratix II Devices
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration related pins on the Stratix II device. Table 2–17 describes
the dedicated configuration pins, which are required to be connected
properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 1 of 9)
User Mode
Configuration
Scheme
N/A
All
Pin Name
VC C P D
Pin Type
Power
Description
Dedicated power pin. This pin is used to power
the I/O pre-drivers and a 3.3-V/2.5-V buffer
available on the configuration input pins and
JTAG pins. VCCPD applies to all the JTAG pins
(TCK, TMS, TDI, TDO, and TRST) and the
configuration pins; nCONFIG, DCLK (when
used as an input), nIO_Pullup,
DATA[7..0], RUnLU, nCE, nCEO, nWS,
nRS, CS, nCS and CLKUSR.
This pin must be connected to 3.3-V. VCCPD
must ramp-up from 0-V to 3.3-V within 100 ms.
If VCCPD is not ramped up within this specified
time, your Stratix II device will not configure
successfully. If your system does not allow for
a VCCPD ramp-up time of 100 ms or less, you
must hold nCONFIG low until all power
supplies are stable.
VCCSEL
N/A
All
Input
Dedicated input that selects which input buffer
is used on the configuration input pins;
nCONFIG, DCLK (when used as an input),
RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR. The 3.3-V/2.5-V input buffer is
powered by VCCPD, while the 1.8-V/1.5-V input
buffer is powered by VCCIO.
The VCCSEL input buffer has an internal 5-kΩ
pull-down resistor that is always active. The
VCCSEL input buffer is powered by VCCPD and
must be hardwired to VCCPD or ground. A logic
high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects the
1.8-V/1.5-V input buffer, and a logic low
selects the 3.3-V/2.5-V input buffer. For more
information, see “VCCSEL Pin” section.
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July 2004
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Device Configuration Pins
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 2 of 9)
Pin Name
PORSEL
User Mode
Configuration
Scheme
N/A
All
Pin Type
Input
Description
Dedicated input which selects between a POR
time of 12 ms or 100 ms. A logic high (1.5 V,
1.8 V, 2.5 V, 3.3 V) selects a POR time of
about 12 ms and a logic low selects POR time
of about 100 ms.
The PORSEL input buffer is powered by
VC C I N T and has an internal 5-kΩ pull-down
resistor that is always active. The PORSEL pin
should be tied directly to VC C P D or GND.
nIO_PULLUP
N/A
All
Input
Dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins
and dual-purpose I/O pins (nCSO, nASDO,
DATA[7..0], nWS, nRS, RDYnBSY, nCS,
CS, RUnLU, PGM[], CLKUSR, INIT_DONE,
DEV_OE, DEV_CLR) are on or off before and
during configuration. A logic high (1.5 V, 1.8 V,
2.5 V, 3.3 V) turns off the weak internal pull-up
resistors, while a logic low turns them on.
The nIO_PULLUP pin has an internal 5-kΩ
pull-down resistor that is always active.
MSEL[3..0]
N/A
All
Input
The nIO-PULLUP input buffer is powered by
VC C P D and has an internal 5-kΩ pull-down
resistor that is always active. The
nIO-PULLUP can be tied directly to VC C P D or
use a 1-kΩ pull-up resistor or tied directly to
GND.
The MSEL[3..0] pins have internal 5-kΩ pulldown resistors that are always active.
4-bit configuration input that sets the Stratix II
device configuration scheme. See Table 2–1
for the appropriate connections.
These pins must be hard-wired to VC C P D or
GND.
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Configuring Stratix II Devices
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 3 of 9)
User Mode
Configuration
Scheme
N/A
All
Pin Name
nCONFIG
Pin Type
Input
Description
Configuration control input. Pulling this pin low
during user-mode will cause the device to lose
its configuration data, enter a reset state, tristate all I/O pins. Returning this pin to a logic
high level will initiate a reconfiguration.
If your configuration scheme uses an
enhanced configuration device or EPC2
device, nCONFIG can be tied directly to VC C
or to the configuration device’s nINIT_CONF
pin.
nSTATUS
N/A
All
Bidirectional
open-drain
The device drives nSTATUS low immediately
after power-up and releases it after the POR
time.
Status output. If an error occurs during
configuration, nSTATUS is pulled low by the
target device.
Status input. If an external source drives the
nSTATUS pin low during configuration or
initialization, the target device enters an error
state.
Driving nSTATUS low after configuration and
initialization does not affect the configured
device. If a configuration device is used,
driving nSTATUS low will cause the
configuration device to attempt to configure
the device, but since the device ignores
transitions on nSTATUS in user-mode, the
device does not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low.
The enhanced configuration devices’ and
EPC2 devices’ OE and nCS pins have optional
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-kΩ
pull-up resistors should not be used on these
pins. When using EPC2 devices, only external
10-kΩ pull-up resistors should be used.
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Device Configuration Pins
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 4 of 9)
Pin Name
CONF_DONE
User Mode
Configuration
Scheme
N/A
All
Pin Type
Bidirectional
open-drain
Description
Status output. The target device drives the
CONF_DONE pin low before and during
configuration. Once all configuration data is
received without error and the initialization
cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and
CONF_DONE goes high, the target device
initializes and enters user mode.
Driving CONF_DONE low after configuration
and initialization does not affect the configured
device.
The enhanced configuration devices’ and
EPC2 devices’ OE and nCS pins have optional
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-kΩ
pull-up resistors should not be used on these
pins. When using EPC2 devices, only external
10-kΩ pull-up resistors should be used.
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates
the device with a low signal to allow
configuration. The nCE pin must be held low
during configuration, initialization, and user
mode. In single device configuration, it should
be tied low. In multi-device configuration, nCE
of the first device is tied low while its nCEO pin
is connected to nCE of the next device in the
chain.
The nCE pin must also be held low for
successful JTAG programming of the device.
nCEO
N/A
All
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Configuration Handbook, Volume 1
Output
Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In multidevice configuration, this pin feeds the next
device’s nCE pin. The nCEO of the last device
in the chain is left floating.
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Configuring Stratix II Devices
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 5 of 9)
Pin Name
ASDO
User Mode
N/A in AS
mode I/O in
non-AS
mode
Configuration
Scheme
AS
Pin Type
Output
Description
Control signal from the Stratix II device to the
serial configuration device in AS mode used to
read out configuration data.
In AS mode, ASDO has an internal pull-up
resistor that is always active.
nCSO
N/A in AS
mode I/O in
non-AS
mode
AS
Output
Output control signal from the Stratix II device
to the serial configuration device in AS mode
that enables the configuration device.
In AS mode, nCSO has an internal pull-up
resistor that is always active.
DCLK
N/A
Synchronous Input (PS,
configuration FPP) Output
schemes (PS, (AS)
FPP, AS)
In PS and FPP configuration, DCLK is the
clock input used to clock data from an external
source into the target device. Data is latched
into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the
Stratix II device that provides timing for the
configuration interface. In AS mode, DCLK has
an internal pull-up resistor (typically 25 kΩ)
that is always active.
In PPA mode, DCLK should be tied high to VCC
to prevent this pin from floating.
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK will be driven low after configuration is
done. In schemes that use a control host,
DCLK should be driven either high or low,
whichever is more convenient. Toggling this
pin after configuration does not affect the
configured device.
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Device Configuration Pins
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 6 of 9)
Pin Name
DATA0
User Mode
I/O
Configuration
Scheme
PS, FPP,
PPA, AS
Pin Type
Input
Description
Data input. In serial configuration modes, bitwide configuration data is presented to the
target device on the DATA0 pin.
The VI H and VI L levels for this pin are
dependent on the VC C I O of the I/O bank that
this pin resides in.
In AS mode, DATA0 has an internal pull-up
resistor that is always active.
After configuration, DATA0 is available as a
user I/O pin and the state of this pin depends
on the Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
DATA[7..1]
I/O
Parallel
configuration
schemes
(FPP and
PPA)
Inputs
Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0].
The VI H and VI L levels for this pin are
dependent on the VC C I O of the I/O bank that
this pin resides in.
In serial configuration schemes, they function
as user I/O pins during configuration, which
means they are tri-stated.
After PPA or FPP configuration,
DATA[7..1] are available as user I/O pins
and the state of these pin depends on the
Dual-Purpose Pin settings.
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Configuring Stratix II Devices
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 7 of 9)
User Mode
Configuration
Scheme
I/O
PPA
Pin Name
DATA7
Pin Type
Bidirectional
Description
In the PPA configuration scheme, the DATA7
pin presents the RDYnBSY signal after the
nRS signal has been strobed low.
The VI H and VI L levels for this pin are
dependent on the VC C I O of the I/O bank that
this pin resides in.
In serial configuration schemes, it functions as
a user I/O pin during configuration, which
means it is tri-stated.
After PPA configuration, DATA7 is available
as a user I/O and the state of this pin depends
on the Dual-Purpose Pin settings.
nWS
I/O
PPA
Input
Write strobe input. A low-to-high transition
causes the device to latch a byte of data on the
DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O
pin during configuration, which means it is tristated.
After PPA configuration, nWS is available as a
user I/O pins and the state of this pin depends
on the Dual-Purpose Pin settings.
nRS
I/O
PPA
Input
Read strobe input. A low input directs the
device to drive the RDYnBSY signal on the
DATA7 pin.
If the nRS pin is not used in PPA mode, it
should be tied high. In non-PPA schemes, it
functions as a user I/O during configuration,
which means it is tri-stated.
After PPA configuration, nRS is available as a
user I/O pin and the state of this pin depends
on the Dual-Purpose Pin settings.
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Device Configuration Pins
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 8 of 9)
Pin Name
RDYnBSY
User Mode
Configuration
Scheme
I/O
PPA
Pin Type
Output
Description
Ready output. A high output indicates that the
target device is ready to accept another data
byte. A low output indicates that the target
device is busy and not ready to receive
another data byte.
In PPA configuration schemes, this pin will
drive out high after power-up, before
configuration and after configuration before
entering user-mode. In non-PPA schemes, it
functions as a user I/O pin during
configuration, which means it is tri-stated.
After PPA configuration, RDYnBSY is
available as a user I/O pin and the state of this
pin depends on the Dual-Purpose Pin
settings.
nCS/CS
I/O
PPA
Input
Chip-select inputs. A low on nCS and a high
on CS select the target device for
configuration. The nCS and CS pins must be
held active during configuration and
initialization.
During the PPA configuration mode, it is only
required to use either the nCS or CS pin.
Therefore, if only one chip-select input is used,
the other must be tied to the active state. For
example, nCS can be tied to ground while CS
is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O
pin during configuration, which means it is tristated.
After PPA configuration, nCS and CS are
available as user I/O pins and the state of
these pins depends on the Dual-Purpose Pin
settings.
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Configuring Stratix II Devices
Table 2–17. Dedicated Configuration Pins on the Stratix II Device (Part 9 of 9)
User Mode
Configuration
Scheme
N/A if using
Remote
System
Upgrade
I/O if not
Remote
System
Upgrade in
FPP, PS or
PPA
Pin Name
RUnLU
Pin Type
Input
Description
Input that selects between remote update and
local update. A logic high (1.5-V, 1.8-V, 2.5-V,
3.3-V) selects remote update and a logic low
selects local update.
When not using remote update or local update
configuration modes, this pin is available as
general-purpose user I/O pin.
When using remote system upgrade in AS
more, the RUnLU pin is available as a generalpurpose I/O pin.
PGM[2..0]
N/A if using
Remote
System
Upgrade
I/O if not
using
Remote
System
Upgrade in
FPP, PS or
PPA
Input
These output pins select one of eight pages in
the memory (either flash or enhanced
configuration device) when using a remote
system upgrade mode.
When not using remote update or local update
configuration modes, these pins are available
as general-purpose user I/O pins.
When using remote system upgrade in AS
more, the PGM[] pins are available as
general-purpose I/O pins.
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Device Configuration Pins
Table 2–18 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-up resistors.
Table 2–18. Optional Configuration Pins
Pin Name
CLKUSR
User Mode
N/A if option is on.
I/O if option is off.
INIT_DONE N/A if option is on.
I/O if option is off.
Pin Type
Input
Description
Optional user-supplied clock input synchronizes the
initialization of one or more devices. This pin is
enabled by turning on the Enable user-supplied
start-up clock (CLKUSR) option in the Quartus II
software.
Output open-drain Status pin can be used to indicate when the device
has initialized and is in user mode. When nCONFIG
is low and during the beginning of configuration, the
INIT_DONE pin is tri-stated and pulled high due to
an external 10-kΩ pull-up resistor. Once the option bit
to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is
complete, the INIT_DONE pin will be released and
pulled high and the device enters user mode. Thus,
the monitoring circuitry must be able to detect a lowto-high transition. This pin is enabled by turning on the
Enable INIT_DONE output option in the Quartus II
software.
DEV_OE
N/A if option is on.
I/O if option is off.
Input
Optional pin that allows the user to override all tristates on the device. When this pin is driven low, all
I/O pins are tri-stated; when this pin is driven high, all
I/O pins behave as programmed. This pin is enabled
by turning on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is on.
I/O if option is off.
Input
Optional pin that allows you to override all clears on
all device registers. When this pin is driven low, all
registers are cleared; when this pin is driven high, all
registers behave as programmed. This pin is enabled
by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.
Table 2–19 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. The TDI, TMS, and TRST have weak internal pull-up
resistors (typically 25 kΩ) while TCK has a weak internal pull-down
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Configuring Stratix II Devices
resistor. If you plan to use the SignalTap® embedded logic array analyzer,
you need to connect the JTAG pins of the Stratix II device to a JTAG
header on your board.
Table 2–19. Dedicated JTAG Pins
Pin Name User Mode Pin Type
TDI
N/A
Input
Description
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to VC C .
TDO
N/A
Output
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is
not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. Transitions within the state machine occur on
the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to VCC.
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting TCK to GND.
TRST
N/A
Input
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting the TRST pin to GND.
Conclusion
Altera Corporation
July 2004
Stratix II devices can be configured in a number of different schemes to fit
your system’s need. In addition, configuration bitstream encryption,
configuration data decompression, and remote system upgrade support
supplement the Stratix II configuration solution.
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Chapter 3. Configuring
Stratix & Stratix GX Devices
S52013-3.1
Introduction
You can configure Stratix® and Stratix GX devices using one of several
configuration schemes. All configuration schemes use either a
microprocessor, configuration device, or a download cable. See
Table 3–1.
Table 3–1. Stratix & Stratix GX Device Configuration Schemes
Configuration Scheme
Typical Use
Fast passive parallel (FPP)
Configuration with a parallel synchronous configuration device or microprocessor
interface where eight bits of configuration data are loaded on every clock cycle.
Passive serial (PS)
Configuration with a serial synchronous microprocessor interface or the
MasterBlasterTM communications cable, USB Blaster, ByteBlasterTM II, or
ByteBlasterMV parallel port download cable.
Passive parallel
asynchronous (PPA)
Configuration with a parallel asynchronous microprocessor interface. In this
scheme, the microprocessor treats the target device as memory.
Remote/local update FPP
Configuration using a NiosTM (16-bit ISA) and Nios® II (32-bit ISA) or other
embedded processor. Allows you to update the Stratix or Stratix GX device
configuration remotely using the FPP scheme to load data.
Remote/local update PS
Passive serial synchronous configuration using a Nios or other embedded
processor. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PS scheme to load data.
Remote/local update PPA
Passive parallel asynchronous configuration using a Nios or other embedded
processor. In this scheme, the Nios microprocessor treats the target device as
memory. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PPA scheme to load data.
Joint Test Action Group
(JTAG)
Configuration through the IEEE Std. 1149.1 JTAG pins. You can perform JTAG
configuration with either a download cable or an embedded device. Ability to use
SignalTap® II Embedded Logic Analyzer.
This chapter discusses how to configure one or more Stratix or Stratix GX
devices. It should be used together with the following documents:
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■
■
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■
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August 2004
MasterBlaster Serial/USB Communications Cable Data Sheet
USB Blaster USB Port Download Cable Development Tools Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheets
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
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Preliminary
Device Configuration Overview
■
f
Device
Configuration
Overview
Chapter 12, Remote System Configuration with Stratix & Stratix GX
Devices
For more information on setting device configuration options or
generating configuration files, see the Software Setting chapter in
Volume 2 of the Configuration Handbook.
During device operation, the FPGA stores configuration data in SRAM
cells. Because SRAM memory is volatile, you must load the SRAM cells
with the configuration data each time the device powers up. After
configuration, the device must initialize its registers and I/O pins. After
initialization, the device enters user mode. Figure 3–1 shows the state of
the device during the configuration, initialization, and user mode.
Figure 3–1. Stratix & Stratix GX Configuration Cycle
D(N – 1)
nCONFIG
nSTATUS
CONF_DONE (1)
(4)
DCLK
DATA High-Z
User I/O Pins (2)
D0
D1
D2
D3
DN
High-Z
High-Z
(5)
User I/O
INIT_DONE (3)
MODE
Configuration
Configuration
Initialization
User
Notes to Figure 3–1:
(1)
(2)
(3)
(4)
(5)
During initial power up and configuration, CONF_DONE is low. After configuration, CONF_DONE goes high. If the
device is reconfigured, CONF_DONE goes low after nCONFIG is driven low.
User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistor
on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform
the function assigned in the user’s design.
If the INIT_DONE pin is used, it will be high because of an external 10 kΩ resistor pull-up when nCONFIG is low
and during the beginning of configuration. Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go low.
DCLK should not be left floating. It should be driven high or low.
DATA0 should not be left floating. It should be driven high or low.
You can load the configuration data for the Stratix or Stratix GX device
using a passive configuration scheme. When using any passive
configuration scheme, the Stratix or Stratix GX device is incorporated into
a system with an intelligent host, such as a microprocessor, that controls
the configuration process. The host supplies configuration data from a
storage device (e.g., a hard disk, RAM, or other system memory). When
using passive configuration, you can change the target device’s
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Configuring Stratix & Stratix GX Devices
functionality while the system is in operation by reconfiguring the device.
You can also perform in-field upgrades by distributing a new
programming file to system users.
The following sections describe the MSEL[2..0], VCCSEL, PORSEL, and
nIO_PULLUP pins used in Stratix and Stratix GX device configuration.
MSEL[2..0] Pins
You can select a Stratix or Stratix GX device configuration scheme by
driving its MSEL2, MSEL1, and MSEL0 pins either high or low, as shown
in Table 3–2.
Table 3–2. Stratix & Stratix GX Device Configuration Schemes
Description
MSEL2
MSEL1
MSEL0
FPP configuration
0
0
0
PPA configuration
0
0
1
PS configuration
0
1
0
Remote/local update FPP (1)
1
0
0
Remote/local update PPA (1)
1
0
1
Remote/local update PS (1)
1
1
0
JTAG-based configuration (3)
(2)
(2)
(2)
Notes to Table 3–2:
(1)
(2)
(3)
These schemes require that you drive a secondary pin RUnLU to specify whether
to perform a remote update or local update.
Do not leave MSEL pins floating. Connect them to VC C I O or GND. These pins
support the non-JTAG configuration scheme used in production. If only JTAG
configuration is used you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means the MSEL pins are ignored.
The MSEL[] pins can be tied to VCCIO of the I/O bank they reside in or
ground.
VCCSEL Pins
You can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-,
or 1.5-V LVTTL I/O standard on configuration and JTAG input pins.
VCCSEL is a dedicated input on Stratix and Stratix GX devices that selects
between 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers for
dedicated configuration input pins. A logic low supports 3.3-V/2.5-V
signaling, and a logic high supports 1.8-V/1.5-V signaling. A logic high
can also support 3.3-V/2.5-V signaling. VCCSEL affects the configuration
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Device Configuration Overview
related I/O banks (3, 4, 7, and 8) where the following pins reside: TDI,
TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA,
CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or
3.3-V for a logic high level. There is an internal 2.5-kΩ pull-down resistor
on VCCSEL. Therefore, if you are using a pull-up resister to pull up this
signal, you need to use a 1-kΩ resistor.
VCCSEL also sets the power-on-reset (POR) trip point for all the
configuration related I/O banks (3, 4, 7, and 8), ensuring that these I/O
banks have powered up to the appropriate voltage levels before
configuration begins. Upon power-up, the FPGA does not release
nSTATUS until VCCINT and all of the VCCIOs of the configuration I/O
banks are above their POR trip points. If you set VCCSEL to ground (logic
low), this sets the POR trip point for all configuration I/O banks to a
voltage consistent with 3.3-V/2.5-V signaling. When VCCSEL = 0, the
POR trip point for these I/O banks may be as high as 1.8 V. If VCCIO of any
of the configuration banks is set to 1.8 or 1.5 V, the voltage supplied to this
I/O bank(s) may never reach the POR trip point, which will not allow the
FPGA to begin configuration.
1
If the VCCIO of I/O banks 3, 4, 7, or 8 is set to 1.5 or 1.8 V and the
configuration signals used require 3.3-V or 2.5-V signaling you
should set VCCSEL to VCC (logic high) in order to lower the POR
trip point to enable successful configuration.
Table 3–3 shows how you should set the VCCSEL depending on the
VCCIO setting of the configuration I/O banks and your configuration
input signaling voltages.
Table 3–3. VCCSEL Setting
VCCIO (banks 3,4,7,8)
Configuration Input
Signaling Voltage
VCCSEL
3.3-V/2.5-V
3.3-V/2.5-V
GND
1.8-V/1.5-V
3.3-V/2.5-V/1.8-V/1.5-V
VCC
3.3-V/2.5-V
1.8-V/1.5-V
Not Supported
The VCCSEL signal does not control any of the dual-purpose pins,
including the dual-purpose configuration pins, such as the DATA[7..0]
and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration,
these dual-purpose pins drive out voltage levels corresponding to the
VCCIO supply voltage that powers the I/O bank containing the pin. After
configuration, the dual-purpose pins inherit the I/O standards specified
in the design.
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Configuring Stratix & Stratix GX Devices
PORSEL Pins
PORSEL is a dedicated input pin used to select POR delay times of 2 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
VCC, the POR time is 2 ms. There is an internal 2.5-kΩ pull-down resistor
on VCCSEL. Therefore if you are using a pull-up resistor to pull up this
signal, you need to use a 1-kΩ resistor.
When using enhanced configuration devices to configure Stratix devices,
make sure that the PORSEL setting of the Stratix device is the same or
faster than the PORSEL setting of the enhanced configuration device. If
the FPGA is not powered up after the enhanced configuration device
exits POR, the CONF_DONE signal will be high since the pull-up resistor is
pulling this signal high. When the enhanced configuration device exits
POR, OE of the enhanced configuration device is released and pulled
high by a pull-up resistor. Since the enhanced configuration device sees
its nCS/CONF_DONE signal also high, it enters a test mode. Therefore, you
must ensure the FPGA powers up before the enhanced configuration
device exits POR.
For more margin, the 100-ms setting can be selected when using an
enhanced configuration device to allow the Stratix FPGA to power-up
before configuration is attempted (see Table 3–4).
Table 3–4. PORSEL Settings
PORSEL Settings
POR Time (ms)
GND
100
VCC
2
nIO_PULLUP Pins
The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all
user I/O pins to VCCIO before and during device configuration. If
nIO_PULLUP is connected to VCC during configuration, the weak pullups on all user I/O pins and all dual-purpose pins are disabled. If
connected to ground, the pull-ups are enabled during configuration. The
nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3-V for a logic level
high. There is an internal 2.5-kΩ pull-down resistor on VCCSEL.
Therefore, if you are using a pull-up resistor to pull up this signal, you
need to use a 1-kΩ resistor.
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Configuration File Size
TDO & nCEO Pins
TDO and nCEO pins drive out the same voltage levels as the VCCIO that
powers the I/O bank where the pin resides. You must select the VCCIO
supply for the bank containing TDO accordingly. For example, when
using the ByteBlasterMV cable, the VCCIO for the bank containing TDO
must be powered up at 3.3-V. The current strength for TDO is 12 mA.
Configuration
File Size
Tables 3–5 and 3–6 summarize the approximate configuration file size
required for each Stratix and Stratix GX device. To calculate the amount
of storage space required for multi-device configurations, add the file size
of each device together.
Table 3–5. Stratix Configuration File Sizes
Device
Raw Binary File (.rbf) Size (Bits)
EP1S10
3,534,640
EP1S20
5,904,832
EP1S25
7,894,144
EP1S30
10,379,368
EP1S40
12,389,632
EP1S60
17,543,968
EP1S80
23,834,032
Table 3–6. Stratix GX Configuration File Sizes
Device
Raw Binary File Size (Bits)
EP1SGX10C
3,579,928
EP1SGX10D
3,579,928
EP1SGX25C
7,951,248
EP1SGX25D
7,951,248
EP1SGX25F
7,951,248
EP1SGX40D
12,531,440
EP1SGX40G
12,531,440
You should only use the numbers in Tables 3–5 and 3–6 to estimate the
file size before design compilation. The exact file size may vary because
different Altera® Quartus® II software versions may add a slightly
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Configuring Stratix & Stratix GX Devices
different number of padding bits during programming. However, for any
specific version of the Quartus II software, any design targeted for the
same device has the same configuration file size.
Altera
Configuration
Devices
f
The Altera enhanced configuration devices (EPC16, EPC8, and EPC4
devices) support a single-device configuration solution for high-density
FPGAs and can be used in the FPP and PS configuration schemes. They
are
ISP-capable through its JTAG interface. The enhanced configuration
devices are divided into two major blocks, the controller and the flash
memory.
For information on enhanced configuration devices, see the Enhanced
Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet and the Using
Altera Enhanced Configuration Devices chapter in the Configuration
Handbook.
The EPC2 and EPC1 configuration devices provide configuration support
for the PS configuration scheme. The EPC2 device is ISP-capable through
its JTAG interface. The EPC2 and EPC1 can be cascaded to hold large
configuration files.
f
Configuration
Schemes
For more information on EPC2, EPC1, and EPC1441 configuration
devices, see the Configuration Devices for SRAM-Based LUT Devices Data
Sheet.
This section describes how to configure Stratix and Stratix GX devices
with the following configuration schemes:
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PS Configuration with Configuration Devices
PS Configuration with a Download Cable
PS Configuration with a Microprocessor
FPP Configuration
PPA Configuration
JTAG Programming & Configuration
JTAG Programming & Configuration of Multiple Devices
PS Configuration
PS configuration of Stratix and Stratix GX devices can be performed using
an intelligent host, such as a MAX® device, microprocessor with flash
memory, an Altera configuration device, or a download cable. In the PS
scheme, an external host (MAX device, embedded processor,
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Configuration Schemes
configuration device, or host PC) controls configuration. Configuration
data is clocked into the target Stratix devices via the DATA0 pin at each
rising edge of DCLK.
PS Configuration with Configuration Devices
The configuration device scheme uses an Altera configuration device to
supply data to the Stratix or Stratix GX device in a serial bitstream (see
Figure 3–3).
In the configuration device scheme, nCONFIG is usually tied to VCC
(when using EPC16, EPC8, EPC4, or EPC2 devices, nCONFIG may be
connected to nINIT_CONF). Upon device power-up, the target Stratix or
Stratix GX device senses the low-to-high transition on nCONFIG and
initiates configuration. The target device then drives the open-drain
CONF_DONE pin low, which in-turn drives the configuration device’s nCS
pin low. When exiting power-on reset (POR), both the target and
configuration device release the open-drain nSTATUS pin.
Before configuration begins, the configuration device goes through a
POR delay of up to 200 ms to allow the power supply to stabilize (power
the Stratix or Stratix GX device before or during the POR time of the
configuration device). This POR delay has a maximum of 200 ms for
EPC2 devices. For enhanced configuration devices, you can select
between 2 ms and 100 ms by connecting PORSEL pin to VCC or GND,
accordingly. During this time, the configuration device drives its OE pin
low. This low signal delays configuration because the OE pin is connected
to the target device’s nSTATUS pin. When the target and configuration
devices complete POR, they release nSTATUS, which is then pulled high
by a pull-up resistor.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. When all devices are ready, the
configuration device clocks data out serially to the target devices using an
internal oscillator.
After successful configuration, the Stratix FPGA starts initialization using
the 10-MHz internal oscillator as the reference clock. After initialization,
this internal oscillator is turned off. The CONF_DONE pin is released by the
target device and then pulled high by a pull-up resistor. When
initialization is complete, the FPGA enters user mode.
If an error occurs during configuration, the target device drives its
nSTATUS pin low, resetting itself internally and resetting the
configuration device. If the Auto-Restart Configuration on Frame Error
option—available in the Quartus II Global Device Options dialog box
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Configuring Stratix & Stratix GX Devices
(Assign menu)—is turned on, the device reconfigures automatically if an
error occurs. To find this option, choose Compiler Settings (Processing
menu), then click on the Chips & Devices tab.
If this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low to restart configuration. The external
system can pulse nCONFIG if it is under system control rather than tied to
VCC. When configuration is complete, the target device releases
CONF_DONE, which disables the configuration device by driving nCS
high. The configuration device drives DCLK low before and after
configuration.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the target
device has not configured successfully. In this case, the configuration
device pulses its OE pin low for a few microseconds, driving the target
device’s nSTATUS pin low. If the Auto-Restart Configuration on Frame
Error option is set in the software, the target device resets and then pulses
its nSTATUS pin low. When nSTATUS returns high, the configuration
device reconfigures the target device. When configuration is complete,
the configuration device drives DCLK low.
Do not pull CONF_DONE low to delay initialization. Instead, use the
Quartus II software’s Enable User-Supplied Start-Up Clock (CLKUSR)
option to synchronize the initialization of multiple devices that are not in
the same configuration chain. Devices in the same configuration chain
initialize together. When CONF_DONE is driven low after device
configuration, the configuration device recognizes that the target device
has not configured successfully.
Figure 3–2 shows how to configure one Stratix or Stratix GX device with
one configuration device.
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Configuration Schemes
Figure 3–2. Single Device Configuration Circuit
VCC (1)
10 kΩ
(2)
Stratix or Stratix GX Device
MSEL2
MSEL1
MSEL0
GND
nCEO
10 kΩ
(3)
VCC (1)
10 kΩ
(2)
Configuration
Device
DCLK
DATA
OE (2)
nCS (2)
nINIT_CONF (3)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC
VCC (1)
N.C.
nCE
GND
Notes to Figure 3–2:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The enhanced configuration devices and EPC2 devices have internal
programmable pull-ups on OE and nCS. You should only use the internal pull-ups
of the configuration device if the nSTATUS and CONF_DONE signals are pulled up
to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be
10 kΩ.
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If
nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. he
nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,
EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up
resistor on the nINIT_CONF pin.
Figure 3–3 shows how to configure multiple Stratix and Stratix GX
devices with multiple EPC2 or EPC1 configuration devices.
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August 2004
Configuring Stratix & Stratix GX Devices
Figure 3–3. Multi-Device Configuration Circuit
Note (1)
VCC (2) VCC (2) VCC (2)
10 kΩ 10 kΩ 10 kΩ
(3)
Stratix or Stratix GX Device 2
VCC
MSEL2
MSEL1
MSEL0
Stratix or Stratix GX Device 1
MSEL2
MSEL1
MSEL0
nCEO
nCE
nCEO
(3)
EPC1/EPC2
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (4)
GND
GND
N.C.
VCC
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
(4)
EPC1/EPC2
DCLK
DATA
nCS
OE
nINIT_CONF (4)
nCE
GND
Notes to Figure 3–3:
(1)
(2)
(3)
(4)
When performing multi-device active serial configuration, you must generate the configuration device programmer
object file (.pof) from each project’s SOF. You can combine multiple SOFs using the Quartus II software through the
Device & Pin Option dialog box. For more information on how to create configuration and programming files, see
the Software Settings chapter in Volume 2 of the Configuration Handbook.
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The enhanced configuration devices and EPC2 devices have internal programmable pull-ups on OE and nCS. You
should only use the internal pull-ups of the configuration device if the nSTATUS and CONF_DONE signals are pulled
up to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be 10 kΩ
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC through a resistor. The nINIT_CONF pin has an internal pull-up resistor that is always active
in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the
nINIT_CONF pin.
After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activates the second device’s
nCE pin, prompting the second device to begin configuration. Because all
device CONF_DONE pins are tied together, all devices initialize and enter
user mode at the same time.
In addition, all nSTATUS pins are tied together; thus, if any device
(including the configuration devices) detects an error, configuration stops
for the entire chain. Also, if the first configuration device does not detect
CONF_DONE going high at the end of configuration, it resets the chain by
pulsing its OE pin low for a few microseconds. This low pulse drives the
OE pin low on the second configuration device and drives nSTATUS low
on all Stratix and Stratix GX devices, causing them to enter an error state.
If the Auto-Restart Configuration on Frame Error option is turned on in
the software, the Stratix or Stratix GX device releases its nSTATUS pins
after a reset time-out period. When the nSTATUS pins are released and
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Configuration Schemes
pulled high, the configuration devices reconfigure the chain. If the AutoRestart Configuration on Frame Error option is not turned on, the Stratix
or Stratix GX devices drive nSTATUS low until they are reset with a low
pulse on nCONFIG.
You can also cascade several EPC2/EPC1 configuration devices to
configure multiple Stratix and Stratix GX devices. When all data from the
first configuration device is sent, it drives nCASC low, which in turn
drives nCS on the subsequent configuration device. Because a
configuration device requires less than one clock cycle to activate a
subsequent configuration device, the data stream is uninterrupted.
1
You cannot cascade enhanced (EPC16, EPC8, and EPC4)
configuration devices.
You can use a single configuration chain to configure multiple Stratix and
Stratix GX devices. In this scheme, the nCEO pin of the first device is
connected to the nCE pin of the second device in the chain. If there are
additional devices, connect the nCE pin of the next device to the nCEO pin
of the previous device. To configure properly, all of the device
CONF_DONE and nSTATUS pins must be tied together.
Figure 3–4 shows an example of configuring multiple Stratix and Stratix
GX devices using a configuration device.
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August 2004
Configuring Stratix & Stratix GX Devices
Figure 3–4. Configuring Multiple Stratix & Stratix GX Devices with A Single Configuration
Device
Note (1)
VCC (2)
VCC (2)
VCC (2)
10 kΩ
Stratix or Stratix GX Device 2
VCC
MSEL2
MSEL1
MSEL0
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
Configuration
Device (4)
Stratix or Stratix GX Device 1
MSEL2
MSEL1
MSEL0
10 kΩ
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE
nCS
nCASC
nINIT_CONF (5)
GND
GND
N.C.
VCC
(3)
nCEO
nCE
nCEO
nCE
GND
Notes to Figure 3–4:
(1)
(2)
(3)
(4)
(5)
When performing multi-device active serial configuration, you must generate the configuration device programmer
object file (.pof) from each project’s SOF. You can combine multiple SOFs using the Quartus II software through the
Device & Pin Option dialog box. For more information on how to create configuration and programming files, see
Software Settings in Volume 2 of the Configuration Handbook.
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The enhanced configuration devices and EPC2 devices have internal programmable pull-ups on OE and nCS. You
should only use the internal pull-ups of the configuration device if the nSTATUS and CONF_DONE signals are pulled
up to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be 10 kΩ.
EPC16, EPC8, and EPC4 configuration devices cannot be cascaded.
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC through a resistor. The nINIT_CONF pin has an internal pull-up resistor that is always active
in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the
nINIT_CONF pin.
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Configuration Schemes
Table 3–7 shows the status of the device DATA pins during and after
configuration.
Table 3–7. DATA Pin Status Before & After Configuration
Stratix or Stratix GX Device
Pins
During
After
DATA0 (1)
Used for configuration
DATA[7..1] (2)
Used in some configuration modes User defined
I/O Pins
Tri-state
User defined
User defined
Notes to Table 3–7:
(1)
(2)
The status shown is for configuration with a configuration device.
The function of these pins depends upon the settings specified in the Quartus II
software using the Device & Pin Option dialog box (see Software Settings in
Volume 2 of the Configuration Handbook and the Quartus II Help software for
more information).
PS Configuration with a Download Cable
In PS configuration with a download cable, an intelligent host transfers
data from a storage device to the Stratix or Stratix GX device through the
MasterBlaster, USB-Blaster, ByteBlaster II or ByteBlasterMV cable. To
initiate configuration in this scheme, the download cable generates a lowto-high transition on the nCONFIG pin. The programming hardware then
places the configuration data one bit at a time on the device’s DATA0 pin.
The data is clocked into the target device until CONF_DONE goes high.
When using programming hardware for the Stratix or Stratix GX device,
turning on the Auto-Restart Configuration on Frame Error option does
not affect the configuration cycle because the Quartus II software must
restart configuration when an error occurs. Additionally, the Enable
User-Supplied Start-Up Clock (CLKUSR) option has no affect on the
device initialization since this option is disabled in the SOF when
programming the FPGA using the Quartus II software programmer and
a download cable. Therefore, if you turn on the CLKUSR option, you do
not need to provide a clock on CLKUSR when you are configuring the
FPGA with the Quartus II programmer and a download cable. Figure 3–5
shows PS configuration for the Stratix or Stratix GX device using a
MasterBlaster, USB-Blaster, ByteBLaster II or ByteBlasterMV cable.
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August 2004
Configuring Stratix & Stratix GX Devices
Figure 3–5. PS Configuration Circuit with a Download Cable
VCC (1)
(2)
VCC (1)
10 kΩ
(2)
VCC
10 kΩ
MSEL2
VCC (1)
10 kΩ
Stratix or
Stratix GX Device
MSEL1
VCC (1)
10 kΩ
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
MSEL0
(2)
nCE
nCEO
Download Cable
10-Pin Male Header
(PS Mode)
N.C.
GND
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 3–5:
(1)
(2)
(3)
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. This pin is a no-connect pin for the ByteBlasterMV header.
You can use programming hardware to configure multiple Stratix and
Stratix GX devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. All other configuration pins are connected
to each device in the chain.
Because all CONF_DONE pins are tied together, all devices in the chain
initialize and enter user mode at the same time. In addition, because the
nSTATUS pins are tied together, the entire chain halts configuration if any
device detects an error. In this situation, the Quartus II software must
restart configuration; the Auto-Restart Configuration on Frame Error
option does not affect the configuration cycle.
Figure 3–6 shows how to configure multiple Stratix and Stratix GX
devices with a MasterBlaster or ByteBlasterMV cable.
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Configuration Schemes
Figure 3–6. Multi-Device PS Configuration with a Download Cable
VCC (1)
VCC
Stratix or
Stratix GX Device 1
VCC (1)
MSEL1
(2)
10 kΩ
CONF_DONE
nSTATUS
DCLK
MSEL0
10 kΩ
10 kΩ
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
VCC (1)
(2)
10 kΩ
Pin 1
VCC
MSEL2
VCC (1)
GND
VIO (3)
nCE
10 kΩ
GND
DATA0
nCONFIG
VCC
nCEO
GND
Stratix or
Stratix GX Device 2
MSEL0
MSEL1
CONF_DONE
nSTATUS
DCLK
MSEL2
GND
nCE
nCEO
N.C.
DATA0
nCONFIG
Notes to Figure 3–6:
(1)
(2)
(3)
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. Refer to the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value.
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration devices from the target device(s) and cable. One way to
isolate the configuration devices is to add logic, such as a multiplexer,
that can select between the configuration devices and the cable. The
multiplexer device should allow bidirectional transfers on the nSTATUS
and CONF_DONE signals. Another option is to add switches to the five
common signals (CONF_DONE, nSTATUS, DCLK, nCONFIG, and DATA0)
between the cable and the configuration devices. The last option is to
remove the configuration devices from the board when configuring with
the cable. Figure 3–7 shows a combination of a configuration device and
a download cable to configure a Stratix or Stratix GX device.
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Configuring Stratix & Stratix GX Devices
Figure 3–7. Configuring with a Combined PS & Configuration Device Scheme
VCC (1)
VCC (1)
VCC
10 kΩ
10 kΩ
(6)
(2)
10 kΩ
(6)
Stratix or Stratix GX Device
VCC (1)
10 kΩ
MSEL0
MSEL1
MSEL2
nCE
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
VCC (1)
(2)
CONF_DONE
nSTATUS
DCLK
10 kΩ
Pin 1
VCC
GND
VIO (3)
nCEO
N.C.
GND
DATA0
nCONFIG
(4)
(4)
(4)
GND
Configuration
Device
(4)
DCLK
DATA
OE (6)
nCS (6)
(4)
nINIT_CONF (5)
Notes to Figure 3–7:
(1)
(2)
(3)
(4)
(5)
(6)
You should connect the pull-up resistor to the same supply voltage as the configuration device.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the target
device’s VCCIO. This is a no-connect pin for the ByteBlasterMV header.
You should not attempt configuration with a download cable while a configuration device is connected to a Stratix
or Stratix GX device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device. Remove the download cable when configuring with a configuration device.
If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor.
If external pull-ups are used on CONF_DONE and nSTATUS pins, they should always be 10 kΩ resistors. You can use
the internal pull-ups of the configuration device only if the CONF_DONE and nSTATUS signals are pulled-up to 3.3 V
or 2.5 V (not 1.8 V or 1.5 V).
f
For more information on how to use the MasterBlaster or ByteBlasterMV
cables, see the following documents:
■
■
■
■
Altera Corporation
August 2004
USB-Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
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Configuration Schemes
PS Configuration with a Microprocessor
In PS configuration with a microprocessor, a microprocessor transfers
data from a storage device to the target Stratix or Stratix GX device. To
initiate configuration in this scheme, the microprocessor must generate a
low-to-high transition on the nCONFIG pin and the target device must
release nSTATUS. The microprocessor or programming hardware then
places the configuration data one bit at a time on the DATA0 pin of the
Stratix or Stratix GX device. The least significant bit (LSB) of each data
byte must be presented first. Data is clocked continuously into the target
device until CONF_DONE goes high.
After all configuration data is sent to the Stratix and Stratix GX device, the
CONF_DONE pin will go high to show successful configuration and the
start of initialization. Initialization, by default, uses an internal oscillator,
which runs at 10 MHz. After initialization, this internal oscillator is
turned off. If you are using the clkusr option, after all data is transferred
clkusr must be clocked an additional 136 times for the Stratix or Stratix
GX device to initialize properly. Driving DCLK to the device after
configuration is complete does not affect device operation.
Handshaking signals are not used in PS configuration modes. Therefore,
the configuration clock speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists. You can
pause configuration by halting DCLK for an indefinite amount of time.
If the target device detects an error during configuration, it drives its
nSTATUS pin low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on in the Quartus II software, the target device releases
nSTATUS after a reset time-out period. After nSTATUS is released, the
microprocessor can reconfigure the target device without needing to
pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
data and the initialization clock starts but CONF_DONE and INIT_DONE
have not gone high, it must reconfigure the target device. By default the
INIT_DONE output is disabled. You can enable the INIT_DONE output
by turning on Enable INIT_DONE output option in the Quartus II
software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for the maximum value of
tCD2UM (see Table 3–8) after the CONF_DONE signal goes high to ensure the
device has been initialized properly and that it has entered user mode.
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Configuring Stratix & Stratix GX Devices
During configuration and initialization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 40 µs).
Figure 3–8 shows the circuit for PS configuration with a microprocessor.
Figure 3–8. PS Configuration Circuit with Microprocessor
Memory
ADDR
DATA0
VCC
10 k Ω
VCC
VCC
Stratix Device
10 k Ω
MSEL2
CONF_DONE
nSTATUS
MSEL1
MSEL0
nCE
Microprocessor
GND
GND
nCEO
N.C.
DATA0
nCONFIG
DCLK
PS Configuration Timing
Figure 3–9 shows the PS configuration timing waveform for Stratix and
Stratix GX devices. Table 3–8 shows the PS timing parameters for Stratix
and Stratix GX devices.
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Configuration Schemes
Table 3–8. PS Timing Parameters for Stratix & Stratix GX Devices
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
tCF2ST1
nCONFIG high to nSTATUS high
40 (2)
µs
tCFG
nCONFIG low pulse width
40
tSTATUS
nSTATUS low pulse width
10
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
µs
40 (2)
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
7
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (1)
6
100
MHz
20
µs
Notes to Table 3–8:
(1)
(2)
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
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Configuring Stratix & Stratix GX Devices
Figure 3–9. PS Timing Waveform for Stratix & Stratix GX Devices
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
Bit 0 Bit 1 Bit 2 Bit 3
DATA
Bit n
(4)
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 3–9:
(1)
(2)
(3)
(4)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
FPP Configuration
Parallel configuration of Stratix and Stratix GX devices meets the
continuously increasing demand for faster configuration times. Stratix
and Stratix GX devices can receive byte-wide configuration data per clock
cycle, and guarantee a configuration time of less than 100 ms with a 100MHz configuration clock. Stratix and Stratix GX devices support
programming data bandwidth up to 800 megabits per second (Mbps) in
this mode. You can use parallel configuration with an EPC16, EPC8, or
EPC4 device, or a microprocessor.
This section discusses the following schemes for FPP configuration in
Stratix and Stratix GX devices:
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FPP Configuration Using an Enhanced Configuration Device
FPP Configuration Using a Microprocessor
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FPP Configuration Using an Enhanced Configuration Device
When using FPP with an enhanced configuration device, it supplies data
in a byte-wide fashion to the Stratix or Stratix GX device every DCLK
cycle. See Figure 3–10.
Figure 3–10. FPP Configuration Using Enhanced Configuration Devices
VCC (1) VCC (1)
10 kΩ
Stratix or
Stratix GX Device
10 kΩ
(2)
nCEO
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE (2)
nCS (2)
nINIT_CONF (3)
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL2
MSEL1
MSEL0
(2)
N.C.
nCE
GND
GND
Notes to Figure 3–10:
(1)
(2)
(3)
The pull-up resistors should be connected to the same supply voltage as the
configuration device.
The enhanced configuration devices and EPC2 devices have internal
programmable pull-ups on OE and nCS. You should only use the internal pull-ups
of the configuration device if the nSTATUS and CONF_DONE signals are pulled up
to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be
10 kΩ.
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If
nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. The
nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,
EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up
resistor on the nINIT_CONF pin.
In the enhanced configuration device scheme, nCONFIG is tied to
nINIT_CONF. On power up, the target Stratix or Stratix GX device senses
the low-to-high transition on nCONFIG and initiates configuration. The
target Stratix or Stratix GX device then drives the open-drain CONF_DONE
pin low, which in-turn drives the enhanced configuration device’s nCS
pin low.
Before configuration starts, there is a 2-ms POR delay if the PORSEL pin
is connected to VCC in the enhanced configuration device. If the PORSEL
pin is connected to ground, the POR delay is 100 ms. When each device
determines that its power is stable, it releases its nSTATUS or OE pin.
Because the enhanced configuration device’s OE pin is connected to the
target Stratix or Stratix GX device’s nSTATUS pin, configuration is
delayed until both the nSTATUS and OE pins are released by each device.
The nSTATUS and OE pins are pulled up by a resistor on their respective
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Configuring Stratix & Stratix GX Devices
devices once they are released. When configuring multiple devices,
connect the nSTATUS pins together to ensure configuration only happens
when all devices release their OE or nSTATUS pins. The enhanced
configuration device then clocks data out in parallel to the Stratix or
Stratix GX device using a 66-MHz internal oscillator, or drives it to the
Stratix or Stratix GX device through the EXTCLK pin.
If there is an error during configuration, the Stratix or Stratix GX device
drives the nSTATUS pin low, resetting itself internally and resetting the
enhanced configuration device. The Quartus II software provides an
Auto-restart configuration after error option that automatically initiates
the reconfiguration whenever an error occurs. See the Software Settings
chapter in Volume 2 of the Configuration Handbook for information on how
to turn this option on or off.
If this option is turned off, you must set monitor nSTATUS to check for
errors. To initiate reconfiguration, pulse nCONFIG low. The external
system can pulse nCONFIG if it is under system control rather than tied to
VCC. Therefore, nCONFIG must be connected to nINIT_CONF if you want
to reprogram the Stratix or Stratix GX device on the fly.
When configuration is complete, the Stratix or Stratix GX device releases
the CONF_DONE pin, which is then pulled up by a resistor. This action
disables the EPC16, EPC8, or EPC4 enhanced configuration device as nCS
is driven high. Initialization, by default, uses an internal oscillator, which
runs at 10 MHz. After initialization, this internal oscillator is turned off.
When initialization is complete, the Stratix or Stratix GX device enters
user mode. The enhanced configuration device drives DCLK low before
and after configuration.
If, after sending out all of its data, the enhanced configuration device does
not detect CONF_DONE going high, it recognizes that the Stratix or
Stratix GX device has not configured successfully. The enhanced
configuration device pulses its OE pin low for a few microseconds,
driving the nSTATUS pin on the Stratix or Stratix GX device low. If the
Auto-restart configuration after error option is on, the Stratix or Stratix
GX device resets and then pulses its nSTATUS low. When nSTATUS
returns high, reconfiguration is restarted (see Figure 3–11 on page 3–24).
Do not drive CONF_DONE low after device configuration to delay
initialization. Instead, use the Enable User-Supplied Start-Up Clock
(CLKUSR) option in the Device & Pin Options dialog box. You can use
this option to synchronize the initialization of multiple devices that are
not in the same configuration chain. Devices in the same configuration
chain initialize together.
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After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activates the second Stratix or
Stratix GX device’s nCE pin, prompting the second device to begin
configuration. Because CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time. Because nSTATUS pins
are tied together, configuration stops for the whole chain if any device
(including enhanced configuration devices) detects an error. Also, if the
enhanced configuration device does not detect a high on CONF_DONE at
the end of configuration, it pulses its OE low for a few microseconds to
reset the chain. The low OE pulse drives nSTATUS low on all Stratix and
Stratix GX devices, causing them to enter an error state. This state is
similar to a Stratix or Stratix GX device detecting an error.
If the Auto-restart configuration after error option is on, the Stratix and
Stratix GX devices release their nSTATUS pins after a reset time-out
period. When the nSTATUS pins are released and pulled high, the
configuration device reconfigures the chain. If the Auto-restart
configuration after error option is off, nSTATUS stays low until the
Stratix and Stratix GX devices are reset with a low pulse on nCONFIG.
Figure 3–11 shows the FPP configuration with a configuration device
timing waveform for Stratix and Stratix GX devices.
Figure 3–11. FPP Configuration with a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
Note (1)
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA[7..0]
tDSU
tCL
Byte0
Byte1
tCH
tDH
tOEZX
Byte2 Byte3
(2)
Byten
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(3)
Notes to Figure 3–11
(1)
(2)
(3)
For timing information, refer to the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet.
The configuration device drives DATA high after configuration.
Stratix and Stratix GX devices enter user mode 136 clock cycles after CONF_DONE goes high.
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Configuring Stratix & Stratix GX Devices
FPP Configuration Using a Microprocessor
When using a microprocessor for parallel configuration, the
microprocessor transfers data from a storage device to the Stratix or
Stratix GX device through configuration hardware. To initiate
configuration, the microprocessor needs to generate a low-to-high
transition on the nCONFIG pin and the Stratix or Stratix GX device must
release nSTATUS. The microprocessor then places the configuration data
to the DATA[7..0] pins of the Stratix or Stratix GX device. Data is
clocked continuously into the Stratix or Stratix GX device until
CONF_DONE goes high.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists. You can pause configuration by halting DCLK for an indefinite
amount of time.
After all configuration data is sent to the Stratix or Stratix GX device, the
CONF_DONE pin will go high to show successful configuration and the
start of initialization. Initialization, by default, uses an internal oscillator,
which runs at 10 MHz. After initialization, this internal oscillator is
turned off. If you are using the clkusr option, after all data is transferred
clkusr must be clocked an additional 136 times for the Stratix or Stratix
GX device to initialize properly. Driving DCLK to the device after
configuration is complete does not affect device operation. By default, the
INIT_DONE output is disabled. You can enable the INIT_DONE output
by turning on the Enable INIT_DONE output option in the Quartus II
software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for maximum value of
tCD2UM (see Table 3–9) after the CONF_DONE signal goes high to ensure the
device has been initialized properly and that it has entered user mode.
During configuration and initialization and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 40 µs).
If the Stratix or Stratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The pin on the
microprocessor connected to nSTATUS must be an input. The
microprocessor can then pulse nCONFIG low to restart the configuration
error. With the Auto-restart configuration after error option on, the
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Stratix or Stratix GX device releases nSTATUS after a reset time-out
period. After nSTATUS is released, the microprocessor can reconfigure
the Stratix or Stratix GX device without pulsing nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
the data and the initialization clock starts but CONF_DONE and
INIT_DONE have not gone high, it must reconfigure the Stratix or
Stratix GX device. After waiting the specified 136 DCLK cycles, the
microprocessor should restart configuration by pulsing nCONFIG low.
Figure 3–12 shows the circuit for Stratix and Stratix GX parallel
configuration using a microprocessor.
Figure 3–12. Parallel Configuration Using a Microprocessor
VCC (1)
VCC (1)
Memory
ADDR DATA[7..0]
10 kΩ
10 kΩ
Stratix Device
MSEL2
CONF_DONE
nSTATUS
MSEL1
MSEL0
nCE
Microprocessor
GND
nCEO
GND
N.C.
DATA[7..0]
nCONFIG
DCLK
Notes to Figure 3–12:
(1)
The pull-up resistors should be connected to any VCC that meets the Stratix highlevel input voltage (VIH) specification.
For multi-device parallel configuration with a microprocessor, the nCEO
pin of the first Stratix or Stratix GX device is cascaded to the second
device’s nCE pin. The second device in the chain begins configuration
within one clock cycle; therefore, the transfer of data destinations is
transparent to the microprocessor. Because the CONF_DONE pins of the
devices are connected together, all devices initialize and enter user mode
at the same time.
Because the nSTATUS pins are also tied together, if any of the devices
detects an error, the entire chain halts configuration and drives nSTATUS
low. The microprocessor can then pulse nCONFIG low to restart
configuration. If the Auto-restart configuration after error option is on,
the Stratix and Stratix GX devices release nSTATUS after a reset time-out
period. The microprocessor can then reconfigure the devices once
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Configuring Stratix & Stratix GX Devices
nSTATUS is released. Figure 3–13 shows multi-device configuration
using a microprocessor. Figure 3–14 shows multi-device configuration
when both Stratix and Stratix GX devices are receiving the same data. In
this case, the microprocessor sends the data to both devices
simultaneously, and the devices configure simultaneously.
Figure 3–13. Parallel Data Transfer in Serial Configuration with a Microprocessor
VCC (1)
10 kΩ
Memory
ADDR DATA[7..0]
VCC (1)
Stratix Device
10 kΩ
Stratix Device
MSEL2
MSEL2
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
MSEL1
MSEL0
CONF_DONE
nSTATUS
nCEO
MSEL1
MSEL0
nCE
GND
nCEO
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
N.C.
Notes to Figure 3–13:
(1)
You should connect the pull-up resistors to any VCC that meets the Stratix high-level input voltage (VIH)
specification.
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Figure 3–14. Multiple Device Parallel Configuration with the Same Data Using a Microprocessor
VCC (1)
10 kΩ
Memory
ADDR DATA[7..0]
VCC (1)
Stratix Device
10 kΩ
Stratix Device
MSEL2
CONF_DONE
nSTATUS
nCE
Microprocessor
CONF_DONE
nSTATUS
N.C. (2)
MSEL1
MSEL0
nCE
GND
nCEO
GND
MSEL2
MSEL1
MSEL0
GND
nCEO
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (2)
Notes to Figure 3–14:
(1)
(2)
You should connect the pull-up resistors to any VCC that meets the Stratix high-level input voltage (VIH)
specification.
The nCEO pins are left unconnected when configuring the same data into multiple Stratix or Stratix GX devices.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in Volume II of the Configuration Handbook.
FPP Configuration Timing
Figure 3–15 shows FPP timing waveforms for configuring a Stratix or
Stratix GX device in FPP mode. Table 3–9 shows the FPP timing
parameters for Stratix or Stratix GX devices.
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Configuring Stratix & Stratix GX Devices
Figure 3–15. Timing Waveform for Configuring Devices in FPP Mode
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA[7..0}
Bit 0 Bit 1 Bit 2 Bit 3
(4)
Bit n
User Mode
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to:
(1)
(2)
(3)
(4)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings
Table 3–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Units
tCF2CK
nCONFIG high to first rising edge on DCLK
tDSU
Data setup time before rising edge on DCLK
7
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCFG
nCONFIG low pulse width
40
µs
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK frequency
40
µs
100
MHz
tCD2UM
CONF_DONE high to user mode (1)
20
µs
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
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Table 3–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 2 of 2)
Symbol
Parameter
Min
tCF2ST1
nCONFIG high to nSTATUS high
tSTATUS
nSTATUS low pulse width
10
tST2CK
nSTATUS high to firstrising edge of DCLK
1
Max
Units
40 (2)
µs
40 (2)
µs
µs
Notes to Table 3–9:
(1)
(2)
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
PPA Configuration
In PPA schemes, a microprocessor drives data to the Stratix or Stratix GX
device through a download cable. When using a PPA scheme, use a 1-kΩ
pull-up resistor to pull the DCLK pin high to prevent unused
configuration pins from floating.
To begin configuration, the microprocessor drives nCONFIG high and
then asserts the target device’s nCS pin low and CS pin high. Next, the
microprocessor places an 8-bit configuration word on the target device’s
data inputs and pulses nWS low. On the rising edge of nWS, the target
device latches a byte of configuration data and then drives its RDYnBSY
signal low, indicating that it is processing the byte of configuration data.
The microprocessor then performs other system functions while the
Stratix or Stratix GX device is processing the byte of configuration data.
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is high and CONF_DONE is low, the microprocessor sends the next data
byte. If nSTATUS is low, the device is signaling an error and the
microprocessor should restart configuration. However, if nSTATUS is
high and all the configuration data is received, the device is ready for
initialization. At the beginning of initialization, CONF_DONE goes high to
indicate that configuration is complete. Initialization, by default, uses an
internal oscillator, which runs at 10 MHz. After initialization, this internal
oscillator is turned off. When initialization is complete, the Stratix or
Stratix GX device enters user mode.
Figure 3–16 shows the PPA configuration circuit. An optional address
decoder controls the device’s nCS and CS pins. This decoder allows the
microprocessor to select the Stratix or Stratix GX device by accessing a
particular address, simplifying the configuration process.
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Configuring Stratix & Stratix GX Devices
Figure 3–16. PPA Configuration Circuit
VCC (1)
10 kΩ
Address Decoder
ADDR
VCC (1)
Memory
10 kΩ
VCC (1)
ADDR DATA[7..0]
10 k Ω
VCC
Stratix Device
nCS
MSEL2
CS
MSEL1
CONF_DONE
MSEL0
nSTATUS
GND
nCE
Microprocessor
nCEO
GND
N.C.
VCC (1)
DATA[7..0]
nWS
nRS
10 kΩ
nCONFIG
RDYnBSY
DCLK
Notes to Figure 3–16:
(1)
The pull-up resistor should be connected to the same supply voltage as the Stratix or Stratix GX device.
The device’s nCS or CS pins can be toggled during PPA configuration if
the design meets the specifications for tCSSU, tWSP, and tCSH given in
Table 3–10 on page 3–36. The microprocessor can also directly control the
nCS and CS signals. You can tie one of the nCS or CS signals to its active
state (i.e., nCS may be tied low) and toggle the other signal to control
configuration.
Stratix and Stratix GX devices can serialize data internally without the
microprocessor. When the Stratix or Stratix GX device is ready for the
next byte of configuration data, it drives RDYnBSY high. If the
microprocessor senses a high signal when it polls RDYnBSY, the
microprocessor strobes the next byte of configuration data into the
device. Alternatively, the nRS signal can be strobed, causing the
RDYnBSY signal to appear on DATA7. Because RDYnBSY does not need to
be monitored, reading the state of the configuration data by strobing nRS
low saves a system I/O port. Do not drive data onto the data bus while
nRS is low because it causes contention on DATA7. If the nRS pin is not
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used to monitor configuration, you should tie it high. To simplify
configuration, the microprocessor can wait for the total time of
tBUSY (max) + tRDY2WS + tW2SB before sending the next data bit.
After configuration, the nCS, CS, nRS, nWS, and RDYnBSY pins act as user
I/O pins. However, if the PPA scheme is chosen in the Quartus II
software, these I/O pins are tri-stated by default in user mode and should
be driven by the microprocessor. To change the default settings in the
Quartus II software, select Device & Pin Option (Compiler Setting
menu).
If the Stratix or Stratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on, the Stratix or Stratix GX device releases nSTATUS after a
reset time-out period. After nSTATUS is released, the microprocessor can
reconfigure the Stratix or Stratix GX device. At this point, the
microprocessor does not need to pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The microprocessor must
monitor the CONF_DONE pin to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data and starts initialization but CONF_DONE is not asserted, the
microprocessor must reconfigure the Stratix or Stratix GX device.
By default, the INIT_DONE is disabled. You can enable the INIT_DONE
output by turning on the Enable INIT_DONE output option in the
Quartus II software. If you do not turn on the Enable INIT_DONE
output option in the Quartus II software, you are advised to wait for the
maximum value of tCD2UM (see Table 3–10) after the CONF_DONE signal
goes high to ensure the device has been initialized properly and that it has
entered user mode.
During configuration and initialization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
You can also use PPA mode to configure multiple Stratix and Stratix GX
devices. Multi-device PPA configuration is similar to single-device PPA
configuration, except that the Stratix and Stratix GX devices are cascaded.
After you configure the first Stratix or Stratix GX device, nCEO is asserted,
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Configuring Stratix & Stratix GX Devices
which asserts the nCE pin on the second device, initiating configuration.
Because the second Stratix or Stratix GX device begins configuration
within one write cycle of the first device, the transfer of data destinations
is transparent to the microprocessor. All Stratix and Stratix GX device
CONF_DONE pins are tied together; therefore, all devices initialize and
enter user mode at the same time. See Figure 3–17.
Figure 3–17. PPA Multi-Device Configuration Circuit
VCC (2)
VCC (2)
VCC (2)
10 kΩ
10 kΩ
VCC (3)
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
Stratix Device 1
DATA[7..0]
nCS
CS (1)
CONF_DONE
nSTATUS
Microprocessor
Stratix Device 2
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL2
MSEL1
MSEL0
GND
DATA[7..0]
DCLK
nCS
CS (1)
CONF_DONE
nSTATUS
nCE
nCEO
nWS
nRS
MSEL2
nCONFIG
MSEL1
RDYnBSY
MSEL0
N.C.
VCC
GND
Notes to Figure 3–17:
(1)
(2)
If not used, you can connect the CS pin to VCC directly. If not used, the nCS pin can be connected to GND directly.
Connect the pull-up resistor to the same supply voltage as the Stratix or Stratix GX device.
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PPA Configuration Timing
Figure 3–18 shows the Stratix and Stratix GX device timing waveforms
for PPA configuration.
Figure 3–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
tCFG tCF2ST1
nCONFIG
nSTATUS (1)
CONF_DONE (2)
Byte 0
DATA[7..0]
Byte 1
Byte n Ð 1
Byte n
tDSU
tCSSU
tCF2WS
CS (3)
(4)
tDH
tCSSU
(4)
nCS (3)
tWSP
tCSH
(4)
nWS (3)
tRDY2WS
(4)
RDYnBSY (3)
tWS2B
tSTATUS
tCF2ST0
tCF2CD
User I/Os
tBUSY
tCD2UM
(4)
High-Z
INIT_DONE
Notes to Figure 3–18:
(1)
(2)
(3)
(4)
Upon power-up, nSTATUS is held low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or
Stratix GX device.
Device I/O pins are in user mode.
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Configuring Stratix & Stratix GX Devices
Figure 3–19 shows the Stratix and Stratix GX timing waveforms when
using strobed nRS and nWS signals.
Figure 3–19. PPA Timing Waveforms Using Strobed nRS & nWS Signals
tCF2ST1
tCFG
nCONFIG
nSTATUS
tCF2SCD
tCF2ST0
tSTATUS
CONF_DONE
tCSSU
(2)
nCS (1)
tCSH
(2)
CS (1)
tDH
Byte 0
DATA[7..0]
Byte n
Byte 1
(3)
tDSU
(2)
nWS
tWSP
nRS
INIT_DONE
User I/O
tRS2WS
tWS2RS
tCF2WS
(2)
tWS2RS
tRSD7
tRDY2WS
(2)
tWS2B
(2)
DATA7/RDYnBSY (4)
tCD2UM
tBUSY
Notes to Figure 3–19:
(1)
(2)
(3)
(4)
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
Device I/O pins are in user mode.
The DATA[7..0] pins are available as user I/Os after configuration and the state of theses pins depends on the
dual-purpose pin settings. Do not leave DATA[7..0] floating. If these pins are not used in user-mode, you should
drive them high or low, whichever is more convenient.
DATA7 is a bidirectional pin. It represents an input for data input, but represents an output to show the status of
RDYnBSY.
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August 2004
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Configuration Schemes
Table 3–10 defines the Stratix and Stratix GX timing parameters for PPA
configuration
Table 3–10. PPA Timing Parameters for Stratix & Stratix GX Devices
Symbol
Parameter
Min
Max
Units
tCF2WS
nCONFIG high to first rising edge on nWS
40
µs
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0
ns
tCSSU
Chip select setup time before rising edge on nWS
10
ns
tCSH
Chip select hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
15
ns
40
tCFG
nCONFIG low pulse width
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
tRDY2WS
RDYnBSY rising edge to nWS rising edge
15
ns
tWS2RS
nWS rising edge to nRS falling edge
15
ns
tRS2WS
nRS rising edge to nWS rising edge
15
ns
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
tSTATUS
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCF2ST1
nCONFIG high to nSTATUS high
7
µs
20
ns
45
ns
20
ns
CONF_DONE high to user mode (1)
6
20
µs
nSTATUS low pulse width
10
40 (2)
µs
800
ns
800
ns
40 (2)
µs
Notes to Table 3–10:
(1)
(2)
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtained if you do not delay configuration by extending the nstatus to low pulse width.
f
For information on how to create configuration and programming files
for this configuration scheme, see Software Settings in Volume 2 of the
Configuration Handbook.
JTAG Programming & Configuration
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on printed circuit boards (PCBs) with tight lead spacing.
The BST architecture can test pin connections without using physical test
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August 2004
Configuring Stratix & Stratix GX Devices
probes and capture functional data while a device is operating normally.
You can also use the JTAG circuitry to shift configuration data into the
device.
f
For more information on JTAG boundary-scan testing, see AN 39: IEEE
1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
To use the SignalTap® II embedded logic analyzer, you need to connect
the JTAG pins of your Stratix device to a download cable header on your
PCB.
f
For more information on SignalTap II, see the Design Debugging Using
SignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The four JTAG input pins (TDI,
TMS, TCK and TRST) have weak, internal pull-up resistors, whose values
range from 20 to 40 kΩ. All other pins are tri-stated during JTAG
configuration. Do not begin JTAG configuration until all other
configuration is complete. Table 3–11 shows each JTAG pin’s function.
Table 3–11. JTAG Pin Descriptions
Pin
Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. The VCCSEL pin controls the input buffer
selection.
TDO
Test data output
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. The high level output voltage is determined by VCCIO.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of the Test
Access Port (TAP) controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK. The VCCSEL pin
controls the input buffer selection.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. The VCCSEL pin controls the input buffer
selection.
TRST Test reset input
Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to IEEE Std. 1149.1. The VCCSEL pin controls the input
buffer selection.
(optional)
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August 2004
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Configuration Schemes
During JTAG configuration, data is downloaded to the device on the PCB
through the MasterBlaster or ByteBlasterMV header. Configuring devices
through a cable is similar to programming devices in-system. One
difference is to connect the TRST pin to VCC to ensure that the TAP
controller is not reset. See Figure 3–20.
Figure 3–20. JTAG Configuration of a Single Device
VCC (1)
1 kΩ
VCC
VCC (1)
10 kΩ
VCC
10 kΩ
Stratix or
Stratix GX Device
nCE
TCK
TDO
TRST
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
MSEL2
DATA0
DCLK
TMS
TDI
GND
VCC
(2)
(2)
(2)
(2)
(2)
(2)
1 kΩ
MasterBlaster or ByteBlasterMV
10-Pin Male Header
(Top View)
Pin 1
VCC (1)
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 3–20:
(1)
(2)
(3)
You should connect the pull-up resistor to the same supply voltage as the
download cable.
You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG
configuration scheme. If you only use JTAG configuration, connect nCONFIG to
VCC, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK to high or
low.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the
device’s VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data
Sheet for this value.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
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August 2004
Configuring Stratix & Stratix GX Devices
Stratix and Stratix GX devices have dedicated JTAG pins. You can
perform JTAG testing on Stratix and Stratix GX devices before and after,
but not during configuration. The chip-wide reset and output enable pins
on Stratix and Stratix GX devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins does not affect JTAG
operations (other than the usual boundary-scan operation).
When designing a board for JTAG configuration of Stratix and Stratix GX
devices, you should consider the regular configuration pins. Table 3–12
shows how you should connect these pins during JTAG configuration.
Table 3–12. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all Stratix and Stratix GX devices in the chain, nCE should be driven low by connecting it to
ground, pulling it low via a resistor, or driving it by some control circuitry. For devices that are
also in multi-device PS, FPP or PPA configuration chains, the nCE pins should be connected to
GND during JTAG configuration or JTAG configured in the same order as the configuration
chain.
nCEO
On all Stratix and Stratix GX devices in the chain, nCEO can be left floating or connected to the
nCE of the next device. See nCE pin description above.
MSEL
These pins must not be left floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG
nCONFIG must be driven high through the JTAG programming process. Driven high by
connecting to VC C , pulling high via a resistor, or driven by some control circuitry.
nSTATUS
Pull to VC C via a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain,
each nSTATUS pin should be pulled up to VC C individually. nSTATUS pulling low in the middle
of JTAG configuration indicates that an error has occurred.
CONF_DONE Pull to VC C via a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain,
each CONF_DONE pin should be pulled up to VC C individually. CONF_DONE going high at the
end of JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0
Should not be left floating. Drive low or high, whichever is more convenient on your board.
JTAG Programming & Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header,
such as the ByteBlasterMV header, is connected to several devices. The
number of devices in the JTAG chain is limited only by the drive capacity
of the download cable. However, when more than five devices are
connected in a JTAG chain, Altera recommends buffering the TCK, TDI,
and TMS pins with an on-board buffer.
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Configuration Schemes
JTAG-chain device programming is ideal when the PCB contains
multiple devices, or when testing the PCB using JTAG BST circuitry.
Figure 3–21 shows multi-device JTAG configuration.
Figure 3–21. Multi-Device JTAG Configuration
VCC
MasterBlaster or ByteBlasterMV
10-Pin Male Header
Notes (1), (2)
VCC
10 kΩ
10 kΩ
10 kΩ
Stratix Device
VCC
VCC
VCC
10 kΩ
VCC
10 kΩ
Stratix Device
10 kΩ
Stratix Device
VCC
Pin 1
1 kΩ
VCC
VCC
1 kΩ
VIO
(4)
(3)
(3)
(3)
(3)
(3)
(3)
(5)
nSTATUS
DATA0
DCLK
nCONFIG
MSEL2 CONF_DONE
MSEL1
MSEL0
nCE
TDI
TMS
TCK
TDO
(3)
(3)
(3)
(3)
(3)
(3)
(5)
nSTATUS
DATA0
DCLK
nCONFIG
MSEL2 CONF_DONE
MSEL1
MSEL0
nCE
TDI
TMS
TDO
TCK
nSTATUS
(3)
(3)
(3)
(3)
(3)
(3)
(5)
DATA0
DCLK
nCONFIG
MSEL2 CONF_DONE
MSEL1
MSEL0
nCE
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 3–21:
(1)
(2)
(3)
(4)
(5)
Stratix, Stratix GX, APEXTM II, APEX 20K, MercuryTM, ACEX® 1K, and FLEX® 10K devices can be placed within the
same JTAG chain for device programming and configuration.
For more information on all configuration pins connected in this mode, refer to Table 3–11 on page 3–37.
Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK
to either high or low.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. Refer to the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, FPP and PPA configuration chains, the
first device's nCE pin is connected to GND while its nCEO pin is connected
to nCE of the next device in the chain. The last device's nCE input comes
from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its
nCEO pin drives low to activate the second device's nCE pin, which
prompts the second device to begin configuration. Therefore, if these
devices are also in a JTAG chain, you should make sure the nCE pins are
connected to GND during JTAG configuration or that the devices are JTAG
configured in the same order as the configuration chain. As long as the
devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives nCE of the
next device low when it has successfully been JTAG configured.
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August 2004
Configuring Stratix & Stratix GX Devices
The Quartus II software verifies successful JTAG configuration upon
completion. The software checks the state of CONF_DONE through the
JTAG port. If CONF_DONE is not in the correct state, the Quartus II
software indicates that configuration has failed. If CONF_DONE is in the
correct state, the software indicates that configuration was successful.
1
If VCCIO is tied to 3.3 V, both the I/O pins and JTAG TDO port
drive at 3.3-V levels.
Do not attempt JTAG and non-JTAG configuration simultaneously.
When configuring through JTAG, allow any non-JTAG configuration to
complete first.
Figure 3–22 shows the JTAG configuration of a Stratix or Stratix GX
device with a microprocessor.
Figure 3–22. JTAG Configuration of Stratix & Stratix GX Devices with a
Microprocessor
Stratix or
Stratix GX Device
Memory
ADDR
DATA
(1)
(2)
(2)
Microprocessor
MSEL2
MSEL1
nCONFIG MSEL0
DATA0
DCLK
TDI
TCK
TDO
TMS
nSTATUS
(1)
(1)
(1)
VCC
VCC
10 kΩ
10 kΩ
CONF_DONE
Notes to Figure 3–22:
(1)
(2)
Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG
configuration scheme. If your design only uses JTAG configuration, connect the
nCONFIG pin to VCC and the MSEL2, MSEL1, and MSEL0 pins to ground.
Pull DATA0 and DCLK to either high or low.
Configuration with JRunner Software Driver
JRunner is a software driver that allows you to configure Altera FPGAs
through the ByteBlasterMV download cable in JTAG mode. The
programming input file supported is in Raw Binary File (.rbf) format.
JRunner also requires a Chain Description File (.cdf) generated by the
Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has been developed for the Windows NT
operating system. You can customize the code to make it run on other
platforms.
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August 2004
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Configuration Schemes
f
For more information on the JRunner software driver, refer to the
JRunner Software Driver: An Embedded Solution to the JTAG Configuration
White Paper and zip file.
Jam STAPL Programming & Test Language
The JamTM Standard Test and Programming Language (STAPL), JEDEC
standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or
configuration of programmable devices and testing of electronic systems,
using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely licensed open
standard.
Connecting the JTAG Chain to the Embedded Processor
There are two ways to connect the JTAG chain to the embedded
processor. The most straightforward method is to connect the embedded
processor directly to the JTAG chain. In this method, four of the processor
pins are dedicated to the JTAG interface, saving board space but reducing
the number of available embedded processor pins.
Figure 3–23 illustrates the second method, which is to connect the JTAG
chain to an existing bus through an interface PLD. In this method, the
JTAG chain becomes an address on the existing bus. The processor then
reads from or writes to the address representing the JTAG chain.
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Configuring Stratix & Stratix GX Devices
Figure 3–23. Embedded System Block Diagram
Embedded System
TDI
TMS
to/from ByteBlasterMV
Interface
Logic
(Optional)
TCK
TDO
TDI
Control
Control
8
d[7..0]
4
TMS
TDI
TCK
d[3..0]
Any JTAG
Device
TMS
TDO
TCK
20
adr[19..0]
TDO
Embedded
Processor
MAX® 9000,
MAX 9000A,
MAX 7000S,
MAX 7000A,
MAX 7000AE,
or MAX 3000
Device
TDI
Control
8
d[7..0]
TMS
EPROM or
System
Memory
TCK
TDO
adr[19..0]
20
20
VCC VCC
adr[19..0]
VCC
TDI
TMS
TCK
10 kΩ
TRST
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
nCE
TDO
10 kΩ
Any Cyclone,
FLEX 10K,
FLEX 10KA,
FLEX10KE,
APEX 20K,
or APEX 20KE
Device
GND
TDI
TMS
TCK
(2)
(2)
DATA0
(1)
nCONFIG
DCLK
MSEL1
(1)
MSEL0
(1)
Cyclone FPGA
TDO
Notes to Figure 3–23:
(1)
(2)
Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design
only uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL2, MSEL1, and MSEL0 pins to ground.
Pull DATA0 and DCLK to either high or low.
Both JTAG connection methods should include space for the
MasterBlaster or ByteBlasterMV header connection. The header is useful
during prototyping because it allows you to verify or modify the Stratix
or Stratix GX device’s contents. During production, you can remove the
header to save cost.
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Configuration Schemes
Program Flow
The Jam Player provides an interface for manipulating the IEEE
Std. 1149.1 JTAG TAP state machine. The TAP controller is a 16-state state
machine that is clocked on the rising edge of TCK, and uses the TMS pin to
control JTAG operation in a device. Figure 3–24 shows the flow of an
IEEE Std. 1149.1 TAP controller state machine.
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August 2004
Configuring Stratix & Stratix GX Devices
Figure 3–24. JTAG TAP Controller State Machine
TMS = 1
TEST_LOGIC/
RESET
TMS = 0
SELECT_IR_SCAN
TMS = 1
TMS = 1
TMS = 0
TMS = 1
SELECT_DR_SCAN
RUN_TEST/
IDLE
TMS = 0
TMS = 0
TMS = 1
TMS = 1
CAPTURE_IR
CAPTURE_DR
TMS = 0
TMS = 0
SHIFT_DR
SHIFT_IR
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 1
EXIT1_DR
EXIT1_IR
TMS = 0
TMS = 0
PAUSE_DR
PAUSE_IR
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
EXIT2_DR
EXIT2_IR
TMS = 1
TMS = 1
TMS = 1
TMS = 1
UPDATE_DR
TMS = 0
UPDATE_IR
TMS = 0
While the Jam Player provides a driver that manipulates the TAP
controller, the Jam Byte-Code File (.jbc) provides the high-level
intelligence needed to program a given device. All Jam instructions that
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Configuration Schemes
send JTAG data to the device involve moving the TAP controller through
either the data register leg or the instruction register leg of the state
machine. For example, loading a JTAG instruction involves moving the
TAP controller to the SHIFT_IR state and shifting the instruction into the
instruction register through the TDI pin. Next, the TAP controller is
moved to the RUN_TEST/IDLE state where a delay is implemented to
allow the instruction time to be latched. This process is identical for data
register scans, except that the data register leg of the state machine is
traversed.
The high-level Jam instructions are the DRSCAN instruction for scanning
the JTAG data register, the IRSCAN instruction for scanning the
instruction register, and the WAIT command that causes the state machine
to sit idle for a specified period of time. Each leg of the TAP controller is
scanned repeatedly, according to instructions in the JBC file, until all of
the target devices are programmed.
Figure 3–25 illustrates the functional behavior of the Jam Player when it
parses the JBC file. When the Jam Player encounters a DRSCAN, IRSCAN,
or WAIT instruction, it generates the proper data on TCK, TMS, and TDI to
complete the instruction. The flow diagram shows branches for the
DRSCAN, IRSCAN, and WAIT instructions. Although the Jam Player
supports other instructions, they are omitted from the flow diagram for
simplicity.
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August 2004
Configuring Stratix & Stratix GX Devices
Figure 3–25. Jam Player Flow Diagram (Part 1 of 2)
Start
Set TMS to 1
and Pulse TCK
Five Times
Test-Logic-Reset
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
WAIT
Read Instruction
from the Jam
File
EOF?
F
T
Case[]
DRSCAN
IRSCAN
Set TMS to 0
and Pulse TCK
Parse Argument
Parse Argument
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Twice
Delay
Set TMS to 1
and Pulse TCK
Select-IR-Scan
Set TMS to 1
and Pulse TCK
Three Times
Set TMS to 0
and Pulse TCK
Twice
Set TMS to 0
and Pulse TCK
Twice
Switch
Test-Logic-Reset
Shift-DR
Shift-IR
Set TMS to 0
and Pulse TCK
and Write TDI
End
Set TMS to 1
and Pulse TCK
Select-DR-Scan
Set TMS to 0
and Pulse TCK
and Write TDI
Shift-IR
Shift-DR
Exit1-IR
Set TMS to 0
and Pulse TCK
Pause-IR
Set TMS to 1
and Pulse TCK
Twice
T
EOF
Shift-IR
Continued on
Part 2 of
Flow Diagram
F
Set TMS to 0
and Pulse TCK
and Write TDI
Update-IR
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
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Configuration Schemes
Figure 3–26. Jam Player Flow Diagram (Part 2 of 2)
Continued from
Part 1 of
Flow Diagram
Compare
Case[]
Default
Capture
Set TMS to 1
and Pulse TCK
and Store TDO
F
Exit1-DR
Loop<
DR Length
F
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 1
and Pulse TCK
Update-IR
Shift-DR
T
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Exit1-DR
T
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Loop<
DR Length
Correct F
TDO Value
Report
Error
Set TMS to 0
and Pulse TCK
Set TMS to 1
and Pulse TCK
and Store TDO
F
Loop<
DR Length
Run-Test/Idle
Exit1-DR
T
T
Switch
Set TMS to 1
and Pulse TCK
Set TMS to 1
and Pulse TCK
Update-IR
Set TMS to 0
and Pulse TCK
and Write TDI
Update-IR
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
Switch
Execution of a Jam program starts at the beginning of the program. The
program flow is controlled using GOTO, CALL/RETURN, and FOR/NEXT
structures. The GOTO and CALL statements refer to labels that are
symbolic names for program statements located elsewhere in the Jam
program. The language itself enforces almost no constraints on the
organizational structure or control flow of a program.
1
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Configuration Handbook, Volume 1
The Jam language does not support linking multiple Jam
programs together or including the contents of another file into
a Jam program.
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August 2004
Configuring Stratix & Stratix GX Devices
Jam Instructions
Each Jam statement begins with one of the instruction names listed in
Table 3–13. The instruction names, including the names of the optional
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 3–13. Instruction Names
BOOLEAN
INTEGER
PREIR
CALL
IRSCAN
PRINT
CRC
IRSTOP
PUSH
DRSCAN
LET
RETURN
DRSTOP
NEXT
STATE
EXIT
NOTE
WAIT
EXPORT
POP
VECTOR (1)
FOR
POSTDR
VMAP (1)
GOTO
POSTIR
–
IF
PREDR
–
Note to Table 3–13:
(1)
This instruction name is an optional language extension.
Table 3–14 shows the state names that are reserved keywords in the Jam
language. These keywords correspond to the state names specified in the
IEEE Std. 1149.1 JTAG specification.
Table 3–14. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names
Test-Logic-Reset
Altera Corporation
August 2004
Jam Reserved State Names
RESET
Run-Test-Idle
IDLE
Select-DR-Scan
DRSELECT
Capture-DR
DRCAPTURE
Shift-DR
DRSHIFT
Exit1-DR
DREXIT1
Pause-DR
DRPAUSE
Exit2-DR
DREXIT2
Update-DR
DRUPDATE
Select-IR-Scan
IRSELECT
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Configuration Schemes
Table 3–14. Reserved Keywords (Part 2 of 2)
IEEE Std. 1149.1 JTAG State Names
Jam Reserved State Names
Capture-IR
IRCAPTURE
Shift-IR
IRSHIFT
Exit1-IR
IREXIT1
Pause-IR
IRPAUSE
Exit2-IR
IREXIT2
Update-IR
IRUPDATE
Example Jam File that Reads the IDCODE
Figure 3–27 illustrates the flexibility and utility of the Jam STAPL. The
example reads the IDCODE out of a single device in a JTAG chain.
1
The array variable, I_IDCODE, is initialized with the IDCODE
instruction bits ordered the LSB first (on the left) to most
significant bit (MSB) (on the right). This order is important
because the array field in the IRSCAN instruction is always
interpreted, and sent, MSB to LSB.
Figure 3–27. Example Jam File Reading IDCODE
BOOLEAN read_data[32];
BOOLEAN I_IDCODE[10] = BIN 1001101000; ‘assumed
BOOLEAN ONES_DATA[32] = HEX FFFFFFFF;
INTEGER i;
‘Set up stop state for IRSCAN
IRSTOP IRPAUSE;
‘Initialize device
STATE RESET;
IRSCAN 10, I_IDCODE[0..9]; ‘LOAD IDCODE INSTRUCTION
STATE IDLE;
WAIT 5 USEC, 3 CYCLES;
DRSCAN 32, ONES_DATA[0..31], CAPTURE
read_data[0..31];
‘CAPTURE IDCODE
PRINT “IDCODE:”;
FOR i=0 to 31;
PRINT read_data[i];
NEXT i;
EXIT 0;
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August 2004
Configuring Stratix & Stratix GX Devices
Configuring
Using the
MicroBlaster
Driver
The MicroBlasterTM software driver allows you to configure Altera
devices in an embedded environment using PS or FPP mode. The
MicroBlaster software driver supports a Raw Binary File (.rbf)
programming input file. The source code is developed for the Windows
NT operating system, although you can customize it to run on other
operating systems. For more information on the MicroBlaster software
driver, go to the Altera web site (http://www.altera.com).
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration related pins on the Stratix or Stratix GX device. Table 3–15
describes the dedicated configuration pins, which are required to be
connected properly on your board for successful configuration. Some of
these pins may not be required for your configuration schemes.
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
VCCSEL
User Mode
N/A
Configuration
Scheme
All
Pin Type
Input
(Part 1 of 8)
Description
Dedicated input that selects which input buffer
is used on the configuration input pins;
nCONFIG, DCLK, RUnLU, nCE, nWS, nRS, CS,
nCS and CLKUSR.
The VCCSEL input buffer is powered by VC C I N T
and has an internal 2.5 kΩ pull-down resistor
that is always active.
A logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects
the 1.8-V/1.5-V input buffer, and a logic low
selects the 3.3-V/2.5-V input buffer. See the
“VCCSEL Pins” section for more details.
PORSEL
N/A
All
Input
Dedicated input which selects between a POR
time of 2 ms or 100 ms. A logic high (1.5-V, 1.8V, 2.5-V, 3.3-V) selects a POR time of about 2
ms and a logic low selects POR time of about
100 ms.
The PORSEL input buffer is powered by VC C I N T
and has an internal 2.5 kΩ pull-down resistor
that is always active.
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Device Configuration Pins
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
nIO_PULLUP
User Mode
N/A
Configuration
Scheme
All
Pin Type
Input
(Part 2 of 8)
Description
Dedicated input that chooses whether the
internal pull-ups on the user I/Os and dualpurpose I/Os (DATA[7..0], nWS, nRS,
RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR,
INIT_DONE, DEV_OE, DEV_CLR) are on or off
before and during configuration. A logic high
(1.5-V, 1.8-V, 2.5-V, 3.3-V) turns off the weak
internal pull-ups, while a logic low turns them
on.
The nIO_PULLUP input buffer is powered by
VC C I N T and has an internal 2.5 kΩ pull-down
resistor that is always active.
MSEL[2..0]
N/A
All
Input
3-bit configuration input that sets the Stratix or
Stratix GX device configuration scheme. See
Table 3–2 for the appropriate connections.
These pins can be connected to VC C I O of the
I/O bank they reside in or ground. This pin uses
Schmitt trigger input buffers.
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low
during user-mode causes the FPGA to lose its
configuration data, enter a reset state, tri-state
all I/O pins. Returning this pin to a logic high
level initiates a reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, nCONFIG
can be tied directly to VC C or to the
configuration device’s nINIT_CONF pin. This
pin uses Schmitt trigger input buffers.
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August 2004
Configuring Stratix & Stratix GX Devices
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
nSTATUS
User Mode
N/A
Configuration
Scheme
All
Pin Type
(Part 3 of 8)
Description
Bidirectional The device drives nSTATUS low immediately
open-drain
after power-up and releases it after the POR
time.
Status output. If an error occurs during
configuration, nSTATUS is pulled low by the
target device. Status input. If an external source
drives the nSTATUS pin low during
configuration or initialization, the target device
enters an error state.
Driving nSTATUS low after configuration and
initialization does not affect the configured
device. If a configuration device is used, driving
nSTATUS low causes the configuration device
to attempt to configure the FPGA, but since the
FPGA ignores transitions on nSTATUS in usermode, the FPGA does not reconfigure. To
initiate a reconfiguration, nCONFIG must be
pulled low.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins have optional internal
programmable pull-up resistors. If internal pullup resistors on the enhanced configuration
device are used, external 10-kΩ pull-up
resistors should not be used on these pins.
When using EPC2 devices, only external 10-kΩ
pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
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Device Configuration Pins
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
CONF_DONE
User Mode
N/A
Configuration
Scheme
All
Pin Type
(Part 4 of 8)
Description
Bidirectional Status output. The target FPGA drives the
open-drain
CONF_DONE pin low before and during
configuration. Once all configuration data is
received without error and the initialization cycle
starts, the target device releases CONF_DONE.
Status input. After all data is received and
CONF_DONE goes high, the target device
initializes and enters user mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured
device.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins have optional internal
programmable pull-up resistors. If internal pullup resistors on the enhanced configuration
device are used, external 10-kΩ pull-up
resistors should not be used on these pins.
When using EPC2 devices, only external 10-kΩ
pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates
the device with a low signal to allow
configuration. The nCE pin must be held low
during configuration, initialization, and user
mode. In single device configuration, it should
be tied low. In multi-device configuration, nCE
of the first device is tied low while its nCEO pin
is connected to nCE of the next device in the
chain.
The nCE pin must also be held low for
successful JTAG programming of the FPGA.
This pin uses Schmitt trigger input buffers.
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August 2004
Configuring Stratix & Stratix GX Devices
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
nCEO
User Mode
N/A
Configuration
Scheme
All MultiDevice
Schemes
Pin Type
Output
(Part 5 of 8)
Description
Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In multidevice configuration, this pin feeds the next
device’s nCE pin. The nCEO of the last device in
the chain is left floating.
The voltage levels driven out by this pin are
dependent on the VC C I O of the I/O bank it
resides in.
DCLK
N/A
Synchronous
configuration
schemes
(PS, FPP)
Input
(PS, FPP)
In PS and FPP configuration, DCLK is the clock
input used to clock data from an external source
into the target device. Data is latched into the
FPGA on the rising edge of DCLK.
In PPA mode, DCLK should be tied high to VC C
to prevent this pin from floating.
After configuration, this pin is tri-stated. In
schemes that use a configuration device, DCLK
is driven low after configuration is done. In
schemes that use a control host, DCLK should
be driven either high or low, whichever is more
convenient. Toggling this pin after configuration
does not affect the configured device. This pin
uses Schmitt trigger input buffers.
DATA0
I/O
PS, FPP,
PPA
Input
Data input. In serial configuration modes, bitwide configuration data is presented to the
target device on the DATA0 pin. The VI H and
VI L levels for this pin are dependent on the
VC C I O of the I/O bank that it resides in.
After configuration, DATA0 is available as a
user I/O and the state of this pin depends on the
Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
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Device Configuration Pins
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
DATA[7..1]
User Mode
I/O
Configuration
Scheme
Parallel
configuration
schemes
(FPP and
PPA)
Pin Type
Inputs
(Part 6 of 8)
Description
Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0]. The VI H and VI L levels for these
pins are dependent on the VC C I O of the I/O
banks that they reside in.
In serial configuration schemes, they function
as user I/Os during configuration, which means
they are tri-stated.
After PPA or FPP configuration, DATA[7..1]
are available as a user I/Os and the state of
these pin depends on the Dual-Purpose Pin
settings.
DATA7
I/O
PPA
Bidirectional In the PPA configuration scheme, the DATA7
pin presents the RDYnBSY signal after the nRS
signal has been strobed low. The VI L and VI L
levels for this pin are dependent on the VC C I O
of the I/O bank that it resides in.
In serial configuration schemes, it functions as
a user I/O during configuration, which means it
is tri-stated.
After PPA configuration, DATA7 is available as
a user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
nWS
I/O
PPA
Input
Write strobe input. A low-to-high transition
causes the device to latch a byte of data on the
DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O
during configuration, which means it is tristated.
After PPA configuration, nWS is available as a
user I/O and the state of this pin depends on the
Dual-Purpose Pin settings.
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August 2004
Configuring Stratix & Stratix GX Devices
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
nRS
User Mode
I/O
Configuration
Scheme
PPA
Pin Type
Input
(Part 7 of 8)
Description
Read strobe input. A low input directs the
device to drive the RDYnBSY signal on the
DATA7 pin.
If the nRS pin is not used in PPA mode, it should
be tied high. In non-PPA schemes, it functions
as a user I/O during configuration, which means
it is tri-stated.
After PPA configuration, nRS is available as a
user I/O and the state of this pin depends on the
Dual-Purpose Pin settings.
RDYnBSY
I/O
PPA
Output
Ready output. A high output indicates that the
target device is ready to accept another data
byte. A low output indicates that the target
device is busy and not ready to receive another
data byte.
In PPA configuration schemes, this pin drives
out high after power-up, before configuration
and after configuration before entering usermode. In non-PPA schemes, it functions as a
user I/O during configuration, which means it is
tri-stated.
After PPA configuration, RDYnBSY is available
as a user I/O and the state of this pin depends
on the Dual-Purpose Pin settings.
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Device Configuration Pins
Table 3–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
nCS/CS
User Mode
I/O
Configuration
Scheme
PPA
Pin Type
Input
(Part 8 of 8)
Description
Chip-select inputs. A low on nCS and a high on
CS select the target device for configuration.
The nCS and CS pins must be held active
during configuration and initialization.
During the PPA configuration mode, it is only
required to use either the nCS or CS pin.
Therefore, if only one chip-select input is used,
the other must be tied to the active state. For
example, nCS can be tied to GND while CS is
toggled to control configuration.In non-PPA
schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are
available as a user I/Os and the state of these
pins depends on the Dual-Purpose Pin
settings.
RUnLU
N/A if using
Remote
Configuration;
I/O if not
Remote
Configuration
in FPP, PS or
PPA
Input
Input that selects between remote update and
local update. A logic high (1.5-V, 1.8-V, 2.5-V,
3.3-V) selects remote update and a logic low
selects local update.
When not using remote update or local update
configuration modes, this pins is available as
general-purpose user I/O pin.
PGM[2..0]
N/A if using
Remote
Configuration;
I/O if not using
Remote
Configuration
in FPP, PS or
PPA
Input
These output pins select one of eight pages in
the memory (either flash or enhanced
configuration device) when using a remote
configuration mode.
When not using remote update or local update
configuration modes, these pins are available
as general-purpose user I/O pins.
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August 2004
Configuring Stratix & Stratix GX Devices
Table 3–16 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-ups.
Table 3–16. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is
on. I/O if option
is off.
Input
Optional user-supplied clock input. Synchronizes the
initialization of one or more devices. This pin is enabled by
turning on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software.
INIT_DONE
N/A if option is
on. I/O if option
is off.
Output opendrain
Status pin. Can be used to indicate when the device has
initialized and is in user mode. When nCONFIG is low and
during the beginning of configuration, the INIT_DONE pin is
tri-stated and pulled high due to an external 10-kΩ pull-up.
Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data),
the INIT_DONE pin goes low. When initialization is
complete, the INIT_DONE pin is released and pulled high
and the FPGA enters user mode. Thus, the monitoring
circuitry must be able to detect a low-to-high transition. This
pin is enabled by turning on the Enable INIT_DONE output
option in the Quartus II software.
DEV_OE
N/A if option is
on. I/O if option
is off.
Input
Optional pin that allows the user to override all tri-states on
the device. When this pin is driven low, all I/Os are tri-stated.
When this pin is driven high, all I/Os behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is
on. I/O if option
is off.
Input
Optional pin that allows you to override all clears on all
device registers. When this pin is driven low, all registers are
cleared. When this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
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Device Configuration Pins
Table 3–17 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. If you plan to use the SignalTap II Embedded Logic
Analyzer, you will need to connect the JTAG pins of your device to a
JTAG header on your board.
Table 3–17. Dedicated JTAG pins
Pin Name
User Mode
Pin Type
Description
TDI
N/A
Input
Serial input pin for instructions as well as test and
programming data. Data is shifted in on the rising edge of
TCK. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by connecting this pin to
VC C . This pin uses Schmitt trigger input buffers.
TDO
N/A
Output
Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge
of TCK. The pin is tri-stated if data is not being shifted out
of the device. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by leaving this
pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
within the state machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the rising edge of
TCK. TMS is evaluated on the rising edge of TCK. If the
JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to VC C .
This pin uses Schmitt trigger input buffers.
TCK
N/A
Input
The clock input to the BST circuitry. Some operations
occur at the rising edge, while others occur at the falling
edge. If the JTAG interface is not required on the board,
the JTAG circuitry can be disabled by connecting this pin
to GND. This pin uses Schmitt trigger input buffers.
TRST
N/A
Input
Active-low input to asynchronously reset the boundaryscan circuit. The TRST pin is optional according to IEEE
Std. 1149.1. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting
this pin to GND. This pin uses Schmitt trigger input buffers.
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August 2004
Chapter 4. Configuring
Cyclone II Devices
CII51013-1.0
Introduction
Cyclone™ II devices use SRAM cells to store configuration data. Since
SRAM memory is volatile, configuration data must be downloaded to
Cyclone II devices each time the device powers up. You can use the active
serial (AS) configuration scheme, which can operate at a DCLK frequency
up to 40 MHz, to configure Cyclone II devices. You can also use the
passive serial (PS) and Joint Test Action Group (JTAG)-based
configuration schemes to configure Cyclone II devices. Additionally,
Cyclone II devices can receive a compressed configuration bitstream and
decompress this data on-the-fly, reducing storage requirements and
configuration time.
This chapter explains the Cyclone II configuration features and describes
how to configure Cyclone II devices using the supported configuration
schemes. This chapter also includes configuration pin descriptions and
the Cyclone II configuration file format.
f
Cyclone II
Configuration
Overview
Altera Corporation
June 2004
For more information on setting device configuration options or creating
configuration files, see the Software Settings chapter in the Configuration
Handbook.
You can use the AS, PS, and JTAG configuration schemes to configure
Cyclone II devices. You can select which configuration scheme to use by
driving the Cyclone II device MSEL pins either high or low as shown in
Table 4–1. The MSEL pins are powered by the VCCIO power supply of the
bank they reside in. During power-on reset (POR) and reconfiguration,
the MSEL pins have to be at LVTTL VIL or VIH levels to be considered a
logic low or logic high, respectively. Therefore, to avoid any problems
with detecting an incorrect configuration scheme, you should connect the
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4–1
Preliminary
Cyclone II Configuration Overview
MSEL[] pins to the VCCIO of the I/O bank they reside in and GND
without any pull-up or pull-down resistors. The MSEL[] pins should not
be driven by a microprocessor or another device.
Table 4–1. Cyclone II Configuration Schemes
Configuration Scheme
AS (20 MHz) (1)
MSEL1
MSEL0
0
0
PS
0
1
Fast AS (40 MHz) (1)
1
0
(3)
(3)
JTAG-based Configuration (2)
Notes to Table 4–1:
(1)
(2)
(3)
Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz. Other EPCS
devices support a DCLK up to 20 MHz. See the Serial Configuration Devices Data
Sheet for more information.
JTAG-based configuration takes precedence over other configuration schemes,
which means MSEL pin settings are ignored.
Do not leave the MSEL pins floating; connect them to VCCIO or ground. These pins
support the non-JTAG configuration scheme used in production. If you are only
using JTAG configuration, you should connect the MSEL pins to ground.
You can download configuration data to Cyclone II FPGAs with the AS,
PS, or JTAG interfaces using the options in Table 4–2.
Table 4–2. Cyclone II Device Configuration Schemes
Configuration Scheme
Description
AS configuration
Configuration using serial configuration
devices (EPCS1, EPCS4, EPCS16 or
EPCS64 devices)
PS configuration
Configuration using enhanced configuration
devices (EPC4, EPC8, and EPC16 devices),
EPC2 and EPC1 configuration devices, an
intelligent host (microprocessor), or a
download cable
JTAG-based configuration
Configuration via JTAG pins using a
download cable, an intelligent host
(microprocessor), or the Jam™ Standard
Test and Programming Language (STAPL)
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June 2004
Configuring Cyclone II Devices
Configuration
File Format
Table 4–3 shows the approximate uncompressed configuration file sizes
for Cyclone II devices. To calculate the amount of storage space required
for multiple device configurations, add the file size of each device
together.
Table 4–3. Cyclone II Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
Note (1)
Data Size (Bytes)
EP2C5
1,223,980
152,998
EP2C8
1,983,792
247,974
EP2C20
3,930,986
491,374
EP2C35
7,071,234
883,905
EP2C50
9,122,148
1,140,269
EP2C70
10,249,694
1,281,212
Note to Table 4–3:
(1)
These values are preliminary.
Use the data in Table 4–3 only to estimate the file size before design
compilation. Different configuration file formats, such as a Hexadecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II software, any design
targeted for the same device will have the same uncompressed
configuration file size. If compression is used, the file size can vary after
each compilation since the compression ratio is dependent on the design.
Configuration
Data
Compression
Cyclone II devices support configuration data decompression, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory and transmit this compressed bitstream to Cyclone II devices.
During configuration, the Cyclone II device decompresses the bitstream
in real time and programs its SRAM cells.
1
Preliminary data indicates that compression reduces
configuration bitstream size by 35 to 55%.
Cyclone II devices support decompression in the AS and PS configuration
schemes. Decompression is not supported in JTAG-based configuration.
Although they both use the same compression algorithm, the
decompression feature supported by Cyclone II devices is different from
the decompression feature in enhanced configuration devices (EPC16,
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June 2004
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Configuration Handbook, Volume 1
Configuration Data Compression
EPC8, and EPC4 devices). The data decompression feature in the
enhanced configuration devices allows them to store compressed data
and decompress the bitstream before transmitting it to the target devices.
In PS mode, you should use the Cyclone II decompression feature since
sending compressed configuration data reduces configuration time. You
should not use both the Cyclone II device and the enhanced configuration
device decompression features simultaneously. The compression
algorithm is not intended to be recursive and could expand the
configuration file instead of compressing it further.
You should use the Cyclone II decompression feature during AS
configuration if you need to save configuration memory space in the
serial configuration device.
When you enable compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash,
and decreases the time needed to transmit the bitstream to the Cyclone II
device. The time required by a Cyclone II device to decompress a
configuration file is less than the time needed to transmit the
configuration data to the FPGA.
There are two methods to enable compression for Cyclone II bitstreams:
before design compilation (in the Compiler Settings menu) and after
design compilation (in the Convert Programming Files window).
To enable compression in the project's compiler settings, select Device
under the Assignments menu to bring up the settings window. After
selecting your Cyclone II device open the Device & Pin Options window,
and in the General settings tab enable the check box for Generate
compressed bitstreams (see Figure 4–1).
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June 2004
Configuring Cyclone II Devices
Figure 4–1. Enabling Compression for Cyclone II Bitstreams in Compiler
Settings
You can also use the following steps to enable compression when creating
programming files from the Convert Programming Files window.
Altera Corporation
June 2004
1.
Click Convert Programming Files (File menu).
2.
Select the Programming File type. Only Programmer Object Files
(.pof), SRAM HEXOUT, RBF, or TTF files support compression.
3.
For POFs, select a configuration device.
4.
Select Add File and add a Cyclone II SRAM Object File(s) (.sof).
5.
Select the name of the file you added to the SOF Data area and click
on Properties.
6.
Check the Compression check box.
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Active Serial Configuration (Serial Configuration Devices)
When multiple Cyclone II devices are cascaded, the compression feature
can be selectively enabled for each device in the chain. Figure 4–2 depicts
a chain of two Cyclone II devices. The first Cyclone II device has
compression enabled and therefore receives a compressed bitstream from
the configuration device. The second Cyclone II device has the
compression feature disabled and receives uncompressed data.
Figure 4–2. Compressed & Uncompressed Configuration Data in a
Programming File
Serial Data
Serial or Enhanced
Configuration
Device
Compressed
Uncompressed
VCC
Decompression
Controller
Decompression
Controller
10 kΩ
Cyclone II
Device
nCE
nCEO
Cyclone II
Device
nCE
nCEO
N.C.
GND
You can generate programming files (e.g., POF files) for this setup in the
Quartus II software.
Active Serial
Configuration
(Serial
Configuration
Devices)
f
In the AS configuration scheme, Cyclone II devices are configured using
a serial configuration device. These configuration devices are low-cost
devices with non-volatile memory that feature a simple, four-pin
interface and a small form factor. These features make serial
configuration devices an ideal low-cost configuration solution.
For more information on serial configuration devices, see the Serial
Configuration Devices Data Sheet in the Configuration Handbook.
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Cyclone II devices read
configuration data via the serial interface, decompress data if necessary,
and configure their SRAM cells. The FPGA controls the configuration
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Configuring Cyclone II Devices
interface in the AS configuration scheme, while the external host (e.g., the
configuration device or microprocessor) controls the interface in the PS
configuration scheme.
1
The Cyclone II decompression feature is available when
configuring your Cyclone II device using AS mode.
Table 4–4 shows the MSEL pin settings when using the AS configuration
scheme.
Table 4–4. Cyclone II Configuration Schemes
Configuration Scheme
MSEL1
MSEL0
AS (20 MHz) (1)
0
0
Fast AS (40 MHz) (1)
1
0
Note to Table 4–4:
(1)
The EPCS16 and EPCS64 supported a DCLK up to 40 MHz. Other EPCS devices
support a DCLK up to 20 MHz. See the Serial Configuration Devices Data Sheet for
more information.
Single Device AS Configuration
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an activelow chip select (nCS). This four-pin interface connects to Cyclone II
device pins, as shown in Figure 4–3.
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June 2004
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Active Serial Configuration (Serial Configuration Devices)
Figure 4–3. Single Device AS Configuration
VCC (1)
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Serial Configuration
Device
10 kΩ
Cyclone II FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
N.C. (4)
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
MSEL1 (3)
ASDO
MSEL0 (3)
ASDI
(2)
VCC
GND
Notes to Figure 4–3:
(1)
(2)
(3)
(4)
Connect the pull-up resistors to a 3.3-V supply.
Cyclone II device uses the ASDO to ASDI path to control the configuration device.
If your design uses an EPCS4 or an EPCS1 device, set the MSEL[1..0] pins to 00.
See Table 4–4 for more details.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not
feed another device’s nCE pin.
Upon power-up, the Cyclone II device goes through a POR. During POR,
the device will reset, hold nSTATUS and CONF_DONE low, and tri-state all
user I/O pins. After POR, which typically lasts 100 ms, the Cyclone II
device releases nSTATUS and enters configuration mode when the
external 10-kΩ resistor pulls the nSTATUS pin high. Once the FPGA
successfully exits POR, all user I/O pins continue to be tri-stated.
Cyclone II devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration are available in the DC Characteristics
& Timing Specifications chapter of the Cyclone II Device Handbook.
The configuration cycle consists of the reset, configuration, and
initialization stages.
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Configuring Cyclone II Devices
Reset Stage
When nCONFIG or nSTATUS are low, the device is in reset. After POR, the
Cyclone II device releases nSTATUS. An external 10-kΩ pull-up resistor
pulls the nSTATUS signal high, and the Cyclone II device enters
configuration mode.
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
Configuration Stage
The serial clock (DCLK) generated by the Cyclone II device controls the
entire configuration cycle and provides the timing for the serial interface.
Cyclone II devices use an internal oscillator to generate DCLK. Using the
MSEL[] pins, you can select either a 20- or 40-MHz oscillator. Although
you can select either 20- or 40-MHz oscillator when designing with
EPCS16 and EPCS64 serial configuration devices, the 40-MHz oscillator
provides faster configuration times.
1
Only the EPCS16 and EPCS64 configuration devices support a
DCLK up to 40 MHz. Other serial configuration devices support
a DCLK up to 20 MHz. See the Serial Configuration Devices Data
Sheet for more information.
Table 4–5 shows the AS DCLK output frequencies.
Table 4–5. AS DCLK Output Frequency
Oscillator Selected
Note (1)
Minimum
Typical
Maximum
Units
40 MHz (2)
20
26
40
MHz
20 MHz
10
13
20
MHz
Notes to Table 4–5:
(1)
(2)
These values are preliminary.
The EPCS16 and EPCS64 devices support a DCLK clock up to 40 MHz. Other serial
configuration devices support a DCLK clock up to 20 MHz. See the Serial
Configuration Devices Data Sheet for more information.
The serial configuration device latches input/control signals on the rising
edge of DCLK and drives out configuration data on the falling edge.
Cyclone II devices drive out control signals on the falling edge of DCLK
and latch configuration data on the rising edge of DCLK.
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June 2004
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Active Serial Configuration (Serial Configuration Devices)
In configuration mode, the Cyclone II device enables the serial
configuration device by driving its nCSO output pin low, which connects
to the chip select (nCS) pin of the configuration device. The Cyclone II
device uses the serial clock (DCLK) and serial data output (ASDO) pins to
send operation commands and/or read address signals to the serial
configuration device. The configuration device then provides data on its
serial data output (DATA) pin, which connects to the DATA0 input of the
Cyclone II device.
After the Cyclone II device receives all the configuration bits, it releases
the open-drain CONF_DONE pin, which is then pulled high by an external
10-kΩ resistor. Also, the Cyclone II device stops driving the DCLK signal.
Initialization begins only after the CONF_DONE signal reaches a logic high
level. All AS configuration pins (DATA0, DCLK, nCSO, and ASDO) have
weak internal pull-up resistors which are always active. Therefore, after
configuration, these pins will be driven high.
Initialization Stage
In Cyclone II devices, the initialization clock source is either the
Cyclone II 10-MHz (typical) internal oscillator (separate from the AS
internal oscillator) or the optional CLKUSR pin. The internal oscillator is
the default clock source for initialization. If the internal oscillator is used,
the Cyclone II device will provide itself with enough clock cycles for
proper initialization. The advantage of using the internal oscillator is you
do not need to send additional clock cycles from an external source to the
CLKUSR pin during the initialization stage. Additionally, you can use the
CLKUSR pin as a user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSR pin option. Using the CLKUSR pin allows you to control when
your device enters user mode. The device can be delayed from entering
user mode for an indefinite amount of time. When you enable the User
Supplied Start-Up Clock option, the CLKUSR pin is the initialization
clock source. Supplying a clock on CLKUSR will not affect the
configuration process. After all configuration data has been accepted and
CONF_DONE goes high, Cyclone II devices require 136 clock cycles to
initialize properly and support a CLKUSR fMAX of 100 MHz.
Cyclone II devices offer an optional INIT_DONE pin which signals the
end of initialization and the start of user mode with a low-to-high
transition. The Enable INIT_DONE output option is available in the
Quartus II software from the General tab of the Device & Pin Options
window. If you use the INIT_DONE pin, an external 10-kΩ pull-up
resistor is required to pull the signal high when nCONFIG is low and
during the beginning of configuration. Once the optional bit to enable
INIT_DONE is programmed into the device (during the first frame of
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Configuring Cyclone II Devices
configuration data), the INIT_DONE pin will go low. When initialization
is complete, the INIT_DONE pin will be released and pulled high. This
low-to-high transition signals that the FPGA has entered user mode. If
you do not use the INIT_DONE pin, the initialization period will be
complete after CONF_DONE goes high and 136 clock cycles are sent to the
CLKUSR pin or after the time tCF2UM (see Table 4–8) if the Cyclone II device
uses the internal oscillator.
User Mode
When initialization is complete, the FPGA enters user mode. In user
mode, the user I/O pins will no longer have weak pull-up resistors and
will function as assigned in your design.
When the Cyclone II device is in user mode, you can initiate
reconfiguration by pulling the nCONFIG signal low. The nCONFIG signal
should be low for at least 40 µs. When nCONFIG is pulled low, the
Cyclone II device is reset and enters the reset stage. The Cyclone II device
also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Once nCONFIG returns to a logic high level and nSTATUS is released by
the Cyclone II device, reconfiguration begins.
Error During Configuration
If an error occurs during configuration, the Cyclone II device drives the
nSTATUS signal low to indicate a data frame error, and the CONF_DONE
signal will stay low. If you enable the Auto-restart configuration after
error option in the Quartus II software from the General tab of the Device
& Pin Options dialog box, the Cyclone II device resets the serial
configuration device by pulsing nCSO, releases nSTATUS after a reset
time-out period (about 40 µs), and retries configuration. If the Autorestart configuration after error option is turned off, the external system
must monitor nSTATUS for errors and then pull nCONFIG low for at least
40 µs to restart configuration.
1
f
Altera Corporation
June 2004
If you use the optional CLKUSR pin and the nCONFIG pin is
pulled low to restart configuration during device initialization,
ensure CLKUSR continues to toggle during the time nSTATUS is
low (a maximum of 40 µs).
For more information on configuration issues, see the Debugging
Configuration Problems chapter of the Configuration Handbook and the
FPGA Configuration Troubleshooter on the Altera web site
(www.altera.com).
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Active Serial Configuration (Serial Configuration Devices)
Multiple Device AS Configuration
You can configure multiple Cyclone II devices using a single serial
configuration device. You can cascade multiple Cyclone II devices using
the chip-enable (nCE) and chip-enable-out (nCEO) pins. Connect the nCE
pin of the first device in the chain to ground and connect the nCEO pin to
the nCE pin of the next device in the chain. Use an external 10-kΩ pull-up
resistor to pull the nCEO signal high to its VCCIO level to help the internal
weak pull-up resistor. When the first device captures all of its
configuration data from the bitstream, it transitions its nCEO pin low,
initiating the configuration of the next device in the chain. You can leave
the nCEO pin of the last device unconnected or use it as a user I/O pin
after configuration if the last device in chain is a Cyclone II device.
1
The Quartus II software sets the Cyclone II device nCEO pin as
an output pin driving to ground by default. If the device is in a
chain, and the nCEO pin is connected to the next device’s nCE
pin, you must make sure that the nCEO pin is not used as a user
I/O pin after configuration. The software setting is in the DualPurpose Pins tab of the Device & Pin Options dialog box in
Quartus II software.
The first Cyclone II device in the chain is the configuration master and
controls the configuration of the entire chain. Select the AS configuration
scheme for the first Cyclone II device and the PS configuration scheme for
the remaining Cyclone II devices (configuration slaves). Any other
Altera® device that supports PS configuration can also be part of the chain
as a configuration slave. In a multiple device chain, the nCONFIG,
nSTATUS, CONF_DONE, DCLK, and DATA0 pins of each device in the chain
are connected (see Figure 4–4). Figure 4–4 shows the pin connections for
this setup.
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Configuring Cyclone II Devices
Figure 4–4. Multiple Device AS Configuration
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
VCC (3)
10 kΩ
Serial Configuration
Device
10 kΩ
Cyclone II FPGA
Slave Device
Cyclone II FPGA
Master Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (4)
VCC
GND
VCC
DATA
DATA0
MSEL1 (2)
DATA0
DCLK
DCLK
MSEL0 (2)
DCLK
nCS
nCSO
ASDI
ASDO
MSEL1
MSEL0
GND
GND
Notes to Figure 4–4:
(1)
(2)
(3)
(4)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 or an EPCS1 device, set MSEL[1..0] to 00. See Table 4–4 for more details.
Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEO pin resides in.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
As shown in Figure 4–4, the nSTATUS and CONF_DONE pins on all target
FPGAs are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the FPGAs. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. However, the subsequent devices in the chain keep the
CONF_DONE signal low until they receive their configuration data. When
all the target FPGAs in the chain have received their configuration data
and have released CONF_DONE, the pull-up resistor pulls this signal high,
and all devices simultaneously enter initialization mode.
During initialization, the initialization clock source is either the
Cyclone II 10 MHz (typical) internal oscillator (separate from the AS
internal oscillator) or the optional CLKUSR pin. By default, the internal
oscillator is the clock source for initialization. If the internal oscillator is
used, the Cyclone II device will provide itself with enough clock cycles
for proper initialization. The advantage of using the internal oscillator is
you do not need to send additional clock cycles from an external source
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Active Serial Configuration (Serial Configuration Devices)
to the CLKUSR pin during the initialization stage. You can also make use
of the CLKUSR pin as a user I/O pin, which means you have an additional
user I/O pin.
If you want to delay the initialization of the devices in the chain, you can
use the CLKUSR pin option. The CLKUSR pin allows you to control when
your device enters user mode. This feature also allows you to control the
order of when each device enters user mode by feeding a separate clock
to each device’s CLKUSR pin. By using the CLKUSR pins, you can choose
any device in the multiple device chain to enter user mode first and have
the other devices enter user mode at a later time.
Different device families may require a different number of initialization
clock cycles. Therefore, if your multiple device chain consists of devices
from different families, the devices may enter user mode at a slightly
different time due to the different number of initialization clock cycles
required. However, if the number of initialization clock cycles is similar
across different device families or if the devices are from the same family,
then the devices enter user mode at the same time. See the respective
device family handbook for more information about the number of
initialization clock cycles required.
If an error occurs at any point during configuration, the FPGA with the
error drives the nSTATUS signal low. If you enable the Auto-restart
configuration after error option, the entire chain begins reconfiguration
after a reset time-out period (a maximum of 40 µs). If the Auto-restart
configuration after error option is turned off, a microprocessor or
controller must monitor nSTATUS for errors and then pulse nCONFIG low
to restart configuration. The microprocessor or controller can pulse
nCONFIG if it is under system control rather than tied to VCC.
1
While you can cascade Cyclone II devices, serial configuration
devices cannot be cascaded or chained together.
1
If you use the optional CLKUSR pin and the nCONFIG is pulled
low to restart configuration during device initialization, make
sure the CLKUSR pin continues to toggle while nSTATUS is low
(a maximum of 40 µs).
If the configuration bitstream size exceeds the capacity of a serial
configuration device, you must select a larger configuration device
and/or enable the compression feature. When configuring multiple
devices, the size of the bitstream is the sum of the individual devices'
configuration bitstreams.
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Configuring Cyclone II Devices
Configuring Multiple Cyclone II Devices with the Same Design
Certain designs require you to configure multiple Cyclone II devices with
the same design through a configuration bitstream or SOF. You can do
this through one of two methods, as described in this section. For both
methods, the serial configuration devices cannot be cascaded or chained
together.
Multiple SOFs
In the first method, two copies of the SOF file are stored in the serial
configuration device. Use the first copy to configure the master Cyclone II
device and the second copy to configure all remaining slave devices
concurrently. In this setup, the master Cyclone II device is in AS mode,
and the slave Cyclone II devices are in PS mode (MSEL=01). See
Figure 4–5.
To configure four identical Cyclone II devices with the same SOF file,
connect the three slave devices for concurrent configuration as shown in
Figure 4–5. The nCEO pin from the master device drives the nCE input
pins on all three slave devices. Connect the configuration device’s DATA
and DCLK pins to the Cyclone II device's DATA and DCLK pins in parallel.
During the first configuration cycle, the master device reads its
configuration data from the serial configuration device while holding
nCEO high. After completing its configuration cycle, the master drives
nCE low and transmits the second copy of the configuration data to all
three slave devices, configuring them simultaneously.
The advantage of using the setup in Figure 4–5 is that you can have a
different SOF file for the Cyclone II master device. However, all the
Cyclone II slave devices must be configured with the same SOF file. The
SOF files in this configuration method can be either compressed or
uncompressed.
1
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June 2004
You can still use this method if the master and slave Cyclone II
devices use the same SOF.
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Figure 4–5. Multiple Device AS Configuration When FPGAs Receive the Same Data with Multiple SOFs
Cyclone II Device Slave
nSTATUS
CONF_DONE
VCC (1)
VCC (1)
VCC (1) VCC (3)
nCONFIG
nCE
10 k9
10 k9
10 k9
10 k9
VCC
DATA0
DCLK
N.C. (4)
nCEO
MSEL0
MSEL1
Cyclone II Device Master
Serial
Configuration
Device
Cyclone II Device Slave
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
nCEO
nCE
VCC
Data
DATA0
DCLK
DCLK
MSEL0
nCS
nCSO
MSEL1
ASDI
ASDO
VCC
DATA0
DCLK
N.C. (4)
nCEO
MSEL0
MSEL1
Cyclone II Device Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC
DATA0
DCLK
N.C. (4)
nCEO
MSEL0
MSEL1
Notes to Figure 4–5:
(1)
(2)
(3)
(4)
Connect the pull-up resistors to a 3.3-V supply.
If your design uses an EPCS4 or EPCS1 device, set the MSEL[1..0] pins to 00. See Table 4–4 for more details.
Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEO pin resides in.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
Single SOF
The second method configures both the master and slave Cyclone II
devices with the same SOF. The serial configuration device stores one
copy of the SOF file. This setup is shown in Figure 4–6 where the master
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Configuring Cyclone II Devices
is setup in AS mode, and the slave devices are setup in PS mode
(MSEL=01). You could setup one or more slave devices in the chain and
all the slave devices are setup in the same way as shown in Figure 4–6.
Figure 4–6. Multiple Device AS Configuration When FPGAs Receive the Same Data with a Single SOF
VCC (1)
10 k9
10 k9
VCC (1)
VCC (1)
10 k9
Cyclone II Device Master
Serial
Configuration
Device
Cyclone II Device Slave 1
Cyclone II Device Slave 2
nSTATUS
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
nCEO
N.C. (3)
VCC
Data
DATA0
DCLK
DCLK
MSEL0
nCS
nCSO
MSEL1
ASDI
ASDO
nCE
nCONFIG
nCEO
VCC
DATA0
DCLK
N.C. (3)
MSEL0
MSEL1
nCE
nCEO
VCC
DATA0
DCLK
N.C. (3)
MSEL0
MSEL1
Buffers
Notes to Figure 4–6:
(1)
(2)
(3)
Connect the pull-up resistors to a 3.3-V supply.
If your design uses an EPCS4 or EPCS1 device, set the MSEL[1..0] pins to 00. See Table 4–4 for more details.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
In this setup, all the Cyclone II devices in the chain are connected for
concurrent configuration. This can reduce the AS configuration time
because all the Cyclone II devices are configured in one configuration
cycle. Connect the nCE input pins of all the Cyclone II devices to ground.
You can either leave the nCEO output pins on all the Cyclone II devices
unconnected or use the nCEO output pins as normal user I/O pins. The
DATA and DCLK pins are connected in parallel to all the Cyclone II
devices.
You should put a buffer before the DATA and DCLK output from the
master Cyclone II device to avoid signal strength and signal integrity
issues. The buffer should not significantly change the DATA-to-DCLK
relationships or delay them with respect to other AS signals (ASDI and
nCS). Also, the buffer should only drive the slave Cyclone II devices, so
that the timing between the master Cyclone II device and serial
configuration device is unaffected.
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Active Serial Configuration (Serial Configuration Devices)
This configuration method supports both compressed and uncompressed
SOFs. Therefore, if the configuration bitstream size exceeds the capacity
of a serial configuration device, you can enable the compression feature
in the SOF file used or you can select a larger serial configuration device.
Estimating AS Configuration Time
The AS configuration time is the time it takes to transfer data from the
serial configuration device to the Cyclone II device. The Cyclone II DCLK
output (generated from an internal oscillator) clocks this serial interface.
As listed in Table 4–5, if you are using the 40-MHz oscillator, the DCLK
minimum frequency is 20 MHz (50 ns). Therefore, the maximum
configuration time estimate for an EP2C5 device (1,223,980 bits of
uncompressed data) is:
RBF size × (maximum DCLK period / 1 bit per DCLK cycle) =
estimated maximum configuration time
1,223,980 bits × (50 ns / 1 bit) = 61.2 ms
To estimate the typical configuration time, use the typical DCLK period
listed in Table 4–5. With a typical DCLK period of 38.46 ns, the typical
configuration time is 47.1 ms. Enabling compression reduces the amount
of configuration data that is transmitted to the Cyclone II device, which
also reduces configuration time. On average, compression reduces
configuration time by 50%.
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based
devices. You can program these devices in-system using the
USB-Blaster™ or ByteBlaster™ II download cable. Alternatively, you can
program them using the Altera Programming Unit (APU), supported
third-party programmers, or a microprocessor with the SRunner
software driver.
You can use the AS programming interface to program serial
configuration devices in-system. During in-system programming, the
download cable disables FPGA access to the AS interface by driving the
nCE pin high. Cyclone II devices are also held in reset by pulling the
nCONFIG signal low. After programming is complete, the download
cable releases the nCE and nCONFIG signals, allowing the pull-down and
pull-up resistor to drive GND and VCC, respectively. Figure 4–7 shows
the download cable connections to the serial configuration device.
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Configuring Cyclone II Devices
f
For more information on the USB-Blaster download cable, see the USBBlaster USB Port Download Cable Data Sheet. For more information on the
ByteBlaster II cable, see the ByteBlaster II Download Cable Data Sheet.
Figure 4–7. In-System Programming of Serial Configuration Devices
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Cyclone II FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
nCEO
N.C. (2)
nCONFIG
nCE
10 kΩ
DATA
DATA0
DCLK
DCLK
nCS
nCSO
(4) MSEL1
ASDI
ASDO
(4) MSEL0
VCC
GND
Pin 1
VCC (3)
ByteBlaster II or USB Blaster
10-Pin Male Header
Notes to Figure 4–7:
(1)
(2)
(3)
(4)
Connect these pull-up resistors to 3.3-V supply.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
Power up the ByteBlaster II or USB Blaster cable’s VCC with a 3.3-V supply.
If using an EPCS4 or an EPCS1 device, set the MSEL[1..0] pins to 00. See Table 4–4 for more details.
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Active Serial Configuration (Serial Configuration Devices)
You can use the Quartus II software with the APU and the appropriate
configuration device programming adapter to program serial
configuration devices. All serial configuration devices are offered in an
8-pin or 16-pin small outline integrated circuit (SOIC) package and can be
programmed using the PLMSEPC-8 adapter.
Altera programming hardware (APU) or other third-party programming
hardware can be used to program blank serial configuration devices
before they are mounted onto PCBs. Alternatively, you can use an onboard microprocessor to program the serial configuration device on the
PCB using C-based software drivers provided by Altera (i.e., the SRunner
software driver).
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming,
which can be easily customized to fit in different embedded systems.
SRunner can read a Raw Programming Data File (.rpd) and write to the
serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming
time when using the Quartus II Programmer.
f
For more information about SRunner, see the SRunner: An Embedded
Solution for EPCS Programming White Paper and the source code on the
Altera web site at www.altera.com. For more information on
programming serial configuration devices, see the Serial Configuration
Devices Data Sheet in the Configuration Handbook.
Figure 4–8 shows the timing waveform for the AS configuration scheme
using a serial configuration device.
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Configuring Cyclone II Devices
Figure 4–8. AS Configuration Timing
tPOR
nCONFIG
nSTATUS
CONF_DONE
nCSO
tCL
DCLK
tCH
tH
ASDO
Read Address
tSU
bit N
DATA0
bit N − 1
bit 1
bit 0
136 Cycles
INIT_DONE
User Mode
User I/O
PS Configuration
You can use an Altera configuration device, a download cable, or an
intelligent host, such as a MAX® II device or microprocessor to configure
a Cyclone II device with the PS scheme. In the PS scheme, an external host
(configuration device, MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is input to the target
Cyclone II devices via the DATA0 pin at each rising edge of DCLK.
1
The Cyclone II decompression feature is fully available when
configuring your Cyclone II device using PS mode.
Table 4–6 shows the MSEL pin settings when using the PS configuration
scheme.
Table 4–6. Cyclone II MSEL Pin Settings for PS Configuration Schemes
Configuration Scheme
PS
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MSEL1
MSEL0
0
1
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PS Configuration
Single Device PS Configuration Using a MAX II Device as an
External Host
In the PS configuration scheme, you can use a MAX II device as an
intelligent host that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Cyclone II device.
Configuration data can be stored in RBF, HEX, or TTF format. Figure 4–9
shows the configuration interface connections between the Cyclone II
device and a MAX II device for single device configuration.
Figure 4–9. Single Device PS Configuration Using an External Host
Memory
ADDR
VCC. (1) VCC. (1)
DATA0
10 k Ω
VCC
Cyclone II Device
10 k Ω
CONF_DONE
nSTATUS
MSEL0
MSEL1
nCE
External Host
(MAX II Device or
Microprocessor)
GND
GND
nCEO
N.C. (2)
DATA0
nCONFIG
DCLK
Notes to Figure 4–9:
(1)
(2)
Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
Upon power-up, the Cyclone II device goes through a POR, which lasts
approximately 100 ms. During POR, the device will reset, hold nSTATUS
low, and tri-state all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins continue to be tri-stated.
f
The value of the weak pull-up resistors on the I/O pins that are on
beforeand during configuration can be found in the Cyclone II Device
Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization.
Reset Stage
While the Cyclone II device’s nCONFIG or nSTATUS pins are low, the
device is in reset. To initiate configuration, the MAX II device must
transition the Cyclone II nCONFIG pin from low to high.
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Configuring Cyclone II Devices
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
When Cyclone II nCONFIG pin transitions high, the Cyclone II device
comes out of reset and releases the open-drain nSTATUS pin, which is
then pulled high by an external 10-kΩ pull-up resistor. Once nSTATUS is
released, the FPGA is ready to receive configuration data and the MAX II
device can start the configuration at any time.
Configuration Stage
After the Cyclone II device’s nSTATUS pin transitions high, the MAX II
device should send the configuration data on the DATA0 pin one bit at a
time. If you are using configuration data in RBF, HEX, or TTF format,
send the least significant bit (LSB) of each data byte first. For example, if
the RBF contains the byte sequence 02 1B EE 01 FA, you should transmit
the serial bitstream 0100-0000 1101-1000 0111-0111 1000-0000
0101-1111 to the device first.
The Cyclone II device receives configuration data on its DATA0 pin and
the clock on the DCLK pin. Data is latched into the FPGA on the rising
edge of DCLK. Data is continuously clocked into the target device until the
CONF_DONE pin transitions high. After the Cyclone II device receives all
the configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
The configuration clock (DCLK) speed must be below the specified system
frequency (see Table 4–7) to ensure correct configuration. No maximum
DCLK period exists, which means you can pause configuration by halting
DCLK for an indefinite amount of time.
Initialization Stage
In Cyclone II devices, the initialization clock source is either the
Cyclone II internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. The internal oscillator is the default clock source for initialization. If
you use the internal oscillator, the Cyclone II device will make sure to
provide enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. You do not need to provide additional clock cycles externally
during the initialization stage. Driving DCLK back to the device after
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PS Configuration
configuration is complete does not affect device operation. Additionally,
if you use the internal oscillator as the clock source, you can use the
CLKUSR pin as a user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSR pin. Using the CLKUSR pin allows you to control when your
device enters user mode. You can delay the device from entering user
mode for an indefinite amount of time.
The Enable user-supplied start-up clock (CLKUSR) option can be
turned on in the Quartus II software from the General tab of the Device
& Pin Options dialog box. Supplying a clock on CLKUSR will not affect
the configuration process. After all configuration data has been accepted
and CONF_DONE goes high, Cyclone II devices require 136 clock cycles to
initialize properly and support a CLKUSR fMAX of 100 MHz.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
An optional INIT_DONE pin signals the end of initialization and the start
of user mode with a low-to-high transition. By default, the INIT_DONE
output is disabled. You can enable the INIT_DONE output by turning on
the Enable INIT_DONE output option in the Quartus II software. If you
use the INIT_DONE pin, an external 10-kΩ pull-up resistor pulls the pin
high when nCONFIG is low and during the beginning of configuration.
Once the optional bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin
transitions low. When initialization is complete, the INIT_DONE pin will
be released and pulled high. The MAX II device must be able to detect this
low-to-high transition, which signals the FPGA has entered user mode.
If you want to use the INIT_DONE pin as a user I/O pin, you should wait
for the maximum value of tCD2UM (see Table 4–7) after the CONF_DONE
signal transitions high so to ensure the Cyclone II device has been
initialized properly and is in user mode.
Make sure the MAX II device does not drive the CONF_DONE signal low
during configuration, initialization, and before the device enters user
mode.
User Mode
When initialization is complete, the Cyclone II device enters user mode.
In user mode, the user I/O pins no longer have pull-up resistors and will
function as assigned in your design.
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Configuring Cyclone II Devices
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
which ever is convenient on your PCB. The Cyclone II device DATA0 pin
is not available as a user I/O pin after configuration.
When the FPGA is in user mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 40 µs. When the nCONFIG transitions low, the Cyclone II
device also pulls nSTATUS and CONF_DONE low and tri-states all I/O
pins. Once the nCONFIG pin returns to a logic high level and the
Cyclone II device releases the nSTATUS pin, the MAX II device can begin
reconfiguration.
Error During Configuration
If an error occurs during configuration, the Cyclone II device transitions
its nSTATUS pin low, resetting itself internally. The low signal on the
nSTATUS pin tells the MAX II device that there is an error. If you turn on
the Auto-restart configuration after error option in the Quartus II
software, the Cyclone II device releases nSTATUS after a reset time-out
period (maximum of 40 µs). After nSTATUS is released and pulled high
by a pull-up resistor, the MAX II device can try to reconfigure the target
device without needing to pulse nCONFIG low. If this option is turned off,
the MAX II device must generate a low-to-high transition (with a low
pulse of at least 40 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The MAX II device must monitor
the Cyclone II device's CONF_DONE pin to detect errors and determine
when programming completes. If all configuration data is sent, but
CONF_DONE or INIT_DONE do not transition high, the MAX II device
must reconfigure the target device.
f
For more information on configuration issues, see the Debugging
Configuration Problems chapter of the Configuration Handbook and the
FPGA Configuration Troubleshooter on the Altera web site
(www.altera.com).
Multiple Device PS Configuration Using a MAX II Device as an
External Host
Figure 4–10 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the PS configuration circuit for a single
device, except Cyclone II devices are cascaded for multiple device
configuration.
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PS Configuration
Figure 4–10. Multiple Device PS Configuration Using an External Host
Memory
VCC (1)
ADDR
VCC (1)
VCC
DATA0
10 kΩ
Cyclone II Device 1
10 kΩ
VCC (2)
VCC
10 kΩ Cyclone II Device 2
MSEL1
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
MSEL1
MSEL0
CONF_DONE
GND
nCEO
MSEL0
nSTATUS
GND
nCE
GND
nCEO
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (3)
Notes to Figure 4–10:
(1)
(2)
(3)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the devices and the external host.
Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEO pin resides in.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed another device’s nCE pin.
In multiple device PS configuration, connect the first Cyclone II device’s
nCE pin to GND and connect the nCEO pin to the nCE pin of the next
Cyclone II device in the chain. Use an external 10-kΩ pull-up resistor to
pull the Cyclone II device’s nCEO pin high to its VCCIO level to help the
internal weak pull-up resistor when the nCEO pin feeds next Cyclone II
device's nCE pin. The input to the nCE pin of the last Cyclone II device in
the chain comes from the previous Cyclone II device. After the first device
completes configuration in a multiple device configuration chain, its
nCEO pin transitions low to activate the second device’s nCE pin, which
prompts the second device to begin configuration. The second device in
the chain begins configuration within one clock cycle. Therefore, the
MAX II device begins to transfer data to the next Cyclone II device
without interruption. The nCEO pin is a dual-purpose pin in Cyclone II
devices. You can leave the nCEO pin of the last device unconnected or use
it as a user I/O pin after configuration if the last device in chain is a
Cyclone II device.
1
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The Quartus II software sets the Cyclone II device nCEO pin as a
dedicated output by default. If the nCEO pin feeds the next
device’s nCE pin, you must make sure that the nCEO pin is not
used as a user I/O after configuration. This software setting is in
the Dual-Purpose Pins tab of the Device & Pin Options dialog
box in Quartus II software.
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Configuring Cyclone II Devices
You must connect all other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) to every Cyclone II device in the chain.
The configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. You should buffer the DCLK and DATA
lines for every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are connected, if any Cyclone II
device detects an error, configuration stops for the entire chain and the
entire chain must be reconfigured. For example, if the first Cyclone II
detects an error, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single Cyclone II device detecting an error.
If the Auto-restart configuration after error option is turned on, the
Cyclone II devices release their nSTATUS pins after a reset time-out
period (maximum of 40 µs). After all nSTATUS pins are released and
pulled high, the MAX II device reconfigures the chain without pulsing
nCONFIG low. If the Auto-restart configuration after error option is
turned off, the MAX II device must generate a low-to-high transition
(with a low pulse of at least 40 µs) on nCONFIG to restart the configuration
process.
If you want to delay the initialization of the devices in the chain, you can
use the CLKUSR pin option. The CLKUSR pin allows you to control when
your device enters user mode. This feature also allows you to control the
order of when each device enters user mode by feeding a separate clock
to each device’s CLKUSR pin. By using the CLKUSR pins, you can choose
any device in the multiple device chain to enter user mode first and have
the other devices enter user mode at a later time.
Different device families may require a different number of initialization
clock cycles. Therefore, if your multiple device chain consists of devices
from different families, the devices may enter user mode at a slightly
different time due to the different number of initialization clock cycles
required. However, if the number of initialization clock cycles is similar
across different device families or if the devices are from the same family,
then the devices enter user mode at the same time. See the respective
device family handbook for more information about the number of
initialization clock cycles required.
If your system has multiple Cyclone II devices (in the same density and
package) with the same configuration data, you can configure them in
one configuration cycle by connecting all device’s nCE pins to ground and
connecting all the Cyclone II device’s configuration pins (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) together. You can also use the
nCEO pin as a user I/O pin after configuration. The configuration signals
may require buffering to ensure signal integrity and prevent clock skew
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PS Configuration
problems. Make sure the DCLK and DATA lines are buffered for every
fourth device. All devices will start and complete configuration at the
same time. Figure 4–11 shows multiple device PS configuration when
both Cyclone II devices are receiving the same configuration data.
Figure 4–11. Multiple Device PS Configuration When Both FPGAs Receive the Same Data
Memory
VCC (1)
ADDR
VCC (1)
VCC
DATA0
10 kΩ
10 kΩ
VCC
Cyclone II Device
Cyclone II Device
MSEL1
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device
or Microprocessor)
MSEL1
MSEL0
CONF_DONE
GND
nCEO
GND
nCE
N.C. (3)
GND
MSEL0
nSTATUS
nCEO
GND
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (2)
Notes to Figure 4–11:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the devices and the external host.
The nCEO pins of both devices can be left unconnected or used as user I/O pins when configuring the same
configuration data into multiple devices.
You can use a single configuration chain to configure Cyclone II devices
with other Altera devices. Connect all the Cyclone II device’s and all other
Altera device’s CONF_DONE and nSTATUS pins together so all devices in
the chain complete configuration at the same time or that an error
reported by one device initiates reconfiguration in all devices.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and
the maximum clock frequency. When using a microprocessor or another
intelligent host to control the PS interface, ensure that you meet these
timing requirements.
Figure 4–12 shows the timing waveform for PS configuration for Cyclone
II devices.
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Configuring Cyclone II Devices
Figure 4–12. PS Configuration Timing Waveform
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
DCLK (4)
tDH
Bit 0 Bit 1 Bit 2 Bit 3
DATA
Bit n
(5)
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 4–12:
(1)
(2)
(3)
(4)
(5)
The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS and CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Cyclone II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more
convenient. When using the AS configuration scheme, DCLK is a Cyclone II output pin and should not be driven
externally.
Do not leave the DATA pin floating after configuration. Drive it high or low, whichever is more convenient.
Table 4–7 defines the timing parameters for Cyclone II devices for PS
configuration.
Table 4–7. PS Timing Parameters for Cyclone II Devices
Symbol
Note (1)
Parameter
Minimum
Maximum
Units
tP O R
POR delay
100
ms
tC F 2 C D
nCONFIG low to CONF_DONE low
800
ns
tC F 2 S T 0
nCONFIG low to nSTATUS low
tC F G
nCONFIG low pulse width
40
tS T A T U S
nSTATUS low pulse width
10
tC F 2 S T 1
nCONFIG high to nSTATUS high
tC F 2 C K
nCONFIG high to first rising edge on DCLK
40
µs
tS T 2 C K
nSTATUS high to first rising edge of DCLK
1
µs
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ns
µs
40 (2)
µs
40 (2)
µs
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PS Configuration
Table 4–7. PS Timing Parameters for Cyclone II Devices
Symbol
Note (1)
Parameter
Minimum
Maximum
Units
tD S U
Data setup time before rising edge on DCLK
7
ns
tD H
Data hold time after rising edge on DCLK
0
ns
tC H
DCLK high time
4
ns
tC L
DCLK low time
4
ns
tC L K
DCLK period
10
ns
fM A X
DCLK frequency
tC D 2 U M
CONF_DONE high to user mode (3)
6
100
MHz
20
µs
Notes to Table 4–7:
(1)
(2)
(3)
This information is preliminary.
This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device. If the clock source is CLKUSR, multiply the clock period by 136 for Cyclone II devices to obtain this
value.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in Volume 2 of the
Configuration Handbook.
PS Configuration Using a Microprocessor
In the PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Cyclone II device.
f
All information in the “Single Device PS Configuration Using a MAX II
Device as an External Host” on page 4–22 section is also applicable when
using a microprocessor as an external host. Refer to that section for all
configuration information.
The MicroBlaster™ software driver allows you to configure Altera
FPGAs, including Cyclone II devices, through the ByteBlaster II or
ByteBlasterMV cable in PS mode. The MicroBlaster software driver
supports a RBF programming input file and is targeted for embedded PS
configuration. The source code is developed for the Windows NT
operating system, although you can customize it to run on other
operating systems.
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Configuring Cyclone II Devices
1
f
Since the Cyclone II device can decompress the compressed
configuration data on-the-fly during PS configuration, the
MicroBlaster software can accept a compressed RBF file as its
input file.
For more information on the MicroBlaster software driver, see the
Configuring the MicroBlaster Passive Serial Software Driver White Paper and
source files on the Altera web site at www.altera.com.
If you turn on the Enable user-supplied start-up clock (CLKUSR) option
in the Quartus II software, the Cyclone II devices will not enter user mode
after the MicroBlaster has transmitted all the configuration data in the
RBF file. You need to supply enough initialization clock cycles to CLKUSR
pin to enter user mode.
Single Device PS Configuration Using a Configuration Device
You can use an Altera configuration device (e.g., an EPC2, EPC1, or
enhanced configuration device) to configure Cyclone II devices using a
serial configuration bitstream. Configuration data is stored in the
configuration device. Figure 4–13 shows the configuration interface
connections between the Cyclone II device and a configuration device.
1
f
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June 2004
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
For more information on enhanced configuration devices and flash
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet.
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PS Configuration
Figure 4–13. Single Device PS Configuration Using an Enhanced Configuration
Device
VCC (1)
10 kΩ
Cyclone II FPGA
MSEL0
MSEL1
nCEO
10 kΩ
VCC (1)
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC
VCC (1)
N.C. (4)
nCE
GND
GND
Notes to Figure 4–13:
(1)
(2)
(3)
(4)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device. This pull-up resistor is 10 kΩ.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active, meaning an external pull-up resistor
should not be used on the nINIT_CONF to nCONFIG line. The nINIT_CONF pin
does not need to be connected if its functionality is not used. If nINIT_CONF is not
used, nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not
feed other device’s nCE pin.
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Enhanced Configuration
Devices (EPC4, EPC8, & EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet.
When using enhanced configuration devices or EPC2 devices, you can
connect the Cyclone II nCONFIG pin to the configuration device
nINIT_CONF pin, which allows the INIT_CONF JTAG instruction to
initiate FPGA configuration. You do not need to connect the
nINIT_CONF pin if you are not using it. If nINIT_CONF is not used or not
available (e.g., on EPC1 devices), pull the nCONFIG signal to VCC either
directly or through a resistor. An internal pull-up resistor on the
nINIT_CONF pin is always active in enhanced configuration devices and
EPC2 devices. Therefore, you do not need an external pull-up if nCONFIG
is connected to nINIT_CONF.
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Configuring Cyclone II Devices
Upon power-up, the Cyclone II device goes through a POR. During POR,
the device will reset, hold nSTATUS and CONF_DONE low, and tri-state all
user I/O pins. After POR, which typically lasts 100 ms, the Cyclone II
FPGA releases nSTATUS and enters configuration mode when this signal
is pulled high by the external 10-kΩ resistor. Once the FPGA successfully
exits POR, all user I/O pins continue to be tri-stated. Cyclone II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
The configuration device also goes through a POR delay to allow the
power supply to stabilize. The maximum POR time for EPC2 or EPC1
devices is 200 ms. The POR time for enhanced configuration devices can
be set to 100 ms or 2 ms, depending on the device’s PORSEL pin setting.
If the PORSEL pin is connected to ground, the POR delay is 100 ms. If the
PORSEL pin is connected to VCC, the POR delay is 2 ms. You must power
the Cyclone II device before or during the enhanced configuration device
POR time. During POR, the configuration device transitions its OE pin
low. This low signal delays configuration because the OE pin is connected
to the target device's nSTATUS pin. When the target and configuration
devices complete POR, they both release the nSTATUS to OE line, which
is then pulled high by a pull-up resistor.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization.
Reset Stage
While nCONFIG or nSTATUS is low, the device is in reset. You can delay
configuration by holding the nCONFIG or nSTATUS pin low.
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
When the nCONFIG signal goes high, the device comes out of reset and
releases the nSTATUS pin, which is pulled high by a pull-up resistor.
Enhanced configuration and EPC2 devices have an optional internal pullup resistor on the OE pin. You can turn on this option in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If this internal pull-up resistor is not used, you need to connect an
external 10-kΩ pull-up resistor to the OE and nSTATUS line. Once
nSTATUS is released, the FPGA is ready to receive configuration data and
the configuration stage begins.
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PS Configuration
Configuration Stage
When the nSTATUS pin transitions high, the configuration device’s OE
pin also transitions high and the configuration device clocks data out
serially to the FPGA using its internal oscillator. The Cyclone II device
receives configuration data on its DATA0 pin and the clock is received on
the DCLK pin. Data is latched into the FPGA on the rising edge of DCLK.
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a pullup resistor. Since the Cyclone II device’s CONF_DONE pin is tied to the
configuration device's nCS pin, the configuration device is disabled when
CONF_DONE goes high. Enhanced configuration and EPC2 devices have
an optional internal pull-up resistor on the nCS pin. You can turn this
option on in the Quartus II software from the General tab of the Device
& Pin Options dialog box. If you do not use this internal pull-up resistor,
you need to connect an external 10-kΩ pull-up resistor to the nCS and
CONF_DONE line. A low-to-high transition on CONF_DONE indicates
configuration is complete, and the device can begin initialization.
Initialization Stage
In Cyclone II devices, the default initialization clock source is the
Cyclone II internal oscillator (typically 10 MHz). Cyclone II devices can
also use the optional CLKUSR pin. If your design uses the internal
oscillator, the Cyclone II device will supply itself with enough clock
cycles for proper initialization. The advantage of using the internal
oscillator is you do not need to use another device or source to send
additional clock cycles to the CLKUSR pin during the initialization stage.
Additionally, you can use of the CLKUSR pin as a user I/O pin, which
means you have an additional user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSR pin. Using the CLKUSR pin allows you to control when the
Cyclone II device enters user mode. You can delay the Cyclone II devices
from entering user mode for an indefinite amount of time. You can turn
on the Enable user-supplied start-up clock (CLKUSR) option in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data is accepted and CONF_DONE goes
high, Cyclone II devices require 136 clock cycles to properly initialize and
support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user mode with a low-to-high transition. The
Enable INIT_DONE output option is available in the Quartus II software
from the General tab of the Device & Pin Options dialog box. If you use
the INIT_DONE pin, an external 10-kΩ pull-up resistor pulls it high when
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Configuring Cyclone II Devices
nCONFIG is low and during the beginning of configuration. Once the
optional bit to enable INIT_DONE is programmed into the device (during
the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high.
This low-to-high transition signals that the FPGA has entered user mode.
If you do not use the INIT_DONE pin, the initialization period will be
complete after the CONF_DONE signal transitions high and 136 clock
cycles are sent to the CLKUSR pin or after the time tCF2UM (see Table 4–7)
if the Cyclone II device uses the internal oscillator.
After successful configuration, if you intend to synchronize the
initialization of multiple devices that are not in the same configuration
chain, your system must not pull the CONF_DONE signal low to delay
initialization. Instead, use the optional CLKUSR pin to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
User Mode
When initialization is complete, the FPGA enters user mode. In user
mode, the user I/O pins do not have weak pull-up resistors and will
function as assigned in your design. Enhanced configuration devices and
EPC2 devices drive DCLK low and DATA0 high (EPC1 devices drive the
DCLK pin low and tri-state the DATA pin) at the end of configuration.
When the FPGA is in user mode, pull the nCONFIG pin low to begin
reconfiguration. The nCONFIG pin should be low for at least 40 µs. When
nCONFIG transitions low, the Cyclone II device also pulls the nSTATUS
and CONF_DONE pins low and all I/O pins are tri-stated. Since
CONF_DONE transitions low, this will activate the configuration device
since it will see its nCS pin transition low. Once nCONFIG returns to a
logic high level and nSTATUS is released by the FPGA, reconfiguration
begins.
Error During Configuration
If an error occurs during configuration, the Cyclone II drives its nSTATUS
pin low, resetting itself internally. Since the nSTATUS pin is tied to OE,
the configuration device will also be reset. If you turn on the Auto-restart
configuration after error option in the Quartus II software from the
General tab of the Device & Pin Options dialog box, the FPGA
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PS Configuration
automatically initiates reconfiguration if an error occurs. The Cyclone II
device will release its nSTATUS pin after a reset time-out period
(maximum of 40 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 40 µs to restart
configuration. The external system can pulse the nCONFIG pin if the pin
is under system control rather than tied to VCC.
Additionally, if the configuration device sends all of its data and then
detects that the CONF_DONE pin has not transitioned high, it recognizes
that the FPGA has not configured successfully. Enhanced configuration
devices wait for 64 DCLK cycles after the last configuration bit was sent for
the CONF_DONE pin to transition high. EPC2 devices wait for 16 DCLK
cycles. After that, the configuration device pulls its OE pin low, which in
turn drives the target device’s nSTATUS pin low. If you turn on the Autorestart configuration after error option in the Quartus II software, the
target device resets and then releases its nSTATUS pin after a reset timeout period (maximum of 40 µs). When nSTATUS transitions high again,
the configuration device reconfigures the FPGA.
f
For more information on configuration issues, see the Debugging
Configuration Problems chapter of the Configuration Handbook and the
FPGA Configuration Troubleshooter on the Altera web site
(www.altera.com).
Multiple Device PS Configuration Using a Configuration Device
You can use Altera enhanced configuration devices (EPC16, EPC8, and
EPC4 devices) or EPC2 and EPC1 configuration devices to configure
multiple Cyclone II devices in a PS configuration chain.
Figure 4–14 shows how to configure multiple devices with an enhanced
configuration device. This circuit is similar to the configuration device
circuit for a single device, except Cyclone II devices are cascaded for
multiple device configuration.
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Configuring Cyclone II Devices
Figure 4–14. Multiple Device PS Configuration Using an Enhanced Configuration Device
VCC (4)
VCC (1)
10 kΩ
VCC
10 kΩ
MSEL0
MSEL1
MSEL0
MSEL1
(3)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
GND
GND
(5) N.C.
Cyclone II Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
10 kΩ
Enhanced
Configuration
Device
VCC
Cyclone II Device 2
(3)
VCC (1)
nCEO
nCE
nCEO
nCE
GND
Notes to Figure 4–14:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF to nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEO pin resides in.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
1
You cannot cascade enhanced configuration devices (EPC16,
EPC8, and EPC4 devices).
When configuring multiple devices, you must generate the configuration
device's POF from each project's SOF. You can combine multiple SOFs
using the Convert Programming Files window in the Quartus II
software.
f
For more information on how to create configuration files for multiple
device configuration chains, see the Software Settings section in Volume 2
of the Configuration Handbook.
When configuring multiple devices with the PS scheme, connect the first
Cyclone II device's nCE pin to GND and connect its nCEO pin to the nCE
pin of the Cyclone II device in the chain. Use an external 10-kΩ pull-up
resistor to pull the Cyclone II device’s nCEO pin to the VCCIO level when
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it feeds the next device’s nCE pin. After the first device in the chain
completes configuration, its nCEO pin transitions low to activate the
second device's nCE pin, which prompts the second device to begin
configuration. You can leave the nCEO pin of the last device unconnected
or use it as a user I/O pin after configuration. The nCEO pin is a dualpurpose pin in Cyclone II devices.
1
The Quartus II software sets the Cyclone II device nCEO pin as
an output pin driving to ground by default. If the device is in a
chain, and the nCEO pin is connected to the next device’s nCE
pin, you must make sure that the nCEO pin is not used as a user
I/O pin after configuration. This software setting is in the DualPurpose Pins tab of the Device & Pin Options dialog box in
Quartus II software.
Connect all other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0,
and CONF_DONE) to every Cyclone II device in the chain. The
configuration signals may require buffering to ensure signal integrity and
prevent clock skew problems. Buffer the DCLK and DATA lines for every
fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
You should not pull CONF_DONE low to delay initialization. Instead, use
the Quartus II software’s User-Supplied Start-Up Clock option to
synchronize the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain initialize
together since their CONF_DONE pins are tied together.
Since all nSTATUS and CONF_DONE pins are connected, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if there is an error when
configuring the first Cyclone II device, it resets the chain by pulling its
nSTATUS pin low. This low signal drives the OE pin low on the enhanced
configuration device and drives nSTATUS low on all FPGAs, which
causes them to enter a reset state.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUS pins after a reset time-out period (40 µs
maximum). When all the nSTATUS pins are released and pulled high, the
configuration device reconfigures the chain. If the Auto-restart
configuration after error option is turned off, a microprocessor or
controller must monitor the nSTATUS pin for errors and then pulse
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Configuring Cyclone II Devices
nCONFIG low for at least 40 µs to restart configuration. The
microprocessor or controller can only transition the nCONFIG pin low if
the pin is under system control and not tied to VCC.
The enhanced configuration devices support parallel configuration of up
to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode allows
enhanced configuration devices to concurrently configure a chain of
FPGAs. These devices do not have to be the same device family or
density; they can be any combination of Altera FPGAs with different
designs. An individual enhanced configuration device DATA pin is
available for each targeted FPGA. Each DATA line can also feed a chain of
FPGAs. Figure 4–15 shows how to concurrently configure multiple
devices using an enhanced configuration device.
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PS Configuration
Figure 4–15. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
(1) VCC
Cyclone II Device 1
N.C.
VCC
N.C.
VCC
(3)
(3)
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO (4)
nCONFIG
DCLK
DATA0
nCE
OE (3)
MSEL1
MSEL0
GND
10 kΩ
VCC (1)
DATA1
DATA[2..6]
nCS (3)
Cyclone II Device 2
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO (4)
nCONFIG
MSEL1
MSEL0
nINIT_CONF (2)
DATA 7
nCE
GND
GND
Cyclone II Device 8
N.C.
VCC
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO (4)
nCONFIG
MSEL1
MSEL0
nCE
GND
GND
Notes to Table 4–15:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF to nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
The Quartus II software only allows you to set n to 1, 2, 4, or 8. However,
you can use these modes to configure any number of devices from 1 to 8.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
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Configuring Cyclone II Devices
DATA3, you can leave the corresponding bit 3 line blank in the Quartus II
software. On the printed circuit board (PCB), leave the DATA3 line from
the enhanced configuration device unconnected. Use the Quartus II
Convert Programming Files window (Tools menu) setup for this scheme.
You can also connect two FPGAs to one of the configuration device’s
DATA pins while the other DATA pins drive one device each. For example,
you could use the 2-bit PS mode to drive two FPGAs with DATA bit 0 (two
EP2C5 devices) and the third device (an EP2C8 device) with DATA bit 1.
In this example, the memory space required for DATA bit 0 is the sum of
the SOF file size for the two EP2C5 devices.
1,223,980 bits + 1,223,980 bits = 2,447,960 bits
The memory space required for DATA bit 1 is the SOF file size for on
EP2C8 device (1,983,792 bits). Since the memory space required for DATA
bit 0 is larger than the memory space required for DATA bit 1, the size of
the POF file is 2 × 2,447,960 = 4,895,920.
f
For more information on using n-bit PS modes with enhanced
configuration devices, see the Using Altera Enhanced Configuration Devices
in the Configuration Handbook.
When configuring SRAM-based devices using n-bit PS modes, use
Table 4–8 to select the appropriate configuration mode for the fastest
configuration times.
Table 4–8. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 4–8:
(1)
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June 2004
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
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PS Configuration
If your design has multiple Cyclone II devices of the same density and
package that contain the same configuration data, connect the nCE inputs
to GND and leave the nCEO pins floating. You can also use the nCEO pin
as a user I/O pin. Connect the configuration device nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE pins to each Cyclone II device in the
chain. The configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Make sure that the DCLK and
DATA lines are buffered for every fourth device. All devices will start and
complete configuration at the same time. Figure 4–16 shows multiple
device PS configuration when the Cyclone II devices are receiving the
same configuration data.
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Configuring Cyclone II Devices
Figure 4–16. Multiple Device PS Configuration Using an Enhanced Configuration Device When FPGAs
Receive the Same Data
(1) VCC
Cyclone II Device 1
(4) N.C.
VCC
nCEO
MSEL1
MSEL0
GND
(4) N.C.
VCC
MSEL1
MSEL0
(3)
(3)
10 kΩ
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
Enhanced
Configuration
Device
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
nCE
Cyclone II Device 2
nCEO
10 kΩ
VCC (1)
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
GND
Cyclone II Device 8
(4) N.C.
VCC
nCEO
MSEL1
MSEL0
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
Notes to Figure 4–16:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF to nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
You can cascade several EPC2 or EPC1 devices to configure multiple
Cyclone II devices. The first configuration device in the chain is the
master configuration device, and the subsequent devices are the slave
devices. The master configuration device sends DCLK to the Cyclone II
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devices and to the slave configuration devices. Connect the first
configuration device’s nCS pin to all the Cyclone II device's CONF_DONE
pins, and connect the nCASC pin to the nCS pin of the next configuration
device in the chain. Leave the nCASC pin of the last configuration device
floating. When the master configuration device sends all the data to the
Cyclone II device, the configuration device transitions the nCASC pin low,
which drives nCS on the next configuration device. Because a
configuration device requires less than one clock cycle to activate a
subsequent configuration device, the data stream is uninterrupted.
1
Enhanced configuration devices (EPC16, EPC8, and EPC4
devices) cannot be cascaded.
Since all nSTATUS and CONF_DONE pins are connected, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect the Cyclone II device’s
CONF_DONE pin transitioning high at the end of configuration, it resets
the entire chain by transitioning its OE pin low. This low signal drives the
OE pin low on the slave configuration device(s) and drives nSTATUS low
on all Cyclone II devices, causing them to enter a reset state. This behavior
is similar to the FPGA detecting an error in the configuration data.
Figure 4–17 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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Configuring Cyclone II Devices
Figure 4–17. Multiple Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (4)
VCC (1)
VCC (1)
VCC (1)
10 kΩ
(3) 10 kΩ
VCC
(2)
VCC
Cyclone II Device 2
MSEL0
MSEL1
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
GND
nCEO
nCE
nCEO
10 kΩ (3)
EPC2 or EPC1
Device 1
Cyclone II Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
GND
(5) N.C.
10 kΩ
EPC2 or EPC1
Device 2
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 4–17:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor should not be used on the nINIT_CONF to
nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a
resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
Use an external 10-kΩ pull-up resistor to pull the nCEO pin high to the I/O bank VCCIO level to help the internal
weak pull-up when it feeds next device’s nCE pin.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
When using enhanced configuration devices or EPC2 devices, you can
connect the Cyclone II device's nCONFIG pin to the configuration device’s
nINIT_CONF pin, which allows the INIT_CONF JTAG instruction to
initiate FPGA configuration. You do not need to connect the
nINIT_CONF pin if it is not used. If the nINIT_CONF pin is not used or
not available (e.g., on EPC1 devices), pull the nCONFIG pin to VCC levels
either directly or through a resistor. An internal pull-up resistor on the
nINIT_CONF pin is always active in the enhanced configuration devices
and the EPC2 devices. Therefore, do not use an external pull-up resistor
if you connect the nCONFIG pin to nINIT_CONF. If you use multiple
EPC2 devices to configure a Cyclone II device(s), only connect the first
EPC2 device’s nINIT_CONF pin to the device's nCONFIG pin.
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You can use a single configuration chain to configure Cyclone II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, connect all the Cyclone II device
CONF_DONE pins and connect all Cyclone II device nSTATUS pins
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook.
During PS configuration, the design must meet the setup and hold timing
parameters and maximum DCLK frequency. The enhanced configuration
and EPC2 devices are designed to meet these interface timing
specifications.
Figure 4–18 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 4–18. Cyclone II PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
tDSU
tCL
D0
D1
tDH
tOEZX
DATA
tCH
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
t CD2UM (1)
Note to Figure 4–18:
(1)
Cyclone II devices enter user mode 136 clock cycles after CONF_DONE goes high. The initialization clock can come
from the Cyclone II internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet in the Configuration Handbook.
f
For more information on device configuration options and how to create
configuration files, see the Software Settings section in Volume 2 of the
Configuration Handbook.
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Configuring Cyclone II Devices
PS Configuration Using a Download Cable
In PS configuration, an intelligent host (e.g., a PC) can use a download
cable to transfer data from a storage device to the Cyclone II device. You
can use the Altera USB-Blaster universal serial bus (USB) port download
cable, MasterBlaster™ serial/USB communications cable, ByteBlaster II
parallel port download cable, or the ByteBlasterMV™ parallel port as a
download cable.
Upon power up, the Cyclone II device goes through POR, which lasts
approximately 100 ms. During POR, the device will reset, hold nSTATUS
low, and tri-state all user I/O pins. Once the FPGA successfully exits
POR, the nSTATUS pin is released and all user I/O pins continue to be tristated.
f
The value of the weak pull-up resistors on the I/O pins that are on
beforeand during configuration can be found in the Cyclone II Device
Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While the nCONFIG or nSTATUS pins are low, the device is
in reset. To initiate configuration in this scheme, the download cable
generates a low-to-high transition on the nCONFIG pin.
1
Make sure VCCINT and VCCIO for the banks where the
configuration and JTAG pins reside are powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG transitions high, the Cyclone II device comes out of reset
and begins configuration. The Cyclone II device releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up
resistor. Once nSTATUS transitions high, the Cyclone II device is ready to
receive configuration data. The programming hardware or download
cable then transmits the configuration data one bit at a time to the
device’s DATA0 pin. The configuration data is clocked into the target
device until CONF_DONE goes high.
When using a download cable, you cannot use the Auto-restart
configuration after error option. You must manually restart
configuration in the Quartus II software when an error occurs.
Additionally, you cannot use the Enable user-supplied start-up clock
(CLKUSR) option when programming the FPGA using the Quartus II
programmer and download cable. This option is disabled in the SOF.
Therefore, if you turn on the CLKUSR option, you do not need to provide
a clock on CLKUSR when you are configuring the FPGA with the
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Configuration Handbook, Volume 1
PS Configuration
Quartus II programmer and a download cable. Figure 4–19 shows the PS
configuration for Cyclone II devices using a USB-Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cable.
Figure 4–19. PS Configuration Using a USB-Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV Cable
VCC (1)
(2)
VCC (1)
10 kΩ
(2)
10 kΩ
VCC (1)
VCC (1)
10 kΩ
Cyclone II Device
VCC
CONF_DONE
nSTATUS
10 kΩ
MSEL0
MSEL1
nCE
nCEO
N.C. (4)
GND
DCLK
DATA0
nCONFIG
VCC (1)
10 kΩ
USB-Blaster, ByteBlaster II,
MasterBlaster,
or ByteBlasterMV
10-Pin Male Header
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 4–19:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCE when it is used for AS
programming, otherwise it is a no connect.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
You can use a download cable to configure multiple Cyclone II devices by
connecting each device’s nCEO pin to the subsequent device’s nCE pin.
Connect the first Cyclone II device's nCE pin to GND and connect its
nCEO pin to the nCE pin of the next device in the chain. Use an external
10-kΩ pull-up resistor to pull the nCEO pin high to VCCIO when it feeds
next device’s nCE pin. Connect all other configuration pins (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) on every device in the chain
together. Because all CONF_DONE pins are connected, all devices in the
chain initialize and enter user mode at the same time.
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Configuring Cyclone II Devices
In addition, because the nSTATUS pins are connected, all the Cyclone II
devices in the chain stop configuration if any device detects an error. If
this happens, you must manually restart configuration in the Quartus II
software.
Figure 4–20 shows how to configure multiple Cyclone II devices with a
download cable.
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June 2004
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PS Configuration
Figure 4–20. Multiple Device PS Configuration Using a USB-Blaster, MasterBlaster, ByteBlaster II or
ByteBlasterMV Cable
VCC (1)
VCC (1)
VCC (1)
10 kΩ
10 kΩ
(2)
VCC
VCC (1)
Pin 1
CONF_DONE
nSTATUS
DCLK
MSEL0
USB-Blaster, ByteBlaster II,
MasterBlaster, or ByteBlasterMV
10-Pin Male Header
(Passive Serial Mode)
10 kΩ
Cyclone II FPGA 1
VCC (4)
10 kΩ
10 kΩ
(2)
VCC (2)
MSEL1
VCC (1)
GND
VIO (3)
nCE
10 kΩ
GND
DATA0
nCONFIG
VCC
GND
Cyclone II FPGA 2
MSEL0
MSEL1
GND
nCEO
CONF_DONE
nSTATUS
DCLK
nCEO
nCE
N.C. (5)
DATA0
nCONFIG
Notes to Figure 4–20:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for AS programming, otherwise it is a no connect.
Connect the pull-up resistor to the VCCIO supply voltage of I/O bank that the nCEO pin resides in.
The nCEO pin of the last device in chain can be left unconnected or used as a user I/O pin.
If you are using a download cable to configure Cyclone II devices on a
PCB that also has configuration devices, you should electrically isolate
the configuration devices from the target Cyclone II devices and cable.
One way to isolate the configuration device is to add logic, such as a
multiplexer, that can select between the configuration device and the
cable. The multiplexer should allow bidirectional transfers on the
nSTATUS and CONF_DONE signals. Additionally, you can add switches to
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Configuring Cyclone II Devices
the five common signals (nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE) between the cable and the configuration device. You can
also remove the configuration device from the board when configuring
the FPGA with the cable. Figure 4–21 shows a combination of a
configuration device and a download cable to configure an FPGA.
Figure 4–21. PS Configuration with a Download Cable & Configuration Device Circuit
VCC (1)
VCC
VCC (1)
10 kΩ
(5)
10 kΩ
(5)
Cyclone II FPGA
VCC (1)
10 kΩ
(4)
MSEL0
MSEL1
USB Blaster, ByteBlaster II,
MasterBlaster, or ByteBlasterMV
10-Pin Male Header
(Passive Serial Mode)
CONF_DONE
nSTATUS
DCLK
Pin 1
VCC
GND
VIO (2)
nCE
nCEO
N.C. (6)
GND
DATA0
nCONFIG
(3)
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (5)
nCS (5)
nINIT_CONF (4)
(3)
Notes to Figure 4–21:
(1)
(2)
(3)
(4)
(5)
(6)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCE when it is used for AS
programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to a
Cyclone II device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor should not be used on the nINIT_CONF to
nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a
resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
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Configuration Handbook, Volume 1
JTAG Configuration
f
For more information on how to use the USB-Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following documents:
■
■
■
■
JTAG
Configuration
f
USB-Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture allows
you to test components on PCBs with tight lead spacing. The BST
architecture can test pin connections without using physical test probes
and capture functional data while a device is operating normally. The
JTAG circuitry can also be used to shift configuration data into the device.
The Quartus II software automatically generates SOF files that can be
used for JTAG configuration with a download cable in the Quartus II
programmer.
For more information on JTAG boundary-scan testing, see the following
documents:
■
■
IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices
chapter in Volume 2 of the Cyclone II Device Handbook
Jam Programming & Testing Language Specification
Cyclone II devices are designed such that JTAG instructions have
precedence over any device configuration modes. This means that JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Cyclone II devices during PS configuration, PS configuration will
terminate and JTAG configuration will begin. If the Cyclone II MSEL pins
are set to AS or fast AS mode, the Cyclone II device will not output a DCLK
signal when JTAG configuration takes place.
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You cannot use the Cyclone II decompression feature if you are
configuring your Cyclone II device when using JTAG-based
configuration.
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June 2004
Configuring Cyclone II Devices
A device operating in JTAG mode uses the TDI, TDO, TMS, and TCK pins.
The TCK pin has a weak internal pull-down resistor while the other JTAG
input pins, TDI and TMS, have weak internal pull-up resistors. All user
I/O pins are tri-stated during JTAG configuration. Table 4–9 explains
each JTAG pin's function.
Table 4–9. Dedicated JTAG Pins
Pin Name
Description
TDI
Test data input Serial input pin for instructions as well as test
and programming data. Data is shifted in on
the rising edge of TCK.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to VC C .
TDO
Test data
output
Serial data output pin for instructions as well as
test and programming data. Data is shifted out
on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
leaving this pin unconnected.
TMS
Test mode
select
Input pin that provides the control signal to
determine the transitions of the TAP controller
state machine. Transitions within the state
machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the
rising edge of TCK. TMS is evaluated on the
rising edge of TCK.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to VC C .
TCK
Test clock
input
The clock input to the BST circuitry. Some
operations occur at the rising edge, while
others occur at the falling edge.
If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by
connecting this pin to GND.
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June 2004
Pin Type
The TDO output is powered by the VCCIO power supply. If VCCIO
is tied to 3.3-V, both the I/O pins and the JTAG TDO port drive
at 3.3-V levels.
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JTAG Configuration
Single Device JTAG Configuration
During JTAG configuration, you can use the USB-Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV download cable to download data to the
device. Configuring Cyclone II devices through a cable is similar to
programming devices in system. Figure 4–22 shows JTAG configuration
of a single Cyclone II device using a download cable.
Figure 4–22. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
VCC (1)
VCC (1)
VCC (1)
1 kΩ
10 kΩ
Cyclone II Device 1 kΩ
10 kΩ
nCE (4)
TCK
TDO
GND
N.C. (5)
(2)
(2)
(2)
(2)
(2)
nCE
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
DATA0
DCLK
USB-Blaster, ByteBlaster II,
MasterBlaster, or ByteBlasterMV
10-Pin Male Header
(Top View)
TMS
TDI
Pin 1
VCC (1)
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 4–22:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
Connect the nCONFIG and MSEL[1..0] pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect the nCONFIG pin to VCC, and the MSEL[1..0] pins to ground. In addition, pull DCLK
and DATA0 to either high or low, whichever is convenient on your board.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB-Blaster and ByteBlaster II, this pin is connected to nCE when it is used for AS
programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, Cyclone II
devices pass programming data from the TDI pin to the TDO pin through
a single bypass register without being affected internally. This scheme
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Configuring Cyclone II Devices
enables the programming software to program or verify the target device.
Configuration data driven into the target device appears on the TDO pin
one clock cycle later.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the
CONF_DONE pin through the JTAG port. When the Quartus II software
generates a JAM file for a multiple device chain, it contains instructions
so that all the devices in the chain will be initialized at the same time. If
CONF_DONE is not high, the Quartus II software indicates that
configuration has failed. If the CONF_DONE pin transitions high, the
software indicates that configuration was successful. After the
configuration bitstream is transmitted serially via the JTAG TDI port, the
TCK port is clocked an additional 136 cycles to perform Cyclone II device
initialization.
The Enable user-supplied start-up clock (CLKUSR) option has no affect
on the device initialization since this option is disabled in the SOF when
configuring the FPGA in JTAG using the Quartus II programmer and
download cable. Therefore, if you turn on the CLKUSR option, you do not
need to provide a clock on CLKUSR when you are configuring the FPGA
with the Quartus II programmer and a download cable.
Cyclone II devices have dedicated JTAG pins that always function as
JTAG pins. You can perform JTAG testing on Cyclone II devices before,
after, and during configuration. Cyclone II devices support the BYPASS,
IDCODE and SAMPLE instructions during configuration without
interruption. All other JTAG instructions may only be issued by first
interrupting configuration and reprogramming I/O pins using the
CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port. The CONFIG_IO instruction will interrupt configuration. This
instruction allows you to perform board-level testing before configuring
the Cyclone II device or waiting for a configuration device to complete
configuration. If you interrupt configuration, the Cyclone II device must
be reconfigured via JTAG (PULSE_CONFIG instruction) or by pulsing
nCONFIG low after JTAG testing is complete.
f
For more information, see the MorphIO: An I/O Reconfiguration Solution
for Altera White Paper.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Cyclone II devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins will not affect JTAG
operations (other than the usual boundary-scan operation).
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JTAG Configuration
When designing a Cyclone II board for JTAG configuration, use the
guidelines in Table 4–10 for the placement of the dedicated configuration
pins.
Table 4–10. Dedicated Configuration Pin Connections During JTAG
Configuration
Signal
Description
nCE
On all Cyclone II devices in the chain, nCE should be driven
low by connecting it to ground, pulling it low via a resistor, or
driving it by some control circuitry. For devices that are also in
multiple device AS, or PS configuration chains, the nCE pins
should be connected to GND during JTAG configuration or
JTAG configured in the same order as the configuration chain.
nCEO
On all Cyclone II devices in the chain, nCEO can be used as a
user I/O or connected to the nCE of the next device. If nCEO is
connected to the nCE of the next device, the nCEO pin must
be pulled high to VC C I O by an external 10-kΩ pull-up resistor
to help the internal weak pull-up resistor. If the nCEO pin is not
connected to the nCE pin of the next device, you can use it as
a user I/O pin after configuration.
MSEL
These pins must not be left floating. These pins support
whichever non-JTAG configuration is used in production. If
only JTAG configuration is used, you should tie these pins to
ground.
nCONFIG
Driven high by connecting to VC C , pulling up via a resistor, or
driven high by some control circuitry.
nSTATUS
Pull to VCC via a 10-kΩ resistor. When configuring multiple
devices in the same JTAG chain, each nSTATUS pin should
be pulled up to VCC individually. nSTATUS pulling low in the
middle of JTAG configuration indicates that an error has
occurred.
CONF_DONE
Pull to VCC via a 10-kΩ resistor. When configuring multiple
devices in the same JTAG chain, each CONF_DONE pin
should be pulled up to VCC individually. CONF_DONE going
high at the end of JTAG configuration indicates successful
configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more
convenient on your board.
Figure 4–23 shows JTAG configuration of a Cyclone II device with a
microprocessor.
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Configuring Cyclone II Devices
Figure 4–23. JTAG Configuration of a Single Device Using a Microprocessor
Cyclone II FPGA
Memory
nCE (3)
ADDR
DATA
(4)
(2)
(2)
(2)
Microprocessor
nCEO
MSEL1
nCONFIG MSEL0
DATA0
DCLK
TDI
TCK
TDO
TMS
nSTATUS
(2)
(2)
VCC (1)
VCC (1)
10 kΩ
10 kΩ
CONF_DONE
Notes to Figure 4–23:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain.
Connect the nCONFIG and MSEL[1..0] pins to support a non-JTAG
configuration scheme. If only JTAG configuration is used, connect the nCONFIG
pin to VCC, and the MSEL[1..0] pins to ground. In addition, pull DCLK and
DATA0 to either high or low, whichever is convenient on your board.
nCE must be connected to GND or driven low for successful JTAG configuration.
If using an EPCS4 or EPCS1 device, set MSEL[1..0] to 00. See Table 4–4 for more
details.
JTAG Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 4–24 shows multiple device JTAG configuration.
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June 2004
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JTAG Configuration
Figure 4–24. JTAG Configuration of Multiple Devices Using a Download Cable
VCC
USB-Blaster, ByteBlaster II,
MasterBlaster,
or ByteBlasterMV
10-Pin Male Header
(1)
10 kΩ
VCC
1 kΩ
VIO
(3)
(2)
(2)
(2)
(2)
(2)
(5)
nSTATUS
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCEO
nCE (4)
TDI
TMS
TCK
TDO
VCC
(1)
VCC (1)
10 kΩ
Cyclone II FPGA
1 kΩ
VCC
VCC
10 kΩ
VCC
Pin 1
(1)
10 kΩ
nSTATUS
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCEO
nCE (4)
TDI
TMS
TDO
TCK
(1)
VCC
10 kΩ
Cyclone II FPGA
(2)
(2)
(2)
(2)
(2)
(5)
VCC
(1)
10 kΩ
Cyclone II FPGA
nSTATUS
(2)
(2)
(2)
(2)
(2)
(5)
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCEO
nCE (4)
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 4–24:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
Connect the nCONFIG and MSEL[1..0] pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect the nCONFIG pin to VCC, and the MSEL[1..0] pins to ground. In addition, pull DCLK
and DATA0 to either high or low, whichever is convenient on your board.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCE when it is
used for AS programming, otherwise it is a no connect.
nCE must be connected to ground or driven low for successful JTAG configuration.
If using an EPCS4 or EPCS1 device, set MSEL[1..0] to 00. See Table 4–4 for more details.
Connect the nCE pin to GND or pull it low during JTAG configuration. In
multiple device AS and PS configuration chains, connect the first device's
nCE pin to GND and connect its nCEO pin to the nCE pin of the next
device in the chain or you can use it as a user I/O pin after configuration.
After the first device completes configuration in a multiple device
configuration chain, its nCEO pin drives low to activate the second
device's nCE pin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, you
should make sure the nCE pins are connected to GND during JTAG
configuration or that the devices are JTAG configured in the same order
as the configuration chain. As long as the devices are JTAG configured in
the same order as the multiple device configuration chain, the nCEO pin
of the previous device will drive the nCE pin of the next device low when
it has successfully been JTAG configured.
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Configuring Cyclone II Devices
1
The Quartus II software sets the Cyclone II device nCEO pin as
an output pin driving to ground by default. If the nCEO pin
inputs to the next device’s nCE pin, make sure that the nCEO pin
is not used as a user I/O pin after configuration.
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP). Jam STAPL supports programming or
configuration of programmable devices and testing of electronic systems
using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely licensed open
standard. The Jam player provides an interface for manipulating the IEEE
Std. 1149.1 JTAG TAP state machine.
f
For more information on JTAG and Jam STAPL in embedded
environments, see AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the Jam player, go to the Altera web
site (www.altera.com).
Configuring Cyclone II FPGAs with JRunner
JRunner is a software driver that allows you to configure Cyclone II
devices through the ByteBlaster II or ByteBlasterMV cables in JTAG
mode. The programming input file supported is in .rbf format. JRunner
also requires a Chain Description File (.cdf) generated by the Quartus II
software. JRunner is targeted for embedded JTAG configuration. The
source code has been developed for the Windows NT operating system
(OS). You can customize the code to make it run on your embedded
platform.
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June 2004
The RBF file used by the JRunner software driver can not be a
compressed RBF file because JRunner uses JTAG-based
configuration. During JTAG-based configuration, the real-time
decompression feature is not available.
For more information on the JRunner software driver, see JRunner
Software Driver: An Embedded Solution for PLD JTAG Configuration and the
source files on the Altera web site.
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JTAG Configuration
Programming Serial Configuration Devices In-System Using the
JTAG Interface
Cyclone II devices in a single device chain or in a multiple device chain
support in-system programming of a serial configuration device using
the JTAG interface via the serial flash loader design. The board’s
intelligent host or download cable can use the four JTAG pins on the
Cyclone II device to program the serial configuration device in system,
even if the host or download cable cannot access the configuration
device’s configuration pins (DCLK, DATA, ASDI, and nCS pins).
The serial flash loader design is a JTAG-based in-system programming
solution for Altera serial configuration devices. The serial flash loader is
a bridge design for the FPGA that uses its JTAG interface to access the
EPCS JIC (JTAG Indirect Configuration Device Programming) file and
then uses the AS interface to program the EPCS device. Both the JTAG
interface and AS interface are bridged together inside the serial flash
loader design.
In a multiple device chain, you only need to configure the master
Cyclone II device which is controlling the serial configuration device. The
slave devices in the multiple device chain which are configured by the
serial configuration device do not need to be configured when using this
feature. To use this feature successfully, set the MSEL[1..0] pins of the
master Cyclone II device to select the AS configuration scheme or fast AS
configuration scheme (see Table 4–1).
1
The Quartus II software version 4.1 and higher supports serial
configuration device ISP through an FPGA JTAG interface using
a JIC file.
The serial configuration device in-system programming through the
Cyclone II JTAG interface has three stages, which are described in the
following sections.
Loading the Serial Flash Loader Design
The serial flash loader design is a design inside the Cyclone II device that
bridges the JTAG interface and AS interface inside the Cyclone II device
using glue logic.
The intelligent host uses the JTAG interface to configure the master
Cyclone II device with a serial flash loader design. The serial flash loader
design allows the master Cyclone II device to control the access of four
serial configuration device pins, also known as the Active Serial Memory
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Configuring Cyclone II Devices
Interface (ASMI) pins, through the JTAG interface. The ASMI pins are the
serial clock input (DCLK), serial data output (DATA), AS data input (ASDI),
and an active-low chip select (nCS) pins.
If you configure a master Cyclone II device with a serial flash loader
design, the master Cyclone II device can enter user mode even though the
slave devices in the multiple device chain are not being configured. The
master Cyclone II device can enter user mode with a serial flash loader
design even though the CONF_DONE signal is externally held low by the
other slave devices in chain. Figure 4–25 shows the JTAG configuration of
a single Cyclone II device with a serial flash loader design.
Figure 4–25. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
VCC (1)
1 kΩ
VCC (1)
VCC (1)
10 kΩ VCC (1)
10 kΩ
Cyclone II Device
10 kΩ
nCE (4)
GND N.C.
Serial Configuration Device
ASDI
nCS
DCLK
DATA
(2)
(2)
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
ASDO
nCSO
DCLK
DATA0
1 kΩ
TCK
TDO
TMS
TDI
USB Blaster, ByteBlaster II,
MasterBlaster, or
ByteBlasterMV 10-Pin Male
Header (Top View)
Pin 1
VCC
GND
VIO (3)
Serial
Flash
Loader
1 kΩ
GND
GND
Notes to Figure 4–25:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL[1..0] pins should be connected to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL[3..0] to ground. Pull DCLK either high or low,
whichever is convenient on your board.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
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June 2004
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Device Configuration Pins
ISP of Serial Configuration Device
In the second stage, the serial flash loader design in the master Cyclone II
device allows you to write the configuration data for the device chain into
the serial configuration device by using the Cyclone II JTAG interface.
The JTAG interface sends the programming data for the serial
configuration device to the Cyclone II device first. The Cyclone II device
then uses the ASMI pins to transmit the data to the serial configuration
device.
Reconfiguration
After all the configuration data is written into the serial configuration
device successfully, the intelligent host issues the PULSE_NCONFIG JTAG
instruction to initialize the reconfiguration process. During
reconfiguration, the master Cyclone II device will be reset and the serial
flash loader design will no longer exist in the Cyclone II device and the
serial configuration device will configure all the devices in the chain with
your user design.
Device
Configuration
Pins
This section describes the connections and functionality of all the
configuration related pins on the Cyclone II device. Table 4–11 describes
the dedicated configuration pins, which are required to be connected
properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Table 4–11. Dedicated Configuration Pins on the Cyclone II Device (Part 1 of 5)
Pin Name
User
Mode
MSEL[1..0] N/A
Configuration
Scheme
All
Pin Type
Input
Description
This pin is a two-bit configuration input that sets the
Cyclone II device configuration scheme. See
Table 4–1 for the appropriate settings.
You must connect these pins to VC C I O or ground.
nCONFIG
N/A
All
Input
This pin is a configuration control input. If this pin is
pulled low during user mode, the FPGA will lose its
configuration data, enter a reset state, and tri-state all
I/O pins. Transitioning this pin high initiates a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, you can
connect the nCONFIG pin directly to VC C or to the
configuration device's nINIT_CONF pin.
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Configuring Cyclone II Devices
Table 4–11. Dedicated Configuration Pins on the Cyclone II Device (Part 2 of 5)
Pin Name
nSTATUS
User
Mode
N/A
Configuration
Scheme
All
Pin Type
Bidirectional
open-drain
Description
The Cyclone II device drives nSTATUS low
immediately after power-up and releases it after the
POR time.
This pin provides a status output and input for the
Cyclone II device. If the Cyclone II device detects an
error during configuration, it drives the nSTATUS pin
low to stop configuration. If an external source (e.g.,
another Cyclone II device) drives the nSTATUS pin
low during configuration or initialization, the target
device enters an error state.
Driving nSTATUS low after configuration and
initialization does not affect the configured device. If
your design uses a configuration device, driving
nSTATUS low causes the configuration device to
attempt to configure the FPGA, but since the FPGA
ignores transitions on nSTATUS in user mode, the
FPGA will not reconfigure. To initiate a
reconfiguration, pull the nCONFIG pin low.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins are connected to the
Cyclone II device’s nSTATUS and CONF_DONE pins,
respectively, and have optional internal
programmable pull-up resistors. If you use these
internal pull-up resistors on the enhanced
configuration device, do not use external 10-kΩ pullup resistors on these pins. When using EPC2
devices, you should only use external 10-kΩ pull-up
resistors.
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June 2004
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Device Configuration Pins
Table 4–11. Dedicated Configuration Pins on the Cyclone II Device (Part 3 of 5)
Pin Name
CONF_DONE
User
Mode
N/A
Configuration
Scheme
All
Pin Type
Bidirectional
open-drain
Description
This pin is a status output and input.
The target Cyclone II device drives the CONF_DONE
pin low before and during configuration. Once the
Cyclone II device receives all the configuration data
without error and the initialization cycle starts, it
releases CONF_DONE. Driving CONF_DONE low
during user mode does not affect the configured
device. Do not drive CONF_DONE low before the
device enters user mode.
After the Cyclone II device receives all the data, the
CONF_DONE pin transitions high, and the device
initializes and enters user mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins are connected to the
Cyclone II device’s nSTATUS and CONF_DONE pins,
respectively, and have optional internal
programmable pull-up resistors. If internal pull-up
resistors on the enhanced configuration device are
used, external 10-kΩ pull-up resistors should not be
used on these pins. When using EPC2 devices, you
should only use external 10-kΩ pull-up resistors.
nCE
N/A
All
Input
This pin is an active-low chip enable. The nCE pin
activates the device with a low signal to allow
configuration. The nCE pin must be held low during
configuration, initialization, and user mode. In single
device configuration, it should be tied low. In multiple
device configuration, nCE of the first device is tied low
while its nCEO pin is connected to nCE of the next
device in the chain.
The nCE pin must also be held low for successful
JTAG programming of the FPGA.
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Configuring Cyclone II Devices
Table 4–11. Dedicated Configuration Pins on the Cyclone II Device (Part 4 of 5)
Pin Name
nCEO
User
Mode
N/A if
option
is on.
I/O if
option
is off.
Configuration
Scheme
All
Pin Type
Output
Description
This pin is an output that drives low when device
configuration is complete. In single device
configuration, you can leave this pin floating or use it
as a user I/O pin after configuration. In multiple
device configuration, this pin inputs the next device's
nCE pin. The nCEO of the last device in the chain can
be left floating or used as a user I/O pin after
configuration.
If you use the nCEO pin to feed next device’s nCE pin,
use an external 10-kΩ pull-up resistor to pull the
nCEO pin high to the VC C I O voltage of its I/O bank to
help the internal weak pull-up resistor.
Use the Quartus II software to make this pin a user
I/O pin.
ASDO
nCSO
N/A in AS
AS
mode
I/O in
PS and
JTAG
mode
Output
N/A in AS
AS
mode
I/O in
PS and
JTAG
mode
Output
Altera Corporation
June 2004
This pin sends a control signal from the Cyclone II
device to the serial configuration device in AS mode
and is used to read out configuration data.
In AS mode, ASDO has an internal pull-up that is
always active.
This pin sends an output control signal from the
Cyclone II device to the serial configuration device in
AS mode that enables the configuration device.
In AS mode, nCSO has an internal pull-up resistor
that is always active.
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Device Configuration Pins
Table 4–11. Dedicated Configuration Pins on the Cyclone II Device (Part 5 of 5)
Pin Name
DCLK
User
Mode
N/A
Configuration
Scheme
PS,
AS
Pin Type
Input (PS)
Output (AS)
Description
In PS configuration, DCLK is the clock input used to
clock data from an external source into the target
device. Data is latched into the Cyclone II device on
the rising edge of DCLK.
In AS mode, DCLK is an output from the Cyclone II
device that provides timing for the configuration
interface. In AS mode, DCLK has an internal pull-up
that is always active.
After configuration, this pin is tri-stated. If you are
using a configuration device, it drives DCLK low after
configuration is complete. If your design uses a
control host, drive DCLK either high or low. Toggling
this pin after configuration does not affect the
configured device.
DATA0
N/A
All
Input
This is the data input pin. In serial configuration
modes, bit-wide configuration data is presented to the
target device on the DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor
that is always active.
After configuration, EPC1 and EPC1441 devices tristate this pin, while enhanced configuration and
EPC2 devices drive this pin high.
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Configuring Cyclone II Devices
Table 4–12 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-up resistors.
Table 4–12. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is
on. I/O if option
is off.
Input
This is an optional user-supplied clock input that
synchronizes the initialization of one or more devices. This
pin is enabled by turning on the Enable user-supplied
start-up clock (CLKUSR) option in the Quartus II software
INIT_DONE
N/A if option is
on. I/O if option
is off.
Output opendrain
This is a status pin that can be used to indicate when the
device has initialized and is in user mode. When nCONFIG
is low and during the beginning of configuration, the
INIT_DONE pin is tri-stated and pulled high due to an
external 10-kΩ pull-up resistor. Once the option bit to
enable INIT_DONE is programmed into the device (during
the first frame of configuration data), the INIT_DONE pin
will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high and the
FPGA enters user mode. Thus, the monitoring circuitry
must be able to detect a low-to-high transition. This pin is
enabled by turning on the Enable INIT_DONE output
option in the Quartus II software.
DEV_OE
N/A if option is
on. I/O if option
is off.
Input
Optional pin that allows the user to override all tri-states on
the device. When this pin is driven low, all I/O pins are tristated. When this pin is driven high, all I/O pins behave as
programmed. This pin is enabled by turning on the Enable
device-wide output enable (DEV_OE) option in the
Quartus II software.
DEV_CLRn
N/A if option is
on. I/O if option
is off.
Input
Optional pin that allows you to override all clears on all
device registers. When this pin is driven low, all registers
are cleared. When this pin is driven high, all registers
behave as programmed. This pin is enabled by turning on
the Enable device-wide reset (DEV_CLRn) option in the
Quartus II software.
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June 2004
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Conclusion
Table 4–13 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. The TCK pin has a weak internal pull-down resistor
and the TDI and TMS JTAG input pins have weak internal pull-up
resistors.
Table 4–13. Dedicated JTAG Pins
Pin Name
TDI
User Mode
N/A
Pin Type
Input
Description
Serial input pin for instructions as well as test and programming
data. Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to VC C .
TDO
N/A
Output
Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge of
TCK. The pin is tri-stated if data is not being shifted out of the
device.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
within the state machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the rising edge of TCK.
TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to VCC.
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at
the rising edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to GND.
Conclusion
Cyclone II devices can be configured in AS, PS or JTAG configuration
schemes to fit your system's need. The AS configuration scheme
supported by Cyclone II devices can now operate at a higher DCLK
frequency (up to 40 MHz), which reduces your configuration time. In
addition, Cyclone II devices can receive a compressed configuration
bitstream and decompress this data on-the-fly in the AS or PS
configuration scheme, which further reduces storage requirements and
configuration time.
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Chapter 5. Configuring
Cyclone FPGAs
C51013-1.2
Introduction
You can configure CycloneTM FPGAs using one of several configuration
schemes, including the active serial (AS) configuration scheme. This
scheme is used with the low cost serial configuration devices. Passive
serial (PS) and Joint Test Action Group (JTAG)-based configuration
schemes are also supported by Cyclone FPGAs. Additionally, Cyclone
FPGAs can receive a compressed configuration bit stream and
decompress this data in real-time, reducing storage requirements and
configuration time.
This chapter describes how to configure Cyclone devices using each of
the three supported configuration schemes.
f
Device
Configuration
Overview
For more information on setting device configuration options or
generating configuration files, see the Software Settings chapter in
Volume II of the Configuration Handbook.
Cyclone FPGAs use SRAM cells to store configuration data. Since SRAM
memory is volatile, configuration data must be downloaded to Cyclone
FPGAs each time the device powers up. You can download configuration
data to Cyclone FPGAs using the AS, PS, or JTAG interfaces (see
Table 5–1).
Table 5–1. Cyclone FPGA Configuration Schemes
Configuration Scheme
Altera Corporation
August 2004
Description
Active serial (AS)
configuration
●
Configuration using:
Serial configuration devices (EPCS1 or EPCS4)
Passive serial (PS)
configuration
●
JTAG-based
configuration
●
Configuration using:
Enhanced configuration devices (EPC4, EPC8, and
EPC16)
● EPC2, EPC1 configuration devices
● Intelligent host (microprocessor)
● Download cable
Configuration via JTAG pins using:
Download cable
● Intelligent host (microprocessor)
● JamTM Standard Test and Programming Language
(STAPL)
● Ability to use SignalTap® II Embedded Logic
Analyzer.
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5–1
Preliminary
Device Configuration Overview
You can select a Cyclone FPGA configuration scheme by driving its
MSEL1 and MSEL0 pins either high (1) or low (0), as shown in Table 5–2.
If your application only requires a single configuration mode, the MSEL
pins can be connected to VCC (the I/O bank’s VCCIO voltage where the
MSEL pin resides) or to ground. If your application requires more than
one configuration mode, the MSEL pins can be switched after the FPGA
has been configured successfully. Toggling these pins during user mode
does not affect the device operation. However, the MSEL pins must be
valid before initiating reconfiguration.
Table 5–2. Selecting Cyclone Configuration Schemes
MSEL1
MSEL0
Configuration Scheme
0
0
AS
0
1
PS
0
0 or 1 (1)
JTAG-based (2)
Notes to Table 5–2:
(1)
(2)
Do not leave MSEL pins floating. Connect them to a low- or high-logic level. These
pins support the non-JTAG configuration scheme used in production. If your
design only uses JTAG configuration, you should connect the MSEL0 pin to VC C .
JTAG-based configuration takes precedence over other schemes, which means
that MSEL pin settings are ignored.
After configuration, Cyclone FPGAs will initialize registers and I/O pins,
then enter user mode and function as per the user design. Figure 5–1
shows an AS configuration waveform.
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August 2004
Configuring Cyclone FPGAs
Figure 5–1. AS Configuration Waveform
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
ASDO
Read Address
DATA0
bit N
bit N − 1
bit 1
bit 0
136 Cycles
INIT_DONE
User Mode
User I/O
You can configure Cyclone FPGAs using the 3.3-, 2.5-, 1.8-, or 1.5-V
LVTTL I/O standard on configuration and JTAG input pins. These
devices do not feature a VCCSEL pin; therefore, you should connect the
VCCIO pins of the I/O banks containing configuration or JTAG pins
according to the I/O standard specifications.
Table 5–3 summarizes the approximate uncompressed configuration file
size for each Cyclone FPGA. To calculate the amount of storage space
required for multi-device configurations, add the file size of each device
together.
Table 5–3. Cyclone Raw Binary File (.rbf) Sizes Note (1)
Device
Data Size (Bits)
Data Size (Bytes)
627,376
78,422
EP1C4
924,512
115,564
EP1C6
1,167,216
145,902
EP1C12
2,326,528
290,816
EP1C20
3,559,608
444,951
EP1C3
Note to Table 5–3:
(1)
Altera Corporation
August 2004
These values are preliminary.
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Configuration Handbook, Volume 1
Data Compression
You should only use the numbers in Table 5–3 to estimate the
configuration file size before design compilation. Different file formats,
such as .hex or .ttf files, have different file sizes. For any specific version
of the Quartus® II software, any design targeted for the same device has
the same uncompressed configuration file size. If compression is used,
the file size can vary after each compilation.
Data
Compression
Cyclone FPGAs are the first FPGAs to support decompression of
configuration data. This feature allows you to store compressed
configuration data in configuration devices or other memory, and
transmit this compressed bit stream to Cyclone FPGAs. During
configuration, the Cyclone FPGA decompresses the bit stream in real
time and programs its SRAM cells.
Cyclone FPGAs support compression in the AS and PS configuration
schemes. Compression is not supported for JTAG-based configuration.
1
Preliminary data indicates that compression reduces
configuration bit stream size by 35 to 60%.
When you enable compression, the Quartus II software generates
configuration files with compressed configuration data. This
compression reduces the storage requirements in the configuration
device or flash, and decreases the time needed to transmit the bit stream
to the Cyclone FPGA.
There are two methods to enable compression for Cyclone bitstreams:
before design compilation (in the Compiler Settings menu) and after
design compilation (in the Convert Programming Files window).
To enable compression in the project's compiler settings, select Device
under the Assignments menu to bring up the settings window. After
selecting your Cyclone device open the Device & Pin Options window,
and in the General settings tab enable the check box for Generate
compressed bitstreams (as shown in Figure 5–2).
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Configuring Cyclone FPGAs
Figure 5–2. Enabling Compression for Cyclone Bitstreams in Compiler Settings
Altera Corporation
August 2004
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Configuration Handbook, Volume 1
Data Compression
Compression can also be enabled when creating programming files from
the Convert Programming Files window. See Figure 5–3.
1.
Click Convert Programming Files (File menu).
2.
Select the programming file type (POF, SRAM HEXOUT, RBF, or
TTF).
3.
For POF output files, select a configuration device.
4.
Select Add File and add a Cyclone SOF file(s).
5.
Select the name of the file you added to the SOF Data area and click
on Properties.
6.
Check the Compression checkbox.
Figure 5–3. Enabling Compression for Cyclone Bitstreams in Convert
Programming Files
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August 2004
Configuring Cyclone FPGAs
When multiple Cyclone devices are cascaded, the compression feature
can be selectively enabled for each device in the chain. Figure 5–4 depicts
a chain of two Cyclone FPGAs. The first Cyclone FPGA has the
compression feature enabled and therefore receives a compressed bit
stream from the configuration device. The second Cyclone FPGA has the
compression feature disabled and receives uncompressed data.
Figure 5–4. Compressed & Uncompressed Configuration Data in the Same
Programming File
Note (1)
Serial Data
Serial or Enhanced
Configuration
Device
Compressed
Uncompressed
Decompression
Controller
Cyclone FPGA
nCE
nCEO
Decompression
Controller
Cyclone FPGA
nCE
nCEO
N.C.
GND
Note to Figure 5–4:
(1)
The first device in the chain should be set up in AS configuration mode
(MSEL[1..0]="00"). The remaining devices in the chain must be set up in PS
configuration mode (MSEL[1..0]="01").
You can generate programming files for this setup from the Convert
Programming Files window (File menu) in the Quartus II software.
The decompression feature supported by Cyclone FPGAs is separate
from the decompression feature in enhanced configuration devices
(EPC16, EPC8, and EPC4 devices). The data compression feature in the
enhanced configuration devices allows them to store compressed data
and decompress the bit stream before transmitting to the target devices.
When using Cyclone FPGAs with enhanced configuration devices, Altera
recommends using compression on one of the devices, not both
(preferably the Cyclone FPGA since transmitting compressed data
reduces configuration time).
Altera Corporation
August 2004
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Configuration Handbook, Volume 1
Configuration Schemes
Configuration
Schemes
This section describes the various configuration schemes you can use to
configure Cyclone FPGAs. Descriptions include an overview of the
protocol, pin connections, and timing information. The schemes
discussed are:
■
■
■
AS configuration (serial configuration devices)
PS configuration
JTAG-based configuration
Active Serial Configuration (Serial Configuration Devices)
In the AS configuration scheme, Cyclone FPGAs are configured using the
new serial configuration devices. These configuration devices are low
cost devices with non-volatile memory that feature a simple four-pin
interface and a small form factor. These features make serial
configuration devices an ideal solution for configuring the low-cost
Cyclone FPGAs.
f
For more information on serial configuration devices, see Chapter 4,
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data
Sheet.
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Cyclone FPGAs read
configuration data via the serial interface, decompress data if necessary,
and configure their SRAM cells. This scheme is referred to as an AS
configuration scheme because the FPGA controls the configuration
interface. This scheme is in contrast to the PS configuration scheme where
the configuration device controls the interface.
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an activelow chip select (nCS). This four-pin interface connects to Cyclone FPGA
pins as shown in Figure 5–5.
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Configuring Cyclone FPGAs
Figure 5–5. AS Configuration of a Single Cyclone FPGA
VCC (1)
VCC (1)
10 kΩ
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Cyclone FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C.
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
MSEL1
ASDI
ASDO
MSEL0
(2)
GND
Notes to Figure 5–5:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
Cyclone FPGAs use the ASDO to ASDI path to control the configuration device.
Connecting the MSEL[1..0] pins to 00 selects the AS configuration
scheme. The Cyclone chip enable signal, nCE, must also be connected to
ground or driven low for successful configuration.
During system power up, both the Cyclone FPGA and serial
configuration device enter a power-on reset (POR) period. As soon as the
Cyclone FPGA enters POR, it drives nSTATUS low to indicate it is busy
and drives CONF_DONE low to indicate that it has not been configured.
After POR, which typically lasts 100 ms, the Cyclone FPGA releases
nSTATUS and enters configuration mode when this signal is pulled high
by the external 10-kΩ resistor. Once the FPGA successfully exits POR, all
user I/O pins are tri-stated. Cyclone devices have weak pull-up resistors
on the user I/O pins which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in Chapter 4, DC &
Switching Characteristics.
The serial clock (DCLK) generated by the Cyclone FPGA controls the
entire configuration cycle (see Figure 5–1 on page 5–3) and this clock
signal provides the timing for the serial interface. Cyclone FPGAs use an
Altera Corporation
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Configuration Schemes
internal oscillator to generate DCLK. After configuration, this internal
oscillator is turned off. Table 5–4 shows the active serial DCLK output
frequencies.
Table 5–4. Active Serial DCLK Output Frequency
Minimum
Typical
Maximum
Units
14
17
20
MHz
The serial configuration device latches input/control signals on the rising
edge of DCLK and drives out configuration data on the falling edge.
Cyclone FPGAs drive out control signals on the falling edge of DCLK and
latch configuration data on the rising edge of DCLK.
In configuration mode, the Cyclone FPGA enables the serial
configuration device by driving its nCSO output pin low that is connected
to the chip select (nCS) pin of the configuration device. The Cyclone
FPGA’s serial clock (DCLK) and serial data output (ASDO) pins are used to
read configuration data. The configuration device provides data on its
serial data output (DATA) pin that is connected to the DATA0 input on
Cyclone FPGAs.
After the Cyclone FPGA receives all configuration bits, it releases the
open-drain CONF_DONE pin allowing the external 10-kΩ resistor to pull
this signal to a high level. Initialization begins only after the CONF_DONE
line reaches a high level.
You can select the clock used for initialization by using the User Supplied
Start-Up Clock option in the Quartus II software. The Quartus II
software uses the 10-MHz (typical) internal oscillator (separate from the
AS internal oscillator) by default to initialize the Cyclone FPGA. After
initialization, the internal oscillator is turned off. When you enable the
User Supplied Start-Up Clock option, the software uses the CLKUSR pin
as the initialization clock. Supplying a clock on the CLKUSR pin does not
affect the configuration process. After all configuration data is accepted
and the CONF_DONE signal goes high, Cyclone devices require 136 clock
cycles to initialize properly.
An optional INIT_DONE pin is available. This pin signals the end of
initialization and the start of user mode with a low-to-high transition. The
Enable INIT_DONE output option is available in the Quartus II
software. If the INIT_DONE pin is used, it is high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
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Configuring Cyclone FPGAs
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the FPGA has entered user mode. In user mode, the user I/O
pins do not have weak pull-ups and functions as assigned in your design.
If an error occurs during configuration, the Cyclone FPGA asserts the
nSTATUS signal low indicating a data frame error, and the CONF_DONE
signal stays low. With the Auto-Restart Configuration on Frame Error
option enabled in the Quartus II software, the Cyclone FPGA resets the
configuration device by pulsing nCSO, releases nSTATUS after a reset
time-out period (about 30 µs), and retries configuration. If this option is
turned off, the system must monitor nSTATUS for errors and then pulse
nCONFIG low for at least 40 µs to restart configuration. After successful
configuration, the CONF_DONE signal is tri-stated by the target device and
then pulled high by the pull-up resistor.
All AS configuration pins, DATA0, DCLK, nCSO, and ASDO, have weak
internal pull-up resistors. These pull-up resistors are always active.
When the Cyclone FPGA is in user mode, you can initiate reconfiguration
by pulling the nCONFIG pin low. The nCONFIG pin should be low for at
least 40 µs. When nCONFIG is pulled low, the FPGA also pulls nSTATUS
and CONF_DONE low and all I/O pins are tri-stated. Once nCONFIG
returns to a logic high level and nSTATUS is released by the Cyclone
FPGA, reconfiguration begins.
Configuring Multiple Devices (Cascading)
You can configure multiple Cyclone FPGAs using a single serial
configuration device. You can cascade multiple Cyclone FPGAs using the
chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the
chain must have its nCE pin connected to ground. You must connect its
nCEO pin to the nCE pin of the next device in the chain. When the first
device captures all of its configuration data from the bit stream, it drives
the nCEO pin low enabling the next device in the chain. You must leave
the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA0 pins of each device in the chain are
connected (see Figure 5–6).
This first Cyclone FPGA in the chain is the configuration master and
controls configuration of the entire chain. You must connect its MSEL pins
to select the AS configuration scheme. The remaining Cyclone FPGAs are
configuration slaves and you must connect their MSEL pins to select the
PS configuration scheme. Figure 5–6 shows the pin connections for this
setup.
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Configuration Schemes
Figure 5–6. Configuring Multiple Devices Using a Serial Configuration Device (AS)
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Cyclone FPGA Slave
Cyclone FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA
DATA0
MSEL1
DATA0
DCLK
DCLK
MSEL0
DCLK
nCS
nCSO
ASDI
ASDO
nCEO
N.C.
GND
VCC
MSEL1
MSEL0
GND
GND
Note to Figure 5–6:
(1)
Connect the pull-up resistors to a 3.3-V supply.
As shown in Figure 5–6, the nSTATUS and CONF_DONE pins on all target
FPGAs are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the FPGAs. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. But the subsequent devices in the chain keep this shared
CONF_DONE line low until they have received their configuration data.
When all target FPGAs in the chain have received their configuration data
and have released CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode. If an
error occurs at any point during configuration, the nSTATUS line is
driven low by the failing FPGA. If you enable the Auto Restart
Configuration on Frame Error option, reconfiguration of the entire chain
begins after a reset time-out period (a maximum of 40 µs). If the option is
turned off, the external system must monitor nSTATUS for errors and
then pulse nCONFIG low to restart configuration. The external system can
pulse nCONFIG if it is under system control rather than tied to VCC.
1
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While you can cascade Cyclone FPGAs, serial configuration
devices cannot be cascaded or chained together.
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Configuring Cyclone FPGAs
If the configuration bit stream size exceeds the capacity of a serial
configuration device, you must select a larger configuration device
and/or enable the compression feature. While configuring multiple
devices, the size of the bit stream is the sum of the individual devices’
configuration bit streams.
Configuring Multiple Devices with the Same Data
Certain applications require the configuration of multiple Cyclone
devices with the same design through a configuration bit stream or SOF
file. This can actually be done by two methods and they are shown below.
For both methods, the serial configuration devices cannot be cascaded or
chained together.
Method 1
For method 1, the serial configuration device stores two copies of the SOF
file. The first copy configures the master Cyclone device, and the second
copy configures all the remaining slave devices concurrently. The setup
is similar to Figure 5–7 where the master is setup in AS mode (MSEL=00)
and the slave devices are setup in PS mode (MSEL01).
To configure four identical Cyclone devices with the same SOF file, you
could setup the chain similar to the example shown in Figure 5–6, except
connect the three slave devices for concurrent configuration. The nCEO
pin from the master device drives the nCE input pins on all three slave
devices, and the DATA and DCLK pins connect in parallel to all four
devices. During the first configuration cycle, the master device reads its
configuration data from the serial configuration device while holding
nCEO high. After completing its configuration cycle, the master drives
nCE low and transmits the second copy of the configuration data to all
three slave devices, configuring them simultaneously. The advantage of
using the setup in Figure 5–7 is you can have a different SOF file for the
Cyclone master device. However, all the Cyclone slave devices must be
configured with the same SOF file.
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Configuration Schemes
Figure 5–7. Configuring Multiple Devices with the Same Design Using a Serial Configuration Device
Cyclone FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC (1)
nCEO
N.C.
VCC
10 kΩ 10 kΩ 10 kΩ
Data0
DCLK
MSEL0
MSEL1
GND
Cyclone FPGA Slave
Cyclone FPGA Master
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCONFIG
nCE
nCONFIG
nCE
nCEO
nCEO
N.C.
VCC
GND
Data
Data0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
Data0
MSEL0
DCLK
MSEL1
MSEL0
MSEL1
GND
GND
Serial
Configuration
Device
Cyclone FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C.
VCC
Data0
DCLK
MSEL0
MSEL1
GND
Note to Figure 5–7:
(1)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Method 2
Method 2 configures multiple Cyclone devices with the same SOFs by
storing only one copy of the SOF in the serial configuration device. This
saves memory space in the serial configuration device for generalpurpose use and may reduce costs. This method is shown in Figure 5–8
where the master device is set up in AS mode (MSLE=00), and the slave
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Configuring Cyclone FPGAs
devices are set up in PS mode (MSEL=01). You could set up one or more
slave devices in the chain and all the slave devices are set up in the same
way as the design shown in Figure 5–8.
Figure 5–8. Configuring Multiple Devices with the Same Design Using a Serial Configuration Device
VCC
10 kΩ
10 kΩ
10 kΩ
Master Cyclone Device
EPCS4
Device
Slave Cyclone Device
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
nCE
GND
VCC
GND
Data
Data0
MSEL0
Data0
MSEL0
DCLK
DCLK
MSEL1
DCLK
MSEL1
nCS
nCS0
ASDI
ASDO
nCS0
GND
ASDO
GND
Buffer
In this setup, all the Cyclone devices in the chain are connected for
concurrent configuration. This reduces the active serial configuration
time because all the Cyclone devices are configured in only one
configuration cycle. To achieve this, the nCE input pins on all the Cyclone
devices are connected to ground and the nCEO output pins on all the
Cyclone devices are left unconnected. The DATA and DCLK pins connect
in parallel to all the Cyclone devices.
It is recommended to add a buffer before the DATA and DCLK output from
the master Cyclone to avoid signal strength and signal integrity issues.
The buffer should not significantly change the DATA-to-DCLK
relationships or delay them with respect to other ASMI signals, which are
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Configuration Schemes
ASDI and nCS signals. Also, the buffer should only drive the slave
Cyclone devices, so that the timing between the master Cyclone device
and serial configuration device is unaffected.
This setup can support both compressed and uncompressed SOFs.
Therefore, if the configuration bit stream size exceeds the capacity of a
serial configuration device, you can enable the compression feature on
the SOF used or you can select a larger serial configuration device.
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to
transfer data from the serial configuration device to the Cyclone FPGA.
This serial interface is clocked by the Cyclone DCLK output (generated
from an internal oscillator). As listed in Table 5–4, the DCLK minimum
frequency is 14 MHz (71 ns). Therefore, the maximum configuration time
estimate for an EP1C3 device (0.628 MBits of uncompressed data) is:
(0.628 MBits × 71 ns) = 47 ms.
The typical configuration time is 33 ms.
Enabling compression reduces the amount of configuration data that is
transmitted to the Cyclone device, reducing configuration time. On
average, compression reduces configuration time by 50%.
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based
devices. You can program these devices in-system using the
ByteBlasterTM II download cable. Alternatively, you can program them
using the Altera Programming Unit (APU) or supported third-party
programmers.
You can perform in-system programming of serial configuration devices
via the AS programming interface. During in-system programming, the
download cable disables FPGA access to the AS interface by driving the
nCE pin high. Cyclone FPGAs are also held in reset by a low level on
nCONFIG. After programming is complete, the download cable releases
nCE and nCONFIG, allowing the pull-down and pull-up resistor to drive
GND and VCC, respectively. Figure 5–9 shows the download cable
connections to the serial configuration device.
f
For more information on the ByteBlaster II cable, see the ByteBlaster II
Download Cable Data Sheet.
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Configuring Cyclone FPGAs
The serial configuration devices can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming that
can be customized to fit in different embedded systems. The SRunner can
read a Raw Programming Data file (.rpd) and write to the serial
configuration devices. The programming time is comparable to the
Quartus II software programming time.
f
For more information about SRunner, see the “SRunner: An Embedded
Solution for Serial Configuration Device Programming” white paper and the
source code on the Altera web site (www.altera.com).
Figure 5–9. In-System Programming of Serial Configuration Devices
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Cyclone FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
nCEO
N.C. (2)
nCONFIG
nCE
10 kΩ
DATA
DATA0
DCLK
DCLK
nCS
nCSO
MSEL1
ASDI
ASDO
MSEL0
GND
Pin 1
VCC (3)
ByteBlaser II
10-Pin Male Header
Notes to Figure 5–9:
(1)
(2)
(3)
Connect these pull-up resistors to 3.3-V supply.
The nCEO pin is left unconnected.
Power up the ByteBlaster II cable’s VCC with a 3.3-V supply.
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Configuration Schemes
You can program serial configuration devices by using the Quartus II
software with the APU and the appropriate configuration device
programming adapter. All serial configuration devices are offered in an
eight-pin small outline integrated circuit (SOIC) package and can be
programmed using the PLMSEPC-8 adapter.
In production environments, serial configuration devices can be
programmed using multiple methods. Altera programming hardware
(APU) or other third-party programming hardware can be used to
program blank serial configuration devices before they are mounted onto
PCBs. Alternatively, you can use an on-board microprocessor to program
the serial configuration device in-system using C-based software drivers
provided by Altera.
f
For more information on programming serial configuration devices, see
the Cyclone Literature web page and the Serial Configuration Devices
(EPCS1 & EPCS4) Data Sheet.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in Volume II of the
Configuration Handbook.
Passive Serial Configuration
Cyclone FPGAs also feature the PS configuration scheme supported by
all Altera FPGAs. In the PS scheme, an external host (configuration
device, embedded processor, or host PC) controls configuration.
Configuration data is clocked into the target Cyclone FPGAs via the
DATA0 pin at each rising edge of DCLK. The configuration waveforms for
this scheme are shown in Figure 5–10.
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Configuring Cyclone FPGAs
Figure 5–10. PS Configuration Cycle Waveform
D(N – 1)
nCONFIG
nSTATUS
CONF_DONE (1)
(4)
DCLK
DATA High-Z
User I/O Pins (2)
D0
D1
D2
D3
DN
High-Z
High-Z
(5)
User I/O
INIT_DONE (3)
MODE
Configuration
Configuration
Initialization
User
Notes to Figure 5–10:
(1)
(2)
(3)
(4)
(5)
During initial power up and configuration, CONF_DONE is low. After configuration, CONF_DONE goes high to
indicate successful configuration. If the device is reconfigured, CONF_DONE goes low after nCONFIG is driven low.
User I/O pins are tri-stated during configuration. Cyclone FPGAs also have a weak pull-up resistor on I/O pins
during configuration. After initialization, the user I/O pins perform the function assigned in the user’s design.
When used, the optional INIT_DONE signal is high when nCONFIG is low before configuration and during the first
136 clock cycles of configuration.
In user mode, DCLK should be driven high or low when using the PS configuration scheme. When using the AS
configuration scheme, DCLK is a Cyclone output pin and should not be driven externally.
In user mode, DATA0 should be driven high or low.
PS Configuration Using Configuration Device
In the PS configuration device scheme, nCONFIG is usually tied to VCC
(when using EPC16, EPC8, EPC4, or EPC2 devices, you can connect
nCONFIG to nINIT_CONF). Upon device power-up, the target Cyclone
FPGA senses the low-to-high transition on nCONFIG and initiates
configuration. The target device then drives the open-drain CONF_DONE
pin low, which in-turn drives the configuration device’s nCS pin low.
When exiting POR, both the target and configuration device release the
open-drain nSTATUS pin (typically Cyclone POR lasts 100 ms).
Before configuration begins, the configuration device goes through a
POR delay of up to 100 ms (maximum) to allow the power supply to
stabilize. You must power the Cyclone FPGA before or during the POR
time of the enhanced configuration device. During POR, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin. When the target and configuration devices complete POR,
they both release the nSTATUS to OE line, which is then pulled high by a
pull-up resistor.
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Configuration Schemes
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. When all devices are ready, the
configuration device clocks out DATA and DCLK to the target devices
using an internal oscillator.
After successful configuration, the Cyclone FPGA starts initialization
using the 10-MHz internal oscillator as the reference clock. After
initialization, this internal oscillator is turned off. The CONF_DONE pin is
released by the target device and then pulled high by a pull-up resistor.
When initialization is complete, the target Cyclone FPGA enters user
mode.
If an error occurs during configuration, the target device drives its
nSTATUS pin low, resetting itself internally and resetting the
configuration device. If you turn on the Auto-Restart Configuration on
Frame Error option, the device reconfigures automatically if an error
occurs. To set this option, select Compiler Settings (Processing menu),
and click on the Chips & Devices tab. Select Device & Pin Options, and
click on the Configuration tab.
If the Auto-Restart Configuration on Frame Error option is turned off,
the external system (configuration device or microprocessor) must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to VCC. When configuration is complete,
the target device releases CONF_DONE, which disables the configuration
device by driving nCS high. The configuration device drives DCLK low
before and after configuration.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the target
device has not configured successfully. (For CONF_DONE to reach a high
state, enhanced configuration devices wait for 64 DCLK cycles after the
last configuration bit. EPC2 devices wait for 16 DCLK cycles.) In this case,
the configuration device pulses its OE pin low for a few microseconds,
driving the target device’s nSTATUS pin low. If the Auto-Restart
Configuration on Frame Error option is set in the Quartus II software, the
target device resets and then releases its nSTATUS pin after a reset timeout period. When nSTATUS returns high, the configuration device
reconfigures the target device.
You should not pull CONF_DONE low to delay initialization. Instead, use
the Quartus II software’s User-Supplied Start-Up Clock option to
synchronize the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain initialize
together since their CONF_DONE pins are tied together.
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Configuring Cyclone FPGAs
CONF_DONE goes high during the first few clock cycles of initialization.
Hence, when using the CLKUSR feature you would not see the
CONF_DONE signal high until you start clocking CLKUSR. However, the
device does retain configuration data and waits for these initialization
clocks to release CONF_DONE and go into user mode. Figure 5–11 shows
how to configure one Cyclone FPGA with one configuration device.
Figure 5–11. Single Device Configuration Circuit
VCC (1)
10 kΩ
Cyclone FPGA
MSEL0
MSEL1
nCEO
10 kΩ
VCC (1)
10 kΩ
Configuration
Device
DCLK
DATA
OE
nCS
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC (4)
VCC (1)
N.C. (3)
nCE
GND
GND
Notes to Figure 5–11:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the
configuration device. This pull-up resistor is 10 kΩ. The EPC16, EPC8, EPC4, and
EPC2 devices’ OE and nCS pins have internal, user-configurable pull-up resistors.
If you use internal pull-up resistors, do not use external pull-up resistors on these
pins.
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices and
has an internal pull-up resistor that is always active. If nINIT_CONF is not used,
nCONFIG must be pulled to VCC through a resistor.
The nCEO pin is left unconnected for the last device in the chain.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
Configuring Multiple Cyclone FPGAs
You can use a single configuration device to configure multiple Cyclone
FPGAs. In this setup, the nCEO pin of the first device is connected to the
nCE pin of the second device in the chain. If there are additional devices,
connect the nCE pin of the next device to the nCEO pin of the previous
device. You should leave the nCEO pin on the last device in the chain
unconnected. To configure properly, all of the target device CONF_DONE
and nSTATUS pins must be tied together. Figure 5–12 shows an example
of configuring multiple Cyclone FPGAs using a single configuration
device.
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Configuration Schemes
Figure 5–12. Configuring Multiple Cyclone FPGAs with a Single Configuration Device
VCC (1)
VCC (1)
10 kΩ
VCC (6)
Cyclone FPGA 2
MSEL0
MSEL1
VCC (6)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE
nCS
nCASC
nINIT_CONF (4), (5)
GND
GND
N.C.
10 kΩ
Configuration
Device (2)
Cyclone FPGA 1
MSEL0
MSEL1
10 kΩ
VCC (1)
nCEO (3)
nCE
nCEO
nCE
GND
Notes to Figure 5–12:
(1)
(2)
(3)
(4)
(5)
(6)
The pull-up resistor should be connected to the same supply voltage as the configuration device. The EPC16, EPC8,
EPC4, and EPC2 devices’ OE and nCS pins have internal, user-configurable pull-up resistors. If you use internal
pull-up resistors, do not use external pull-up resistors on these pins.
EPC16, EPC8, and EPC4 configuration devices cannot be cascaded.
The nCEO pin is left unconnected for the last device in the chain.
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC through a resistor.
The nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16, EPC8, EPC4, and EPC2 devices.
These devices do not need an external pull-up resistor on the nINIT_CONF pin.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
When performing multi-device PS configuration, you must generate the
configuration device programming file (.sof) from each project. Then you
must combine multiple .sof files using the Quartus II software through
the Convert Programming Files dialog box.
f
For more information on how to create Programmer Object Files (.pof)
for enhanced configuration devices, see AN 218: Using Enhanced
Configuration Devices.
After the first Cyclone FPGA completes configuration during multidevice configuration, its nCEO pin activates the second device’s nCE pin,
prompting the second device to begin configuration. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
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Configuring Cyclone FPGAs
In addition, all nSTATUS pins are tied together; therefore, if any device
(including the configuration device) detects an error, configuration stops
for the entire chain. Also, if the configuration device does not detect
CONF_DONE going high at the end of configuration, it resets the chain by
pulsing its OE pin low for a few microseconds. For CONF_DONE to reach a
high state, enhanced configuration devices wait for 64 DCLK cycles after
the last configuration bit. EPC2 devices wait for 16 DCLK cycles.
If the Auto-Restart Configuration on Frame Error option is turned on in
the Quartus II software, the Cyclone FPGA releases its nSTATUS pins
after a reset time-out period (about 30 µs). When the nSTATUS pins are
released and pulled high, the configuration device reconfigures the chain.
If the Auto-Restart Configuration on Frame Error option is not turned
on, the devices drive nSTATUS low until they are reset with a low pulse
on nCONFIG.
You can also cascade several EPC2 or EPC1 configuration devices to
configure multiple Cyclone FPGAs. When all data from the first
configuration device is sent, it drives nCASC low, which in turn drives
nCS on the subsequent EPC2 or EPC1 device. Because a configuration
device requires less than one clock cycle to activate a subsequent
configuration device, the data stream is uninterrupted. You cannot
cascade EPC16, EPC8, and EPC4 configuration devices.
Figure 5–13 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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Configuration Schemes
Figure 5–13. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (1)
VCC (1)
VCC (1)
(3) 10 kΩ
Cyclone Device 2
VCC
MSEL1
MSEL0
GND
N.C.
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCEO
10 kΩ
(2)
10 kΩ (3)
EPC2 or EPC1
Device 1
Cyclone Device 1
VCC
MSEL1
MSEL0
nCEO
nCE
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
EPC2 or EPC1
Device 2
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 5–13:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor should not be used on the nINIT_CONFnCONFIG line. The nINIT_CONF pin does not need to be connected if its function is not used. If nINIT_CONF is
not used or not available (such as on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a
resistor.
The enhanced configuration devices' and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. External 10-kΩ pull-up resistors should be used. To turn off the internal pull-up resistors, check the
Disable nCS and OE pull-ups on configuration device option when generating programming files.
PS Configuration Using a Download Cable
Using a download cable in PS configuration, an intelligent host (for
example, your PC) transfers data from a storage device (for example,
your hard drive) to the Cyclone FPGA through a USB Blaster,
ByteBlaster II, MasterBlaster, or ByteBlasterMV cable. To initiate
configuration in this scheme, the download cable generates a low-to-high
transition on the nCONFIG pin. The programming hardware then sends
the configuration data one bit at a time on the device’s DATA0 pin. The
data is clocked into the target device using DCLK until the CONF_DONE
goes high.
When using programming hardware for the Cyclone FPGA, turning on
the Auto-Restart Configuration on Frame Error option does not affect
the configuration cycle because the Quartus II software must restart
configuration when an error occurs. Figure 5–14 shows the PS
configuration setup for the Cyclone FPGA using a USB Blaster,
ByteBlaster II, MasterBlaster, or ByteBlasterMV cable.
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August 2004
Configuring Cyclone FPGAs
Figure 5–14. PS Configuration Circuit with a Download Cable
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
10 kΩ
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Cyclone Device
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
VCC (4)
MSEL0
MSEL1
nCE
nCEO
N.C.
10-Pin Male Header
(PS Mode)
GND
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (2)
Shield
GND
Notes to Figure 5–14:
(1)
(2)
(3)
(4)
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. This pin is a no-connect pin for the ByteBlasterMV header.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
You can use the download cable to configure multiple Cyclone FPGAs by
connecting each device’s nCEO pin to the subsequent device’s nCE pin.
All other configuration pins are connected to each device in the chain.
Because all CONF_DONE pins are tied together, all devices in the chain
initialize and enter user mode at the same time. In addition, because the
nSTATUS pins are tied together, the entire chain halts configuration if any
device detects an error. In this situation, the Quartus II software must
restart configuration; the Auto-Restart Configuration on Frame Error
option does not affect the configuration cycle. Figure 5–15 shows how to
configure multiple Cyclone FPGAs with a ByteBlaster II, MasterBlaster,
or ByteBlasterMV cable.
Altera Corporation
August 2004
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Configuration Handbook, Volume 1
Configuration Schemes
Figure 5–15. Multi-Device PS Configuration with a Download Cable
VCC (1)
VCC (1)
VCC (1)
10 kΩ
(3)
10 kΩ
VCC (4)
10 kΩ
(3)
VCC (1)
10 kΩ
Cyclone FPGA 1
Pin 1
CONF_DONE
nSTATUS
DCLK
MSEL0
10-Pin Male Header
(PS Mode)
VCC
MSEL1
VCC (1)
GND
VIO (2)
nCE
10 kΩ
GND
DATA0
nCONFIG
VCC
GND
Cyclone FPGA 2
MSEL0
MSEL1
GND
nCEO
CONF_DONE
nSTATUS
DCLK
nCE
nCEO
N.C.
DATA0
nCONFIG
Notes to Figure 5–15:
(1)
(2)
(3)
(4)
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. Refer to the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
If you are using a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable to
configure device(s) on a board that also is populated with configuration
devices, you should electrically isolate the configuration devices from the
target device(s) and cable. One way to isolate the configuration devices is
to add logic, such as a multiplexer, that can select between the
configuration devices and the cable. The multiplexer allows bidirectional
transfers on the nSTATUS and CONF_DONE signals. Another option is to
add switches to the five common signals (CONF_DONE, nSTATUS, DCLK,
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August 2004
Configuring Cyclone FPGAs
nCONFIG, and DATA0) between the cable and the configuration devices.
The last option is to remove the configuration devices from the board
when configuring with the cable. Figure 5–16 shows a combination of a
configuration device and a ByteBlaster II, MasterBlaster, or
ByteBlasterMV cable to configure a Cyclone FPGA.
Figure 5–16. Configuring with a Combined PS & Configuration Device Scheme
VCC (1)
10 kΩ
(5)
VCC (1)
VCC (6)
10 kΩ
VCC (1)
VCC (1)
10 kΩ
10 kΩ
(5)
Cyclone FPGA
CONF_DONE
MSEL0
nSTATUS
DCLK
MSEL1
10 kΩ
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
Pin 1
VCC
VIO GND
(2)
nCEO N.C.
nCE
GND
DATA0
nCONFIG
(3)
(3)
(3)
GND
Configuration Device
(3)
DCLK
DATA
OE
nCS
nINIT_CONF (4)
(3)
Notes to Figure 5–16:
(1)
(2)
(3)
(4)
(5)
(6)
You should connect the pull-up resistor to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the target
device’s VCCIO. This is a no-connect pin for the ByteBlasterMV header.
You should not attempt configuration with a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable while a
configuration device is connected to a Cyclone FPGA. Instead, you should either remove the configuration device
from its socket when using the download cable or place a switch on the five common signals between the download
cable and the configuration device. Remove the ByteBlaster II, MasterBlaster, or ByteBlasterMV cable when
configuring with a configuration device.
If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
f
For more information on how to use the ByteBlaster II, MasterBlaster, or
ByteBlasterMV cables, see the following documents:
■
■
■
Altera Corporation
August 2004
ByteBlaster II Parallel Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
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Configuration Schemes
PS Configuration from a Microprocessor
In PS configuration with a microprocessor, a microprocessor transfers
data from a storage device to the target Cyclone FPGA. To initiate
configuration in this scheme, the microprocessor must generate a low-tohigh transition on the nCONFIG pin and the target device must release
nSTATUS. The microprocessor then places the configuration data one bit
at a time on the DATA0 pin of the Cyclone FPGA. The least significant bit
(LSB) of each data byte must be presented first. Data is clocked
continuously into the target device using DCLK until the CONF_DONE
signal goes high.
The Cyclone FPGA starts initialization using the internal oscillator after
all configuration data is transferred. After initialization, this internal
oscillator is turned off. The device’s CONF_DONE pin goes high to show
successful configuration and the start of initialization. During
configuration and initialization and before the device enters user ode the
microprocessor must not drive CONF_DONE low. Driving DCLK to the
device after configuration does not affect device operation.
Since the PS configuration scheme is a synchronous scheme, the
configuration clock speed must be below the specified maximum
frequency to ensure successful configuration. Maximum DCLK frequency
supported by Cyclone FPGAs is 100 MHz (see Table 5–5 on page 5–30).
No maximum DCLK period (i.e., minimum DCLK frequency) exists. You
can pause configuration by halting DCLK for an indefinite amount of time.
If the target device detects an error during configuration, it drives its
nSTATUS pin low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on in the Quartus II software, the target device releases
nSTATUS after a reset time-out period. After nSTATUS is released, the
microprocessor can reconfigure the target device without needing to
pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration and initialization. If the
microprocessor sends all data, but CONF_DONE and INIT_DONE has not
gone high, it must reconfigure the target device. Figure 5–17 shows the
circuit for PS configuration with a microprocessor.
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August 2004
Configuring Cyclone FPGAs
Figure 5–17. PS Configuration Circuit with a Microprocessor
Memory
ADDR
DATA0
VCC
10 k Ω
VCC
VCC (2)
Cyclone Device
10 k Ω
CONF_DONE
nSTATUS
MSEL0
MSEL1
nCE
Microprocessor
GND
GND
nCEO
N.C. (1)
DATA0
nCONFIG
DCLK
Notes to Figure 5–17:
(1)
(2)
The nCEO pin is left unconnected.
Connect MSEL0 to the VCC supply voltage of the I/O bank it resides in.
Configuring Cyclone FPGAs with the MicroBlaster Software
The MicroBlasterTM software driver allows you to configure Altera
FPGAs, including Cyclone FPGAs, through the ByteBlaster II or
ByteBlasterMV cable in PS mode. The MicroBlaster software driver
supports a Raw Binary File (.rbf) programming input file and is targeted
for embedded PS configuration. The source code is developed for the
Windows NT operating system, although you can customize it to run on
other operating systems. For more information on the MicroBlaster
software driver, see the Configuring the MicroBlaster Passive Serial Software
Driver White Paper and source files on the Altera web site at
www.altera.com.
Passive Serial Timing
For successful configuration using the PS scheme, several timing
parameters such as setup, hold, and maximum clock frequency must be
satisfied. The enhanced configuration and EPC2 devices are designed to
meet these interface timing specifications. If you use a microprocessor or
another intelligent host to control the PS interface, ensure that you meet
these timing requirements.
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August 2004
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Configuration Schemes
Figure 5–18 shows the PS timing waveform for Cyclone FPGAs.
Figure 5–18. PS Timing Waveform for Cyclone FPGAs
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (1)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (2)
tCF2CD
tST2CK
tCH tCL
DCLK (3)
tDH
Bit 0 Bit 1 Bit 2 Bit 3
DATA
Bit n
(4)
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 5–18:
(1)
(2)
(3)
(4)
Upon power-up, the Cyclone FPGA holds nSTATUS low for about 100 ms.
Upon power-up and before configuration, CONF_DONE is low.
In user mode, DCLK should be driven high or low when using the PS configuration scheme. When using the AS
configuration scheme, DCLK is a Cyclone output pin and should not be driven externally.
DATA should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
Table 5–5 contains the PS timing information for Cyclone FPGAs.
Table 5–5. PS Timing Parameters for Cyclone Devices
of 2)
Symbol
Parameter
Note (1) (Part 1
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
tCF2ST1
nCONFIG high to nSTATUS high
40 (4)
µs
tCFG
nCONFIG low pulse width (2)
40
tSTATUS
nSTATUS low pulse width
10
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
µs
40 (4)
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
7
ns
tDH
Data hold time after rising edge on DCLK
0
ns
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August 2004
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Configuration Handbook, Volume 1
Configuring Cyclone FPGAs
Table 5–5. PS Timing Parameters for Cyclone Devices
of 2)
Symbol
Parameter
Note (1) (Part 2
Min
tCH
DCLK high time
tCL
tCLK
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (3)
Max
Units
4
ns
DCLK low time
4
ns
DCLK period
10
ns
6
100
MHz
20
µs
Notes to Table 5–5:
(1)
(2)
(3)
(4)
f
This information is preliminary.
This value applies only if the internal oscillator is selected as the clock source for
device initialization. If the clock source is CLKUSR, multiply the clock period by
270 to obtain this value. CLKUSR must be running during this period to reset the
device.
The minimum and maximum numbers apply only if the internal oscillator is
chosen as the clock source for device initialization. If the clock source is CLKUSR,
multiply the clock period by 140 to obtain this value.
You can obtain this value if you do not delay configuration by extending the
nSTATUS low-pulse width.
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in Volume II of the
Configuration Handbook.
JTAG-Based Configuration
JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on printed circuit boards (PCBs) with tight lead spacing.
The BST architecture can test pin connections without using physical test
probes and capture functional data while a device is operating normally.
You can also use the JTAG circuitry to shift configuration data into
Cyclone FPGAs. The Quartus II software automatically generates .sof
files that can be used for JTAG configuration.
f
For more information on JTAG boundary-scan testing, see
AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
To use the SignalTap II Embedded Logic Analyzer, you need to connect
the JTAG pins of your Cyclone device to a download cableheader on your
PCB.
f
Altera Corporation
August 2004
For more information on SignalTap II, see the Design Debugging Using the
SignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook.
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Configuration Schemes
Cyclone devices are designed such that JTAG instructions have
precedence over any device operating modes. So JTAG configuration can
take place without waiting for other configuration to complete (e.g.,
configuration with serial or enhanced configuration devices). If you
attempt JTAG configuration in Cyclone FPGAs during non-JTAG
configuration, non-JTAG configuration is terminated and JTAG
configuration is initiated.
1
The Cyclone configuration data decompression feature is not
supported in JTAG-based configuration.
A device operating in JTAG mode uses four required pins: TDI, TDO, TMS,
and TCK. Cyclone FPGAs do not support the optional TRST pin. The three
JTAG input pins, TCK, TDI, and TMS, have weak internal pull-up
resistors, whose values are approximately 20 to 40 kΩ. All user I/O pins
are tri-stated during JTAG configuration.
Table 5–6 shows each JTAG pin’s function.
Table 5–6. JTAG Pin Descriptions
Pin
Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to VCC.
TDO
Test data output
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by leaving this pin unconnected.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of the Test
Access Port (TAP) controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK. If the JTAG interface
is not required on the board, the JTAG circuitry can be disabled by connecting
this pin to VCC.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled, by connecting this pin to GND.
JTAG Configuration Using a Download Cable
During JTAG configuration, data is downloaded to the device on the
board through a USB Blaster, ByteBlaster II, ByteBlasterMV, or
MasterBlaster download cable. Configuring devices through a cable is
similar to programming devices in-system. See Figure 5–19 for pin
connection information.
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Configuring Cyclone FPGAs
Figure 5–19. JTAG Configuration of Single Cyclone FPGA
VCC
VCC
VCC
10 kΩ
10 kΩ
Cyclone Device 10 kΩ
10 kΩ
TCK
TDO
nCE (4)
GND
N.C.
(2)
(2)
(2)
(2)
(2)
VCC
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
DATA0
DCLK
TMS
TDI
Download Cable
10-Pin Male Header (JTAG Mode)
(Top View)
Pin 1
VCC (1)
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 5–19:
(1)
(2)
(3)
(4)
You should connect the pull-up resistor to the same supply voltage as the download cable.
You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG configuration scheme. If you only
use JTAG configuration, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground. Pull DATA0 and DCLK to high
or low.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. Refer to the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlaster MV, this pin is a no
connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active Serial
programming; otherwise it is a no connect.
nCE must be connected to GND or driven low for successful configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in bypass mode. In bypass mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon
completion. The software checks the state of CONF_DONE through the
JTAG port. If CONF_DONE is not high, the Quartus II software indicates
that configuration has failed. If CONF_DONE is high, the software
indicates that configuration was successful. After the configuration bit
stream is transmitted serially via the JTAG TDI port, the TCK port is
clocked an additional 134 cycles to perform device initialization.
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August 2004
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Configuration Schemes
1
If VCCIO is tied to 3.3-V, both the I/O pins and the JTAG TDO port
drive at 3.3-V levels.
Cyclone FPGAs have dedicated JTAG pins. Not only can you perform
JTAG testing on Cyclone FPGAs before and after, but also during
configuration. While other device families do not support JTAG testing
during configuration, Cyclone FPGAs support the BYPASS, IDCODE, and
SAMPLE instructions during configuration without interrupting
configuration. All other JTAG instructions may only be issued by first
interrupting configuration and reprogramming I/O pins using the
CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port, and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Cyclone FPGA or waiting for a configuration device to complete
configuration. Once configuration has been interrupted and JTAG testing
is complete, the part must be reconfigured via JTAG (PULSE_CONFIG
instruction) or by pulsing nCONFIG low.
The chip-wide reset and output enable pins on Cyclone FPGAs do not
affect JTAG boundary-scan or programming operations. Toggling these
pins does not affect JTAG operations (other than the usual boundary-scan
operation).
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August 2004
Configuring Cyclone FPGAs
When designing a board for JTAG configuration of Cyclone FPGAs, you
should consider the dedicated configuration pins. Table 5–7 shows how
you should connect these pins during JTAG configuration.
Table 5–7. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
Drive all Cyclone devices in the chain low by connecting nCE to ground, pulling it down via a
resistor, or driving it low by some control circuitry. For devices in a multi-device PS and AS
configuration chains, connect the nCE pins to ground during JTAG configuration or configure
them via JTAG in the same order as the configuration chain.
nCEO
For all Cyclone devices in a chain, the nCEO pin can be left floating or connected to the nCE
pin of the next device. See nCE description above.
nSTATUS
Pulled to VCC through a 10-kΩ resistor. When configuring multiple devices in the same JTAG
chain, pull up each nSTATUS pin to VCC individually. (1)
CONF_DONE
Pulled to VCC through a 10-kΩ resistor. When configuring multiple devices in the same JTAG
chain, pull up each CONF_DONE pin to VCC individually. (1)
nCONFIG
Driven high by connecting to VCC, pulling up through a resistor, or driving it high by some
control circuitry.
MSEL0,
MSEL1
Do not leave these pins floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie these pins to ground.
DCLK
Do not leave these pins floating. Drive low or high, whichever is more convenient.
DATA0
Do not leave these pins floating. Drive low or high, whichever is more convenient.
Note to Table 5–7:
(1)
nSTATUS going low in the middle of JTAG configuration indicates that an error has occurred; CONF_DONE going
high at the end of JTAG configuration indicates successful configuration.
JTAG Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header,
such as the ByteBlaster II header, is connected to several devices. The
number of devices in the JTAG chain is limited only by the drive capacity
of the download cable. However, when four or more devices are
connected in a JTAG chain, Altera recommends buffering the TCK, TDI,
and TMS pins with an on-board buffer.
JTAG-chain device configuration is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 5–20 shows multi-device JTAG configuration.
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August 2004
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Configuration Schemes
Figure 5–20. Multi-Device JTAG Configuration
VCC
Download Cable
10-Pin Male Header
(JTAG Mode)
Note (1)
VCC
10 kΩ
10 kΩ
10 kΩ
Cyclone FPGA
VCC
VCC
VCC
10 kΩ
VCC
10 kΩ
Cyclone FPGA
10 kΩ
Cyclone FPGA
VCC
Pin 1
10 kΩ
VCC
VCC
10 kΩ
VIO
(3)
(2)
(2)
(2)
(2)
(2)
nSTATUS
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCE (4)
TDI
TMS
TCK
TDO
(2)
(2)
(2)
(2)
(2)
nSTATUS
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCE (4)
TDI
TMS
TDO
TCK
nSTATUS
(2)
(2)
(2)
(2)
(2)
DATA0
DCLK
nCONFIG
MSEL1 CONF_DONE
MSEL0
nCE (4)
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 5–20:
(1)
(2)
(3)
(4)
Cyclone, Stratix, Stratix GX, APEXTM II, APEX 20K, MercuryTM, ACEX® 1K, and FLEX® 10K devices can be placed
within the same JTAG chain for device programming and configuration.
Connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground. Pull DATA0 and DCLK to either
high or low.
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. Refer to the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlaster MV, this pin is a no
connect. In the USB Blaster and ByteBlaster, this pin is connected to nCE when it is used for Active Serial
programming; otherwise it is a no connect.
nCE must be connected to GND or driven low for successful configuration.
Connect the nCE pin to ground or drive it low during JTAG
configuration. In multi-device PS and AS configuration chains, connect
the first device’s nCE pin to ground and connect the nCEO pin to the nCE
pin of the next device in the chain. The last device’s nCE input comes from
the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, it’s
nCEO pin drives low to activate the second device’s nCE pin, which
prompts the second device to begin configuration. Therefore, if these
devices are also in a JTAG chain, you should make sure the nCE pins are
connected to ground during JTAG configuration or that the devices are
configured via JTAG in the same order as the configuration chain. As long
as the devices are configured in the same order as the multi-device
configuration chain, the nCEO pin of the previous device drives the nCE
pin of the next device low when it has successfully been configured.
Figure 5–21 shows the JTAG configuration of a Cyclone FPGA with a
microprocessor.
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August 2004
Configuring Cyclone FPGAs
Figure 5–21. JTAG Configuration of Cyclone FPGAs with a Microprocessor
Memory
ADDR
Cyclone FPGA
DATA
(1)
(2)
(2)
Microprocessor
(1)
MSEL1
(1)
VCC
nCONFIG MSEL0
DATA0
VCC
10 kΩ
nCE (3)
DCLK
nCEO N.C.
TDI
10 kΩ
TCK
TDO
TMS
nSTATUS
CONF_DONE
Notes to Figure 5–21:
(1)
(2)
(3)
f
Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG
configuration scheme. If your design only uses JTAG configuration, connect the
nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground.
Pull DATA0 and DCLK to either high or low.
nCE must be connected to GND or driver low for succesful JTAG configuration.
For more information about JTAG programming in an embedded
environment, refer to AN 122: Using JamSTAPL for ISP &ICR via an
Embedded Processor.
Configuring Cyclone FPGAs with JRunner
JRunner is a software driver that allows you to configure Altera FPGAs,
including Cyclone FPGAs, through the ByteBlaster II or ByteBlasterMV
cables in JTAG mode. The programming input file supported is in .rbf
format. JRunner also requires a Chain Description File (.cdf) generated by
the Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has been developed for the Windows NT
operating system (OS). You can customize the code to make it run on
other platforms. For more information on the JRunner software driver,
see JRunner Software Driver: An Embedded Solution to the JTAG
Configuration and the source files on the Altera web site.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
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August 2004
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Configuration Schemes
1
Both JTAG connection methods should include space for the
MasterBlaster or ByteBlasterMV header connection. The header
is useful during prototyping because it allows you to verify or
modify the Cyclone FPGA’s contents. During production, you
can remove the header to save cost.
Program Flow
The Jam Player provides an interface for manipulating the IEEE
Std. 1149.1 JTAG TAP state machine. The TAP controller is a 16-state,
state machine that is clocked on the rising edge of TCK, and uses the TMS
pin to control JTAG operation in a device. Figure 5–22 shows the flow of
an IEEE Std. 1149.1 TAP controller state machine.
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August 2004
Configuring Cyclone FPGAs
Figure 5–22. JTAG TAP Controller State Machine
TMS = 1
TEST_LOGIC/
RESET
TMS = 0
SELECT_IR_SCAN
TMS = 1
TMS = 1
TMS = 0
TMS = 1
SELECT_DR_SCAN
RUN_TEST/
IDLE
TMS = 0
TMS = 0
TMS = 1
TMS = 1
CAPTURE_IR
CAPTURE_DR
TMS = 0
TMS = 0
SHIFT_DR
SHIFT_IR
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 1
EXIT1_DR
EXIT1_IR
TMS = 0
TMS = 0
PAUSE_DR
PAUSE_IR
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
EXIT2_DR
EXIT2_IR
TMS = 1
TMS = 1
TMS = 1
TMS = 1
UPDATE_DR
TMS = 0
UPDATE_IR
TMS = 0
While the Jam Player provides a driver that manipulates the TAP
controller, the Jam Byte-Code File (.jbc) provides the high-level
intelligence needed to program a given device. All Jam instructions that
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August 2004
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Configuration Handbook, Volume 1
Configuration Schemes
send JTAG data to the device involve moving the TAP controller through
either the data register leg or the instruction register leg of the state
machine. For example, loading a JTAG instruction involves moving the
TAP controller to the SHIFT_IR state and shifting the instruction into the
instruction register through the TDI pin. Next, the TAP controller is
moved to the RUN_TEST/IDLE state where a delay is implemented to
allow the instruction time to be latched. This process is identical for data
register scans, except that the data register leg of the state machine is
traversed.
The high-level Jam instructions are the DRSCAN instruction for scanning
the JTAG data register, the IRSCAN instruction for scanning the
instruction register, and the WAIT command that causes the state machine
to sit idle for a specified period of time. Each leg of the TAP controller is
scanned repeatedly, according to instructions in the .jbc file, until all of
the target devices are programmed.
Figure 5–23 shows the functional behavior of the Jam Player when it
parses the .jbc file. When the Jam Player encounters a DRSCAN, IRSCAN,
or WAIT instruction, it generates the proper data on TCK, TMS, and TDI to
complete the instruction. The flow diagram shows branches for the
DRSCAN, IRSCAN, and WAIT instructions. Although the Jam Player
supports other instructions, they are omitted from the flow diagram for
simplicity.
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August 2004
Configuring Cyclone FPGAs
Figure 5–23. Jam Player Flow Diagram (Part 1 of 2)
Start
Set TMS to 1
and Pulse TCK
Five Times
Test-Logic-Reset
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
WAIT
Read Instruction
from the Jam
File
EOF?
F
T
Case[]
DRSCAN
IRSCAN
Set TMS to 0
and Pulse TCK
Parse Argument
Parse Argument
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Twice
Delay
Set TMS to 1
and Pulse TCK
Select-IR-Scan
Set TMS to 1
and Pulse TCK
Three Times
Set TMS to 0
and Pulse TCK
Twice
Set TMS to 0
and Pulse TCK
Twice
Switch
Test-Logic-Reset
Shift-DR
Shift-IR
Set TMS to 0
and Pulse TCK
and Write TDI
End
Set TMS to 1
and Pulse TCK
Select-DR-Scan
Set TMS to 0
and Pulse TCK
and Write TDI
Shift-IR
Shift-DR
Exit1-IR
Set TMS to 0
and Pulse TCK
Pause-IR
Set TMS to 1
and Pulse TCK
Twice
T
EOF
Shift-IR
Continued on
Part 2 of
Flow Diagram
F
Set TMS to 0
and Pulse TCK
and Write TDI
Update-IR
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
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Configuration Schemes
Figure 5–24. Jam Player Flow Diagram (Part 2 of 2)
Continued from
Part 1 of
Flow Diagram
Compare
Case[]
Default
Capture
Set TMS to 1
and Pulse TCK
and Store TDO
F
Exit1-DR
Loop<
DR Length
F
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 1
and Pulse TCK
Update-IR
Shift-DR
T
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Exit1-DR
T
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Loop<
DR Length
Correct F
TDO Value
Report
Error
Set TMS to 0
and Pulse TCK
Set TMS to 1
and Pulse TCK
and Store TDO
F
Loop<
DR Length
Run-Test/Idle
Exit1-DR
T
T
Switch
Set TMS to 1
and Pulse TCK
Set TMS to 1
and Pulse TCK
Update-IR
Set TMS to 0
and Pulse TCK
and Write TDI
Update-IR
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Set TMS to 0
and Pulse TCK
Run-Test/Idle
Switch
Switch
Execution of a Jam program starts at the beginning of the program. The
program flow is controlled using GOTO, CALL/RETURN, and FOR/NEXT
structures. The GOTO and CALL statements refer to labels that are
symbolic names for program statements located elsewhere in the Jam
program. The language itself enforces almost no constraints on the
organizational structure or control flow of a program.
1
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Configuration Handbook, Volume 1
The Jam language does not support linking multiple Jam
programs together or including the contents of another file into
a Jam program.
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August 2004
Configuring Cyclone FPGAs
Jam Instructions
Each Jam statement begins with one of the instruction names listed in
Table 5–8. The instruction names, including the names of the optional
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 5–8. Instruction Names
BOOLEAN
INTEGER
PREIR
CALL
IRSCAN
PRINT
CRC
IRSTOP
PUSH
DRSCAN
LET
RETURN
DRSTOP
NEXT
STATE
EXIT
NOTE
WAIT
EXPORT
POP
VECTOR (1)
FOR
POSTDR
VMAP (1)
GOTO
POSTIR
-
IF
PREDR
-
Note to Table 5–8:
(1)
This instruction name is an optional language extension.
Table 5–9 shows the state names that are reserved keywords in the Jam
language. These keywords correspond to the state names specified in the
IEEE Std. 1149.1 JTAG specification.
Table 5–9. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names
Test-Logic-Reset
Altera Corporation
August 2004
Jam Reserved State Names
RESET
Run-Test-Idle
IDLE
Select-DR-Scan
DRSELECT
Capture-DR
DRCAPTURE
Shift-DR
DRSHIFT
Exit1-DR
DREXIT1
Pause-DR
DRPAUSE
Exit2-DR
DREXIT2
Update-DR
DRUPDATE
Select-IR-Scan
IRSELECT
Capture-IR
IRCAPTURE
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Configuration Handbook, Volume 1
Configuration Schemes
Table 5–9. Reserved Keywords (Part 2 of 2)
IEEE Std. 1149.1 JTAG State Names
Jam Reserved State Names
Shift-IR
IRSHIFT
Exit1-IR
IREXIT1
Pause-IR
IRPAUSE
Exit2-IR
IREXIT2
Update-IR
IRUPDATE
Example Jam File that Reads the IDCODE
The following illustrates the flexibility and utility of the Jam STAPL. The
example code reads the IDCODE out of a single device in a JTAG chain.
1
The array variable, I_IDCODE, is initialized with the IDCODE
instruction bits ordered the LSB first (on the left) to most
significant bit (MSB) (on the right). This order is important
because the array field in the IRSCAN instruction is always
interpreted and sent, MSB to LSB.
Example Jam File Reading IDCODE
BOOLEAN read_data[32];
BOOLEAN I_IDCODE[10] = BIN 1001101000; ‘assumed
BOOLEAN ONES_DATA[32] = HEX FFFFFFFF;
INTEGER i;
‘Set up stop state for IRSCAN
IRSTOP IRPAUSE;
‘Initialize device
STATE RESET;
IRSCAN 10, I_IDCODE[0..9]; ‘LOAD IDCODE INSTRUCTION
STATE IDLE;
WAIT 5 USEC, 3 CYCLES;
DRSCAN 32, ONES_DATA[0..31], CAPTURE read_data[0..31];
‘CAPTURE IDCODE
PRINT “IDCODE:”;
FOR i=0 to 31;
PRINT read_data[i];
NEXT i;
EXIT 0;
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August 2004
Configuring Cyclone FPGAs
Combining
Configuration
Schemes
This section shows you how to configure Cyclone FPGAs using multiple
configuration schemes on the same board.
Active Serial & JTAG
You can combine the AS configuration scheme with JTAG-based
configuration. Set the MSEL[1..0] pins to 00 in this setup, as shown in
Figure 5–25. This setup uses two 10-pin download cable headers on the
board. The first header programs the serial configuration device insystem via the AS programming interface, and the second header
configures the Cyclone FPGA directly via the JTAG interface.
If you try configuring the device using both schemes simultaneously,
JTAG configuration takes precedence and AS configuration is
terminated.
Figure 5–25. Combining AS & JTAG Configuration
(1) VCC
10 kΩ
VCC (1)
VCC (1)
10 kΩ
10 kΩ
Serial Configuration
Device
Cyclone FPGA
nSTATUS
CONF_DONE nCEO
nCONFIG
nCE
VCC
N.C.
10 kΩ
VCC
MSEL1
10 kΩ
MSEL0
GND
DATA
DATA
TCK
DCLK
DCLK
TDO
nCS
nCSO
TMS
ASDI
ASDO
TDI
10 kΩ
GND
Download Cable
(JTAG Mode)
10-Pin Male Header (top View)
Pin 1
Pin 1
VCC
VCC (1)
VIO
1 kΩ
Download Cable
(AS Mode)
10-Pin Male Header
GND
Notes to Figure 5–25:
(1)
Connect these pull-up resistors to 3.3 V.
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August 2004
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Configuration Handbook, Volume 1
Device Configuration Pins
Device
Configuration
Pins
Tables 5–10 through 5–12 describe the connections and functionality of all
the configuration related pins on the Cyclone device. Table 5–10
describes the dedicated configuration pins. These pins are required to be
connected properly on your board for successful configuration. Some of
these pins may not be required for your configuration schemes.
Table 5–10. Dedicated Cyclone Device Configuration Pins (Part 1 of 3)
User
Mode
Pin Name
Configuration
Scheme
Pin Type
Description
MSEL1
MSEL0
–
All
Input
Two-bit configuration input that set the Cyclone
device configuration scheme (see Table 5–2). Use
these pins to select the Cyclone configuration
schemes for the appropriate connections. These pins
must remain at a valid state during power-up before
nCONFIG is pulled low to initiate a reconfiguration
and during configuration. This pin uses Schmitt trigger
input buffers.
nCONFIG
–
All
Input
Configuration control input. Pulling this pin low during
user-mode causes the FPGA to lose its configuration
data, enter a reset state, and tri-state all I/O pins.
Returning this pin to a logic high initiates a
reconfiguration. If the configuration scheme uses an
enhanced configuration device or EPC2 device, the
nCONFIG pin can be tied directly to VC C or to the
configuration device's nINIT_CONF pin. This pin
uses Schmitt trigger input buffers
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August 2004
Configuring Cyclone FPGAs
Table 5–10. Dedicated Cyclone Device Configuration Pins (Part 2 of 3)
User
Mode
Pin Name
nSTATUS
–
Configuration
Scheme
All
Pin Type
Description
Bidirectional The device drives nSTATUS low immediately after
open-drain power-up and releases it within 5 µs. (When using a
configuration device, the configuration device holds
nSTATUS low for up to 200 ms.)
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the
nSTATUS pin low during configuration or initialization,
the target device enters an error state. Driving
nSTATUS low after configuration and initialization
does not affect the configured device.
If the design uses a configuration device, driving
nSTATUS low causes the configuration device to
attempt to configure the FPGA, but since the FPGA
ignores transitions on nSTATUS in user-mode, the
FPGA does not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low. The
OE and nCS pins in the enhanced configuration
devices and EPC2 devices have optional internal
programmable pull-up resistors. If the design uses
internal pull-up resistors, do not use external 10-kΩ
pull-up resistors on these pins. This pin uses Schmitt
trigger input buffers
CONF_DONE –
All
Bidirectional Status output. The target device drives the
open-drain CONF_DONE pin low before and during configuration.
Once all configuration data is received without error
and the initialization clock cycle starts, the target
device releases CONF_DONE.
Status input. After all data is received and
CONF_DONE goes high, the target device initializes
and enters user mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The OE and nCS pins in the enhanced configuration
devices and EPC2 devices have optional internal
programmable pull-up resistors. If the design uses
internal pull-up resistors, do not use external 10-kΩ
pull-up resistors on these pins. This pin uses Schmitt
trigger input buffers
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August 2004
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Configuration Handbook, Volume 1
Device Configuration Pins
Table 5–10. Dedicated Cyclone Device Configuration Pins (Part 3 of 3)
User
Mode
Pin Name
Configuration
Scheme
Pin Type
Description
DCLK
–
ASDO
I/O in PS AS
mode,
N/A in AS
mode
Output
Control signal from the Cyclone FPGA to the serial
configuration device in AS mode used to read out
configuration data.
nCSO
I/O in PS AS
mode,
N/A in AS
mode
Output
Output control signal from the Cyclone FPGA to the
serial configuration device in AS mode that enables
the configuration device.
nCE
–
All
Input
Active-low chip enable. The nCE pin activates the
device with a low signal to allow configuration. The
nCE pin must be held low during configuration,
initialization, and user mode. In single device
configuration, tie the nCE pin low. In multi-device
configuration, the first device’s nCE pin is tied low
while its nCEO pin is connected to nCE of the next
device in the chain. Hold the nCE pin low for
programming the FPGA via JTAG. This pin uses
Schmitt trigger input buffers
nCEO
–
All
Output
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds
the next device's nCE pin. The nCEO of the last
device in the chain is left floating.
DATA0
–
All
Input
Data input. In serial configuration mode, bit-wide
configuration data is presented to the target device on
the DATA0 pin. Toggling DATA0 after configuration
does not affect the configured device. This pin uses
Schmitt trigger input buffers
PS
AS
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Configuration Handbook, Volume 1
Input (PS)
In PS configuration, the clock input clocks data from
Output (AS) an external source into the target device. Data is
latched into the FPGA on the rising edge of DCLK. In
AS configuration, DCLK is an output from the Cyclone
FPGA that provides timing for the configuration
interface. After configuration, the logic levels on this
pin do not affect the Cyclone FPGA. This pin uses
Schmitt trigger input buffers
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Altera Corporation
August 2004
Configuring Cyclone FPGAs
Table 5–11 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-ups.
Table 5–11. Optional Cyclone Device Configuration Pins
Pin Name
CLKUSR
User Mode
Pin Type
Input
N/A if option is
on, I/O if option is
off
Description
Optional user-supplied clock input. Synchronizes the
initialization of one or more devices. This pin is enabled by
turning on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software.
INIT_DONE N/A if option is
Output
Status pin. Can be used to indicate when the device has
on, I/O if option is open-drain initialized and is in user mode. The INIT_DONE pin must be
off
pulled to VCC with a 10-kΩ resistor. The INIT_DONE pin drives
low during configuration. Before and after configuration, the
INIT_DONE pin is released and is pulled to VCC by an external
pull-up resistor. Because INIT_DONE is tri-stated before
configuration, it is pulled high by the external pull-up resistor.
Thus, the monitoring circuitry must be able to detect a low-tohigh transition. This pin is enabled by turning on the Enable
INIT_DONE output option in the Quartus II software.
DEV_OE
N/A if the option
is on, I/O if the
option is off.
Input
Optional pin that allows the user to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated;
when this pin is driven high, all I/O pins behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if the option
is on, I/O if the
option is off.
Input
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared;
when this pin is driven high, all registers behave as programmed.
This pin is enabled by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.
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August 2004
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Configuration Handbook, Volume 1
Device Configuration Pins
Table 5–12 describes the dedicated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions.
Table 5–12. Dedicated JTAG Pins
Pin Name
User
Pin Type
Mode
TDI
N/A
Input
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to VC C . This pin
uses Schmitt trigger input buffers
TDO
N/A
Output
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS
is evaluated on the rising edge of TCK. If the JTAG interface is not required on
the board, the JTAG circuitry can be disabled by connecting this pin to VC C . This
pin uses Schmitt trigger input buffers
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting this pin to ground. This
pin uses Schmitt trigger input buffers
Description
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August 2004
Chapter 6. Configuring
APEX II Devices
CF51004-2.0
Introduction
APEXTM II devices can be configured using one of four configuration
schemes. All configuration schemes use either a microprocessor or
configuration device.
APEX II devices can be configured using the passive serial (PS), fast
passive parallel (FPP), passive parallel asynchronous (PPA), and Joint
Test Action Group (JTAG) configuration schemes. The configuration
scheme used is selected by driving the APEX II device MSEL1 and MSEL0
pins either high or low as shown in Table 6–1. If your application only
requires a single configuration mode, the MSEL pins can be connected to
VCC (VCCIO of the I/O bank where the MSEL pin resides) or to ground. If
your application requires more than one configuration mode, you can
switch the MSEL pins after the FPGA is configured successfully. Toggling
these pins during user-mode does not affect the device operation;
however, the MSEL pins must be valid before a reconfiguration is
initiated.
Table 6–1. APEX II Configuration Schemes
MSEL1
MSEL0
Configuration Scheme
0
0
PS
1
0
FPP
1
1
PPA
(1)
(1)
JTAG Based (2)
Notes to Table 6–1:
(1)
(2)
Altera Corporation
July 2004
Do not leave the MSEL pins floating; connect them to a low- or high-logic level.
These pins support the non-JTAG configuration scheme used in production. If
only JTAG configuration is used, you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means MSEL pin settings are ignored.
Core Version a.b.c variable
6–1
Preliminary
Passive Serial Configuration
Table 6–2 shows the approximate configuration file sizes for APEX II
devices.
Table 6–2. APEX II Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
Data Size (Bytes)
EP2A15
4,358,512
544,814
EP2A25
6,275,200
784,400
EP2A40
9,640,528
1,208,320
EP2A70
17,417,088
2,177,136
Use the data in Table 6–2 only to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II or MAX+PLUS® II
software, all designs targeted for the same device will have the same
configuration file size.
The following chapter describes in detail how to configure APEX II
devices using the supported configuration schemes. The last section
describes the device configuration pins available. In this chapter, the
generic term device(s) or FPGA(s) will include all APEX II devices.
f
Passive Serial
Configuration
For more information on setting device configuration options or creating
configuration files, see Section II, Software Settings, in Volume 2.
You can perform APEX II PS configuration using an Altera configuration
device, an intelligent host (e.g., a microprocessor or Altera® MAX®
device), or a download cable.
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure APEX II devices
using a serial configuration bitstream. Configuration data is stored in the
configuration device. Figure 6–1 shows the configuration interface
connections between the APEX II device and a configuration device.
1
6–2
Configuration Handbook, Volume 1
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring APEX II Devices
f
For more information on the enhanced configuration device and flash
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet in the Configuration Handbook.
Figure 6–1. Single Device PS Configuration Using an Enhanced Configuration
Device
VCC (1)
VCC (1)
APEX II Device
1 kΩ
(3)
GND
nCEO
(3)
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
1 kΩ
Enhanced
Configuration
Device
N.C.
nCE
GND
Notes to Figure 6–1:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2
devices only) has an internal pull-up resistor that is always active, meaning an
external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If
nINIT_CONF is not used or not available (e.g., on EPC1 devices), nCONFIG must
be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have
internal programmable pull-up resistors. If internal pull-up resistors are used,
external pull-up resistors should not be used on these pins. The internal pull-up
resistors are used by default in the Quartus II software. To turn off the internal
pull-up resistors, check the Disable nCS and OE pull-ups on configuration device
option when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8, & EPC16)
Data Sheet or the Configuration Devices for SRAM-based LUT Devices
Data Sheet.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC either directly or through a resistor. An
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Passive Serial Configuration
internal pull-up on the nINIT_CONF pin is always active in enhanced
configuration devices and EPC2 devices, which means an external pullup resistor is not required if nCONFIG is tied to nINIT_CONF.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for EPC2, EPC1, and EPC1441 devices is 200 ms (maximum),
and for enhanced configuration devices, the POR time can be set to either
100 ms or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin
is connected to GND, the POR delay is 100 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin. When both devices complete POR, they release their opendrain OE or nSTATUS pin, which is then pulled high by a pull-up resistor.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
APEX II devices have weak pull-up resistors on the user I/O pins which
are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels to begin the configuration process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up on the
OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pullup resistor is not used, an external 1-kΩ pull-up resistor on the
OE/nSTATUS line is required. Once nSTATUS is released, the FPGA is
ready to receive configuration data and the configuration stage begins.
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Configuring APEX II Devices
When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX II device receives configuration
data on its DATA0 pin and the clock is received on the DCLK pin. Data is
latched into the FPGA on the rising edge of DCLK.
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a pullup resistor. Since CONF_DONE is tied to the configuration device’s nCS
pin, the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration and EPC2 devices have an optional internal pullup resistor on the nCS pin. This option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If this internal pull-up is not used, an external 1-kΩ pull-up resistor on the
nCS/CONF_DONE line is required. A low-to-high transition on
CONF_DONE indicates configuration is complete and initialization of the
device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will supply itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices by using the CLKUSR
option. You can turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General tab of the Device &
Pin Options dialog box. Supplying a clock on CLKUSR will not affect the
configuration process. After all configuration data is accepted and
CONF_DONE goes high, APEX II devices require 40 clock cycles to
properly initialize.
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Passive Serial Configuration
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 1-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the FPGA has entered user mode. In user-mode, the user I/O
pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device drives DCLK
low and DATA high at the end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option available in the Quartus II software from the General
tab of the Device & Pin Options dialog box is turned on, the FPGA
automatically initiates reconfiguration if an error occurs. The APEX II
device will release its nSTATUS pin after a reset time-out period
(maximum of 40 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 8 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. EPC2 devices wait for 16 DCLK cycles. In this case, the
configuration device pulls its OE pin low, which in turn drives the target
device’s nSTATUS pin low. If the Auto-Restart Configuration After Error
option is set in the software, the target device resets and then releases its
nSTATUS pin after a reset time-out period (maximum of 40 µs). When
nSTATUS returns high, the configuration device tries to reconfigure the
FPGA.
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Configuring APEX II Devices
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
8 µs. When nCONFIG is pulled low, the FPGA also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE is
pulled low, this will activate the configuration device since it will see its
nCS pin drive low. Once nCONFIG returns to a logic high state and
nSTATUS is released by the FPGA, reconfiguration begins.
Figure 6–2 shows how to configure multiple devices with a configuration
device. This circuit is similar to the configuration device circuit for a
single device, except APEX II devices are cascaded for multi-device
configuration.
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Passive Serial Configuration
Figure 6–2. Multi-Device PS Configuration Using an Enhanced Configuration Device
VCC (1)
1 kΩ
APEX II Device 2
MSEL0
MSEL1
MSEL1
(3)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
GND
GND
N.C.
MSEL0
1 kΩ
Enhanced
Configuration
Device
APEX II Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
(3)
VCC (1)
nCEO
nCE
nCEO
nCE
GND
Notes to Figure 6–2:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
1
Enhanced configuration devices (EPC4, EPC8, and EPC16)
cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device’s Programmer Object File (.pof) from each project’s
SRAM Object File (.sof). You can combine multiple SOFs using the
Quartus II software.
f
For more information on how to create configuration files for multidevice configuration chains, see Section II, Software Settings, in Volume 2.
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Configuring APEX II Devices
In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they can
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLK and DATA lines are buffered
for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all FPGAs, which causes them to enter a reset
state. This behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-Restart Configuration After Error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 8 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
The enhanced configuration devices also support parallel configuration
of up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode
allows enhanced configuration devices to concurrently configure FPGAs
or a chain of FPGAs. In addition, these devices do not have to be the same
device family or density; they can be any combination of Altera FPGAs.
An individual enhanced configuration device DATA line is available for
each targeted FPGA. Each DATA line can also feed a daisy chain of FPGAs.
Figure 6–3 shows how to concurrently configure multiple devices using
an enhanced configuration device.
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Passive Serial Configuration
Figure 6–3. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
(1) VCC
APEX II Device 1
N.C.
nCEO
nCEO
(3)
1 kΩ
DCLK
DATA0
nCE
OE (3)
DATA1
DATA[2..6]
nCS (3)
APEX II Device 2
N.C.
(3)
Enhanced
Configuration
Device
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
GND
1 kΩ
VCC (1)
GND
nINIT_CONF (2)
DATA 7
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL1
MSEL0
GND
GND
APEX II Device 8
N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
nCE
GND
GND
Notes to Figure 6–3:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
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Configuring APEX II Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 6–3 to
select the appropriate configuration mode for the fastest configuration
times.
Table 6–3. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 6–3:
(1)
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus
II software. On the printed circuit board (PCB), leave the DATA3 line from
the enhanced configuration device unconnected. Figure 6–4 shows the
Quartus II Convert Programming Files window (Tools menu) setup for
this scheme.
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Passive Serial Configuration
Figure 6–4. Software Settings for Configuring Devices Using n-Bit PS Modes
Alternatively, you can daisy chain two FPGAs to one DATA line while the
other DATA lines drive one device each. For example, you could use the 2bit PS mode to drive two FPGAs with DATA Bit0 (EP2A15 and EP2A25
devices) and the third device (the EP2A40 device) with DATA Bit1. This
2-bit PS configuration scheme requires less space in the configuration
flash memory, but can increase the total system configuration time. See
Figure 6–5.
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Configuring APEX II Devices
Figure 6–5. Software Settings for Daisy Chaining Two FPGAs on One DATA
Line
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 6–6 shows multi-device
PS configuration when the APEX II devices are receiving the same
configuration data.
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–6. Multiple-Device PS Configuration Using an Enhanced Configuration Device When FPGAs
Receive the Same Data
(1) VCC
APEX II Device 1
(4) N.C.
nCEO
nCEO
(3)
1 KΩ
Enhanced
Configuration
Device
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
nCE
APEX II Device 2
(4) N.C.
(3)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
GND
1 KΩ
VCC (1)
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL1
MSEL0
GND
GND
APEX II Device 8
(4) N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
nCE
GND
GND
Notes to Figure 6–6:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
The nCEO pins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
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Configuring APEX II Devices
You can cascade several EPC2 or EPC1 devices to configure multiple
APEX II devices. The first configuration device in the chain is the master
configuration device, while the subsequent devices are the slave devices.
The master configuration device sends DCLK to the APEX II devices and
to the slave configuration devices. The first EPC device’s nCS pin is
connected to the CONF_DONE pins of the FPGAs, while its nCASC pin is
connected to nCS of the next configuration device in the chain. The last
device’s nCS input comes from the previous device, while its nCASC pin
is left floating. When all data from the first configuration device is sent, it
drives nCASC low, which in turn drives nCS on the next configuration
device. Because a configuration device requires less than one clock cycle
to activate a subsequent configuration device, the data stream is
uninterrupted.
1
Enhanced configuration devices EPC4, EPC8, and EPC16 cannot
be cascaded.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONE going high
at the end of configuration, it resets the entire chain by pulling its OE pin
low. This low signal drives the OE pin low on the slave configuration
device(s) and drives nSTATUS low on all FPGAs, causing them to enter a
reset state. This behavior is similar to the FPGA detecting an error in the
configuration data.
Figure 6–7 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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Passive Serial Configuration
Figure 6–7. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (1)
VCC (1)
VCC (1)
(3) 1 kΩ
APEX II Device 2
MSEL0
MSEL1
(2)
1 kΩ (3)
EPC2/EPC1
Device 1
APEX II Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
GND
GND
N.C.
1 kΩ
nCEO
nCEO
nCE
EPC2/EPC1
Device 2
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 6–7:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC either directly or through a resistor. An
internal pull-up resistor on the nINIT_CONF pin is always active in the
enhanced configuration devices and the EPC2 devices, which means an
external pull-up is not required if nCONFIG is tied to nINIT_CONF. If
multiple EPC2 devices are used to configure an APEX II device(s), only
the first EPC2 has its nINIT_CONF pin tied to the device’s nCONFIG pin.
You can use a single configuration chain to configure APEX II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
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Configuring APEX II Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–8 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 6–8. APEX II PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
tDSU
tCL
D0
D1
tCH
tDH
tOEZX
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 6–8:
(1)
APEX II devices enter user-mode 40 clock cycles after CONF_DONE goes high. The initialization clock can come from
the APEX II internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
PS Configuration Using a Microprocessor
In the PS configuration scheme, an intelligent host (e.g., a microprocessor
or CPLD) can transfer configuration data from a storage device (e.g., flash
memory) to the target APEX II devices. Configuration data can be stored
in RBF, HEX, or TTF format. Figure 6–9 shows the configuration interface
connections between the APEX II device and a microprocessor for single
device configuration.
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Passive Serial Configuration
Figure 6–9. Single Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
(1) VCC
1 kΩ
VCC (1)
APEX II Device
1 kΩ
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCEO
nCE
Microprocessor
GND
N.C.
GND
DATA0
nCONFIG
DCLK
Note to Figure 6–9:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal
for the device.
Upon power-up, the APEX II device goes through a POR for
approximately 5 µs. During POR, the device resets and holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins are tri-stated. APEX II devices have weak pull-up
resistors on the user I/O pins which are on before and during
configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
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VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
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July 2004
Configuring APEX II Devices
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should place the configuration data one
bit at a time on the DATA0 pin. The least significant bit (LSB) of each data
byte must be sent first.
The APEX II device receives configuration data on its DATA0 pin and the
clock is received on the DCLK pin. Data is latched into the FPGA on the
rising edge of DCLK. Data is continuously clocked into the target device
until CONF_DONE goes high. After the FPGA has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 1-kΩ pull-up resistor. A low-tohigh transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
APEX II devices require 40 clock cycles to initialize properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-up resistors and
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Passive Serial Configuration
will function as assigned in your design. To ensure DCLK and DATA are
not left floating at the end of configuration, the microprocessor must
drive them either high or low, whichever is convenient on your board.
Handshaking signals are not used in PS configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option (available in the Quartus II software from
the General tab of the Device & Pin Options dialog box) is turned on, the
APEX II device releases nSTATUS after a reset time-out period (maximum
of 40 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the microprocessor can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the
microprocessor must generate a low-to-high transition (with a low pulse
of at least 8 µs) on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 8 µs. When nCONFIG is pulled low, the FPGA also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high state and nSTATUS is released by the
FPGA, reconfiguration begins.
Figure 6–10 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the PS configuration circuit for a
single device, except APEX II devices are cascaded for multi-device
configuration.
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Configuring APEX II Devices
Figure 6–10. Multi-Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
VCC (1)
VCC (1)
1 kΩ
1 kΩ
APEX II Device 1
APEX II Device 2
MSEL1
CONF_DONE
nSTATUS
nCE
Microprocessor
MSEL1
MSEL0
CONF_DONE
GND
nCEO
MSEL0
nSTATUS
GND
nCE
GND
nCEO
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C.
Note to Figure 6–10:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PS configuration the first device’s nCE pin is connected to
GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they can require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLK and DATA lines
are buffered for every fourth device. Because all device CONF_DONE pins
are tied together, all devices initialize and enter user mode at the same
time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
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Passive Serial Configuration
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 6–11 shows multi-device
PS configuration when both APEX II devices are receiving the same
configuration data.
Figure 6–11. Multiple-Device PS Configuration Using a Microprocessor When Both FPGAs Receive the Same
Data
Memory
ADDR
DATA0
VCC (1)
VCC (1)
1 kΩ
1 kΩ
APEX II Device
APEX II Device
MSEL1
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
CONF_DONE
GND
nCEO
GND
nCE
N.C. (2)
GND
MSEL0
nSTATUS
nCEO
GND
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (2)
Notes to Figure 6–11:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
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Configuring APEX II Devices
You can use a single configuration chain to configure APEX II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–12 shows the timing waveform for the PS configuration for
APEX II devices using a microprocessor.
Figure 6–12. APEX II PS Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (1)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (2)
tCF2CD
tST2CK
tCH tCL
(3)
DCLK
tDH
DATA
Bit 0 Bit 1 Bit 2 Bit 3
Bit n
(3)
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 6–12:
(1)
(2)
(3)
Upon power-up, the APEX II device holds nSTATUS low for not more than 5 µs after VCC reaches its minimum
requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is more
convenient.
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July 2004
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Passive Serial Configuration
Table 6–4 defines the timing parameters for APEX II devices for PS
configuration.
Table 6–4. PS Timing Parameters for APEX II Devices Note (1)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
Max
Units
200
ns
200
ns
µs
40
µs
1 (2)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
7.5
ns
tCL
DCLK low time
7.5
ns
tCLK
DCLK period
15
ns
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (3)
2
66
MHz
8
µs
Notes to Table 6–4:
(1)
(2)
(3)
This information is preliminary.
This value is applicable if users do not delay configuration by extending the nSTATUS low pulse width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX II devices to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver allows you to configure Altera’s
FPGAs through the ByteBlasterMV cable in PS mode. The MicroBlaster
software driver supports a RBF programming input file and is targeted
for embedded passive serial configuration. The source code is developed
for the Windows NT operating system, although you can customize it to
run on other operating systems. For more information on the
MicroBlaster software driver, go to the Altera web site
(http://www.altera.com).
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July 2004
Configuring APEX II Devices
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB Blaster universal serial bus (USB) port download cable,
MasterBlasterTM serial/USB communications cable, ByteBlasterTM II
parallel port download cable, and the ByteBlasterMVTM parallel port
download cable.
In PS configuration with a download cable, an intelligent host (e.g., a PC)
transfers data from a storage device to the FPGA via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Upon power-up, the APEX II device goes through a POR for
approximately 5 µs. During POR, the device resets and holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins are tri-stated. APEX II devices have weak pull-up
resistors on the user I/O pins which are on before and during
configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
The configuration cycle consists of 3 stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration,
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high.
When using a download cable, setting the Auto-Restart Configuration After
Error option does not affect the configuration cycle because you must
manually restart configuration in the Quartus II software when an error
occurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)
option has no affect on the device initialization since this option is
disabled in the SOF when programming the FPGA using the Quartus II
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Passive Serial Configuration
programmer and download cable. Therefore, if you turn on the CLKUSR
option, you do not need to provide a clock on CLKUSR when you are
configuring the FPGA with the Quartus II programmer and a download
cable. Figure 6–13 shows PS configuration for APEX II devices using a
USB Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV cable.
Figure 6–13. PS Configuration Using a USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV Cable
VCC (1)
VCC (1)
1 kΩ
(2)
1 kΩ
VCC (1)
APEX II Device
MSEL0
VCC (1)
1 kΩ
(2)
MSEL1
1 kΩ
VCC (1)
1 kΩ
CONF_DONE
nSTATUS
GND
nCE
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
GND
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 6–13:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB
Blaster, MasterBlaster (VIO pin), ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable
is the only configuration scheme used on your board. This is to ensure that DATA0
and DCLK are not left floating after configuration. For example, if you are also
using a configuration device, the pull-up resistors on DATA0 and DCLK are not
needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver.
VIO should match the device’s VCCIO. Refer to the MasterBlaster Serial/USB
Communications Cable Data Sheet for this value. In the ByteBlasterMV, this pin is
a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE
when it is used for Active Serial programming, otherwise it is a no connect.
You can use a download cable to configure multiple APEX II devices by
connecting each device’s nCEO pin to the subsequent device’s nCE pin.
The first device’s nCE pin is connected to GND while its nCEO pin is
connected to the nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
All other configuration pins, nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE are connected to every device in the chain. Because all
CONF_DONE pins are tied together, all devices in the chain initialize and
enter user mode at the same time.
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Configuring APEX II Devices
In addition, because the nSTATUS pins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-Restart
Configuration After Error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
Figure 6–14 shows how to configure multiple APEX II devices with a
download cable.
Figure 6–14. Multi-Device PS Configuration using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV Cable
VCC (1)
1 kΩ
1 kΩ
APEX II Device 1
VCC (1)
1 kΩ
MSEL1
(2)
VCC (1)
VCC (1)
1 kΩ
CONF_DONE
nSTATUS
DCLK
MSEL0
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
(2)
Pin 1
VCC
GND
VIO (3)
GND
nCEO
nCE
1 kΩ
GND
DATA0
nCONFIG
MSEL0
MSEL1
GND
CONF_DONE
nSTATUS
DCLK
GND
nCE
nCEO
N.C.
DATA0
nCONFIG
APEX II Device 2
Notes to Figure 6–14:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
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Passive Serial Configuration
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration device from the target device(s) and cable. One way to
isolate the configuration device is to add logic, such as a multiplexer, that
can select between the configuration device and the cable. The
multiplexer chip should allow bidirectional transfers on the nSTATUS
and CONF_DONE signals. Another option is to add switches to the five
common signals (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
between the cable and the configuration device. The last option is to
remove the configuration device from the board when configuring the
FPGA with the cable. Figure 6–15 shows a combination of a configuration
device and a download cable to configure an FPGA.
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Configuring APEX II Devices
Figure 6–15. PS Configuration with a Download Cable and Configuration Device Circuit
VCC (1)
1 kΩ
1 kΩ
(5)
APEX II Device
VCC (1)
(4)
MSEL0
MSEL1
Download Cable
10-Pin Male Header
(PS Mode)
(5) VCC (1)
1 kΩ
Pin 1
CONF_DONE
nSTATUS
DCLK
VCC
GND
VIO (2)
GND
nCE
nCEO
N.C.
GND
DATA0
nCONFIG
(3)
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (5)
nCS (5)
(3)
nINIT_CONF (4)
Notes to Figure 6–15:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to an
APEX II device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-up resistors on configuration device option when generating programming files.
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following data sheets.
■
■
■
■
Altera Corporation
July 2004
USB Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
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Fast Passive Parallel Configuration
Fast Passive
Parallel
Configuration
Fast Passive Parallel (FPP) configuration in APEX II devices is designed
to meet the continuously increasing demand for faster configuration
times. APEX II devices are designed with the capability of receiving bytewide configuration data per clock cycle, and guarantee a configuration
time of less than 100 ms with a 66-MHz configuration clock.
FPP configuration of APEX II devices can be performed using an Altera
enhanced configuration device or an intelligent host, such as a
microprocessor.
FPP Configuration Using an Enhanced Configuration Device
In the FPP configuration scheme, an enhanced configuration device sends
a byte of configuration data every DCLK cycle to the APEX II device.
Configuration data is stored in the configuration device. Figure 6–16
shows the configuration interface connections between the APEX II
device and the enhanced configuration device for single device
configuration.
1
f
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
For more information on the enhanced configuration device and flash
interface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8, &
EPC16) Data Sheet in the Configuration Handbook.
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Configuring APEX II Devices
Figure 6–16. Single Device FPP Configuration Using an Enhanced
Configuration Device
VCC (1)
APEX II Device
1 kΩ
(3) (3)
MSEL1
MSEL0
GND
nCEO
1 kΩ
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
VCC
VCC (1)
N.C.
nCE
GND
Notes to Figure 6–16:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin
does not need to be connected if its functionality is not used. If nINIT_CONF is not
used, nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option when
generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Operating Conditions table of the Enhanced
Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet in the
Configuration Handbook.
When using enhanced configuration devices, nCONFIG of the FPGA can
be connected to nINIT_CONF, which allows the INIT_CONF JTAG
instruction to initiate FPGA configuration. The nINIT_CONF pin does
not need to be connected if its functionality is not used. If nINIT_CONF is
not used, nCONFIG must be pulled to VCC either directly or through a
resistor. An internal pull-up on the nINIT_CONF pin is always active in
the enhanced configuration devices, which means an external pull-up is
not required if nCONFIG is tied to nINIT_CONF.
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Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for enhanced configuration devices can be set to either 100 ms
or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin is
connected to GND, the POR delay is 100 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin. When both devices complete POR, they release their opendrain OE or nSTATUS pin, which is then pulled high by a pull-up resistor.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
APEX II devices have weak pull-up resistors on the user I/O pins which
are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of 3
stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration devices have an optional internal pull-up on the OE pin.
This option is available in the Quartus II software from the General tab
of the Device & Pin Options dialog box. If this internal pull-up is not
used, an external 1-kΩ pull-up on the OE/nSTATUS line is required. Once
nSTATUS is released the FPGA is ready to receive configuration data and
the configuration stage begins.
When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX II device receives configuration
data on its DATA[7..0] pins and the clock is received on the DCLK pin.
A byte of data is latched into the FPGA on the rising edge of DCLK.
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Configuring APEX II Devices
After the FPGA has received all configuration data successfully it releases
the open-drain CONF_DONE pin, which is pulled high by a pull-up
resistor. Since CONF_DONE is tied to the configuration device’s nCS pin,
the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration devices have an optional internal pull-up on the
nCS pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pullup is not used, an external 1kΩ pull-up on the nCS/CONF_DONE line is
required. A low to high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. You also have the
flexibility to synchronize initialization of multiple devices by using the
CLKUSR option. The Enable user-supplied start-up clock (CLKUSR) option
can be turned on in the Quartus II software from the General tab of the
Device & Pin Options dialog box. Supplying a clock on CLKUSR will not
affect the configuration process. After all configuration data has been
accepted and CONF_DONE goes high, APEX II devices require 40 clock
cycles to initialize properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. In user-mode, the user
I/O pins will no longer have weak pull-ups and will function as assigned
in your design. The enhanced configuration device will drive DCLK low
and DATA[7..0] high at the end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option-available in the Quartus II software from the General
tab of the Device & Pin Options dialog box-is turned on, the FPGA will
automatically initiate reconfiguration if an error occurs. The APEX II
device will release its nSTATUS pin after a reset time-out period
(maximum of 40 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
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this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 8 µs to restart
configuration. The external system can pulse nCONFIG, if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. In this case, the configuration device pulls its OE pin
low, which in turn drives the target device’s nSTATUS pin low. If the
Auto-Restart Configuration After Error option is set in the software, the
target device resets and then release its nSTATUS pin after a reset timeout period (maximum of 40 µs). When nSTATUS returns high, the
configuration device will try to reconfigure the FPGA.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, you should use the CLKUSR option to synchronize
the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain will
initialize together if their CONF_DONE pins are tied together.
If the optional CLKUSR pin is being used and nCONFIG is pulled low to
restart configuration during device initialization, you need to ensure
CLKUSR continues toggling during the time nSTATUS is low (maximum
of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
8 µs. When nCONFIG is pulled low, the FPGA also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE is
pulled low, this will activate the configuration device since it will see its
nCS pin drive low. Once nCONFIG returns to a logic high state and
nSTATUS is released by the FPGA, reconfiguration begins.
Figure 6–17 shows how to configure multiple APEX II devices with an
enhanced configuration device. This circuit is similar to the configuration
device circuit for a single device, except the APEX II devices are cascaded
for multi-device configuration.
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Configuring APEX II Devices
Figure 6–17. Multi-Device FPP Configuration Using an Enhanced Configuration Device
VCC (1)
VCC (1)
1 kΩ
(3)
(3)
VCC
APEX II Device 2
Enhanced
Configuration Device
APEX II Device 1
MSEL1
DCLK
MSEL1
DCLK
MSEL0
DATA[7..0]
MSEL0
DATA[7..0]
nSTATUS
GND
N.C.
VCC
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCEO
nCE
DCLK
DATA[7..0]
OE (3)
nCS (3)
nSTATUS
GND
nCEO
1 kΩ
nINIT_CONF (2)
nCE
GND
Notes to Figure 6–17:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-up resistors on configuration device option when generating programming files.
1
Enhanced configuration devices (EPC4/8/16) cannot be
cascaded.
When performing multi-device configuration, you must generate the
configuration device’s POF from each project’s SOF. You can combine
multiple SOFs using the Quartus II software.
f
For more information on how to create configuration files for multidevice configuration chains, see Section II, Software Settings, in Volume 2.
In multi-device FPP configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
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DATA[7..0], and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they may require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLK and DATA lines
are buffered for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all FPGAs, which causes them to enter a reset
state. This behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-Restart Configuration After Error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 8 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–18 shows
multi-device FPP configuration when both APEX II devices are receiving
the same configuration data.
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Configuring APEX II Devices
Figure 6–18. Multiple-Device FPP Configuration Using an Enhanced Configuration Device When Both FPGAs
Receive the Same Data
VCC (1)
VCC (1)
1 kΩ
(3)
(3)
APEX II Device
VCC
MSEL1
DCLK
MSEL1
DCLK
MSEL0
DATA[7..0]
MSEL0
DATA[7..0]
nSTATUS
GND
(4) N.C.
Enhanced
Configuration Device
APEX II Device
VCC
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCEO
(4) N.C.
nCE
DCLK
DATA[7..0]
OE (3)
nSTATUS
GND
nCEO
1 kΩ
nCS (3)
nINIT_CONF (2)
nCE
GND
GND
Notes to Figure 6–18:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single enhanced configuration chain to configure multiple
APEX II devices with other Altera devices that support FPP
configuration, such as Stratix® and Stratix GX devices. To ensure that all
devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–19 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
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Figure 6–19. APEX II FPP Configuration Using an Enhanced Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tCE
tLC
DCLK
DATA
Driven High
bit/byte bit/byte
1
2
bit/byte
n
tOE
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 6–19:
(1)
APEX II devices enter user mode 40 clock cycles after CONF_DONE goes high. The initialization clock can come from
the APEX II internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, & EPC16) Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, an intelligent host, such as a
microprocessor or CPLD, can transfer configuration data from a storage
device, such as flash memory, to the target APEX II device. Configuration
data can be stored in RBF, HEX or TTF format. Figure 6–20 shows the
configuration interface connections between the APEX II device and a
microprocessor for single device configuration.
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Configuring APEX II Devices
Figure 6–20. Single Device FPP Configuration Using a Microprocessor
Memory
ADDR DATA[7..0]
VCC (1)
1 kΩ
VCC (1)
1 kΩ
APEX II Device
VCC
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
nCEO
GND
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Note to Figure 6–20:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration,
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should place the configuration data one
byte at a time on the DATA[7..0] pins.
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The APEX II device receives configuration data on its DATA[7..0] pins
and the clock is received on the DCLK pin. Data is latched into the FPGA
on the rising edge of DCLK. Data is continuously clocked into the target
device until CONF_DONE goes high. After the FPGA has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 1-kΩ pull-up resistor. A low-tohigh transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
APEX II devices require 40 clock cycles to initialize properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The microprocessor
must be able to detect this low-to-high transition which signals the FPGA
has entered user mode. In user-mode, the user I/O pins will no longer
have weak pull-ups and will function as assigned in your design. When
initialization is complete, the FPGA enters user mode.
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Configuring APEX II Devices
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the microprocessor must take care to drive them either
high or low, whichever is convenient on your board. The DATA[7..1]
pins are available as user I/O pins after configuration. When the FPP
scheme is chosen in the Quartus II software, as a default these I/O pins
are tri-stated in user mode and should be driven by the microprocessor.
To change this default option in the Quartus II software, select the DualPurpose Pins tab of the Device & Pin Options dialog box.
Handshaking signals are not used in FPP configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of 40
µs). After nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 8 µs)
on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 8 µs. When nCONFIG is pulled low, the FPGA also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high state and nSTATUS is released by the
FPGA, reconfiguration begins.
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Figure 6–21 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the FPP configuration circuit for
a single device, except the APEX II devices are cascaded for multi-device
configuration.
Figure 6–21. Multi-Device FPP Configuration Using a Microprocessor
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
1 kΩ
APEX II Device 1
1 kΩ
VCC
APEX II Device 2
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
VCC
MSEL1
CONF_DONE
GND
nCEO
MSEL0
nSTATUS
nCE
nCEO
GND
N.C.
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Note to Figure 6–21:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device FPP configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. You should pay special attention to the configuration signals
because they may require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLK and DATA lines
are buffered for every fourth device. Because all device CONF_DONE pins
are tied together, all devices initialize and enter user mode at the same
time.
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Configuring APEX II Devices
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–22 shows
multi-device FPP configuration when both APEX II devices are receiving
the same configuration data.
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Fast Passive Parallel Configuration
Figure 6–22. Multiple-Device FPP Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
Memory
VCC (1) VCC (1)
ADDR DATA[7..0]
1 kΩ
APEX II Device
1 kΩ
VCC
APEX II Device
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
nCEO
VCC
MSEL1
CONF_DONE
MSEL0
nSTATUS
GND
N.C. (2)
nCEO
nCE
GND
N.C. (2)
GND
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Notes to Figure 6–22:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure APEX II devices
with other Altera devices that support FPP configuration, such as Stratix.
To ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–23 shows the timing waveform for the FPP configuration
scheme using a microprocessor.
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July 2004
Configuring APEX II Devices
Figure 6–23. APEX II FPP Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
(1) nSTATUS
tSTATUS
tCF2ST0
t
CLK
(2) CONF_DONE
tCF2CD
tST2CK
tCH tCL
(3)
DCLK
tDH
DATA
Byte 0 Byte 1 Byte 2 Byte 3
(3)
User Mode
Byte n
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 6–23:
(1)
(2)
(3)
Upon power-up, the APEX II device holds nSTATUS low for not more than 5 µs after VCC reaches its minimum
requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is more
convenient. DATA[7..1] are available as user I/O pins after configuration and the state of theses pins depends on
the design programmed into the device.
Table 6–5 defines the timing parameters for APEX II devices for FPP
configuration.
Table 6–5. FPP Timing Parameters for APEX II Devices (Part 1 of 2)
Symbol
Parameter
Note (1)
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
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July 2004
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µs
40 (2)
µs
1 (2)
µs
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Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Table 6–5. FPP Timing Parameters for APEX II Devices (Part 2 of 2)
Symbol
Note (1)
Parameter
Min
Max
Units
tCH
DCLK high time
7.5
ns
tCL
DCLK low time
7.5
ns
tCLK
DCLK period
15
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (3)
2
ns
66
MHz
8
µs
Notes to Table 6–5:
(1)
(2)
(3)
This information is preliminary.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver supports a RBF programming input
file and is targeted for embedded fast passive parallel configuration. The
source code is developed for the Windows NT operating system,
although you can customize it to run on other operating systems. For
more information on the MicroBlaster software driver, go to the Altera
web site (http://www.altera.com).
Passive Parallel
Asynchronous
Configuration
Passive Parallel Asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target APEX II device.
Configuration data can be stored in TTF, RBF or HEX format. The host
system outputs byte-wide data and the accompanying strobe signals to
the FPGA. When using PPA, you should pull the DCLK pin high through
a 1-kΩ pull-up resistor to prevent unused configuration input pins from
floating.
Figure 6–24 shows the configuration interface connections between the
FPGA and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCS and CS. The address decoder allows the
microprocessor to select the APEX II device by accessing a particular
address, which simplifies the configuration process. The nCS and CS pins
must be held active during configuration and initialization.
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July 2004
Configuring APEX II Devices
Figure 6–24. Single Device PPA Configuration Using a Microprocessor Note (1)
Address Decoder
ADDR
VCC (2)
Memory
1 kΩ
VCC (2)
ADDR DATA[7..0]
1 kΩ
APEX II Device
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL1
MSEL0
nCEO
N.C.
VCC (2)
1 kΩ
DCLK
Notes to Figure 6–24:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if only one chip-select input is used, the other must be tied
to the active state. For example, nCS can be tied to ground while CS is
toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 6–6.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
f
Altera Corporation
July 2004
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX II Programmable Logic Device Family Data
Sheet.
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Passive Parallel Asynchronous Configuration
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the APEX II device is processing
the byte of configuration data.
During the time RDYnBSY is low, the APEX II device internally processes
the configuration data using its internal oscillator (typically 10 MHz).
When the device is ready for the next byte of configuration data, it will
drive RDYnBSY high. If the microprocessor senses a high signal when it
polls RDYnBSY, the microprocessor sends the next byte of configuration
data to the FPGA.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Data should not be driven onto the data bus while nRS is low because it
will cause contention on the DATA7 pin. If the nRS pin is not used to
monitor configuration, it should be tied high.
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY(max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The tBUSY, tRDY2WS and
tW2SB timing specifications are listed in Table 6–6.
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Configuring APEX II Devices
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. After the FPGA
has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 1-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high, APEX
II devices require 40 clock cycles to initialize properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-ups and will
function as assigned in your design. When initialization is complete, the
FPGA enters user mode.
To ensure DATA0 is not left floating at the end of configuration, the
microprocessor must take care to drive them either high or low,
whichever is convenient on your board. After configuration, the nCS, CS,
nRS, nWS, RDYnBSY, and DATA[7..1] pins can be used as user I/O pins.
When the PPA scheme is chosen in the Quartus II software, as a default
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Passive Parallel Asynchronous Configuration
these I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of 40
µs). After nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 8 µs)
on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE has not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 8 µs. When nCONFIG is pulled low, the FPGA also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high state and nSTATUS is released by the
FPGA, reconfiguration begins.
Figure 6–25 shows how to configure multiple APEX II devices using a
microprocessor. This circuit is similar to the PPA configuration circuit for
a single device, except the devices are cascaded for multi-device
configuration.
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Configuring APEX II Devices
Figure 6–25. Multi-Device PPA Configuration Using a Microprocessor
VCC (2)
VCC (2)
1 kΩ
(2) VCC
1 kΩ
1 kΩ
Address Decoder
VCC (2)
ADDR
Memory
1 kΩ
ADDR DATA[7..0]
APEX II Device 1
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Microprocessor
APEX II Device 2
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL1
MSEL0
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C.
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 6–25:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPA configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
Each device’s RDYnBSY pin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSY pins can feed an AND gate and the output of the AND gate can
feed the microprocessor. For example, if you have 2 devices in a PPA
configuration chain, the second device’s RDYnBSY pin will be high during
the time that the first device is being configured. When the first device has
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Passive Parallel Asynchronous Configuration
been successfully configured, it will driven nCEO low to activate the next
device in the chain and drive its RDYnBSY pin high. Therefore, since
RDYnBSY signal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the AND gate.
The nRS signal can be used in multi-device PPA chain since the APEX II
device will tri-state its DATA[7..0] pins before configuration and after
configuration before entering user-mode to avoid contention. Therefore,
only the device that is currently being configured will respond to the nRS
strobe by asserting DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRS and CONF_DONE) are connected to every device in the chain.
You should pay special attention to the configuration signals because
they may require buffering to ensure signal integrity and prevent clock
skew problems. Specifically, ensure that the DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..1], nCS, CS, nWS,
nRS and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they
may require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–26 shows
multi-device PPA configuration when both devices are receiving the
same configuration data.
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July 2004
Configuring APEX II Devices
Figure 6–26. Multiple-Device PPA Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
VCC (2)
VCC (2)
1 kΩ
(2) VCC
1 kΩ
1 kΩ
Address Decoder
VCC (2)
ADDR
Memory
1 kΩ
ADDR DATA[7..0]
APEX II Device
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
APEX II Device
nCE
GND
DCLK
nCEO
Microprocessor
nWS
nRS
nCONFIG
RDYnBSY
N.C. (3)
VCC
MSEL1
MSEL0
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C. (3)
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 6–26:
(1)
(2)
(3)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure APEX II devices
with other Altera devices that support PPA configuration, such as Stratix,
Mercury, APEX 20K, ACEX 1K, and FLEX 10KE devices. To ensure that
all devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–27 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
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Passive Parallel Asynchronous Configuration
Figure 6–27. APEX II PPA Configuration Timing Waveform
tCFG
tCF2ST1
nCONFIG
nSTATUS (1)
CONF_DONE (2)
Byte 0
DATA[7..0]
Byte 1
Byte n 1
Byte n
(4)
tCSH
(4)
tDSU
(3) CS
tCF2WS
tCSSU
tDH
(4)
(3) nCS
tWSP
(4)
nWS
tRDY2WS
(4)
RDYnBSY
tWS2B
tSTATUS
tBUSY
tCF2ST0
tCF2CD
User I/Os
tCD2UM
High-Z
High-Z
User-Mode
INIT_DONE
Notes to Figure 6–27:
(1)
(2)
(3)
(4)
Upon power-up, the APEX II device holds nSTATUS low for not more than 5 µs after VCCINT reaches its minimum
requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Figure 6–28 shows the timing waveform for the PPA configuration
scheme when using a strobed nRS and nWS signal.
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July 2004
Configuring APEX II Devices
Figure 6–28. APEX II PPA Configuration Timing Waveform Using nRS & nWS
tCF2ST1
tCFG
nCONFIG
(1) nSTATUS
tSTATUS
tCF2SCD
(2) CONF_DONE
tCSSU
(4)
nCS (3)
tCSH
(4)
CS (3)
tDH
Byte 0
DATA[7..0]
(4)
Byte n
Byte 1
tDSU
(4)
nWS
tWSP
nRS
tRS2WS
tWS2RS
tCF2WS
(4)
tWS2RS
tRSD7
INIT_DONE
tRDY2WS
User I/O
High-Z
User-Mode
tWS2B
(4)
DATA7/RDYnBSY (5)
tCD2UM
tBUSY
Notes to Figure 6–28:
(1)
(2)
(3)
(4)
(5)
Upon power-up, the APEX II device holds nSTATUS low for not more than 5 µs after VCCINT reaches its minimum
requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
DATA7 is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Table 6–6 defines the timing parameters for APEX II devices for PPA
configuration.
Table 6–6. PPA Timing Parameters for APEX II Devices (Part 1 of 2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Note (1)
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
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Max
Units
200
ns
200
ns
µs
40 (2)
µs
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Configuration Handbook, Volume 1
JTAG Configuration
Table 6–6. PPA Timing Parameters for APEX II Devices (Part 2 of 2)
Symbol
Parameter
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge on nWS
Note (1)
Min
Max
Units
1 (2)
µs
10
ns
tCSH
Chip select hold time after rising edge on nWS
0
ns
tCF2WS
nCONFIG high to first rising edge on nWS
40
µs
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
200
0.1
ns
50
ns
1.6
µs
tRDY2WS
RDYnBSY rising edge to nWS rising edge
50
ns
tWS2RS
nWS rising edge to nRS falling edge
200
ns
tRS2WS
nRS rising edge to nWS rising edge
200
ns
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
CONF_DONE high to user mode (3)
2
50
ns
8
µs
Notes to Table 6–6:
(1)
(2)
(3)
This information is preliminary.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX II devices to obtain this
value.
f
JTAG
Configuration
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture offers
the capability to efficiently test components on PCBs with tight lead
spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is
operating normally. The JTAG circuitry can also be used to shift
configuration data into the device.
For more information on JTAG boundary-scan testing, see Application
Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
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Configuring APEX II Devices
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. All user I/O pins are tri-stated
during JTAG configuration. APEX II devices are designed such that JTAG
instructions have precedence over any device configuration modes. This
means that JTAG configuration can take place without waiting for other
configuration modes to complete. For example, if you attempt JTAG
configuration of APEX II FPGAs during PS configuration, PS
configuration will be terminated and JTAG configuration will begin.
Table 6–7 explains each JTAG pin’s function.
Table 6–7. JTAG Pin Descriptions
Pin
Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data.
Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TDO
Test data output
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMS must be set up before
the rising edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST
Test reset input (optional)
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
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July 2004
If VCCIO of the bank where the JTAG pins reside, are tied to
3.3-V, both the I/O pins and JTAG TDO port will drive at 3.3-V
levels.
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JTAG Configuration
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV header. Configuring devices through a cable is similar to
programming devices in-system, except the TRST pin should be
connected to VCC. This ensures that the TAP controller is not reset.
Figure 6–29. shows JTAG configuration of a single APEX II device.
Figure 6–29. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
1 kΩ
(1) VCC
VCC (1)
(1) VCC
1 kΩ
1 kΩ
APEX II Device
1 kΩ
nCE (4)
GND N.C.
(2)
(2)
(2)
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
TCK
TDO
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
VCC
TRST
Pin 1
VCC
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 6–29:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
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Configuring APEX II Devices
APEX II devices have dedicated JTAG pins that always function as JTAG
pins. JTAG testing can be performed on APEX II devices both before and
after configuration, but not during configuration. The chip-wide reset
(DEV_CLRn) and chip-wide output enable (DEV_OE) pins on APEX II
devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of APEX II devices, the
dedicated configuration pins should be considered. Table 6–8 shows how
these pins should be connected during JTAG configuration.
Table 6–8. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all APEX II devices in the chain, nCE should be driven low by connecting it to ground, pulling
it low via a resistor, or driving it by some control circuitry. For devices that are also in multidevice PS, FPP, or PPA configuration chains, the nCE pins should be connected to GND during
JTAG configuration or JTAG configured in the same order as the configuration chain.
nCEO
On all APEX II devices in the chain, nCEO can be left floating or connected to the nCE of the
next device. See nCE description above.
MSEL
These pins must not be left floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG
Driven high by connecting to VCC, pulling high via a resistor, or driven by some control circuitry.
nSTATUS
Pull to VCC via a 1-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
nSTATUS pin should be pulled up to VCC individually. nSTATUS pulling low in the middle of JTAG
configuration indicates that an error has occurred.
CONF_DONE Pull to VCC via a 1-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONE pin should be pulled up to VCC individually. CONF_DONE going high at the end of
JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0
Should not be left floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 6–30 shows multi-device JTAG configuration.
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JTAG Configuration
Figure 6–30. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
(1) VCC
(1) VCC
Pin 1
VCC
(1) VCC
(2)
(2)
(2)
1 kΩ
VCC
VIO
(3)
(1) VCC
1 kΩ
1 kΩ
APEX II Device
nSTATUS
nCONFIG
MSEL0 CONF_DONE
MSEL1
nCE (4)
TRST
TDI
TDO
TMS
TCK
(1) VCC
1 kΩ
(2)
(2)
(2)
VCC
1 kΩ
APEX II Device
(1) VCC (1) VCC
(1) VCC
1 kΩ
1 kΩ
1 kΩ
APEX II Device
nSTATUS
(2)
nCONFIG
(2)
MSEL0 CONF_DONE
(2)
MSEL1
nCE (4)
VCC
TRST
TDI
TDO
TMS
TCK
nSTATUS
nCONFIG
MSEL0 CONF_DONE
MSEL1
nCE (4)
TRST
TDI
TDO
TMS
TCK
1 kΩ
Notes to Figure 6–30:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, FPP, and PPA configuration chains, the
first device’s nCE pin is connected to GND while its nCEO pin is
connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device
configuration chain, its nCEO pin drives low to activate the second
device’s nCE pin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, you
should make sure the nCE pins are connected to GND during JTAG
configuration or that the devices are JTAG configured in the same order
as the configuration chain. As long as the devices are JTAG configured in
the same order as the multi-device configuration chain, the nCEO of the
previous device will drive nCE of the next device low when it has
successfully been JTAG configured.
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
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Configuring APEX II Devices
f
For more information about configuring multiple Altera devices in the
same configuration chain, see Configuring Mixed Altera FPGA Chains in
the Configuration Handbook.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONE through the JTAG port. If CONF_DONE is not high, the
Quartus II software indicates that configuration has failed. If CONF_DONE
is high, the software indicates that configuration was successful. When
Quartus II generates a JAM file for a multi-device chain, it contains
instructions so that all the devices in the chain will be initialized at the
same time.
Figure 6–31 shows JTAG configuration of an APEX II FPGA with a
microprocessor.
Figure 6–31. JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR
APEX II Device
(3) nCE
DATA
GND
VCC
TRST
TDI
TCK
TMS
TDO
nCEO
nCONFIG
MSEL0
MSEL1
nSTATUS
CONF_DONE
Microprocessor
N.C.
(2)
(2)
(2)
VCC (1)
VCC(1)
1 kΩ
1 kΩ
Notes to Figure 6–31:
(1)
(2)
(3)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design only
uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground.
nCE must be connected to GND or driven low for successful JTAG configuration.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
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Device Configuration Pins
f
For more information on JTAG and Jam STAPL in embedded
environments, see AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web
site:
www.altera.com/support/software/download/programming/jam/
jam-index.jsp
Configuring APEX II FPGAs with JRunner
JRunner is a software driver that allows you to configure Altera FPGAs,
including APEX II FPGAs, through the ByteBlaster II or ByteBlasterMV
cables in JTAG mode. The programming input file supported is in RBF
format. JRunner also requires a Chain Description File (.cdf) generated by
the Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has been developed for the Windows NT
operating system (OS). You can customize the code to make it run on
other platforms.
f
Device
Configuration
Pins
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files.
The following tables describe the connections and functionality of all the
configuration related pins on the APEX II device. Table 6–9 describes the
dedicated configuration pins, which are required to be connected
properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 1 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
MSEL0
MSEL1
N/A
All
Input
Two-bit configuration input that sets the APEX II device
configuration scheme. See Table 6–3 for the appropriate
connections. These pins must remain at a valid state
during power-up, before nCONFIG is pulled low to initiate
a reconfiguration and during configuration.
VCCSEL
N/A
All
Input
Dedicated input that ensures the configuration related
I/O banks have powered up to the appropriate 1.8-V or
2.5-V/3.3-V voltage levels before starting configuration.
A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V) means 1.8 V, and
a logic low means 2.5-V/3.3 V.
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Configuring APEX II Devices
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 2 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low during
user-mode will cause the FPGA to lose its configuration
data, enter a reset state, tri-state all I/O pins, and
returning this pin to a logic high level will initiate a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, nCONFIG can be
tied directly to VCC or to the configuration device’s
nINIT_CONF pin.
nSTATUS
N/A
All
Bidirectional
open-drain
The FPGA drives nSTATUS low immediately after
power-up and releases it within 5 µs. (When using a
configuration device, the configuration device holds
nSTATUS low for up to 200 ms.)
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If a configuration
device is used, driving nSTATUS low will cause the
configuration device to attempt to configure the FPGA,
but since the FPGA ignores transitions on nSTATUS in
user-mode, the FPGA will not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low.
The enhanced configuration devices' and EPC2 devices'
OE and nCS pins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
CONF_DON
E
N/A
All
Bidirectional
open-drain
Status output. The target FPGA drives the CONF_DONE
pin low before and during configuration. Once all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The enhanced configuration devices' and EPC2 devices'
OE and nCS pins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
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Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 3 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin
must be held low during configuration, initialization, and
user mode. In single device configuration, it should be
tied low. In multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to nCE
of the next device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the FPGA.
nCEO
N/A
All
Output
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCE pin. The nCEO of the last device in the
chain is left floating.
DCLK
N/A
Synchronous
configuration
schemes (PS
and FPP)
Input
Clock input used to clock data from an external source
into the target device. Data is latched into the FPGA on
the rising edge of DCLK.
In PPA mode, DCLK should be tied high to VCC to prevent
this pin from floating.
After configuration, this pin is tri-stated. In schemes that
use a configuration device, DCLK will be driven low after
configuration is done. In schemes that use a control
host, DCLK should be driven either high or low,
whichever is more convenient. Toggling this pin after
configuration does not affect the configured device.
DATA0
N/A
All
Input
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0 pin.
After configuration, EPC1 and EPC1441 devices tristate this pin, while EPC2 devices drive this pin high. In
schemes that use a control host, DATA0 should be
driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
DATA[7..1]
I/O
Parallel
configuration
schemes
(FPP and
PPA)
Inputs
Data inputs. Byte-wide configuration data is presented to
the target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tristated.
After PPA or FPP configuration, DATA[7..1] are
available as a user I/O pins and the state of these pin
depends on the Dual-Purpose Pin settings.
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Configuring APEX II Devices
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 4 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
DATA7
I/O
PPA
Bidirectional
In the PPA configuration scheme, the DATA7 pin
presents the RDYnBSY signal after the nRS signal has
been strobed low.
In serial configuration schemes, it functions as a user I/O
during configuration, which means it is tri-stated.
After PPA configuration, DATA7 is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nWS
I/O
PPA
Input
Write strobe input. A low-to-high transition causes the
device to latch a byte of data on the DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nWS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nRS
I/O
PPA
Input
Read strobe input. A low input directs the device to drive
the RDYnBSY signal on the DATA7 pin.
If the nRS pin is not used in PPA mode, it should be tied
high.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nRS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
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Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 5 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
RDYnBSY
I/O
PPA
Output
Ready output. A high output indicates that the target
device is ready to accept another data byte. A low output
indicates that the target device is busy and not ready to
receive another data byte.
In PPA configuration schemes, this pin will drive out high
after power-up, before configuration and after
configuration before entering user-mode.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, RDYnBSY is available as a user
I/O and the state of this pin depends on the dual-purpose
pin settings.
nCS/CS
I/O
PPA
Input
Chip-select inputs. A low on nCS and a high on CS select
the target device for configuration. The nCS and CS pins
must be held active during configuration and
initialization.
During the PPA configuration mode, it is only required to
use either the nCS or CS pin. Therefore, if only one chipselect input is used, the other must be tied to the active
state. For example, nCS can be tied to ground while CS
is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are available as a
user I/O pins and the state of these pins depends on the
dual-purpose pin settings.
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Configuring APEX II Devices
Table 6–10 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration they function as user I/O pins, which means they are tristated with weak pull-up resistors.
Table 6–10. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is on. I/O if
option is off.
Input
Optional user-supplied clock input.
Synchronizes the initialization of one or
more devices. This pin is enabled by turning
on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software
INIT_DONE
N/A if option is on. I/O if
option is off.
Output open-drain
Status pin. Can be used to indicate when
the device has initialized and is in user
mode. When nCONFIG is low and during the
beginning of configuration, the INIT_DONE
pin is tri-stated and pulled high due to an
external 1-kΩ pull-up resistor. Once the
option bit to enable INIT_DONE is
programmed into the device (during the first
frame of configuration data), the
INIT_DONE pin will go low. When
initialization is complete, the INIT_DONE
pin will be released and pulled high and the
FPGA enters user mode. Thus, the
monitoring circuitry must be able to detect a
low-to-high transition. This pin is enabled by
turning on the Enable INIT_DONE output
option in the Quartus II software.
DEV_OE
N/A if option is on. I/O if
option is off.
Input
Optional pin that allows the user to override
all tri-states on the device. When this pin is
driven low, all I/O pins are tri-stated; when
this pin is driven high, all I/O pins behave as
programmed. This pin is enabled by turning
on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is on. I/O if
option is off.
Input
Optional pin that allows you to override all
clears on all device registers. When this pin
is driven low, all registers are cleared; when
this pin is driven high, all registers behave
as programmed. This pin is enabled by
turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II
software.
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JTAG pins must be kept stable before and during configuration. JTAG pin
stability prevents accidental loading of JTAG instructions. Table 6–11
describes the dedicated JTAG pins.
Table 6–11. Dedicated JTAG Pins
Pin Name User Mode Pin Type
Description
TDI
N/A
Input
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TDO
N/A
Output
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is
not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. Transitions within the state machine occur
on the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST
N/A
Input
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
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Chapter 7. Configuring
APEX 20KE & APEX 20KC
Devices
CF51005-2.0
Introduction
APEX™ 20KE and APEX 20KC devices can be configured using one of
four configuration schemes. All configuration schemes use either a
microprocessor or configuration device.
This section covers how to configure APEX 20KE and APEX 20KC
Devices, which use a 1.8-V voltage supply for VCCINT. APEX 20K (non-E
and non-C) devices use a 2.5-V voltage supply for the core. If your target
FPGA is an APEX 20K device which uses a 2.5-V VCCINT, see Configuring
Mercury, APEX 20K (2.5 V), ACEX 1K and FLEX 10K Devices in the
Configuration Handbook.
APEX 20KE and APEX 20KC devices can be configured using the passive
serial (PS), passive parallel synchronous (PPS), passive parallel
asynchronous (PPA), and Joint Test Action Group (JTAG) configuration
schemes. The configuration scheme used is selected by driving the
APEX 20KE or APEX 20KC device MSEL1 and MSEL0 pins either high or
low as shown in Table 7–1. If your application only requires a single
configuration mode, the MSEL pins can be connected to VCC (VCCIO of the
I/O bank where the MSEL pin resides) or to ground. If your application
requires more than one configuration mode, you can switch the MSEL
pins after the FPGA is configured successfully. Toggling these pins
during user-mode does not affect the device operation; however, the
MSEL pins must be valid before a reconfiguration is initiated.
Table 7–1. APEX 20KE & APEX 20KC Configuration Schemes
MSEL1
MSEL0
Configuration Scheme
0
0
PS
1
0
PPS
1
1
PPA
(1)
(1)
JTAG Based (2)
Notes to Table 7–1:
(1)
(2)
Altera Corporation
July 2004
Do not leave the MSEL pins floating; connect them to a low- or high-logic level.
These pins support the non-JTAG configuration scheme used in production. If
only JTAG configuration is used, you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means MSEL pin settings are ignored.
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Preliminary
Introduction
Table 7–2 shows the approximate configuration file sizes for APEX 20KE
and APEX 20KE devices.
Table 7–2. APEX 20KE & APEX 20KC Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
Data Size (Bytes)
EP20K30E
354,832
44,354
EP20K60E
648,016
81,002
EP20K100E
1,008,016
126,002
EP20K160E
1,524,016
190,502
EP20K200E
EP20K200C
1,968,016
246,002
EP20K300E
2,741,616
342,702
EP20K400E
EP20K400C
3,909,776
488,722
EP20K600E
EP20K600C
5,673,936
709,242
EP20K1000E
EP20K1000C
8,960,016
1,120,002
EP20K1500E
12,042,256
1,505,282
Use the data in Table 7–2 only to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II or MAX+PLUS® II
software, all designs targeted for the same device will have the same
configuration file size.
The following sections describe in detail how to configure APEX 20KE
and APEX 20KC devices using the supported configuration schemes. The
Device Configuration Pins section describes the device configuration pins
available. The last section applies only to APEX 20KE devices and
provides guidelines that you must follow to ensure successful
configuration upon power-up and recovery from brown-out conditions.
In this chapter, the generic term “device(s)” or “FPGA(s)” will include all
APEX 20KE and APEX 20KC devices.
f
For more information on setting device configuration options or creating
configuration files, see Section II, Software Settings, in Volume 2.
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Core Version a.b.c variable
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Passive Serial
Configuration
You can perform APEX 20KE and APEX 20KC PS configuration using an
Altera configuration device, an intelligent host (e.g., a microprocessor or
Altera® MAX® device), or a download cable.
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure APEX 20KE and
APEX 20KC devices using a serial configuration bitstream. Configuration
data is stored in the configuration device. Figure 7–1 shows the
configuration interface connections between the APEX 20KE or APEX
20KC device and a configuration device for single device configuration.
1
f
Altera Corporation
July 2004
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
For more information on the enhanced configuration device and flash
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), see the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet in the Configuration Handbook.
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 7–1. Single Device PS Configuration Using a Configuration Device
VCC (2)
VCC (1)
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device
10 kΩ
(4)
(2)
10 kΩ
GND
nCEO
Configuration
Device
DCLK
DATA
OE (4)
nCS (4)
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
(4)
N.C.
(3)
nCE
GND
Notes to Figure 7–1:
(1)
(2)
(3)
(4)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2
devices only) does not need to be connected if its functionality is not used. If
nINIT_CONF is not used or not available (e.g., on EPC1 devices), nCONFIG must
be pulled to VCC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG
should be pulled up to VCCINT. For APEX 20KC devices, nCONFIG should be
connected to the same supply voltage as the configuration device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active.
Since a 10-kΩ pull-up resistor to VCCINT is required to successfully configure APEX
20KE devices, you need to isolate the 1.8-V VCCINT from the configuration device’s
3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between
the APEX 20KE device’s nCONFIG pin and the configuration device’s
nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than or equal to
0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will
only be able to drive low or tri-state. If nINIT_CONF is not used or not available
(e.g., on EPC1 devices), this diode is not needed. The diode is also not needed
when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have
internal programmable pull-up resistors. For successful configuration of
APEX 20KE and APEX 20KC devices using EPC2 devices, you should use external
10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration
device are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off
the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on
configuration device option when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data
Sheet or the Configuration Devices for SRAM-based LUT Devices Data Sheet
in the Configuration Handbook.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. An internal pull-up resistor on the nINIT_CONF pin is always
active in the enhanced configuration devices and the EPC2 devices,
which means an external pull-up resistor is not required if nCONFIG is
tied to nINIT_CONF. Since a 10-kΩ pull-up resistor to VCCINT is required
to successfully configure APEX 20KE devices, you need to isolate the
1.8-V VCCINT from the configuration device’s 3.3-V supply. To isolate the
1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE
device’s nCONFIG pin and the configuration device’s nINIT_CONF pin.
Select a diode with a threshold voltage (VT) less than or equal to 0.7 V. The
diode will make the nINIT_CONF pin an open-drain pin; the pin will only
be able to drive low or tri-state. If nINIT_CONF is not used or not
available (e.g., on EPC1 devices), nCONFIG must be pulled to VCCINT
through a 10-kΩ pull-up resistor and the isolating diode is not needed.
Upon power-up, the APEX 20KE or APEX 20KC device goes through a
Power-On Reset (POR) for approximately 5 µs. During POR, the device
resets and holds nSTATUS low, and tri-states all user I/O pins. The
configuration device also goes through a POR delay to allow the power
supply to stabilize. The POR time for EPC2, EPC1, and EPC1441 devices
is 200 ms (maximum), and for enhanced configuration devices, the POR
time can be set to either 100 ms or 2 ms, depending on its PORSEL pin
setting. If the PORSEL pin is connected to GND, the POR delay is 100 ms.
During this time, the configuration device drives its OE pin low. This low
signal delays configuration because the OE pin is connected to the target
device’s nSTATUS pin. When both devices complete POR, they release
their open-drain OE or nSTATUS pin, which is then pulled high by a pullup resistor. Once the FPGA successfully exits POR, all user I/O pins are
tri-stated. APEX 20KE and APEX 20KC devices have weak pull-up
resistors on the user I/O pins which are on before and during
configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX 20K Programmable Logic Device Family Data
Sheet or APEX 20KC Programmable Logic Device Family Data Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
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July 2004
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Passive Serial Configuration
1
VCCINT and VCCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels to begin the configuration process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up on the
OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. For successful
configuration of APEX 20KE and APEX 20KC devices using EPC2
devices, you should use external 10-kΩ pull-up resistors. If internal pullup resistors on the enhanced configuration device are used, an external
10-kΩ pull-up resistor on the nCS/CONF_DONE line is not required. Once
nSTATUS is released, the FPGA is ready to receive configuration data and
the configuration stage begins.
When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX 20KE or APEX 20KC device
receives configuration data on its DATA0 pin and the clock is received on
the DCLK pin. Data is latched into the FPGA on the rising edge of DCLK.
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a pullup resistor. Since CONF_DONE is tied to the configuration device’s nCS
pin, the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration and EPC2 devices have an optional internal pullup resistor on the nCS pin. This option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
For successful configuration of APEX 20KE and APEX 20KC devices
using EPC2 devices, you should use external 10-kΩ pull-up resistors. If
internal pull-up resistors on the enhanced configuration device are used,
an external 10-kΩ pull-up resistor on the nCS/CONF_DONE line is not
required. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin.
In APEX 20KE and APEX 20KC devices, the initialization clock source is
either the APEX 20KE or APEX 20KC internal oscillator (typically 10
MHz) or the optional CLKUSR pin. By default, the internal oscillator is the
clock source for initialization. If the internal oscillator is used, the
APEX 20KE or APEX 20KC device will supply itself with enough clock
cycles for proper initialization. You also have the flexibility to
synchronize initialization of multiple devices by using the CLKUSR
option. You can turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General tab of the Device &
Pin Options dialog box. Supplying a clock on CLKUSR will not affect the
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
configuration process. After all configuration data is accepted and
CONF_DONE goes high, APEX 20KE and APEX 20KC devices require 40
clock cycles to properly initialize.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the FPGA has entered user mode. In user-mode, the user I/O
pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device and EPC2
device drives DCLK low and DATA high (EPC1 devices tri-state DATA) at
the end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option available in the Quartus II software from the General
tab of the Device & Pin Options dialog box is turned on, the FPGA
automatically initiates reconfiguration if an error occurs. The APEX 20KE
or APEX 20KC device will release its nSTATUS pin after a reset time-out
period (maximum of 40 µs). When the nSTATUS pin is released and
pulled high by a pull-up resistor, the configuration device reconfigures
the chain. If this option is turned off, the external system must monitor
nSTATUS for errors and then pulse nCONFIG low for at least 8 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. EPC1 and EPC2 devices wait for 16 DCLK cycles. In this
case, the configuration device pulls its OE pin low, which in turn drives
the target device’s nSTATUS pin low. If the Auto-Restart Configuration
After Error option is set in the software, the target device resets and then
releases its nSTATUS pin after a reset time-out period (maximum of
40 µs). When nSTATUS returns high, the configuration device tries to
reconfigure the FPGA.
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July 2004
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Passive Serial Configuration
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
8 µs. When nCONFIG is pulled low, the FPGA also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Since CONF_DONE is
pulled low, this will activate the configuration device since it will see its
nCS pin drive low. Once nCONFIG returns to a logic high state and
nSTATUS is released by the FPGA, reconfiguration begins.
Figure 7–2 shows how to configure multiple devices with a configuration
device. This circuit is similar to the configuration device circuit for a
single device, except the APEX 20KE or APEX 20KC devices are cascaded
for multi-device configuration.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–2. Multi-Device PS Configuration Using a Configuration Device
VCC (1)
10 kΩ
(2)
VCC (1)
VCC (1)
10 kΩ
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
N.C.
nCEO
nCE
(4)
Configuration
Device
DCLK
DATA
OE (4)
nCS (4)
nINIT_CONF (2)
GND
GND
10 kΩ
APEX 20KE or
APEX 20KC Device 1
DCLK
MSEL0
DATA0
MSEL1
nSTATUS
CONF_DONE
nCONFIG
APEX 20KE or
APEX 20KC Device 2
MSEL0
(4)
(3)
nCEO
nCE
GND
Notes to Figure 7–2:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG should be pulled up
to VCCINT. For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the configuration
device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the configuration
device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’s
nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than
or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive
low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed. The
diode is also not needed when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should use
external 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on
configuration device option when generating programming files.
When performing multi-device configuration, you must generate the
configuration device’s Programmer Object File (.pof) from each project’s
SRAM Object File (.sof). You can combine multiple SOFs using the
Quartus II software.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
f
For more information on how to create configuration files for multidevice configuration chains, see Section II, Software Settings, in Volume 2.
In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they can
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLK and DATA lines are buffered
for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the configuration device and drives
nSTATUS low on all FPGAs, which causes them to enter a reset state. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the AutoRestart Configuration After Error option is turned off, the external system
must monitor nSTATUS for errors and then pulse nCONFIG low for at
least 8 µs to restart configuration. The external system can pulse nCONFIG
if nCONFIG is under system control rather than tied to VCC.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
The enhanced configuration devices also support parallel configuration
of up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode
allows enhanced configuration devices to concurrently configure FPGAs
or a chain of FPGAs. In addition, these devices do not have to be the same
device family or density; they can be any combination of Altera FPGAs.
An individual enhanced configuration device DATA line is available for
each targeted FPGA. Each DATA line can also feed a daisy chain of FPGAs.
Figure 7–3 shows how to concurrently configure multiple devices using
an enhanced configuration device.
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July 2004
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Passive Serial Configuration
Figure 7–3. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
(2) VCC
10 kΩ
(1) VCC
N.C.
APEX 20KE or
APEX 20KC Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO
nCONFIG
MSEL1
MSEL0
GND
N.C.
(4)
VCC (1)
(4)
Enhanced
Configuration
Device
10 kΩ
DCLK
DATA0
DATA1
DATA[2..6]
nCE
OE (4)
nCS (4)
APEX 20KE or
APEX 20KC Device 2
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO
nCONFIG
MSEL1
MSEL0
10 kΩ
(2)
nINIT_CONF (2)
GND
(3)
DATA 7
nCE
GND
GND
APEX 20KE or
APEX 20KE Device 8
N.C.
nCEO
MSEL1
MSEL0
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
GND
Notes to Figure 7–3:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG should be pulled up
to VCCINT. For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the configuration
device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the configuration
device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’s
nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than
or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive
low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed. The
diode is also not needed when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should use
external 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on
configuration device option when generating programming files.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 7–3 to
select the appropriate configuration mode for the fastest configuration
times.
Table 7–3. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 7–3:
(1)
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus
II software. On the printed circuit board (PCB), leave the DATA3 line from
the enhanced configuration device unconnected. Figure 7–4 shows the
Quartus II Convert Programming Files window (Tools menu) setup for
this scheme.
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July 2004
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Passive Serial Configuration
Figure 7–4. Software Settings for Configuring Devices Using n-Bit PS Modes
Alternatively, you can daisy chain two FPGAs to one DATA line while the
other DATA lines drive one device each. For example, you could use the 2bit PS mode to drive two FPGAs with DATA Bit0 (EP20K400E and
EP20K600E devices) and the third device (the EP20K1000E device) with
DATA Bit1. This 2-bit PS configuration scheme requires less space in the
configuration flash memory, but can increase the total system
configuration time. See Figure 7–5.
7–14
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–5. Software Settings for Daisy Chaining Two FPGAs on One DATA
Line
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 7–6 shows multi-device
PS configuration when the APEX 20KE and APEX 20KC devices are
receiving the same configuration data.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 7–6. Multiple-Device PS Configuration Using an Enhanced Configuration Device When FPGAs
Receive the Same Data
VCC (2)
(2)
(1) VCC
APEX 20KE or
APEX 20KC Device
(4) N.C.
nCEO
MSEL1
MSEL0
GND
(4) N.C.
(4)
VCC (1)
(4)
10 KΩ
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
Configuration
Device
DCLK
DATA0
OE (4)
nCS (4)
nINIT_CONF (2)
(3)
nCE
APEX 20KE or
APEX 20KC Device
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCEO
MSEL1
MSEL0
10 KΩ
10 KΩ
GND
nCE
GND
GND
APEX 20KE or
APEX 20KC Device
(4) N.C.
nCEO
MSEL1
MSEL0
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
GND
Notes to Figure 7–6:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG should be pulled up
to VCCINT. For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the configuration
device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the configuration
device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’s
nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less
than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive
low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed. The
diode is also not needed when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should use
external 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on
configuration device option when generating programming files.
The nCEO pins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
You can cascade several EPC2 or EPC1 devices to configure multiple
APEX 20KE or APEX 20KC devices. The first configuration device in the
chain is the master configuration device, while the subsequent devices
are the slave devices. The master configuration device sends DCLK to the
APEX 20KE and APEX 20KC devices and to the slave configuration
devices. The first EPC device’s nCS pin is connected to the CONF_DONE
pins of the FPGAs, while its nCASC pin is connected to nCS of the next
configuration device in the chain. The last device’s nCS input comes from
the previous device, while its nCASC pin is left floating. When all data
from the first configuration device is sent, it drives nCASC low, which in
turn drives nCS on the next configuration device. Because a configuration
device requires less than one clock cycle to activate a subsequent
configuration device, the data stream is uninterrupted.
1
Enhanced configuration devices EPC4, EPC8, and EPC16 cannot
be cascaded.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONE going high
at the end of configuration, it resets the entire chain by pulling its OE pin
low. This low signal drives the OE pin low on the slave configuration
device(s) and drives nSTATUS low on all FPGAs, causing them to enter a
reset state. This behavior is similar to the FPGA detecting an error in the
configuration data.
Figure 7–7 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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Passive Serial Configuration
Figure 7–7. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (2)
VCC (1)
VCC (1)
(4) 10 kΩ
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (4)
nCS (4)
nCASC
nINIT_CONF (2)
nCEO
nCE
(3)
nCEO
10 kΩ (4)
EPC2/EPC1
Device 1
GND
GND
(2)
APEX 20KE or
APEX 20KC Device 1
APEX 20KE or
APEX 20KC Device 2
DCLK
MSEL0
DATA0
MSEL1
nSTATUS
CONF_DONE
nCONFIG
N.C.
10 kΩ
EPC2/EPC1
Device 2
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 7–7:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC through a 10-kΩ resistor. For APEX 20KE devices, nCONFIG should be pulled up
to VCCINT. For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the configuration
device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up resistor to
VCCINT is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the
configuration device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX
20KE device’s nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold
voltage (VT) less than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will
only be able to drive low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode
is not needed. The diode is also not needed when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should use
external 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the
Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on
configuration device option when generating programming files.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. An internal pull-up resistor on the nINIT_CONF pin is always
active in the enhanced configuration devices and the EPC2 devices,
which means an external pull-up resistor is not required if nCONFIG is
tied to nINIT_CONF. Since a 10-kΩ pull-up resistor to VCCINT is required
to successfully configure APEX 20KE devices, you need to isolate the
1.8-V VCCINT from the configuration device’s 3.3-V supply. To isolate the
1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE
device’s nCONFIG pin and the configuration device’s nINIT_CONF pin.
Select a diode with a threshold voltage (VT) less than or equal to 0.7 V. The
diode will make the nINIT_CONF pin an open-drain pin; the pin will only
be able to drive low or tri-state. If nINIT_CONF is not used or not
available (e.g., on EPC1 devices), nCONFIG must be pulled to VCCINT
through a 10 kΩ resistor and the isolating diode is not needed. If multiple
EPC2 devices are used to configure an APEX 20KE or APEX 20KC
device(s), only the first EPC2 has its nINIT_CONF pin tied to the device’s
nCONFIG pin.
You can use a single configuration chain to configure APEX 20KE and
APEX 20KC devices with other Altera devices. To ensure that all devices
in the chain complete configuration at the same time or that an error
flagged by one device initiates reconfiguration in all devices, all of the
device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 7–8 shows the timing waveform for the PS configuration scheme
using a configuration device.
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Passive Serial Configuration
Figure 7–8. APEX 20KE & APEX 20KC PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
tDSU
tCL
D0
D1
tCH
tDH
tOEZX
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 7–8:
(1)
APEX 20KE and APEX 20KC devices enter user-mode 40 clock cycles after CONF_DONE goes high. The initialization
clock can come from the APEX 20KE or APEX 20KC internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
PS Configuration Using a Microprocessor
In the PS configuration scheme, an intelligent host (e.g., a microprocessor
or CPLD) can transfer configuration data from a storage device (e.g., flash
memory) to the target APEX 20KE and APEX 20KC devices.
Configuration data can be stored in RBF, HEX, or TTF format. Figure 7–9
shows the configuration interface connections between the APEX 20KE or
APEX 20KC device and a microprocessor for single device configuration.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–9. Single Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
(1) VCC
10 kΩ
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
nCEO
GND
N.C.
GND
DATA0
nCONFIG
DCLK
Note to Figure 7–9:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal
for the device.
Upon power-up, the APEX 20KE or APEX 20KC device goes through a
POR for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX 20KE and
APEX 20KC devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX 20K Programmable Logic Device Family Data
Sheet or APEX 20KC Programmable Logic Device Family Data Sheet.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
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Passive Serial Configuration
pulled high, the microprocessor should place the configuration data one
bit at a time on the DATA0 pin. The least significant bit (LSB) of each data
byte must be sent first.
The APEX 20KE or APEX 20KC device receives configuration data on its
DATA0 pin and the clock is received on the DCLK pin. Data is latched into
the FPGA on the rising edge of DCLK. Data is continuously clocked into
the target device until CONF_DONE goes high. After the FPGA has
received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In APEX 20KE and APEX 20KC devices, the initialization clock source is
either the APEX 20KE or APEX 20KC internal oscillator (typically
10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If the internal oscillator is used, the
APEX 20KE or APEX 20KC device will take care to provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
APEX 20KE and APEX 20KC devices require 40 clock cycles to initialize
properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The microprocessor
must be able to detect this low-to-high transition which signals the FPGA
has entered user mode. In user-mode, the user I/O pins will no longer
have weak pull-up resistors and will function as assigned in your design.
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Configuring APEX 20KE & APEX 20KC Devices
To ensure DCLK and DATA are not left floating at the end of configuration,
the microprocessor must drive them either high or low, whichever is
convenient on your board.
Handshaking signals are not used in PS configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option (available in the Quartus II software from
the General tab of the Device & Pin Options dialog box) is turned on, the
APEX 20KE or APEX 20KC device releases nSTATUS after a reset timeout period (maximum of 40 µs). After nSTATUS is released and pulled
high by a pull-up resistor, the microprocessor can try to reconfigure the
target device without needing to pulse nCONFIG low. If this option is
turned off, the microprocessor must generate a low-to-high transition
(with a low pulse of at least 8 µs) on nCONFIG to restart the configuration
process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 8 µs. When nCONFIG is pulled low, the FPGA also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high state and nSTATUS is released by the
FPGA, reconfiguration begins.
Figure 7–10 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the PS configuration circuit for a
single device, except the APEX 20KE or APEX 20KC devices are cascaded
for multi-device configuration.
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Passive Serial Configuration
Figure 7–10. Multi-Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
VCC (1)
10 kΩ
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device 1
APEX 20KE or
APEX 20KC Device 2
MSEL1
CONF_DONE
nSTATUS
nCE
Microprocessor
MSEL1
MSEL0
CONF_DONE
GND
nCEO
MSEL0
nSTATUS
GND
nCE
GND
nCEO
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C.
Note to Figure 7–10:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PS configuration the first device’s nCE pin is connected to
GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they can require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLK and DATA lines
are buffered for every fourth device. Because all device CONF_DONE pins
are tied together, all devices initialize and enter user mode at the same
time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
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Configuring APEX 20KE & APEX 20KC Devices
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 7–11 shows multi-device
PS configuration when both APEX 20KE and APEX 20KC devices are
receiving the same configuration data.
Figure 7–11. Multiple-Device PS Configuration Using a Microprocessor When Both FPGAs Receive the Same
Data
Memory
ADDR
DATA0
VCC (1)
10 kΩ
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device
APEX 20KE or
APEX 20KC Device
MSEL1
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
CONF_DONE
GND
nCEO
GND
nCE
N.C. (2)
GND
MSEL0
nSTATUS
nCEO
GND
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (2)
Notes to Figure 7–11:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
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Passive Serial Configuration
You can use a single configuration chain to configure APEX 20KE and
APEX 20KC devices with other Altera devices. To ensure that all devices
in the chain complete configuration at the same time or that an error
flagged by one device initiates reconfiguration in all devices, all of the
device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 7–12 shows the timing waveform for the PS configuration for
APEX 20KE and APEX 20KC devices using a microprocessor.
Figure 7–12. APEX 20KE & APEX 20KC PS Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (1)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (2)
tCF2CD
tST2CK
tCH tCL
(3)
DCLK
tDH
DATA
Bit 0 Bit 1 Bit 2 Bit 3
Bit n
(3)
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 7–12:
(1)
(2)
(3)
Upon power-up, the APEX 20KE or APEX 20KC device holds nSTATUS low for not more than 5 µs after VCC reaches
its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is more
convenient.
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Configuring APEX 20KE & APEX 20KC Devices
Table 7–4 defines the timing parameters for APEX 20KE and APEX 20KC
devices for PS configuration.
Table 7–4. PS Timing Parameters for APEX 20KE & APEX 20KC Devices
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
Max
Units
200
ns
200
ns
µs
40 (1)
µs
1 (1)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
7.5
ns
tCL
DCLK low time
7.5
ns
tCLK
DCLK period
15
ns
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (2)
2
66
MHz
8
µs
Notes to Table 7–4:
(1)
(2)
This value is applicable if users do not delay configuration by extending the nSTATUS low pulse width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX 20KE and APEX 20KC devices
to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver allows you to configure Altera’s
FPGAs through the ByteBlasterMV cable in PS mode. The MicroBlaster
software driver supports a RBF programming input file and is targeted
for embedded passive serial configuration. The source code is developed
for the Windows NT operating system, although you can customize it to
run on other operating systems. For more information on the
MicroBlaster software driver, go to the Altera web site
(http://www.altera.com).
Altera Corporation
July 2004
Core Version a.b.c variable
7–27
Configuration Handbook, Volume 1
Passive Serial Configuration
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB Blaster universal serial bus (USB) port download cable,
MasterBlasterTM serial/USB communications cable, ByteBlasterTM II
parallel port download cable, and the ByteBlasterMVTM parallel port
download cable.
In PS configuration with a download cable, an intelligent host (e.g., a PC)
transfers data from a storage device to the FPGA via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Upon power-up, the APEX 20KE or APEX 20KC device goes through a
POR for approximately 5 µs. During POR, the device resets and holds
nSTATUS low, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX 20KE and
APEX 20KC devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX 20K Programmable Logic Device Family Data
Sheet or APEX 20KC Programmable Logic Device Family Data Sheet.
The configuration cycle consists of 3 stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
When using a download cable, setting the Auto-Restart Configuration After
Error option does not affect the configuration cycle because you must
manually restart configuration in the Quartus II software when an error
occurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)
option has no affect on the device initialization since this option is
disabled in the SOF when programming the FPGA using the Quartus II
programmer and download cable. Therefore, if you turn on the CLKUSR
option, you do not need to provide a clock on CLKUSR when you are
configuring the FPGA with the Quartus II programmer and a download
cable. Figure 7–13 shows PS configuration for APEX 20KE and APEX
20KC devices using a USB Blaster, MasterBlaster, ByteBlaster II or
ByteBlasterMV cable.
Figure 7–13. PS Configuration Using a USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV Cable
VCC (1)
VCC (1)
10 kΩ
(2)
10 kΩ
VCC (1)
APEX 20KE or
APEX 20KC Device
MSEL0
VCC (1)
10 kΩ
(2)
MSEL1
10 kΩ
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
GND
nCE
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
GND
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 7–13:
(1)
(2)
(3)
Altera Corporation
July 2004
The pull-up resistor should be connected to the same supply voltage as the USB
Blaster, MasterBlaster (VIO pin), ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable
is the only configuration scheme used on your board. This is to ensure that DATA0
and DCLK are not left floating after configuration. For example, if you are also
using a configuration device, the pull-up resistors on DATA0 and DCLK are not
needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver.
VIO should match the device’s VCCIO. Refer to the MasterBlaster Serial/USB
Communications Cable Data Sheet for this value. In the ByteBlasterMV, this pin is
a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE
when it is used for Active Serial programming, otherwise it is a no connect.
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Configuration Handbook, Volume 1
Passive Serial Configuration
You can use a download cable to configure multiple APEX 20KE and
APEX 20KC devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. The first device’s nCE pin is connected to
GND while its nCEO pin is connected to the nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. All other configuration pins, nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE are connected to every device
in the chain. Because all CONF_DONE pins are tied together, all devices in
the chain initialize and enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-Restart
Configuration After Error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
Figure 7–14 shows how to configure multiple APEX 20KE and
APEX 20KC devices with a download cable.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–14. Multi-Device PS Configuration using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV Cable
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device 1
VCC (1)
10 kΩ
MSEL1
(2)
VCC (1)
10 kΩ
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
DCLK
MSEL0
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
(2)
Pin 1
VCC
GND
VIO (3)
GND
nCEO
nCE
10 kΩ
GND
DATA0
nCONFIG
GND
APEX 20KE or
APEX 20KC Device 2
CONF_DONE
nSTATUS
MSEL0
DCLK
MSEL1
GND
nCEO
nCE
N.C.
DATA0
nCONFIG
Notes to Figure 7–14:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration device from the target device(s) and cable. One way to
isolate the configuration device is to add logic, such as a multiplexer, that
can select between the configuration device and the cable. The
multiplexer chip should allow bidirectional transfers on the nSTATUS
and CONF_DONE signals. Another option is to add switches to the five
common signals (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
between the cable and the configuration device. The last option is to
remove the configuration device from the board when configuring the
FPGA with the cable. Figure 7–15 shows a combination of a configuration
device and a download cable to configure an FPGA.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–15. PS Configuration with a Download Cable & Configuration Device Circuit
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device
VCC (4)
10 kΩ
(4)
MSEL0
MSEL1
Download Cable
10-Pin Male Header
(PS Mode)
(6) VCC (1)
(6)
10 kΩ
Pin 1
CONF_DONE
nSTATUS
DCLK
VCC
GND
VIO (2)
GND
nCE
nCEO
N.C.
GND
(3)
DATA0
nCONFIG
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (6)
nCS (6)
(3)
nINIT_CONF (4)
(5)
Notes to Figure 7–15:
(1)
(2)
(3)
(4)
(5)
(6)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to an
APEX 20KE or APEX 20KC device. Instead, you should either remove the configuration device from its socket when
using the download cable or place a switch on the five common signals between the download cable and the
configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC through a 10-kΩ pull-up resistor. For APEX 20KE devices, nCONFIG should be
pulled up to VCCINT. For APEX 20KC devices, nCONFIG should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the configuration
device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’s
nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less
than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive
low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed. The
diode is also not needed when configuring APEX 20KC devices.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE and APEX 20KC devices using EPC2 devices, you should use
external 10-kΩ pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus
II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-up resistors on configuration
device option when generating programming files.
Altera Corporation
July 2004
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Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV cables, refer to the followig data sheets.
■
■
■
■
Passive Parallel
Synchronous
Configuration
USB Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Passive Parallel Synchronous (PPS) configuration uses an intelligent host,
such as a microprocessor, to transfer configuration data from a storage
device, such as flash memory, to the target APEX 20KE or APEX 20KC
device. Configuration data can be stored in TTF, RBF, or HEX format. The
host system outputs byte-wide data and the serializing clock to the FPGA.
The target device latches the byte-wide data on the DATA[7..0] pins on
the rising edge of DCLK and then uses the next eight falling edges on DCLK
to serialize the data internally. On the ninth rising DCLK edge, the next
byte of configuration data is latched into the target device. Figure 7–16
shows the configuration interface connections between the FPGA and a
microprocessor for single device configuration.
Figure 7–16. Single Device PPS Configuration Using a Microprocessor
(1) VCC
Memory
ADDR
10 kΩ
DATA[7..0]
VCC (1)
10 kΩ
APEX 20KE or
APEX 20KC Device
MSEL0
GND
VCC
MSEL1
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
DCLK
nCONFIG
Note to Figure 7–16:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Upon power-up, the APEX 20KE or APEX 20KC device goes through a
Power-On Reset (POR) for approximately 5 µs. During POR, the device
resets and holds nSTATUS low, and tri-states all user I/O pins. Once the
FPGA successfully exits POR, all user I/O pins are tri-stated. APEX 20KE
and APEX 20KC devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
The configuration cycle consists of 3 stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the microprocessor must
generate a low-to-high transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should place the configuration data one
byte at a time on the DATA[7..0] pins. New configuration data should
be sent to the FPGA every eight DCLK cycles.
The APEX 20KE or APEX 20KC device receives configuration data on its
DATA[7..0] pins and the clock is received on the DCLK pin. On the first
rising DCLK edge, a byte of configuration data is latched into the target
device; the subsequent eight falling DCLK edges serialize the
configuration data in the device. On the ninth rising clock edge, the next
byte of configuration data is latched and serialized into the target device.
Data is clocked into the target device until CONF_DONE goes high. After
the FPGA has received all configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin.
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July 2004
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Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
In APEX 20KE and APEX 20KC devices, the initialization process is
synchronous and can be clocked by its internal oscillator (typically
10 MHz) or by the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If the internal oscillator is used, the
APEX 20KE or APEX 20KC device will take care to provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLK to the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
APEX 20KE and APEX 20KC devices require 40 clock cycles to initialize
properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The microprocessor
must be able to detect this low-to-high transition which signals the FPGA
has entered user mode. In user-mode, the user I/O pins will no longer
have weak pull-ups and will function as assigned in your design. When
initialization is complete, the FPGA enters user mode.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the microprocessor must take care to drive them either
high or low, whichever is convenient on your board. The DATA[7..1]
pins are available as user I/O pins after configuration. When the PPS
scheme is chosen in the Quartus II software, as a default these I/O pins
are tri-stated in user mode and should be driven by the microprocessor.
To change this default option in the Quartus II software, select the DualPurpose Pins tab of the Device & Pin Options dialog box.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
The configuration clock (DCLK) speed must be below the specified
frequency, as listed in Table 7–5, to ensure correct configuration. No
maximum DCLK period exists, which means you can pause configuration
by halting DCLK for an indefinite amount of time. An optional status pin
(RDYnBSY) on the FPGA indicates when it is busy serializing
configuration data and when it is ready to accept the next data byte. The
RDYnBSY pin is not required in the PPS mode. Configuration data can be
sent every 8 DCLK cycles without monitoring this status pin.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration on Error option-available in the Quartus II software from the
General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of 40
µs). After nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 8 µs)
on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 8 µs for APEX 20KE and APEX 20KC devices. When
nCONFIG is pulled low, the FPGA also pulls nSTATUS and CONF_DONE
low and all I/O pins are tri-stated. Once nCONFIG returns to a logic high
state and nSTATUS is released by the FPGA, reconfiguration begins.
Figure 7–17 shows how to configure multiple APEX 20KE and
APEX 20KC devices using a microprocessor. This circuit is similar to the
PPS configuration circuit for a single device, except the devices are
cascaded for multi-device configuration.
Altera Corporation
July 2004
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Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
Figure 7–17. Multi-Device PPS Configuration Using a Microprocessor
(1) VCC
1 kΩ
APEX 20KE or
APEX 20KC Device 1
1 kΩ
APEX 20KE or
APEX 20KC Device 2
MSELO
MSELO
Memory
ADDR
VCC (1)
DATA[7..0]
GND
GND
VCC
VCC
MSEL 1
MSEL 1
CONF_DONE
nSTATUS
nCE
GND
Microprocessor
nCEO
DATA[7..0]
DCLK
nCONFIG
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
DATA[7..0]
DCLK
nCONFIG
Note to Figure 7–17:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPS configuration the first device's nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device's nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
Altera recommends keeping the configuration data valid on the
DATA[7..0] bus for the 8 serializing clock cycles. The configuration data
should be held valid on the DATA bus for the complete byte period
because the nCEO of the first (and preceding) device can go low during
the serializing DCLK cycles. Once the nCEO of the first (and preceding)
device goes low, the second (and next) device becomes active and will
begin trying to accept configuration data. If the configuration data is not
valid on the first DCLK edge after nCEO goes low, then the second device
will see incorrect configuration data and will never begin accepting
configuration data. This situation will only arise if you are sharing the
DATA[7..0] bus with other system data such that the configuration data
is only valid for a portion of the byte period.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
If your system requires to bus-share the DATA[7..0] line, you can workaround this by ensuring that the second (or next) device sees correct
configuration data on the first rising edge of DCLK after the nCEO signal
goes low. This can be achieved by delaying the nCEO signal by using
external registers or by presenting the next byte of configuration data
after the nCEO transition.
All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0],
and CONF_DONE) are connected to every device in the chain. You should
pay special attention to the configuration signals because they may
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLK and DATA lines are buffered
for every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration on Frame Error option is turned on, the
FPGAs release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). After all nSTATUS pins are released and pulled high,
the microprocessor can try to reconfigure the chain without needing to
pulse nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 7–18 shows
multi-device PPS configuration when both devices are receiving the same
configuration data.
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July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
Figure 7–18. Multiple-Device PPS Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
(1) VCC
1 kΩ
APEX 20KE or
APEX 20KC Device 1
1 kΩ
APEX 20KE or
APEX 20KC Device 2
MSELO
MSELO
Memory
ADDR
VCC (1)
DATA[7..0]
GND
GND
VCC
VCC
MSEL 1
MSEL 1
CONF_DONE
nSTATUS
nCE
GND
Microprocessor
nCEO
DATA[7..0]
DCLK
nCONFIG
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
DATA[7..0]
DCLK
nCONFIG
Notes to Figure 7–18:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure APEX 20KE or
APEX 20KC devices with other Altera devices that support PPS
configuration, such as MercuryTM, ACEX® 1K, or FLEX® 10K devices. To
ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 7–19 shows the timing waveform for the PPS configuration
scheme using a microprocessor.
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–19. APEX 20KE & APEX 20KC PPS Configuration Timing Waveform
tCFG
nCONFIG
(1) nSTATUS
tCF2CK
DCLK
ZZ
tCLK
tCL
(3)
tDSU
DATA[7..0]
tCH
7.5 Cycles
tDH
Byte 1
Byte 0
Byte n
FF
User Mode
(3)
tCH2B
(4) RDYnBSY
User Mode
(3)
(2) CONF_DONE
INIT_DONE
User I/O
High z
High z
User Mode
tCD2UM
Notes to Figure 7–19:
(1)
(2)
(3)
(4)
Upon power-up, the APEX 20KE and APEX 20KC devices holds nSTATUS low for approximately 5 µs after VCC
reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is
more convenient. DATA[7..1] and RDYnBSY are available as user I/Os after configuration and the state of
theses pins depends on the design programmed into the device.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
Table 7–5 defines the timing parameters for APEX 20KE and APEX 20KC
devices for PPS configuration.
Table 7–5. PPS Timing Parameters for APEX 20KE & APEX 20KC Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
40
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH2B
First rising DCLK to first rising RDYnBSY (2)
0.75 (3)
µs
Altera Corporation
July 2004
Core Version a.b.c variable
µs
40 (1)
µs
1 (1)
µs
7–41
Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Table 7–5. PPS Timing Parameters for APEX 20KE & APEX 20KC Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Units
tCH
DCLK high time
15
ns
tCL
DCLK low time
15
ns
tCLK
DCLK period
30
ns
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (4)
2
33.3
MHz
8
µs
Notes to Table 7–5:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the rising
edge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
f
Passive Parallel
Asynchronous
Configuration
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume, 2 of the
Configuration Handbook.
Passive Parallel Asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target APEX 20KE or
APEX 20KC device. Configuration data can be stored in TTF, RBF, or
HEX format. The host system outputs byte-wide data and the
accompanying strobe signals to the FPGA. When using PPA, you should
pull the DCLK pin high through a 10-kΩ pull-up resistor to prevent
unused configuration input pins from floating.
Figure 7–20 shows the configuration interface connections between the
FPGA and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCS and CS. The address decoder allows the
microprocessor to select the APEX 20KE or APEX 20KC device by
accessing a particular address, which simplifies the configuration
process. The nCS and CS pins must be held active during configuration
and initialization.
7–42
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–20. Single Device PPA Configuration Using a Microprocessor
Note (1)
Address Decoder
ADDR
VCC (2)
Memory
10 kΩ
VCC (2)
ADDR DATA[7..0]
10 kΩ
APEX 20KE or
APEX 20KC Device
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL1
MSEL0
nCEO
N.C.
VCC (2)
10 kΩ
DCLK
Notes to Figure 7–20:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if only one chip-select input is used, the other must be tied
to the active state. For example, nCS can be tied to ground while CS is
toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 7–6.
Upon power-up, the APEX 20KE or APEX 20KC device goes through a
Power-On Reset (POR) for approximately 5 µs. During POR, the device
resets and holds nSTATUS low, and tri-states all user I/O pins. Once the
FPGA successfully exits POR, all user I/O pins are tri-stated. APEX 20KE
and APEX 20KC devices have weak pull-up resistors on the user I/O pins
which are on before and during configuration.
f
Altera Corporation
July 2004
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the APEX 20K Programmable Logic Device Family Data
Sheet or APEX 20KC Programmable Logic Device Family Data Sheet.
Core Version a.b.c variable
7–43
Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
The configuration cycle consists of 3 stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the APEX 20KE or APEX 20KC
device is processing the byte of configuration data.
During the time RDYnBSY is low, the APEX 20KE or APEX 20KC device
internally processes the configuration data using its internal oscillator
(typically 10 MHz). When the device is ready for the next byte of
configuration data, it will drive RDYnBSY high. If the microprocessor
senses a high signal when it polls RDYnBSY, the microprocessor sends the
next byte of configuration data to the FPGA.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Data should not be driven onto the data bus while nRS is low because it
will cause contention on the DATA7 pin. If the nRS pin is not used to
monitor configuration, it should be tied high.
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY(max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The tBUSY, tRDY2WS and
tW2SB timing specifications are listed in Table 7–6.
7–44
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. After the FPGA
has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In APEX 20KE and APEX 20KC devices, the initialization clock source is
either the APEX 20KE or APEX 20KC internal oscillator (typically
10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If the internal oscillator is used, the
APEX 20KE or APEX 20KC device will take care to provide itself with
enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
APEX 20KE and APEX 20KC devices require 40 clock cycles to initialize
properly.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-kΩ pullup when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-ups and will
function as assigned in your design. When initialization is complete, the
FPGA enters user mode.
Altera Corporation
July 2004
Core Version a.b.c variable
7–45
Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
To ensure DATA0 is not left floating at the end of configuration, the
microprocessor must take care to drive them either high or low,
whichever is convenient on your board. After configuration, the nCS, CS,
nRS, nWS, RDYnBSY, and DATA[7..1] pins can be used as user I/O pins.
When the PPA scheme is chosen in the Quartus II software, as a default
these I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of
40 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the microprocessor can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the
microprocessor must generate a low-to-high transition (with a low pulse
of at least 8 µs) on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE has not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 8 µs. When nCONFIG is pulled low, the FPGA also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high state and nSTATUS is released by the
FPGA, reconfiguration begins.
Figure 7–21 shows how to configure multiple APEX 20KE and
APEX 20KC devices using a microprocessor. This circuit is similar to the
PPA configuration circuit for a single device, except the devices are
cascaded for multi-device configuration.
7–46
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Altera Corporation
July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–21. Multi-Device PPA Configuration Using a Microprocessor
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
APEX 20KE or
APEX 20KC Device 2
APEX 20KE or
APEX 20KC Device 1
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Microprocessor
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL1
MSEL0
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C.
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 7–21:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPA configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
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July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Each device’s RDYnBSY pin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSY pins can feed an AND gate and the output of the AND gate can
feed the microprocessor. For example, if you have 2 devices in a PPA
configuration chain, the second device’s RDYnBSY pin will be high during
the time that the first device is being configured. When the first device has
been successfully configured, it will driven nCEO low to activate the next
device in the chain and drive its RDYnBSY pin high. Therefore, since
RDYnBSY signal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the AND gate.
The nRS signal can be used in multi-device PPA chain since the
APEX 20KE or APEX 20KC device will tri-state its DATA[7..0] pins
before configuration and after configuration before entering user-mode
to avoid contention. Therefore, only the device that is currently being
configured will respond to the nRS strobe by asserting DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRS and CONF_DONE) are connected to every device in the chain.
You should pay special attention to the configuration signals because
they may require buffering to ensure signal integrity and prevent clock
skew problems. Specifically, ensure that the DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of
40 µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIG to restart the configuration process.
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Altera Corporation
July 2004
Configuring APEX 20KE & APEX 20KC Devices
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..1], nCS, CS, nWS,
nRS and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they
may require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 7–22 shows
multi-device PPA configuration when both devices are receiving the
same configuration data.
Figure 7–22. Multiple-Device PPA Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
APEX 20KE or
APEX 20KC Device
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
GND
DCLK
nCEO
Microprocessor
nWS
nRS
nCONFIG
RDYnBSY
APEX 20KE or
APEX 20KC Device
N.C. (3)
VCC
MSEL1
MSEL0
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C. (3)
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 7–22:
(1)
(2)
(3)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
Altera Corporation
July 2004
Core Version a.b.c variable
7–49
Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
You can use a single configuration chain to configure APEX 20KE and
APEX 20KC devices with other Altera devices that support PPA
configuration, such as Stratix®, Mercury, APEX II, ACEX 1K, and
FLEX 10KE devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 7–23 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
Figure 7–23. APEX 20KE & APEX 20KC PPA Configuration Timing Waveform
tCFG
tCF2ST1
nCONFIG
nSTATUS (1)
CONF_DONE (2)
Byte 0
DATA[7..0]
Byte 1
Byte n 1
Byte n
(4)
tCSH
(4)
tDSU
(3) CS
tCF2WS
tCSSU
tDH
(4)
(3) nCS
tWSP
(4)
nWS
tRDY2WS
(4)
RDYnBSY
tWS2B
tSTATUS
tBUSY
tCF2ST0
tCF2CD
User I/Os
tCD2UM
High-Z
High-Z
User-Mode
INIT_DONE
Notes to Figure 7–23:
(1)
(2)
(3)
(4)
Upon power-up, the APEX 20KE or APEX 20KC device holds nSTATUS low for not more than 5 µs after VCCINT
reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Figure 7–24 shows the timing waveform for the PPA configuration
scheme when using a strobed nRS and nWS signal.
7–50
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring APEX 20KE & APEX 20KC Devices
Figure 7–24. APEX 20KE & APEX 20KC PPA Configuration Timing Waveform Using nRS & nWS
tCF2ST1
tCFG
nCONFIG
(1) nSTATUS
tSTATUS
tCF2SCD
(2) CONF_DONE
tCSSU
(4)
nCS (3)
tCSH
(4)
CS (3)
tDH
Byte 0
DATA[7..0]
(4)
Byte n
Byte 1
tDSU
(4)
nWS
tWSP
nRS
tRS2WS
tWS2RS
tCF2WS
(4)
tWS2RS
tRSD7
INIT_DONE
tRDY2WS
User I/O
High-Z
User-Mode
tWS2B
(4)
DATA7/RDYnBSY (5)
tCD2UM
tBUSY
Notes to Figure 7–24:
(1)
(2)
(3)
(4)
(5)
Upon power-up, the APEX 20KE or APEX 20KC device holds nSTATUS low for not more than 5 µs after VCCINT
reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
DATA7 is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Table 7–6 defines the timing parameters for APEX 20KE or APEX 20KC
devices for PPA configuration.
Table 7–6. PPA Timing Parameters for APEX 20KE & APEX 20KC Devices (Part 1 of 2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
Altera Corporation
July 2004
Core Version a.b.c variable
Max
Units
200
ns
200
ns
µs
40 (1)
µs
7–51
Configuration Handbook, Volume 1
JTAG Configuration
Table 7–6. PPA Timing Parameters for APEX 20KE & APEX 20KC Devices (Part 2 of 2)
Symbol
Parameter
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge on nWS
Min
Max
Units
1 (1)
µs
10
ns
tCSH
Chip select hold time after rising edge on nWS
0
ns
tCF2WS
nCONFIG high to first rising edge on nWS
40
µs
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
200
0.1
ns
50
ns
1.6
µs
tRDY2WS
RDYnBSY rising edge to nWS rising edge
50
ns
tWS2RS
nWS rising edge to nRS falling edge
200
ns
tRS2WS
nRS rising edge to nWS rising edge
200
ns
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
CONF_DONE high to user mode (2)
2
50
ns
8
µs
Notes to Table 7–6:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX 20KE and APEX 20KC
devices to obtain this value.
f
JTAG
Configuration
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 in the
Configuration Handbook.
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture offers
the capability to efficiently test components on PCBs with tight lead
spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is
operating normally. The JTAG circuitry can also be used to shift
configuration data into the device.
For more information on JTAG boundary-scan testing, see Application
Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
7–52
Configuration Handbook, Volume 1
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July 2004
Configuring APEX 20KE & APEX 20KC Devices
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. All user I/O pins are tri-stated
during JTAG configuration. APEX 20KE and APEX 20KC devices are
designed such that JTAG instructions have precedence over any device
configuration modes. This means that JTAG configuration can take place
without waiting for other configuration modes to complete. For example,
if you attempt JTAG configuration of APEX 20KE and APEX 20KC
FPGAs during PS configuration, PS configuration will be terminated and
JTAG configuration will begin.
Table 7–7 explains each JTAG pin’s function.
Table 7–7. JTAG Pin Descriptions
Pin
Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data.
Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TDO
Test data output
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMS must be set up before
the rising edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST
Test reset input (optional)
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
1
If VCCIO of the bank where the JTAG pins reside, are tied to
3.3-V, both the I/O pins and JTAG TDO port will drive at 3.3-V
levels.
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV header. Configuring devices through a cable is similar to
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JTAG Configuration
programming devices in-system, except the TRST pin should be
connected to VCC. This ensures that the TAP controller is not reset.
Figure 7–25. shows JTAG configuration of a single APEX 20KE or
APEX 20KC device.
Figure 7–25. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
1 kΩ
(1) VCC
VCC (1)
(1) VCC
10 kΩ
10 kΩ
APEX 20KE or
APEX 20KC Device
nCE (4)
GND N.C.
(2)
(2)
(2)
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
1 kΩ
TCK
TDO
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
VCC
TRST
Pin 1
VCC
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 7–25:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cable, this pin is connected to
nCE when it is used for Active Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
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Configuring APEX 20KE & APEX 20KC Devices
APEX 20KE and APEX 20KC devices have dedicated JTAG pins that
always function as JTAG pins. JTAG testing can be performed on
APEX 20KE and APEX 20KC devices both before and after configuration,
but not during configuration. The chip-wide reset (DEV_CLRn) and chipwide output enable (DEV_OE) pins on APEX 20KE and APEX 20KC
devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of APEX 20KE and
APEX 20KC devices, the dedicated configuration pins should be
considered. Table 7–8 shows how these pins should be connected during
JTAG configuration.
Table 7–8. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all APEX 20KE and APEX 20KC devices in the chain, nCE should be driven low by
connecting it to ground, pulling it low via a resistor, or driving it by some control circuitry. For
devices that are also in multi-device PS, PPS or PPA configuration chains, the nCE pins should
be connected to GND during JTAG configuration or JTAG configured in the same order as the
configuration chain.
nCEO
On all APEX 20KE and APEX 20KC devices in the chain, nCEO can be left floating or connected
to the nCE of the next device. See nCE description above.
MSEL
These pins must not be left floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG
Driven high by connecting to VCC, pulling high via a resistor, or driven by some control circuitry.
nSTATUS
Pull to VCC via a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain,
each nSTATUS pin should be pulled up to VCC individually. nSTATUS pulling low in the middle
of JTAG configuration indicates that an error has occurred.
CONF_DONE Pull to VCC via a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain,
each CONF_DONE pin should be pulled up to VCC individually. CONF_DONE going high at the end
of JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0
Should not be left floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
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JTAG Configuration
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 7–26 shows multi-device JTAG configuration.
Figure 7–26. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
(1) VCC
1 kΩ
Pin 1
VCC
10 kΩ
(1) VCC
(2)
(2)
(2)
1 kΩ
VCC
VIO
(3)
(1) VCC
(1) VCC
APEX 20KE or
APEX 20KC Device
nSTATUS
nCONFIG
MSEL0 CONF_DONE
MSEL1
nCE (4)
TRST
TDI
TDO
TMS
TCK
(1) VCC
10 kΩ
10 kΩ
(2)
(2)
(2)
VCC
(1) VCC (1) VCC
(1) VCC
APEX 20KE or
APEX 20KE or
10 kΩ
10 kΩ
APEX 20KC Device
APEX
20KC
Device
10 kΩ
nSTATUS
nSTATUS
(2)
nCONFIG
nCONFIG
(2)
MSEL0 CONF_DONE
MSEL0 CONF_DONE
(2)
MSEL1
MSEL1
nCE (4)
VCC
nCE (4)
TRST
TRST
TDI
TDI
TDO
TDO
TMS
TCK
TMS
TCK
1 kΩ
Notes to Figure 7–26:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV, this
pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active
Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, PPS, and PPA configuration chains, the
first device’s nCE pin is connected to GND while its nCEO pin is
connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device
configuration chain, its nCEO pin drives low to activate the second
device’s nCE pin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, you
should make sure the nCE pins are connected to GND during JTAG
configuration or that the devices are JTAG configured in the same order
as the configuration chain. As long as the devices are JTAG configured in
the same order as the multi-device configuration chain, the nCEO of the
previous device will drive nCE of the next device low when it has
successfully been JTAG configured.
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Configuring APEX 20KE & APEX 20KC Devices
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
f
For more information about configuring multiple Altera devices in the
same configuration chain, see Configuring Mixed Altera FPGA Chains in
the Configuration Handbook.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONE through the JTAG port. If CONF_DONE is not high, the
Quartus II software indicates that configuration has failed. If CONF_DONE
is high, the software indicates that configuration was successful. When
Quartus II generates a Jam file for a multi-device chain, it contains
instructions so that all the devices in the chain will be initialized at the
same time.
Figure 7–27 shows JTAG configuration of an APEX 20KE or APEX 20KC
FPGA with a microprocessor.
Figure 7–27. JTAG Configuration of a Single Device Using a Microprocessor
APEX 20KE or
APEX 20KC Device
Memory
ADDR
(3) nCE
DATA
GND
VCC
TRST
TDI
TCK
TMS
TDO
nCEO
nCONFIG
MSEL0
MSEL1
nSTATUS
CONF_DONE
Microprocessor
N.C.
(2)
(2)
VCC (1)
VCC(1)
10 kΩ
10 kΩ
(2)
Notes to Figure 7–27:
(1)
(2)
(3)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design only
uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground.
nCE must be connected to GND or driven low for successful JTAG configuration.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
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JTAG Configuration
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
f
For more information on JTAG and Jam STAPL in embedded
environments, see AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web site
at:
www.altera.com/support/software/download/programming/jam/
jam-index.jsp
Configuring APEX 20KE & APEX 20KC FPGAs with JRunner
JRunner is a software driver that allows you to configure Altera FPGAs,
including APEX 20KE and APEX 20KC FPGAs, through the ByteBlaster
II or ByteBlasterMV cables in JTAG mode. The programming input file
supported is in RBF format. JRunner also requires a Chain Description
File (.cdf) generated by the Quartus II software. JRunner is targeted for
embedded JTAG configuration. The source code has been developed for
the Windows NT operating system (OS). You can customize the code to
make it run on other platforms.
f
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files.
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Configuring APEX 20KE & APEX 20KC Devices
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration related pins on the APEX 20KE or APEX 20KC device.
Table 7–9 describes the dedicated configuration pins, which are required
to be connected properly on your board for successful configuration.
Some of these pins may not be required for your configuration schemes.
Table 7–9. Dedicated Configuration Pins on the APEX 20KE & APEX 20KC Device (Part 1 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
MSEL0
MSEL1
N/A
All
Input
Two-bit configuration input that sets the APEX 20KE or
APEX 20KC device configuration scheme. See
Table 7–3 for the appropriate connections. These pins
must remain at a valid state during power-up, before
nCONFIG is pulled low to initiate a reconfiguration and
during configuration.
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low during
user-mode will cause the FPGA to lose its configuration
data, enter a reset state, tri-state all I/O pins, and
returning this pin to a logic high level will initiate a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, nCONFIG can be
tied directly to VCC or to the configuration device’s
nINIT_CONF pin. For succesful configuration of
APEX 20KE devices, nCONFIG must be tied to VCCINT
through a 10-kΩ pull-up resistor.
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Device Configuration Pins
Table 7–9. Dedicated Configuration Pins on the APEX 20KE & APEX 20KC Device (Part 2 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nSTATUS
N/A
All
Bidirectional
open-drain
The FPGA drives nSTATUS low immediately after
power-up and releases it within 5 µs. (When using a
configuration device, the configuration device holds
nSTATUS low for up to 200 ms.)
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If a configuration
device is used, driving nSTATUS low will cause the
configuration device to attempt to configure the FPGA,
but since the FPGA ignores transitions on nSTATUS in
user-mode, the FPGA will not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low.
The enhanced configuration devices’ and EPC2 devices’
OE and nCS pins have optional internal programmable
pull-up resistors. For succesful configuration of
APEX 20KE and APEX 20KC devices using EPC2
devices, use an external 10-kΩ pull-up resistor. If
internal pull-up resistors on the enhanced configuration
devices are used, external 10-kΩ pull-up resistors
should not be used on these pins.
CONF_DON
E
N/A
All
Bidirectional
open-drain
Status output. The target FPGA drives the CONF_DONE
pin low before and during configuration. Once all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The enhanced configuration devices’ and EPC2 devices’
OE and nCS pins have optional internal programmable
pull-up resistors. For successful configuration of
APEX 20KE and APEX 20KC devices using EPC2
devices, use an external 10-kΩ pull-up resistor. If
internal pull-up resistors on the enhanced configuration
devices are used, external 10-kΩ pull-up resistors
should not be used on these pins.
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Configuring APEX 20KE & APEX 20KC Devices
Table 7–9. Dedicated Configuration Pins on the APEX 20KE & APEX 20KC Device (Part 3 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin
must be held low during configuration, initialization, and
user mode. In single device configuration, it should be
tied low. In multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to nCE
of the next device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the FPGA.
nCEO
N/A
All
Output
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCE pin. The nCEO of the last device in the
chain is left floating.
DCLK
N/A
Synchronous
configuration
schemes (PS
and PPS)
Input
Clock input used to clock data from an external source
into the target device. Data is latched into the FPGA on
the rising edge of DCLK.
In PPA mode, DCLK should be tied high to VCC to prevent
this pin from floating.
After configuration, this pin is tri-stated. In schemes that
use a configuration device, DCLK will be driven low after
configuration is done. In schemes that use a control
host, DCLK should be driven either high or low,
whichever is more convenient. Toggling this pin after
configuration does not affect the configured device.
DATA0
N/A
All
Input
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0 pin.
After configuration, EPC1 and EPC1441 devices tristate this pin, while enhanced and EPC2 devices drive
this pin high. In schemes that use a control host, DATA0
should be driven either high or low, whichever is more
convenient. Toggling this pin after configuration does not
affect the configured device.
DATA[7..1]
I/O
Parallel
configuration
schemes
(PPS and
PPA)
Inputs
Data inputs. Byte-wide configuration data is presented to
the target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tristated.
After PPA or PPS configuration, DATA[7..1] are
available as a user I/O pins and the state of these pin
depends on the Dual-Purpose Pin settings.
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Device Configuration Pins
Table 7–9. Dedicated Configuration Pins on the APEX 20KE & APEX 20KC Device (Part 4 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
DATA7
I/O
PPA
Bidirectional
In the PPA configuration scheme, the DATA7 pin
presents the RDYnBSY signal after the nRS signal has
been strobed low.
In serial configuration schemes, it functions as a user I/O
during configuration, which means it is tri-stated.
After PPA configuration, DATA7 is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nWS
I/O
PPA
Input
Write strobe input. A low-to-high transition causes the
device to latch a byte of data on the DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nWS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nRS
I/O
PPA
Input
Read strobe input. A low input directs the device to drive
the RDYnBSY signal on the DATA7 pin.
If the nRS pin is not used in PPA mode, it should be tied
high.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nRS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
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Configuring APEX 20KE & APEX 20KC Devices
Table 7–9. Dedicated Configuration Pins on the APEX 20KE & APEX 20KC Device (Part 5 of 5)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
RDYnBSY
I/O
PPS and PPA
Output
Ready output. A high output indicates that the target
device is ready to accept another data byte. A low output
indicates that the target device is busy and not ready to
receive another data byte.
In PPS and PPA configuration schemes, this pin will
drive out high after power-up, before configuration and
after configuration before entering user-mode.
In non-PPS and non-PPA schemes, it functions as a
user I/O during configuration, which means it is tristated.
After PPS and PPA configuration, RDYnBSY is available
as a user I/O and the state of this pin depends on the
Dual-Purpose Pin settings.
nCS/CS
I/O
PPA
Input
Chip-select inputs. A low on nCS and a high on CS select
the target device for configuration. The nCS and CS pins
must be held active during configuration and
initialization.
During the PPA configuration mode, it is only required to
use either the nCS or CS pin. Therefore, if only one chipselect input is used, the other must be tied to the active
state. For example, nCS can be tied to ground while CS
is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are available as a
user I/O pins and the state of these pins depends on the
dual-purpose pin settings.
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Device Configuration Pins
Table 7–10 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration they function as user I/O pins, which means they are tristated with weak pull-up resistors.
Table 7–10. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is on. I/O if
option is off.
Input
Optional user-supplied clock input.
Synchronizes the initialization of one or
more devices. This pin is enabled by turning
on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software
INIT_DONE
N/A if option is on. I/O if
option is off.
Output open-drain
Status pin. Can be used to indicate when
the device has initialized and is in user
mode. When nCONFIG is low and during the
beginning of configuration, the INIT_DONE
pin is tri-stated and pulled high due to an
external 10-kΩ pull-up. Once the option bit
to enable INIT_DONE is programmed into
the device (during the first frame of
configuration data), the INIT_DONE pin will
go low. When initialization is complete, the
INIT_DONE pin will be released and pulled
high and the FPGA enters user mode. Thus,
the monitoring circuitry must be able to
detect a low-to-high transition. This pin is
enabled by turning on the Enable
INIT_DONE output option in the Quartus II
software.
DEV_OE
N/A if option is on. I/O if
option is off.
Input
Optional pin that allows the user to override
all tri-states on the device. When this pin is
driven low, all I/O pins are tri-stated; when
this pin is driven high, all I/O pins behave as
programmed. This pin is enabled by turning
on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is on. I/O if
option is off.
Input
Optional pin that allows you to override all
clears on all device registers. When this pin
is driven low, all registers are cleared; when
this pin is driven high, all registers behave
as programmed. This pin is enabled by
turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II
software.
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Configuring APEX 20KE & APEX 20KC Devices
JTAG pins must be kept stable before and during configuration. JTAG pin
stability prevents accidental loading of JTAG instructions. Table 7–11
describes the dedicated JTAG pins.
Table 7–11. Dedicated JTAG Pins
Pin Name User Mode Pin Type
Description
TDI
N/A
Input
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TDO
N/A
Output
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is
not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine.Transitions within the state machine occur on
the rising edge of TCK. Therefore, TMS must be set up before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST
N/A
Input
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
APEX 20KE
Power
Sequencing
The following guidelines explain how to manage device power
sequencing for APEX 20KE devices. These guidelines apply to all
configuration schemes.
1
Altera has enhanced the APEX II and APEX 20KC devices, so
you do not need to follow these guidelines for those devices. A
system designed for an APEX 20KE device can successfully
configure an APEX II or APEX 20KC device.
The APEX 20KE logic array and I/O pins can operate on different power
supplies. VCCINT powers the logic array, and each I/O bank has a separate
VCCIO supply.
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Configuration Handbook, Volume 1
APEX 20KE Power Sequencing
These guidelines will allow you to configure APEX 20KE devices upon
power-up as well as recover from power brown-out conditions.
Specifically, VCCINT can decrease to any voltage, and the device will
successfully reconfigure when power is restored. During the brown-out
condition, APEX 20KE devices may lose configuration if VCCINT falls
below the minimum VCCINT device specification. If VCCINT drops below
the specified operating range, the APEX 20KE device resets and drives
nSTATUS low. When VCCINT is in the specified operating range, nSTATUS
will be released and configuration will begin.
1
Stratix, Stratix GX, Cyclone, APEX II, APEX 20KC, Mercury,
ACEX 1K, FLEX 10K, and FLEX 6000 devices' power supplies
(VCCINT and VCCIO) can be powered up in either order.
When configuring APEX 20KE devices in the same configuration chain as
other Altera FPGAs, you must follow these guidelines.
Power Sequencing Considerations
If the APEX 20KE device is configured by an external host, such as a
microprocessor, ensure that the configuration controller holds nCONFIG
low during power-up and then drives nCONFIG high to begin
configuration when all power supplies are stable. This applies for all
possible power-up sequences. External pull-ups used on nCONFIG,
nSTATUS, and CONF_DONE should be 10 kΩ.
To ensure recovery from brown-out conditions and successful
configuration between APEX 20KE devices and configuration devices in
all possible power-up sequences, pull nCONFIG up to VCCINT through a
10-kΩ resistor and hold nCONFIG low for the entire time that the two
supplies are powering up to their specified operating ranges. All other
external pull-up resistors used on nSTATUS, and CONF_DONE should also
be 10 kΩ.
When using enhanced configuration devices or EPC2 device, nCONFIG of
the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. Figure 7–28
shows the board connections used to support the initiate configuration
JTAG instruction with the nINIT_CONF pin.
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Configuring APEX 20KE & APEX 20KC Devices
Figure 7–28. Configuring an APEX 20KE Device Using a Configuration Device
VCC (1)
APEX 20KE Device
10 kΩ
(4)
VCCINT (2)
(2)
10 kΩ
VCC (1)
(4)
GND
nCEO
Configuration
Device
DCLK
DATA
OE (4)
nCS (4)
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
10 kΩ
N.C.
(3)
nCE
GND
Notes to Figure 7–28:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) does not need to be
connected if its functionality is not used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCCINT through a 10-kΩ resistor.
The nINIT_CONF pin has an internal pull-up resistor to 3.3 V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to isolate the 1.8-V VCCINT from the configuration
device’s 3.3-V supply. To isolate the 1.8-V and 3.3-V power supplies, add a diode between the APEX 20KE device’s
nCONFIG pin and the configuration device’s nINIT_CONF pin. Select a diode with a threshold voltage (VT) less
than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive
low or tri-state. If nINIT_CONF is not used or not available (e.g., on EPC1 devices), this diode is not needed.
The enhanced configuration devices' and EPC2 devices' OE and nCS pins have internal programmable pull-up
resistors. For successful configuration of APEX 20KE devices, you should use external 10-kΩ pull-up resistors. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
The nINIT_CONF pin is an open-drain output and has an internal pullup resistor to 3.3-V that is always active. Since a 10-kΩ pull-up to VCCINT
is required to successfully configure APEX 20KE devices, you need to
isolate the 1.8-V VCCINT from the configuration device's 3.3-V supply. To
isolate the 1.8-V and 3.3-V power supplies, add a diode between the
APEX 20KE device's nCONFIG pin and the configuration device's
nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than
or equal to 0.7 V. The diode will make the nINIT_CONF pin an opendrain pin; the pin will only be able to drive low or tri-state.
If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCCINT through a 10-kΩ resistor and the
isolating diode is not needed.
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Configuration Handbook, Volume 1
APEX 20KE Power Sequencing
Use these guidelines to ensure a successful power-up and configuration:
■
■
VCCINT is powered before VCCIO—These guidelines should be
followed for applications where the sequence of the power supplies
is unknown. It is highly recommended that you follow these
guidelines to ensure successful configuration of your APEX 20KE
device.
VCCINT is powered after VCCIO—These guidelines should be followed
if VCCIO is powered before VCCINT.
VCCINT is Powered Before VCCIO
If VCCINT is powered before VCCIO, the nCONFIG signal must be held low
for the entire time that the two supplies are powering up to their specified
operating ranges. The recommendations in this section should also be
followed for applications where the sequence of the power supplies is
unknown (e.g., hot-socketing applications). These guidelines should be
followed for all configuration schemes using a configuration device or an
external host, such as a microprocessor.
f
For more details on APEX 20KE and configuration device voltage supply
specifications, refer to the APEX 20K Programmable Logic Device Family
Data Sheet and the Configuration Devices for Altera FPGAs Data Sheet or
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet,
respectively.
Use one of the following methods to hold nCONFIG low:
■
■
■
Use a power-monitoring circuit on the board. This circuit will drive
nCONFIG low when VCCINT and VCCIO are out of range, and then
release nCONFIG. nCONFIG can then be externally pulled up when
VCCINT returns to a normal operating level. National Semiconductor
offers a small power-on reset circuit (part number LP3470) for a
power monitor.
Many voltage regulators offer a power-good signal that can be used
to hold nCONFIG low during power-up. If there are multiple
regulators, use the power-good signal on the regulator that powers
up last. If the power sequence is unknown, the power-good signals
can be ANDed in a discrete device.
A microcontroller or intelligent host can externally drive nCONFIG
low while both the VCCINT and VCCIO supplies are being powered.
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Configuring APEX 20KE & APEX 20KC Devices
VCCINT is Powered After VCCIO
If the APEX 20KE device is configured by an external host, such as a
microprocessor, ensure that the configuration controller holds nCONFIG
low during power-up and then drives nCONFIG high when all power
supplies are stable to begin of configuration.
If the APEX 20KE device is configured using a configuration device and
VCCINT is powered up during or after the configuration device has exited
POR (released nSTATUS/OE signal), nCONFIG must be tied to VCCINT
through a 10-kΩ resistor. The configuration device will exit POR 200 ms
(maximum) after power-up.
When using an enhanced configuration device to configure any Altera
FPGAs, including APEX 20KE devices, the VCCINT of the FPGA must be
powered before the enhanced configuration device exits POR (signaled
by the low-to-high transition on the OE/nSTATUS signal). Power up
needs to be controlled so that the enhanced configuration device's OE
signal goes high after the CONF_DONE signal is pulled low.
If the FPGA is not powered up after the enhanced configuration device
exits POR, the CONF_DONE signal will be high since the pull-up resistor is
pulling this signal high. When the enhanced configuration device exits
POR, OE is released and pulled high by a pull-up resistor. If the enhanced
configuration device sees its nCS/CONF_DONE signal also high, the
configuration device will go into an idle state because it sees the FPGA is
already configured. DATA and DCLK will not toggle and the enhanced
configuration device will only exit this idle state if it is powered down
and then powered up correctly.
To ensure the enhanced configuration device enters configuration mode
properly, you need to ensure that the FPGA completes its power-up
before the enhanced configuration device exits POR. Alternatively the
nSTATUS/OE line can be held low by an open-drain signal until after the
VCCINT power supply is stable.
f
Altera Corporation
July 2004
For more information about power sequencing of enhanced
configuration devices, see the Enhanced Configuration Devices (EPC4,
EPC8, & EPC16) Data Sheet in the Configuration Handbook.
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APEX 20KE Power Sequencing
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July 2004
Chapter 8. Configuring
Mercury, APEX 20K (2.5 V),
ACEX 1K & FLEX 10K Devices
CF51006-2.0
Introduction
MercuryTM, APEXTM 20K (2.5 V), ACEX® 1K, and FLEX® 10K devices can
be configured using one of four configuration schemes. All configuration
schemes use either a microprocessor or configuration device.
1
This section covers how to configure Mercury, APEX 20K (2.5
V), ACEX 1K and FLEX 10K devices. APEX 20K (non-E and nonC) devices use a 2.5-V voltage supply for VCCINT, while
APEX 20KE and APEX 20KC devices use a 1.8-V voltage supply
for VCCINT. If your target FPGA is an APEX 20K device which
uses a 1.8-V VCCINT,. For more information, see Configuring
APEX 20KE & APEX 20KC Devices in the Configuration
Handbook.
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices can be
configured using the passive serial (PS), passive parallel synchronous
(PPS), passive parallel asynchronous (PPA), and Joint Test Action Group
(JTAG) configuration schemes. The configuration scheme used is selected
by driving the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device
MSEL1 and MSEL0 pins either high or low as shown in Table 8–1. If your
application only requires a single configuration mode, the MSEL pins can
be connected to VCC (VCCIO of the I/O bank where the MSEL pin resides)
or to ground. If your application requires more than one configuration
mode, you can switch the MSEL pins after the FPGA is configured
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Preliminary
Introduction
successfully. Toggling these pins during user-mode does not affect the
device operation; however, the MSEL pins must be valid before a
reconfiguration is initiated.
Table 8–1. Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Configuration
Schemes
MSEL1
MSEL0
Configuration Scheme
0
0
PS
1
0
PPS
1
1
PPA
(1)
(1)
JTAG Based (2)
Notes to Table 8–1:
(1)
(2)
Do not leave the MSEL pins floating; connect them to a low- or high-logic level.
These pins support the non-JTAG configuration scheme used in production. If
only JTAG configuration is used, you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means MSEL pin settings are ignored.
Tables 8–2 through 8–5 show the approximate configuration file sizes for
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices.
Table 8–2. Mercury Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
Data Size (Bytes)
EP1M120
1,303,120
162,890
EP1M350
4,394,032
549,254
Table 8–3. APEX 20K (2.5 V) Raw Binary File (.rbf) Sizes
Devices
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Configuration Handbook, Volume 1
Data Size (Bits)
Data Size (Bytes)
EP20K100
993,360
124,170
EP20K200
1,950,800
243,850
EP20K400
3,880,720
485,090
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–4. ACEX 1K Raw Binary File (.rbf) Sizes
Devices
Data Size (Bits)
Data Size (Bytes)
EP1K10
159,160
19,895
EP1K30
473,720
59,215
EP1K50
784,184
98,023
EP1K100
1,335,720
166,965
Table 8–5. FLEX 10K Raw Binary File (.rbf) Sizes
Devices
Data Size (Bits)
Data Size (Bytes)
EPF10K30E
473,720
59,215
EPF10K50E
784,184
98,023
EPF10K50S
784,184
98,023
EPF10K100B
1,200,000
150,000
EPF10K100E
1,335,720
166,965
EPF10K130E
1,838,360
229,795
EPF10K200E
2,756,296
344,537
EPF10K200S
2,756,296
344,537
EPF10K10A
120,000
15,000
EPF10K30A
406,000
50,750
EPF10K50V
621,000
77,625
EPF10K100A
1,200,000
150,000
EPF10K130V
1,600,000
200,000
EPF10K250A
3,300,000
412,500
EPF10K10
118,000
14,750
EPF10K20
231,000
28,875
EPF10K30
376,000
47,000
EPF10K40
498,000
62,250
EPF10K50
621,000
77,625
EPF10K70
892,000
111,500
EPF10K100
1,200,000
150,000
Use the data in Tables 8–2 through 8–5 only to estimate the file size before
design compilation. Different configuration file formats, such as a
Hexidecimal (.hex) or Tabular Text File (.ttf) format, will have different
file sizes. However, for any specific version of the Quartus® II or
MAX+PLUS® II software, all designs targeted for the same device will
have the same configuration file size.
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Configuration Handbook, Volume 1
Passive Serial Configuration
The following chapter describes in detail how to configure Mercury,
APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices using the supported
configuration schemes. The last section describes the device
configuration pins available. In this chapter, the generic term device(s) or
FPGA(s) will include all Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices.
f
Passive Serial
Configuration
For more information on setting device configuration options or creating
configuration files, see Section II, Software Settings, in Volume 2.
You can perform Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K
PS configuration using an Altera configuration device, an intelligent host
(e.g., a microprocessor or Altera® MAX® device), or a download cable.
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure Mercury,
APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices using a serial
configuration bitstream. Configuration data is stored in the configuration
device. Figure 8–1 shows the configuration interface connections
between Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K devices and
a configuration device.
1
f
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
For more information on the configuration device and flash interface
pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and DQ[15..0]),
see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
in the Configuration Handbook.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–1. Single Device PS Configuration Using a Configuration Device
VCC(1)
VCC (1)
VCC (1)
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device 1 kΩ
1 kΩ
(3)
GND
nCEO
1 kΩ
(3)
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
(2)
N.C.
nCE
GND
Notes to Figure 8–1:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2
devices only) has an internal pull-up resistor that is always active, meaning an
external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If
nINIT_CONF is not used or not available (e.g., on EPC1 devices), nCONFIG must
be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have
internal programmable pull-up resistors. If internal pull-up resistors are used,
external pull-up resistors should not be used on these pins. The internal pull-up
resistors are used by default in the Quartus II software. To turn off the internal
pull-up resistors, check the Disable nCS and OE pull-ups on configuration device
option when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data
Sheet or the Configuration Devices for SRAM-based LUT Devices Data Sheet
in the Configuration Handbook.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC either directly or through a resistor. An
internal pull-up on the nINIT_CONF pin is always active in enhanced
configuration devices and EPC2 devices, which means an external pullup is not required if nCONFIG is tied to nINIT_CONF.
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Passive Serial Configuration
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K
device goes through a Power-On Reset (POR) for approximately 5 µs.
During POR, the device resets and holds nSTATUS low, and tri-states all
user I/O pins. The configuration device also goes through a POR delay to
allow the power supply to stabilize. The POR time for EPC2, EPC1, and
EPC1441 devices is 200 ms (maximum), and for enhanced configuration
devices, the POR time can be set to either 100 ms or 2 ms, depending on
its PORSEL pin setting. If the PORSEL pin is connected to GND, the POR
delay is 100 ms. During this time, the configuration device drives its OE
pin low. This low signal delays configuration because the OE pin is
connected to the target device’s nSTATUS pin. When both devices
complete POR, they release their open-drain OE or nSTATUS pin, which
is then pulled high by a pull-up resistor. Once the FPGA successfully exits
POR, all user I/O pins are tri-stated. Mercury, APEX 20K (2.5 V),
ACEX 1K and FLEX 10KE devices have weak pull-up resistors on the user
I/O pins which are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels to begin the configuration process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up on the
OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pullup resistor is not used, an external 1-kΩ pull-up resistor on the
OE/nSTATUS line is required. Once nSTATUS is released, the FPGA is
ready to receive configuration data and the configuration stage begins.
When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The Mercury, APEX 20K (2.5 V), ACEX 1K, or
FLEX 10K device receives configuration data on its DATA0 pin and the
clock is received on the DCLK pin. Data is latched into the FPGA on the
rising edge of DCLK.
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Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a pullup resistor. Since CONF_DONE is tied to the configuration device’s nCS
pin, the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration and EPC2 devices have an optional internal pullup resistor on the nCS pin. This option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If this internal pull-up is not used, an external 1-kΩ pull-up resistor on the
nCS/CONF_DONE line is required. A low-to-high transition on
CONF_DONE indicates configuration is complete and initialization of the
device can begin.
In Mercury and APEX 20K (2.5 V) devices, the initialization clock source
is either the FPGA's internal oscillator (typically 10 MHz) or the optional
CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If the internal oscillator is used, the Mercury or APEX 20K
(2.5 V) device will allow enough clock cycles for proper initialization.
In ACEX 1K and FLEX 10K devices, the initialization clock source is either
an external host (e.g. a configuration device or microprocessor) or the
optional CLKUSR pin. By default, an external host must provide the
initialization clock on the DCLK pin. Programming files generated by the
Quartus II or MAX+PLUS II software already have these initialization
clock cycles included in the file.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. You can turn on the Enable usersupplied start-up clock (CLKUSR) option in the Quartus II software from
the General tab of the Device & Pin Options dialog box. Supplying a
clock on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
Mercury devices require 136 clock cycles to initialize properly, APEX 20K
(2.5 V) devices require 40 clock cycles, ACEX 1K and FLEX 10K devices
require 10 clock cycles.
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Passive Serial Configuration
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 1-kΩ pullup resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the FPGA has entered user mode. In user-mode, the user I/O
pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device and EPC2
device drive DCLK low and DATA high (EPC1 devices tri-state DATA) at the
end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option available in the Quartus II software from the General
tab of the Device & Pin Options dialog box is turned on, the FPGA
automatically initiates reconfiguration if an error occurs. The Mercury,
APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device releases its nSTATUS
pin after a reset time-out period (maximum of 40 µs). When the nSTATUS
pin is released and pulled high by a pull-up resistor, the configuration
device reconfigures the chain. If this option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low to
restart configuration. The external system can pulse nCONFIG if
nCONFIG is under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. EPC1 and EPC2 devices wait for 16 DCLK cycles. In this
case, the configuration device pulls its OE pin low, which in turn drives
the target device’s nSTATUS pin low. If the Auto-Restart Configuration
After Error option is set in the software, the target device resets and then
releases its nSTATUS pin after a reset time-out period (maximum of
40 µs). When nSTATUS returns high, the configuration device tries to
reconfigure the FPGA.
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Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. When nCONFIG is pulled low, the FPGA
also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Since CONF_DONE is pulled low, this will activate the configuration
device since it will see its nCS pin drive low. Once nCONFIG returns to a
logic high state and nSTATUS is released by the FPGA, reconfiguration
begins.
Figure 8–2 shows how to configure multiple devices with a configuration
device. This circuit is similar to the configuration device circuit for a
single device, except Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices are cascaded for multi-device configuration.
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Passive Serial Configuration
Figure 8–2. Multi-Device PS Configuration Using a Configuration Device
VCC (1)
1 kΩ
VCC (1)
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 2
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC (1)
1 kΩ
(3)
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
GND
GND
N.C.
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 1
(3)
(2)
nCEO
nCE
nCEO
nCE
GND
Notes to Figure 8–2:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
When performing multi-device configuration, you must generate the
configuration device’s Programmer Object File (.pof) from each project’s
SRAM Object File (.sof). You can combine multiple SOFs using the
Quartus II software.
f
For more information on how to create configuration files for multidevice configuration chains, see Section II, Software Settings, in Volume 2.
8–10
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they can
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLK and DATA lines are buffered
for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the configuration device and drives
nSTATUS low on all FPGAs, which causes them to enter a reset state. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUS pins after a reset time-out period
(maximum of 40 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the AutoRestart Configuration After Error option is turned off, the external system
must monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
Enhanced configuration devices also support parallel configuration of up
to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode allows
enhanced configuration devices to concurrently configure FPGAs or a
chain of FPGAs. In addition, these devices do not have to be the same
device family or density; they can be any combination of Altera FPGAs.
An individual enhanced configuration device DATA line is available for
each targeted FPGA. Each DATA line can also feed a daisy chain of FPGAs.
Figure 8–3 shows how to concurrently configure multiple devices using
an enhanced configuration device.
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July 2004
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Passive Serial Configuration
Figure 8–3. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
(1) VCC
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device 1 1 kΩ
N.C.
nCEO
(3)
VCC (1)
(3)
1 kΩ
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA0
nCE
OE (3)
MSEL1
MSEL0
DATA1
DATA[2..6]
nCS (3)
Mercury, APEX 20K (2.5-V)
GND
ACEX 1K or FLEX 10K Device 2
GND
N.C.
nCEO
Enhanced
Configuration
Device
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
nINIT_CONF (2)
DATA 7
nCE
GND
GND
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device 8
DCLK
DATA0
nSTATUS
CONF_DONE
N.C. nCEO
nCONFIG
MSEL1
MSEL0
nCE
GND
GND
Notes to Figure 8–3:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
8–12
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 8–6 to
select the appropriate configuration mode for the fastest configuration
times.
Table 8–6. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 8–6:
(1)
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus
II software. On the printed circuit board (PCB), leave the DATA3 line from
the enhanced configuration device unconnected. Figure 8–4 shows the
Quartus II Convert Programming Files window (Tools menu) setup for
this scheme.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–4. Software Settings for Configuring Devices Using n-Bit PS Modes
Alternatively, you can daisy chain two FPGAs to one DATA line while the
other DATA lines drive one device each. For example, you could use the
2-bit PS mode to drive two FPGAs with DATA Bit0 (EPF10K100E and
EP20K400 devices) and the third device (the EP1M350 device) with DATA
Bit1. This 2-bit PS configuration scheme requires less space in the
configuration flash memory, but can increase the total system
configuration time. See Figure 8–5.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–5. Software Settings for Daisy Chaining Two FPGAs on One DATA
Line
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 8–6 shows multi-device
PS configuration when the Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices are receiving the same configuration data.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–6. Multiple-Device PS Configuration Using an Enhanced Configuration Device When FPGAs
Receive the Same Data
(1) VCC
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device 1 KΩ
(4) N.C.
nCEO
(3)
VCC (1)
(3)
1 KΩ
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
Enhanced
Configuration
Device
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
nCE
MSEL1
MSEL0
Mercury, APEX 20K (2.5-V) GND
ACEX 1K or FLEX 10K Device
GND
(4) N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL1
MSEL0
GND
GND
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device
(4) N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
MSEL0
nCE
GND
GND
Notes to Figure 8–6:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
The nCEO pins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
You can cascade several EPC2 or EPC1 devices to configure multiple
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices. The first
configuration device in the chain is the master configuration device,
while the subsequent devices are the slave devices. The master
configuration device sends DCLK to the Mercury, APEX 20K (2.5 V),
ACEX 1K, and FLEX 10K devices and to the slave configuration devices.
The first EPC device’s nCS pin is connected to the CONF_DONE pins of the
FPGAs, while its nCASC pin is connected to nCS of the next configuration
device in the chain. The last device’s nCS input comes from the previous
device, while its nCASC pin is left floating. When all data from the first
configuration device is sent, it drives nCASC low, which in turn drives
nCS on the next configuration device. Because a configuration device
requires less than one clock cycle to activate a subsequent configuration
device, the data stream is uninterrupted.
1
Enhanced configuration devices EPC4, EPC8, and EPC16 cannot
be cascaded.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONE going high
at the end of configuration, it resets the entire chain by pulling its OE pin
low. This low signal drives the OE pin low on the slave configuration
device(s) and drives nSTATUS low on all FPGAs, causing them to enter a
reset state. This behavior is similar to the FPGA detecting an error in the
configuration data.
Figure 8–7 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–7. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC (1)
VCC (1)
VCC (1)
(3) 1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or Flex 10K Device 2
MSEL0
MSEL1
(2)
1 kΩ (3)
Mercury, APEX 20K (2.5-V),
ACEX 1K or Flex 10K Device 1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCEO
nCE
nCEO
EPC2/EPC1
Device 1
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
GND
GND
N.C.
1 kΩ
EPC2/EPC1
Device 2
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 8–7:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used or not available (e.g., on EPC1 devices),
nCONFIG must be pulled to VCC either directly or through a resistor. An
internal pull-up on the nINIT_CONF pin is always active in the enhanced
configuration devices and the EPC2 devices, which means an external
pull-up is not required if nCONFIG is tied to nINIT_CONF. If multiple
EPC2 devices are used to configure a Mercury, APEX 20K (2.5 V),
ACEX 1K, and FLEX 10K device(s), only the first EPC2 has its
nINIT_CONF pin tied to the device’s nCONFIG pin.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
You can use a single configuration chain to configure Mercury,
APEX 20K, ACEX 1K, and FLEX 10KE devices with other Altera devices.
To ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 8–8 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 8–8. PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
tDSU
tCL
D0
D1
tCH
tDH
tOEZX
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 8–8:
(1)
Mercury devices enter user-mode 136 clock cycles after CONF_DONE goes high. APEX 20K devices enter user-mode
40 clock cycles after CONF_DONE goes high. The initialization clock can come from the Mercury or APEX 20K
internal oscillator or the CLKUSR pin. ACEX 1K and FLEX 10K devices enter user-mode 10 clock cycles after
CONF_DONE goes high. The initialization clock can come from DCLK or CLKUSR.
f
For timing information, refer to the Configuration Handbook Section
Altera Configuration Devices, the Enhanced Configuration Devices (EPC4,
EPC8, and EPC16) Data Sheet or the Configuration Devices for SRAM-based
LUT Devices Data Sheet in the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, Volume 2 of the
Configuration Handbook.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
PS Configuration Using a Microprocessor
In the PS configuration scheme, an intelligent host (e.g., a microprocessor
or CPLD) can transfer configuration data from a storage device (e.g., flash
memory) to the target Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices. Configuration data can be stored in RBF, HEX, or TTF
format. Figure 8–9 shows the configuration interface connections
between the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device
and a microprocessor for single device configuration.
Figure 8–9. Single Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
(1) VCC
1 kΩ
VCC (1)
Mercury, APEX 20K (2.5-V)
ACEX 1K or FLEX 10K Device
1 kΩ
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCEO
nCE
Microprocessor
GND
N.C.
GND
DATA0
nCONFIG
DCLK
Note to Figure 8–9:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal
for the device.
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K
device goes through a POR for approximately 5 µs. During POR, the
device resets and holds nSTATUS low, and tri-states all user I/O pins.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE devices have
weak pull-up resistors on the user I/O pins which are on before and
during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should place the configuration data one
bit at a time on the DATA0 pin. The least significant bit (LSB) of each data
byte must be sent first.
The Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device receives
configuration data on its DATA0 pin and the clock is received on the DCLK
pin. Data is latched into the FPGA on the rising edge of DCLK. Data is
continuously clocked into the target device until CONF_DONE goes high.
After the FPGA has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by an
external 1-kΩ pull-up resistor. A low-to-high transition on CONF_DONE
indicates configuration is complete and initialization of the device can
begin.
In Mercury and APEX 20K (2.5 V) devices, the initialization clock source
is either the FPGA's internal oscillator (typically 10 MHz) or the optional
CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If the internal oscillator is used, the Mercury or APEX 20K
(2.5 V) device allows enough clock cycles for proper initialization.
In ACEX 1K and FLEX 10K devices, the initialization clock source is either
an external host (e.g. a configuration device or microprocessor) or the
optional CLKUSR pin. By default, the clock on DCLK is the clock source for
initialization. Programming files generated by the Quartus II or
MAX+PLUS II software already have these initialization clock cycles
included in the file. Therefore, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Mercury devices require 136 clock cycles to initialize properly, APEX 20K
(2.5 V) devices require 40 clock cycles, ACEX 1K and FLEX 10K devices
require 10 clock cycles.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-up resistors and
will function as assigned in your design. To ensure DCLK and DATA are
not left floating at the end of configuration, the microprocessor must
drive them either high or low, whichever is convenient on your board.
Handshaking signals are not used in PS configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option (available in the Quartus II software from
the General tab of the Device & Pin Options dialog box) is turned on, the
Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device releases
nSTATUS after a reset time-out period (maximum of 40 µs). After
nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition on nCONFIG to restart the
configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 21 µs for Mercury devices, 8 µs for APEX 20K devices and
2 µs for ACEX 1K and Flex 10K devices. When nCONFIG is pulled low, the
FPGA also pulls nSTATUS and CONF_DONE low and all I/O pins are tristated. Once nCONFIG returns to a logic high state and nSTATUS is
released by the FPGA, reconfiguration begins.
Figure 8–10 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the PS configuration circuit for a
single device, except Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices are cascaded for multi-device configuration.
Figure 8–10. Multi-Device PS Configuration Using a Microprocessor
Memory
ADDR
DATA0
VCC (1)
VCC (1)
1 kΩ
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 1
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 2
MSEL1
MSEL1
CONF_DONE
MSEL0
nSTATUS
nCE
Microprocessor
CONF_DONE
GND
nCEO
MSEL0
nSTATUS
GND
nCE
GND
nCEO
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C.
Note to Figure 8–10:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
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July 2004
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Passive Serial Configuration
In multi-device PS configuration the first device’s nCE pin is connected to
GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they can require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLK and DATA lines
are buffered for every fourth device. Because all device CONF_DONE pins
are tied together, all devices initialize and enter user mode at the same
time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition on nCONFIG to restart the configuration
process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 8–11 shows multi-device
PS configuration when Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices are receiving the same configuration data.
8–24
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–11. Multiple-Device PS Configuration Using a Microprocessor When Both FPGAs Receive the Same
Data
Memory
ADDR
DATA0
VCC (1)
VCC (1)
1 kΩ
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
MSEL1
CONF_DONE
nSTATUS
nCE
Microprocessor
MSEL1
MSEL0
CONF_DONE
GND
nCEO
GND
nCE
N.C. (2)
GND
MSEL0
nSTATUS
nCEO
GND
DATA0
DATA0
nCONFIG
nCONFIG
DCLK
DCLK
N.C. (2)
Notes to Figure 8–11:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure Mercury,
APEX 20K, ACEX 1K, and FLEX 10KE devices with other Altera devices.
To ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 8–12 shows the timing waveform for the PS configuration for
Mercury, APEX 20K, ACEX 1K, and FLEX 10KE devices when using a
microprocessor.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–12. PS Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (1)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (2)
tCF2CD
tST2CK
tCH tCL
(3)
DCLK
tDH
Bit 0 Bit 1 Bit 2 Bit 3
DATA
Bit n
(3)
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 8–12:
(1)
(2)
(3)
Upon power-up, the Mercury, APEX 20K, ACEX 1K, or FLEX 10K device holds nSTATUS low for not more than 5
µs after VCC reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is more
convenient.
Tables 8–7 through 8–10 defines the timing parameters for Mercury,
APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices for PS
configuration.
Table 8–7. PS Timing Parameters for Mercury Devices (Part 1 of 2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Note (1)
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
21
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
Max
Units
200
ns
200
ns
µs
40 (2)
µs
1 (2)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
45
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
8–26
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–7. PS Timing Parameters for Mercury Devices (Part 2 of 2)
Symbol
Parameter
Note (1)
Min
Max
Units
tCH
DCLK high time
10
ns
tCL
DCLK low time
10
ns
tCLK
DCLK period
20
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (3)
6
ns
50
MHz
28
µs
Notes to Table 8–7:
(1)
(2)
(3)
This information is preliminary.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
Table 8–8. PS Timing Parameters for APEX 20K Devices
Max
Units
tCF2CD
Symbol
nCONFIG low to CONF_DONE low
Parameter
Min
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
8
µs
tSTATUS
nSTATUS low pulse width
10
40 (1)
µs
tCF2ST1
nCONFIG high to nSTATUS high
1 (1)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
tST2CK
tDSU
40
µs
nSTATUS high to first rising edge on DCLK
1
µs
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
15
ns
tCL
DCLK low time
15
ns
tCLK
DCLK period
30
ns
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (2)
2
33.3
MHz
8
µs
Notes to Table 8–8:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Table 8–9. PS Timing Parameters for ACEX & FLEX 10KE Devices
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
2
µs
tSTATUS
nSTATUS low pulse width
1
10 (1)
µs
tCF2ST1
nCONFIG high to nSTATUS high
4 (1)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
tST2CK
tDSU
5
µs
nSTATUS high to first rising edge on DCLK
1
µs
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
15
ns
tCL
DCLK low time
15
ns
tCLK
DCLK period
30
ns
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (2)
0.6
33.3
MHz
2
µs
Notes to Table 8–9:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
The minimum and maximum numbers apply only if DCLK is chosen as the clock source for starting up the device.
If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.
Table 8–10. PS Timing Parameters for FLEX 10K Devices (Part 1 of 2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
1
tCF2ST1
nCONFIG high to nSTATUS high
Max
Units
200
ns
200
ns
µs
10 (1)
µs
4 (1)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
5
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
30
ns
tCL
DCLK low time
30
ns
tCLK
DCLK period
60
ns
8–28
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–10. PS Timing Parameters for FLEX 10K Devices (Part 2 of 2)
Symbol
Parameter
fMAX
DCLK maximum frequency
tCD2UM
CONF_DONE high to user mode (2)
Min
0.6
Max
Units
16.7
MHz
2
µs
Notes to Table 8–10:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
The minimum and maximum numbers apply only if DCLK is chosen as the clock source for starting up the device.
If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, in Volume 2 of the
Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver allows you to configure Altera’s
FPGAs through the ByteBlasterMV cable in PS mode. The MicroBlaster
software driver supports a RBF programming input file and is targeted
for embedded passive serial configuration. The source code is developed
for the Windows NT operating system, although you can customize it to
run on other operating systems. For more information on the
MicroBlaster software driver, go to the Altera web site
(http://www.altera.com).
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB Blaster universal serial bus (USB) port download cable,
MasterBlasterTM serial/USB communications cable, ByteBlasterTM II
parallel port download cable, and the ByteBlasterMVTM parallel port
download cable.
In PS configuration with a download cable, an intelligent host (e.g., a PC)
transfers data from a storage device to the FPGA via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K
device goes through a POR for approximately 5 µs. During POR, the
device resets and holds nSTATUS low, and tri-states all user I/O pins.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE devices have
weak pull-up resistors on the user I/O pins which are on before and
during configuration.
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Passive Serial Configuration
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
The configuration cycle consists of 3 stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high.
When using a download cable, setting the Auto-Restart Configuration After
Error option does not affect the configuration cycle because you must
manually restart configuration in the Quartus II software when an error
occurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)
option has no affect on the device initialization since this option is
disabled in the SOF when programming the FPGA using the Quartus II
programmer and download cable. Therefore, if you turn on the CLKUSR
option, you do not need to provide a clock on CLKUSR when you are
configuring the FPGA with the Quartus II programmer and a download
cable. Figure 8–13 shows PS configuration for Mercury, APEX 20K (2.5
V), ACEX 1K, and FLEX 10K devices using a USB Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cable.
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Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–13. PS Configuration Using a USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV Cable
VCC (1)
VCC (1)
1 kΩ
(2)
1 kΩ
VCC (1)
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
MSEL0
VCC (1)
1 kΩ
(2)
MSEL1
1 kΩ
VCC (1)
1 kΩ
CONF_DONE
nSTATUS
GND
nCE
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
GND
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 8–13:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB
Blaster, MasterBlaster (VIO pin), ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable
is the only configuration scheme used on your board. This is to ensure that DATA0
and DCLK are not left floating after configuration. For example, if you are also
using a configuration device, the pull-up resistors on DATA0 and DCLK are not
needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver.
VIO should match the device’s VCCIO. Refer to the MasterBlaster Serial/USB
Communications Cable Data Sheet for this value. In the ByteBlasterMV, this pin is
a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE
when it is used for Active Serial programming, otherwise it is a no connect.
You can use a download cable to configure multiple Mercury, APEX 20K
(2.5 V), ACEX 1K, and FLEX 10K devices by connecting each device’s
nCEO pin to the subsequent device’s nCE pin. The first device’s nCE pin is
connected to GND while its nCEO pin is connected to the nCE of the next
device in the chain. The last device’s nCE input comes from the previous
device, while its nCEO pin is left floating. All other configuration pins,
nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE are connected to
every device in the chain. Because all CONF_DONE pins are tied together,
all devices in the chain initialize and enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-Restart
Configuration After Error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
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July 2004
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–14 shows how to configure multiple Mercury, APEX 20K (2.5 V),
ACEX 1K, and FLEX 10K devices with a download cable.
Figure 8–14. Multi-Device PS Configuration Using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV Cable
VCC (1)
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 1
VCC (1)
1 kΩ
MSEL1
(2)
VCC (1)
1 kΩ
VCC (1)
1 kΩ
CONF_DONE
nSTATUS
DCLK
MSEL0
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
(2)
Pin 1
VCC
GND
VIO (3)
GND
nCEO
nCE
1 kΩ
GND
DATA0
nCONFIG
MSEL0
MSEL1
GND
CONF_DONE
nSTATUS
DCLK
GND
nCE
nCEO
N.C.
DATA0
nCONFIG
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 2
Notes to Figure 8–14:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active
Serial programming, otherwise it is a no connect.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration device from the target device(s) and cable. One way to
isolate the configuration device is to add logic, such as a multiplexer, that
can select between the configuration device and the cable. The
multiplexer chip should allow bidirectional transfers on the nSTATUS
and CONF_DONE signals. Another option is to add switches to the five
common signals (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
between the cable and the configuration device. The last option is to
remove the configuration device from the board when configuring the
FPGA with the cable. Figure 8–15 shows a combination of a configuration
device and a download cable to configure an FPGA.
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July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 8–15. PS Configuration with a Download Cable & Configuration Device Circuit
VCC (1)
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
VCC (1)
1 kΩ
(4)
MSEL0
MSEL1
Download Cable
10-Pin Male Header
(PS Mode)
(5) VCC (1)
(5)
1 kΩ
Pin 1
CONF_DONE
nSTATUS
DCLK
VCC
GND
VIO (2)
GND
nCE
nCEO
N.C.
GND
DATA0
nCONFIG
(3)
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (5)
nCS (5)
(3)
nINIT_CONF (4)
Notes to Figure 8–15:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it
is used for Active Serial programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to a
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K device. Instead, you should either remove the configuration
device from its socket when using the download cable or place a switch on the five common signals between the
download cable and the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used
or not available (e.g., on EPC1 devices), nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-up resistors on configuration device option when generating programming files.
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV cables, refer to the following data
sheets.
■
■
■
■
USB Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
8–34
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Passive Parallel
Synchronous
Configuration
Passive parallel synchronous (PPS) configuration uses an intelligent host,
such as a microprocessor, to transfer configuration data from a storage
device, such as flash memory, to the target Mercury, APEX 20K (2.5 V),
ACEX 1K, or FLEX 10K device. Configuration data can be stored in TTF,
RBF, or HEX format. The host system outputs byte-wide data and the
serializing clock to the FPGA. The target device latches the byte-wide
data on the DATA[7..0] pins on the rising edge of DCLK and then uses
the next eight falling edges on DCLK to serialize the data internally. On the
ninth rising DCLK edge, the next byte of configuration data is latched into
the target device. Figure 8–16 shows the configuration interface
connections between the FPGA and a microprocessor for single device
configuration.
Figure 8–16. Single Device PPS Configuration Using a Microprocessor
VCC VCC
Memory
(1) 1 kΩ
(1)
1 kΩ
APEX 20K (2.5-V),
ACEX 1K, Mercury, or
FLEX 10K Device
MSEL0
ADDR DATA[7..0]
GND
VCC
MSEL1
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
DCLK
nCONFIG
Note to Figure 8–16:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device.
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K or FLEX 10K
device goes through a Power-On Reset (POR) for approximately 5 µs.
During POR, the device resets and holds nSTATUS low, and tri-states all
user I/O pins. Once the FPGA successfully exits POR, all user I/O pins
are tri-stated. Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K
devices have weak pull-up resistors on the user I/O pins which are on
before and during configuration.
f
Altera Corporation
July 2004
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
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Passive Parallel Synchronous Configuration
The configuration cycle consists of 3 stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the microprocessor must
generate a low-to-high transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should place the configuration data one
byte at a time on the DATA[7..0] pins. New configuration data should
be sent to the FPGA every eight DCLK cycles.
The Mercury, APEX 20K (2.5 V), ACEX 1K or FLEX 10K device receives
configuration data on its DATA[7..0] pins and the clock is received on
the DCLK pin. On the first rising DCLK edge, a byte of configuration data
is latched into the target device; the subsequent eight falling DCLK edges
serialize the configuration data in the device. On the ninth rising clock
edge, the next byte of configuration data is latched and serialized into the
target device.
Data is clocked into the target device until CONF_DONE goes high. After
the FPGA has received all configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 1-kΩ
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin.
In Mercury and APEX 20K devices, the initialization process is
synchronous and can be clocked by its internal oscillator (typically
10 MHz) or by the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If the internal oscillator is used, the
Mercury or APEX 20K device will take care to provide itself with enough
clock cycles for proper initialization. Therefore, if the internal oscillator is
the initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
8–36
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Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
In ACEX 1K and FLEX 10K devices, initialization can be clocked by the
clock input on the DCLK pin or by the optional CLKUSR pin. By default,
the clock on DCLK is the clock source for initialization. The configuration
files created by the Quartus II and the MAX+PLUS II software
incorporate the extra bits for proper device initialization. Therefore,
sending the entire configuration file to the device is sufficient to configure
and initialize the device. Driving DCLK to the device after configuration is
complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
Mercury devices require 136 clock cycles to initialize properly. APEX 20K
devices require 40 clock cycles, while ACEX 1K and FLEX 10K devices
require 10 clock cycles.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ
pull-up when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-ups and will
function as assigned in your design. When initialization is complete, the
FPGA enters user mode.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the microprocessor must take care to drive them either
high or low, whichever is convenient on your board. The DATA[7..1]
pins are available as user I/O pins after configuration. When the PPS
scheme is chosen in the Quartus II software, as a default these I/O pins
are tri-stated in user mode and should be driven by the microprocessor.
To change this default option in the Quartus II software, select the DualPurpose Pins tab of the Device & Pin Options dialog box.
Altera Corporation
July 2004
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8–37
Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
The configuration clock (DCLK) speed must be below the specified
frequency, as listed in Tables 8–12 through 8–14, to ensure correct
configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time. An
optional status pin (RDYnBSY) on the FPGA indicates when it is busy
serializing configuration data and when it is ready to accept the next data
byte. The RDYnBSY pin is not required in the PPS mode. Configuration
data can be sent every 8 DCLK cycles without monitoring this status pin.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration on Error option-available in the Quartus II software from the
General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of 40
µs). After nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition on nCONFIG to restart the
configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE have not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 21 µs for Mercury devices, 8 µs for APEX 20K devices and
2 µs for ACEX 1K and FLEX 10K devices. When nCONFIG is pulled low,
the FPGA also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. Once nCONFIG returns to a logic high state and nSTATUS is
released by the FPGA, reconfiguration begins.
Figure 8–17 shows how to configure multiple Mercury, APEX 20K (2.5 V),
ACEX 1K or FLEX 10K devices using a microprocessor. This circuit is
similar to the PPS configuration circuit for a single device, except the
devices are cascaded for multi-device configuration.
8–38
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–17. Multi-Device PPS Configuration Using a Microprocessor
(1) VCC
1 kΩ
APEX 20K (2.5-V),
ACEX 1K, Mercury, or
FLEX 10K Device 1
1 kΩ
APEX 20K (2.5-V),
ACEX 1K, Mercury, or
FLEX 10K Device 2
MSELO
MSELO
Memory
GND
ADDR DATA[7..0]
GND
VCC
VCC
MSEL 1
CONF_DONE
nSTATUS
nCE
Microprocessor
VCC (1)
GND
nCEO
DATA[7..0]
DCLK
nCONFIG
MSEL 1
CONF_DONE
nSTATUS
nCE
DATA[7..0]
DCLK
nCONFIG
Note to Figure 8–17:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPS configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
Altera recommends keeping the configuration data valid on the
DATA[7..0] bus for the 8 serializing clock cycles. The configuration data
should be held valid on the DATA bus for the complete byte period
because the nCEO of the first (and preceding) device can go low during
the serializing DCLK cycles. Once the nCEO of the first (and preceding)
device goes low, the second (and next) device becomes active and will
begin trying to accept configuration data. If the configuration data is not
valid on the first DCLK edge after nCEO goes low, then the second device
will see incorrect configuration data and will never begin accepting
configuration data. This situation will only arise if you are sharing the
DATA[7..0] bus with other system data such that the configuration data
is only valid for a portion of the byte period.
Altera Corporation
July 2004
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Passive Parallel Synchronous Configuration
If your system requires to bus-share the DATA[7..0] line, you can workaround this by ensuring that the second (or next) device sees correct
configuration data on the first rising edge of DCLK after the nCEO signal
goes low. This can be achieved by delaying the nCEO signal by using
external registers or by presenting the next byte of configuration data
after the nCEO transition.
All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0],
and CONF_DONE) are connected to every device in the chain. You should
pay special attention to the configuration signals because they may
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLK and DATA lines are buffered
for every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration on Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition on nCONFIG to restart the configuration
process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 8–18 shows
multi-device PPS configuration when both devices are receiving the same
configuration data.
8–40
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–18. Multiple-Device PPS Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
VCC
(1) 1 kΩ
APEX 20K (2.5-V),
ACEX 1K, Mercury, or
FLEX 10K Device 1
VCC
1 kΩ (1)
APEX 20K (2.5-V),
ACEX 1K, Mercury, or
FLEX 10K Device 2
MSELO
MSELO
Memory
GND
ADDR DATA[7..0]
GND
VCC
VCC
MSEL 1
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
MSEL 1
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
DATA[7..0]
DCLK
nCONFIG
GND
DATA[7..0]
DCLK
nCONFIG
nCEO
N.C.
Notes to Figure 8–18:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure Mercury, APEX 20K
(2.5 V), ACEX 1K or FLEX 10KE devices with other Altera devices that
support PPS configuration, such as APEX 20KE devices. To ensure that all
devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 8–19 shows the timing waveform for the PPS configuration
scheme using a microprocessor.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
Figure 8–19. Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10KE PPS Configuration Timing Waveform
tCFG
nCONFIG
(1) nSTATUS
tCF2CK
DCLK
tCH
7.5 Cycles
ZZ
tCLK
(3)
tDSU
DATA[7..0]
tCL
tDH
Byte 1
Byte 0
Byte n
FF
User Mode
(3)
tCH2B
(4) RDYnBSY
User Mode
(3)
(2) CONF_DONE
INIT_DONE
User I/O
High z
High z
User Mode
tCD2UM
Notes to Figure 8–19:
(1)
(2)
(3)
(4)
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE device holds nSTATUS low for
approximately 5 µs after VCC reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
DATA0 and DCLK should not be left floating after configuration. It should be driven high or low, whichever is more
convenient. DATA[7..1] and RDYnBSY are available as user I/O pins after configuration and the state of theses
pins depends on the design programmed into the device.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
Tables 8–12 through 8–14 define the timing parameters for Mercury,
APEX 20K, ACEX 1K, and FLEX 10K devices for PPS configuration.
Table 8–11. PPS Timing Parameters for Mercury Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
21
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
45
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH2B
First rising DCLK to first rising RDYnBSY (2)
0.75 (3)
µs
8–42
Configuration Handbook, Volume 1
Core Version a.b.c variable
µs
40 (1)
µs
1 (1)
µs
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–11. PPS Timing Parameters for Mercury Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Units
tCH
DCLK high time
10
ns
tCL
DCLK low time
10
ns
tCLK
DCLK period
20
ns
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (4)
6
50
MHz
28
µs
Notes to Table 8–11:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the rising
edge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
Table 8–12. PPS Timing Parameters for APEX 20K Devices (Part 1 of 2)
Symbol
Parameter
Min
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
8
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
tST2CK
tDSU
Max
Units
200
ns
200
ns
µs
40 (1)
µs
1 (1)
µs
40
µs
nSTATUS high to first rising edge on DCLK
1
µs
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH2B
First rising DCLK to first rising RDYnBSY (2)
0.75 (3)
µs
tCH
DCLK high time
15
ns
tCL
DCLK low time
15
ns
tCLK
DCLK period
30
ns
fMAX
DCLK frequency
Altera Corporation
July 2004
33.3
Core Version a.b.c variable
MHz
8–43
Configuration Handbook, Volume 1
Passive Parallel Synchronous Configuration
Table 8–12. PPS Timing Parameters for APEX 20K Devices (Part 2 of 2)
Symbol
tCD2UM
Parameter
CONF_DONE high to user mode (4)
Min
Max
Units
2
8
µs
Notes to Tables 8–12:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the rising
edge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
Table 8–13. PPS Timing Parameters for ACEX 1K & FLEX 10KE Devices
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
1
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
5
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH2B
First rising DCLK to first rising RDYnBSY (2)
0.75 (3)
µs
tCH
DCLK high time
15
ns
tCL
DCLK low time
15
ns
tCLK
DCLK period
30
ns
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (4)
0.6
µs
10 (1)
µs
4 (1)
µs
33.3
MHz
2
µs
Notes to Table 8–13:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the rising
edge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.
The minimum and maximum numbers apply only if DCLK is chosen as the clock source for starting up the device.
If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.
8–44
Configuration Handbook, Volume 1
Core Version a.b.c variable
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–14. PPS Timing Parameters for FLEX 10K Devices
Max
Units
tCF2CD
Symbol
nCONFIG low to CONF_DONE low
Parameter
Min
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
1
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
5
µs
tST2CK
nSTATUS high to first rising edge on DCLK
1
µs
tDSU
Data setup time before rising edge on DCLK
10
ns
tDH
Data hold time after rising edge on DCLK
0
ns
µs
10 (1)
µs
4 (1)
µs
tCH2B
First rising DCLK to first rising RDYnBSY (2)
0.75 (3)
µs
tCH
DCLK high time
30
ns
tCL
DCLK low time
30
ns
tCLK
DCLK period
60
ns
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode (4)
0.6
16.7
MHz
2
µs
Notes to Table 8–14:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
The RDYnBSY pin is not required in the PPS mode. Configuration data can be sent every 8 DCLK cycles without
monitoring this status pin.
This parameter depends on the DCLK frequency. The RDYnBSY signal goes high 7.5 clock cycles after the rising
edge of DCLK. This value was calculated with a DCLK frequency of 10 MHz.
The minimum and maximum numbers apply only if DCLK is chosen as the clock source for starting up the device.
If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.
f
Passive Parallel
Asynchronous
Configuration
Altera Corporation
July 2004
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, in Volume 2 of the
Configuration Handbook.
Passive Parallel Asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target Mercury, APEX 20K
(2.5 V), ACEX 1K, and FLEX 10K devices. Configuration data can be
stored in TTF, RBF, or HEX format. The host system outputs byte-wide
data and the accompanying strobe signals to the FPGA. When using PPA,
you should pull the DCLK pin high through a 1-kΩ pull-up resistor to
prevent unused configuration input pins from floating.
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Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Figure 8–20 shows the configuration interface connections between the
FPGA and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCS and CS. The address decoder allows the
microprocessor to select the Mercury, APEX 20K (2.5 V), ACEX 1K, or
FLEX 10K device by accessing a particular address, which simplifies the
configuration process. The nCS and CS pins must be held active during
configuration and initialization.
Figure 8–20. Single Device PPA Configuration Using a Microprocessor
Note (1)
Address Decoder
ADDR
VCC (2)
Memory
ADDR DATA[7..0]
1 kΩ
VCC (2)
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device VCC
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
MSEL1
MSEL0
nCEO
N.C.
VCC (2)
1 kΩ
DCLK
Notes to Figure 8–20:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if only one chip-select input is used, the other must be tied
to the active state. For example, nCS can be tied to ground while CS is
toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Tables 8–15 through 8–17.
Upon power-up, the Mercury, APEX 20K (2.5 V), ACEX 1K, or FLEX 10K
device goes through a Power-On Reset (POR) for approximately 5 µs.
During POR, the device resets and holds nSTATUS low, and tri-states all
user I/O pins. Once the FPGA successfully exits POR, all user I/O pins
8–46
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
are tri-stated. Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10KE
devices have weak pull-up resistors on the user I/O pins which are on
before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on
before and during configuration can be found in the Operating
Conditions table of the appropriate device family data sheet.
The configuration cycle consists of 3 stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT and VCCIO pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUS is released the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the Mercury, APEX 20K (2.5 V),
ACEX 1K, or FLEX 10K device is processing the byte of configuration
data.
During the time RDYnBSY is low, the Mercury, APEX 20K (2.5 V),
ACEX 1K, or FLEX 10K device internally processes the configuration data
using its internal oscillator (typically 10 MHz). When the device is ready
for the next byte of configuration data, it will drive RDYnBSY high. If the
microprocessor senses a high signal when it polls RDYnBSY, the
microprocessor sends the next byte of configuration data to the FPGA.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Data should not be driven onto the data bus while nRS is low because it
will cause contention on the DATA7 pin. If the nRS pin is not used to
monitor configuration, it should be tied high.
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Passive Parallel Asynchronous Configuration
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY(max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The tBUSY, tRDY2WS and
tW2SB timing specifications are listed in Tables 8–15 through 8–17.
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. After the FPGA
has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 1-kΩ pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin.
In Mercury and APEX 20K (2.5 V) devices, the initialization clock source
is either the FPGA's internal oscillator (typically 10 MHz) or the optional
CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If the internal oscillator is used, the Mercury or APEX 20K
(2.5 V) device allows enough clock cycles for proper initialization.
Therefore, sending the entire configuration file to the device is sufficient
to configure and initialize the device.
In ACEX 1K and FLEX 10K devices, the initialization clock source is either
an external host (e.g. a configuration device or microprocessor) or the
optional CLKUSR pin. By default, in PPA, the device uses its internal
oscillator (typically 10MHz) to clock the initialization cycle. The
ACEX 1K or FLEX 10K device will take care to provide itself with enough
clock cycles for proper initialization.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSR option. The Enable user-supplied start-up
clock (CLKUSR) option can be turned on in the Quartus II software from
the General tab of the Device & Pin Options dialog box. Supplying a
clock on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
Mercury devices require 136 clock cycles to initialize properly, APEX 20K
(2.5 V) devices require 40 clock cycles, ACEX and FLEX 10K devices
require 10 clock cycles.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 1-kΩ pullup when nCONFIG is low and during the beginning of configuration.
Once the option bit to enable INIT_DONE is programmed into the device
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
(during the first frame of configuration data), the INIT_DONE pin will go
low. When initialization is complete, the INIT_DONE pin will be released
and pulled high. The microprocessor must be able to detect this low-tohigh transition which signals the FPGA has entered user mode. In usermode, the user I/O pins will no longer have weak pull-up resistors and
will function as assigned in your design. When initialization is complete,
the FPGA enters user mode.
To ensure DATA0 is not left floating at the end of configuration, the
microprocessor must take care to drive them either high or low,
whichever is convenient on your board. After configuration, the nCS, CS,
nRS, nWS, RDYnBSY, and DATA[7..1] pins can be used as user I/O pins.
When the PPA scheme is chosen in the Quartus II software, as a default
these I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the FPGA drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUS after a reset time-out period (maximum of 40
µs). After nSTATUS is released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition on nCONFIG to restart the
configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONE or INIT_DONE has not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 21 µs for Mercury devices, 8 µs for APEX 20K devices, and
2 µs for ACEX 1K and FLEX 10K devices. When nCONFIG is pulled low,
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Passive Parallel Asynchronous Configuration
the FPGA also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. Once nCONFIG returns to a logic high state and nSTATUS is
released by the FPGA, reconfiguration begins.
Figure 8–21 shows how to configure multiple Mercury, APEX 20K (2.5 V),
ACEX 1K, and FLEX 10K devices using a microprocessor. This circuit is
similar to the PPA configuration circuit for a single device, except the
devices are cascaded for multi-device configuration.
Figure 8–21. Multi-Device PPA Configuration Using a Microprocessor
VCC (2)
VCC (2)
1 kΩ
(2) VCC
1 kΩ
1 kΩ
Address Decoder
VCC (2)
ADDR
Memory
1 kΩ
ADDR DATA[7..0]
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 1
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Microprocessor
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
VCC
MSEL1
MSEL0
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device 2
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C.
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 8–21:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPA configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
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Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
Each device’s RDYnBSY pin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSY pins can feed an AND gate and the output of the AND gate can
feed the microprocessor. For example, if you have 2 devices in a PPA
configuration chain, the second device’s RDYnBSY pin will be high during
the time that the first device is being configured. When the first device has
been successfully configured, it will driven nCEO low to activate the next
device in the chain and drive its RDYnBSY pin high. Therefore, since
RDYnBSY signal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the AND gate.
The nRS signal can be used in multi-device PPA chain since the Mercury,
APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device will tri-state its
DATA[7..0] pins before configuration and after configuration before
entering user-mode to avoid contention. Therefore, only the device that is
currently being configured will respond to the nRS strobe by asserting
DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRS and CONF_DONE) are connected to every device in the chain.
You should pay special attention to the configuration signals because
they may require buffering to ensure signal integrity and prevent clock
skew problems. Specifically, ensure that the DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUS pins after a reset time-out period (maximum of 40
µs). After all nSTATUS pins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIG low. If this option is turned off, the microprocessor must
generate a low-to-high transition on nCONFIG to restart the configuration
process.
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Passive Parallel Asynchronous Configuration
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..1], nCS, CS, nWS,
nRS and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they
may require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 8–22 shows
multi-device PPA configuration when both devices are receiving the
same configuration data.
Figure 8–22. Multiple-Device PPA Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
VCC (2)
VCC (2)
1 kΩ
(2) VCC
1 kΩ
1 kΩ
Address Decoder
VCC (2)
ADDR
Memory
1 kΩ
ADDR DATA[7..0]
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
GND
DCLK
nCEO
Microprocessor
nWS
nRS
nCONFIG
RDYnBSY
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
N.C. (3)
VCC
MSEL1
MSEL0
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO N.C. (3)
nCE
nWS
VCC
nRS
MSEL1
nCONFIG
MSEL0
RDYnBSY
Notes to Figure 8–22:
(1)
(2)
(3)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
You can use a single configuration chain to configure Mercury, APEX
20K, ACEX, and FLEX 10KE devices with other Altera devices that
support PPA configuration, such as Stratix® or APEX II devices. To
ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, see Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 8–23 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
Figure 8–23. PPA Configuration Timing Waveform
tCFG
tCF2ST1
nCONFIG
nSTATUS (1)
CONF_DONE (2)
Byte 0
DATA[7..0]
Byte 1
Byte n 1
Byte n
(4)
tCSH
(4)
tDSU
(3) CS
tCF2WS
tCSSU
tDH
(4)
(3) nCS
tWSP
(4)
nWS
tRDY2WS
(4)
RDYnBSY
tWS2B
tSTATUS
tBUSY
tCF2ST0
tCF2CD
User I/Os
tCD2UM
High-Z
High-Z
User-Mode
INIT_DONE
Notes to Figure 8–23:
(1)
(2)
(3)
(4)
Upon power-up, the Mercury, APEX 20K, ACEX 1K, or FLEX 10K device holds nSTATUS low for not more than 5 µs
after VCC reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Figure 8–24 shows the timing waveform for the PPA configuration
scheme when using a strobed nRS and nWS signal.
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Passive Parallel Asynchronous Configuration
Figure 8–24. PPA Configuration Timing Waveform Using nRS & nWS
tCF2ST1
tCFG
nCONFIG
(1) nSTATUS
tSTATUS
tCF2SCD
(2) CONF_DONE
tCSSU
(4)
nCS (3)
tCSH
(4)
CS (3)
tDH
Byte 0
DATA[7..0]
(4)
Byte n
Byte 1
tDSU
(4)
nWS
tWSP
tRS2WS
tWS2RS
tCF2WS
nRS
(4)
tWS2RS
tRSD7
INIT_DONE
tRDY2WS
User I/O
High-Z
User-Mode
tWS2B
(4)
DATA7/RDYnBSY (5)
tCD2UM
tBUSY
Notes to Figure 8–24:
(1)
(2)
(3)
(4)
(5)
Upon power-up, the Mercury, APEX 20K, ACEX 1K, or FLEX 10K device holds nSTATUS low for not more than 5 µs
after VCC reaches its minimum requirement.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA0 should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
DATA7 is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Tables 8–15 through 8–17 define the timing parameters for Mercury,
APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices for PPA
configuration.
Table 8–15. PPA Timing Parameters for Mercury Devices (Part 1 of 2)
Symbol
Parameter
Note (1)
Min
Max
Units
tCF2CD
nCONFIG low to CONF_DONE low
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
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Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–15. PPA Timing Parameters for Mercury Devices (Part 2 of 2)
Symbol
Parameter
tSTATUS
nSTATUS low pulse width
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge on nWS
Note (1)
Min
Max
Units
10
40 (2)
µs
1 (2)
µs
10
ns
tCSH
Chip select hold time after rising edge on nWS
0
ns
tCF2WS
nCONFIG high to first rising edge on nWS
40
µs
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
tWSP
nWS low pulse width
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
0.4
tRDY2WS
RDYnBSY rising edge to nWS rising edge
50
ns
tWS2RS
nWS rising edge to nRS falling edge
200
ns
tRS2WS
nRS rising edge to nWS rising edge
200
ns
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
CONF_DONE high to user mode (3)
0
ns
200
ns
6
50
ns
1.6
µs
50
ns
28
µs
Notes to Table 8–15:
(1)
(2)
(3)
This information is preliminary.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
Table 8–16. PPA Timing Parameters for APEX 20K Devices (Part 1 of 2)
Max
Units
tCF2CD
Symbol
nCONFIG low to CONF_DONE low
Parameter
200
ns
tCF2ST0
nCONFIG low to nSTATUS low
200
ns
tCFG
nCONFIG low pulse width
8
10
tSTATUS
nSTATUS low pulse width
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge on nWS
Min
10
µs
40 (1)
µs
1 (1)
µs
ns
tCSH
Chip select hold time after rising edge on nWS
0
ns
tCF2WS
nCONFIG high to first rising edge on nWS
40
µs
tDSU
Data setup time before rising edge on nWS
10
ns
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Passive Parallel Asynchronous Configuration
Table 8–16. PPA Timing Parameters for APEX 20K Devices (Part 2 of 2)
Symbol
Parameter
tDH
Data hold time after rising edge on nWS
tWSP
nWS low pulse width
Min
Max
Units
0
ns
200
ns
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
0.1
tRDY2WS
RDYnBSY rising edge to nWS rising edge
50
ns
tWS2RS
nWS rising edge to nRS falling edge
200
ns
tRS2WS
nRS rising edge to nWS rising edge
200
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
CONF_DONE high to user mode (2)
2
50
ns
1.6
µs
ns
50
ns
8
µs
Notes to Table 8–16:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
Table 8–17. PPA Timing Parameters for ACEX 1K & FLEX 10K Devices (Part 1 of 2)
Symbol
Parameter
tCF2CD
nCONFIG low to CONF_DONE low
Min
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
1
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge on nWS
tCSH
Chip select hold time after rising edge on nWS
tCF2WS
tDSU
Max
Units
200
ns
200
ns
µs
10 (1)
µs
4 (1)
µs
20
ns
10 (2)
15 (3)
ns
nCONFIG high to first rising edge on nWS
5
µs
Data setup time before rising edge on nWS
20
ns
tDH
Data hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
0.4
tRDY2WS
RDYnBSY rising edge to nWS rising edge
50
ns
tWS2RS
nWS rising edge to nRS falling edge
200
ns
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ns
50
ns
1.6
µs
Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–17. PPA Timing Parameters for ACEX 1K & FLEX 10K Devices (Part 2 of 2)
Symbol
Parameter
tRS2WS
nRS rising edge to nWS rising edge
tRSD7
nRS falling edge to DATA7 valid with RDYnBSY signal
tCD2UM
CONF_DONE high to user mode (4)
Min
Max
200
0.6
Units
ns
50
ns
2
µs
Notes to Table 8–17:
(1)
(2)
(3)
(4)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
This parameter value applies to EPF10K10, EPF10K20, EPF10K40, EPF10K50, all FLEX 10KA, and FLEX 10KE
devices.
This parameter value applies to only EPF10K70 and EPF10K100 devices.
If the clock source is CLKUSR, multiply the clock period by 10 to obtain this value.
f
JTAG
Configuration
f
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, in Volume 2 of the
Configuration Handbook.
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture offers
the capability to efficiently test components on PCBs with tight lead
spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is
operating normally. The JTAG circuitry can also be used to shift
configuration data into the device.
For more information on JTAG boundary-scan testing, see Application
Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. All user I/O pins are tri-stated
during JTAG configuration. Mercury, APEX 20K (2.5 V), ACEX 1K, and
FLEX 10K devices are designed such that JTAG instructions have
precedence over any device configuration modes. This means that JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K FPGAs during PS
configuration, PS configuration will be terminated and JTAG
configuration will begin.
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JTAG Configuration
Table 8–18 explains each JTAG pin’s function.
Table 8–18. JTAG Pin Descriptions
Pin
Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data.
Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TDO
Test data output
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMS must be set up before
the rising edge of TCK. TMS is evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST (1)
Test reset input (optional)
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
Note to Table 8–18:
(1)
FLEX 10K devices in 144-pin thin quad flat pack (TQFP) packages do not have a TRST pin. Therefore, the TRST pin
can be ignored when using these devices.
1
If VCCIO of the bank where the JTAG pins reside, are tied to
3.3-V, both the I/O pins and JTAG TDO port will drive at 3.3-V
levels.
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV header. Configuring devices through a cable is similar to
programming devices in-system, except the TRST pin should be
connected to VCC. This ensures that the TAP controller is not reset.
Figure 8–25. shows JTAG configuration of a single Mercury, APEX 20K
(2.5 V), ACEX 1K, or FLEX 10K device.
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Altera Corporation
July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Figure 8–25. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
1 kΩ
(1) VCC
VCC (1)
(1) VCC
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
1 kΩ
nCE (4)
GND N.C.
(2)
(2)
(2)
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
1 kΩ
TCK
TDO
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
VCC
TRST
Pin 1
VCC
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 8–25:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II, or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active
Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
JTAG Configuration
Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices have
dedicated JTAG pins that always function as JTAG pins. JTAG testing can
be performed on Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K
devices both before and after configuration, but not during configuration.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices do
not affect JTAG boundary-scan or programming operations. Toggling
these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of Mercury, APEX 20K
(2.5 V), ACEX 1K, and FLEX 10K devices, the dedicated configuration
pins should be considered. Table 8–19 shows how these pins should be
connected during JTAG configuration.
Table 8–19. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices in the chain, nCE should
be driven low by connecting it to ground, pulling it low via a resistor, or driving it by some control
circuitry. For devices that are also in multi-device PS, PPS or PPA configuration chains, the nCE
pins should be connected to GND during JTAG configuration or JTAG configured in the same
order as the configuration chain.
nCEO
On all Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K devices in the chain, nCEO can be
left floating or connected to the nCE of the next device. See nCE description above.
MSEL
These pins must not be left floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG
Driven high by connecting to VCC, pulling high via a resistor, or driven by some control circuitry.
nSTATUS
Pull to VCC via a 1-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
nSTATUS pin should be pulled up to VCC individually. nSTATUS pulling low in the middle of JTAG
configuration indicates that an error has occurred.
CONF_DONE Pull to VCC via a 1-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONE pin should be pulled up to VCC individually. CONF_DONE going high at the end of
JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0
Should not be left floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header
is connected to several devices. The number of devices in the JTAG chain
is limited only by the drive capability of the download cable. When four
or more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 8–26 shows multi-device JTAG configuration.
Figure 8–26. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
(1) VCC
(1) VCC
Pin 1
VCC
(1) VCC
(2)
(2)
(2)
1 kΩ
VCC
VIO
(3)
(1) VCC
(1) VCC
1 kΩ
1 kΩ
1 kΩ
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
1 kΩ
nSTATUS
nCONFIG
MSEL0 CONF_DONE
MSEL1
nCE (4)
TRST
TDI
TDO
TMS
TCK
(2)
(2)
(2)
VCC
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
(1) VCC (1) VCC
1 kΩ
1 kΩ
nSTATUS
(2)
nCONFIG
(2)
MSEL0 CONF_DONE
(2)
MSEL1
nCE (4)
VCC
TRST
TDI
TDO
TMS
TCK
(1) VCC
1 kΩ
nSTATUS
nCONFIG
MSEL0 CONF_DONE
MSEL1
nCE (4)
TRST
TDI
TDO
TMS
TCK
1 kΩ
Notes to Figure 8–26:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The nCONFIG, MSEL0, and MSEL1 pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV, this
pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE when it is used for Active
Serial programming, otherwise it is a no connect.
nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, PPS, and PPA configuration chains, the
first device’s nCE pin is connected to GND while its nCEO pin is
connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device
configuration chain, its nCEO pin drives low to activate the second
device’s nCE pin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, you
should make sure the nCE pins are connected to GND during JTAG
configuration or that the devices are JTAG configured in the same order
as the configuration chain. As long as the devices are JTAG configured in
the same order as the multi-device configuration chain, the nCEO of the
previous device will drive nCE of the next device low when it has
successfully been JTAG configured.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
JTAG Configuration
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
f
For more information about configuring multiple Altera devices in the
same configuration chain, see Configuring Mixed Altera FPGA Chains in
the Configuration Handbook.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONE through the JTAG port. If CONF_DONE is not high, the
Quartus II software indicates that configuration has failed. If CONF_DONE
is high, the software indicates that configuration was successful. When
Quartus II generates a JAM file for a multi-device chain, it contains
instructions so that all the devices in the chain will be initialized at the
same time.
Figure 8–27 shows JTAG configuration of a Mercury, APEX 20K (2.5 V),
ACEX 1K, or FLEX 10K FPGA with a microprocessor.
Figure 8–27. JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR
Mercury, APEX 20K (2.5-V),
ACEX 1K or FLEX 10K Device
(3) nCE
DATA
GND
VCC
Microprocessor
TRST
TDI
TCK
TMS
TDO
nCEO
nCONFIG
MSEL0
MSEL1
nSTATUS
CONF_DONE
N.C.
(2)
(2)
(2)
VCC (1)
VCC(1)
1 kΩ
1 kΩ
Notes to Figure 8–27:
(1)
(2)
(3)
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain.
Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG
configuration scheme. If your design only uses JTAG configuration, connect the
nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground.
nCE must be connected to GND or driven low for successful JTAG configuration.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
f
For more information on JTAG and Jam STAPL in embedded
environments, see AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web site
at:
www.altera.com/support/software/download/programming/jam/
jam-index.jsp
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K
FPGAs with JRunner
JRunner is a software driver that allows you to configure Altera FPGAs,
including Mercury, APEX 20K (2.5 V), ACEX 1K, and FLEX 10K FPGAs,
through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The
programming input file supported is in RBF format. JRunner also
requires a Chain Description File (.cdf) generated by the Quartus II
software. JRunner is targeted for embedded JTAG configuration. The
source code has been developed for the Windows NT operating system
(OS). You can customize the code to make it run on other platforms.
f
Altera Corporation
July 2004
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files.
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Configuration Handbook, Volume 1
Device Configuration Pins
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration related pins on the Mercury, APEX 20K (2.5 V), ACEX 1K,
or FLEX 10K device. Table 8–20 describes the dedicated configuration
pins, which are required to be connected properly on your board for
successful configuration. Some of these pins may not be required for your
configuration schemes.
Table 8–20. Dedicated Configuration Pins (Part 1 of 4)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
MSEL0
MSEL1
N/A
All
Input
Two-bit configuration input that sets the Mercury,
APEX 20K (2.5 V), ACEX 1K, or FLEX 10K device
configuration scheme. See Table 8–6 for the appropriate
connections. These pins must remain at a valid state
during power-up, before nCONFIG is pulled low to initiate
a reconfiguration and during configuration.
VCCSEL
N/A
All
Input
This pin is only available in Mercury devices. Dedicated
input that ensures the configuration related I/O banks
have powered up to the appropriate 1.8-V or 2.5-V/3.3-V
voltage levels before starting configuration. A logic high
(1.5 V, 1.8 V, 2.5 V, 3.3 V) means 2.5 V/3.3 V, and a logic
low means 1.8 V.
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low during
user-mode will cause the FPGA to lose its configuration
data, enter a reset state, tri-state all I/O pins, and
returning this pin to a logic high level will initiate a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, nCONFIG can be
tied directly to VCC or to the configuration device’s
nINIT_CONF pin.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–20. Dedicated Configuration Pins (Part 2 of 4)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nSTATUS
N/A
All
Bidirectional
open-drain
The FPGA drives nSTATUS low immediately after
power-up and releases it within 5 µs. (When using a
configuration device, the configuration device holds
nSTATUS low for up to 200 ms.)
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If a configuration
device is used, driving nSTATUS low will cause the
configuration device to attempt to configure the FPGA,
but since the FPGA ignores transitions on nSTATUS in
user-mode, the FPGA will not reconfigure. To initiate a
reconfiguration, nCONFIG must be pulled low.
The enhanced configuration devices’ and EPC2 devices’
OE and nCS pins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
CONF_DONE
N/A
All
Bidirectional
open-drain
Status output. The target FPGA drives the CONF_DONE
pin low before and during configuration. Once all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The enhanced configuration devices’ and EPC2 devices’
OE and nCS pins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin
must be held low during configuration, initialization, and
user mode. In single device configuration, it should be
tied low. In multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to nCE
of the next device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the FPGA.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Device Configuration Pins
Table 8–20. Dedicated Configuration Pins (Part 3 of 4)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nCEO
N/A
All
Output
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCE pin. The nCEO of the last device in the
chain is left floating.
DCLK
N/A
Synchronous
configuration
schemes (PS
and PPS)
Input
Clock input used to clock data from an external source
into the target device. Data is latched into the FPGA on
the rising edge of DCLK.
In PPA mode, DCLK should be tied high to VCC to prevent
this pin from floating.
After configuration, this pin is tri-stated. In schemes that
use a configuration device, DCLK will be driven low after
configuration is done. In schemes that use a control
host, DCLK should be driven either high or low,
whichever is more convenient. Toggling this pin after
configuration does not affect the configured device.
DATA0
N/A
All
Input
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0 pin.
After configuration, EPC1 and EPC1441 devices tristate this pin, while EPC2 devices drive this pin high. In
schemes that use a control host, DATA0 should be
driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
DATA[7..1]
I/O
Parallel
configuration
schemes
(PPS and
PPA)
Inputs
Data inputs. Byte-wide configuration data is presented to
the target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tristated.
After PPA or PPS configuration, DATA[7..1] are
available as a user I/O pins and the state of these pin
depends on the Dual-Purpose Pin settings.
DATA7
I/O
PPA
Bidirectional
In the PPA configuration scheme, the DATA7 pin
presents the RDYnBSY signal after the nRS signal has
been strobed low.
In serial configuration schemes, it functions as a user I/O
during configuration, which means it is tri-stated.
After PPA configuration, DATA7 is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
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July 2004
Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices
Table 8–20. Dedicated Configuration Pins (Part 4 of 4)
Pin Name
User Configuration
Mode
Scheme
Pin Type
Description
nWS
I/O
PPA
Input
Write strobe input. A low-to-high transition causes the
device to latch a byte of data on the DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nWS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nRS
I/O
PPA
Input
Read strobe input. A low input directs the device to drive
the RDYnBSY signal on the DATA7 pin.
If the nRS pin is not used in PPA mode, it should be tied
high.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nRS is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
RDYnBSY
I/O
PPS and PPA
Output
Ready output. A high output indicates that the target
device is ready to accept another data byte. A low output
indicates that the target device is busy and not ready to
receive another data byte.
In PPS and PPA configuration schemes, this pin will
drive out high after power-up, before configuration and
after configuration before entering user-mode.
In non-PPS and non-PPA schemes, it functions as a
user I/O during configuration, which means it is tristated.
After PPS and PPA configuration, RDYnBSY is available
as a user I/O and the state of this pin depends on the
Dual-Purpose Pin settings.
nCS/CS
I/O
PPA
Input
Chip-select inputs. A low on nCS and a high on CS select
the target device for configuration. The nCS and CS pins
must be held active during configuration and
initialization.
During the PPA configuration mode, it is only required to
use either the nCS or CS pin. Therefore, if only one chipselect input is used, the other must be tied to the active
state. For example, nCS can be tied to ground while CS
is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are available as a
user I/O pins and the state of these pins depends on the
Dual-Purpose Pin settings.
Altera Corporation
July 2004
Core Version a.b.c variable
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Configuration Handbook, Volume 1
Device Configuration Pins
Table 8–21 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration they function as user I/O pins, which means they are tristated with weak pull-up resistors.
Table 8–21. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is on. I/O if
option is off.
Input
Optional user-supplied clock input.
Synchronizes the initialization of one or
more devices. This pin is enabled by turning
on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software
INIT_DONE
N/A if option is on. I/O if
option is off.
Output open-drain
Status pin. Can be used to indicate when
the device has initialized and is in user
mode. When nCONFIG is low and during the
beginning of configuration, the INIT_DONE
pin is tri-stat