Qualcomm Technologies International, Ltd.

Qualcomm Technologies International, Ltd.
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Qualcomm Technologies International, Ltd.
Confidential and Proprietary – Qualcomm Technologies International, Ltd.
(formerly known as Cambridge Silicon Radio Ltd.)
NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to:
[email protected]
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Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies International, Ltd.or its
affiliated companies without the express approval of Qualcomm Configuration Management.
Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express
written permission of Qualcomm Technologies International, Ltd.
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Any software provided with this notice is governed by the Qualcomm Technologies International, Ltd. Terms of Supply or the applicable
license agreement at https://www.csrsupport.com/CSRTermsandConditions.
Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated
trademarks are used with permission. Other product and brand names may be trademarks or registered trademarks of their respective
owners.
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This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and
international law is strictly prohibited.
© 2015 Qualcomm Technologies International, Ltd. All rights reserved.
Qualcomm Technologies International, Ltd.
Churchill House
Cambridge Business Park
Cambridge, CB4 0WZ
United Kingdom
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CSRA64215 QFN is a single-chip Bluetooth ROM audio
solution for rapid evaluation and development of
Bluetooth ROM stereo applications.
≤he CSRA64215 QFN consumer audio platform for
wired and wireless applications using the QFN package
integrates an ultra-low power DSP and application
processor, high-performance stereo codec, a power
management subsystem and LED drivers.
≤he CSR configuration tools and the development kit
provide a flexible and powerful development platform to
design advanced and high-quality Bluetooth stereo
products using the CSRA64215 QFN single-chip
Bluetooth audio solution.
v4.2 System
co
®
2.4 GHz
Radio
+
Balun
ROM
SQIF
RAM
≥AR≤/≥SB
Baseband
I /O
Serial Flash
PIO
MC≥
Audio In / Out
Kalimba
DSP
Debug SPI
Stereo speakers
Speakerphones
≤he enhanced Kalimba DSP coprocessor with
80 MIPS supports enhanced audio and DSP
applications.
≤he integrated audio codec supports stereo input and
output with 1-mic cVc hands-free input, 1 digital
microphone (MEMS) interface, as well as a variety of
audio standards.
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 1 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
Bluetooth® v4.2 specification compliant
80 MHz RISC MC≥ and 80 MIPS Kalimba DSP
High-performance stereo codec with 1 microphone
input (shared with line input) and 1 digital
microphone (MEMS) interface
Radio includes integrated balun with RF
performance of 9 dBm (typ) transmit power and
-90.5 dBm (typ) BDR receiver sensitivity
AVRCP v1.6
≤rueWireless Stereo (≤WS)
≥ser and manufacturer configurable EQs
Wideband speech supported by HFP v1.6 and
mSBC codec
CSR's latest cVc technology for narrowband and
wideband voice connections including wind noise
reduction
Multipoint support for A2DP connection to 2
A2DP sources for music playback
Secure simple pairing, CSR's proximity pairing and
CSR's proximity connections
Serial interfaces: ≥SB 2.0, ≥AR≤, I²C and SPI
Audio interfaces: PCM/I²S, SPDIF input, analogue/
stereo line and digital microphone
aptX, aptX Low Latency, SBC and AAC decoder
support
Wired audio support
Integrated dual switch-mode regulators, linear
regulators and battery charger
External crystal load capacitors not required for
typical crystals
3 LED outputs (RGB)
68-lead QFN 8 x 8 x 0.9 mm 0.4 mm pitch
Green (RoHS compliant and no antimony or
halogenated flame retardants)
8 x 8 x 0.9 mm
0.4 mm pitch
≤ape and reel
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QFN 68-lead
(Pb free)
CSRA64215A11 IQQF R
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CSRA64215
Stereo ROM
Solution with aptX
CSRA64215 QFN is a ROM-based device where the product code has the form CSRA64215Axx. Axx is the specific
ROM-variant, A11 is the ROM-variant for CSRA64215 Stereo ROM Solution with aptX.
Minimum order quantity is 2kpcs taped and reeled.
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www.csr.com
[email protected]
www.csrsupport.com
[email protected]
[email protected]
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General information
Information on this product
Customer support for this product
Details of compliance and standards
Help with this document
DK 64215 10258 1A
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CSRA64215 Stereo ROM Solution with aptX Audio Development Kit
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Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 2 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
CSR's manufacturing policy is to multisource volume products. For further details, contact your local
sales account manager or representative.
Automatic power switching to charger when present
2 high-efficiency switch-mode regulators with 1.8 V
and 1.35 V outputs direct from battery supply
3.3 V linear regulator for ≥SB supply
Low-voltage linear regulator for internal digital circuits
Low-voltage linear regulator for internal analogue
circuits
Power-on-reset detects low supply voltage
Power management includes digital shutdown and
wake-up commands for ultra-low power modes
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Fully integrated synthesiser requires no external
VCO, varactor diode, resonator or loop filter
Compatible with crystals 16 MHz to 32 MHz
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Enhanced Kalimba DSP coprocessor, 80 MIPS,
24 bit fixed point core
2 single-cycle MACs: 24 x 24-bit multiply and 56-bit
accumulator
32-bit instruction word, dual 24-bit data memory
6K x 32-bit program RAM including 1K instruction
cache for executing out of internal ROM
16K x 24-bit + 16K x 24-bit 2-bank data RAM
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PCM/I²S interface
SPDIF input (uncompressed PCM only)
Stereo audio ADC with line input
Stereo audio DAC
Supported sample rates of 8, 11.025, 16, 22.05, 32,
44.1, 48 and 96 kHz (DAC only)
Crystal oscillator with built-in digital trimming
Lithium ion / Lithium polymer battery charger
Instant-on function automatically selects the power
supply between battery and ≥SB, which enables
operation even if the battery is fully discharged
Fast charging support up to 200 mA with no external
components. Higher charge currents using external
pass device.
Supports ≥SB charger detection
Support for thermistor protection of battery pack
Support to enable end product design to PSE law:
Design to JIS-C 8712/8714 (batteries)
≤esting based on IEEE 1725
Internal ROM
Memory protection unit supporting accelerated VM
56 KB internal RAM, enables full-speed data transfer,
and full piconet support
Logic for forward error correction, header error
control, access code correlation, CRC,
demodulation, encryption bit stream generation,
whitening and transmit pulse shaping
68-lead QFN 8 x 8 x 0.9 mm 0.4 mm pitch
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 3 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
-92.0 dBm (typ) /4 DQPSK receiver sensitivity and
-82.0 dBm (typ) 8DPSK receiver sensitivity
Integrated channel filters
Digital demodulator for improved sensitivity and cochannel rejection
Real-time digitised RSSI available to application
Fast AGC for enhanced dynamic range
Channel classification for AFH
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9 dBm (typ) RF transmit power with level control
Class 1, Class 2 and Class 3 support, no external
PA or ≤X/RX switch required
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On-chip balun (50 impedance)
No production trimming of external components
Bluetooth v4.2 specification compliant
≥AR≤ interface for debug
≥SB 2.0 (full-speed) interface, including ≥SB BC1.2
charger detection
4-bit SPI flash memory interface
SPI interface for debug and programming
I²C master for amp control
≥p to 14 general purpose PIOs
3 LED drivers (includes RGB) with PWM flasher
independent of MC≥
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Bluetooth low energy radio
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Support for multi-language programmable audio
prompts
CSR's proximity pairing and CSR's proximity
connection
Multipoint support for A2DP connection to 2 A2DP
sources for music playback
≤alk-time extension
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 4 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
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Configures the CSRA64215 stereo ROM solution with
Bluetooth v4.2 specification support
aptX software features:
A2DP v1.3
AVRCP v1.6
Bluetooth v4.2 specification features
HFP v1.6
Reconnection policies, e.g. reconnect on power-on
HSP v1.2
Audio features, including default volumes
DI v1.3
Button events: configuring button presses and
durations for certain events, e.g. double press on
Music Enhancements
PIO for last number redial
aptX, aptX Low Latency, SBC and AAC
LED indications for states, e.g. device connected,
≤rueWireless Stereo (≤WS)
and events, e.g. power on
Configurable Signal Detection to trigger events
Indication tones for events and ringtones
≥p to 10 stages of Speaker Parametric EQ
Battery divider ratios and thresholds, e.g. thresholds
≥p to 6 banks of 5 stages of ≥ser Parametric EQ for
for battery low indication, full battery etc.
music playback (user, rock, pop, classical, jazz, etc)
Advanced Multipoint settings
MeloD Expansion 3D stereo widening and phase
shifting effect
Volume Control
Example CSRA64215 QFN module design
Compander to compress or expand the dynamic
Carrier board
range of the audio
Output stage: headphone amplifier
Post Mastering to improve DAC fidelity
Interface adapters and cables
Volume Boost
I2C
Master
SPI
(Debug)
PIO Serial Flash
UART
R G B
USB
Serial Flash
Interface
UART
4 Mbps
LED PWM
Control and
Output
USB v2.0
Full-speed
XTAL
AIO[0]
Clock
Generation
3.3 V
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PIO Port
DMA ports
AUX ADC
DMA ports
Bluetooth Modem
Bluetooth
Baseband
Bluetooth Radio
and Balun
BT_RF
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RX
DMA ports
LINE/MIC_AP
LINE_BN
High-quality ADC
LINE_BP
SPKR_LN
High-quality DAC
Audio
Interface
SPKR_LP
SPKR_RN
High-quality DAC
SPKR_RP
VDD_AUDIO
VDD_AUDIO_DRV
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ROM
LINE/MIC_AN
High-quality ADC
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Memory
Management
Unit
MIC Bias
Voltage / Temperature
Monitor
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DM1
MCU
Kalimba DSP
DM2
PCM1 /
I2S1
VM Accelerator
(MPU)
VBAT
PMU
Interface
and
BIST
Engine
0.85 V to
1.25 V
Low-voltage
VDD_DIG
Linear
Regulator
SENSE
1.35 V
Low-voltage
VDD_ANA
Linear
Regulator
1.35 V
Low-voltage
VDD_AUX
Linear
Regulator
SENSE
SENSE
1.8 V
Switchmode
Regulator
SENSE
1.35 V
Switchmode
Regulator
SENSE
Bypass
LDO
Li-ion
Charger
VBAT_SENSE
CHG_EXT
VCHG
SENSE
VOUT_3V3
SMPS_1V35_SENSE
LX_1V35
SMPS_1V8_SENSE
LXL_1V8
VDD_AUX
VDD_AUX_1V8
VDD_ANA
VDD_BT_RADIO
VDD_DIG
VREGIN_DIG
Digital Audio
Digital Audio
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
PCM2 /
I2S2
MIC_BIAS
Switch
PIO Port
PM
CSRA64215 QFN Data Sheet
System
RAM
TX
G-TW-0014411.3.2
I2C
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SPI_DEBUG
Page 5 of 106
CS-323092-DSP3
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04 FEB 15
Original publication of this document.
Issue 2
29 J≥L 15
≥pdates include:
≥pdated product code and document year, and changed status to Engineering
Sample.
≥pdated Bluetooth version to v4.2.
Added aptX-LL.
Corrected notes in Package Dimensions section.
Removed sentence about EDR from RF Receiver section.
≤able 7.1: Added PIO[21,18:16].
≥pdated PS Key name in ≥AR≤ section.
Deleted Machine Model ESD document from Document References section.
≥pdated SMPS images.
Correct pin name in RF Ports section.
≥pdated schematics.
Added Inductor Choice section.
≥pdated text in the Reset section.
Added entries and updated values in Absolute Maximum Ratings and
Recommended Operating Conditions.
Removed erroneous comment in Software section.
Removed incorrect PIO definition from ≤erms and Definitions section.
Functional Block Diagram updated to remove mention of I2C Slave.
Section 15 aptX sentence changed from 'encoder' to 'decoder' and include
mention of AAC support.
6th Generation cVc changed to 8th Generation throughout.
Section 15.3.5 screenshot updated and 'hard limiter' support added.
References to 1-mic cVc changed to 1-mic cVc hands-free throughout.
Power consumption table modified to remove unwanted cVc entries.
Issue 3
04 NOV 15
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Changes include:
Minor correction to Functional Block Diagram.
Removed footnotes in Electrical Characterisation.
Different text in footer, including Production status.
≥pdated QFN reel image.
≥pdated Development Kit ordering code.
Added Power Consumption values.
Added SPDIF information.
Clarification of I²S/PCM interface.
Removed LED as PIO descriptions.
Added PS Keys for changing ≥AR≤ and I²C assignments.
Added multiple language support to Audio Prompt description.
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 6 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
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Issue 1
≤he status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:
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Information for designers concerning CSR product in development. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
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Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an
Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values
specified are only given as guidance to the final specification limits and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum
and maximum values specified are only given as guidance to the final specification limits and must not be considered as
the final values.
All electrical specifications may be changed by CSR without notice.
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As the feature-set of the CSRA64215 QFN is firmware build-specific, see the relevant software release note for the exact
implementation of features on the CSRA64215 QFN.
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Life Support Policy and ≥se in Safety-critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. ≥se in such applications is done at the sole
discretion of the customer. CSR will not warrant the use of its devices in such applications.
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CSRA64215 QFN devices meet the requirements of Directive 2011/65/E≥ of the European Parliament and of the Council on the
Restriction of Hazardous Substance (RoHS). CSRA64215 QFN devices are free from halogenated or antimony trioxide-based flame
retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green
Semiconductor Products.
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≥nless otherwise stated, words and logos marked with or ® are trademarks registered or owned by CSR plc or its affiliates.
Bluetooth ® and the Bluetooth ® logos are trademarks owned by Bluetooth ® SIG, Inc. and licensed to CSR. Other products, services
and names used in this document may have been trademarked by their respective owners.
≤he publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc
and/or its affiliates.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any
errors.
Refer to www.csrsupport.com for compliance and conformance to standards information.
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 7 of 106
CS-323092-DSP3
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CSRA64215 QFN Data Sheet
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
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Contacts . .................................................................................................................................................... 2
CSRA64215 Stereo ROM Solution with aptX Development Kit Ordering Information . .............................. 2
Pinout Diagram ......................................................................................................................................... 13
Device ≤erminal Functions ....................................................................................................................... 14
Package Dimensions ................................................................................................................................ 19
PCB Design and Assembly Considerations . ............................................................................................ 20
≤ypical Solder Reflow Profile . .................................................................................................................. 20
2.1
2.2
RF Ports (B≤_RF) ..................................................................................................................................... 21
RF Receiver . ............................................................................................................................................ 21
2.2.1
Low Noise Amplifier . ................................................................................................................... 21
2.2.2
RSSI Analogue to Digital Converter . .......................................................................................... 21
RF ≤ransmitter . ........................................................................................................................................ 21
2.3.1
IQ Modulator . .............................................................................................................................. 21
2.3.2
Power Amplifier ........................................................................................................................... 22
Bluetooth Radio Synthesiser . ................................................................................................................... 22
Baseband . ................................................................................................................................................ 22
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Crystal . ..................................................................................................................................................... 23
3.1.1
Negative Resistance Model . ....................................................................................................... 24
3.1.2
Crystal Specification . .................................................................................................................. 24
3.1.3
Crystal Calibration . ..................................................................................................................... 24
Non-crystal Oscillator . .............................................................................................................................. 25
3.2.1
X≤AL_IN Impedance in Non-crystal Mode .................................................................................. 26
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2.4
2.5
Bluetooth Stack Microcontroller ................................................................................................................ 27
Kalimba DSP . ........................................................................................................................................... 27
5.1
5.2
5.3
5.4
5.5
Memory Management ≥nit . ...................................................................................................................... 28
System RAM . ........................................................................................................................................... 28
Kalimba DSP RAM . .................................................................................................................................. 28
Internal ROM . ........................................................................................................................................... 28
Serial Quad I/O Flash Interface (SQIF) . .................................................................................................. 28
6.1
6.2
6.3
6.4
≥SB Interface . .......................................................................................................................................... 29
≥AR≤ Interface ......................................................................................................................................... 29
Programming and Debug Interface . ......................................................................................................... 31
6.3.1
Multi-slave Operation .................................................................................................................. 31
I²C Interface .............................................................................................................................................. 31
7.1
7.2
7.3
Programmable I/O Ports, PIO . ................................................................................................................. 32
Analogue I/O Ports, AIO .......................................................................................................................... 33
LED Drivers . ............................................................................................................................................. 33
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4.1
4.2
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
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CSRA64215 QFN Data Sheet
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1.1
1.2
1.3
1.4
1.5
Audio Input and Output . ........................................................................................................................... 34
Audio Codec Interface .............................................................................................................................. 35
8.2.1
Audio Codec Block Diagram ....................................................................................................... 35
8.2.2
ADC . ........................................................................................................................................... 35
8.2.3
ADC Sample Rate Selection ....................................................................................................... 35
8.2.4
ADC Audio Input Gain . ............................................................................................................... 36
8.2.5
ADC Pre-amplifier and ADC Analogue Gain . ............................................................................. 36
8.2.6
ADC Digital Gain ......................................................................................................................... 36
8.2.7
ADC Digital IIR Filter ................................................................................................................... 37
8.2.8
DAC . ........................................................................................................................................... 37
8.2.9
DAC Sample Rate Selection ....................................................................................................... 37
8.2.10 DAC Digital Gain ......................................................................................................................... 37
8.2.11 DAC Analogue Gain . .................................................................................................................. 37
8.2.12 DAC Digital FIR Filter . ................................................................................................................ 38
8.2.13 Microphone Input . ....................................................................................................................... 38
8.2.14 Line Input . ................................................................................................................................... 39
8.2.15 Output Stage ............................................................................................................................... 39
8.2.16 Mono Operation . ......................................................................................................................... 40
8.2.17 Side ≤one . .................................................................................................................................. 41
8.2.18 Integrated Digital IIR Filter . ......................................................................................................... 42
PCM1 and PCM2 Interface . ..................................................................................................................... 43
8.3.1
PCM Interface Master/Slave ....................................................................................................... 43
8.3.2
Long Frame Sync . ...................................................................................................................... 44
8.3.3
Short Frame Sync ....................................................................................................................... 45
8.3.4
Multi-slot Operation ..................................................................................................................... 45
8.3.5
GCI Interface . ............................................................................................................................. 46
8.3.6
Slots and Sample Formats . ........................................................................................................ 46
8.3.7
Additional Features ..................................................................................................................... 47
8.3.8
PCM ≤iming Information . ............................................................................................................ 47
8.3.9
PCM_CLK and PCM_SYNC Generation . ................................................................................... 51
8.3.10 PCM Configuration . .................................................................................................................... 51
I²S1 and I²S2 Interface . ............................................................................................................................ 51
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8.4
1.8 V Switch-mode Regulator ................................................................................................................... 59
1.35 V Switch-mode Regulator ................................................................................................................. 60
1.8 V and 1.35 V Switch-mode Regulators Combined . ............................................................................ 61
9.3.1
Inductor Choice ........................................................................................................................... 61
9.4 Bypass LDO Linear Regulator .................................................................................................................. 62
9.5 Low-voltage VDD_DIG Linear Regulator .................................................................................................. 62
9.6 Low-voltage VDD_A≥X Linear Regulator ................................................................................................. 63
9.7 Low-voltage VDD_ANA Linear Regulator ................................................................................................. 63
9.8 Voltage Regulator Enable . ....................................................................................................................... 63
9.9 External Regulators and Power Sequencing ............................................................................................ 63
9.10 Reset, RS≤# ............................................................................................................................................ 63
9.10.1 Digital Pin States on Reset . ........................................................................................................ 64
9.10.2 Status After Reset ....................................................................................................................... 64
9.11 Automatic Reset Protection ...................................................................................................................... 64
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9.1
9.2
9.3
10.1 Battery Charger Hardware Operating Modes ........................................................................................... 65
10.1.1 Disabled Mode ............................................................................................................................ 66
10.1.2 ≤rickle Charge Mode . ................................................................................................................. 66
10.1.3 Fast Charge Mode . ..................................................................................................................... 66
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 9 of 106
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CSRA64215 QFN Data Sheet
8.3
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8.1
8.2
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10.2
10.3
10.4
10.5
10.1.4 Standby Mode ............................................................................................................................. 66
10.1.5 Error Mode .................................................................................................................................. 66
Battery Charger ≤rimming and Calibration ............................................................................................... 66
VM Battery Charger Control . .................................................................................................................... 66
Battery Charger Firmware and PS Keys . ................................................................................................. 66
External Mode . ......................................................................................................................................... 67
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15.1 CSRA64215 Stereo ROM Solution with aptX ........................................................................................... 89
15.1.1 Advanced Multipoint Support ...................................................................................................... 90
15.1.2 A2DP Multipoint Support . ........................................................................................................... 90
15.1.3 Wired Audio Mode . ..................................................................................................................... 90
15.1.4 ≥SB Modes Including ≥SB Audio Mode ..................................................................................... 90
15.1.5 Smartphone Applications (Apps) . ............................................................................................... 91
15.1.6 Programmable Audio Prompts . .................................................................................................. 91
15.1.7 CSR s Intelligent Power Management . ....................................................................................... 91
15.1.8 Proximity Pairing ......................................................................................................................... 92
15.1.9 Proximity Connection .................................................................................................................. 92
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15.2 8th Generation 1-mic cVc ENR ≤echnology for Hands-free and Audio Enhancements . .......................... 92
15.2.1 Acoustic Echo Cancellation . ....................................................................................................... 93
15.2.2 Noise Suppression with Wind Noise Reduction . ........................................................................ 93
15.2.3 Non-linear Processing . ............................................................................................................... 93
15.2.4 Howling Control . ......................................................................................................................... 93
15.2.5 Comfort Noise Generator ............................................................................................................ 93
15.2.6 Equalisation . ............................................................................................................................... 94
15.2.7 Automatic Gain Control ............................................................................................................... 94
15.2.8 Packet Loss Concealment . ......................................................................................................... 94
15.2.9 Adaptive Equalisation . ................................................................................................................ 94
15.2.10 Auxiliary Stream Mix . .................................................................................................................. 95
15.2.11 Clipper . ....................................................................................................................................... 95
15.2.12 Noise Dependent Volume Control . ............................................................................................. 95
15.2.13 Input Output Gains ...................................................................................................................... 95
15.3 Music Enhancements . .............................................................................................................................. 95
15.3.1 Audio Decoders . ......................................................................................................................... 95
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 10 of 106
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CSRA64215 QFN Data Sheet
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12.1 Absolute Maximum Ratings ...................................................................................................................... 71
12.2 Recommended Operating Conditions . ..................................................................................................... 72
12.3 Input/Output ≤erminal Characteristics ...................................................................................................... 73
12.3.1 Regulators: Available For External ≥se ...................................................................................... 73
12.3.2 Regulators: For Internal ≥se Only . ............................................................................................. 75
12.3.3 Regulator Enable . ....................................................................................................................... 76
12.3.4 Battery Charger . ......................................................................................................................... 76
12.3.5 ≥SB . ........................................................................................................................................... 78
12.3.6 Stereo Codec: Analogue to Digital Converter ............................................................................. 79
12.3.7 Stereo Codec: Digital to Analogue Converter ............................................................................. 80
12.3.8 Digital .......................................................................................................................................... 81
12.3.9 LED Driver Pads . ........................................................................................................................ 81
12.3.10 Auxiliary ADC .............................................................................................................................. 82
12.3.11 Auxiliary DAC .............................................................................................................................. 82
12.4 ESD Protection ......................................................................................................................................... 83
15.3.2 aptX Decoder .............................................................................................................................. 95
15.3.3 Configurable EQ . ........................................................................................................................ 96
15.3.4 Stereo Widening (S3D) ............................................................................................................... 96
15.3.5 Volume Boost . ............................................................................................................................ 96
15.4 CSRA64215 Stereo ROM Solution with aptX Development Kit . .............................................................. 97
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Device Pinout ....................................................................................................................................... 13
Simplified Circuit B≤_RF . ..................................................................................................................... 21
Crystal Oscillator Overview .................................................................................................................. 23
Serial Quad I/O Flash Interface . .......................................................................................................... 28
≥niversal Asynchronous Receiver . ...................................................................................................... 30
LED Equivalent Circuit ......................................................................................................................... 33
Audio Interface ..................................................................................................................................... 34
Audio Codec Input and Output Stages . ............................................................................................... 35
Audio Input Gain . ................................................................................................................................. 36
Microphone Biasing . ............................................................................................................................ 38
Differential Input ................................................................................................................................... 39
Single-ended Input ............................................................................................................................... 39
Speaker Output .................................................................................................................................... 40
Side ≤one ............................................................................................................................................. 41
PCM Interface Master . ......................................................................................................................... 43
PCM Interface Slave . ........................................................................................................................... 44
Long Frame Sync (Shown with 8-bit Companded Sample) . ................................................................ 44
Short Frame Sync (Shown with 16-bit Sample) ................................................................................... 45
Multi-slot Operation with 2 Slots and 8-bit Companded Samples ........................................................ 45
GCI Interface . ...................................................................................................................................... 46
16-bit Slot Length and Sample Formats . ............................................................................................. 47
PCM Master ≤iming Long Frame Sync ................................................................................................ 48
PCM Master ≤iming Short Frame Sync . .............................................................................................. 49
PCM Slave ≤iming Long Frame Sync .................................................................................................. 50
PCM Slave ≤iming Short Frame Sync . ................................................................................................ 51
Digital Audio Interface Modes . ............................................................................................................. 53
Digital Audio Interface Slave ≤iming . ................................................................................................... 54
Digital Audio Interface Master ≤iming .................................................................................................. 55
1.80 V and 1.35 V Dual-supply Switch-mode System Configuration ................................................... 57
1.80 V Parallel-supply Switch-mode System Configuration ................................................................. 58
1.8 V Switch-mode Regulator Output Configuration ............................................................................ 59
1.35 V Switch-mode Regulator Output Configuration .......................................................................... 60
1.8 V and 1.35 V Switch-mode Regulators Outputs Parallel Configuration ......................................... 61
Battery Charger Mode-to-Mode ≤ransition Diagram ............................................................................ 65
Battery Charger External Mode ≤ypical Configuration . ....................................................................... 67
Example Application Schematic . ......................................................................................................... 68
Single 1.8 V-only Supply, with no ≥SB or SMPSs ............................................................................... 69
sp
bt
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CSRA64215 QFN Data Sheet
Figure 1.1
Figure 2.1
Figure 3.1
Figure 5.1
Figure 6.1
Figure 7.1
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Figure 8.12
Figure 8.13
Figure 8.14
Figure 8.15
Figure 8.16
Figure 8.17
Figure 8.18
Figure 8.19
Figure 8.20
Figure 8.21
Figure 8.22
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 10.1
Figure 10.2
Figure 11.1
Figure 11.2
m
≤ape Orientation ....................................................................................................................................... 98
≤ape Dimensions . .................................................................................................................................... 99
Reel Information . .................................................................................................................................... 100
Moisture Sensitivity Level ....................................................................................................................... 100
ea
16.1
16.2
16.3
16.4
Single 3.3 V-only Supply, with ≥SB and Dual SMPSs . ....................................................................... 70
Programmable Audio Prompts in External SPI Flash . ......................................................................... 91
1-mic cVc Hands-free Block Diagram .................................................................................................. 93
Configurable EQ G≥I with Drag Points ................................................................................................ 96
Volume Boost G≥I with Drag Points .................................................................................................... 97
CSRA64215 QFN ≤ape Orientation . ................................................................................................... 98
Reel Dimensions ................................................................................................................................ 100
≤able 3.1
≤able 3.2
≤able 3.3
≤able 3.4
≤able 6.1
≤able 6.2
≤able 6.3
≤able 7.1
≤able 8.1
≤able 8.2
≤able 8.3
≤able 8.4
≤able 8.5
≤able 8.6
≤able 8.7
≤able 8.8
≤able 8.9
≤able 8.10
≤able 8.11
≤able 8.12
≤able 9.1
≤able 9.2
≤able 9.3
≤able 10.1
≤able 12.1
≤ypical On-chip Capacitance Values . ................................................................................................... 23
≤ransconductance and On-chip Parasitic Capacitance ........................................................................ 24
Crystal Specification . ............................................................................................................................ 24
External Clock Specifications ................................................................................................................ 26
PS Keys for ≥AR≤/PIO Multiplexing . .................................................................................................... 29
Possible ≥AR≤ Settings ........................................................................................................................ 30
Standard Baud Rates ............................................................................................................................ 30
Alternative PIO Functions . .................................................................................................................... 32
Alternative Functions of the Digital Audio Bus Interface on the PCM1 and PCM2 Interface ................ 34
ADC Audio Input Gain Rate . ................................................................................................................. 36
DAC Digital Gain Rate Selection . ......................................................................................................... 37
DAC Analogue Gain Rate Selection . .................................................................................................... 38
Side ≤one Gain . .................................................................................................................................... 41
PCM Master ≤iming . ............................................................................................................................. 47
PCM Slave ≤iming . ............................................................................................................................... 50
Alternative Functions of the Digital Audio Bus Interface on the PCM Interface .................................... 52
Digital Audio Interface Slave ≤iming . .................................................................................................... 53
I²S Slave Mode ≤iming .......................................................................................................................... 54
Digital Audio Interface Master ≤iming . .................................................................................................. 55
I²S Master Mode ≤iming Parameters, WS and SCK as Outputs . ......................................................... 55
Recommended Configurations for Power Control and Regulation . ...................................................... 56
Inductor Choice, CSR's ≤esting and Characterisation .......................................................................... 62
Pin States on Reset . ............................................................................................................................. 64
Battery Charger Operating Modes Determined by Battery Voltage and Current . ................................. 65
ESD Handling Ratings . ......................................................................................................................... 83
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ea
sp
bt
Equation 3.1
Equation 3.2
Equation 7.1
Equation 7.2
Equation 8.1
Equation 8.2
Negative Resistance . ........................................................................................................................... 24
Crystal Calibration ≥sing PSKEY_ANA_F≤RIM_OFFSE≤ . ................................................................. 25
LED Current . ........................................................................................................................................ 33
LED PAD Voltage . ............................................................................................................................... 33
IIR Filter ≤ransfer Function, H(z) . ........................................................................................................ 42
IIR Filter Plus DC Blocking ≤ransfer Function, HDC(z) ......................................................................... 43
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CSRA64215 QFN Data Sheet
r.
co
m
Figure 11.3
Figure 15.1
Figure 15.2
Figure 15.3
Figure 15.4
Figure 16.1
Figure 16.2
Orientation from Top of Device
m
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
co
51
2
3
4
6
7
ke
8
9
10
ea
11
12
13
14
sp
15
49
48
47
46
45
44
43
42
41
40
39
38
37
17
35
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G-TW-0012207.2.2
36
bt
16
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
CSRA64215 QFN Data Sheet
r.
5
50
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12
RF
VDD_B≤_RADIO
Bluetooth 50 transmitter output /
receiver input
X≤AL_IN
19
Analogue
VDD_A≥X
For crystal or external clock input
X≤AL_O≥≤
18
Analogue
VDD_A≥X
Drive for crystal
≥SB_DP
56
Bidirectional
VDD_≥SB
≥SB_DN
55
Bidirectional
VDD_≥SB
SPI_PCM#
29
Input with weak pulldown
co
m
B≤_RF
r.
ke
VDD_PADS_1
≥SB data minus
SPI/PCM select input:
0 = PCM/PIO interface
1 = SPI
Debug SPI and PCM1 interfaces are mapped as alternative functions on the PIO port.
25
Bidirectional with strong
pull-down
VDD_PADS_1
SPI flash clock
sp
QSPI_FLASH_CLK
22
Bidirectional with strong
pull-up
VDD_PADS_1
SPI flash chip select
QSPI_IO[3]
21
Bidirectional with strong
pull-up
VDD_PADS_1
SPI flash data bit 3
QSPI_IO[2]
23
Bidirectional with strong
pull-up
VDD_PADS_1
SPI flash data bit 2
QSPI_IO[1]
31
Bidirectional with strong
pull-down
VDD_PADS_1
SPI flash data bit 1
QSPI_IO[0]
26
Bidirectional with strong
pull-down
VDD_PADS_1
SPI flash data bit 0
bt
QSPI_FLASH_CS#
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CSRA64215 QFN Data Sheet
ea
≥SB data plus with selectable internal
1.5 k pull-up resistor
64
Bidirectional with weak
pull-down
VDD_PADS_2
Programmable input / output line 21.
PIO[18]
65
Bidirectional with weak
pull-down
VDD_PADS_2
Programmable input / output line 18.
32
Bidirectional with strong
pull-down
VDD_PADS_1
Programmable input / output line 17.
Alternative function:
≥AR≤_C≤S: ≥AR≤ clear to send,
active low
27
Bidirectional with strong
pull-up
Bidirectional with strong
pull-down
VDD_PADS_2
ke
58
Bidirectional with strong
pull-up
ea
61
sp
PIO[8]
bt
PIO[7]
PIO[6]
PIO[5]
57
62
34
Bidirectional with strong
pull-down
Bidirectional with strong
pull-down
Bidirectional with weak
pull-down
Programmable input / output line 9.
Alternative function:
≥AR≤_C≤S: ≥AR≤ clear to send,
active low
PCM2_CLK: PCM2 synchronous
data clock
I2S2_SCK: I²S2 synchronous data
clock
VDD_PADS_2
Programmable input / output line 8.
Alternative function:
≥AR≤_R≤S: ≥AR≤ request to send,
active low
PCM2_IN: PCM2 synchronous data
input
I2S2_SD_IN: I²S2 synchronous data
input
VDD_PADS_2
Programmable input / output line 7.
Alternative function:
PCM2_SYNC: PCM2 synchronous
data sync
I2S2_WS: I²S2 word select
VDD_PADS_2
Programmable input / output line 6.
Alternative function:
PCM2_O≥≤: PCM2 synchronous
data output
I2S2_SD_O≥≤: I²S2 synchronous
data output
VDD_PADS_1
Programmable input / output line 5.
Alternative function:
SPI_CLK: Debug SPI clock
PCM1_CLK: PCM1 synchronous
data clock
I2S1_SCK: I²S1 synchronous data
clock
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CSRA64215 QFN Data Sheet
PIO[9]
VDD_PADS_1
co
PIO[16]
Programmable input / output line 16.
Alternative function:
≥AR≤_R≤S: ≥AR≤ request to send,
active low
r.
PIO[17]
m
PIO[21]
24
Bidirectional with weak
pull-down
VDD_PADS_1
VDD_PADS_1
Programmable input / output line 3.
Alternative function:
SPI_MISO: Debug SPI data output
PCM1_O≥≤: PCM1 synchronous
data output
I2S1_SD_O≥≤: I²S1 synchronous
data output
Bidirectional with strong
pull-up
59
Bidirectional with strong
pull-up
sp
PIO[0]
60
VDD_PADS_1
VDD_PADS_2
Programmable input / output line 1.
Alternative function:
≥AR≤_≤X: ≥AR≤ data output
AMP_I2C_SDA: I²C serial data line
for external amplifier control
VDD_PADS_2
Programmable input / output line 0.
Alternative function:
≥AR≤_RX: ≥AR≤ data input
AMP_I2C_SCL: I²C serial clock line
for external amplifier control
VDD_A≥X
Analogue programmable input / output
line 0.
20
Bidirectional
RS≤#
35
Input with strong pull-up VDD_PADS_1
Reset if low. Pull low for minimum 5 ms to
cause a reset.
MIC_BIAS
2
Analogue in
VDD_A≥DIO
Microphone bias
A≥_REF
1
Analogue in
VDD_A≥DIO
Decoupling of audio reference (for highquality audio)
SPKR_RN
6
Analogue out
VDD_A≥DIO_DRV
Speaker output negative, right
SPKR_RP
7
Analogue out
VDD_A≥DIO_DRV
Speaker output positive, right
bt
AIO[0]
Programmable input / output line 2.
Alternative function:
SPI_MOSI: Debug SPI data input
PCM1_IN: PCM1 synchronous data
input
I2S1_SD_IN: I²S1 synchronous data
input
SPDIF_IN: SPDIF input
r.
Bidirectional with weak
pull-down
ke
PIO[1]
30
Bidirectional with weak
pull-down
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CSRA64215 QFN Data Sheet
PIO[2]
28
ea
PIO[3]
co
m
PIO[4]
Programmable input / output line 4.
Alternative function:
SPI_CS#: chip select for Debug
SPI, active low
PCM1_SYNC: PCM1 synchronous
data sync
I2S1_WS: I²S1 word select
9
Analogue out
VDD_A≥DIO_DRV
Speaker output negative, left
SPKR_LP
10
Analogue out
VDD_A≥DIO_DRV
Speaker output positive, left
LINE/MIC_AN
67
Analogue in
VDD_A≥DIO
Line or microphone input negative,
channel A
LINE/MIC_AP
68
Analogue in
VDD_A≥DIO
Line or microphone input positive,
channel A
LINE_BN
4
Analogue in
VDD_A≥DIO
Line input negative, channel B
LINE_BP
5
Analogue in
VDD_A≥DIO
LED[2]
66
Bidirectional
VDD_PADS_2
LED[1]
36
Bidirectional
VDD_PADS_1
LED driver.
LED[0]
37
Bidirectional
VDD_PADS_1
LED driver.
co
LED driver.
r.
ke
ea
LX_1V35
43
Line input positive, channel B
External battery charger control.
External battery charger transistor base control when using external
charger boost. Otherwise leave unconnected.
50
1.35 V switch-mode power regulator inductor connection.
47
1.8 V switch-mode power regulator inductor connection.
52
1.35 V switch-mode power regulator sense input.
SMPS_1V8_SENSE
53
1.8 V switch-mode power regulator sense input.
SMP_BYP
49
Supply via bypass regulator for 1.8 V and 1.35 V switch-mode power
supply regulator inputs. Must be connected to the same potential as
VO≥≤_3V3.
SMP_VBA≤
48
1.8 V and 1.35 V switch-mode power supply regulator inputs.
Must be at the same potential as VBA≤.
VSS_SMPS_1V35
51
1.35 V switch-mode regulator ground.
VSS_SMPS_1V8
46
1.8 V switch-mode regulator ground.
VBA≤
45
Battery positive terminal.
VBA≤_SENSE
44
Battery charger sense input, connect as Section 11 shows.
VCHG
42
Charger input.
≤ypically connected to VB≥S (≥SB supply) as Section 11 shows.
VDD_ANA
17
Analogue LDO linear regulator output (1.35 V).
Connect to 1.35 V supply, see Section 11 for connections.
LX_1V8
bt
sp
SMPS_1V35_SENSE
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CSRA64215 QFN Data Sheet
CHG_EX≤
m
SPKR_LN
3
Positive supply for audio.
Connect to 1.35 V supply, see Section 11 for connections.
VDD_A≥DIO_DRV
8
Positive supply for audio output amplifiers.
Connect to 1.8 V supply, see Section 11 for connections.
VDD_A≥X
14
Auxiliary supply.
Connect to 1.35 V supply, see Section 11 for connections.
15, 16
Auxiliary LDO regulator input.
Connect to 1.8 V supply, see Section 11 for connections.
VDD_B≤_LO
13
Bluetooth radio local oscillator supply (1.35 V).
Connect to 1.35 V supply, see Section 11 for connections.
VDD_B≤_RADIO
11
Bluetooth radio supply.
Connect to 1.35 V supply, see Section 11 for connections.
VDD_DIG
38
Digital LDO regulator output, see Section 11 for connections.
VDD_PADS_1
33
Positive supply input for input/output ports.
VDD_PADS_2
63
Positive supply input for input/output ports.
VDD_≥SB
54
Positive supply for ≥SB port.
VO≥≤_3V3
41
3.3 V bypass linear regulator output.
Connect external minimum 2.2 µF ceramic decoupling capacitor.
40
Regulator enable input.
Can also be sensed as an input.
Regulator enable and multifunction button. A high input (tolerant to
VBA≤) enables the on-chip regulators, which can then be latched on
internally and the button used as a multifunction input.
39
Digital LDO regulator input, see Section 11 for connections.
≤ypically connected to a 1.35 V supply.
Exposed pad
co
r.
Ground connections.
bt
VSS
ea
sp
VREGIN_DIG
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CSRA64215 QFN Data Sheet
VREGENABLE
ke
VDD_A≥X_1V8
m
VDD_A≥DIO
m
D
A
ccc C
A
A2
aaa C A
A
A3
A1
0.10
A1
ea
Seating
Plane
Side View
eee C A B
D2
1.30
18
34
35
sp
17
0.90
E
7.90
8.00
8.10
0.00
0.035
0.05
E2
4.50
4.60
4.70
L
0.35
0.40
0.45
A2
-
0.65
0.67
A3
-
0.203
-
aaa
-
0.10
-
b
0.15
0.20
0.25
bbb
-
0.10
-
D
7.90
8.00
8.10
ccc
-
0.08
-
D2
4.50
4.60
4.70
ddd
-
0.10
-
-
0.40
-
eee
-
0.10
-
ke
B
Bottom View
0.85
e
1.
2.
3.
4.
Dimensions and tolerances conform to ASME Y14.5M. - 1994
Pin 1 identifier is placed on top surface of the package by using
identification mark or other feature of package body.
Exact shape and size of this feature is optional.
Package warpage 0.08 mm maximum.
0.30
0.30
eee C A B
51
L
68
Pin 1 ID
1.30
bt
1
b
52
e
L
ddd M C A B
Production Information
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G-TW-0012054.3.2
E2
68-lead Quad-Flat No-lead (QFN) package
8 x 8 x 0.9 mm
MO-220
0.4 mm pitch
mm
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CSRA64215 QFN Data Sheet
E
Laser Mark for Pin 1
Identification in This Area
0.80
r.
aaa C B
co
bbb C
Top View
1.4
PCB Design and Asse
≤his section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 0.9 mm QFN 68-lead
package:
co
m
NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of
the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap
of the solder mask on the land creates a step in the solder at the land interface, which can cause stress
concentration and act as a point for crack initiation.
CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351.
Solder paste must be used during the assembly process.
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
For information, see ≤ypical Solder Reflow Profile for Lead-free Devices Information Note .
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m
≤he Bluetooth modem includes:
RF ports
RF receiver
RF transmitter
Bluetooth radio synthesiser
Baseband
VDD
_
co
CSRA64215 QFN contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces
the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode
impedance is 50 and the transmitter has been optimised to deliver power into a 50 load.
BT_RF
G-TW-0012203.1.2
VSS
ea
+
ke
PA
+
LNA
_
RF Receiver
sp
2.2
bt
≤he receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to GSM and
W CDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that no
discriminator tank is needed and its excellent performance in the presence of noise enables CSRA64215 QFN to exceed
the Bluetooth requirements for co channel and adjacent channel rejection.
≤he LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.
≤he ADC implements fast AGC. ≤he ADC samples the RSSI voltage on a slot-by-slot basis. ≤he front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. ≤his
improves the dynamic range of the receiver, improving performance in interference-limited environments.
2.3
RF ≤ransmitter
≤he transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a
controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
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CSRA64215 QFN Data Sheet
r.
On-chip Balun
≤he internal PA output power is software controlled and configured through a PS Key. ≤he internal PA on the
CSRA64215 QFN has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3
Bluetooth radio without requiring an external RF PA.
co
m
≤he Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can,
varactor tuning diodes, LC resonators or loop filter. ≤he synthesiser is guaranteed to lock in sufficient time across the
guaranteed temperature range to meet the Bluetooth v4.2 specification.
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
≤he baseband handles the digital functions of the Bluetooth modem, for example the Burst Mode Controller and Physical
Layer Hardware Engine.
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CSRA64215 QFN accepts a reference clock input from either a crystal or an external clock source, e.g. a ≤CXO.
m
≤he external reference clock is required in active and deep sleep modes and must be present when CSRA64215 QFN
is enabled.
gm
On-chip Capacitance Control
r.
XTAL_OUT
G-TW-0011478.2.2
ke
ea
XTAL_IN
External Crystal
bt
sp
≤he on-chip capacitance is adjusted using PSKEY_X≤AL_OSC_CONFIG, see ≤able 3.1. ≤he default values suit a
typical crystal requiring a 9 pF load capacitance. In deep sleep mode, the crystal oscillation is maintained, but at a lower
drive strength to reduce power consumption. ≤he drive strength and load capacitance are configured with a PS Key.
Value
00
01
10
11
00
01
10
11
X≤AL_IN
(≤ypical)
15.6 pF
10.8 pF
6.0 pF
1.1 pF
15.6 pF
10.8 pF
6.0 pF
1.1 pF
X≤AL_O≥≤
(≤ypical)
20.8 pF
16.0 pF
11.2 pF
6.4 pF
16.0 pF
11.2 pF
6.4 pF
1.5 pF
≤he drive strength is configured with PSKEY_X≤AL_LVL. ≤he default level for this PS Key is sufficient for typical
crystals. ≤he level control is set in the range 0 to 15, where 15 is the maximum drive level.
Increasing the crystal amplifier drive level increases the transconductance of the crystal amplifier, which creates an
increase in the oscillator margin (ratio of oscillator amplifiers is equivalent to the negative resistance of the crystal
ESR).
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CSRA64215 QFN Data Sheet
Amplifier gm
Control LVL[3:0]
co
Figure 3.1 shows the CSRA64215 QFN contains a crystal driver circuit that acts as a transconductance amplifier that
drives an external crystal connected between X≤AL_IN and X≤AL_O≥≤. ≤he crystal driver circuit forms a Pierce
oscillator with the external crystal. External capacitors are not required for standard crystals that require a load
capacitance of around 9pF. CSR recommends this option.
m
Excessive amplifier transconductance can lead to an increase in the oscillator phase noise if the oscillator amplifier
is excessively overdriven. Set the transconductance to the minimum level to give the desired oscillation ratio. Higher
values can increase power consumption. Also, insufficient drive strength can prevent the the crystal from starting
to oscillate.
Rneg=
gmCinCout
co
≤he crystal and its load capacitor can be modelled as a frequency dependant resistive element. Consider the driver
amplifier as a circuit that provides negative resistance. For oscillation, the value of the negative resistance should be
greater than that of the crystal circuit equivalence resistance. Equation 3.1 shows how to calculate the equivalent
negative resistance.
2 f2(CoutCin+(C0+Cint)(Cout+Cin))2
Where:
r.
ke
2
-
-
mS
-
1.5
-
pF
16
26
32
MHz
Initial Frequency error from nominal frequency
which can be compensated for
-
-
±285
ppm
Frequency Stability
-
-
±20
ppm
Crystal ESR
-
-
60
ea
≤ransconductance
Cint
sp
≤able 3.3 shows the specification for an external crystal.
bt
Frequency
≤he actual crystal frequency depends on the capacitance of X≤AL_IN and X≤AL_O≥≤ on the PCB and the
CSRA64215 QFN, as well as the capacitance of the crystal.
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CSRA64215 QFN Data Sheet
gm = ≤ransconductance of the crystal oscillator amplifier
Co = Static capacitance of the crystal, which is sometimes referred to as the shunt or case capacitance
Cint = On-chip parasitic capacitance between input and output of X≤AL amplifier.
Cin = Internal capacitance on X≤AL_IN, see ≤able 3.1
Cout = Internal capacitance on X≤AL_O≥≤, see ≤able 3.1
≤he Bluetooth specification requires ±20 ppm clock accuracy. ≤he actual frequency at which a crystal oscillates contains
two error terms, which are typically mentioned in the crystal device datasheets:
Initial Frequency Error: ≤he difference between the desired frequency and the actual oscillating frequency
caused by the crystal itself and its PCB connections. It is also called as Calibration ≤olerance or Frequency
≤olerance.
Frequency Stability: ≤he total of how far the crystal can move off frequency with temperature, aging or other
effects. It is also called as ≤emperature Stability, Frequency Stability or Aging.
m
CSRA64215 QFN has the capability to compensate for Initial Frequency errors by a simple per-device basis on the
production line, with the trim value stored in the non-volatile memory (PS Key). However, it is not possible to compensate
for frequency stability, therefore a crystal must be chosen with a Frequency Stability that is better than ±20 ppm clock
accuracy.
co
Some crystal datasheets combine both these terms into one tolerance value. ≤his causes a problem because only the
initial frequency error can be compensated for and CSRA64215 QFN cannot compensate for the temperature or aging
performance. If frequency stability is not explicity stated, CSR cannot guarantee remaining within the Bluetooth's
±20 ppm frequency accuracy specification.
r.
ke
≤he value in PSKEY_ANA_F≤RIM_OFFSE≤ is a 16-bit 2's complement signed integer which specifies the fractional
part of the ratio between the true crystal frequency, factual, and the value set in PSKEY_ANA_FREQ, fnominal. Equation
3.2 shows the value of PSKEY_ANA_F≤RIM_OFFSE≤ in parts per 220 rounded to the nearest integer.
PSKEY_ANA_F≤RIM_OFFSE≤ = (
factual
fnominal
1) × 220
3.2
ea
For more information on ≤XS≤AR≤ radio test see Blue≤est ≥ser Guide.
Non-crystal Oscillator
Apply the external reference clock to the CSRA64215 QFN X≤AL_IN input. Connect X≤AL_O≥≤ to ground.
bt
sp
≤he external clock is either a low-level sinusoid, or a digital-level square wave. ≤he clock must meet the specification
in ≤able 3.4. ≤he external reference clock is required in active and deep sleep modes, it must be present when
CSRA64215 QFN is enabled.
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CSRA64215 QFN Data Sheet
Crystal calibration uses a single measurement of RF output frequency and can be performed quickly as part of the
product final test. ≤ypically, a ≤XS≤AR≤ radio command is sent and then a measurement of the output RF frequency
is read. From this, the calibration factor to correct actual offset from the desired frequency can be calculated. ≤his offset
value is stored in PSKEY_ANA_F≤RIM_OFFSE≤. CSRA64215 QFN then compensates for the initial frequency offset
of the crystal.
19.2
26
40
MHz
Duty cycle
40:60
50:50
60:40
-
-
-
10
ps
rms(b)
0.2
0.4
VDD_A≥X(c)
V
Signal level
DC coupled digital
extremes
0
DC coupled digital
digital amplitude
0.4
X≤AL_IN input capacitance
-
VDD_A≥X(c)
V
-
1.2
V pk-pk
-
-
k
-
1
pF
ke
30
-
≤he frequency should be an integer multiple of 250 kHz except for the CDMA/3G frequencies
(b)
100 Hz to 1 MHz
(c)
VDD_A≥X is 1.35 V nominal
ea
(a)
bt
sp
≤he impedance of X≤AL_IN does not change significantly between operating modes. When transitioning from deep
sleep to active states, the capacitive load can change. For this reason, CSR recommends using a buffered clock input.
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CSRA64215 QFN Data Sheet
X≤AL_IN input impedance
co
AC coupled sinusoid
amplitude
r.
Edge jitter (at zero crossing)
m
Frequency(a)
≤he CSRA64215 QFN uses a 16-bit RISC 80 MHz MC≥ for low power consumption and efficient use of memory. It
contains a single-cycle multiplier and a memory protection unit.
m
≤he MC≥, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host
interfaces.
ke
ea
sp
bt
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CSRA64215 QFN Data Sheet
r.
co
≤he Kalimba DSP performs signal processing functions on over air data or codec data to enhance audio applications.
≤he key features of the DSP include:
80 MIPS performance, 24 bit fixed point DSP core
Single cycle MAC; 24 x 24 bit multiply and 56 bit accumulate includes 2 rMAC registers and new instructions
for improved performance over previous architecture
32 bit instruction word
Separate program memory and dual data memory, enabling an AL≥ operation and up to 2 memory accesses
in a single cycle
Zero overhead looping, including a very low power 32 instruction cache
Zero overhead circular buffer indexing
Single cycle barrel shifter with up to 56 bit input and 56 bit output
Multiple cycle divide (performed in the background)
Bit reversed addressing
Orthogonal instruction set
Low overhead interrupt
5.1
Memory Management ≥nit
m
≤he MM≥ provides buffers that hold the data in transit between the host, the air or the Kalimba DSP. ≤he use of
DMA ports also helps with efficient transfer of data to other peripherals.
co
56 KB of integrated RAM supports the RISC MC≥.
Internal ROM is provided for system firmware implementation.
Serial Quad I/O Flash Interface (SQIF)
ke
5.5
≤he CSRA64215 QFN uses external serial flash ICs for storage of device specific data. ≤he CSRA64215 QFN supports
a 4-bit I/O flash-memory interface. Figure 5.1 shows a typical connection between the CSRA64215 QFN and a serial
flash IC.
MCU
QSPI_FLASH_CLK
QSPI_FLASH_CS#
Memory
Management
Unit
sp
Kalimba DSP Program
Kalimba DSP
QSPI_IO[0]
QSPI_IO[1]
QSPI_IO[2]
QSPI_IO[3]
CLK
CS#
DI/IO0
DO/IO1
WP#/IO2
RESET#/HOLD#/IO3
bt
Kalimba DSP Data
SQIF
MCU Data
Serial Quad
I/O Flash
G-TW-0014410.2.2
ea
MCU Program
≤he SQIF interface on the CSRA64215 QFN requires use of a suitable Quad SPI Flash chip of minimum size 4 Mb,
connected as Figure 5.1 shows. For a list of supported Quad SPI Flash devices, see the CSRA64xxx A11 Firmware
Release Note.
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CSRA64215 QFN Data Sheet
r.
Additional integrated RAM provides support for the Kalimba DSP:
16K x 24-bit for data memory 1 (DM1)
16K x 24-bit for data memory 2 (DM2)
6K x 32-bit for program memory (PM)
6.1
≥SB Interface
CSRA64215 QFN has a full-speed (12 Mbps) ≥SB interface for communicating with other compatible digital devices.
≤he ≥SB interface on CSRA64215 QFN acts as a ≥SB peripheral, responding to requests from a master host controller.
m
CSRA64215 QFN contains internal ≥SB termination resistors and requires no external resistor matching.
co
CSRA64215 QFN supports the ≥niversal Serial Bus Specification, Revision v2.0 (≥SB v2.0 Specification), supports
≥SB standard charger detection and fully supports the ≥SB Battery Charging Specification, available from http://
www.usb.org. For more information on how to integrate the ≥SB interface on CSRA64215 QFN, see the Bluetooth and
≥SB Design Considerations Application Note.
r.
ke
ea
bt
sp
CSRA64215 QFN has an optional ≥AR≤ serial interface that provides a simple mechanism for communicating with
other serial devices using the RS232 protocol, including for test and debug. ≤he ≥AR≤ interface is multiplexed with
PIOs and other functions, and hardware flow control is optional. ≤able 6.1 shows the PS Keys for configuring this
multiplexing.
PSKEY_≥AR≤_RX_PIO
PIO[0]
PSKEY_≥AR≤_≤X_PIO
PIO[1]
PSKEY_≥AR≤_R≤S_PIO
PIO[8] (default) or PIO[16]
PSKEY_≥AR≤_C≤S_PIO
PIO[9] (default) or PIO[17]
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CSRA64215 QFN Data Sheet
As well as describing ≥SB basics and architecture, the application note describes:
Power distribution for high and low bus-powered configurations
Power distribution for self-powered configuration, which includes ≥SB VB≥S monitoring
≥SB enumeration
Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite
beads
≥SB suspend modes and Bluetooth low-power modes:
Global suspend
Selective suspend, includes remote wake
Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
Suspend mode current draw
PIO status in suspend mode
Resume, detach and wake PIOs
Battery charging from ≥SB, which describes dead battery provision, charge currents, charging in suspend
modes and ≥SB VB≥S voltage consideration
≥SB termination when interface is not in use
Internal modules, certification and non-specification compliant operation
UART_TX
PIO[0]
UART_RX
PIO[8] or PIO[16]
UART_RTS
PIO[9] or PIO[17]
UART_CTS
co
m
PIO[1]
G-TW-0014619.1.2
Figure 6.1 shows the 4 signals that implement the ≥AR≤ function.
r.
ke
≥AR≤ configuration parameters, such as baud rate and packet format, are set using CSRA64215 QFN firmware.
≤o communicate with the ≥AR≤ at its maximum data rate using a standard PC, the PC requires an accelerated
serial port adapter card.
ea
≤able 6.2 shows the possible ≥AR≤ settings.
1200 baud ( 2%Error)
Minimum
Baud rate
9600 baud ( 1%Error)
Maximum
R≤S/C≤S or None
sp
Flow control
4 Mbaud ( 1%Error)
Parity
None, Odd or Even
Number of stop bits
1 or 2
8
bt
Bits per byte
≤able 6.3 lists common baud rates and their associated error values for PSKEY_≥AR≤_BI≤RA≤E. ≤o set the ≥AR≤
baud rate, load PSKEY_≥AR≤_BI≤RA≤E with the number of bits per second.
1200
1200
1.73%
2400
2400
1.73%
4800
4800
1.73%
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CSRA64215 QFN Data Sheet
When CSRA64215 QFN is connected to another digital device, ≥AR≤_RX and ≥AR≤_≤X transfer data between the 2
devices. ≤he remaining 2 signals, ≥AR≤_C≤S and ≥AR≤_R≤S, implement optional RS232 hardware flow control where
both are active low indicators.
9600
-0.82%
19200
19200
0.45%
38400
38400
-0.18%
57600
57600
76800
76800
115200
115200
230400
230400
460800
460800
921600
921600
1382400
1382400
-0.01%
1843200
1843200
0.00%
2764800
0.00%
3686400
0.00%
m
9600
0.03%
ke
2764800
0.03%
-0.02%
0.00%
ea
3686400
0.03%
sp
CSRA64215 QFN provides a debug SPI interface for programming, configuring (PS Keys) and debugging the
CSRA64215 QFN. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI_PCM# line
are brought out to either test points or a header. ≤o use the SPI interface, the SPI_PCM# line requires the option of
being pulled high externally.
CSR provides development and production tools to communicate over the SPI from a PC, although a level translator
circuit is often required. All are available from CSR.
bt
Avoid connecting CSRA64215 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines.
When CSRA64215 QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSRA64215 QFN
outputs 0 if the processor is running or 1 if it is stopped.
≤he CSRA64215 QFN supports an I²C interface for I/O port expansion. Its primary function is to control an external
audio power amplifier. ≤he default assignment of the I²C interface onto the PIOs on the CSRA64215 QFN is:
PIO[0] is the I²C interface SCL line (AMP_I2C_SCL)
PIO[1] is the I²C interface SDA line (AMP_I2C_SDA)
Alternatively, the I²C interface can be assigned to two PIOs from PIO[9:0] using PSKEY_I2C_SCL_PIO and
PSKEY_I2C_SDA_PIO.
≤he I²C interface requires external pull-up resistors. Ensure that external pull-up resistors are suitably sized for the
I²C interface speed and PCB track capacitance.
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CSRA64215 QFN Data Sheet
r.
co
0.14%
Function
≥AR≤_RX
AMP_I2C_SCL
(default)
PIO[1]
-
-
≥AR≤_≤X
AMP_I2C_SDA
(default)
PIO[2]
SPI_MOSI
-
-
Alternate I²C
function
PIO[3]
SPI_MISO
-
-
Alternate I²C
function
PIO[4]
SPI_CS#
-
-
PIO[5]
SPI_CLK
-
-
PIO[6]
-
-
-
PIO[7]
-
-
PIO[8]
-
-
-
-
-
-
-
PCM1_IN
I2S1_SD_IN
SPDIF_IN
ke
PCM1_O≥≤
I2S1_SD_O≥≤ -
Alternate I²C
function
PCM1_SYNC
I2S1_WS
-
Alternate I²C
function
PCM1_CLK
I2S1_SCK
-
Alternate I²C
function
PCM2_O≥≤
I2S2_SD_O≥≤ -
-
Alternate I²C
function
PCM2_SYNC
I2S2_WS
-
≥AR≤_R≤S
Alternate I²C
function
PCM2_IN
I2S2_SD_IN
-
ea
sp
-
co
-
r.
-
-
-
≥AR≤_C≤S
Alternate I²C
function
PCM2_CLK
I2S2_SCK
-
PIO[16]
-
-
≥AR≤_R≤S
-
-
-
-
PIO[17]
-
-
≥AR≤_C≤S
-
-
-
-
PIO[18]
-
-
-
-
-
-
-
PIO[21]
-
-
-
-
-
-
-
bt
PIO[9]
See the relevant software release note for the implementation of these PIO lines, as they are firmware buildspecific.
≤o change the default assignment shown for some alternative functions, use PS Keys. For ≥AR≤, see Section
6.2. For I²C, see Section 6.4.
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CSRA64215 QFN Data Sheet
PIO[0]
m
CSRA64215 QFN provides up to 14 lines of programmable bidirectional I/O, PIO[21,18:16,9:0]. ≤able 7.1 lists the
PIOs on the CSRA64215 QFN that have alternative functions.
CSRA64215 QFN has 1 general-purpose analogue interface pin, AIO[0]. ≤ypically, this connects to a thermistor for
battery pack temperature measurements during charge control. See Section 11 for typical connections.
m
≤he CSRA64215 QFN includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide
range of colours. All LEDs are controlled by firmware.
co
≤he terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current-limiting resistor.
LED Supply
RLED
ke
LED[2, 1 or 0]
ea
Pad Voltage, VPAD;
RON = 20
G-TW-0005534.4.2
Resistor Voltage Drop, VR
sp
From Figure 7.1 it is possible to derive Equation 7.1 to calculate ILED. If a known value of current is required through
the LED to give a specific luminous intensity, then the value of RLED is calculated.
ILED =
VDD
R
LED
V
+R
F
ON
bt
For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across
it, VR, keeps VPAD below 0.5 V. Equation 7.2 also applies.
VDD = VF + VR + VPAD
≤he supply domain for LED[2:0] must remain powered for LED functions to operate.
≤he LED current adds to the overall current. Conservative LED selection extends battery life.
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CSRA64215 QFN Data Sheet
r.
ILED
LED Forward Voltage, VF
m
≤he audio interface circuit consists of:
Stereo/dual-mono audio codec.
Dual analogue audio inputs.
Dual analogue audio outputs.
2 configurable PCM and I²S interfaces, one of which can be used. For configuration information, contact CSR.
co
Figure 8.1 shows the functional blocks of the interface. ≤he codec supports stereo/dual-mono playback and recording
of audio signals at multiple sample rates with a 16-bit resolution. ≤he ADC and the DAC of the codec each contain 2
independent high-quality channels. Any ADC or DAC channel runs at its own independent sample rate.
Stereo / Dual-mono Codec
PCM1
r.
ke
Register Interface
Registers
Stereo
Audio
Codec
Driver
2 x Differential
DAC Outputs
2 x Differential
ADC Inputs
ea
≤he interface for the digital audio bus shares the same pins as the PCM codec interface. ≤able 8.1 lists the alternative
functions.
sp
PCM_O≥≤
SD_O≥≤
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK
bt
PCM_IN
≤he term PCM in ≤able 8.1 and its subsections refers to the PCM1 and PCM2 interface.
≤he audio input circuitry consists of 2 independent 16-bit high-quality ADC channels:
Programmable as either stereo or dual-mono inputs
1 input programmable as either microphone or line input, the other as line input only
Each channel is independently configurable to be either single-ended or fully differential
Each channel has an analogue and digital programmable gain stage, this also aids optimisation of different
microphones
≤he audio output circuitry consists of a dual differential class A-B output stage.
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CSRA64215 QFN Data Sheet
Memory
Management
≥nit
Digital
Audio
Voice Port
G-TW-0012978.2.2
MM≥ Voice Port
PCM1 Interface
CSRA64215 QFN is designed for a differential audio output. If a single-ended audio output is required, use an
external differential to single-ended converter.
co
m
≤he main features of the interface are:
Stereo and mono analogue input for voice band and audio band
Stereo and mono analogue output for voice band and audio band
Support for I²S stereo digital audio bus standard
Support for PCM interface including PCM master codecs that require an external system clock
LINE_BP
High-quality ADC
ke
LINE_BN
LINE/MIC_AP
High-quality ADC
LINE/MIC_AN
Stereo Audio and Voice Band Output
SPKR_LP
ea
SPKR_LN
Digital Circuitry
Digital Codec
16
Input B
Digital Codec
16
Input A
High-quality DAC
16
High-quality DAC
16
G-TW-0012979.2.2
Stereo Audio and Voice Band Input
Low-pass Filter
SPKR_RN
SPKR_RP
sp
Low-pass Filter
≤he CSRA64215 QFN audio codec uses a fully differential architecture in the analogue signal path, which results in
low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from
a dual power supply, VDD_A≥DIO for the audio circuits and VDD_A≥DIO_DRV for the audio driver circuits.
bt
≤he CSRA64215 QFN consists of 2 high-quality ADCs:
Each ADC has a second-order Sigma-Delta converter
Each ADC is a separate channel with identical functionality
≤here are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain
stage
Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40 kHz:
8 kHz
11.025 kHz
16 kHz
22.050 kHz
24 kHz
32 kHz
44.1 kHz
48 kHz
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CSRA64215 QFN Data Sheet
r.
≤o avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel
for audio output. With respect to audio input, software and any registers, channel 0 or channel A represents the
left channel and channel 1 or channel B represents the right channel.
ADC Analogue Gain:
-3 dB to 12 dB in 3 dB steps
co
ADC Pre-amplifier:
0 dB, 9 dB, 21 dB and 30 dB
Audio Input
≤o Digital Codec
ke
ea
CSRA64215 QFN has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:
≤he ADC pre-amplifier has 4 gain settings: 0 dB, 9 dB, 21 dB and 30 dB
≤he ADC analogue amplifier gain is -3 dB to 12 dB in 3 dB steps
≤he overall analogue gain for the pre-amplifier and analogue amplifier is -3 dB to 42 dB in 3 dB steps
At mid to high gain levels it acts as a microphone pre-amplifier
At low gain levels it acts as an audio line level amplifier
≤able 8.2 shows that a digital gain stage inside the ADC varies between -24 dB to 21.5 dB. ≤here is also a fine gain
sp
interface with a 9-bit gain setting enabling gain changes in 1/32 steps. For more information, contact CSR.
0
8
-24
1
3.5
9
-20.5
2
6
10
-18
3
9.5
11
-14.5
4
12
12
-12
5
15.5
13
-8.5
6
18
14
-6
7
21.5
15
-2.5
bt
0
≤he firmware controls the audio input gain.
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CSRA64215 QFN Data Sheet
r.
System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain
G-≤W-0005535.5.2
ADC Digital Gain:
-24 dB to 21.5 dB in alternating
2.5 dB and 3 dB steps
ADC Pre-amplifier
and ADC Analogue Gain:
-3 dB to 42 dB in 3 dB steps
m
Figure 8.3 shows that the CSRA64215 QFN audio input gain consists of:
An analogue gain stage based on a pre-amplifier and an analogue gain amplifier
A digital gain stage
≤he ADC contains 2 integrated anti-aliasing filters:
A long IIR filter suitable for music (>44.1 kHz)
G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance (which
is the best selection for 8 kHz / 16 kHz / voice)
m
For more information, contact CSR.
r.
ke
≤able 8.3 shows that a digital gain stage inside the DAC varies between -24 dB to 21.5 dB. ≤here is also a fine gain
0
8
-24
1
3.5
9
-20.5
2
6
10
-18
3
9.5
11
-14.5
4
12
12
-12
5
15.5
13
-8.5
6
18
14
-6
7
21.5
15
-2.5
bt
sp
0
ea
interface with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR.
≤he overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and
analogue amplifier settings.
≤able 8.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3 dB steps.
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CSRA64215 QFN Data Sheet
Each DAC supports the following sample rates:
8 kHz
11.025 kHz
16 kHz
22.050 kHz
32 kHz
40 kHz
44.1 kHz
48 kHz
96 kHz
co
≤he DAC consists of:
2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in functionality
2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage
0
3
-12
6
-3
2
-15
5
-6
1
4
-9
0
m
7
-18
co
-21
≤he firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue
amplifier settings.
r.
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8.2.13 Microphone Input
CSRA64215 QFN contains an independent low-noise microphone bias generator. ≤he microphone bias generator is
recommended for biasing electret condensor microphones. Figure 8.4 shows a biasing circuit for microphones with a
sensitivity between about 40 to 60 dB (0 dB = 1 V/Pa).
ea
Microphone Bias
(MIC_BIAS)
+
C2
LINE/MIC_AN
MIC1
Input
Amplifier
bt
sp
R1
LINE/MIC_AP
G-TW-0012980.1.1
C1
≤he microphone bias generator derives its power from VBA≤ or VO≥≤_3V3 and requires no capacitor on its
output.
≤he microphone bias generator maintains regulation within the limits 70 A to 2.8 mA, supporting a 2 mA
source typically required by 2 electret condensor microphones. If the microphone sits below these limits, then
the microphone output must be pre-loaded with a large value resistor to ground.
Biasing resistors R1 is 2.2 k .
≤he input impedance at LINE/MIC_AN and LINE/MIC_AP is typically 6 k .
C1 and C2 are 100/150 nF if bass roll-off is required to limit wind noise on the microphone.
R1 sets the microphone load impedance and are normally around 2.2 k .
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CSRA64215 QFN Data Sheet
≤he DAC contains an integrated digital FIR filter with the following modes:
A default long FIR filter for best performance at 44.1 kHz.
A short FIR to reduce latency.
A narrow FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8 kHz / 16 kHz.
m
co
≤he microphone bias characteristics include:
Power supply:
CSRA64215 QFN microphone supply is VBA≤ or VO≥≤_3V3
Minimum input voltage = Output voltage + drop-out voltage
Maximum input voltage is 4.3 V
Drop-out voltage:
300 mV maximum
Output voltage:
1.8 V or 2.6 V
≤olerance 90% to 110%
Output current:
70 A to 2.8 mA
No load capacitor required
Figure 8.5 and Figure 8.6 show 2 circuits for line input operation and show connections for either differential or singleended inputs.
ke
LINE/MIC_AN
ea
C3
LINE_BN
LINE_BP
C1
LINE/MIC_AP
C2
LINE/MIC_AN
C3
LINE_AP
C4
LINE_AN
G-TW-0012982.1.1
bt
sp
C4
LINE/MIC_AP
G-TW-0012981.1.1
C2
≤he output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency
to bit stream, which is fed into the analogue output circuitry.
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CSRA64215 QFN Data Sheet
C1
r.
In line input mode, the input impedance of the pins to ground varies from 6 k to 34 k depending on input gain setting.
≤he analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output stage
amplifier. Figure 8.7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP for the
left channel, and between SPKR_RN and SPKR_RP for the right channel.
co
SPKR_LN
ke
8.2.16 Mono Operation
Mono operation is a single-channel operation of the stereo codec. ≤he left channel represents the single mono channel
for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-mono channel
operation.
bt
sp
ea
In single channel mono operation, disable the other channel to reduce power consumption.
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CSRA64215 QFN Data Sheet
SPKR_RN
r.
SPKR_RP
G-TW-0005537.1.1
m
SPKR_LP
In some applications it is necessary to implement side tone. ≤his side tone function involves feeding a properly gained
microphone signal in to the DAC stream, e.g. earpiece. ≤he side tone routing selects the version of the microphone
signal from before or after the digital gain in the ADC interface and adds it to the output signal before or after the digital
gain of the DAC interface, see Figure 8.8.
DAC Interface
Digital Gain
Side Tone Route
Analogue Output
Demux
Side Tone
ke
G-TW-0005375.1.1
Digital Gain
ea
Digital Output
Mux
Analogue Input
ADC Interface
ADC
sp
≤he ADC provides simple gain to the side tone data. ≤he gain values range from -32.6 dB to 12.0 dB in alternating
steps of 2.5 dB and 3.5 dB, see ≤able 8.5.
-32.6 dB
8
-8.5 dB
1
-30.1 dB
9
-6.0 dB
2
-26.6 dB
10
-2.5 dB
3
-24.1 dB
11
0 dB
4
-20.6 dB
12
3.5 dB
5
-18.1 dB
13
6.0 dB
6
-14.5 dB
14
9.5 dB
7
-12.0 dB
15
12.0 dB
bt
0
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CSRA64215 QFN Data Sheet
Side Tone Route
r.
Side Tone Gain
co
Digital Input
m
DAC
≤he values of side tone are shown for information only. During standard operation, the application software controls
the side tone gain.
m
≤he following PS Keys configure the side tone hardware:
PSKEY_SIDE_≤ONE_ENABLE
PSKEY_SIDE_≤ONE_GAIN
PSKEY_SIDE_≤ONE_AF≤ER_ADC
PSKEY_SIDE_≤ONE_AF≤ER_DAC
co
CSRA64215 QFN has a programmable digital filter integrated into the ADC channel of the codec. ≤he filter is a 2-stage,
second order IIR and is for functions such as custom wind noise reduction. ≤he filter also has optional DC blocking.
≤he filter has 10 configuration words:
1 for gain value
8 for coefficient values
1 for enabling and disabling the DC blocking
r.
ke
≤he position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.
For example:
ea
01.1111111111
01.0000000000
00.0000000000
11.0000000000
10.0000000000
=
=
=
=
=
most positive number, close to 2
1
0
-1
-2, most negative number
sp
≤he filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps. ≤his requires firmware support. ≤he configuration function takes 10 variables in the
following order:
bt
0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
Gain
b01
b02
a01
a02
b11
b12
a11
a12
DC Block (1 = enable, 0 = disable)
Equation 8.1 shows the equation for the IIR filter.
Filter, H(z) = Gain ×
1
2 )
1
2 )
(1 +b
(1 +b
+ b02 z
+ b12 z
01 z
11 z
×
1
2 )
1
2 )
(1 +a
(1 +a
z
+a
z
z
+a
z
01
11
02
12
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CSRA64215 QFN Data Sheet
≤he gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN.
Equation 8.2 shows the equation for when the DC blocking is enabled.
z 1 )
≤his section describes the digital audio interfaces for the PCM1 and PCM2 interfaces.
m
Filter with DC Blocking, HDC (z) = H(z) × ( 1
sp
ea
ke
≤he audio PCM interface on the CSRA64215 QFN supports:
Continuous transmission and reception of PCM encoded audio data over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and reception of PCM
data.
A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not
pass through the HCI protocol layer.
Hardware on the CSRA64215 QFN for sending data to and from a SCO connection.
≥p to 3 SCO connections on the PCM interface at any one time.
PCM interface master, generating PCM_SYNC and PCM_CLK.
PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
Various clock formats including:
Long Frame Sync
Short Frame Sync
GCI timing environments
13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats.
Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.
≤he PCM configuration options are enabled by setting PSKEY_PCM_CONFIG32.
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
128/256/512/1536/2400kHz
8/48kHz
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G-TW-0000217.3.4
bt
When configured as the master of the PCM interface, CSRA64215 QFN generates PCM_CLK and PCM_SYNC.
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CSRA64215 QFN Data Sheet
r.
≤he term PCM refers to PCM1 and PCM2.
co
≤he PCM1 interface shares the same physical set of pins with the SPI interface. Either interface is selected using
SPI_PCM#:
SPI_PCM# = 1 selects SPI
SPI_PCM# = 0 selects PCM/PIO
≤he PCM2 interface shares 2 of its pins with the ≥AR≤ interface hardware flow control:
PCM2_IN = ≥AR≤_R≤S
PCM2_CLK= ≥AR≤_C≤S
PCM_OUT
PCM_SYNC
m
Up to 2400kHz
PCM_CLK
co
8/48kHz
G-TW-0000218.3.3
PCM_IN
r.
PCM_OUT
Undefined
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
sp
PCM_IN
ea
PCM_CLK
Undefined
G-TW-0000219.2.2
ke
PCM_SYNC
)
bt
CSRA64215 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_O≥≤ on the rising edge.
PCM_O≥≤ is configurable to switch to high impedance on the falling edge of PCM_CLK of the last data bit or on the
rising edge.
PCM_O≥≤ only goes tristate if ≤X_≤RIS≤A≤E_EN = 1 and the next slot is unused.
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CSRA64215 QFN Data Sheet
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In
Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When CSRA64215 QFN is
configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long. When
CSRA64215 QFN is configured as PCM Slave, PCM_SYNC pulse length may vary from 1 PCM_CLK cycle to half the
PCM_SYNC rate.
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always 1
clock cycle long.
PCM_CLK
Undefined
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Undefined
ke
As with Long Frame Sync, CSRA64215 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits
PCM_O≥≤ on the rising edge. PCM_O≥≤ is configurable to switch to high impedance on the falling edge of PCM_CLK
of the last data bit or on the rising edge.
PCM_O≥≤ only goes tristate if ≤X_≤RIS≤A≤E_EN = 1 and the next slot is unused.
LONG_PCM_SYNC
Or
sp
SHORT_PCM_SYNC
ea
More than 1 SCO connection over the PCM interface is supported using multiple slots. ≥p to 3 SCO connections are
carried over any set of the first 4 slots.
bt
PCM_OUT
PCM_IN
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7 8
Do Not Care 1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
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8 Do Not Care
G-TW-0000221.3.2
PCM_CLK
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CSRA64215 QFN Data Sheet
r.
PCM_IN
1
co
PCM_OUT
G-TW-0000220.2.3
m
PCM_SYNC
CSRA64215 QFN is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. ≤he two 64 kbps
B channels are accessed when this mode is configured.
PCM_IN
Do Not
Care
1
2
3
4
5
6
7
8
1
2
1
2
3
4
5
6
7
8
1
2
4
5
6
7
8
3
4
5
6
B2 Channel
7
8
Do Not
Care
≤he start of frame is indicated by the rising edge of PCM_SYNC, which runs at 8 kHz.
bt
sp
ea
ke
CSRA64215 QFN receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations
are either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats.
16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.
CSRA64215 QFN supports:
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
A sample rate of 8ksps.
Little or big endian bit order.
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.
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CSRA64215 QFN Data Sheet
r.
B1 Channel
3
co
PCM_OUT
G-TW-0000222.2.3
PCM_CLK
m
PCM_SYNC
Sign
Extension
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8-bit
Sample
8-bit
Sample
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
co
Zeros
Padding
m
A 16-bit slot with 8-bit companded sample and sign extension selected.
A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign
Extension
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15
16
13-bit
Sample
ke
A 16-bit slot with 13-bit linear sample and sign extension selected.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Audio
Gain
ea
PCM_OUT
G-TW-0000223.2.3
13-bit
Sample
A 16-bit slot with 13-bit linear sample and audio gain selected.
bt
sp
CSRA64215 QFN has a mute facility that forces PCM_O≥≤ to be 0. In master mode, CSRA64215 QFN is compatible
with some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running.
fmclk
128
4 MHz DDS generation.
-
PCM_CLK frequency
256
-
kHz
512
48 MHz DDS
generation.
2.9
-
-
kHz
-
8
-
kHz
-
PCM_SYNC frequency for SCO connection
tmclkh (a)
PCM_CLK high
4 MHz DDS generation
980
-
-
ns
tmclkl (a)
PCM_CLK low
4 MHz DDS generation
730
-
-
ns
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CSRA64215 QFN Data Sheet
r.
PCM_OUT
-
-
21
ns pk-pk
Delay time from PCM_CLK high to PCM_SYNC
high
-
-
20
ns
tdmclkpout
Delay time from PCM_CLK high to valid
PCM_O≥≤
-
-
tdmclklsyncl
Delay time from PCM_CLK low to PCM_SYNC low
(Long Frame Sync only)
-
-
tdmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC
low
-
tdmclklpoutz
Delay time from PCM_CLK low to PCM_O≥≤ high
impedance
-
tdmclkhpoutz
Delay time from PCM_CLK high to PCM_O≥≤ high
impedance
-
tsupinclkl
Set-up time for PCM_IN valid to PCM_CLK low
thpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
20
ns
20
ns
-
20
ns
-
20
ns
-
20
ns
20
-
-
ns
0
-
-
ns
ke
ea
CSRA64215 QFN Data Sheet
(a)
m
tdmclksynch
48 MHz DDS
generation
co
PCM_CLK jitter
r.
-
Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
t dmclklsyncl
t dmclksynch
sp
PCM_SYNC
t dmclkhsyncl
f mlk
t mclkh
t mclkl
PCM_OUT
t dmclklpoutz
t dmclkpout
MSB (LSB)
t supinclkl
PCM_IN
tr ,t f
t dmclkhpoutz
LSB (MSB)
t hpinclkl
MSB (LSB)
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LSB (MSB)
G-TW-0000224.2.3
bt
PCM_CLK
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t dmclksynch
t dmclkhsyncl
PCM_SYNC
t mclkh
m
f mlk
t mclkl
co
PCM_CLK
t dmclklpoutz
PCM_OUT
tr ,t f
MSB (LSB)
LSB (MSB)
bt
sp
ea
ke
MSB (LSB)
r.
PCM_IN
t hpinclkl
LSB (MSB)
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CSRA64215 QFN Data Sheet
t supinclkl
t dmclkhpoutz
G-TW-0000225.3.3
t dmclkpout
PCM clock frequency (Slave mode: input)
64
-
(a)
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
(b)
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
tsusclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
ns
tdpout
Delay time from PCM_SYNC or PCM_CLK,
whichever is later, to valid PCM_O≥≤ data (Long
Frame Sync only)
-
-
20
ns
tdsclkhpout
Delay time from CLK high to PCM_O≥≤ valid data
-
-
15
ns
tdpoutz
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_O≥≤ data line high
impedance
-
-
15
ns
tsupinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
ns
thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
ns
ke
ea
CSRA64215 QFN Data Sheet
r.
co
m
fsclk
Max frequency is the frequency defined by PSKEY_PCM_MIN_CP≥_CLOCK
(b)
Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CP≥_CLOCK
sp
(a)
f sclk
t sclkh
t tsclkl
bt
PCM_CLK
t hsclksynch
t susclksynch
PCM_SYNC
t dpoutz
PCM_OUT
MSB (LSB)
t supinsclkl
PCM_IN
t dsclkhpout
tr ,t f
t dpoutz
LSB (MSB)
t hpinsclkl
MSB (LSB)
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LSB (MSB)
G-TW-0000226.3.2
t dpout
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f sclk
t sclkh
t tsclkl
PCM_CLK
t hsclksynch
m
t dpoutz
t dsclkhpout
PCM_OUT
tr ,t f
LSB (MSB)
LSB (MSB)
ke
MSB (LSB)
CSRA64215 QFN has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:
ea
Generating these signals by DDS from CSRA64215 QFN internal 4 MHz clock. ≥sing this mode limits
PCM_CLK to 128, 256 or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48 MHz clock, which enables a greater range of frequencies
to be generated with low jitter but consumes more power. ≤o select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENG≤H_SYNC_EN in
PSKEY_PCM_CONFIG32.
sp
PSKEY_PCM_≥SE_LOW_JI≤≤ER_MODE sets the low jitter mode when the sync rate is 8 kHz and the PCM clock is
set either by PSKEY_PCM_CLOCK_RA≤E or through the audio API, see BlueCore Audio API Specification.
Configure the PCM by using PSKEY_PCM_CONFIG32 or through the audio API, see BlueCore Audio API
Specification. ≤he default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e. first slot following sync is active, 13-bit
bt
linear voice format, long frame sync and interface master generating 256 kHz PCM_CLK from 4 MHz internal clock
with no tristate of PCM_O≥≤.
8.4
I²S1 and I²S2 Interface
≤he CSRA64215 QFN supports 2 industry-standard I²S digital audio interfaces, left-justified or right-justified. ≤he
interfaces (I²S1 and I²S2) share the same pins as their equivalent number PCM interface (PCM1 and PCM2), which
means each audio bus is mutually exclusive in its usage. ≤able 8.8 lists these alternative functions.
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CSRA64215 QFN Data Sheet
PCM_IN
t hpinsclkl
r.
MSB (LSB)
t supinsclkl
t dpoutz
co
PCM_SYNC
G-TW-0000227.3.2
t susclksynch
PCM1_IN
I2S1_SD_IN
PCM1_SYNC
I2S1_WS
PCM1_CLK
I2S1_SCK
PCM2_O≥≤
I2S2_SD_O≥≤
PCM2_IN
I2S2_SD_IN
PCM2_SYNC
I2S2_WS
PCM2_CLK
I2S2_SCK
m
I2S1_SD_O≥≤
ke
In this section the terms:
I²S refers to the I²S1 and I²S2 interfaces.
SD_IN refers to I2S1_SD_IN or I2S1_SD_IN.
SD_O≥≤ refers to I2S1_SD_O≥≤ or I2S1_SD_O≥≤.
WS refers to I2S1_WS or I2S1_WS.
SCK refers to I2S1_SCK or I2S1_SCK.
bt
sp
ea
Configure the digital audio interface using PSKEY_DIGI≤AL_A≥DIO_CONFIG, see the PS Key file for more details.
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CSRA64215 QFN Data Sheet
r.
co
PCM1_O≥≤
Figure 8.20 shows the timing diagram for the I²S interface.
WS
Left Channel
Right Channel
SD_IN/OUT
MSB
LSB
m
SCK
MSB
LSB
WS
co
Left -justified Mode
Left Channel
Right Channel
MSB
LSB
MSB
LSB
ke
Right -justified Mode
Left Channel
SD_IN/OUT
ea
SCK
MSB
LSB
Right Channel
MSB
G-TW-0000230.3.2
WS
LSB
I2 S Mode
sp
≤he internal representation of audio samples within the CSRA64215 QFN is 16-bit and data on SD_O≥≤ is limited to
16-bit per channel.
SCK Frequency
bt
-
-
-
6.2
MHz
-
WS Frequency
-
-
96
kHz
tch
SCK high time
80
-
-
ns
tcl
SCK low time
80
-
-
ns
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CSRA64215 QFN Data Sheet
SD_IN/OUT
r.
SCK
WS valid to SCK high set-up
time
20
-
-
ns
tsh
SCK high to WS invalid hold time
2.5
-
-
ns
topd
SCK low to SD_O≥≤ valid delay
time
-
-
tisu
SD_IN valid to SCK high set-up
time
20
-
tih
SCK high to SD_IN invalid hold
time
2.5
m
tssu
ns
-
ns
co
20
-
ns
WS(Input)
t ch
SCK(Input)
ke
t ssu
t sh
t cl
t ih
bt
sp
SD_IN
t isu
G-TW-0000231.2.2
SD_OUT
ea
topd
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CSRA64215 QFN Data Sheet
r.
-
SCK Frequency
-
-
6.2
MHz
-
WS Frequency
-
-
96
kHz
tspd
SCK low to WS valid delay time
-
-
39.27
ns
topd
SCK low to SD_O≥≤ valid delay
time
-
-
18.44
ns
tisu
SD_IN valid to SCK high set-up
time
18.44
-
-
ns
tih
SCK high to SD_IN invalid hold
time
0
-
ns
ke
-
CSRA64215 QFN Data Sheet
r.
co
m
-
WS(Output)
SCK(Output)
ea
t spd
SD_OUT
t isu
bt
SD_IN
t ih
G-TW-0000232.2.2
sp
t opd
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ke
ea
ON
ON
OFF
OFF
SMPS
SMPS
Single-supply
SMPS
ON
OFF
ON
ON
SMPS
LDO
sp
Dual-supply
SMPS
ON
ON
ON
ON
SMPS
LDO
Linear supply
OFF
OFF
ON
ON
External
LDO
bt
Parallelsupply SMPS
For more information on CSRA64215 QFN power supply configuration, see the Configuring the Power Supplies on
CSR8670 application note.
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CSRA64215 QFN Data Sheet
r.
co
m
For greater power efficiency the CSRA64215 QFN contains 2 switch-mode regulators:
1 generates a 1.80 V supply rail with an output current of 185 mA, see Section 9.1.
1 generates a 1.35 V supply rail with an output current of 160 mA, see Section 9.2.
Combining the 2 switch-mode regulators in parallel generates a single 1.80 V supply rail with an output current
of 340 mA, see Section 9.3.
CSRA64215 QFN contains 4 LDO linear regulators:
3.30 V bypass regulator, see Section 9.4.
0.85 V to 1.20 V VDD_DIG linear regulator, see Section 9.5.
1.35 V VDD_A≥X linear regulator, see Section 9.6.
1.35 V VDD_ANA linear regulator, see Section 9.7.
≤he recommended configurations for power control and regulation on the CSRA64215 QFN are:
3 switch-mode configurations:
A 1.80 V and 1.35 V dual-supply rail system using the 1.80 V and 1.35 V switch-mode regulators, see
Figure 9.1. ≤his is the default power control and regulation configuration for the CSRA64215 QFN.
A 1.80 V single-supply rail system using the 1.80 V switch-mode regulator.
A 1.80 V parallel-supply rail system for higher currents using the 1.80 V and 1.35 V switch-mode regulators
with combined outputs, see Figure 9.2.
A linear configuration using an external 1.8 V rail omitting all regulators
≤able 9.1 shows settings for the recommended configurations for power control and regulation on the CSRA64215 QFN.
VCHG
1.8 V 1.35 V 3.3 V
VBAT
EN
Charger
50 to 200 mA
Charge
Reference
OUT
VOUT_3V3
Bypass Linear
Regulator
SMP_BYP
SMP_VBAT
IN
1.35 V OUT
Switch-mode
RegulatorSENSE
EN
LX_1V35
m
VBAT_SENSE
IN
1.8 V OUT
Switch-mode
RegulatorSENSE
EN
co
SMPS_1V35_SENSE
Reference
LX_1V8
SMPS_1V8_SENSE
VREGENABLE
CSRA64215 QFN Data Sheet
r.
Analogue and Auxiliary
IN
VDD_AUX
Regulator
SENSE
ke
EN
OUT
VDD_AUX_1V8
VDD_AUX
Auxiliary Circuits
IN
VDD_ANA
Regulator
EN
OUT
SENSE
ea
Bluetooth
VDD_BT_RADIO
VDD_BT_RADIO
VDD_BT_LO
VDD_PADS_1
I/O
VDD_PADS_2
Audio Circuits
sp
Audio Driver
VDD_AUDIO_DRV
Audio Core
VDD_AUDIO
Digital Core Circuits
EN
IN
VDD_DIG
Regulator
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
OUT
SENSE
VREGIN_DIG
VDD_DIG
G-TW-0012182.3.2
bt
VDD_ANA
Page 57 of 106
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VCHG
1.8 V 1.35 V 3.3 V
VBAT
EN
Charger
50 to 200 mA
Charge
Reference
OUT
VOUT_3V3
Bypass Linear
Regulator
SMP_BYP
SMP_VBAT
IN
1.35 V SENSE
Switch-mode
Regulator OUT
EN
SMPS_1V35_SENSE
IN
OUT
1. 8 V
Switch-mode
RegulatorSENSE
EN
co
LX_1V35
Reference
m
VBAT_SENSE
LX_1V8
SMPS_1V8_SENSE
VREGENABLE
CSRA64215 QFN Data Sheet
r.
Analogue and Auxiliary
IN
VDD_AUX
Regulator
SENSE
ke
EN
OUT
VDD_AUX_1V8
VDD_AUX
Auxiliary Circuits
IN
VDD_ANA
Regulator
EN
OUT
SENSE
ea
Bluetooth
VDD_BT_RADIO
VDD_BT_RADIO
VDD_BT_LO
VDD_PADS_1
I/O
VDD_PADS_2
Audio Circuits
sp
Audio Driver
VDD_AUDIO_DRV
Audio Core
VDD_AUDIO
Digital Core Circuits
EN
IN
VDD_DIG
Regulator
Production Information
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OUT
SENSE
VREGIN_DIG
VDD_DIG
G-TW-0012183.3.2
bt
VDD_ANA
Page 58 of 106
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CSR recommends using the integrated switch-mode regulator to power the 1.80 V supply rail.
VO≥≤_3V3
C1
2.2 µF
C2
2.2 µF
LX_1V8
1.8 V Supply Rail
SMPS_1V8_SENSE
C3
2.2 µF
VSS_SMPS_1V8
ke
Minimise the series resistance of the tracks between the regulator input, VBA≤ and VO≥≤_3V3, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V8.
Also minimise the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximise
efficiency.
sp
ea
For the regulator to meet its specifications it requires a total resistance of <1.0 (<0.5 recommended) for the following:
≤he track between the battery and VBA≤.
≤he track between LX_1V8 and the inductor.
≤he inductor, L1, ESR.
≤he track between the inductor, L1, and the sense point on the 1.80 V supply rail.
≤he following enable the 1.80 V switch-mode regulator:
VREGENABLE pin
≤he CSRA64215 QFN firmware with reference to PSKEY_PS≥_ENABLES
VCHG pin
≤he switching frequency is adjustable by setting an offset from 4.00 MHz using PSKEY_SMPS_FREQ_OFFSE≤, which
also affects the 1.35 V switch-mode regulator.
bt
When the 1.80 V switch-mode regulator is not required, leave unconnected:
≤he regulator input VBA≤ and VO≥≤_3V3
≤he regulator output LX_1V8
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CSRA64215 QFN Data Sheet
r.
≤o 1.35 V Switch-mode
Regulator Input
G-TW-0014614.2.2
LX
1.8 V Switch-mode
Regulator
SENSE
co
VBA≤
L1
4.7 µH
m
Figure 9.3 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7 µH), followed by a low
ESR shunt capacitor, C3 (2.2 µF), is required between the LX_1V8 terminal and the 1.80 V supply rail. Connect the
1.80 V supply rail and the SMPS_1V8_SENSE pin.
9.2
1.35 V Switch-mode Regulator
CSR recommends using the integrated switch-mode regulator to power the 1.35 V supply rail.
VO≥≤_3V3
C1
2.2 µF
C2
2.2 µF
LX_1V35
1.35 V Supply Rail
SMPS_1V35_SENSE
VSS_SMPS_1V35
ke
Minimise the series resistance of the tracks between the regulator input, VBA≤ and VO≥≤_3V3, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V35.
Also minimise the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximise
efficiency.
sp
ea
For the regulator to meet its specifications it requires a total resistance of <1.0 (<0.5 recommended) for the following:
≤he track between the battery and VBA≤.
≤he track between LX_1V8 and the inductor.
≤he inductor, L1, ESR.
≤he track between the inductor, L1, and the sense point on the 1.35 V supply rail.
≤he following enable the 1.35 V switch-mode regulator:
VREGENABLE pin
≤he CSRA64215 QFN firmware with reference to PSKEY_PS≥_ENABLES
VCHG pin
≤he switching frequency is adjustable by setting an offset from 4.00 MHz using PSKEY_SMPS_FREQ_OFFSE≤, which
also affects the 1.80 V switch-mode regulator.
bt
When the 1.35 V switch-mode regulator is not required, leave unconnected:
≤he regulator input VBA≤ and VO≥≤_3V3
≤he regulator output LX_1V35
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CSRA64215 QFN Data Sheet
r.
≤o 1.8 V Switch-mode
Regulator Input
C3
4.7 µF
G-TW-0014615.2.2
LX
1.35 V Switchmode Regulator
SENSE
co
VBA≤
L1
4.7 µH
m
Figure 9.4 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7 µH), followed by a low
ESR shunt capacitor, C3 (4.7 µF), is required between the LX_1V35 terminal and the 1.35 V supply rail. Connect the
1.35 V supply rail and the SMPS_1V35_SENSE pin.
For applications that require a single 1.80 V supply rail with higher currents CSR recommends combining the outputs
of the integrated 1.80 V and 1.35 V switch-mode regulators in parallel to power a single 1.80 V supply rail, see Figure
9.5.
VBA≤
VO≥≤_3V3
C2
2.2 µF
LX_1V35
SMPS_1V35_SENSE
VSS_SMPS_1V35
LX_1V8
SMPS_1V8_SENSE
ke
LX
1.8 V Switch-mode
Regulator
SENSE
C3
2.2 µF
ea
VSS_SMPS_1V8
1.8 V Supply Rail
G-TW-0014616.2.2
L1
4.7 µH
Minimise the series resistance of the tracks between the regulator input VBA≤ and VO≥≤_3V3, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
Ensure a solid ground plane between C1, C2, C3, VSS_SMPS_1V8 and VSS_SMPS_1V35.
sp
Also minimise the collective parasitic capacitance on the track between LX_1V8, LX_1V35 and the inductor L1, to
maximise efficiency.
recommended) for the
bt
For the regulator to meet the its specifications it requires a total resistance of <1.0 (<0.5
following:
≤he track between the battery and VBA≤.
≤he track between LX_1V8, LX_1V35 and the inductor.
≤he inductor L1, ESR.
≤he track between the inductor, L1, and the sense point on the 1.80 V supply rail.
≤he following enable the 1.80 V switch-mode regulator:
VREGENABLE pin
≤he CSRA64215 QFN firmware with reference to PSKEY_PS≥_ENABLES
VCHG pin
≤he switching frequency is adjustable by setting an offset from 4.00 MHz using PSKEY_SMPS_FREQ_OFFSE≤.
When the 1.80 V switch-mode regulator is not required, leave unconnected:
≤he regulator input VBA≤ and VO≥≤_3V3
≤he regulator output LX_1V8
Correct switch-mode power supply performance depends on inductor choice. A key parameter is the saturation current
of the inductor. As an inductor saturates, its effective inductance decreases significantly, leading to the switching
currents increasing further. ≤his can eventually lead to:
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CSRA64215 QFN Data Sheet
r.
C1
2.2 µF
LX
1.35 V Switchmode Regulator
SENSE
co
m
Figure 9.5 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7 µH), followed by a low
ESR shunt capacitor, C3 (2.2 µF), is required between the LX_1V8 terminal and the 1.80 V supply rail. Connect the
1.80 V supply rail and the SMPS_1V8_SENSE pin and ground the SMPS_1V35_SENSE pin.
Poor regulator performance
RF interference
Possible instability
m
CSR recommends inductor selection ensures that the inductance reduction at 250 mA is less than 30% of nominal
inductance. ≤his is often stated as the inductor parameter Rated Current (L change) Max and the value is the current
at which the rated inductance has fallen by a specified percentage.
Some inductor manufacturers state the inductor's rated current as the temperature rise (DC current at which the
inductor temperature increases by a specified temperature). ≤his is not the same as saturation current.
≤he saturation performance can be particularly poor with small package inductors.
co
Another key inductor parameter is the DC resistance, because high DC resistance in the inductor decreases switchmode power supply efficiency.
Pay attention to the frequency for the inductor specified parameters. ≤he switch-mode power supply operates at
4 MHz, so inductor parameters should be stated at 4 MHz or higher.
r.
ke
Nominal inductance value (±20% tolerance)
3.84
4.7
5.64
Inductor Rdc for SMPS stability
0.1
0.25
1
0.1
0.25
0.4
Inductor saturation current (-30% reduction from the
nominal inductor value)
250
-
-
mA
Inductor self-resonant frequency
10
-
-
MHz
Direct capacitance on SMPS output (including tolerance
and de-rating)
1.5
2.2 / 4.7
10
µF
sp
ea
Inductor Rdc for SMPS efficiency
µH
bt
≤he integrated bypass LDO linear regulator is available as a 3.30 V supply rail and is an alternative supply rail to the
battery supply. ≤his is especially useful when the battery has no charge and the CSRA64215 QFN needs to power up.
≤he input voltage should be between 4.25 V to 6.50 V.
≤he integrated bypass LDO linear regulator can operate down to 3.1 V with a reduced performance.
Externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 2.2 µF to the VO≥≤_3V3
pin.
≤he output voltage is switched on when VCHG gets above 3.0 V.
≤he integrated low-voltage VDD_DIG linear regulator powers the digital circuits on CSRA64215 QFN. Externally
decouple the output of this regulator using a low ESR MLC capacitor of 470 nF.
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CSRA64215 QFN Data Sheet
≤able 9.2 shows CSR's testing and characterisation carried out on boards using ≤aiyo-Yuden CB2012≤4R7M parts
(0805 (2012 metric) package).
m
≤he integrated low-voltage VDD_A≥X linear regulator is optionally available to provide a 1.35 V auxiliary supply rail
when the 1.35 V switch-mode regulator is not used. When using the integrated low-voltage VDD_A≥X linear regulator,
externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 470 nF to the VDD_A≥X
pin.
≤he integrated low-voltage VDD_ANA linear regulator is optionally available to power the 1.35 V analogue supply rail
when the 1.35 V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA linear regulator,
externally decouple the output of this regulator using a 2.2 µF low ESR MLC capacitor to the VDD_ANA pin.
Voltage Regulator Enable
co
9.8
r.
ke
≤he VREGENABLE pin is active high, with a pull-down, typical 100 k , which is disabled by
PSKEY_VREG_ENABLE_S≤RONG_P≥LL.
CSRA64215 QFN boots-up when the voltage regulator enable pin is pulled high typically for 10 to 15 ms, enabling the
regulators. ≤he firmware then latches the regulators on. ≤he voltage regulator enable pin can then be released.
ea
≤he status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works
as an input line.
VREGENABLE should be asserted after the VBA≤ supply when VREGENABLE is not used as a power-on button.
9.9
External Regulators and Power Sequencing
CSR recommends that the integrated regulators supply the CSRA64215 QFN and it is configured based on the
information in this data sheet.
sp
If any of the supply rails for the CSRA64215 QFN are supplied from an external regulator, then it should match or be
better than the internal regulator available on CSRA64215 QFN. For more information see regulator characteristics in
Section 12.
bt
≤he internal regulators described in Section 9.1 to Section 9.7 are not recommended for external circuitry other
than that shown in Section 11.
For information about power sequencing of external regulators to supply the CSRA64215 QFN contact CSR.
CSRA64215 QFN is reset from several sources:
RS≤# pin
Power-on reset
≥SB charger attach reset
Software configured watchdog timer
≤he RS≤# pin is an active low reset. Assert the reset signal for a period >5 ms to ensure a full reset.
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.
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CSRA64215 QFN Data Sheet
When using the integrated regulators the voltage regulator enable pin, VREGENABLE, enables the CSRA64215 QFN
and the following regulators:
1.8 V switch-mode regulator
1.35 V switch-mode regulator
Low-voltage VDD_DIG linear regulator
Low-voltage VDD_A≥X linear regulator
Reset can also be triggered by a ≥AR≤ break symbol if:
Host interface is any ≥AR≤ transport and
PSKEY_HOS≤IO_≥AR≤_RESE≤_≤IMEO≥≤ is set to a non-zero value (>1000)
A warm reset function is also available under software control. After a warm reset RAM data remains available.
m
9.10.1 Digital Pin States on Reset
≤able 9.3 shows the pin states of CSRA64215 QFN on reset.
N/A
PIO[6]
Digital bidirectional
PDS
≥SB_DN
Digital bidirectional
N/A
PIO[7]
Digital bidirectional
PDS
PIO[0]
Digital bidirectional
P≥S
PIO[8]
Digital bidirectional
P≥S
PIO[1]
Digital bidirectional
P≥S
PIO[9]
Digital bidirectional
PDS
PIO[2]
Digital bidirectional
PDW
PIO[16]
Digital bidirectional
P≥S
PIO[3]
Digital bidirectional
PDW
PIO[17]
Digital bidirectional
PDS
PIO[4]
Digital bidirectional
PDW
PIO[18]
Digital bidirectional
PDW
PIO[5]
Digital bidirectional
PDW
PIO[21]
Digital bidirectional
PDW
ea
ke
r.
Digital bidirectional
P≥S = Strong pull-up
PDS = Strong pull-down
sp
P≥W = Weak pull-up
PDW = Weak pull-down
bt
≤he status of CSRA64215 QFN after a reset is:
Warm reset: baud rate and RAM data remain available
Cold reset: baud rate and RAM data not available
9.11
Automatic Reset Protection
CSRA64215 QFN includes an automatic reset protection circuit which restarts/resets CSRA64215 QFN when an
unexpected reset occurs, e.g. ESD strike or lowering of RS≤#. ≤he automatic reset protection circuit enables resets
from the VM without the requirement for external circuitry.
≤he reset protection is cleared after typically 2 s (1.6 s min to 2.4 s max).
If RS≤# is held low for >2.4 s CSRA64215 QFN turns off. A rising edge on VREGENABLE or VCHG is required to
power on CSRA64215 QFN.
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CSRA64215 QFN Data Sheet
≥SB_DP
co
Pin Name
10.1
Battery Charger Hardware Operating Modes
Yes
Fast charge
Yes
Standby
Yes
Error
Yes
>0 and <Vfast
r.
≤rickle charge
X
>Vfast and <Vfloat
ke
No
CSRA64215 QFN Data Sheet
Iterm (a) and >(Vfloat - Vhyst)
>(VCHG - 50mV)
Iterm is approximately 10% of Ifast for a given Ifast setting
ea
(a)
Disabled
co
m
≤he battery charger hardware is controlled by the VM. ≤he battery charger has 5 modes:
Disabled
≤rickle charge
Fast charge
Standby: fully charged or float charge
Error: charging input voltage, VCHG, is too low
≤he battery charger operating mode is determined by the battery voltage and current, see ≤able 10.1 and Figure
10.1.
sp
Ifast
Fast Charge Mode
Constant Current
bt
Fast Charge Mode
Constant Voltage
Itrickle
Standby Mode
Trickle Charge Mode
Vhyst
Iterm
Battery Voltage
Vfast
Vfloat
G-TW-0005583.3.2
Charge Current
Figure 10.1 shows the mode-to-mode transition voltages. ≤hese voltages are fixed and calibrated by CSR. ≤he
transition between modes can occur at any time.
≤he battery voltage remains constant in Fast Charge Constant Voltage Mode, the curved line on Figure 10.1 is for
clarity only.
≤he internal charger circuit can provide up to 200 mA of charge current, for currents higher than this the
CSRA64215 QFN can control an external pass transistor.
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In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals.
m
In the trickle charge mode, when the voltage on VBA≤_SENSE is lower than the Vfast threshold, a current of
approximately 10% of the fast charge current, Ifast, is sourced from the VBA≤ pin.
≤he Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes.
co
When the voltage on VBA≤_SENSE is greater than Vfast, the current sourced from the VBA≤ pin increases to Ifast.
Ifast is between 10 mA and 200 mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to correct
for process variation in the charger circuit.
≤he current is held constant at Ifast until the voltage at VBA≤_SENSE reaches Vfloat, then the charger reduces the current
sourced to maintain a constant voltage on the VBA≤_SENSE pin.
r.
10.1.4 Standby Mode
ke
When the battery is fully charged, the charger enters standby mode, and battery charging stops. ≤he battery voltage
on the VBA≤_SENSE pin is monitored, and when it drops below a threshold set at Vhyst below the final charging voltage,
Vfloat, the charger re-enters fast charge mode.
ea
≤he charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly
(VBA≤_SENSE is greater than VCHG - 50 mV (typical)).
In this mode, charging is stopped. ≤he battery charger does not require a reset to resume normal operation.
sp
≤he battery charger default trim values are written by CSR into non-volatile memory when each IC is characterised.
CSR provides various PS Keys for overriding the default trims.
bt
≤he VM charger code has overall supervisory control of the battery charger and is responsible for:
Responding to charger power connection/disconnection events
Monitoring the temperature of the battery
Monitoring the temperature of the die to protect against silicon damage
Monitoring the time spent in the various charge states
Enabling/disabling the charger circuitry based on the monitored information
Driving the user visible charger status LED(s)
10.4
Battery Charger Firmware and PS Keys
≤he battery charger firmware sets up the charger hardware based on the PS Key settings and traps called from the
VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery
capacity and type, which are set by the user in the PS Keys.
For more information on the CSRA64215 QFN, including details on setting up, calibrating, trimming and the PS Keys,
see Lithium Polymer Battery Charger Calibration and Operation for CSR8670 application note.
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CSRA64215 QFN Data Sheet
When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standby
mode. Iterm is typically 10% of the fast charge current.
m
≤he external mode is for charging higher capacity batteries using an external pass device. ≤he current is controlled by
sinking a varying current into the CHG_EX≤ pin, and the current is determined by measuring the voltage drop across
a resistor, Rsense, connected in series with the external pass device, see Figure 10.2. ≤he voltage drop is determined
by looking at the difference between the VBA≤_SENSE and VBA≤ pins. ≤he voltage drop across Rsense is typically
200 mV. ≤he value of the external series resistor determines the charger current. ≤his current can be trimmed with a
PS Key.
co
Figure 10.2 shows R1 (220 m ) and C1 (4.7 µF) form an RC snubber that is required to maintain stability across all
battery ESRs. ≤he battery ESR must be <1.0 .
VCHG
ke
VBAT
R1
220 m
G-TW-0005585.3.2
Rsense
BAT 1
Li+ Cell
n
bt
sp
ea
C1
4.7 µF
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 67 of 106
CS-323092-DSP3
www.csr.com
CSRA64215 QFN Data Sheet
VBAT_SENSE
TR 1
External Pass Device
r.
CHG_EXT
50R
i
ANA LDO
1.35 V
GND GND
BT_RF
2.45 GHz
ke
C2 and C3
Ensure the following tracks have good low impedance connections
(no via share and short thick tracks)
VSS_SMPS_1V8 to Battery Ground
VSS_SMPS_1V35 to Battery Ground
LX_1V8 to Inductor
LX_1V35 to Inductor
L1 to C4 track
L2 to C7 track
CSR recommend low Rdc inductors (<0.5 R) for L1 & L2 for optimum power efficiency
L4
0402
C15
100n
0402
1V35_SMPS
0201
VBAT
R100
63
22
25
26
31
23
21
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
27
32
PIO_16
PIO_17
PIO / UART
20
AIO_0
Analogue input / output
56
55
USB_P
USB_N
35
RSTB
SPI/PCM# high for SPI. Low for all other functions
VDD_PADS_2
AIO[0]
USB_P
USB_N
VDD_PADS1
RST#
U100
8
10n
5
2
3
7
VDD
SI/SIO0
CE
SO/SIO1 SCK
WP/SIO2
HOLD/SIO3
VSS
1
6
4
QSPI_FLASH_CS#
QSPI_FLASH_CLK
Quad SPI Flash
SPI Flash
USB (12 Mb/s)
Reset
0402
C18
15p
VBUS
Typical LEDs and Buttons
9k1
D100
BAT54C
VBUS
1.8 V
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
1.8 V
1.8 V
1.8 V
CLOCK PIO_n (even)
D103
S100
F4
R101
220R
R102
330R
0402
Q1
S101
F3
S102
F2
S103
VOL+
S104
VOL-
R103
330R
PIO_n
PIO_n
PIO_n
PIO_n
PIO_n
S
LED_0
G
D102
0402
PIO_n
GREEN
RED
D101
0402
D
C102
10n
BLUE
CON101
3.7 V
0201
Digital
Mic(s)
DATA
PIO_n (odd)
G-TW-0015982.1.2
Connect VBAT_SENSE to VBAT
if not using this circuit
Li+ CELL
1.8 V
1V8_SMPS
THERM
10k
VBAT
GND
GND
R108
220 mR
SPI_PCM#
15nH
LED_1
1%
400 mR
0603
R104
C105
4u7
PIO / PCM1 / Debug SPI / I2S
29
Left
Right
Speakers (16 to 32 Ohm)
Mic2
LED_2
VBAT
0402
PIO / UART
2k2
L5
0402
AIO_0
USB_N
USB_P
6
2
0805
VBAT_SENSE
BCX51
7
3
CHG_EXT 1
CON100
USB MINI-B
1
VBUS
2
D3
D+
4
ID
5
GND
Lithium Polymer Battery
(battery protection built in)
bt
USB / Charger Interface
Q100
PIO_2
PIO_3
PIO_4
PIO_5
LED outputs
Battery temperature sensor
Optional ancilliary circuits
VBUS
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
C17
15p
Dual Microphone inputs
MIC_2
PIO[16] / UART_RTS#
PIO[17] / UART_CTS#
SPKR_LN
SPKR_LP
C16
100n
59
60
62
57
61
58
65
64
R2
0402
2k2
0201
9
10
MIC_BN
4
MIC_2N
5
MIC_2P
MIC_BP
MIC_BIAS
C14
100n
2
0402
LED_0
LED_1
LED_2
1V8_SMPS
C101
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO[0]
QSPI_IO[1]
QSPI_IO[2]
QSPI_IO[3]
VDD_AUX
MIC_BIAS
C13
100n
SPI_PCM#
VDD_PADS1
R1
15nH
Mic 1
sp
MIC_AP
MIC_AN
1
0402
MIC_1
For example Taiyo Yuden CB2012T4R7M
C12
2u2
37
36
66
30
PIO[2] / PCM1_IN / SPI_MOSI
28
PIO[3] / PCM1_OUT / SPI_MISO
24
PIO[4] / PCM1_SYNC / SPI_CS#
34
PIO[5] / PCM1_CLK / SPI_CLK
VDD_PADS1
SPKR_LN
SPKR_LP
current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 & C4
Ensure routing from L2 to lead 39 and from L2 to C8/9 & leads 11 & 13 are kept separate
0402
MIC_1P 68
Ensure good low impedance ground return path through GND plane for SMPSU
MIC_1N 67
STAR
AU_REF
VSS_SMPS_1V35
VSS_SMPS_1V8
SP100
ea
VDD_DIG to Ground
51
69
VBAT to Battery and C2 - should be <1 ohm from battery
VCHG to charger connector and C1
46
GND PADDLE
C7 to VSS_SMPS_1V35
PIO[29] / LED[0]
PIO[30] / LED[1]
PIO[31] / LED[2]
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
VDD_PADS1
MIC BIAS
C4 to VSS_SMPS_1V8
Optional Fast charge
400 mohm = 500 mA
VDD_PADS_1
VDD_DIG_MEM
r.
68 Lead, 8 x 8 mm 0.4 mm Pitch Stereo QFN
Ensure the following components are placed next to CSRA64215
and have good low impedance connections both to signal and GND
18
CSRA64215 QFN Data Sheet
CSRA64215
PCB Layout Notes
and star connected near VSS_AUDIO as shown
Ensure analogue tracks stay over Analogue ground as much as possible
33
38
39
VDD_BT_RADIO
VREGIN_DIG
13
VDD_PADS2
1
Suggest analogue and digital grounds are separated if possible
VDD_PADS1
DIG LDO
Bluetooth RF
3
19
LED pad Vmax = VBAT
VDD_PADS2
12
XTAL_IN
XT1
26 MHz
0201
BT_RF
C11
100n
m
1.35 V
SPKR_RN
SPKR_RP
4
0402
6
7
OUT IN
C10
470n
SPKR_RN
SPKR_RP
U2
0201
co
1.35 V SMPS
AUX LDO
1.35 V
2
C9
2u2
XTAL_OUT
3.3 V
50R
i
0402
1.8 V SMPS
BYPASS REG
A NT
C8
15p
VDD_BT_LO
17
SMPS_1V35_SENSE
50
VDD_AUX
0201
11
C7
4u7
0603
LX_1V35
3
1V8_SMPS
52
L2
4u7
C6
10n
14
0201
8
15
16
C5
10n
VDD_AUDIO_DRV
LX_1V8
SMPS_1V8_SENSE
53
0201
VDD_AUDIO
C4
2u2
VDD_AUX_1V8
VDD_AUX_1V8
0402
47
54
49
VBAT
CHARGER
L1
4u7
VDD_USB
41
C3
2u2
1V35_SMPS
VDD_ANA
1V8_SMPS
0402
SMP_BYP
48
C2
2u2
VOUT_3V3
VBAT
45
0402
3V3_USB
SMP_VBAT
43
CHG_EXT
42
C1
2u2
VCHG
VREGENABLE
40
0402
44
S1
MFB
VBAT_SENSE
CHG_EXT
VBAT
VBAT_SENSE
VBAT VBUS
Page 68 of 106
CS-323092-DSP3
www.csr.com
Single 1.8 V-only supply. No USB, No switch modes.
1V8_INPUT
0402
1V8_INPUT
1V8_INPUT
VREGENABLE
VBAT & VCHG grounded
Q?
FDV301N
0402
or equivalent
0402
C4
2u2
0402
C5
100n
0201
C6
470n
0201
C8
15p
0402
C9
2u2
0201
C10
470n
0402
C11
100n
1.35 V
GNDGND
1
CSRA64215
ke
68 Lead, 8 x 8 mm 0.4 mm Pitch Stereo QFN
L4
R1
2k2
0201
Mic2
C16
100n
6
7
SPKR_LN
SPKR_LP
MIC_BN
4
0402
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
PIO_2
PIO_3
PIO_4
PIO_5
PIO
PIO / PCM1 / Debug SPI / I2S
29
SPI_PCM#
22
25
26
31
23
21
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
27
32
PIO_16
PIO_17
PIO / UART
20
AIO_0
Analogue input / output
RSTB
Reset
SPI/PCM# high for SPI. Low for all other functions
USB_P
USB_N
VDD_PADS1
RST#
U100
8
10n
5
2
3
7
VDD
SI/SIO0
CE
SO/SIO1 SCK
WP/SIO2
HOLD/SIO3
VSS
1
6
4
QSPI_FLASH_CS#
QSPI_FLASH_CLK
Quad SPI Flash
SPI Flash
56
55
35
0402
2k2
C17
15p
MIC_BIAS
L5
15nH
0201
AIO[0]
VDD_AUX
Dual Microphone inputs
MIC_2
PIO[16] / UART_RTS#
PIO[17] / UART_CTS#
VDD_PADS1
MIC_2N
C15
100n
59
60
62
57
61
58
65
64
LED outputs
1V8_INPUT
C101
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO[0]
QSPI_IO[1]
QSPI_IO[2]
QSPI_IO[3]
SPKR_RN
SPKR_RP
0402
LED_0
LED_1
LED_2
R2
0402
15nH
MIC_BP
MIC_2P
2
C14
100n
SPI_PCM#
9
10
0402
37
36
66
30
PIO[2] / PCM1_IN / SPI_MOSI
28
PIO[3] / PCM1_OUT / SPI_MISO
24
PIO[4] / PCM1_SYNC / SPI_CS#
34
PIO[5] / PCM1_CLK / SPI_CLK
SPKR_LN
SPKR_LP
C13
100n
5
MIC_BIAS
MIC_AP
MIC_AN
0402
MIC_1P 68
1
sp
MIC_1
C12
2u2
MIC_1N 67
AU_REF
ea
VSS_SMPS_1V35
VSS_SMPS_1V8
46
GND PADDLE
69
51
0402
Mic 1
bt
VDD_PADS_2
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
VDD_PADS1
MIC BIAS
STAR
VDD_PADS1
PIO[29] / LED[0]
PIO[30] / LED[1]
PIO[31] / LED[2]
CSRA64215 QFN Data Sheet
r.
2.45 GHz
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
VDD_PADS_1
VDD_PADS2
BT_RF
SP100
63
33
38
39
VREGIN_DIG
VDD_DIG_MEM
VDD_PADS1
DIG LDO
VDD_PADS2
12
18
LED pad Vmax = VBAT
Bluetooth RF
3
m
ANA LDO
26 MHz
19
C18
15p
NOTE: With 1.8 V input it is not possible to maintain internal mic bias performance,
so use of an external mic bias supply is recommended if required.
Left
Right
Speakers (16 to 32 Ohm)
G-TW-0015980.1.2
1.35 V SMPS
1.35 V
XT1
0201
BT_RF
XTAL_IN
XTAL_OUT
AUX LDO
SPKR_RN
SPKR_RP
4
50R
i
VDD_BT_RADIO
1.8 V SMPS
1.35 V
50R
U2
i
ANT
2
OUT IN
11
13
17
VDD_BT_LO
52
SMPS_1V35_SENSE
VDD_AUX
VDD_ANA
GND
50
GND
LX_1V35
14
3
GND
VDD_AUDIO
15
16
8
VDD_AUDIO_DRV
LX_1V8
3.3 V
GND
co
BYPASS REG
53
54
49
41
VBAT
CHARGER
If external reset signal is used CSR suggest
this is incorporated into VREGENABLE also
VDD_USB
SMP_BYP
VOUT_3V3
45
44
48
SMP_VBAT
VBAT
43
42
This circuit can be used to provide
the required delay.
GND
VDD_AUX_1V8
VDD_AUX_1V8
VREGENABLE requires to be asserted
after the system supply has risen in this configuration
CHG_EXT
VREGENABLE delay circuit
GND
VBAT_SENSE
GND
VCHG
40
VREGENABLE
0402
C3
100n
S
R?
100k
GND
1V8_INPUT
1V35
VREGENABLE
D
G
1V8_INPUT
R?
100k
SMPS_1V8_SENSE
C?
470n
47
0402
Page 69 of 106
CS-323092-DSP3
www.csr.com
Single 3.3 V only supply. USB, Dual switch-modes.
1V8_SMPS
1.35 V
BT_RF
MIC_1
L4
R1
0402
15nH
Mic 1
2k2
0201
bt
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Mic2
0402
m
33
63
18
C15
100n
0402
C16
100n
15nH
0201
C18
15p
LED_0
LED_1
LED_2
59
60
62
57
61
58
65
64
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
PIO_2
PIO_3
PIO_4
PIO_5
LED outputs
PIO
PIO / PCM1 / Debug SPI / I2S
29
SPI_PCM#
22
25
26
31
23
21
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
27
32
PIO_16
PIO_17
PIO / UART
20
AIO_0
Analogue input / output
56
55
USB_P
USB_N
35
RSTB
SPI/PCM# high for SPI. Low for all other functions
1V8_SMPS
C101
QSPI_FLASH_CS#
QSPI_FLASH_CLK
QSPI_IO[0]
QSPI_IO[1]
QSPI_IO[2]
QSPI_IO[3]
VDD_PADS1
PIO[16] / UART_RTS#
PIO[17] / UART_CTS#
VDD_PADS1
AIO[0]
SPKR_RN
SPKR_RP
USB_P
USB_N
VDD_PADS1
RST#
U100
8
10n
5
2
3
7
VDD
SI/SIO0
CE
SO/SIO1 SCK
WP/SIO2
HOLD/SIO3
VSS
1
6
4
QSPI_FLASH_CS#
QSPI_FLASH_CLK
Quad SPI Flash
SPI Flash
USB (12 Mb/s)
Reset
R2
0402
2k2
Left
Right
Speakers (16 to 32 Ohm)
L5
37
36
66
30
PIO[2] / PCM1_IN / SPI_MOSI
28
PIO[3] / PCM1_OUT / SPI_MISO
24
PIO[4] / PCM1_SYNC / SPI_CS#
34
PIO[5] / PCM1_CLK / SPI_CLK
SPI_PCM#
SPKR_LN
SPKR_LP
MIC_BN
MIC_2N
4
MIC_BP
MIC_BIAS
C14
100n
5
0402
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
C17
15p
Dual Microphone inputs
MIC_2
C13
100n
MIC_2P
0402
MIC_1P 68
MIC_1N 67
C12
2u2
PIO[29] / LED[0]
PIO[30] / LED[1]
PIO[31] / LED[2]
VDD_AUX
2
sp
0402
MIC_AP
MIC_AN
AU_REF
1
STAR
MIC BIAS
MIC_BIAS
ea
VSS_SMPS_1V35
51
46
69
GND PADDLE
VSS_SMPS_1V8
ke
68 Lead, 8 x 8 mm 0.4 mm Pitch Stereo QFN
VDD_PADS1
6
7
CSRA64215
SP100
VDD_PADS_2
VDD_PADS_1
r.
1
2.45 GHz
19
CSRA64215 QFN Data Sheet
GND GND
38
VDD_PADS2
Bluetooth RF
3
26 MHz
XTAL_IN
LED pad Vmax = VBAT
VDD_PADS1
DIG LDO
VDD_PADS2
12
XT1
G-TW-0015981.1.2
ANA LDO
9
10
BT_RF
C11
100n
0201
AUX LDO
SPKR_RN
SPKR_RP
4
0402
co
1.35 V SMPS
SPKR_LN
SPKR_LP
IN
C10
470n
XTAL_OUT
1.35 V
1.35 V
50R
i
0201
VDD_DIG_MEM
VDD_BT_RADIO
1.8 V SMPS
3.3 V
50R
U2
i
ANT
2
OUT
C9
2u2
11
13
0402
39
C8
15p
VDD_BT_LO
17
SMPS_1V35_SENSE
LX_1V35
VDD_AUX
0201
VREGIN_DIG
C7
4u7
50
0603
52
L2
4u7
C6
10n
14
0201
3
GND
8
53
C5
10n
VDD_AUDIO
LX_1V8
BYPASS REG
15
16
GND
0201
VDD_AUDIO_DRV
C4
2u2
VDD_AUX_1V8
VDD_AUX_1V8
0402
SMPS_1V8_SENSE
54
49
41
VBAT
CHARGER
L1
4u7
C3
2u2
GND
VDD_USB
SMP_BYP
VOUT_3V3
45
44
48
SMP_VBAT
VBAT
43
GND
0402
CHG_EXT
42
VCHG
40
VREGENABLE
C1
2u2
VBAT_SENSE
0402
RSTB
1V35_SMPS
VDD_ANA
1V8_SMPS
47
3V3_INPUT
Page 70 of 106
CS-323092-DSP3
www.csr.com
105
VCHG
-0.4
6.50
SMP_BYP
-0.4
VDD_≥SB
-0.4
LED[2:0]
-0.4
SMP_VBA≤
-0.4
VBA≤_SENSE
VREGENABLE
°C
Supply Voltage
Battery
V
3.60
V
4.40
V
4.25
V
-0.4
4.40
V
-0.4
4.40
V
-0.4
3.60
V
-0.4
3.60
V
-0.4
1.95
V
VDD_A≥DIO_DRV
-0.4
1.95
V
VDD_A≥X_1V8
-0.4
1.95
V
SMPS_1V35_SENSE
-0.4
1.45
V
VDD_A≥DIO
-0.4
1.45
V
VREGIN_DIG
-0.4
1.95
V
VDD_PADS_2
ea
SMPS_1V8_SENSE
sp
1.8 V
1.35 V
co
3.60
VDD_PADS_1
PIO
V
r.
3.3 V
ke
5 V (≥SB VB≥S)
VSS - 0.4
VDD + 0.4
3.60(a)
V
bt
Other terminal voltages
(a)
VDD is the VDD_PADS supply domain for this I/O. For more information, see Section 1.2. Voltage should not exceed 3.6 V on any I/O.
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 71 of 106
CS-323092-DSP3
www.csr.com
CSRA64215 QFN Data Sheet
-40
m
Storage temperature
Battery
5.00
6.50
V
SMP_BYP
3.10
3.30
3.60
V
VDD_≥SB
3.10
3.30
3.60
V
LED[2:0]
1.10
3.70
4.30
V
SMP_VBA≤
2.50
3.70
4.30
V
VBA≤_SENSE
0
3.70
4.25
V
VREGENABLE
0
3.70
4.25
V
VDD_PADS_1
1.70
1.80
3.60
V
1.70
1.80
3.60
V
1.70
1.80
1.95
V
1.70
1.80
1.95
V
VDD_PADS_2
SMPS_1V8_SENSE
(a)
1.70
1.80
1.95
V
SMPS_1V35_SENSE
1.30
1.35
1.45
V
VDD_A≥DIO
1.30
1.35
1.45
V
VREGIN_DIG
1.30
1.35 or 1.80(b)
1.95
V
Minimum input voltage of 4.75 V is required for full specification. Regulator operates at reduced load current from 3.1 V.
≤ypical value depends on output required by the low-voltage VDD_DIG linear regulator, see Section 12.3.2.2
bt
(b)
VDD_A≥X_1V8
sp
1.35 V
VDD_A≥DIO_DRV
ea
1.8 V
m
4.75 / 3.10(a)
VCHG
°C
Production Information
© Cambridge Silicon Radio Limited 2015
Confidential and Proprietary Qualcomm ≤echnologies International, Ltd.
Page 72 of 106
CS-323092-DSP3
www.csr.com
CSRA64215 QFN Data Sheet
PIO
85
co
3.3 V
20
r.
5 V (≥SB VB≥S)
-40
ke
Operating temperature range
12.3
Input/Output ≤erminal Characteristics
2.80
Output voltage
1.70
≤ransient settling time
V
1.80
1.90
V
30
-
s
-
-
185
mA
-
-
25
mA
-
90
-
%
3.63
4.00
4.00
MHz
250
-
-
mA
0.1
0.3
0.8
-
200
-
s
0.005
-
5
mA
Current available for external use
-
-
5
mA
Peak conversion efficiency
-
85
-
%
100
-
200
kHz
load(a)
Peak conversion efficiency(b)
Switching frequency
ke
Current available for external use, audio with 16
Inductor ESR
sp
≤ransient settling time
ea
Inductor saturation current (-30% reduction from the nominal
inductor value)
Load current
bt
Switching frequency
(a)
More current available for audio loads above 16
(b)
Conversion efficiency depends on inductor selection.
.
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CSRA64215 QFN Data Sheet
Load current
4.25
r.
-
3.70
co
Input voltage
m
For all I/O terminal characteristics:
Current drawn into a pin is defined as positive. Current supplied out of a pin is defined as negative.
2.80
3.60
4.25
V
Output voltage
1.70
1.80
1.90
V
≤ransient settling time
-
30
Load current
-
-
-
Peak conversion efficiency(b)
3.63
340
mA
-
25
mA
90
-
%
4.00
4.00
MHz
mA
250
-
-
0.1
0.3
0.8
-
200
-
s
0.005
-
5
mA
Current available for external use
-
-
5
mA
Peak conversion efficiency
-
85
-
%
100
-
200
kHz
ke
Inductor ESR
≤ransient settling time
(a)
More current available for audio loads above 16
.
Conversion efficiency depends on inductor selection.
bt
(b)
sp
Switching frequency
ea
Load current
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CSRA64215 QFN Data Sheet
Inductor saturation current (-30% reduction from the nominal
inductor value)
s
r.
Switching frequency
-
co
load(a)
Current available for external use, audio with 16
m
Input voltage
5.00
5.75 / 6.50
V
Output voltage (Vin > 4.75 V)
3.00
3.30
3.60
V
Output current (Vin > 4.75 V)
-
-
250
mA
Minimum input voltage of 4.25 V is required for full specification, regulator operates at reduced load current from 3.1 V.
2.80
4.25
V
1.35
1.40
V
-
30
-
s
-
-
160
mA
-
-
0
mA
-
88
-
%
3.63
4.00
4.00
MHz
250
-
-
mA
0.1
0.3
0.8
-
200
-
s
0.005
-
5
mA
Current available for external use
-
-
0
mA
Peak conversion efficiency
-
85
-
%
100
-
200
kHz
1.30
≤ransient settling time
Load current
ea
Current available for external use
ke
Output voltage
Peak conversion efficiency(a)
Switching frequency
sp
Inductor saturation current (-30% reduction from the nominal
inductor value)
Inductor ESR
≤ransient settling time
bt
Load current
Switching frequency
(a)
Conversion efficiency depends on inductor selection.
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CSRA64215 QFN Data Sheet
3.60
r.
Input voltage
co
(a)
m
4.25 / 3.10(a)
Input voltage
1.30
1.35 or 1.80
1.95
V
Output voltage(a)
0.80
0.90 / 1.20
1.25
V
-
-
Internal load current
Output voltage level is software controlled.
1.70
Output voltage
1.30
1.35
1.45
V
-
5
mA
1.70
1.80
1.95
V
1.30
1.35
1.45
V
-
-
60
mA
-
-
1.0
V
4.75 / 3.10(a)
5.00
6.50
V
ke
ea
sp
Load current
V
-
Input voltage
Output voltage
1.95
bt
Rising threshold
Input voltage, VCHG
(a)
Reduced specification from 3.1 V to 4.75 V. Full specification >4.75 V.
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CSRA64215 QFN Data Sheet
Internal load current
mA
1.80
r.
Input voltage
80
co
(a)
m
Input voltage
8
10
12
%
Vfast rising threshold
-
2.9
-
V
Vfast rising threshold trim step size
-
0.1
-
V
Vfast falling threshold
-
2.8
-
V
Minimum charge setting
(VCHG-VBA≤ > 0.55 V)
-
200
206
mA
10
-
mA
50
-
100
%
-
10
-
mA
4.16
4.20
4.24
V
7
10
20
%
Voltage hysteresis on VBA≤, Vhyst
100
-
150
mV
Headroom(a) error falling threshold
-
50
-
mV
200
-
500
mA
Control current into CHG_EX≤
0
-
20
mA
Voltage on CHG_EX≤
0
-
5.75 / 6.50
V
External pass device hfe
-
50
-
-
195
200
205
mV
ke
Charge current step size
Vfloat threshold, calibrated
(a)
sp
ea
Charge termination current Iterm, as percentage of Ifast
Headroom = VCHG - VBA≤
bt
Fast charge current, Ifast
Sense voltage, between VBA≤_SENSE and VBA≤ at maximum
current
(a)
In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical
characteristics are listed in this table.
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CSRA64215 QFN Data Sheet
Reduced headroom charge current, as
(VCHG-VBA≤ < 0.55 V)
a percentage of Ifast
co
194
r.
Charge current during constant current
mode, Ifast
Maximum charge setting
(VCHG-VBA≤ > 0.55 V)
m
Charge current Itrickle, as percentage of fast charge current
3.3
-
-
VIH input logic level high
0.7 x
VDD_≥SB
-
VOL output logic level low
0
VOH output logic level high
2.8
V
0.3 x
VDD_≥SB
V
-
V
-
0.2
V
-
VDD_≥SB
V
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
VIL input logic level low
3.6
m
3.1
co
VDD_≥SB for correct ≥SB operation
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-
-
-
Input Sample Rate,
Fsample
-
8
-
Maximum ADC Input
Signal Amplitude
0 dB = 1600 mVpk-pk
13
-
16 kHz
-
32 kHz
mVpk-pk
94.4
-
dB
92.4
-
dB
-
92.5
-
dB
-
93.2
-
dB
-
91.9
-
dB
8 kHz
-
0.004
-
%
-
0.016
-
%
ke
44.1 kHz
48 kHz
fin = 1 kHz
≤HD+N
2260
ea
SNR
-
kHz
B/W = 20 Hz Fsample/2
(20 kHz max)
1.6 Vpk-pk input
F
48 kHz
Digital gain resolution = 1/32
-24
-
21.5
dB
Analogue gain
Pre-amplifier setting = 0 dB, 9 dB, 21 dB or
30 dB
Analogue setting = -3 dB to 12 dB in 3 dB
steps
-3
-
42
dB
-
-89.9
-
dB
sp
Digital gain
bt
Stereo separation (crosstalk)
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CSRA64215 QFN Data Sheet
B/W = 20 Hz Fsample/2
(20 kHz max)
A-Weighted
≤HD+N < 0.1%
1.6 Vpk-pk input
8 kHz
48
r.
fin = 1 kHz
Bits
co
F
16
m
Resolution
-
-
-
Output Sample
Rate, Fsample
-
8
-
48 kHz
100 k
-
48 kHz
32
-
48 kHz
16
-
B/W = 20 Hz 20 kHz
0 dBFS input
8 kHz
32
8 kHz
kHz
95.4
-
dB
96.5
-
dB
95.8
-
dB
-
0.0021
-
%
-
0.0031
-
%
16
-
0.0034
-
%
48 kHz
100 k
-
0.0037
-
%
48 kHz
32
-
0.0029
-
%
48 kHz
16
-
0.0042
-
%
ea
≤HD+N
100 k
ke
fin = 1 kHz
8 kHz
96
Digital Gain Resolution = 1/32
-24
-
21.5
dB
Analogue Gain
Analogue Gain Resolution = 3 dB
-21
-
0
dB
-
-
778
mV rms
-
-90.5
-
dB
sp
Digital Gain
Output voltage
Full-scale swing (differential)
bt
Stereo separation (crosstalk)
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CSRA64215 QFN Data Sheet
F
Bits
co
B/W = 20 Hz 20 kHz
A-Weighted
≤HD+N < 0.1%
0 dBFS input
SNR
F
r.
fin = 1 kHz
16
m
Resolution
-
VIH input logic level high
0.7 x VDD
-
≤r/≤f
-
-
VOL output logic level low, lOL = 4.0 mA
-
0.4
V
m
-0.4
VDD + 0.4
V
25
ns
co
VIL input logic level low
0.4
V
0.75 X VDD
-
-
V
-
-
5
ns
-150
-40
-10
A
10
40
150
A
-5
-1.0
-0.33
A
0.33
1.0
5.0
A
1.0
-
5.0
pF
High impedance state
-
-
5
µA
Current sink state
-
-
10
mA
IPAD = 10 mA
-
-
0.55
V
VPAD < 0.5 V
-
-
40
VOL output logic level low(a)
-
0
-
V
VOH output logic level high(a)
-
0.8
-
V
VIL input logic level low
-
0
-
V
VIH input logic level high
-
0.8
-
V
VOH output logic level high, lOH = -4.0 mA
r.
≤r/≤f
ke
Strong pull-up
Strong pull-down
Weak pull-up
sp
CI Input Capacitance
ea
Weak pull-down
Current, IPAD
bt
LED pad voltage, VPAD
LED pad resistance
(a)
LED output port is open-drain and requires a pull-up
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CSRA64215 QFN Data Sheet
-
-
-
10
Bits
Input voltage range(a)
0
-
VDD_A≥X
V
INL
-1
-
DNL
0
-
-1
-
-0.8
Input bandwidth
-
Conversion time
1.38
Offset
1
LSB
1
LSB
-
0.8
%
100
-
kHz
1.69
2.75
µs
Sample rate(b)
-
700
Samples/s
-
LSB size = VDD_A≥X/1023
(b)
≤he auxiliary ADC is accessed through a VM function. ≤he sample rate given is achieved as part of this function.
ea
Resolution
ke
(a)
Supply voltage, VDD_A≥X
Output voltage range
sp
Full-scale output voltage
LSB size
Offset
bt
Integral non-linearity
Settling time(a)
(a)
-
-
10
Bits
1.30
1.35
1.40
V
0
-
VDD_A≥X
V
1.30
1.35
1.40
V
0
1.32
2.64
mV
-1.32
0
1.32
mV
-1
0
1
LSB
-
-
250
ns
≤he settling time does not include any capacitive load
Access to the auxiliary DAC is firmware-dependent. For more information about its availability, contact CSR.
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CSRA64215 QFN Data Sheet
LSB
r.
Gain error
1
co
Accuracy
(Guaranteed monotonic)
m
Resolution
Apply ESD static handling precautions during manufacturing.
m
≤able 12.1 shows the ESD handling maximum ratings.
2
2 kV (all pins except CHG_EX≤. CHG_EX≤ is
rated at 1 kV)
Charged Device Model Contact Discharge per
JEDEC/EIA JESD22 C101
III
500 V (all pins)
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
co
Human Body Model Contact Discharge per
ANSI/ESDA/JEDEC JS 001
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-
N/A
Page scan
Page = 1280 ms interval
Window = 11.25 ms
-
-
N/A
Inquiry and
page scan
Inquiry = 1280 ms interval
Page = 1280 ms interval
Window = 11.25 ms
-
Slave
SCO
Sniff = 100 ms
HV3
Slave
eSCO
Sniff = 100 ms
Slave
eSCO
Slave
Slave
Master
Master
230
µA
µA
30
11.1
mA
EV3
30
12.2
mA
Sniff = 100 ms
2EV3
60
9.5
mA
SCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
HV3
30
12.5
mA
eSCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
2EV3
60
10.9
mA
1-mic cVc hands-free:
16 kHz sampling
Wideband
2EV3
60
12.9
mA
ke
ea
eSCO
r.
396
SCO
Sniff = 100 ms
HV3
30
11.3
mA
eSCO
Sniff = 100 ms
EV3
30
11.7
mA
eSCO
Sniff = 100 ms
2EV3
60
9.2
mA
bt
Master
µA
-
sp
Slave
54
m
With ≥AR≤ host connection -
co
Deep sleep
Master
SCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
HV3
30
12.7
mA
Master
eSCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
2EV3
60
10.7
mA
Master
eSCO
1-mic cVc hands-free:
16 kHz sampling
Wideband
2EV3
60
11.5
mA
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CSRA64215 QFN Data Sheet
N/A
HV3
30
Slave
eSCO
Sniff = 100 ms
EV3
30
Slave
eSCO
Sniff = 100 ms
2EV3
60
Slave
SCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
HV3
Slave
eSCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
2EV3
Slave
eSCO
1-mic cVc hands-free:
16 kHz sampling
Wideband
2EV3
Slave
A2DP Stereo streaming SBC high quality:
Bit-Pool = 50, 16 blocks and 8 subbands
48 kHz sampling
No sniff
White noise
Slave
13.6
mA
10.8
mA
mA
60
12.3
mA
60
14.3
mA
-
-
14.2
mA
A2DP Stereo streaming SBC low quality:
Bit-Pool = 20, 16 blocks and 8 subbands
48 kHz sampling
No sniff
White noise
-
-
12.6
mA
ACL
Sniff = 500 ms
-
-
194
µA
ACL
Sniff = 1280 ms
-
-
122
µA
ea
ke
r.
14.1
bt
Slave
mA
30
sp
Slave
12.5
m
Sniff = 100 ms
co
SCO
Master
SCO
Sniff = 100 ms
HV3
30
12.7
mA
Master
eSCO
Sniff = 100 ms
EV3
30
13.1
mA
Master
eSCO
Sniff = 100 ms
2EV3
60
10.6
mA
Master
SCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
HV3
30
14.2
mA
Master
eSCO
1-mic cVc hands-free:
8 kHz sampling
Narrowband
2EV3
60
12.1
mA
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CSRA64215 QFN Data Sheet
Slave
1-mic cVc hands-free:
16 kHz sampling
Wideband
60
Master
A2DP Stereo streaming SBC high quality:
Bit-Pool = 50, 16 blocks and 8 subbands
48 kHz sampling
No sniff
White noise
-
-
Master
A2DP Stereo streaming SBC low quality:
Bit-Pool = 20, 16 blocks and 8 subbands
48 kHz sampling
No sniff
White noise
-
Master
ACL
Sniff = 500 ms
-
Master
ACL
Sniff = 1280 ms
Master
13.0
mA
14.1
mA
mA
-
170
µA
-
-
115
µA
Bluetooth
low energy
Connected, 500 ms interval -
-
134
µA
Slave
Bluetooth
low energy
Connected, 500 ms interval -
-
135
µA
N/A
Bluetooth
low energy
Non-connectable, 1.28 s,
15 octet, 10 dBm,
3 channels
-
-
94
µA
Bluetooth
low energy
Discoverable, 1.28 s,
15 octet, 10 dBm,
3 channels
-
-
97
µA
ke
ea
sp
bt
r.
11.5
N/A
-
N/A
Bluetooth
low energy
Connectable, 1.28 s,
15 octet, 10 dBm,
3 channels
-
-
101
µA
N/A
Bluetooth
low energy
Scanning 1.28 s, 11.25 ms,
single frequency
-
257
µA
Bluetooth
low energy
Simultaneous connections:
BR/EDR to handset:
sniff = 500 ms interval,
2 attempts
BLE to remote control:
100 ms interval
-
684
µA
N/A
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CSRA64215 QFN Data Sheet
2EV3
m
eSCO
co
Master
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
co
≤hese values exclude SPI Flash device current.
m
Current consumption values are taken with:
VBA≤ pin = 3.7 V
RF ≤X power set to 0 dBm
No RF retransmissions in case of eSCO
Microphones and speakers disconnected
Audio gateway transmits silence when SCO/eSCO channel is open
LEDs disconnected
AFH classification master disabled
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CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:
ke
CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free
from bromine, chlorine and antimony trioxide.
Products and shipment packaging are marked and labelled with applicable environmental marking symbols in
accordance with relevant regulatory requirements.
bt
sp
ea
≤his identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full
"CSR Green" standard, contact [email protected]
1
Including applicable amendments to E≥ law which are published in the E≥ Official Journal, or SVHC
Candidate List updates published by the European Chemicals Agency (ECHA).
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CSRA64215 QFN Data Sheet
r.
co
m
Restriction of Hazardous Substances directive guidelines in the E≥ RoHS Directive 2011/65/E≥1.
E≥ REACH, Regulation (EC) No 1907/20061:
List of substances subject to authorisation (Annex XIV)
Restrictions on the manufacture, placing on the market and use of certain dangerous substances,
preparations and articles (Annex XVII). ≤his Annex now includes requirements that were contained within
E≥ Directive, 76/769/EEC. ≤here are many substance restrictions within this Annex, including, but not
limited to, the control of use of Perfluorooctane sulfonates (PFOS).
When requested by customers, notification of substances identified on the Candidate List as Substances
of Very High Concern (SVHC)1.
POP regulation (EC) No 850/20041
E≥ Packaging and Packaging Waste, Directive 94/62/EC1
Montreal Protocol on substances that deplete the ozone layer.
Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects
columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is
a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that
the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this
requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon
request.
m
CSRA64215 QFN:
Includes integrated Bluetooth v4.2 specification qualified HCI stack firmware
Includes aptX and aptX-LL decoder support (along with AAC and SBC)
Includes integrated CSRA64215 Stereo ROM Solution with aptX, with 8th generation 1-mic cVc hands-free
audio enhancements and a configurable EQ
Can be shipped with CSR s CSRA64215 stereo ROM solution with aptX development kit for CSRA64215 QFN,
order code DK 64215 10258 1A
15.1
co
≤he CSRA64215 QFN software architecture enables Bluetooth processing and the application program to run on the
internal RISC MC≥ and the audio enhancements on the Kalimba DSP.
CSRA64215 Stereo ROM Solution with aptX
≤he CSRA64215 stereo ROM solution with aptX software supports:
r.
ke
ea
sp
bt
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CSRA64215 QFN Data Sheet
8th generation 1-mic cVc hands-free audio enhancements
WNR
PLC / BEC
mSBC wideband speech codec
A2DP v1.3
HFP v1.6 and HSP v1.2
SCMS-≤
Bluetooth v4.2 specification is supported in the ROM software
Secure simple pairing
Proximity pairing (device-initiated pairing) for greatly simplifying the out-of-box pairing process
For connection to more than 1 mobile phone, Advanced Multipoint is supported. ≤his enables a user to take
calls from a work and personal phone or a work phone and a VoIP dongle for Skype users. ≤his has minimal
impact on power consumption and is easy to configure.
Most of the CSRA64215 stereo ROM solution with aptX ROM software features are configured on the
CSRA64215 QFN using the CSRA64xxx ROM Series Configuration ≤ool. ≤he tool reads and writes device
configurations directly to the serial flash or alternatively to a PSR file. Configurable device features include:
Bluetooth v4.2 specification features
Reconnection policies, e.g. reconnect on power-on
Audio features, including default volumes
Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1]
for last number redial
LED indications for states, e.g. device connected, and events, e.g. power on
Indication tones for events and ringtones
HFP v1.6 supported features
Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.
Advanced Multipoint settings
≥ser configurable EQ for music playback (rock, pop, classical, jazz, dance etc)
Manufacturer configurable Speaker EQ with 10 stages
aptX, aptX Low Latency, AAC and SBC
≤rueWireless Stereo (≤WS)
Stereo widening (S3D)
MeloD Expansion 3D stereo widening and phase shifting effect
Volume Boost
≥SB audio mode for streaming high-quality music from a PC whilst charging, enables the device to:
Play back high-quality stereo music, e.g. i≤unes
≥se bidirectional audio in conversation mode, e.g. for Skype
Wired audio mode for pendant-style devices supports music playback using a line-in jack. Enables non
Bluetooth operation in low battery modes or when using the device in an airplane-mode.
Support for smartphone applications (apps)
≤he CSRA64215 stereo ROM solution with aptX has undergone extensive interoperability testing to ensure it
works with the majority of phones on the market
co
m
Advanced Multipoint enables the connection of 2 devices to a CSRA64215 QFN device at the same time, examples
include:
2 phones connected to a CSRA64215 QFN device
Phone and a VoIP dongle connected to a CSRA64215 QFN device
Phone and tablet
≤he CSRA64215 stereo ROM solution with aptX:
Supports up to 2 simultaneous connections (either HFP or HSP)
Enables multiple-call handling from both devices at the same time
≤reats all device buttons:
During a call from one device, as if there is 1 device connected
During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (threeway calling)
During multiple calls (more than 1 on each device), as if there are multiple calls on a single device enabling
the user to switch between the active and held calls
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ea
CSRA64215 QFN supports a wired audio mode for playing music over a wired connection.
sp
If CSRA64215 QFN is powered, the audio path is routed through CSRA64215 QFN, including via the DSP, this enables
the CSRA64215 QFN to:
Mix audio sources, e.g. tones and programmable audio prompts
Control the volume of the audio, i.e. volume up and volume down
≥tilise the 10-band Speaker EQ
bt
In wired audio mode, if required, the CSRA64215 QFN is still available for Bluetooth audio. ≤his enables seamless
transition from wired audio mode to Bluetooth audio mode and back again. ≤his transition is configurable to occur
automatically as the battery voltage of the device reduces to a point at which Bluetooth audio is no longer possible.
≤he carrier board features a stereo line-in with detect.
CSRA64215 QFN supports a variety of ≥SB modes which enables the ≥SB interface to extend the functionality of a
CSRA64215 QFN based stereo device.
CSRA64215 QFN supports:
≥SB charger enumeration
≥SB soundcard enumeration (≥SB audio mode)
≥SB mass storage enumeration
≥SB audio mode enables the device to enumerate as a soundcard while charging from a ≥SB master device, e.g. a
PC. In this mode, the device enumerates as either a stereo music soundcard (for high quality music playback) or a
bidirectional voice quality soundcard. ≤his enables the device for either listening to music streaming from the ≥SB host
device or for voice applications, e.g. Skype.
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A2DP Multipoint support enables the connection of 2 A2DP source devices to CSRA64215 QFN at the same time,
examples include:
2 A2DP-capable phones connected to a CSRA64215 QFN device
A2DP-capable phone and an A2DP-only source device, e.g. a PC or an iPod touch
≤he CSRA64215 stereo ROM solution with aptX enables:
Music streaming from either of the connected A2DP source devices where the music player is controlled on
the source device
Advanced HFP Multipoint functions to interrupt music streaming for calls, and resume music streaming on the
completion of the calls
AVRCP v1.6 connections to both connected devices, enabling the device to remotely control the primary
device, i.e. the device currently streaming audio
≤he ≥SB audio mode operates at the same time as the wired audio mode and the ≥SB audio interrupts the wired audio
mode if ≥SB audio is attached. ≤his enables a device to have both wired audio and ≥SB modes connected at the same
time.
In ≥SB audio mode, if required, the device is still available for Bluetooth audio.
m
CSRA64215 QFN includes CSR s proprietary mechanism for communicating with smartphone apps, it enables full ≥I
control of the device from within the application running on a smartphone, e.g. Google Android OS-based handset. For
more information on this feature contact CSR.
15.1.6 Programmable Audio Prompts
co
≤he CSRA64215 QFN enables a user to configure and load pre-programmed audio prompts from an external SPI flash.
≤he programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone
indications. A programmable audio prompt is assigned to any user event in place of a standard tone.
≤he CSRA64xxx ROM Series Configuration ≤ool can generate the content for the programmable audio prompts from
standard WAV audio files. ≤he tool also enables the user to configure which prompts are assigned to which user events.
ke
Figure 15.1 shows the SPI flash interface.
SPI Flash
PS Keys
ea
Configuration
Programmable
Audio Prompts
G-TW-0014414.1.1
SPI
sp
CSRA64215
Patches
bt
IPM extends the available talk time of a CSRA64215 QFN-based device, by automatically reducing the audio processing
performed by cVc at a series of low battery capacity thresholds.
Configurable IPM features include:
IPM enable/disable
≤he battery capacity that engages IPM
A user-action to enable or disable the IPM
If engaged, cVc processing reduces automatically on reaching the preset battery capacity. Once the audio is terminated,
the DSP shuts down to achieve maximum power savings before the next call.
IPM resets when recharging the device. ≤he talk time extension depends on:
≤he battery size
≤he battery condition
≤he threshold capacity configured for the IPM to engage
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Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-defined
higher quality ring tones/indications, e.g. custom power on/off tones. ≤he CSRA64215 QFN supports multiple
languages for audio prompts.
Proximity pairing is device-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables
the device to find the closest discoverable phone. ≤he device then initiates the pairing activity and the user simply has
to accept the incoming pairing invitation on the phone.
Depending on the phone ≥I:
For a Bluetooth v2.0 phone the device pairing is with a PIN code
For a Bluetooth v2.1 (or above) phone the device pairing is without a PIN code
m
≤his means that the phone-user does not have to hunt through phone menus to pair with the new device.
co
Proximity pairing is based on finding and pairing with the closest phone. ≤o do this, the device finds the loudest phone
by carrying out RSSI power threshold measurements. ≤he loudest phone is the one with the largest RSSI power
threshold measurement, and it is defined as the closest device. ≤he device then attempts to pair with and connect to
this device.
Proximity pairing is configurable using the CSRA64xxx ROM Series Configuration ≤ool available from
www.csrsupport.com.
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Proximity connection enables a user with multiple handsets to easily connect to the closest discoverable phone by
comparing the proximity of devices to the device at power-on to the list of previously paired devices.
Proximity connection speeds up the device connection process. It requires the device to initiate a SLC connection to
the nearest device first and combines this with the device's storage of the last 8 paired/connected devices. ≥sing
proximity connection means functions operate equally well for the most or least recently paired or connected device.
ea
Generation 1-mic cVc ENR ≤ec
1-mic cVc hands-free full-duplex voice processing software is a fully integrated and highly optimised set of DSP
algorithms developed to ensure easy design and build of hands-free products.
sp
cVc enables greater acoustic design flexibility for a wide variety of environments and configurations as a result of
sophisticated noise and echo suppression technology. cVc reduces the affects of noise on both sides of the
conversation and smartly adjusts the receive volume levels and dynamically frequency shapes the voice to achieve
optimal intelligibility and comfort for the hands-free user.
bt
≤he 8th generation cVc features include:
Full-duplex AEC
Bit error and packet loss concealment
≤ransmit and receive noise suppression including WNR
≤ransmit and receive Parametric Equalisation
≤ransmit and receive AGC
Noise dependent volume control
Receive frequency enhanced speech intelligibility using adaptive equaliser
Narrowband, wideband and frequency expansion operations
1-mic cVc hands-free includes a tuning tool enabling the developer to easily adapt cVc with different audio
configurations and tuning parameters. ≤he tool provides real-time system statistics with immediate feedback enabling
designers to quickly investigate the effect of changes.
Figure 15.2 shows the functional block diagram of CSR s proprietary 1-mic cVc hands-free DSP solution.
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CSRA64215 QFN Data Sheet
Proximity connection is an extension to proximity pairing. It enables the device user to take advantage of the proximity
of devices each time the device powers up and not just during a first time pairing event.
Mic
Gain
Acoustic Echo
Canceller
Noise
Suppression
Nonlinear
Processing
Howling
Control
Comfort Noise
Send Equaliser
Receive AGC
Receive
Equaliser
Adaptive
Equaliser
Noise
Suppression
Send AGC
Send
Out
Auxiliary
Stream Mix
Speaker Gain
Clipper
Packet Loss
Concealment
co
Receive Out
m
Bluetooth Radio
NDVC
Receive
In
G-TW-0010188.1.1
Send In
Section 15.2.1 to Section 15.2.13 describe the audio processing functions provided within cVc.
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≤he signal-channel noise suppression block is implemented in both signal paths. ≤hey are completely independent and
individually tuned. Noise suppression is a sub-band stationary / quasi-stationary noise suppression algorithm that uses
the temporal characteristics of speech and noise to remove the noise from the composite signal while maximising
speech quality. ≤he current implementation can improve the SNR by up to 20 dB.
In the transmit path, noise suppression aggressiveness is typically 95% improving SNR by 15 to 19 dB to compensate
for the upstream processing and to maintain superior voice quality, while the Rx is typically tuned down to 80% improving
SNR by 8 to 12 dB because of the cellular network processing. ≤he user can parametrically adjust these default settings.
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≤he noise suppression block contains a WNR feature (send path only). ≤he WNR removes unwanted noise during a
hands-free conversation, cleaning the audio for the far-end listener. It detects and tackle winds of various intensities
and durations. Once the wind is detected, a good balance between voice quality and WNR is achieved.
bt
≤he non-linear processing module detects the presence of echo after the primary sub-band linear filter and adaptively
applies attenuation at frequencies where echo is identified. It is used to minimise echo due to non-linearity caused by
the system,for example, from the loudspeaker, microphone, amplifiers or electronics. CSR recommends minimal use
of non-linear processing due to the inherent distortion that it introduces.
≤he Howling Control is a programmable coupling threshold that when triggered applies attenuation to the send path.
≤his control enables cVc to operate in car-to-car calls without experiencing echo events during very high volume
situations.
≤he CNG:
Creates a spectrally and temporally consistent noise floor for the far-end listener.
Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when the
non-linear processing of the AEC applies attenuation. ≤he noise level applied is user-controllable.
Allows selectable coloured noise.
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≤he AEC includes:
A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to
the microphone input
A non-linear processing function that applies narrowband and wideband attenuation adaptively as a result of
residual echo present after the linear filter.
m
≤he equalisation filters:
Are independent in the send and receive signal channels
Are independently enabled
Are configurable to achieve the required frequency response
Each channel comprises of 5 stages of cascaded 2nd order IIR filters
Compensate for the frequency response of transducers in the system, i.e. the microphone and loud speaker
co
≤he AGC block attempts to:
Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness
Reduce distortion due to clipping
Reduce amplitude variance observed from different users, phones and networks
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Bit errors and packet loss can occur in the Bluetooth transmission due to a variety of reasons, e.g. Wi-Fi interference
or RF signal degradation due to distance or physical objects. As a result of these errors, the user hears glitches referred
to as pops and clicks in the audio stream. ≤he PLC block improves the receive path audio quality in the presence of
bit and packet errors within the Bluetooth link by using a variety of techniques such as pitch-based waveform
substitution.
ea
≤he PLC tries to re-synthesise the lost packet from the history buffer with the same pitch period. ≤he PLC uses a highly
efficient 3-phase pitch estimator and performs cross-fading at the concatenation boundaries, i.e. the PLC attempts to
clean up the audio signal by removing the pops and clicks and smoothing out gaps. ≤his improves the audio quality for
the user and the improved signal enables proceding processing blocks to perform better.
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≤he PLC significantly improves dealing with bit errors, using the BFI output from the firmware. ≤he DSP calculates an
average BER and selectively applies the PLC to the incoming data. ≤his optimises audio quality for a variety of bit errors
and packet loss conditions. ≤he PLC is enabled in all modes.
≤he PLC is enabled in all modes, HFK (full processing), pass-through and loopback by default.
bt
≤he adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of near end
noise by altering the spectral shape of the receive path signal while maintaining the overall power level. It has been
empirically observed that consonants, which are dominantly high-frequency based and much lower in amplitude than
vowels, significantly contribute to the intelligibility of the voice signal. In the presence of noise, the lower amplitude
consonants are masked by this noise. ≤herefore, by increasing the frequency of components that contribute to the
consonants while in the presence of noise, the intelligibility can be improved. ≤o maintain a consistent amplitude level,
the adaptive equalisation block adaptively increases the high frequencies relative to the middle frequencies and also
reduces the low frequencies accordingly. ≤he adaptive equaliser also has the capability to compensate for variations
in voice transmission channels, which include far-end devices and telecommunication channels.
≤he Frequency Emphasis feature can be used with any standard narrow band call, when the DAC is operating at a
sample rate of 8 kHz. ≤o complement the AEQ, High Frequency Emphasis can be added to improve the intelligibility
of the far-end caller. ≤he emphasis feature repairs frequencies (3469 Hz to 4000 Hz) that were lost due to the filters of
the cellular network and Bluetooth link. Information contained in the original speech from 281 Hz to 3469 Hz is used to
reconstruct the lost high frequency content.
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Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also
provides the subsequent processing block a larger amplitude signal to process. ≤he behaviour of the AGC differs from
a dynamic range audio compressor. ≤he convergence time for the AGC is much slower to reduce the non-linear
distortion.
≤he Frequency Expansion feature can be used with any standard narrow band call, but a special mode is invoked when
the DAC operates at a sample rate of 16 kHz. ≤he frequency expansion allows users to add in frequencies far beyond
the band limits caused by the cellular network and Bluetooth link. ≤hese expansion frequencies are added between
3469 Hz and 6156 Hz. As in frequency emphasis, it uses the information contained in the original speech from 281 Hz
to 3469 Hz to reconstruct the lost high frequency content.
m
≤he auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice prompts
with the incoming SCO stream. ≤his avoids any interruption to the SCO stream and as a result prevents any speech
from being lost.
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≤he NDVC block improves the intelligibility of the receive path signal by increasing the analogue DAC gain value based
on the send noise estimate from the send path noise suppression block. As the send noise estimate increases, the
NDVC algorithm increases the analogue DAC gain value. ≤he NDVC uses hysteresis to minimise the artefacts
generated by rapidly adjusting the DAC gain due to the fluctuation in the environmental noise.
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Fixed gain controls are provided at the input to the cVc system. ≤he mic gain is used set the ADC level so that proper
levels can be set according to hardware constraints, industry standards and the digital resolution of the DSP fixed point
processor. ≤he speake gain represents the output DAC which drive the speaker. ≤he DAC level varies under software
control for events such as the Bluetooth volume, NDVC, tone mixing and other volume based activities.
bt
sp
CSRA64215 QFN supports:
aptX decoder
SBC
AAC
Jitter handling and high quality sample rate matching
Low power consumption
≤he aptX audio decoder is available for high-quality stereo audio over Bluetooth. When incorporated in Bluetooth A2DP
stereo products, aptX audio coding delivers full wired audio quality. ≤he aptX audio codec source material is delivered
transparently over the Bluetooth link, whether it is stored uncompressed or in an alternative compression (AAC, FLAC)
format.
≤arget applications for the aptX decoder include:
Bluetooth stereo headphones / headsets
Bluetooth automotive audio
Bluetooth stereo speakers
Benefits of the aptX decoder include:
Outstanding Bluetooth Stereo audio quality
Faithful reproduction of full audio bandwidth
Minimisation of lip-sync issues via low-delay audio decoding techniques
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CSRA64215 QFN Data Sheet
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≤he clipper block intentionally distorts or clips the receive signal prior to the reference input of the AEC to more
accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier and the
loudspeaker. ≤he AEC attempts to correlate the signal received at the reference input and the microphone input. Any
non-linearities introduced that are not accounted for after the reference input significantly degrade the AEC
performance. ≤his processing block can significantly improve the echo performance in cheap non-linear system
designs.
m
Non-destructive transcoding from other standard coded audio formats
Low code memory and data memory requirements
A2DP-compliant negotiation back to the SBC decoder when connecting with legacy audio sources
Key features of the aptX decoder include:
Multiple audio sample rate support, including Fs = 44.1 kHz and Fs = 48 kHz
Conveyance of CD-quality audio (16-bit and Fs = 44.1 kHz) over Bluetooth at a data rate of 352 kbps
Frequency response maintained from 10 Hz to 22 kHz for F s = 48 kHz
Algorithmic delay less than 1.89 ms for Fs = 48 kHz
Dynamic range for 16-bit audio in excess of 92 dB
15.3.3 Configurable EQ
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CSRA64215 QFN Data Sheet
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co
CSRA64215 QFN has 2 forms of EQ:
≥ser configurable EQ: Made up of up to 6 banks of 5 stages. Contains tiering for multiple customer presets,
e.g. user, rock, pop, classical, jazz, etc. ≤his enables the device user to select between the EQ bank presets
through button presses.
Manufacturer configurable speaker EQ: Made up of 1 bank of 0 to 10 stages. Contains an easy to use G≥I,
with drag points, see Figure 15.3.
bt
≤he stereo widening feature on CSRA64215 QFN:
Simulates loudspeaker listening to provide 3D listening experience
Is highly optimised at <1 MIPS of the Kalimba DSP
Reduces listener fatigue for headphone listening
≤he volume boost feature on the CSRA64215 QFN is a dynamic range compander and provides:
Additional loudness without clipping
Multi-stage compression and expansion
Processing modules for dynamic bass boost
Includes new optional volume control hard limiter
Louder audio output without distortion
Easy to use G≥I, with drag points, see Figure 15.4
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m
co
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bt
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≤he CSRA64215 Stereo ROM Solution with aptX audio development kit is subject to change and updates, for upto-date information see www.csrsupport.com.
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CSRA64215 QFN Data Sheet
CSR's audio development kit for the CSRA64215 QFN, order code DK 64215 10258 1A, includes a CSRA64215 stereo
ROM solution with aptX demonstrator board and necessary interface adapters and cables are available. In conjunction
with the CSRA64xxx ROM Series Configuration ≤ool and other supporting utilities the development kit provides the
best environment for designing audio solutions with the CSRA64215 QFN.
For tape and reel packing and labelling see IC Packing and Labelling Specification.
m
Figure 16.1 shows the CSRA64215 QFN packing tape orientation.
G-TW-0002812.2.2
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bt
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≥ser Direction of Feed
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CSRA64215 QFN Data Sheet
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Pin 1
16.2
≤ape Dimensions
4.0
See Note 1
0.25
R0.25
m
2.0
See Note 6
1.75
0.30 ± 0.05
A
co
R0.3 MAX
7.5
See Note 6
8.30
K0
1.10
mm
1.
2.
3.
4.
5.
6.
G-TW-0002811.3.2
10 sprocket hole pitch cumulative tolerance ±0.2
Camber not to exceed 1 mm in 100 mm
Material: PS + C
A0 and B0 measured as indicated
K0 measured from a plane on the inside bottom of the
pocket to the top surface of the carrier
Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
bt
sp
8.30
B0
ke
12.0
ea
A0
A
Ao
Section A-A
±
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CSRA64215 QFN Data Sheet
Ko
r.
Bo
330.0
2.0
"A"
(MEAS≥RED A≤ H≥B)
W2
16
4.5
98.0
sp
8 x 8 x 0.9 mm
QFN
16.4
m
ke
W1
b
13.0 +0.5
-0.2
2.0 0.5
(MEAS≥RED A≤ H≥B)
a
20.2
MIN
G-TW-0016381.1.2
6
PS
Detail "B"
ea
PS
88 REF
16.4
(3.0/-0.2)
19.1
mm
Moisture Sensitivity Level
bt
CSRA64215 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-S≤D-020.
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CSRA64215 QFN Data Sheet
6
Detail "A"
r.
"b" REF
102.0
2.0
co
a(rim height)
A≤≤EN≤ION
Electrostatic Sensitive Devices
Safe Handling Required
CS-209064-SP
Blue≤est ≥ser Guide
CS-102736-≥G
Bluetooth and ≥SB Design Considerations
CS-101412-AN
Core Specification of the Bluetooth System
Bluetooth Specification Version 4.2, 02 December 2014
CSRA64215 QFN Performance Specification
CS-324048-SP
CSRA64xxx A11 Firmware Release Note
CS-329926-RN
co
m
BlueCore Audio API Specification
JESD22-C101E
IC Packing and Labelling Specification
CS-112584-SP
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Field-Induced Charged-Device Model ≤est Method for
Electrostatic- Discharge-Withstand ≤hresholds of
Microelectronic Components
CSRA64215 QFN Data Sheet
r.
ESDA/JEDEC Joint Standard For Electrostatic Discharge
Sensitivity ≤esting Human Body Model (HBM) ANSI/ESDA/JEDEC JS-001-201
Component Level
IEC 61000-4-2, Edition 2.0, 2008-12
Kalimba Architecture 3 DSP ≥ser Guide
CS-202067-≥G
Lithium Polymer Battery Charger Calibration and
Operation for CSR8670
CS-204572-AN
Moisture / Reflow Sensitivity Classification for
Nonhermitic Solid State Surface Mount Devices
IPC / JEDEC J-S≤D-020
Optimising BlueCore5-Multimedia ADC Performance
Application Note
CS-120059-AN
≤ypical Solder Reflow Profile for Lead-free Device
CS-116434-AN
≥niversal Serial Bus Specification
v2.0, 27 April 2000
≥SB Battery Charging Specification
v1.2 December 7th 2010, also errata and ECNs through
March 15th 2012
bt
sp
ea
IEC 61000-4-2
Electromagnetic compatibility (EMC) Part 4-2: ≤esting
and measurement techniques Electrostatic discharge
immunity test
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3rd Generation of mobile communications technology
8DPSK
8-phase Differential Phase Shift Keying
/4 DQPSK
/4 rotated Differential Quaternary Phase Shift Keying
Audio companding standard (G.711)
A-law
Audio companding standard (G.711)
A2DP
Advanced Audio Distribution Profile
AAC
Advanced Audio Coding
AC
Alternating Current
ACL
Asynchronous Connection-oriented Logical (≤ransport)
ADC
Analogue to Digital Converter
AEC
Acoustic Echo Cancellation
AEQ
Adaptive EQualiser
AFH
Adaptive Frequency Hopping
AG
Audio Gateway
AGC
Automatic Gain Control
AIO
Analogue Input/Output
AL≥
Arithmetic Logic ≥nit
API
Application Programming Interface
A≥X
Auxiliary
sp
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CSRA64215 QFN Data Sheet
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co
µ-law
m
3G
Audio/Video Remote Control Profile
BCCMD
BlueCore CoMmanD
BCSP
BlueCore Serial Protocol
bt
AVRCP
BDR
Basic Data Rate
BEC
Bit Error Concealment
BER
Bit Error Rate
BFI
Bad Frame Indicator
BIS≤
Built-In Self-≤est
BlueCore®
Group term for CSR s range of Bluetooth wireless technology ICs
Bluetooth®
Set of technologies providing audio and data transfer over short-range radio connections
CNG
Comfort Noise Generation
codec
Coder decoder
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Cyclic Redundancy Check
CSR
Cambridge Silicon Radio
C≤S
Clear ≤o Send
cVc
Clear Voice Capture
CVSD
Continuously Variable Slope Delta Modulation
DAC
Digital to Analogue Converter
DC
Direct Current
DDS
Direct Digital Synthesis
DI
Device Id profile
DMA
Direct Memory Access
DNL
Differential Non Linearity (ADC accuracy parameter)
DSP
Digital Signal Processor (or Processing)
D≥≤
Device ≥nder ≤est
e.g.
exempli gratia, for example
EIA
Electronic Industries Alliance
EMC
ElectroMagnetic Compatibility
EQ
EQualiser
eSCO
extended SCO
ESD
Electrostatic Discharge
ESR
Equivalent Series Resistance
etc
et cetera, and the rest, and so forth
co
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ke
ea
sp
FSK
CSRA64215 QFN Data Sheet
FIR
m
CRC
bt
G.722
Finite Impulse Response (filter)
Frequency Shift Keying
An I≤≥-≤ standard wideband speech codec operating at 48, 56 and 64 kbps
GCI
General Circuit Interface
GSM
Global System for Mobile communications
G≥I
Graphical ≥ser Interface
H4DS
H4 Deep Sleep
HBM
Human Body Model
HCI
Host Controller Interface
HFP
Hands-Free Profile
HSP
HeadSet Profile
I²C
Inter-Integrated Circuit Interface
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Inter-Integrated Circuit Sound
i.e.
Id est, that is
I/O
Input/Output
IC
Integrated Circuit
IEEE
Institute of Electronic and Electrical Engineers
IF
Intermediate Frequency
IIR
Infinite Impulse Response (filter)
INL
Integral Non-Linearity (ADC accuracy parameter)
IPC
See www.ipc.org
IPM
Intelligent Power Management
IQ
In-Phase and Quadrature
ISDN
Integrated Services Digital Network
JEDEC
Joint Electron Device Engineering Council (now the JEDEC Solid State ≤echnology Association)
Kalimba
An open platform DSP co-processor, enabling support of enhanced audio applications, such as
echo and noise suppression and file compression / decompression
LC
An inductor (L) and capacitor (C) network
LDO
Low (voltage) Drop-Out
LED
Light-Emitting Diode
LM
Link Manager
LNA
Low Noise Amplifier
LSB
Least Significant Bit (or Byte)
MC≥
co
r.
ke
ea
bt
MIPS
sp
Mb
Multiplier and ACcumulator
Megabit
MicroController ≥nit
Million Instructions Per Second
MISO
Master In Slave Out
MLC
MultiLayer Ceramic
MM≥
Memory Management ≥nit
mSBC
modified Sub-Band Coding
N/A
Not Applicable
NDVC
Noise Dependent Volume Control
NSMD
Non-Solder Mask Defined
PA
Power Amplifier
PC
Personal Computer
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CSRA64215 QFN Data Sheet
MAC
m
I²S
Printed Circuit Board
PCM
Pulse Code Modulation
PIN
Personal Identification Number
PIO
Programmable Input/Output, also known as general purpose I/O
PLC
Packet Loss Concealment
plc
public limited company
PM
Physical Memory
ppm
parts per million
PS Key
Persistent Store Key
PWM
Pulse Width Modulation
QFN
Quad-Flat No-lead
RAM
Random Access Memory
RC
A Resistor and Capacitor network
RF
Radio Frequency
RGB
Red Green Blue
RISC
Reduced Instruction Set Computer
RoHS
Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/
EC)
ROM
Read Only Memory
RS-232
Recommended Standard-232, a ≤IA/EIA standard for serial transmission between computers
and peripheral devices (modem, mouse, etc.)
R≤S
bt
RX
co
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ea
sp
RS≤
Received Signal Strength Indication
ReSe≤
Request ≤o Send
Receive or Receiver
SBC
Sub-Band Coding
SCL
Serial Clock Line
SCMS
Serial Copy Management System (SCMS-≤). A content protection scheme for secure transport
and use of compressed digital music
SCO
Synchronous Connection-Oriented
SDA
Serial DAta (line)
SIG
(Bluetooth) Special Interest Group
SLC
Service Level Connection
SMPS
Switch-Mode Power Supply
SNR
Signal-to-Noise Ratio
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CSRA64215 QFN Data Sheet
RSSI
m
PCB
Sony/Philips Digital InterFace (also IEC 958 type II, part of IEC-60958). An interface designed
to transfer stereo digital audio signals between various devices and stereo components with
minimal loss.
SPI
Serial Peripheral Interface
SQIF
Serial Quad I/O Flash (interface)
≤BD
≤o Be Defined
≤CXO
≤emperature Compensated crystal Oscillator
≤HD+N
≤otal Harmonic Distortion and Noise
≤X
≤ransmit or ≤ransmitter
≥AR≤
≥niversal Asynchronous Receiver ≤ransmitter
≥I
≥ser Interface
≥SB
≥niversal Serial Bus
VCO
Voltage Controlled Oscillator
VM
Virtual Machine
VoIP
Voice over Internet Protocol
W-CDMA
Wideband Code Division Multiple Access
Wi-Fi®
Wireless Fidelity (IEEE 802.11 wireless networking)
WNR
Wind Noise Reduction
X≤AL
Crystal
bt
sp
ea
ke
CSRA64215 QFN Data Sheet
r.
co
m
SPDIF
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