TLV320AIC3106-Q1 Low-Power Stereo Audio

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TLV320AIC3106-Q1
SLAS663C – AUGUST 2009 – REVISED JUNE 2016
TLV320AIC3106-Q1 Low-Power Stereo Audio Codec For Infotainment and Cluster
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C6
Stereo Audio DAC
– 102-dBA Signal-to-Noise Ratio
– 16-, 20-, 24-, or 32-Bit Data
– Supports Rates From 8 kHz to 96 kHz
– 3D, Bass, Treble, EQ, De-Emphasis Effects
– Flexible Power Saving Modes and
Performance are Available
Stereo Audio ADC
– 92-dBA Signal-to-Noise Ratio
– Supports Rates From 8 kHz to 96 kHz
– Digital Signal Processing and Noise Filtering
Available During Record
Ten Audio Input Pins
– Programmable in Single-Ended or Fully
Differential Configurations
– 3-State Capability for Floating Input
Configurations
Seven Audio Output Drivers
– Stereo Fully Differential or Single-Ended
Headphone Drivers
– Fully Differential Stereo Line Outputs
– Fully Differential Mono Output
Low Power: 15-mW Stereo 48-kHz Playback With
3.3-V Analog Supply
Ultralow-Power Mode with Passive Analog Bypass
Programmable I/O Analog Gains
Programmable PLL for Flexible Clock Generation
Control Bus Selectable SPI or I2C
Audio Serial Data Bus Supports I2S, Left/RightJustified, DSP, and TDM Modes
Power Supplies:
– Analog: 2.7 V to 3.6 V
– Digital Core: 1.65 V to 1.95 V
– Digital I/O: 1.1 V to 3.6 V
Cluster
Head Unit
Car Audio
Emergency Call (eCall)
Telematics Control Unit
3 Description
The TLV320AIC3106-Q1 is a low-power stereo audio
codec with stereo headphone amplifier, as well as
multiple inputs and outputs programmable in singleended or fully differential configurations. Extensive
register-based power control is included, enabling
stereo 48-kHz DAC playback as low as 15 mW from
a 3.3-V analog supply, making it ideal for car audio
applications in cluster and head unit systems.
The record path of the TLV320AIC3106-Q1 contains
integrated microphone bias, digitally controlled stereo
microphone preamplifier, and automatic gain control
(AGC), with mix and mux capability among the
multiple analog inputs. Programmable filters are
available during record which can remove audible
noise that can occur in unpredictable environments,
such as when an eCall system is activated. The
playback path includes mix and mux capability from
the stereo DAC and selected inputs, through
programmable volume controls, to the various
outputs.
Device Information(1)
PART NUMBER
PACKAGE
TLV320AIC3106-Q1 VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320AIC3106-Q1
SLAS663C – AUGUST 2009 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
6
8.1
8.2
8.3
8.4
8.5
8.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Switching Characteristics I2S/LJF/RJF In Master
Mode ........................................................................ 10
8.7 Switching Characteristics I2S/LJF/RJF In Slave
Mode ........................................................................ 10
8.8 Switching Characteristics DSP In Master Mode ..... 11
8.9 Switching Characteristics DSP In Slave Mode ....... 11
8.10 Typical Characteristics .......................................... 15
9
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
17
18
18
34
37
49
10 Application and Implementation........................ 90
10.1 Application Information.......................................... 90
10.2 Typical Application ................................................ 91
11 Power Supply Recommendations ..................... 93
12 Layout................................................................... 93
12.1 Layout Guidelines ................................................. 93
12.2 Layout Example .................................................... 94
13 Device and Documentation Support ................. 95
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
95
95
95
95
95
14 Mechanical, Packaging, And Orderable
Information ........................................................... 95
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2012) to Revision C
Page
•
Added Applications section, Device Information table, Device Comparison Table, Table of Contents, Pin
Configuration and Functions section, Specifications section, ESD Ratings table, Timing Requirements table,
Switching Characteristics table, Timing and Switching Diagrams, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information Table; see POA at the end of the datasheet .......................................................................... 1
•
Changed R to R/W for Bit D0 for Page 0, Registers 79, 86, and 93.................................................................................... 71
Changes from Revision A (January 2010) to Revision B
Page
•
Changed TA in Electrical Characteristics condition from 25°C to –40°C to 85°C................................................................... 7
•
Changed TA in Electrical Characteristics condition from 25°C to –40°C to 85°C................................................................... 8
•
Changed TA in Electrical Characteristics condition from 25°C to –40°C to 85°C................................................................... 9
•
Added 25°C to the THD Test Conditions in Electrical Characteristics table. ......................................................................... 9
•
Added 25°C to the DAC DIGITAL INTERPOLATION title in Electrical Characteristics table. ............................................... 9
•
Added 25°C to the DIGITAL I/O title in Electrical Characteristics table. ................................................................................ 9
•
Changed TA in Electrical Characteristics condition from 25°C to –40°C to 85°C................................................................. 10
2
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5 Description (Continued)
The TLV320AIC3106-Q1 contains four high-power output drivers as well as three fully differential output drivers.
The high-power output drivers are capable of driving a variety of load configurations, including up to four
channels of single-ended 16-Ω headphones using AC-coupling capacitors, or stereo 16-Ω headphones in a
capacitorless output configuration. These parameters enable the TLV320AIC3106-Q1 to act as an interface from
the MCU to the speaker amplifiers, such as the TPA3111D1-Q1, in various audio applications in infotainment and
clusters.
The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering
in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz,
44.1‑kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is
preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level
microphone inputs. The TLV320AIC3106-Q1 provides an extremely high range of programmability for both attack
(8 ms to 1408 ms) and for decay (0.05 s to 22.4 s). This extended AGC range allows the AGC to be tuned for
many types of applications.
The serial control bus supports SPI or I2C protocols, while the serial audio data bus is programmable for I2S,
left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and
support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with
special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system
clocks.
The TLV320AIC3106-Q1 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to
1.95 V, and a digital I/O supply of 1.1 V to 3.6 V. The device is available in the 7-mm × 7-mm, 48-lead VQFN
(RGZ) package.
6 Device Comparison Table
DEVICE NAME
DIFFERENCES
TLV320AIC3104-Q1
6 inputs
6 outputs
TLV320AIC3106-Q1
10 inputs
7 outputs
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7 Pin Configuration and Functions
MFP3
MFP2
MFP1
MFP0
IOVDD
SELECT
DVSS
DOUT
DIN
WCLK
BCLK
MCLK
48
47
46
45
44
43
42
41
40
39
38
37
RGZ Package
48-Pin VQFN
Top View
SCL
1
36
DVDD
GPIO1
SDA
2
35
LINE1LP
3
34
GPIO2
LINE1LM
4
33
RESET
24
DRVDD
AVDD_DAC
23
25
HPROUT
12
22
MICDET
HPRCOM
AVSS_DAC
21
26
20
11
DRVSS
MONO_LOP
MIC3L
DRVSS
27
19
10
HPLCOM
MONO_LOM
LINE2RM
18
LEFT_LOP
28
HPLOUT
29
9
17
8
LINE2RP
DRVDD
LINE2LM
16
LEFT_LOM
DRVDD
30
15
7
AVSS_ADC
RIGHT_LOP
LINE2LP
14
RIGHT_LOM
31
13
32
6
MIC3R
5
MICBIAS
LINE1RP
LINE1RM
Not to scale
Solder the VQFN thermal pad to the ground plane (DRVSS).
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AVDD_DAC
25
I
Analog DAC voltage supply, 2.7 V to 3.6 V
AVSS_ADC
15
I
Analog ADC ground supply, 0 V
AVSS_DAC
26
I
Analog DAC ground supply, 0 V
BCLK
38
I/O
DIN
40
i
Audio serial data bus data input
DOUT
41
O
Audio serial data bus data output
DRVDD
16,17
I
ADC analog and output driver voltage supply, 2.7 V to 3.6 V
DRVDD
24
I
ADC analog and output driver voltage supply, 2.7 V to 3.6 V
DRVSS
20, 21
I
Analog output driver ground supply, 0 V
DVDD
36
I
Digital core voltage supply, 1.65 V to 1.95 V
DVSS
42
I
Digital core and I/O ground supply, 0 V
GPIO1
35
I/O
General-purpose I/O 1: input and output, PLL, clock mux output, short circuit interrupt, AGC noise flag, or
digital microphone clock audio serial data bus word clock
GPIO2
34
I/O
General-purpose I/O 2: input and output, digital microphone data input, PLL clock input, or audio serial
data bus bit clock
HPLOUT
18
O
High-power output driver (left+)
HPLCOM
19
O
High-power output driver (left– or multifunctional)
HPRCOM
22
O
High-power output driver (right– or multifunctional)
HPROUT
23
O
High-power output driver (right+)
4
Audio serial data bus bit clock (I/O)
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
IOVDD
44
I
I/O voltage supply, 1.1 V to 3.6 V
LEFT_LOM
30
O
Left line output (–)
LEFT_LOP
29
O
Left line output (+)
LINE1LM
4
I
MIC1 or Line1 analog input (left– or multifunction)
LINE1LP
3
I
MIC1 or Line1 analog input (left+ or multifunction)
LINE1RM
6
I
MIC1 or Line1 analog input (right– or multifunction)
LINE1RP
5
I
MIC1 or Line1 analog input (right+ or multifunction)
LINE2LM
8
I
MIC2 or Line2 analog input (left– or multifunction)
LINE2LP
7
I
MIC2 or Line2 analog input (left+ or multifunction)
LINE2RM
10
I
MIC2 or Line2 analog input (right– or multifunction)
LINE2RP
9
I
MIC2 or Line2 analog input (right+ or multifunction)
MCLK
37
I
Master clock input
MIC3L
11
I
MIC3 input (left or multifunction)
MIC3R
14
I
MIC3 input (right or multifunction)
MICBIAS
13
O
Microphone bias voltage output
MICDET
12
I
Microphone detect
MFP0
45
I/O
Multifunction pin 0. SPI chip select, GPI, or I2C address pin #0
MFP1
46
I/O
Multifunction pin 1. SPI serial clock, GPI, or I2C address pin #1S
MFP2
47
I/O
Multifunction pin 2. SPI MISO slave serial data output or GPIO
MFP3
48
I/O
Multifunction pin 3. SPI MOSI slave serial data input, GPI, or audio serial data bus data input
MONO_LOM
28
O
Mono line output (–)
MONO_LOP
27
O
Mono line output (+)
RESET
33
I
Reset. Active low
RIGHT_LOM
32
O
Right line output (–)
RIGHT_LOP
31
O
Right line output (+)
SCL
1
I/O
I2C serial clock or GPIO
SDA
2
I/O
I2C serial data input and output or GPIO
SELECT
43
I
WCLK
39
I/O
Control mode select pin (1 = SPI, 0 = I2C)
Audio serial data bus word clock (I/O)
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8 Specifications
8.1 Absolute Maximum Ratings
see
(1)
MIN
MAX
UNIT
AVDD_DAC to AVSS_DAC, DRVDD to DRVSS, AVSS_ADC
–0.3
3.9
V
AVDD to DRVSS
–0.3
3.9
V
IOVDD to DVSS
–0.3
3.9
V
DVDD to DVSS
–0.3
2.5
V
AVDD_DAC to DRVDD
–0.1
0.1
V
Digital input voltage to DVSS
–0.3
VIOVDD + 0.3
V
Analog input voltage to AVSS_ADC
–0.3
VAVDD + 0.3
V
Power dissipation
(TJ(MAX) – TA) / θJA
Operating temperature range
–40
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
85
°C
105
°C
105
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±1500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VAVDD_DAC,
VDRVDD
Analog supply voltage
VDVDD
Digital core supply voltage (1)
(1)
(1)
VIOVDD
Digital I/O supply voltage
VI
Analog, full-scale, 0-dB input voltage (DRVDD1 = 3.3 V)
MIN
NOM
MAX
2.7
3.3
3.6
V
1.65
1.8
1.95
V
1.8
3.6
1.1
0.707
Stereo line output load resistance
10
Stereo headphone output load resistance
16
Digital output load capacitance
TA
(1)
6
–40
V
VRMS
kΩ
Ω
10
Operating free-air temperature
UNIT
pF
85
°C
Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to DVSS.
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8.4 Thermal Information
TLV320AIC3106-Q1
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
30.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
13.4
°C/W
RθJB
Junction-to-board thermal resistance
7.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
TA = –40°C to 85°C, VAVDD_DAC, VDRVDD, VIOVDD = 3.3 V, VDVDD = 1.8 V, fS = 48-kHz, 16-bit audio data
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
Input signal level (0 dB)
Single-ended input
Signal-to-noise ratio, A-weighted (1) (2) fS = 48 ksps, 0-dB PGA gain, inputs AC-shorted to ground
Dynamic range (2)
fS = 48 ksps, 0-dB PGA gain, –60-dB full-scale input signal
THD
Total harmonic distortion
fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale,
1-kHz input signal
PSRR
Power supply rejection ratio
Gain error
Input channel separation
ADC programmable gain amplifier
maximum gain
dB
–88
49
1-kHz signal applied to DRVDD
46
–70
dB
dB
fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale,
1-kHz input signal
0.84
1-kHz, –2-dB full-scale signal, MIC3L to MIC3R
–86
1-kHz, –2-dB full-scale signal, MIC2L to MIC2R
–98
1-kHz, –2-dB full-scale signal, MIC1L to MIC1R
–75
1-kHz input tone
59.5
dB
0.5
dB
MIC1L and MIC1R inputs routed to single ADC,
Input mix attenuation = 0 dB
20
MIC1L and MIC1R inputs routed to single ADC,
input mix attenuation = 12 dB
80
MIC2L and MIC2R inputs routed to single ADC,
Input mix attenuation = 0 dB
20
MIC2L and MIC2R inputs routed to single ADC,
input mix attenuation = 12 dB
80
MIC3L and MIC3R inputs routed to single ADC,
Input mix attenuation = 0 dB
20
MIC3L and MIC3R inputs routed to single ADC,
input mix attenuation = 12 dB
80
dB
dB
kΩ
0
dB
Input level control maximum
attenuation setting
12
dB
Signal-to-noise ratio, A-weighted
(2)
dB
91
Input level control minimum
attenuation setting
Input signal level
(1)
VRMS
92
217-Hz signal applied to DRVDD
ADC programmable gain amplifier
step size
Input resistance
0.707
80
Differential Input
(1) (2)
fS = 48 ksps, 0-dB PGA gain, inputs AC-shorted to ground,
differential mode
1.414
92
VRMS
dB
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, VAVDD_DAC, VDRVDD, VIOVDD = 3.3 V, VDVDD = 1.8 V, fS = 48-kHz, 16-bit audio data
(unless otherwise noted)
PARAMETER
THD
Total harmonic distortion
TEST CONDITIONS
MIN
TYP
fS = 48 ksps, 0-dB PGA gain,
–2-dB full-scale 1-kHz input signal, differential mode
–91
MIC1/LINE1 to LINE_OUT
330
MIC2/LINE2 to LINE_OUT
330
MAX
UNIT
dB
ANALOG PASS THROUGH MODE
Input to output switch resistance,
(rDS(ON))
Ω
ADC DIGITAL DECIMATION FILTER, fS = 48 kHz
Filter gain from 0 to 0.39 fS
Filter gain at 0.4125 fS
Filter gain at 0.45 fS
Filter gain at 0.5 fS
Filter gain from 0.55 fS to 64 fS
Filter group delay
±0.1
dB
–0.25
dB
–3
dB
–17.5
dB
–75
dB
17 / fS
s
MICROPHONE BIAS
Programmable setting = 2
Bias voltage
2
Programmable setting = 2.5
2.3
Programmable setting = VDRVDD
Current sourcing
2.5
2.7
V
VDRVDD
Programmable setting = 2.5 V
4
mA
AUDIO DAC: DIFFERENTIAL LINE OUTPUT, LOAD = 10 kΩ
SNR
THD
Full-scale output voltage
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
Signal-to-noise ratio, A-weighted (3)
No input signal, output volume control = 0 dB,
output common mode setting = 1.35 V, fS = 48 kHz
Dynamic range, A-weighted
Total harmonic distortion
Power-supply rejection ratio
1.414
90
VRMS
102
dB
–60-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
99
dB
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
–94
217-Hz signal applied to DRVDD, AVDD_DAC
77
1-kHz signal applied to DRVDD, AVDD_DAC
73
–75
dB
dB
DAC channel separation
0-dB full-scale input signal between left and right line out
123
dB
DAC gain error
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
–0.4
dB
0.707
Vrms
AUDIO DAC: SINGLE ENDED LINE OUTPUT, LOAD = 10 kΩ
Full-scale output voltage
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
SNR
Signal-to-noise ratio, A-weighted
No input signal, output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
97
dB
THD
Total harmonic distortion
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
84
dB
DAC gain error
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
0.55
dB
(3)
8
Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω
single-ended load.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, VAVDD_DAC, VDRVDD, VIOVDD = 3.3 V, VDVDD = 1.8 V, fS = 48-kHz, 16-bit audio data
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO DAC: SINGLE ENDED HEADPHONE OUTPUT, LOAD = 16 Ω
Full-scale output voltage
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
0.707
Vrms
No input signal, output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
95
dB
No input signal, output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz,
50% DAC current boost mode
96
dB
Dynamic range, A-weighted
–60-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
92
dB
THD
Total harmonic distortion
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz, 25°C
PSRR
Power-supply rejection ratio
SNR
Signal-to-noise ratio, A-weighted
–80
–65
dB
217-Hz signal applied to DRVDD, AVDD_DAC
41
1-kHz signal applied to DRVDD, AVDD_DAC
44
DAC channel separation
0-dB full-scale input signal between left and right line out
84
dB
DAC gain error
0-dB, 1-kHz input full-scale signal,
output volume control = 0 dB,
output common-mode setting = 1.35 V, fS = 48 kHz
–0.5
dB
dB
AUDIO DAC: LINEOUT AND HEADPHONE OUT DRIVERS
First option
Output common mode
1.35
Second option
1.5
Third option
V
1.65
Fourth option
1.8
Output volume control maximum
setting
9
dB
Output volume control step size
1
dB
DAC DIGITAL INTERPOLATION (4): FILTER fS = 48 ksps, 25°C
Pass band
0
Pass-band ripple
0.45 fS
±0.06
Hz
dB
Transition band
0.45 fS
0.55 fS
Hz
Stop band
0.55 fS
7.5 fS
Hz
Stop-band attenuation
65
Group delay
dB
21 / fS
s
DIGITAL I/O, 25°C
VIL
Input low level
VIH
Input high level (5)
VOL
Output low level
VOH
Output high level
–0.3
VIOVDD > 1.6 V
0.7 × VIOVDD
VIOVDD < 1.6 V
1.1
0.3 × VIOVDD
V
V
0.1 × VIOVDD
0.8 × VIOVDD
V
V
POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
(4)
(5)
RESET held low
0.1
0.2
Mono ADC record, fS = 8 ksps, I2S slave,
AGC off, no signal
2.1
Stereo ADC record, fS = 8 ksps, I2S slave,
AGC off, no signal
4.1
Stereo ADC record, fS = 48 ksps, I2S slave,
AGC off, no signal
4.3
0.5
0.6
2.5
μA
mA
mA
mA
Not production tested. Specified by design.
When VIOVDD < 1.6 V, minimum VIH is 1.1 V.
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Electrical Characteristics (continued)
TA = –40°C to 85°C, VAVDD_DAC, VDRVDD, VIOVDD = 3.3 V, VDVDD = 1.8 V, fS = 48-kHz, 16-bit audio data
(unless otherwise noted)
PARAMETER
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
TEST CONDITIONS
MIN
TYP
Stereo DAC playback to line out, analog mixer bypassed,
fS = 48 ksps, I2S slave
3.5
Stereo DAC playback to line out, fS = 48 ksps, I2S slave,
no signal
4.9
Stereo DAC playback to stereo single-ended headphone,
fS = 48 ksps, I2S slave, no signal
6.7
MAX
mA
2.3
mA
2.3
mA
2.3
3.1
Stereo line in to stereo line out, no signal
mA
0
1.4
Extra power when PLL enabled
mA
0.9
28
All blocks powered down, headset detection enabled
UNIT
μA
2
8.6 Switching Characteristics I2S/LJF/RJF In Master Mode
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
td(WS)
ADWS/WCLK delay time
td(DO-WS)
ADWS/WCLK to DOUT delay time
td(DO-BCLK)
BCLK to DOUT delay time
ts(DI)
DIN setup time
th(DI)
DIN hold time
tr
Rise time
tf
Fall time
MIN
MAX
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
15
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
20
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
15
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
UNIT
ns
ns
ns
ns
ns
VIOVDD = 1.1 V
30
VIOVDD = 3.3 V
10
VIOVDD = 1.1 V
30
VIOVDD = 3.3 V
10
ns
ns
8.7 Switching Characteristics I2S/LJF/RJF In Slave Mode
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
tH(BCLK)
BCLK high period
tL(BCLK)
BCLK low period
ts(WS)
ADWS/WCLK setup time
th(WS)
ADWS/WCLK hold time
td(DO-WS)
ADWS/WCLK to DOUT delay time (for LJF Mode only)
10
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MIN
VIOVDD = 1.1 V
70
VIOVDD = 3.3 V
35
VIOVDD = 1.1 V
70
VIOVDD = 3.3 V
35
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
MAX
UNIT
ns
ns
ns
ns
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
35
ns
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Switching Characteristics I2S/LJF/RJF In Slave Mode (continued)
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
td(DO-BCLK)
BCLK to DOUT delay time
ts(DI)
DIN setup time
th(DI)
DIN hold time
tr
Rise time
tf
Fall time
MIN
MAX
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
20
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
UNIT
ns
ns
ns
VIOVDD = 1.1 V
8
VIOVDD = 3.3 V
4
VIOVDD = 1.1 V
8
VIOVDD = 3.3 V
4
ns
ns
8.8 Switching Characteristics DSP In Master Mode
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
td(WS)
ADWS/WCLK delay time
td(DO-BCLK)
BCLK to DOUT delay time
ts(DI)
DIN setup time
th(DI)
DIN hold time
tr
Rise time
tf
Fall time
MIN
MAX
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
15
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
15
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
UNIT
ns
ns
ns
ns
VIOVDD = 1.1 V
30
VIOVDD = 3.3 V
10
VIOVDD = 1.1 V
30
VIOVDD = 3.3 V
10
ns
ns
8.9 Switching Characteristics DSP In Slave Mode
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
tH(BCLK)
BCLK high period
tL(BCLK)
BCLK low period
ts(WS)
ADWS/WCLK setup time
th(WS)
ADWS/WCLK hold time
td(DO-BCLK)
BCLK to DOUT delay time
ts(DI)
DIN setup time
th(DI)
DIN hold time
MIN
VIOVDD = 1.1 V
70
VIOVDD = 3.3 V
35
VIOVDD = 1.1 V
70
VIOVDD = 3.3 V
35
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
8
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
8
MAX
ns
ns
ns
ns
VIOVDD = 1.1 V
50
VIOVDD = 3.3 V
20
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
VIOVDD = 1.1 V
10
VIOVDD = 3.3 V
6
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ns
ns
ns
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Switching Characteristics DSP In Slave Mode (continued)
All specifications at 25°C, DVDD = 1.8 V.
PARAMETER
tr
Rise time
tf
Fall time
MIN
MAX
VIOVDD = 1.1 V
8
VIOVDD = 3.3 V
4
VIOVDD = 1.1 V
8
VIOVDD = 3.3 V
4
UNIT
ns
ns
WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0145-01
Figure 1. I2S/LJF/RJF Timing In Master Mode
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WCLK
tS(WS)
th(WS)
tH(BCLK)
BCLK
td(DO-WS)
tL(BCLK)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0145-02
Figure 2. I2S/LJF/RJF Timing In Slave Mode
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0146-01
Figure 3. DSP Timing In Master Mode
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WCLK
tS(WS)
tS(WS)
th(WS)
th(WS)
tL(BCLK)
BCLK
tH(BCLK)
td(DO-BCLK)
SDOUT
tS(DI)
th(DI)
SDIN
T0146-02
Figure 4. DSP Timing In Slave Mode
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8.10 Typical Characteristics
45
0
2.7 VDD_CM 1.35_LDAC
40
3.6 VDD_CM 1.8_LDAC
-20
SNR - Signal-To-Noise - dB
THD - Total Harmonic Distortion - dB
-10
3.3 VDD_CM1.65_LDAC
2.7 VDD_CM 1.35_RDAC
-30
-40
3.3 VDD_CM 1.65_RDAC
-50
-60
35
30
25
20
15
-70
10
-80
LINEIR Routed to RADC in Differential Mode,
48 KSPS, Normal Supply and Temperature,
Input Signal at -65 dB
5
3.6 VDD_CM 1.8_RDAC
0
-90
0
20
40
60
80
0
100
40
50
60
70
Figure 6. Signal-To-Noise Ratio vs ADC PGA Setting
4
AVDD = 3.3 V,
No Load
3.5
3.5
MICBIAS VOLTAGE - V
PGM = VDD
3
PGM = 2.5 V
2.5
PGM = 2 V
PGM = VDD
3
PGM = 2.5 V
2.5
PGM = 2 V
2
2
1.5
2.7
2.9
3.1
3.3
1.5
-60
3.5
-40
VDD - Supply Voltage - V
-20
0
20
40
60
TA - Free- Air Temperature - °C
80
100
Figure 8. MICBIAS Voltage vs Free-Air Temperature
Figure 7. MICBIAS Voltage vs Supply Voltage
0
0
-40
-60
-80
-100
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
-20
-40
Amplitude - dB
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
4096 Samples,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
-20
Amplitude - dB
30
Figure 5. Total Harmonic Distortion vs
Headphone Out Power
No Load
-60
-80
-100
-120
-120
-140
-140
-160
20
ADC, PGA - Setting - dB
4
MICBIAS VOLTAGE - V
10
Headphone Out Power - mW
-160
0
1
2
3
4
5
6
7
8
9 10 11 12
f - Frequency - kHz
13
14
15
16
17
18
19
20
0
1
2
3
4
Figure 9. Left DAC FFT
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5
6
7
8
9
10
11
12
13 14
15 16
17 18
19
20
f - Frequency - kHz
Figure 10. Right DAC FFT
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Typical Characteristics (continued)
0
0
Amplitude - dB
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
-140
-140
-160
0
1
2
3
4
5
6
7
8
9 10 11 12
f - Frequency - kHz
13
14
15
16
17
18
19
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
2048 Samples,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
-20
Amplitude - dB
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
2048 Samples,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
-20
20
-160
0
1
2
3
5
4
Figure 11. Left ADC FFT
16
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6
7
8
9 10 11 12
f - Frequency - kHz
13
14
15
16
17
18
19
20
Figure 12. Right ADC FFT
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9 Detailed Description
9.1 Overview
The TLV320AIC3106-Q1 is a highly flexible, low power, stereo audio codec with extensive feature integration,
intended for applications in infotainment or cluster systems such as head unit, telematics, cluster, emergency call
(eCall), navigation systems, and other car entertainment applications. Available in a 7-mm x 7-mm, 48-lead
VQFN package, the product integrates a host of features to reduce cost, board space, and power consumption in
space-constrained, battery-powered, portable applications.
The TLV320AIC3106-Q1 consists of the following blocks:
• Stereo audio multi-bit delta-sigma DAC (8 kHz to 96 kHz)
• Stereo audio multi-bit delta-sigma ADC (8 kHz to 96 kHz)
• Programmable digital audio effects processing (3D, bass, treble, mid-range, EQ, notch filter, de-emphasis)
• Six audio inputs
• Four high-power audio output drivers (headphone drive capability)
• Three fully differential line output drivers
• Fully programmable PLL
• Headphone or headset jack detection with interrupt
Communication to the TLV320AIC3106-Q1 for control is pin-selectable (using the SELECT pin) as either SPI or
I2C. The SPI interface requires that the Slave Select signal (MFP0) be driven low to communicate with the
TLV320AIC3106-Q1. Data is then shifted into or out of the TLV320AIC3106-Q1 under control of the host
microprocessor, which also provides the serial data clock. The I2C interface supports both standard and fast
communication modes, and also enables cascading of up to four multiple codecs on the same I2C bus through
the use of two pins for addressing (MFP0, MFP1).
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BCLK
WCLK
DIN
DOUT
9.2 Functional Block Diagram
LINE2LP
MIC2LP / LINE2LP
MIC2LM / LINE2LM
+
HPLOUT
LINE2LM
AGC
DINR
MIC3L / LINE3L
VCM
DINL
DOUTL
DOUTR
Audio Serial Bus Interface
HPLCOM
+
SW-D2
LINE1LP
MIC1LP / LINE1LP
MIC1LM / LINE1LM
PGA
0/+59.5dB
0.5dB steps
+
ADC
Volume
Control
Effects
DAC
L
SW-D1
+
LINE1LM
HPRCOM
VCM
HPROUT
+
AGC
SW-D4
SW-L2
LINE1RP
MIC1RP / LINE1RP
MIC1RM / LINE1RM
LINE2LP
PGA
0/+59.5dB
0.5dB steps
+
SW-L1
ADC
Volume
Control
Effects
LINE1LP
DACR
SW-L0
SW-D3
+
LINE1RM
LEFT_LOP
SW-L3
LEFT_LOM
LINE1LM
LINE2LM
SW-L4
SW-L5
MIC3R / LINE3R
SW-R2
LINE2RP
SW-R1
LINE1RP
SW-R0
+
LINE2RP
RIGHT_LOP
SW-R3
RIGHT_LOM
MIC2RP / LINE2RP
MIC2RM / LINE2RM
SW-R4
LINE1RM
SW-R5
LINE2RM
LINE2RM
Bias/
Reference
Voltage Supplies
Audio Clock
Generation
SPI / I2C Serial Control Bus
+
MONO_LOP
MONO_LOM
SDA/GPIO
SCL/GPIO
MISO/GPIO
MOSI/GPIO
SELECT
SCLK/I2C_ADR1
CSEL/I2C_ADR0
RESET
GPIO_2
GPIO_1
MCLK
MICBIAS
MICDET
DVSS
IOVDD
DVDD
DRVSS
DRVSS
DRVDD
DRVDD
AVSS_DAC
AVDD_DAC
AVSS_ADC
AVDD_ADC
9.3 Feature Description
9.3.1 Audio Data Converters
The TLV320AIC3106-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz,
16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations.
The data converters are based on the concept of an fS(ref) rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, fS(ref) is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high quality playback of low sampling rate data, without high frequency audible noise being
generated.
The sampling rate of the ADC and DAC can be set to fS(ref) / NDAC or 2 × fS(ref) / NDAC, with NDAC being 1, 1.5,
2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.
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Feature Description (continued)
While only one fS(ref) can be used at a time in the part, the ADC and DAC sampling rates can differ from each
other by using different NADC and NDAC divider ratios for each. For example, with fS(ref) = 44.1 kHz, the DAC
sampling rate can be set to 44.1 kHz by using NDAC = 1, while the ADC sampling rate can be set to 8.018 kHz
by using NADC = 5.5.
When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to
provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit clock
signal (which can be supplied through the BCLK pin or through GPIO2) is used to transfer both ADC and DAC
data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC word clock
signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1 at the same time the DAC
word clock is supplied or generated from WCLK.
9.3.2 Stereo Audio ADC
The TLV320AIC3106-Q1 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from
8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires that an audio master clock be provided and appropriate audio clock generation be
set up within the device.
To provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to support
the case where only mono record capability is required. In addition, both channels can be fully powered or
entirely powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase
output response with a group delay of 17 / fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and
scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 fS to
64 fS. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
can be independently set.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3106-Q1 integrates a second-order
analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see Page 0, Registers 19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC
power-down flag is no longer set, the audio master clock can be shut down.
9.3.2.1 Stereo Audio ADC High-Pass Filter
Often in audio applications it is desirable to remove the DC offset from the converted audio data stream. The
TLV320AIC3106-Q1 has a programmable first-order high-pass filter which can be used for this purpose. The
digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients,
N0, N1, and D1. The transfer function of the digital high-pass filter is of the form:
H(z) =
N0 + N1´ z -1
32768 - D1´ z -1
(1)
Programming the left channel is done by writing to Page 1, Registers 65 to 70, and the right channel is
programmed by writing to Page 1, Registers 71 to 76. After the coefficients have been loaded, these ADC highpass filter coefficients can be selected by writing to Page 0, Register 107, Bits D7 to D6, and the high-pass filter
can be enabled by writing to Page 0, Register 12, Bits D7 to D4.
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Feature Description (continued)
9.3.3 Automatic Gain Control (AGC)
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several
programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum
PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses
the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the
nominal amplitude of the output signal.
Completely independent AGC circuitry is included with each ADC channel with entirely independent control over
the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a
system, but may have different placement in the end equipment and require different dynamic performance for
optimal system operation.
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC3106-Q1 allows programming of eight different target levels, which can be programmed from
–5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and
not to peak levels, TI recommends the target level be set with enough margin to avoid clipping at the occurrence
of loud sounds.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 7 ms to 1,408 ms. The extended Right Channel Attack time can be programmed by writing to
Page 0, Register 103, and Left Channel is programmed by writing to Page 0, Register 105.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 0.05 s to 22.4 s. The extended Right Channel Decay time can be programmed by writing to
Page 0, Register 104, and Left Channel is programmed by writing to Page 0, Register 106.
The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the
clock set up that is used. The table below shows the relationship of the NADC ratio to the maximum time
available for the AGC decay. In practice, these maximum times are extremely long for audio applications and
must not limit any practical AGC decay time that is required by the system.
Table 1. AGC Decay Time Restriction
NADC RATIO
MAXIMUM DECAY TIME (s)
1
4
1.5
5.6
2
8
2.5
9.6
3
11.2
3.5
11.2
4
16
4.5
16
5
19.2
5.5
22.4
6
22.4
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it
as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold
flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This
ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm
is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This
operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling
between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is
set, the status of gain applied by the AGC and the saturation flag may be ignored.
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Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
W0002-01
Figure 13. Typical Operation Of The AGC Algorithm During Speech Recording
The time constants here are correct when the ADC is not in double-rate audio mode. The time constants are
achieved using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in the registers to,
for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different fS(ref) in
practice, then the time constants would not be correct.
The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the
clock set up that is used. Table 1 shows the relationship of the NADC ratio to the maximum time available for the
AGC decay. In practice, these maximum times are extremely long for audio applications and must not limit any
practical AGC decay time that is required by the system.
9.3.4 Stereo Audio DAC
The TLV320AIC3106-Q1 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each
channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit
digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced
performance at low sampling rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the
audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × fS(ref) and
changing the oversampling ratio as the input sample rate is changed. For an fS(ref) of 48 kHz, the digital deltasigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within
the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an
fS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
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The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
• Allowed Q values = 4, 8, 9, 12, 16
• Q values where equivalent fS(ref) can be achieved by turning on PLL
• Q = 5, 6, 7 (set P = 5, 6, 7 and K = 16 and PLL enabled)
• Q = 10, 14 (set P = 5, 7 and K = 8 and PLL enabled)
9.3.5 Digital Audio Processing For Playback
The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment,
speaker equalization, and 3D effects processing. The de-emphasis function is implemented by a programmable
digital filter block with fully programmable coefficients (see Page 1, Registers 21 to 26 for left channel, Page 1,
Registers 47 to 52 for right channel). If de-emphasis is not required in a particular application, this programmable
filter block can be used for some other purpose. The de-emphasis filter transfer function is given by:
H(z) =
N0 + N1´ z -1
32768 - D1´ z -1
(2)
where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that
must be loaded to implement standard de-emphasis filters are given in Table 2.
Table 2. De-Emphasis Coefficients For Common Audio Sampling Rates
SAMPLING FREQUENCY
N0
N1
D1
32 kHz
16950
–1220
17037
44.1 kHz
15091
–2877
20555
48 kHz (1)
14677
–3283
21374
(1)
The 48-kHz coefficients listed in Table 2 are used as defaults.
In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR
filter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquad
sections with frequency response given by:
æ N0 + 2 ´ N1´ z -1 + N2 ´ z -2 ö æ N3 + 2 ´ N4 ´ z -1 + N5 ´ z -2 ö
çç
֍
÷
-1
-2 ÷ ç
-1
-2 ÷
è 32768 - 2 ´ D1´ z - D2 ´ z ø è 32768 - 2 ´ D4 ´ z - D5 ´ z ø
(3)
The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure
of the filtering when configured for independent channel processing is shown in Figure 14, with LB1
corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly
corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and
RB2 filters refer to the first and second right-channel biquad filters, respectively.
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LB1
LB2
RB1
RB2
Figure 14. Structure Of The Digital Effects Processing For Independent Channel Processing
The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most
commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 3
and implement a shelving filter with 0-dB gain from DC to approximately 150 Hz, at which point it rolls off to a
3‑dB attenuation for higher frequency signals, thus giving a 3‑dB boost to signals below 150 Hz. The N and D
coefficients are represented by 16-bit, 2s-complement numbers with values ranging from –32768 to 32767.
Table 3. Default Digital Effects Processing Filter Coefficients,
When In Independent Channel Processing Configuration
COEFFICIENTS
N0 = N3
D1 = D4
N1 = N4
D2 = D5
N2 = N5
27,619
32,131
–27,034
–31,506
26,461
The digital processing also includes capability to implement 3D processing algorithms by providing means to
process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo
output playback. The architecture of this processing mode, and the programmable filters available for use in the
system, is shown in Figure 15. The programmable attenuation block provides a method of adjusting the level of
3D effect introduced into the final stereo output. This combined with the fully programmable biquad filters in the
system enables the user to fully optimize the audio effects for a particular system and provide extensive
differentiation from other systems using the same device.
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+ +
+
L
+
+
–
LB2
To Left Channel
Atten
LB1
R
+
–
+
To Right Channel
RB2
B0155-01
Figure 15. Architecture Of The Digital Audio Processing When 3D Effects Are Enabled
TI recommends the digital effects filters be disabled while the filter coefficients are being modified. While new
coefficients are being written to the device over the control port, it is possible that a filter using partially updated
coefficients may actually implement an unstable system and lead to oscillation or objectionable audio output. By
disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be
entirely avoided.
9.3.6 Digital Interpolation Filter
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21 / fS. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (8 kHz, 16 kHz, 24 kHz, and so on). The images at 8 kHz and 16 kHz are below 20 kHz and
still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The
interpolation filter is designed to maintain at least 65-dB rejection of images that land below 7.455 fS. To use the
programmable interpolation capability, the fS(ref) must be programmed to a higher rate (restricted to be in the
range of 39 kHz to 53 kHz when the PLL is in use), and the actual fS is set using the NDAC divider. For example,
if fS = 8 kHz is required, then fS(ref) can be set to 48 kHz, and the DAC fS set to fS(ref) / 6. This ensures that all
images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
9.3.7 Delta-Sigma Audio Dac
The stereo audio DAC incorporates a third-order multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a
continuous time RC filter. The analog FIR operates at a rate of 128 × fS(ref) (6.144 MHz when fS(ref) = 48 kHz,
5.6448 MHz when fS(ref) = 44.1 kHz). The DAC analog performance may be degraded by excessive clock jitter on
the MCLK input. Therefore, take care to keep jitter on this clock to a minimum.
9.3.8 Audio Dac Digital Volume Control
The audio DAC includes a digital volume control block which implements a programmable digital gain. The
volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for
each channel. The volume level of both channels can also be changed simultaneously by the master volume
control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by
one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can
be slowed to one step per two input samples through a register bit.
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Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. To help with this situation, the device provides a flag back to the host through a read-only register bit that
alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired
volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is
enabled, the MCLK signal must be kept applied to the device until the DAC power-down flag is set. When this
flag is set, the internal soft-stepping process and power down sequence is complete, and the MCLK can then be
stopped if desired.
The TLV320AIC3106-Q1 also includes functionality to detect when the user switches on or off the de-emphasis
or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of
the digital effects processing, and (3) soft-unmute the part. This avoids any possible pops or clicks in the audio
output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down
the DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the
desired volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers
down the circuitry.
9.3.9 Analog Output Common-Mode Adjustment
The output common-mode voltage and output range of the analog output are determined by an internal bandgap
reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to
reduce the coupling of noise that may be on the supply into the audio signal path.
However, due to the possible wide variation in analog supply range (2.7 V to 3.6 V), an output common-mode
voltage setting of 1.35 V, which would be used for a 2.7-V supply case, is overly conservative if the supply is
actually much larger, such as 3.3 V or 3.6 V. To optimize device operation, the TLV320AIC3106-Q1 includes a
programmable output common-mode level, which can be set by register programming to a level most appropriate
to the actual supply range used by a particular customer. The output common-mode level can be varied among
four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most
appropriate for high supply ranges, near 3.6 V). There is also some limitation on the range of DVDD voltage as
well in determining which setting is most appropriate.
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Table 4. Appropriate Settings
CM SETTING
AVDD_DAC, DRVDD
DVDD
1.35
2.7 V – 3.6 V
1.65 V – 1.95 V
1.5
3 V – 3.6 V
1.65 V – 1.95 V
1.65 V
3.3 V – 3.6 V
1.8 V – 1.95 V
1.8 V
3.6 V
1.95 V
9.3.10 Audio DAC Power Control
The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can
be powered up or down independently. This provides power savings when only a mono playback stream is
required.
9.3.11 Audio Analog Inputs
The TLV320AIC3106-Q1 includes ten analog audio input pins, which can be configured as up to four fullydifferential pair plus one single-ended pair of audio inputs, or up to six single-ended audio inputs. These pins
connect through series resistors and switches to the virtual ground terminals of two fully differential opamps (one
per ADC PGA channel). By selecting to turn on only one set of switches per opamp at a time, the inputs can be
effectively muxed to each ADC PGA channel.
By selecting to turn on multiple sets of switches per opamp at a time, mixing can also be achieved. Mixing of
multiple inputs can easily lead to PGA outputs that exceed the range of the internal opamps, resulting in
saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the user must take
adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal must not
exceed 2 VPP (single-ended) or 4 VPP (differential).
In most mixing applications, the levels of the individual signals being mixed must be adjusted. For example, if a
soft signal and a large signal are to be mixed and played together, the soft signal generally must be amplified to
a level comparable to the large signal before mixing. To accommodate this, the TLV320AIC3106-Q1 includes
input level control on each of the individual inputs before they are mixed or muxed into the ADC PGAs, with gain
programmable from 0 dB to –12 dB in 1.5-dB steps. This input level control is not intended to be a volume
control, but instead used occasionally for level setting. Soft-stepping of the input level control settings is
implemented in this device, with the speed and functionality following the settings used by the ADC PGA for softstepping.
The TLV320AIC3106-Q1 supports the ability to mix up to three fully-differential analog inputs into each ADC PGA
channel. Figure 16 shows the mixing configuration for the left channel, which can mix the signals LINE1LPLINE1LM, LINE2LP-LINE2LM, and LINE1RP-LINE1RM
GAIN=0,−1.5,−3,..,−12dB,MUTE
LINE1LP
LINE1LM
GAIN=0,−1.5,−3,..,−12dB, MUTE
LINE2LP
TO LEFT ADC
LINE2LM
PGA
GAIN=0,−1.5,−3,..,−12dB,MUTE
LINE1RP
LINE1RM
Figure 16. Left Channel Fully-Differential Analog Input Mixing Configuration
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Three fully-differential analog inputs can similarly be mixed into the right ADC PGA as well, consisting of
LINE1RP-LINE1RM, LINE2RP-LINE2RM, and LINE1LP-LINE1LM. It is not necessary to mix all three fullydifferential signals if this is not desired, unnecessary inputs can simply be muted using the input level control
registers.
Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC PGAs
is also possible in this mode. It is not possible, however, for an input pair to be selected as fully-differential for
connection to one ADC PGA and simultaneously selected as single-ended for connection to the other ADC PGA
channel. However, it is possible for an input to be selected or mixed into both left and right channel PGAs, as
long as it has the same configuration for both channels (either both single-ended or both fully-differential).
Figure 17 shows the single-ended mixing configuration for the left channel ADC PGA, which enables mixing of
the signals LINE1LP, LINE2LP, LINE1RP, MIC3L, and MIC3R. The right channel ADC PGA mix is similar,
enabling mixing of the signals LINE1RP, LINE2RP, LINE1LP, MIC3L, and MIC3R.
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE1LP/MIC1LP
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE2LP /MIC2LP
GAIN=0,-1.5,-3,..,-12dB,MUTE
TO LEFT ADC
PGA
LINE1RP /MIC1RP
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE3L/MIC3L
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE3R/MIC3R
Figure 17. Left Channel Single-Ended Analog Input Mixing Configuration
9.3.12 Analog Input Bypass Path Functionality
The TLV320AIC3106-Q1 includes the additional ability to route some analog input signals past the integrated
data converters, for mixing with other analog signals and then direct connection to the output drivers. The
TLV320AIC3106-Q1 supports this in a low power mode by providing a direct analog path through the device to
the output drivers, while all ADCs and DACs can be completely powered down to save power.
For fully-differential inputs, the TLV320AIC3106-Q1 provides the ability to pass the signals LINE2LP-LINE2LM
and LINE2RP-LINE2RM to the output stage directly. If in single-ended configuration, the device can pass the
signal LINE2LP and LINE2RP to the output stage directly.
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9.3.13 ADC PGA Signal Bypass Path Functionality
In addition to the input bypass path described in Analog Input Bypass Path Functionality, the
TLV320AIC3106‑Q1 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with
other analog signals and then direct connection to the output drivers. These bypass functions are described in
more detail in the sections on output mixing and output driver configurations.
9.3.14 Input Impedance and VCM Control
The TLV320AIC3106-Q1 includes several programmable settings to control analog input pins, particularly when
they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
3-state condition, such that the input impedance seen looking into the device is extremely high. The pins on the
device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a
pin approximately one diode drop (approximately 0.6 V) above AVDD or one diode drop below AVSS, these
protection diodes begins conducting current, resulting in an effective impedance that no longer appears as a 3state condition.
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the AC-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the
necessity of charging them up suddenly when the input is changed from being unselected to selected for
connection to an ADC PGA. This option is controlled in Page 0, Registers 20 and 23. The user must ensure this
option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input
bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC3106-Q1 must be AC-coupled to analog input sources,
the only exception to this generally being if an ADC is being used for DC voltage measurement. The AC-coupling
capacitor causes a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of
0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a
0.1-μF AC-coupling capacitor at an analog input results in a highpass filter pole of 80 Hz when the 0-dB input
level control setting is selected.
9.3.15 MICBIAS Generation
The TLV320AIC3106-Q1 includes a programmable microphone bias output voltage (MICBIAS), capable of
providing output voltages of 2 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output
current drive. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip
switch, or it can be powered down completely when not required, for power savings. This function is controlled by
register programming in Page 0, Register 25.
9.3.16 Analog Fully Differential Line Output Drivers
The TLV320AIC3106-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differential
load. The output stage design leading to the fully differential line output drivers is shown in Figure 18 and
Figure 19. This design includes extensive capability to adjust signal levels independently before any mixing
occurs, beyond that already provided by the PGA gain and the DAC digital volume control.
The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage.
The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to
the output stage. Because both left and right channel signals are routed to all output drivers, a mono mix of any
of the stereo signals can easily be obtained by setting the volume controls of both left and right channel signals
to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through register
control.
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DAC_L1
DAC_L
DAC_L2
STEREO
AUDIO
DAC
DAC_L3
DAC_R
DAC_R1
DAC_R2
DAC_R3
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
LEFT_LOP
LEFT_LOM
Gain = 0dB to +9dB,
Mute
DAC_L3
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
RIGHT_LOP
RIGHT_LOM
Gain = 0dB to +9dB,
Mute
DAC_R3
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
MONO_LOP
VOLUME
CONTROLS,
MIXING
MONO_LOM
Gain = 0dB to +9dB,
Mute
DAC_R1
Figure 18. Architecture Of The Output Stage Leading To The Fully Differential Line Output Drivers
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LINE2L/MIC2L
0dB to -78dB
LINE2R/MIC2R
0dB to -78dB
PGA_L
0dB to -78dB
+
PGA_R
0dB to -78dB
DAC_L1
0dB to -78dB
DAC_R1
0dB to -78dB
Figure 19. Detail Of The Volume Control and Mixing Function
The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based
on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC
output is only required at the stereo line outputs, then TI recommends to use the routing through path
DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher quality output performance,
but also in lower power operation, because the analog volume controls and mixing blocks ahead of these drivers
can be powered down.
If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to
LEFT_LOP/M, RIGHT_LOP/M, and MONO_LOP/M) or must be mixed with other analog signals, then the DAC
outputs must be switched through the DAC_L1/R1 path. This option provides the maximum flexibility for routing
of the DAC analog signals to the output drivers
The TLV320AIC3106-Q1 includes an output level control on each output driver with limited gain adjustment from
0 dB to 9 dB. The output driver circuitry in this device are designed to provide a low distortion output while
playing fullscale stereo DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained
at the cost of increased signal distortion at the output. This output level control allows the user to make this
tradeoff based on the requirements of the end equipment. This output level control is not intended to be used as
a standard output volume control. It is expected to be used only sparingly for level setting, such as adjustment of
the fullscale output range of the device.
Each differential line output driver can be powered down independently of the others when it is not required in
the system. When placed into powerdown through register programming, the driver output pins are placed into a
3‑stated, high-impedance state.
9.3.17 Analog High Power Output Drivers
The TLV320AIC3106-Q1 includes four high power output drivers with extensive flexibility in their usage. These
output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and
they can be used in pairs connected in bridge-terminated load (BTL) configuration between two driver outputs.
The high power output drivers can be configured in a variety of ways, including:
1. driving up to two fully differential output signals
2. driving up to four single-ended output signals
3. driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level,
for a pseudo-differential stereo output
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The output stage architecture leading to the high power output drivers is shown in Figure 20, with the volume
control and mixing blocks being effectively identical to that shown in Figure 19. Each of these drivers have a
output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on
the output signal. As in the previous case, this output level adjustment is not intended to be used as a standard
volume control, but instead is included for additional fullscale output signal level control.
Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs to
be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using the
DAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playback
performance with reduced power dissipation, but can only be used if the DAC output is not routed to multiple
output drivers simultaneously, and if mixing of the DAC output with other analog signals is not required.
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
Volume 0dB to
+9dB, mute
HPLOUT
DAC_L2
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
VCM
VCM
Volume 0dB to
+9dB, mute
Volume 0dB
to +9dB,
mute
HPLCOM
HPRCOM
DAC_R2
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
Volume 0dB to
+9dB, mute
HPROUT
Figure 20. Architecture Of The Output Stage Leading To The High Power Output Drivers
The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. The user must first program the type of output configuration being used in
Page 0, Register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The
power-up delay time for the high power output drivers is also programmable over a wide range of time delays,
from instantaneous up to 4 s, using Page 0, Register 42.
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When these output drivers are powered down, they can be placed into a variety of output conditions based on
register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state
condition, and all power to the output stage is removed. However, this generally results in the output nodes
drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results
in a longer delay requirement to avoid output artifacts during driver power-on. To reduce this required power-on
delay, the TLV320AIC3106-Q1 includes an option for the output pins of the drivers to be weakly driven to the
VCM level they would normally rest at when powered with no signal applied. This output VCM level is determined
by an internal bandgap voltage reference, and thus results in extra power dissipation when the drivers are in
powerdown. However, this option provides the fastest method for transitioning the drivers from powerdown to full
power operation without any output artifact introduced.
The device includes a further option that falls between the other two, while it requires less power drawn while the
output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the
bandgap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a
voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage does not
match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a
much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output
voltage options are controlled in Page 0, Register 42.
The high power output drivers can also be programmed to power up first with the output level control in a highly
attenuated state, then the output driver automatically slowly reduces the output attenuation to reach the desired
output level setting programmed. This capability is enabled by default but can be enabled in Page 0, Register 40.
9.3.18 Short Circuit Output Protection
The TLV320AIC3106-Q1 includes programmable short-circuit protection for the high power output drivers, for
maximum flexibility in a given application. By default, if these output drivers are shorted, they automatically limit
the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from
an overcurrent condition. In this mode, the user can read Page 0, Register 95 to determine whether the part is in
short-circuit protection or not, and then decide whether to program the device to power down the output drivers.
However, the device includes further capability to automatically power down an output driver whenever it does
into short-circuit protection, without requiring intervention from the user. In this case, the output driver stays in a
power down condition until the user specifically programs it to power down and then power back up again, to
clear the short-circuit flag.
9.3.19 Jack and Headset Detection
The TLV320AIC3106-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack,
determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is
wired to the plug. Figure 21 shows one configuration of the device that enables detection and determination of
headset type when a pseudo-differential (capless) stereo headphone output configuration is used. The registers
used for this function are Page 0, Registers 14, 96, 97, and 13. The type of headset detected can be read back
from Page 0, Register 13. For best results, TI recommends selecting a MICBIAS value as high as possible, and
to program the output driver common-mode level at a 1.35-V or 1.5-V level.
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Stereo
g
s
AVDD
MICBIAS
MICDET
s
To Detection block
MIC3(L/R)
Cellular
g
m
s
HPLOUT
Stereo +
g
Cellular
m
s
s
HPROUT
m = mic
HPRCOM
s = earspeaker
To
detection
block
1.35
HPLCOM
g = ground/midbias
Figure 21. Configuration Of Device For Jack Detection Using A Pseudo-Differential (Capless) Headphone
Output Connection
A modified output configuration used when the output drivers are AC-coupled is shown in Figure 22. In this
mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.
Stereo
g
s
MICBIAS
MICDET
s
AVDD
To Detection block
MIC3(L/R)
Cellular
g
m
s
HPLOUT
Stereo +
Cellular
g
m
s
s
HPROUT
m = mic
s = earspeaker
g = ground/midbias
Figure 22. Configuration Of Device For Jack Detection Using An AC-Coupled Stereo Headphone Output
Connection
An output configuration for the case of the outputs driving fully differential stereo headphones is shown in
Figure 23. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to
ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to
function properly, short-circuit detection must be enabled and configured to power down the drivers if a shortcircuit is detected. The registers that control this functionality are in Page 0, Register 38, Bits D2 to D1.
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This switch closes when
MICDET
jack is removed
To Detection block
HPLOUT
HPLCOM
HPRCOM
HPROUT
Figure 23. Configuration Of Device For Jack Detection Using A Fully Differential Stereo Headphone
Output Connection
9.3.20 General-Purpose I/O
TLV320AIC3106-Q1 has two dedicated pins for general-purpose I/O. These pins can be used to read status of
external signals through register read when configured as general-purpose input. When configured as generalpurpose output , these pins can also drive logic high or low. Besides these standard GPIO functions, these pins
can also be used in a variety of ways, such as output for internal clocks and interrupt signals. The
TLV320AIC3106-Q1 generates a variety of interrupts of use to the host processor such interrupts on jack
detection, button press, short-circuit detection, and AGC noise detection. All these interrupts can be routed
individually to the GPIO pins or can be combined by a logical OR. In case of a combined interrupt, the user can
read an internal status register to find the actual cause of interrupt. When configured as interrupt, the
TLV320AIC3106-Q1 also offers the flexibility of generating a single pulse or a train of pulses until the interrupt
status register is read by the user.
9.4 Device Functional Modes
9.4.1 Digital Audio Processing For Record Path
In applications where record only is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or
notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the
ADC output data through the digital signal processing blocks. Because the DAC's Digital Signal Processing
blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC
digital processing and are located on Page 1, Registers 1 to 52. This record only mode is enabled by powering
down both DACs by writing to Page 0, Register 37, Bits D7 to D6 (D7 = D6 = 0). Next, enable the digital filter
pathway for the ADC by writing a 1 to Page 0, Register 107, Bit D3. This pathway is only enabled if both DACs
are powered down. This record only path can be seen in Figure 24.
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BCLK
WCLK
DIN
DOUT
Device Functional Modes (continued)
DINL
DINR
AGC
DOUTR
DOUTL
Audio Serial Bus Interface
DAC
Powered
Down
Record Path
SW-D2
Left Channel
Analog Inputs
+
PGA
0/+59.5dB
0.5dB steps
ADC
Effects
SW-D1
Volume
Control
DAC
Powered
Down
AGC
Record Path
SW-D4
Right Channel
Analog Inputs
+
PGA
0/+59.5dB
0.5dB steps
ADC
Effects
SW-D3
DAC
L
Volume
Control
DACR
Figure 24. Record Only Mode With Digital Processing Path Enabled
9.4.2 Increasing DAC Dynamic Range
The TLV320AIC3106-Q1 allows trading off dynamic range with power consumption. The DAC dynamic range can
be increased by writing to Page 0, Register 109, Bits D7 to D6. The lowest DAC current setting is the default,
and the dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic
range by up to 1.5 dB.
9.4.3 Passive Analog Bypass During Powerdown
Programming the TLV320AIC3106-Q1 to passive analog bypass occurs by configuring the output stage switches
for pass through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or
SW-L2 and SW-R1 or SW-R2. See Figure 25 Passive Analog Bypass Mode Configuration. Programming this
mode is done by writing to Page 0, Register 108.
Connecting MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0,
this action is done by writing a 1 to Page 0, Register 108, Bit D0. Connecting MIC2LP/LINE2LP input signal to
the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0, this action is done by writing a 1 to Page 0,
Register 108, Bit D2. Connecting MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing SW-L4
and opening SW-L3, this action is done by writing a 1 to Page 0, Register 108, Bit D1. Connecting
MIC2LM/LINE2LM input signal to the LEFT_LOM pin is done by closing SW-L5 and opening SW-L3, this action
is done by writing a 1 to Page 0, Register 108, Bit D3.
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Device Functional Modes (continued)
Connecting MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SWR0, this action is done by writing a 1 to Page 0, Register 108, Bit D4. Connecting MIC2RP/LINE2RP input signal
to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0, this action is done by writing a 1 to
Page 0, Register 108, Bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by
closing SW-R4 and opening SW-R3, this action is done by writing a 1 to Page 0, Register 108, Bit D5.
Connecting MIC2RM/LINE2RM input signal to the RIGHT_LOM pin is done by closing SW-R5 and opening SWR3, this action is done by writing a 1 to Page 0, Register 108, Bit D7. A diagram of the passive analog bypass
mode configuration can be seen in Figure 25.
In general, connecting two switches to the same output pin must be avoided, as this error shorts two input
signals together, and causes distortion of the signal as the two signal are in contention, and poor frequency
response would also likely occur.
LINE2LP
SW-L2
LINE2LP
MIC2LP / LINE2LP
MIC2LM / LINE2LM
SW-L1
LINE1LP
SW-L0
LINE2LM
LEFT_LOP
SW-L3
LEFT_LOM
LINE1LP
SW-L4
LINE1LM
MIC1LP / LINE1LP
MIC1LM / LINE1LM
SW-L5
LINE2LM
LINE1LM
LINE1RP
SW-R2
MIC1RP / LINE1RP
MIC1RM / LINE1RM
LINE2RP
SW-R1
LINE1RP
LINE1RM
SW-R0
RIGHT_LOP
SW-R3
RIGHT_LOM
LINE2RP
SW-R4
LINE1RM
MIC2RP / LINE2RP
MIC2RM / LINE2RM
SW-R5
LINE2RM
LINE2RM
Figure 25. Passive Analog Bypass Mode Configuration
9.4.4 Digital Microphone Connectivity
The TLV320AIC3106-Q1 includes support for connection of a digital microphone to the device by routing the
digital signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the
host processor over the audio data serial bus.
When digital microphone mode is enabled, the TLV320AIC3106-Q1 provides an oversampling clock output for
use by the digital microphone to transmit its data. The TLV320AIC3106-Q1 includes the capability to latch the
data on either the rising, falling, or both edges of this supplied clock, enabling support for stereo digital
microphones.
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Device Functional Modes (continued)
In this mode, the oversampling ratio of the digital mic modulator can be programmed as 128, 64 or 32 times the
ADC sample rate, ADCFS. The GPIO1 pin outputs the serial oversampling clock at the programmed rate.
TLV320AIC3106-Q1 latches the data input on GPIO2 as the Left and Right channel digital microphone data. For
the Left channel input, GPIO2 is sampled on the rising edge of the clock, and for the Right channel input, GPIO2
is sampled on the falling edge of the clock. If a single digital mic channel is required then the corresponding ADC
channel must be powered up, and the unused channel must be powered down. When digital microphone mode is
enabled, neither ADC can be used for digitizing analog inputs.
Configuring the digital microphone configuration set up is done by writing to Page 0, Register 107, Bits D5 to D4,
and Register 25, Bits D5 to D4.
9.5 Programming
9.5.1 Hardware Reset
The TLV320AIC3106-Q1 requires a hardware reset after power-up for proper operation. After all power supplies
are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320AIC3106-Q1 may not respond properly to register reads and writes.
9.5.2 Digital Control Serial Interface
The TLV320AIC3106-Q1 control interface supports SPI or I2C communication protocols, with the protocol
selectable using the SELECT pin. For SPI, SELECT must be tied high; for I2C, SELECT must be tied low. The
state of SELECT must not be changed during device operation.
9.5.2.1 SPI Control Mode
SS
SCLK
MOSI
Hi-Z
RA(6)
RA(5)
RA(0)
7-bit Register Address
MISO
D(7)
D(6)
Write
D(0)
Hi-Z
8-bit Register Data
Hi-Z
Hi-Z
Figure 26. SPI Write
SS
SCLK
MOSI
Hi-Z
RA(6)
RA(5)
RA(0)
7-bit Register Address
MISO
Hi-Z
Hi-Z
Don’t Care
Read
8-bit Register Data
D(7)
D(6)
D(0)
Hi-Z
Figure 27. SPI Read
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Programming (continued)
In the SPI control mode, the TLV320AIC3106-Q1 uses the pins MFP0 = SSB, MFP1 = SCLK, MFP2 = MISO,
MFP3 = MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication from a host processor (the
master) to peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3106-Q1) depend on a master to start and synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the
slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI
pin, a byte shifts out on the MISO pin to the master shift register.
The TLV320AIC3106-Q1 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor
SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on
the first serial clock edge. The SSB pin can remain low between transmissions; however, the
TLV320AIC3106‑Q1 only interprets the first 8 bits transmitted after the falling edge of SSB as a command byte,
and the next 8 bits as a data byte only if writing to a register. Reserved register bits must be written to their
default values.
9.5.2.2 SPI Communication Protocol
The TLV320AIC3106-Q1 is entirely controlled by registers. Reading and writing these registers is accomplished
by the use of an 8-bit command, which is sent to the MOSI pin of the part before the data for that register. The
command is constructed as shown in Table 5. The first 7 bits specify the register address which is being written
or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data
flow on the serial bus. In the case of a register write, the R/W bit must be set to 0. A second byte of data is sent
to the MOSI pin and contains the data to be written to the register.
Reading of registers is accomplished in similar fashion. The 8-bit command word sends the 7-bit register
address, followed by R/W bit = 1 to signify a register read is occurring,. The 8-bit register data is then clocked out
of the part on the MISO pin during the second 8 SCLK clocks in the frame.
Table 5. Command Word
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
R/W
The register map of the TLV320AIC3106-Q1 actually consists of multiple pages of registers, with each page
containing 128 registers. The register at address zero on each page is used as a page-control register, and
writing to this register determines the active page for the device. All subsequent read or write operations
accesses the page that is active at the time, unless a register write is performed to change the active page. Only
two pages of registers are implemented in this product, with the active page defaulting to Page 0 upon device
reset.
For example, at device reset, the active page defaults to Page 0, and thus all register read and write operations
for addresses 1 to 127 accesses registers in Page 0. If registers on Page 1 must be accessed, the user must
write the 8-bit sequence 0x01 to Register 0, the page control register, to change the active page from Page 0 to
Page 1. After this write, TI recommends the user also read back the page control register, to safely ensure the
change in page control has occurred properly. Future read or write operations to addresses 1 to 127 now
accesses registers in Page 1. When Page 0 registers must be accessed again, the user writes the 8-bit
sequence 0x00 to Register 0, the page control register, to change the active page back to Page 0. After a read of
the page control register, all further read or write operations to addresses 1 to 127 now accesses Page 0
registers again.
9.5.2.2.1 Limitation On Register Writing
Do not use the auto-increment mode when writing in SPI mode to registers related to the audio output driver
properties such as mux, mix, and gain configuration. In addition, between two successive writes to these
registers, the host must keep MFP0 (SPI chip select) high for at least 6.25 µs, to ensure that the register writes
have occurred properly.
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9.5.2.3 Continuous Read and Write Operation
The TLV320AIC3106-Q1 includes the ability to read or write registers continuously, without requiring to provide
an address for every register accessed. In SPI mode, a continuous write is executed by transitioning MFP0 (SPI
chip select) low to start the frame, sending the first 8-bit command word to read or write a particular register, and
then sending multiple bytes of register data, intended for the addressed register and those following. A
continuous read is done similarly, with multiple bytes read in from the addressed register and the following
registers on the page. When the MFP0 (SPI chip select) pin is transitioned high again, the frame ends, as does
the continuous read and write operation. A new frame must begin again with a new command word, to start the
next bus transaction.
This continuous read and write operation does not continue past a page boundary. The user must not attempt to
read or write past the end of a page, because this may result in undesirable operation.
9.5.3 I2C Control Mode
The TLV320AIC3106-Q1 supports the I2C control protocol when the SELECT pin is tied low, using 7-bit
addressing and capable of both standard and fast modes. For I2C fast mode, note that the minimum timing for
each of tHD‑STA, tSU-STA, and tSU-STO is 0.9 µs, as seen in Figure 28. When in I2C control mode, the
TLV320AIC3106-Q1 can be configured for one of four different addresses, using the multifunction pins MFP0
and MFP1, which control the two LSBs of the device address. The 5 MSBs of the device address are fixed as
00110 and cannot be changed, while the two LSBs are given by MFP1:MFP0. This results in four possible device
addresses:
Table 6. I2C Slave Device Addresses For MFP1, MFP0
Settings
MFP1
MFP0
Device Address
0
0
0011000
0
1
0011001
1
0
0011010
1
1
0011011
SDA
tHD-STA ³ 0.9 ms
SCL
tSU-STA ³ 0.9 ms
tSU-STO ³ 0.9 ms
tHD-STA ³ 0.9 ms
S
Sr
P
S
T0114-02
Figure 28. I2C Interface Timing
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
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Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the TLV320AIC3106-Q1 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate
level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA
line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the
receivers shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Under normal circumstances the master drives the clock line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start a communication. They do this by
causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock
line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its
counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from
HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that indicates which slave device it wants to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. Slaves can also have 10-bit addresses; see the I2C specification for details. The master sends
an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the
slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW
to acknowledge this to the slave. It then sends a clock pulse to clock the bit.
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is
present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3106-Q1 also responds to and acknowledges a General Call, which consists of the master
issuing a command with a slave address byte of 00H.
SCL
DA(6)
SDA
Start
(M)
DA(0)
7-bit Device Address
(M)
RA(7)
Write
(M)
Slave
Ack
(S)
RA(0)
8-bit Register Address
(M)
D(7)
Slave
Ack
(S)
D(0)
8-bit Register Data
(M)
Slave
Ack
(S)
Stop
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 29. I2C Write
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SCL
DA(6)
SDA
Start
(M)
DA(0)
7-bit Device Address
(M)
RA(7)
Write
(M)
Slave
Ack
(S)
DA(6)
RA(0)
8-bit Register Address
(M)
Slave
Ack
(S)
Repeat
Start
(M)
DA(0)
7-bit Device Address
(M)
D(7)
Read
(M)
Slave
Ack
(S)
8-bit Register Data
(S)
D(0)
Master
No Ack
(M)
Stop
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 30. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters autoincrement mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next 8 clocks the data of the next incremental register.
9.5.4 I2C Bus Debug In A Glitched System
Occasionally, some systems may encounter noise or glitches on the I2C bus. In the unlikely event that this
affects bus performance, then it can be useful to use the I2C Debug register. This feature terminates the I2C bus
error allowing this I2C device and system to resume communications. The I2C bus error detector is enabled by
default. The TLV320AIC3106-Q1 I2C error detector status can be read from Page 0, Register 107, Bit D0. If
desired, the detector can be disabled by writing to Page 0, Register 107, Bit D2.
9.5.5 Digital Audio Data Serial Interface
Audio data is transferred from the host processor to the TLV320AIC3106-Q1 through the digital audio data serial
interface, or audio bus. The audio bus on this device is very flexible, including left or right justified data options,
support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,
very flexible master and slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The data serial interface uses two sets of pins for communication between external devices, with the particular
pin used controlled through register programming. This configuration is shown in Figure 31 below.
WCLK
GPIO1 GPIO2
BCLK
DIN DOUT
MFP3
Audio Serial Data Bus
Figure 31. Alternate Audio Bus Mulitplexing Function
In cases where MFP3 is required for a secondary device digital input, the TLV320AIC3106-Q1 must be used in
I2C mode (when in SPI mode, MFP3 is used as the SPI bus MOSI pin and thus cannot be used here as an
alternate digital input source).
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This mux capability allows the TLV320AIC3106-Q1 to communicate with two separate devices with independent
I2S/PCM buses. Figure 32 shows an application example with an infotainment system that contains a Bluetooth
transceiver and uses a PCM/I2S interface. The applications processor can be connected to the WCLK, BCLK,
DIN, DOUT pins on the TLV320AIC3106-Q1, while a Bluetooth device with PCM interface can be connected to
the GPIO1, GPIO2, MFP3, and DOUT pins on the TLV320AIC3106-Q1. By programming the registers through
I2C control, the applications processor can determine which device is communicating with the TLV320AIC3106Q1. This is attractive in cases where the TLV320AIC3106-Q1 can be configured to communicate data with the
Bluetooth device, then the applications processor can be put into a low power sleep mode, while voice and audio
transmission still occurs between the Bluetooth device and the TLV320AIC3106-Q1.
GPIO2
GPIO1
MFP3
DOUT
Processor
2
DIN
BCLK
WCLK
Processor
1
AIC3106
Possible Processor Types:
Application Processor, Multimedia Processor,
Compressed Audio Decoder, Wireless Modem,
Bluetooth Module, Additional Audio/Voice Codec
Figure 32. TLV320AIC3106-Q1 Connected To Multiple Audio Devices
The audio bus of the TLV320AIC3106-Q1 can be configured for left or right justified, I2S, DSP, or TDM modes of
operation, where communication with standard audio PCM interfaces is supported within the TDM mode. These
modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock
(WCLK or GPIO1) and bit clock (BCLK or GPIO2) can be independently configured in either Master or Slave
mode, for flexible connectivity to a wide variety of processors.
The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC
and DAC sampling frequencies.
The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in
Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are
generated, so in general the number of bit clocks per frame is two times the data width. For example, if data
width is chosen as 16-bits, then 32-bit clocks is generated per frame. If the bit clock signal in master mode is
used by a PLL in another device, TI recommends the 16-bit or 32-bit data width selections be used. These cases
result in a low jitter bit clock signal being generated, having frequencies of 32 × fS or 64 × fS. In the cases of
20‑bit and 24-bit data width in master mode, the bit clocks generated in each frame are not all be of equal period,
due to the device not having a clean 40 × fS or 48 × fS clock signal readily available. The average frequency of
the bit clock signal is still accurate in these cases (being 40 × fS or 48 × fS), but the resulting clock signal has
higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256-bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3106-Q1 further includes programmability to 3 state the DOUT line during all bit clocks when
valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame
the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to
use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface are put into a 3-state output condition.
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9.5.6 Right-Justified Mode
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
1/fs
WCLK
BCLK
Left Channel
SDIN/
SDOUT
0
n−1 n−2 n−3
MSB
Right Channel
2
1
0
n−1 n−2 n−3
2
1
0
LSB
Figure 33. Right-Justified Serial Bus Mode Operation
9.5.7 Left-Justified Mode
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
n-1 n-2 n-3
n-1 n-2 n-3
Figure 34. Left-Justified Serial Data Bus Mode Operation
9.5.8 I2S Mode
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
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n-1 n-2 n-3
n-1 n-2 n-3
Figure 35. I2S Serial Data Bus Mode Operation
9.5.9 DSP Mode
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
1/fs
WCLK
BCLK
Right Channel
Left Channel
SDIN/SDOUT
n–1 n–2 n–3 n–4
LSB MSB
2
1
0
n–1 n–2 n–3
LSB MSB
2
1
0
n–1
LSB
T0152-01
Figure 36. DSP Serial Bus Mode Operation
9.5.10 TDM Data Transfer
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, but TI recommends the use of either left-justified mode or DSP mode. By changing the
programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data
output driver (DOUT) can also be programmed to 3 state during all bit clocks except when valid data is being put
onto the bus. This allows other codecs to be programmed with different offsets and to drive their data onto the
same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except
where it is expected based on the programmed offset.
The location of the data when an offset is programmed is different, depending on what transfer mode is selected.
In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in the
frame. This differs from left-justified mode, where the left and right channel data are always a half-frame apart in
each frame. In this case, as the offset is programmed from zero to some higher value, both the left and right
channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
Figure 37 for the two cases.
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DSP Mode
word
clock
bit clock
data
in/out
N-1
N-2
1
Left Channel Data
offset
0
N-1
N-2
1
0
Right Channel Data
Left Justified Mode
word
clock
bit clock
data
in/out
N-1
offset
N-2
1
Left Channel Data
0
N-1
offset
N-2
1
0
Right Channel Data
Figure 37. DSP Mode And Left Justified Modes, Showing The
Effect Of A Programmed Data Word Offset
9.5.11 Audio Clock Generation
The audio converters in the TLV320AIC3106-Q1 require an internal audio master clock at a frequency of 256 ×
fS(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC3106-Q1 is shown in Figure 38.
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MCLK
BCLK
GPIO2
CLKDIV_CLKIN
PLL_CLKIN
CLKDIV_IN
Q=2,3,…..,16,17
PLL_IN
K = J.D
J = 1,2,3,…..,62,63
D= 0000,0001,….,9998,9999
R= 1,2,3,4,….,15,16
P= 1,2,….,7,8
K*R/P
2/Q
PLL_OUT
CLKDIV_OUT
1/8
PLLDIV_OUT
CLKMUX _OUT
CODEC_CLKIN
CODEC_CLK=256*Fsref
CLKOUT_IN
M =1,2,4,8
N = 2,3,……,16,17
2/(N*M)
CLKOUT
CODEC
DAC_FS
GPIO1
ADC_FS
WCLK = Fsref/ Ndac
GPIO1 = Fsref/ Nadc
Ndac=1,1.5,2,…..,5.5,6
DAC DRA => Ndac = 0.5
Nadc=1,1.5,2,…..,5.5,6
ADC DRA => Nadc = 0.5
Figure 38. Audio Clock Generation Processing
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock required by the part. The BCLK or
GPIO2 inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not
powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting output
clock driven out GPIO1, for use by other devices in the system.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is disabled:
fS(ref) = CLKDIV_IN / (128 × Q)
where
•
•
46
Q = 2, 3, …, 17
CLKDIV_IN can be MCLK, BCLK, or GPIO2, selected by Register 102, Bits D7 to D6
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NOTE
When NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode,
MCLK can be as high as 50 MHz, and fS(ref) must fall within 39 kHz to 53 kHz.
When the PLL is enabled:
fS(ref) = (PLLCLK_IN × K × R) / (2048 × P)
where
•
•
•
•
•
•
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, Register 102, Bits D5 to D4
(5)
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R=1
Example:
MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Table 7 lists several example cases of typical MCLK rates and how to program the PLL to achieve
fS(ref) = 44.1 kHz or 48 kHz.
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Table 7. Typical MCLK Rates
fS(ref) = 44.1 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
2.8224
1
1
32
0
44100.00
0.0000
5.6448
1
1
16
0
44100.00
0.0000
12
1
1
7
5264
44100.00
0.0000
13
1
1
6
9474
44099.71
–0.0007
16
1
1
5
6448
44100.00
0.0000
19.2
1
1
4
7040
44100.00
0.0000
19.68
1
1
4
5893
44100.30
0.0007
48
4
1
7
5264
44100.00
0.0000
fS(ref) = 48 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
2.048
1
1
48
0
48000.00
0.0000
3.072
1
1
32
0
48000.00
0.0000
4.096
1
1
24
0
48000.00
0.0000
6.144
1
1
16
0
48000.00
0.0000
8.192
1
1
12
0
48000.00
0.0000
12
1
1
8
1920
48000.00
0.0000
13
1
1
7
5618
47999.71
–0.0006
16
1
1
6
1440
48000.00
0.0000
19.2
1
1
5
1200
48000.00
0.0000
19.68
1
1
4
9951
47999.79
–0.0004
48
4
1
8
1920
48000.00
0.0000
The TLV320AIC3106-Q1 can also output a separate clock on the GPIO1 pin. If the PLL is being used for the
audio data converter clock, the M and N settings can be used to provide a divided version of the PLL output. If
the PLL is not being used for the audio data converter clock, the PLL can still be enabled to provide a completely
independent clock output on GPIO1. The formula for the GPIO1 clock output when PLL is enabled and
CLKMUX_OUT is 0 is:
GPIO1 = (PLLCLK_IN × 2 × K × R) / (M × N × P)
(6)
When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output divider
can be selected as MCLK, BCLK, or GPIO2. Is this case, the formula for the GPIO1 clock is:
GPIO1 = (CLKDIV_IN × 2) / (M × N)
where
•
•
•
48
M = 1, 2, 4, 8
N = 2, 3, …, 17
CLKDIV_IN can be BCLK, MCLK, or GPIO2, selected by Page 0, Register 102, Bits D7 to D6
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9.6 Register Maps
The control registers for the TLV320AIC3106-Q1 are described in detail below. All registers are 8 bits in width,
with D7 referring to the most significant bit of each register, and D0 referring to the least significant bit.
Table 8. Page 0, Register 0: Page Select Register
BIT
READ/
WRITE
RESET
VALUE
D7–D1
X
0000 000
Reserved, write only zeros to these bits.
0
Page Select Bit
Writing zero to this bit sets Page 0 as the active page for following register accesses. Writing a one to this
bit sets Page 1 as the active page for following register accesses. TI recommends the user read this
register bit back after each write, to ensure that the proper page is being accessed for future register read
and writes.
D0
R/W
DESCRIPTION
When resetting registers related to routing and volume controls of output drivers, TI recommends reseting them
by writing directly to the registers instead of using software reset.
Table 9. Page 0, Register 1: Software Reset Register
BIT
READ/
WRITE
RESET
VALUE
D7
W
0
D6–D0
W
000 0000
DESCRIPTION
Software Reset Bit
0 : Do Not Care
1 : Self clearing software reset
Reserved, write only zeros to these bits.
Table 10. Page 0, Register 2: Codec Sample Rate Select Register
BIT
D7–D4
D3–D0
READ/
WRITE
R/W
R/W
RESET
VALUE
DESCRIPTION
0000
ADC Sample Rate Select
0000: ADC fS = fS(ref) / 1
0001: ADC fS = fS(ref) / 1.5
0010: ADC fS = fS(ref) / 2
0011: ADC fS = fS(ref) / 2.5
0100: ADC fS = fS(ref) / 3
0101: ADC fS = fS(ref) / 3.5
0110: ADC fS = fS(ref) / 4
0111: ADC fS = fS(ref) / 4.5
1000: ADC fS = fS(ref) / 5
1001: ADC fS = fS(ref) / 5.5
1010: ADC fS = fS(ref) / 6
1011–1111: Reserved, do not write these sequences.
0000
DAC Sample Rate Select
0000 : DAC fS = fS(ref) / 1
0001 : DAC fS = fS(ref) / 1.5
0010 : DAC fS = fS(ref) / 2
0011 : DAC fS = fS(ref) / 2.5
0100 : DAC fS = fS(ref) / 3
0101 : DAC fS = fS(ref) / 3.5
0110 : DAC fS = fS(ref) / 4
0111 : DAC fS = fS(ref) / 4.5
1000 : DAC fS = fS(ref) / 5
1001: DAC fS = fS(ref) / 5.5
1010: DAC fS = fS(ref) / 6
1011–1111: Reserved, do not write these sequences.
Table 11. Page 0, Register 3: PLL Programming Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DESCRIPTION
PLL Control Bit
0: PLL is disabled
1: PLL is enabled
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Table 11. Page 0, Register 3: PLL Programming Register A (continued)
BIT
D6–D3
D2–D0
READ/
WRITE
R/W
R/W
RESET
VALUE
DESCRIPTION
0010
PLL Q Value
0000: Q = 16
0001 : Q = 17
0010 : Q = 2
0011 : Q = 3
0100 : Q = 4
…
1110: Q = 14
1111: Q = 15
000
PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
Table 12. Page 0, Register 4: PLL Programming Register B
BIT
READ/
WRITE
RESET
VALUE
D7–D2
R/W
0000 01
D1–D0
R/W
00
DESCRIPTION
PLL J Value
0000 00: Reserved, do not write this sequence.
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
Reserved, write only zeros to these bits.
Table 13. Page 0, Register 5: PLL Programming Register C
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0000 0000
DESCRIPTION
PLL D value: Eight most significant bits of a 14-bit unsigned integer valid values for D are from zero to
9999, represented by a 14-bit integer located in Page 0, Registers 5 to 6. Values must not be written into
these registers that would result in a D value outside the valid range.
Whenever the D value is changed, Register 5 must be written, immediately followed by Register 6. Even if only
the MSB or LSB of the value changes, both registers must be written.
Table 14. Page 0, Register 6: PLL Programming Register D
BIT
READ/
WRITE
RESET
VALUE
D7–D2
R/W
0000 0000
PLL D value: Six least significant bits of a 14-bit unsigned integer valid values for D are from zero to
9999, represented by a 14-bit integer located in Page 0, Registers 5 to 6. Values must not be written into
these registers that would result in a D value outside the valid range.
D1–D0
R
00
Reserved, write only zeros to these bits.
DESCRIPTION
Table 15. Page 0, Register 7: Codec Datapath Setup Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
fS(ref) setting
This register setting controls timers related to the AGC time constants.
0: fS(ref) = 48 kHz
1: fS(ref) = 44.1 kHz
D6
R/W
0
ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
ADC Dual Rate Mode must match DAC Dual Rate Mode
50
DESCRIPTION
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Table 15. Page 0, Register 7: Codec Datapath Setup Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D5
R/W
0
DAC Dual Rate Control
0: DAC dual rate mode is disabled
1: DAC dual rate mode is enabled
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D4–D3
R/W
DESCRIPTION
D2–D1
R/W
00
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0
R/W
0
Reserved, write only zero to this bit.
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Bit Clock Directional Control
0: BCLK (or GPIO2 if programmed as BCLK) is an input (slave mode)
1: BCLK (or GPIO2 if programmed as BCLK) is an output (master mode)
D6
R/W
0
Word Clock Directional Control
0: WCLK (or GPIO1 if programmed as WCLK) is an input (slave mode)
1: WCLK (or GPIO1 if programmed as WCLK) is an output (master mode)
D5
R/W
0
Serial Output Data Driver (DOUT) 3-State Control
0: Do not place DOUT in high-impedance state when valid data is not being sent
1: Place DOUT in high-impedance state when valid data is not being sent
Table 16. Page 0, Register 8: Audio Serial Data Interface Control Register A
DESCRIPTION
D4
R/W
0
Bit/Word Clock Drive Control
0: BCLK (or GPIO2 if programmed as BCLK) / WCLK (or GPIO1 if programmed as WCLK) does not
continue to be transmitted when running in master mode if codec is powered down
1: BCLK (or GPIO2 if programmed as BCLK) / WCLK (or GPIO1 if programmed as WCLK) continues to
be transmitted when running in master mode, even if codec is powered down
D3
R/W
0
Reserved, write only zero to this bit.
D2
R/W
0
3D Effect Control
0: Disable 3D digital effect processing
1: Enable 3D digital effect processing
00
Digital Microphone Functionality Control
00: Digital microphone support is disabled
01: Digital microphone support is enabled with an oversampling rate of 128
10: Digital microphone support is enabled with an oversampling rate of 64
11: Digital microphone support is enabled with an oversampling rate of 32
D1–D0
R/W
Table 17. Page 0, Register 9: Audio Serial Data Interface Control Register B
BIT
D7–D6
D5–D4
D3
READ/
WRITE
R/W
R/W
R/W
RESET
VALUE
DESCRIPTION
00
Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
00
Audio Serial Data Word Length Control
00: Audio data word length = 16 bits
01: Audio data word length = 20 bits
10: Audio data word length = 24 bits
11: Audio data word length = 32 bits
0
Bit Clock Rate Control
This register only has effect when bit clock is programmed as an output
0: Continuous-transfer mode used to determine master mode bit clock rate
1: 256-clock transfer mode used, resulting in 256-bit clocks per frame
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Table 17. Page 0, Register 9: Audio Serial Data Interface Control Register B (continued)
BIT
READ/
WRITE
RESET
VALUE
D2
R/W
0
DAC Re-Sync
0: Do Not Care
1: Re-sync stereo DAC with codec interface if the group delay changes by more than ±DACFS / 4.
D1
R/W
0
ADC Re-Sync
0: Do Not Care
1: Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADCFS / 4.
D0
R/W
DESCRIPTION
Re-Sync Mute Behavior
0: Re-sync is done without soft-muting the channel. (ADC and DAC)
1: Re-sync is done by internally soft-muting the channel. (ADC and DAC)
Table 18. Page 0, Register 10: Audio Serial Data Interface Control Register C
BIT
D7–D0
READ/
WRITE
R/W
RESET
VALUE
0000 0000
DESCRIPTION
Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling the offset
from beginning of the frame where valid data begins. The offset is measured from the rising edge of word
clock when in DSP mode.
0000 0000: Data offset = 0-bit clocks
0000 0001: Data offset = 1-bit clock
0000 0010: Data offset = 2-bit clocks
…
In continuous transfer mode the maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSP mode. In
256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes.
1111 1110: Data offset = 254-bit clocks
1111 1111: Data offset = 255-bit clocks
Table 19. Page 0, Register 11: Audio Codec Overflow Flag Register
BIT
D7
D6
D5
D4
D3–D0
52
READ/
WRITE
R
R
R
R
R/W
RESET
VALUE
DESCRIPTION
0
Left ADC Overflow Flag
This is a sticky bit, so stays set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
0
Right ADC Overflow Flag
This is a sticky bit, so stays set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
0
Left DAC Overflow Flag
This is a sticky bit, so stays set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
0
Right DAC Overflow Flag
This is a sticky bit, so stays set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
0001
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
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Table 20. Page 0, Register 12: Audio Codec Digital Filter Control Register
READ/
WRITE
BIT
D7–D6
R/W
RESET
VALUE
DESCRIPTION
00
Left ADC Highpass Filter Control
00: Left ADC highpass filter disabled
01: Left ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Left ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Left ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D5–D4
R/W
00
Right ADC Highpass Filter Control
00: Right ADC highpass filter disabled
01: Right ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Right ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Right ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D3
R/W
0
Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2
R/W
0
Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1
R/W
0
Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0
R/W
0
Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Table 21. Page 0, Register 13: Headset and Button Press Detection Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
00
Headset Type Detection Results
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
000
Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110: Reserved, do not write this sequence.
111: Reserved, do not write this sequence.
00
Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0 ms
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
D6–D5
D4–D2
D1–D0
R
R/W
R/W
DESCRIPTION
Table 22. Page 0, Register 14: Headset and Button Press Detection Register B
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for AC-coupled driver configuration
D6 (1)
R/W
0
Stereo Output Driver Configuration A
Do not set Bits D6 and D3 both high at the same time.
0: A stereo fully differential output configuration is not being used
1: A stereo fully differential output configuration is being used
(1)
DESCRIPTION
Do not set D6 and D3 to 1 simultaneously
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Table 22. Page 0, Register 14: Headset and Button Press Detection Register B (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D5
R
0
Button Press Detection Flag
This register is a sticky bit, and stays set to 1 after a button press has been detected, until the register is
read. Upon reading this register, the bit is reset to zero.
0: A button press has not been detected
1: A button press has been detected
D4
R
0
Headset Detection Flag
0: A headset has not been detected
1: A headset has been detected
D3 (1)
R/W
0
Stereo Output Driver Configuration B
Do not set Bits D6 and D3 both high at the same time.
0: A stereo pseudodifferential output configuration is not being used
1: A stereo pseudodifferential output configuration is being used
D2–D0
R
000
Reserved, write only zeros to these bits.
Table 23. Page 0, Register 15: Left ADC PGA Gain Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
000 0000
Left ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
0000010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
D6–D0
R/W
DESCRIPTION
Table 24. Page 0, Register 16: Right ADC PGA Gain Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
Right ADC PGA Mute
0: The right ADC PGA is not muted
1: The right ADC PGA is muted
000 0000
Right ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
D6–D0
R/W
DESCRIPTION
Table 25. Page 0, Register 17: MIC3L/R To Left ADC Control Register
BIT
D7–D4
54
READ/
WRITE
R/W
RESET
VALUE
1111
DESCRIPTION
MIC3L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: MIC3L is not connected to the left ADC PGA
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Table 25. Page 0, Register 17: MIC3L/R To Left ADC Control Register (continued)
BIT
D3–D0
READ/
WRITE
R/W
RESET
VALUE
1111
DESCRIPTION
MIC3R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: MIC3R is not connected to the left ADC PGA
Table 26. Page 0, Register 18: MIC3L/R To Right ADC Control Register
BIT
D7–D4
D3–D0
READ/
WRITE
R/W
R/W
RESET
VALUE
DESCRIPTION
1111
MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: MIC3L is not connected to the right ADC PGA
1111
MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: MIC3R is not connected to right ADC PGA
Table 27. Page 0, Register 19: LINE1L To Left ADC Control Register
BIT
D7
D6–D3
READ/
WRITE
R/W
R/W
RESET
VALUE
DESCRIPTION
0
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
1111
LINE1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE1L is not connected to the left ADC PGA
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Table 27. Page 0, Register 19: LINE1L To Left ADC Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D2
R/W
0
Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1–D0
R/W
00
Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per fS
01: Left ADC PGA soft-stepping at once per two fS
10–11: Left ADC PGA soft-stepping is disabled
DESCRIPTION
Table 28. Page 0, Register 20: LINE2L To Left (1) ADC Control Register
READ/
WRITE
BIT
D7
R/W
RESET
VALUE
DESCRIPTION
0
LINE2L Single-Ended vs Fully Differential Control
If LINE2L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2L is configured in single-ended mode
1: LINE2L is configured in fully differential mode
D6–D3
R/W
1111
LINE2L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE2L is not connected to the left ADC PGA
D2
R/W
0
Left ADC Channel Weak Common-Mode Bias Control
0: Left ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1: Left ADC channel unselected inputs are biased weakly to the ADC common-mode voltage
D1–D0
R
00
Reserved, write only zeros to these bits.
(1)
LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels.
Table 29. Page 0, Register 21: LINE1R To Left ADC Control Register
BIT
D7
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3
R/W
1111
LINE1R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE1R is not connected to the left ADC PGA
D2–D0
R
000
Reserved, write only zeros to these bits.
56
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Table 30. Page 0, Register 22: LINE1R To Right ADC Control Register
BIT
D7
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3
R/W
1111
LINE1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE1R is not connected to the right ADC PGA
D2
R/W
0
Right ADC Channel Power Control
0: Right ADC channel is powered down
1: Right ADC channel is powered up
D1–D0
R/W
00
Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per fS
01: Right ADC PGA soft-stepping at once per two fS
10–11: Right ADC PGA soft-stepping is disabled
Table 31. Page 0, Register 23: LINE2R To Right ADC Control Register
BIT
D7
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
0
LINE2R Single-Ended vs Fully Differential Control
If LINE2R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2R is configured in single-ended mode
1: LINE2R is configured in fully differential mode
D6–D3
R/W
1111
LINE2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE2R is not connected to the right ADC PGA
D2
R/W
0
Right ADC Channel Weak Common-Mode Bias Control
0: Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1: Right ADC channel unselected inputs are biased weakly to the ADC common-mode voltage
D1–D0
R
00
Reserved, write only zeros to these bits.
Table 32. Page 0, Register 24: LINE1L To Right ADC Control Register
BIT
D7
READ/
WRITE
R/W
RESET
VALUE
0
DESCRIPTION
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
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Table 32. Page 0, Register 24: LINE1L To Right ADC Control Register (continued)
READ/
WRITE
BIT
RESET
VALUE
D6–D3
R/W
1111
D2–D0
R
000
DESCRIPTION
LINE1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved, do not write these sequences.
1111: LINE1L is not connected to the right ADC PGA
Reserved, write only zeros to these bits.
Table 33. Page 0, Register 25: MICBIAS Control Register
READ/
WRITE
BIT
D7–D6
R/W
RESET
VALUE
DESCRIPTION
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
D5–D4
R/W
00
Digital Microphone Control
00: If Digital MIC is enabled, both Left and Right Digital MICs are available
01: If Digital MIC is enabled, Left Digital MIC and Right ADC are available
10: If Digital MIC is enabled, Left ADC and Right Digital MIC are available
11: Reserved, do not write this sequence.
D3
R
0
Reserved, write only zero to this bit.
D2–D0
R
XXX
Reserved, write only zeros to these bits.
Table 34. Page 0, Register 26: Left AGC Control Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Left AGC Enable
0: Left AGC is disabled
1: Left AGC is enabled
000
Left AGC Target Level
000: Left AGC target level
001: Left AGC target level
010: Left AGC target level
011: Left AGC target level
100: Left AGC target level
101: Left AGC target level
110: Left AGC target level
111: Left AGC target level
00
Left AGC Attack Time
These time constants (1) are not accurate when double rate audio mode is enabled.
00: Left AGC attack time = 8 ms
01: Left AGC attack time = 11 ms
10: Left AGC attack time = 16 ms
11: Left AGC attack time = 20 ms
00
Left AGC Decay Time
These time constants (1) are not accurate when double rate audio mode is enabled.
00: Left AGC decay time = 100 ms
01: Left AGC decay time = 200 ms
10: Left AGC decay time = 400 ms
11: Left AGC decay time = 500 ms
D6–D4
D3–D2
D1–D0
(1)
58
R/W
R/W
R/W
DESCRIPTION
=
=
=
=
=
=
=
=
–5.5 dB
–8 dB
–10 dB
–12 dB
–14 dB
–17 dB
–20 dB
–24 dB
Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
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Table 35. Page 0, Register 27: Left AGC Control Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D1
R/W
1111 111
Left AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
D0
R/W
0
Reserved, write only zero to this bit.
Table 36. Page 0, Register 28: Left AGC Control Register C
BIT
D7–D6
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
00
Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled
D5–D1
R/W
00 000
Left AGC Noise Threshold Control
00 000: Left AGC Noise/Silence Detection disabled
00 001: Left AGC noise threshold = –30 dB
00 010: Left AGC noise threshold = –32 dB
00 011: Left AGC noise threshold = –34 dB
…
11 101: Left AGC noise threshold = –86 dB
11 110: Left AGC noise threshold = –88 dB
11 111: Left AGC noise threshold = –90 dB
D0
R/W
0
Left AGC Clip Stepping Control
0: Left AGC clip stepping disabled
1: Left AGC clip stepping enabled
Table 37. Page 0, Register 29: Right AGC Control Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Right AGC Enable
0: Right AGC is disabled
1: Right AGC is enabled
000
Right AGC Target Level
000: Right AGC target level
001: Right AGC target level
010: Right AGC target level
011: Right AGC target level
100: Right AGC target level
101: Right AGC target level
110: Right AGC target level
111: Right AGC target level
00
Right AGC Attack Time
These time constants are not accurate when double rate audio mode is enabled.
00: Right AGC attack time = 8 ms
01: Right AGC attack time = 11 ms
10: Right AGC attack time = 16 ms
11: Right AGC attack time = 20 ms
00
Right AGC Decay Time
These time constants are not accurate when double rate audio mode is enabled.
00: Right AGC decay time = 100 ms
01: Right AGC decay time = 200 ms
10: Right AGC decay time = 400 ms
11: Right AGC decay time = 500 ms
D6–D4
D3–D2
D1–D0
R/W
R/W
R/W
DESCRIPTION
=
=
=
=
=
=
=
=
–5.5 dB
–8 dB
–10 dB
–12 dB
–14 dB
–17 dB
–20 dB
–24 dB
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Table 38. Page 0, Register 30: Right AGC Control Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D1
R/W
1111 111
Right AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
D0
R/W
0
Reserved, write only zero to this bit.
Table 39. Page 0, Register 31: Right AGC Control Register C
BIT
D7–D6
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
00
Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled
D5–D1
R/W
00 000
Right AGC Noise Threshold Control
00 000: Right AGC Noise/Silence Detection disabled
00 001: Right AGC noise threshold = –30 dB
00 010: Right AGC noise threshold = –32 dB
00 011: Right AGC noise threshold = –34 dB
…
11 101: Right AGC noise threshold = –86 dB
11 110: Right AGC noise threshold = –88 dB
11 111: Right AGC noise threshold = –90 dB
D0
R/W
0
Right AGC Clip Stepping Control
0: Right AGC clip stepping disabled
1: Right AGC clip stepping enabled
Table 40. Page 0, Register 32: Left AGC Gain Register
BIT
D7–D0
READ/
WRITE
R
RESET
VALUE
0000 0000
DESCRIPTION
Left Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
Table 41. Page 0, Register 33: Right AGC Gain Register
BIT
D7–D0
60
READ/
WRITE
R
RESET
VALUE
0000 0000
DESCRIPTION
Right Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
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Table 42. Page 0, Register 34: Left AGC Noise Gate Debounce Register
READ/
WRITE
BIT
D7–D3
D2–D0
(1)
R/W
R/W
RESET
VALUE
DESCRIPTION
0000 0
Left AGC Noise Detection Debounce Control
These times (1) are not accurate when double rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1472 ms
1111 1: Debounce = 64 × 24 = 1536 ms
000
Left AGC Signal Detection Debounce Control
These times (1) are not accurate when double rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
Time constants are valid when DRA is not enabled. The values would change when DRA is enabled
Table 43. Page 0, Register 35: Right AGC Noise Gate Debounce Register
READ/
WRITE
BIT
D7–D3
D2–D0
(1)
R/W
R/W
RESET
VALUE
DESCRIPTION
0000 0
Right AGC Noise Detection Debounce Control
These times (1) are not accurate when double rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1472 ms
1111 1: Debounce = 64 × 24 = 1536 ms
000
Right AGC Signal Detection Debounce Control
These times (1) are not accurate when double rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
Table 44. Page 0, Register 36: ADC Flag Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
DESCRIPTION
Left ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
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Table 44. Page 0, Register 36: ADC Flag Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D6
R
0
Left ADC Power Status
0: Left ADC is in a power down state
1: Left ADC is in a power up state
D5
R
0
Left AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D4
R
0
Left AGC Saturation Flag
0: Left AGC is not saturated
1: Left AGC gain applied = maximum allowed gain for left AGC
D3
R
0
Right ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D2
R
0
Right ADC Power Status
0: Right ADC is in a power down state
1: Right ADC is in a power up state
D1
R
0
Right AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D0
R
0
Right AGC Saturation Flag
0: Right AGC is not saturated
1: Right AGC gain applied = maximum allowed gain for right AGC
DESCRIPTION
Table 45. Page 0, Register 37: DAC Power And Output Driver Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Left DAC Power Control
0: Left DAC not powered up
1: Left DAC is powered up
D6
R/W
0
Right DAC Power Control
0: Right DAC not powered up
1: Right DAC is powered up
DESCRIPTION
D5–D4
R/W
00
HPLCOM Output Driver Configuration Control
00: HPLCOM configured as differential of HPLOUT
01: HPLCOM configured as constant VCM output
10: HPLCOM configured as independent single-ended output
11: Reserved, do not write this sequence.
D3–D0
R
000
Reserved, write only zeros to these bits.
Table 46. Page 0, Register 38: High-Power Output Driver Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R
00
Reserved, write only zeros to these bits.
DESCRIPTION
D5–D3
R/W
000
HPRCOM Output Driver Configuration Control
000: HPRCOM configured as differential of HPROUT
001: HPRCOM configured as constant VCM output
010: HPRCOM configured as independent single-ended output
011: HPRCOM configured as differential of HPLCOM
100: HPRCOM configured as external feedback with HPLCOM as constant VCM output
101–111: Reserved, do not write these sequences.
D2
R/W
0
Short Circuit Protection Control
0: Short circuit protection on all high power output drivers is disabled
1: Short circuit protection on all high power output drivers is enabled
D1
R/W
0
Short-Circuit Protection Mode Control
0: If short circuit protection enabled, it limits the maximum current to the load
1: If short circuit protection enabled, it powers down the output driver automatically when a short is
detected
D0
R
0
Reserved, write only zero to this bit.
62
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Table 47. Page 0, Register 39: Reserved Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
DESCRIPTION
Reserved, do not write to this register.
Table 48. Page 0, Register 40: High Power Output Stage Control Register
BIT
D7–D6
D5–D4
D3–D2
D1–D0
READ/
WRITE
R/W
R/W
R/W
R/W
RESET
VALUE
DESCRIPTION
00
Output Common-Mode Voltage Control
00: Output common-mode voltage = 1.35 V
01: Output common-mode voltage = 1.5 V
10: Output common-mode voltage = 1.65 V
11: Output common-mode voltage = 1.8 V
00
LINE2L Bypass Path Control
00: LINE2L bypass is disabled
01: LINE2L bypass uses LINE2LP single-ended
10: LINE2L bypass uses LINE2LM single-ended
11: LINE2L bypass uses LINE2LP/M differentially
00
LINE2R Bypass Path Control
00: LINE2R bypass is disabled
01: LINE2R bypass uses LINE2RP single-ended
10: LINE2R bypass uses LINE2RM single-ended
11: LINE2R bypass uses LINE2RP/M differentially
00
Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per fS
01: Output soft-stepping = one step per 2 fS
10: Output soft-stepping disabled
11: Reserved, do not write this sequence.
Table 49. Page 0, Register 41: DAC Output Switching Control Register
BIT
D7–D6
READ/
WRITE
R/W
RESET
VALUE
DESCRIPTION
00
Left DAC Output Switching Control
00: Left DAC output selects DAC_L1 path
01: Left DAC output selects DAC_L3 path to left line output driver
10: Left DAC output selects DAC_L2 path to left high power output drivers
11: Reserved, do not write this sequence.
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high power output drivers
11: Reserved, do not write this sequence.
D3–D2
R/W
00
Reserved, write only zeros to these bits.
00
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
D1–D0
R/W
Table 50. Page 0, Register 42: Output Driver Pop Reduction Register
BIT
D7–D4
READ/
WRITE
R/W
RESET
VALUE
0000
DESCRIPTION
Output Driver Power-On Delay Control
0000: Driver power-on time = 0 μs
0001: Driver power-on time = 10 μs
0010: Driver power-on time = 100 μs
0011: Driver power-on time = 1 ms
0100: Driver power-on time = 10 ms
0101: Driver power-on time = 50 ms
0110: Driver power-on time = 100 ms
0111: Driver power-on time = 200 ms
1000: Driver power-on time = 400 ms
1001: Driver power-on time = 800 ms
1010: Driver power-on time = 2 s
1011: Driver power-on time = 4 s
1100–1111: Reserved, do not write these sequences.
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Table 50. Page 0, Register 42: Output Driver Pop Reduction Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D3–D2
R/W
00
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 1 ms
10: Driver ramp-up step time = 2 ms
11: Driver ramp-up step time = 4 ms
D1
R/W
0
Weak Output Common-mode Voltage Control
0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply
1: Weakly driven output common-mode voltage is generated from bandgap reference
D0
R/W
0
Reserved, write only zero to this bit.
Table 51. Page 0, Register 43: Left DAC Digital Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
Left DAC Digital Mute
0: The left DAC channel is not muted
1: The left DAC channel is muted
000 0000
Left DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
D6–D0
R/W
DESCRIPTION
Table 52. Page 0, Register 44: Right DAC Digital Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
Right DAC Digital Mute
0: The right DAC channel is not muted
1: The right DAC channel is muted
000 0000
Right DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
D6–D0
R/W
DESCRIPTION
9.6.1 Output Stage Volume Controls
A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output
stage network, connected to each of the analog signals that route to the output stage. In addition, to enable
completely independent mixing operations to be performed for each output driver, each analog signal coming into
the output stage may have up to seven separate volume controls. These volume controls all have approximately
0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations.
Table 53 lists the detailed gain versus programmed setting for this basic volume control.
Table 53. Output Stage Volume Control Settings and Gains
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
0
0
30
–15
60
–30.1
90
–45.2
1
–0.5
31
–15.5
61
–30.6
91
–45.8
2
–1
32
–16
62
–31.1
92
–46.2
3
–1.5
33
–16.5
63
–31.6
93
–46.7
4
–2
34
–17
64
–32.1
94
–47.4
5
–2.5
35
–17.5
65
–32.6
95
–47.9
64
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Table 53. Output Stage Volume Control Settings and Gains (continued)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
6
–3
36
–18
66
–33.1
96
–48.2
7
–3.5
37
–18.6
67
–33.6
97
–48.7
8
–4
38
–19.1
68
–34.1
98
–49.3
9
–4.5
39
–19.6
69
–34.6
99
–50
10
–5
40
–20.1
70
–35.1
100
–50.3
11
–5.5
41
–20.6
71
–35.7
101
–51
12
–6
42
–21.1
72
–36.1
102
–51.4
13
–6.5
43
–21.6
73
–36.7
103
–51.8
14
–7
44
–22.1
74
–37.1
104
–52.2
15
–7.5
45
–22.6
75
–37.7
105
–52.7
16
–8
46
–23.1
76
–38.2
106
–53.7
17
–8.5
47
–23.6
77
–38.7
107
–54.2
18
–9
48
–24.1
78
–39.2
108
–55.3
19
–9.5
49
–24.6
79
–39.7
109
–56.7
20
–10
50
–25.1
80
–40.2
110
–58.3
21
–10.5
51
–25.6
81
–40.7
111
–60.2
22
–11
52
–26.1
82
–41.2
112
–62.7
23
–11.5
53
–26.6
83
–41.7
113
–64.3
24
–12
54
–27.1
84
–42.2
114
–66.2
25
–12.5
55
–27.6
85
–42.7
115
–68.7
26
–13
56
–28.1
86
–43.2
116
–72.2
27
–13.5
57
–28.6
87
–43.8
117
–78.3
28
–14
58
–29.1
88
–44.3
118–127
Mute
29
–14.5
59
–29.6
89
–44.8
Table 54. Page 0, Register 45: LINE2L To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPLOUT
1: LINE2L is routed to HPLOUT
D6–D0
R/W
000 0000
LINE2L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 55. Page 0, Register 46: PGA_L To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPLOUT
1: PGA_L is routed to HPLOUT
D6–D0
R/W
000 0000
PGA_L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 56. Page 0, Register 47: DAC_L1 To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT
1: DAC_L1 is routed to HPLOUT
D6–D0
R/W
000 0000
DAC_L1 to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
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Table 57. Page 0, Register 48: LINE2R To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPLOUT
1: LINE2R is routed to HPLOUT
D6–D0
R/W
000 0000
LINE2R to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 58. Page 0, Register 49: PGA_R To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPLOUT
1: PGA_R is routed to HPLOUT
D6–D0
R/W
000 0000
PGA_R to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 59. Page 0, Register 50: DAC_R1 To HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLOUT
1: DAC_R1 is routed to HPLOUT
D6–D0
R/W
000 0000
DAC_R1 to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 60. Page 0, Register 51: HPLOUT Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
HPLOUT Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
HPLOUT Mute
0: HPLOUT is muted
1: HPLOUT is not muted
D2
R/W
1
HPLOUT Power Down Drive Control
0: HPLOUT is weakly driven to a common-mode when powered down
1: HPLOUT is high-impedance when powered down
D1
R
1
HPLOUT Volume Control Status
0: All programmed gains to HPLOUT have been applied
1: Not all programmed gains to HPLOUT have been applied yet
D0
R/W
0
HPLOUT Power Control
0: HPLOUT is not fully powered up
1: HPLOUT is fully powered up
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPLCOM
1: LINE2L is routed to HPLCOM
D6–D0
R/W
000 0000
LINE2L to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 61. Page 0, Register 52: LINE2L To HPLCOM Volume Control Register
66
DESCRIPTION
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Table 62. Page 0, Register 53: PGA_L To HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPLCOM
1: PGA_L is routed to HPLCOM
D6–D0
R/W
000 0000
PGA_L to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 63. Page 0, Register 54: DAC_L1 To HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM
1: DAC_L1 is routed to HPLCOM
D6–D0
R/W
000 0000
DAC_L1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 64. Page 0, Register 55: LINE2R To HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPLCOM
1: LINE2R is routed to HPLCOM
D6–D0
R/W
000 0000
LINE2R to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 65. Page 0, Register 56: PGA_R To HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPLCOM
1: PGA_R is routed to HPLCOM
D6–D0
R/W
000 0000
PGA_R to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 66. Page 0, Register 57: DAC_R1 To HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM
1: DAC_R1 is routed to HPLCOM
D6–D0
R/W
000 0000
DAC_R1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
Table 67. Page 0, Register 58: HPLCOM Output Level Control Register
DESCRIPTION
D7–D4
R/W
0000
HPLCOM Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
HPLCOM Mute
0: HPLCOM is muted
1: HPLCOM is not muted
D2
R/W
1
HPLCOM Power Down Drive Control
0: HPLCOM is weakly driven to a common-mode when powered down
1: HPLCOM is high-impedance when powered down.
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Table 67. Page 0, Register 58: HPLCOM Output Level Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D1
R
1
HPLCOM Volume Control Status
0: All programmed gains to HPLCOM have been applied
1: Not all programmed gains to HPLCOM have been applied yet
D0
R/W
0
HPLCOM Power Control
0: HPLCOM is not fully powered up
1: HPLCOM is fully powered up
DESCRIPTION
Table 68. Page 0, Register 59: LINE2L To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPROUT
1: LINE2L is routed to HPROUT
D6–D0
R/W
000 0000
LINE2L to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 69. Page 0, Register 60: PGA_L To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPROUT
1: PGA_L is routed to HPROUT
D6–D0
R/W
000 0000
PGA_L to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 70. Page 0, Register 61: DAC_L1 To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPROUT
1: DAC_L1 is routed to HPROUT
D6–D0
R/W
000 0000
DAC_L1 to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 71. Page 0, Register 62: LINE2R To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPROUT
1: LINE2R is routed to HPROUT
D6–D0
R/W
000 0000
LINE2R to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 72. Page 0, Register 63: PGA_R To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPROUT
1: PGA_R is routed to HPROUT
D6–D0
R/W
000 0000
PGA_R to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 73. Page 0, Register 64: DAC_R1 To HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPROUT
1: DAC_R1 is routed to HPROUT
D6–D0
R/W
000 0000
DAC_R1 to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
68
DESCRIPTION
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Table 74. Page 0, Register 65: HPROUT Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
HPROUT Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
HPROUT Mute
0: HPROUT is muted
1: HPROUT is not muted
D2
R/W
1
HPROUT Power Down Drive Control
0: HPROUT is weakly driven to a common-mode when powered down
1: HPROUT is high-impedance when powered down
D1
R
1
HPROUT Volume Control Status
0: All programmed gains to HPROUT have been applied
1: Not all programmed gains to HPROUT have been applied yet
D0
R/W
0
HPROUT Power Control
0: HPROUT is not fully powered up
1: HPROUT is fully powered up
Table 75. Page 0, Register 66: LINE2L To HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPRCOM
1: LINE2L is routed to HPRCOM
D6–D0
R/W
000 0000
LINE2L to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 76. Page 0, Register 67: PGA_L To HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPRCOM
1: PGA_L is routed to HPRCOM
D6–D0
R/W
000 0000
PGA_L to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 77. Page 0, Register 68: DAC_L1 To HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPRCOM
1: DAC_L1 is routed to HPRCOM
D6–D0
R/W
000 0000
DAC_L1 to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPRCOM
1: LINE2R is routed to HPRCOM
D6–D0
R/W
000 0000
LINE2R to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 78. Page 0, Register 69: LINE2R To HPRCOM Volume Control Register
DESCRIPTION
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Table 79. Page 0, Register 70: PGA_R To HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPRCOM
1: PGA_R is routed to HPRCOM
D6–D0
R/W
000 0000
PGA_R to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 80. Page 0, Register 71: DAC_R1 To HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM
1: DAC_R1 is routed to HPRCOM
D6–D0
R/W
000 0000
DAC_R1 to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 81. Page 0, Register 72: HPRCOM Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
HPRCOM Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
HPRCOM Mute
0: HPRCOM is muted
1: HPRCOM is not muted
D2
R/W
1
HPRCOM Power Down Drive Control
0: HPRCOM is weakly driven to a common-mode when powered down
1: HPRCOM is high-impedance when powered down
D1
R
1
HPRCOM Volume Control Status
0: All programmed gains to HPRCOM have been applied
1: Not all programmed gains to HPRCOM have been applied yet
D0
R/W
0
HPRCOM Power Control
0: HPRCOM is not fully powered up
1: HPRCOM is fully powered up
Table 82. Page 0, Register 73: LINE2L To MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to MONO_LOP/M
1: LINE2L is routed to MONO_LOP/M
D6–D0
R/W
000 0000
LINE2L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to MONO_LOP/M
1: PGA_L is routed to MONO_LOP/M
D6–D0
R/W
000 0000
PGA_L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 83. Page 0, Register 74: PGA_L To MONO_LOP/M Volume Control Register
70
DESCRIPTION
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Table 84. Page 0, Register 75: DAC_L1 To MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to MONO_LOP/M
1: DAC_L1 is routed to MONO_LOP/M
D6–D0
R/W
000 0000
DAC_L1 to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 85. Page 0, Register 76: LINE2R To MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to MONO_LOP/M
1: LINE2R is routed to MONO_LOP/M
D6–D0
R/W
000 0000
LINE2R to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 86. Page 0, Register 77: PGA_R To MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to MONO_LOP/M
1: PGA_R is routed to MONO_LOP/M
D6–D0
R/W
000 0000
PGA_R to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 87. Page 0, Register 78: DAC_R1 To MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to MONO_LOP/M
1: DAC_R1 is routed to MONO_LOP/M
D6–D0
R/W
000 0000
DAC_R1 to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 88. Page 0, Register 79: MONO_LOP/M Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
MONO_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
MONO_LOP/M Mute
0: MONO_LOP/M is muted
1: MONO_LOP/M is not muted
D2
R
0
Reserved, write only zero to this bit.
D1
R
1
MONO_LOP/M Volume Control Status
0: All programmed gains to MONO_LOP/M have been applied
1: Not all programmed gains to MONO_LOP/M have been applied yet
D0
R/W
0
MONO_LOP/M Power Status
0: MONO_LOP/M is not fully powered up
1: MONO_LOP/M is fully powered up
Table 89. Page 0, Register 80: LINE2L To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DESCRIPTION
LINE2L Output Routing Control
0: LINE2L is not routed to LEFT_LOP/M
1: LINE2L is routed to LEFT_LOP/M
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Table 89. Page 0, Register 80: LINE2L To LEFT_LOP/M Volume Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D6–D0
R/W
000 0000
DESCRIPTION
LINE2L to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
Table 90. Page 0, Register 81: PGA_L To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to LEFT_LOP/M
1: PGA_L is routed to LEFT_LOP/M
D6–D0
R/W
000 0000
PGA_L to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 91. Page 0, Register 82: DAC_L1 To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to LEFT_LOP/M
1: DAC_L1 is routed to LEFT_LOP/M
D6–D0
R/W
000 0000
DAC_L1 to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 92. Page 0, Register 83: LINE2R To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to LEFT_LOP/M
1: LINE2R is routed to LEFT_LOP/M
D6–D0
R/W
000 0000
LINE2R to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 93. Page 0, Register 84: PGA_R To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to LEFT_LOP/M
1: PGA_R is routed to LEFT_LOP/M
D6–D0
R/W
000 0000
PGA_R to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 94. Page 0, Register 85: DAC_R1 To LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to LEFT_LOP/M
1: DAC_R1 is routed to LEFT_LOP/M
D6–D0
R/W
000 0000
DAC_R1 to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 95. Page 0, Register 86: LEFT_LOP/M Output Level Control Register
BIT
D7–D4
72
READ/
WRITE
R/W
RESET
VALUE
0000
DESCRIPTION
LEFT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
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Table 95. Page 0, Register 86: LEFT_LOP/M Output Level Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D3
R/W
0
LEFT_LOP/M Mute
0: LEFT_LOP/M is muted
1: LEFT_LOP/M is not muted
D2
R
0
Reserved, write only zero to this bit.
D1
R
1
LEFT_LOP/M Volume Control Status
0: All programmed gains to LEFT_LOP/M have been applied
1: Not all programmed gains to LEFT_LOP/M have been applied yet
D0
R/W
0
LEFT_LOP/M Power Status
0: LEFT_LOP/M is not fully powered up
1: LEFT_LOP/M is fully powered up
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to RIGHT_LOP/M
1: LINE2L is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
LINE2L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 96. Page 0, Register 87: LINE2L To RIGHT_LOP/M Volume Control Register
DESCRIPTION
Table 97. Page 0, Register 88: PGA_L To RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M
1: PGA_L is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 98. Page 0, Register 89: DAC_L1 To RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M
1: DAC_L1 is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 99. Page 0, Register 90: LINE2R To RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to RIGHT_LOP/M
1: LINE2R is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
LINE2R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 100. Page 0, Register 91: PGA_R To RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M
1: PGA_R is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
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Table 101. Page 0, Register 92: DAC_R1 To RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP/M
1: DAC_R1 is routed to RIGHT_LOP/M
D6–D0
R/W
000 0000
DAC_R1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 53
DESCRIPTION
Table 102. Page 0, Register 93: RIGHT_LOP/M Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
RIGHT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved, do not write these sequences.
D3
R/W
0
RIGHT_LOP/M Mute
0: RIGHT_LOP/M is muted
1: RIGHT_LOP/M is not muted
D2
R
0
Reserved, write only zero to this bit.
D1
R
1
RIGHT_LOP/M Volume Control Status
0: All programmed gains to RIGHT_LOP/M have been applied
1: Not all programmed gains to RIGHT_LOP/M have been applied yet
D0
R/W
0
RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up
1: RIGHT_LOP/M is fully powered up
Table 103. Page 0, Register 94: Module Power Status Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Left DAC Power Status
0: Left DAC not fully powered up
1: Left DAC fully powered up
D6
R
0
Right DAC Power Status
0: Right DAC not fully powered up
1: Right DAC fully powered up
D5
R
0
MONO_LOP/M Power Status
0: MONO_LOP/M output driver powered down
1: MONO_LOP/M output driver powered up
D4
R
0
LEFT_LOP/M Power Status
0: LEFT_LOP/M output driver powered down
1: LEFT_LOP/M output driver powered up
D3
R
0
RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up
1: RIGHT_LOP/M is fully powered up
D2
R
0
HPLOUT Driver Power Status
0: HPLOUT Driver is not fully powered up
1: HPLOUT Driver is fully powered up
D1
R
0
HPROUT Driver Power Status
0: HPROUT Driver is not fully powered up
1: HPROUT Driver is fully powered up
D0
R
0
Reserved, write only zero to this bit.
DESCRIPTION
Table 104. Page 0, Register 95: Output Driver Short Circuit Detection Status Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
74
DESCRIPTION
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT
1: Short circuit detected at HPLOUT
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Table 104. Page 0, Register 95: Output Driver Short Circuit Detection Status Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D6
R
0
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT
1: Short circuit detected at HPROUT
D5
R
0
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM
1: Short circuit detected at HPLCOM
D4
R
0
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM
1: Short circuit detected at HPRCOM
D3
R
0
HPLCOM Power Status
0: HPLCOM is not fully powered up
1: HPLCOM is fully powered up
D2
R
0
HPRCOM Power Status
0: HPRCOM is not fully powered up
1: HPRCOM is fully powered up
D1–D0
R
00
DESCRIPTION
Reserved, write only zeros to these bits.
Table 105. Page 0, Register 96: Sticky Interrupt Flags Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6
R
0
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
D5
R
0
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
D4
R
0
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
D3
R
0
Button Press Detection Status
0: No Headset Button Press detected
1: Headset Button Pressed
D2
R
0
Headset Detection Status
0: No Headset insertion or removal is detected
1: Headset insertion or removal is detected
D1
R
0
Left ADC AGC Noise Gate Status
0: Left ADC Signal Power Greater than Noise Threshold for Left AGC
1: Left ADC Signal Power Lower than Noise Threshold for Left AGC
D0
R
0
Right ADC AGC Noise Gate Status
0: Right ADC Signal Power Greater than Noise Threshold for Right AGC
1: Right ADC Signal Power Lower than Noise Threshold for Right AGC
DESCRIPTION
Table 106. Page 0, Register 97: Real-Time Interrupt Flags Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6
R
0
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
D5
R
0
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
D4
R
0
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
DESCRIPTION
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Table 106. Page 0, Register 97: Real-Time Interrupt Flags Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D3
R
0
Button Press Detection Status (1)
0: No Headset Button Press detected
1: Headset Button Pressed
D2
R
0
Headset Detection Status
0: No Headset is detected
1: Headset is detected
D1
R
0
Left ADC AGC Noise Gate Status
0: Left ADC Signal Power Greater than Noise Threshold for Left AGC
1: Left ADC Signal Power Lower than Noise Threshold for Left AGC
D0
R
0
Right ADC AGC Noise Gate Status
0: Right ADC Signal Power Greater than Noise Threshold for Right AGC
1: Right ADC Signal Power Lower than Noise Threshold for Right AGC
(1)
DESCRIPTION
This bit is a sticky bit, cleared only when Page 0, Register 14 is read.
Table 107. Page 0, Register 98: GPIO1 Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
GPIO1 Output Control
0000: GPIO1 is disabled
0001: GPIO1 used for audio serial data bus ADC word clock
0010: GPIO1 output = clock mux output divided by 1 (M = 1)
0011: GPIO1 output = clock mux output divided by 2 (M = 2)
0100: GPIO1 output = clock mux output divided by 4 (M = 4)
0101: GPIO1 output = clock mux output divided by 8 (M = 8)
0110: GPIO1 output = short circuit interrupt
0111: GPIO1 output = AGC noise interrupt
1000: GPIO1 = general purpose input
1001: GPIO1 = general purpose output
1010: GPIO1 output = digital microphone modulator clock
1011: GPIO1 = word clock for audio serial data bus (programmable as input or output)
1100: GPIO1 output = hook-switch or button press interrupt (interrupt polarity: active high, typical interrupt
duration: button pressed time + clock resolution. Clock resolution depends upon debounce
programmability. Typical interrupt delay from button: debounce duration + 0.5 ms)
1101: GPIO1 output = jack or headset detection interrupt
1110: GPIO1 output = jack or headset detection interrupt OR button press interrupt
1111: GPIO1 output = jack or headset detection OR button press OR Short Circuit detection OR AGC
Noise detection interrupt
D3
R/W
0
GPIO1 Clock Mux Output Control
0: GPIO1 clock mux output = PLL output
1: GPIO1 clock mux output = clock divider mux output
D2
R/W
0
GPIO1 Interrupt Duration Control
0: GPIO1 Interrupt occurs as a single active-high pulse of typical duration 2 ms.
1: GPIO1 Interrupt occurs as continuous pulses until the Interrupt Flags register (Register 96) is read by
the host
D1
R
0
GPIO1 General Purpose Input Value
0: A logic-low level is input to GPIO1
1: A logic-high level is input to GPIO1
D0
R/W
0
GPIO1 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
76
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Table 108. Page 0, Register 99: GPIO2 Control Register
READ/
WRITE
BIT
RESET
VALUE
DESCRIPTION
D7–D4
R/W
0000
GPIO2 Output Control
0000: GPIO2 is disabled
0001: Reserved, do not write this sequence.
0010: GPIO2 output = jack or headset detect interrupt (interrupt polarity: active high. Typical interrupt
duration: 1.75 ms.)
0011: GPIO2 = general purpose input
0100: GPIO2 = general purpose output
0101–0111: GPIO2 input = digital microphone input, data sampled on clock rising and falling edges
1000: GPIO2 = bit clock for audio serial data bus (programmable as input or output)
1001: GPIO2 output = Headset detect OR button press interrupt
1010: GPIO2 output = Headset detect OR button press OR short-circuit detect OR AGC noise detect
interrupt
1011: GPIO2 output = Short-circuit detect OR AGC noise detect interrupt
1100: GPIO2 output = Headset detect OR button press OR short-circuit detect interrupt
1101: GPIO2 output = Short-circuit detect interrupt
1110: GPIO2 output = AGC noise detect interrupt
1111: GPIO2 output = Button press or hook-switch interrupt
D3
R/W
0
GPIO2 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
D2
R
0
GPIO2 General Purpose Input Value
0: A logic-low level is input to GPIO2
1: A logic-high level is input to GPIO2
D1
R/W
0
GPIO2 Interrupt Duration Control
0: GPIO2 Interrupt occurs as a single active-high pulse of typical duration 2 ms.
1: GPIO2 Interrupt occurs as continuous pulses until the Interrupt Flags register (Register 96) is read by
the host
D0
R
0
Reserved, write only zero to this bit.
Table 109. Page 0, Register 100: Additional GPIO Control Register A
READ/
WRITE
BIT
RESET
VALUE
DESCRIPTION
(1)
D7–D6
R/W
00
SDA Pin Control
The SDA pin hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this pin, even in GPIO mode.
00: SDA pin is not used as general purpose I/O
01: SDA pin used as general purpose input
10: SDA pin used as general purpose output
11: Reserved, do not write this sequence.
D5
R/W
0
SDA General Purpose Output Control (1)
0: SDA driven to logic-low when used as general-purpose output
1: SDA driven to logic-high when used as general-purpose output (requires external pullup resistor)
D4
R
0
SDA General Purpose Input Value (1)
0: SDA detects a logic-low when used as general-purpose input
1: SDA is detects a logic-high when used as general purpose input
D3–D2
R/W
00
SCL Pin Control (1)
The SCL pin hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this pin, even in GPIO mode.
00: SCL pin is not used as general purpose I/O
01: SCL pin used as general purpose input
10: SCL pin used as general purpose output
11: Reserved, do not write this sequence.
D1
R/W
0
SCL General Purpose Output Control (1)
0: SCL driven to logic-low when used as general-purpose output
1: SCL driven to logic-high when used as general-purpose output (requires external pullup resistor)
0
SCL General Purpose Input Value (1)
0: SCL detects a logic-low when used as general-purpose input
1: SCL detects a logic-high when used as general-purpose input
D0
(1)
R
The control bits in Register 100 are only valid in SPI Mode, when SELECT = 1.
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Table 110. Page 0, Register 101: Additional GPIO Control Register B
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
I2C Address Pin #0 Status (1)
0: MFP1 pin = I2C address pin #0 = 0 at reset
1: MFP1 pin = I2C address pin #0 = 1 at reset
DESCRIPTION
D6
R
0
I2C Address Pin #1 Status (1)
0: MFP0 pin = I2C address pin #1 = 0 at reset
1: MFP0 pin = I2C address pin #1 = 1 at reset
D5
R/W
0
MFP3 Pin General Purpose Input Control (1)
0: MFP3 pin usage as general purpose input is disabled
1: MFP3 pin usage as general purpose input is enabled
D4
R/W
0
MFP3 Pin Serial Data Bus Input Control (1)
0: MFP3 pin usage as audio serial data input pin is disabled (SDIN)
1: MFP3 pin usage as audio serial data input pin is enabled (MOSI)
D3
R
0
MFP3 General Purpose Input Value (1)
0: MFP3 detects a logic-low when used as general-purpose input
1: MFP3 detects a logic-high when used as general-purpose input
D2
R/W
0
MFP2 General Purpose Output Control (1)
0: MFP2 pin usage as general purpose output is disabled
1: MFP2 pin usage as general purpose output is enabled
D1
R/W
0
MFP2 General Purpose Output Control (1)
0: MFP2 pin drives a logic-low when used as a general-purpose output
1: MFP2 pin drives a logic-high when used as a general-purpose output
D0
R/W
0
CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
(1)
Bits D7–D1 in Register 101 are only valid in I2C control Mode, when SELECT = 0.
Table 111. Page 0, Register 102: Clock Generation Control Register
BIT
D7–D6
D5–D4
D3–D0
READ/
WRITE
R/W
R/W
R/W
RESET
VALUE
DESCRIPTION
00
CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK
01: CLKDIV_IN uses GPIO2
10: CLKDIV_IN uses BCLK
11: Reserved, do not write this sequence.
00
PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK
01: PLLCLK_IN uses GPIO2
10: PLLCLK _IN uses BCLK
11: Reserved, do not write this sequence.
0010
PLL Clock Divider N Value
0000: N = 16
0001: N = 17
0010: N = 2
0011: N = 3
…
1111: N = 15
Table 112. Page 0, Register 103: Left AGC New Programmable Attack Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Attack Time Register Selection
0: Attack time for the left AGC is generated from Register 26.
1: Attack time for the left AGC is generated from this register.
00
Baseline AGC Attack time
00: Left AGC attack time = 7 ms
01: Left AGC Attack time = 8 ms
10: Left AGC Attack time = 10 ms
11: Left AGC Attack time = 11 ms
D6–D5
78
R/W
DESCRIPTION
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Table 112. Page 0, Register 103: Left AGC New Programmable Attack Time Register (continued)
READ/
WRITE
BIT
RESET
VALUE
DESCRIPTION
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC
001: Multiplication factor for the baseline AGC
010: Multiplication factor for the baseline AGC
011: Multiplication factor for the baseline AGC
100: Multiplication factor for the baseline AGC
101: Multiplication factor for the baseline AGC
110: Multiplication factor for the baseline AGC
111: Multiplication factor for the baseline AGC
D1–D0
R/W
00
Reserved, write only zeros to these bits.
Attack
Attack
Attack
Attack
Attack
Attack
Attack
Attack
time = 1
time = 2
time = 4
time = 8
time = 16
time = 32
time = 64
time = 128
Table 113. Page 0, Register 104: Left AGC New Programmable Decay Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Decay Time Register Selection (1)
0: Decay time for the Left AGC is generated from Register 26.
1: Decay time for the Left AGC is generated from this Register.
00
Baseline AGC Decay time
00: Left AGC Decay time = 50 ms
01: Left AGC Decay time = 150 ms
10: Left AGC Decay time = 250 ms
11: Left AGC Decay time = 350 ms
D6–D5
R/W
DESCRIPTION
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC
001: Multiplication factor for the baseline AGC
010: Multiplication factor for the baseline AGC
011: Multiplication factor for the baseline AGC
100: Multiplication factor for the baseline AGC
101: Multiplication factor for the baseline AGC
110: Multiplication factor for the baseline AGC
111: Multiplication factor for the baseline AGC
D1–D0
R/W
00
Reserved, write only zeros to these bits.
(1)
Decay time = 1
Decay time = 2
Decay time = 4
Decay time = 8
Decay time = 16
Decay time = 32
Decay time = 64
Decay time = 128
Decay time is limited based on NADC ratio that is selected. For
NADC = 1, Maximum Decay time = 4 s
NADC = 1.5, Maximum Decay time = 5.6 s
NADC = 2, Maximum Decay time = 8 s
NADC = 2.5, Maximum Decay time = 9.6 s
NADC = 3 or 3.5, Maximum Decay time = 11.2 s
NADC = 4 or 4.5, Maximum Decay time = 16 s
NADC = 5, Maximum Decay time = 19.2 s
NADC = 5.5 or 6, Maximum Decay time = 22.4 s
Table 114. Page 0, Register 105: Right AGC New Programmable Attack Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Attack Time Register Selection
0: Attack time for the Right AGC is generated from Register 29.
1: Attack time for the Right AGC is generated from this Register.
00
Baseline AGC Attack time
00: Right AGC Attack time = 7 ms
01: Right AGC Attack time = 8 ms
10: Right AGC Attack time = 10 ms
11: Right AGC Attack time = 11 ms
D6–D5
R/W
DESCRIPTION
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC
001: Multiplication factor for the baseline AGC
010: Multiplication factor for the baseline AGC
011: Multiplication factor for the baseline AGC
100: Multiplication factor for the baseline AGC
101: Multiplication factor for the baseline AGC
110: Multiplication factor for the baseline AGC
111: Multiplication factor for the baseline AGC
D1–D0
R/W
00
Reserved, write only zeros to these bits.
Attack
Attack
Attack
Attack
Attack
Attack
Attack
Attack
time = 1
time = 2
time = 4
time = 8
time = 16
time = 32
time = 64
time = 128
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Table 115. Page 0, Register 106: Right AGC New Programmable Decay Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Decay Time Register Selection (1)
0: Decay time for the right AGC is generated from Register 29.
1: Decay time for the right AGC is generated from this register.
00
Baseline AGC Decay time
00: Right AGC Decay time = 50 ms
01: Right AGC Decay time = 150 ms
10: Right AGC Decay time = 250 ms
11: Right AGC Decay time = 350 ms
D6–D5
R/W
DESCRIPTION
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC
001: Multiplication factor for the baseline AGC
010: Multiplication factor for the baseline AGC
011: Multiplication factor for the baseline AGC
100: Multiplication factor for the baseline AGC
101: Multiplication factor for the baseline AGC
110: Multiplication factor for the baseline AGC
111: Multiplication factor for the baseline AGC
D1–D0
R/W
00
Reserved, write only zeros to these bits.
(1)
Decay time = 1
Decay time = 2
Decay time = 4
Decay time = 8
Decay time = 16
Decay time = 32
Decay time = 64
Decay time = 128
Decay time is limited based on NADC ratio that is selected. For
NADC = 1, Maximum Decay time = 4 s
NADC = 1.5, Maximum Decay time = 5.6 s
NADC = 2, Maximum Decay time = 8 s
NADC = 2.5, Maximum Decay time = 9.6 s
NADC = 3 or 3.5, Maximum Decay time = 11.2 s
NADC = 4 or 4.5, Maximum Decay time = 16 s
NADC = 5, Maximum Decay time = 19.2 s
NADC = 5.5 or 6, Maximum Decay time = 22.4 s
Table 116. Page 0, Register 107: New Programmable ADC Digital Path And I2C Bus Condition Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Left Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
D6
R/W
0
Right Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
DESCRIPTION
D5–D4
R/W
00
ADC Decimation Filter configuration
00: Left and Right Digital Microphones are used
01: Left Digital Microphone and Right Analog Microphone are used
10: Left Analog Microphone and Right Digital Microphone are used
11: Left and Right Analog Microphones are used
D3
R/W
0
ADC Digital output to Programmable Filter Path Selection
0: No additional Programmable Filters other than the HPF are used for the ADC.
1: The Programmable Filter is connected to ADC output, if both DACs are powered down.
D2
R/W
0
I2C Bus Condition Detector
0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I2C bus error.
D1
R
0
Reserved, write only zero to this bit.
D0
R
0
I2C Bus error detection status
0: I2C bus error is not detected
1: I2C bus error is detected. This bit is cleared by reading this register.
Table 117. Page 0, Register 108: Passive Analog Signal Bypass Selection During Power-Down Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2RM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOM
D6
R/W
0
LINE2RP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOP
80
DESCRIPTION
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Table 117. Page 0, Register 108: Passive Analog Signal Bypass Selection During Power-Down
Register (continued)
BIT
READ/
WRITE
RESET
VALUE
D5
R/W
0
LINE1RM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOM
D4
R/W
0
LINE1RP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOP
D3
R/W
0
LINE2LM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOM
D2
R/W
0
LINE2LP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOP
D1
R/W
0
LINE1LM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOM
D0
R/W
0
LINE1LP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOP
DESCRIPTION
Based on the setting above, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the
two switches used for the connection short the two input signals together on the output pins. The shorting
resistance between the two input pins is two times the bypass switch resistance (RDS(ON)). In general this
condition of shorting must be avoided, as higher drive currents are likely to occur on the circuitry that feeds these
two input pins of this device.
Table 118. Page 0, Register 109: Dac Quiescent Current Adjustment Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
DAC Current Adjustment
00: Default
01: 50% increase in DAC reference current
10: Reserved, do not write this sequence.
11: 100% increase in DAC reference current
D5–D0
R/W
00 0000
Reserved, write only zeros to these bits.
Table 119. Page 0, Register 110–127: Reserved Registers
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
BIT
READ/
WRITE
RESET
VALUE
D7–D1
X
0000 000
Reserved, write only zeros to these bits.
0
Page Select Bit
Writing zero to this bit sets Page 0 as the active page for following register accesses. Writing a one to this
bit sets Page 1 as the active page for following register accesses. TI recommends the user read this
register bit back after each write, to ensure that the proper page is being accessed for future register read
and writes. This register has the same functionality on Page 0 and Page 1.
DESCRIPTION
Reserved, do not write to these registers.
Table 120. Page 1, Register 0: Page Select Register
D0
R/W
DESCRIPTION
Table 121. Page 1, Register 1: Left Channel Audio Effects Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 1011
DESCRIPTION
Left Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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When programming any coefficient value in Page 1, the MSB register must always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB of the coefficient changes, both registers must be
written in this sequence.
Table 122. Page 1, Register 2: Left Channel Audio Effects Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 0011
DESCRIPTION
Left Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 123. Page 1, Register 3: Left Channel Audio Effects Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1001 0110
DESCRIPTION
Left Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 124. Page 1, Register 4: Left Channel Audio Effects Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0110
DESCRIPTION
Left Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 125. Page 1, Register 5: Left Channel Audio Effects Filter N2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0111
DESCRIPTION
Left Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 126. Page 1, Register 6: Left Channel Audio Effects Filter N2 Coefficient LSB
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 1101
DESCRIPTION
Left Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 127. Page 1, Register 7: Left Channel Audio Effects Filter N3 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 1011
DESCRIPTION
Left Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 128. Page 1, Register 8: Left Channel Audio Effects Filter N3 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 0011
DESCRIPTION
Left Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 129. Page 1, Register 9: Left Channel Audio Effects Filter N4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1001 0110
82
DESCRIPTION
Left Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 130. Page 1, Register 10: Left Channel Audio Effects Filter N4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0110
DESCRIPTION
Left Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 131. Page 1, Register 11: Left Channel Audio Effects Filter N5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0111
DESCRIPTION
Left Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 132. Page 1, Register 12: Left Channel Audio Effects Filter N5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 1101
DESCRIPTION
Left Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 133. Page 1, Register 13: Left Channel Audio Effects Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1101
DESCRIPTION
Left Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 134. Page 1, Register 14: Left Channel Audio Effects Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0011
DESCRIPTION
Left Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 135. Page 1, Register 15: Left Channel Audio Effects Filter D2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0100
DESCRIPTION
Left Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 136. Page 1, Register 16: Left Channel Audio Effects Filter D2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 1110
DESCRIPTION
Left Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 137. Page 1, Register 17: Left Channel Audio Effects Filter D4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1101
DESCRIPTION
Left Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 138. Page 1, Register 18: Left Channel Audio Effects Filter D4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0011
DESCRIPTION
Left Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 139. Page 1, Register 19: Left Channel Audio Effects Filter D5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0100
DESCRIPTION
Left Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 140. Page 1, Register 20: Left Channel Audio Effects Filter D5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 1110
DESCRIPTION
Left Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 141. Page 1, Register 21: Left Channel De-Emphasis Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0011 1001
DESCRIPTION
Left Channel De-Emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 142. Page 1, Register 22: Left Channel De-Emphasis Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0101
DESCRIPTION
Left Channel De-Emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 143. Page 1, Register 23: Left Channel De-Emphasis Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1111 0011
DESCRIPTION
Left Channel De-Emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 144. Page 1, Register 24: Left Channel De-Emphasis Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0010 1101
DESCRIPTION
Left Channel De-Emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 145. Page 1, Register 25: Left Channel De-Emphasis Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0011
DESCRIPTION
Left Channel De-Emphasis Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 146. Page 1, Register 26: Left Channel De-Emphasis Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1110
DESCRIPTION
Left Channel De-Emphasis Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 147. Page 1, Register 27: Right Channel Audio Effects Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 1011
84
DESCRIPTION
Right Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 148. Page 1, Register 28: Right Channel Audio Effects Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 0011
DESCRIPTION
Right Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 149. Page 1, Register 29: Right Channel Audio Effects Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1001 0110
DESCRIPTION
Right Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 150. Page 1, Register 30: Right Channel Audio Effects Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0110
DESCRIPTION
Right Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 151. Page 1, Register 31: Right Channel Audio Effects Filter N2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0111
DESCRIPTION
Right Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 152. Page 1, Register 32: Right Channel Audio Effects Filter N2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 1101
DESCRIPTION
Right Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 153. Page 1, Register 33: Right Channel Audio Effects Filter N3 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 1011
DESCRIPTION
Right Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 154. Page 1, Register 34: Right Channel Audio Effects Filter N3 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 0011
DESCRIPTION
Right Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 155. Page 1, Register 35: Right Channel Audio Effects Filter N4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1001 0110
DESCRIPTION
Right Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 156. Page 1, Register 36: Right Channel Audio Effects Filter N4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0110
DESCRIPTION
Right Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 157. Page 1, Register 37: Right Channel Audio Effects Filter N5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0110 0111
DESCRIPTION
Right Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 158. Page 1, Register 38: Right Channel Audio Effects Filter N5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 1101
DESCRIPTION
Right Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 159. Page 1, Register 39: Right Channel Audio Effects Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1101
DESCRIPTION
Right Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 160. Page 1, Register 40: Right Channel Audio Effects Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0011
DESCRIPTION
Right Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 161. Page 1,Register 41: Right Channel Audio Effects Filter D2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
10000100
DESCRIPTION
Right Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 162. Page 1, Register 42: Right Channel Audio Effects Filter D2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 1110
DESCRIPTION
Right Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 163. Page 1, Register 43: Right Channel Audio Effects Filter D4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1101
DESCRIPTION
Right Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 164. Page 1, Register 44: Right Channel Audio Effects Filter D4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0011
DESCRIPTION
Right Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 165. Page 1, Register 45: Right Channel Audio Effects Filter D5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1000 0100
86
DESCRIPTION
Right Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 166. Page 1, Register 46: Right Channel Audio Effects Filter D5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1110 1110
DESCRIPTION
Right Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 167. Page 1, Register 47: Right Channel De-Emphasis Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0011 1001
DESCRIPTION
Right Channel De-Emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 168. Page 1, Register 48: Right Channel De-Emphasis Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0101
DESCRIPTION
Right Channel De-Emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 169. Page 1, Register 49: Right Channel De-Emphasis Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1111 0011
DESCRIPTION
Right Channel De-Emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 170. Page 1, Register 50: Right Channel De-Emphasis Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0010 1101
DESCRIPTION
Right Channel De-Emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 171. Page 1, Register 51: Right Channel De-Emphasis Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0011
DESCRIPTION
Right Channel De-Emphasis Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 172. Page 1, Register 52: Right Channel De-Emphasis Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1110
DESCRIPTION
Right Channel De-Emphasis Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 173. Page 1, Register 53: 3D Attenuation Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1111
DESCRIPTION
3D Attenuation Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 174. Page 1, Register 54: 3D Attenuation Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1111 1111
DESCRIPTION
3D Attenuation Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 175. Page 1, Register 55 to 64: Reserved Registers
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
DESCRIPTION
Reserved, do not write to these registers.
Table 176. Page 1, Register 65: Left Channel ADC High Pass Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0011 1001
DESCRIPTION
Left Channel ADC High Pass Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 177. Page 1, Register 66: Left Channel ADC High Pass Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0101
DESCRIPTION
Left Channel ADC High Pass Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 178. Page 1, Register 67: Left Channel ADC High Pass Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1111 0011
DESCRIPTION
Left Channel ADC High Pass Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 179. Page 1, Register 68: Left Channel ADC High Pass Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0010 1101
DESCRIPTION
Left Channel ADC High Pass Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 180. Page 1, Register 69: Left Channel ADC High Pass Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0011
DESCRIPTION
Left Channel ADC High Pass Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 181. Page 1, Register 70: Left Channel ADC High Pass Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1110
DESCRIPTION
Left Channel ADC High Pass Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 182. Page 1, Register 71: Right Channel ADC High Pass Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0011 1001
DESCRIPTION
Right Channel ADC High Pass Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 183. Page 1, Register 72: Right Channel ADC High Pass Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0101
88
DESCRIPTION
Right Channel ADC High Pass Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
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Table 184. Page 1, Register 73: Right Channel ADC High Pass Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
1111 0011
DESCRIPTION
Right Channel ADC High Pass Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 185. Page 1, Register 74: Right Channel ADC High Pass Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0010 1101
DESCRIPTION
Right Channel ADC High Pass Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 186. Page 1, Register 75: Right Channel ADC High Pass Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0101 0011
DESCRIPTION
Right Channel ADC High Pass Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 187. Page 1, Register 76: Right Channel ADC High Pass Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0111 1110
DESCRIPTION
Right Channel ADC High Pass Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2scomplement integer, with possible values ranging from –32768 to 32767.
Table 188. Page 1, Registers 77 to 127: Reserved Registers
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
DESCRIPTION
Reserved, do not write to these registers.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLV320AIC3106-Q1 is a highly integrated low-power stereo audio codec with integrated stereo
headphone/line amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully
differential configurations. All the features of the TLV320AIC3106-Q1 are accessed by programmable registers.
External processor with SPI or I2C protocol is required to control the device, the protocol is selectable with
external pin configuration. It is good practice to perform a hardware reset after initial power up to ensure that all
registers are in their default states. Extensive register-based power control is included, enabling stereo 48-kHz
DAC playback as low as 14 mW from a 3.3-V analog supply, making it ideal for various car audio applications
such as cluster, telematics, emergency call (eCall), navigation systems, and head unit.
90
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10.2 Typical Application
IOVDD
I2C ADDRESS
Multimedia
Processor
DBB or
Modem
RP
MFP1
MFP2
MFP0
GPIO2
MFP3
GPIO1
DIN
DOUT
BCLK
MCLK
WCLK
SCL
SDA
RESET
RP
AVDD
(2.7 V to 3.6 V)
AVDD_ADC
MIC3L
AVDD_DAC
1 µF
1 kΩ
A
A
TLV320AIC3106-Q1
LINE1LP
0.47 µF
Radio
Tuner
0.1 µF
0.47 µF
1.525 V
to 1.95 V
LINE1RP
0.47 µF
LEFT_LOM
LEFT_LOP
RIGHT_ROP
RIGHT_ROM
HPLOUT
HPROUT
HPLCOM
HPRCOM
AVSS_DAC
MICDET
AVSS_ADC
LINE2RP
MIC3R
A
DVSS
MONO_LOM
LINE2RM
1 µF
1 µF
0.1 µF
SELECT
MONO_LOP
1 kΩ
0.1 µF
DVDD
LINE1RM
1 kΩ
IOVDD
(1.1 V to 3.3 V)
IOVDD
LINE1LM
0.47 µF
1 µF
DRVDD
LINE2LM
1 µF
1 µF
10 µF
0.47 µF
LINE2LP
0.47 µF
0.1 µF
0.1 µF
DRVDD
0.1 µF
1 kΩ
MICBIAS
D
DRVSS
DRVSS
VBAT
A
0.1 µF
33 µF
560 Ω
PVDD
A
A
560 Ω
TLV320AIC3106-Q1
Stereo Speakers with Multiple Audio Processors
4700 pF
560 Ω
560 Ω
4700 pF
TPA6211A1-Q1 (Mono Class-AB in MSOP)
TPA3111D1-Q1 (Mono Class-D in PWP)
TPA3110D2-Q1 (Stereo Class-D in PWP)
TPA2005D1-Q1 (Mono Class-D in SON, MSOP)
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PVSS
A
Figure 39. Typical Connections with Differential Inputs for an External Speaker Driver
10.2.1 Design Requirements
For this design example, use the parameters shown in Table 189.
Table 189. Design Parameters
PARAMETER
VALUE
Supply Voltage (AVDD, DRVDD)
3.3 V
Supply Voltage (DVDD, IOVDD)
1.8 V
Analog Fully Differential Line Output Driver load
10 kΩ
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10.2.2 Detailed Design Procedure
Using Figure 39 as a guide, integrate the hardware into the system.
Follow the schematic layout and routing in Layout to integrate the device and its supporting components into the
system PCB file.
As the TLV320AIC3106-Q1 can be controlled with I2C or SPI protocol, the selection pin of the device must be
connected properly.
Determining sample rate and master clock frequency is required when powering up the device because all
internal timing is derived from the master clock. See Audio Clock Generation for more information on how to
configure correctly the required clocks for the device.
As the TLV320AIC3106-Q1 is designed for low-power applications, when powered up, the device has several
features powered down. A correct routing of the TLV320AIC3106-Q1 signals is achieved by a correct setting of
the device registers, powering up the required stages of the device and configuring the internal switches to follow
a desired route.
10.2.3 Application Curves
0
0
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
Amplitude - dB
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
-140
-140
-160
0
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15 16
17 18
19
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
2048 Samples,
AVDD = DRVDD = 3.3 V,
DVDD = 1.8 V
-20
Amplitude - dB
-20
20
f - Frequency - kHz
-160
0
1
2
3
5
4
Figure 40. Right DAC FFT
6
7
8
9 10 11 12
f - Frequency - kHz
13
14
15
16
17
18
19
20
Figure 41. Right ADC FFT
45
SNR - Signal-To-Noise - dB
40
35
30
25
20
15
10
LINEIR Routed to RADC in Differential Mode,
48 KSPS, Normal Supply and Temperature,
Input Signal at -65 dB
5
0
0
10
20
30
40
50
60
70
ADC, PGA - Setting - dB
Figure 42. Signal-To-Noise Ratio vs ADC PGA Setting
92
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Product Folder Links: TLV320AIC3106-Q1
TLV320AIC3106-Q1
www.ti.com
SLAS663C – AUGUST 2009 – REVISED JUNE 2016
11 Power Supply Recommendations
The TLV320AIC3106-Q1 has been designed to be extremely tolerant of power supply sequencing. However, in
some rare instances, unexpected conditions can be attributed to power supply sequencing. The following
sequence provides the most robust operation.
IOVDD must be powered up first. The analog supplies, which include AVDD and DRVDD, must be powered up
second. The digital supply DVDD must be powered up last. Keep RESET low until all supplies are stable. The
analog supplies must be greater than or equal to DVDD at all times.
Figure 43. TLV320AIC3101 Power Supply Sequencing
Table 190. TLV320AIC3101 Power Supply Sequencing
PARAMETER
MIN
t1
IOVDD to AVDD, DRVDD
0
t2
AVDD to DVDD
0
t3
IOVDD, to DVDD
0
MAX
UNIT
ms
5
ms
ms
12 Layout
12.1 Layout Guidelines
PCB design is made considering the application, and the review is specific for each system's requirements.
However, general considerations can optimize the system performance.
• The TLV320AIC3106-Q1 thermal pad must be connected to analog output driver ground using multiple vias to
minimize impedance from the device to ground.
• Analog and digital grounds must be separated to prevent possible digital noise from affecting the analog
performance of the board.
• The TLV320AIC3106-Q1 requires the decoupling capacitors to be placed as close as possible to the device
power supply terminals.
• TI recommends routing the differential audio signals differentially on the PCB for better noise immunity.
Copyright © 2009–2016, Texas Instruments Incorporated
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TLV320AIC3106-Q1
SLAS663C – AUGUST 2009 – REVISED JUNE 2016
www.ti.com
12.2 Layout Example
LINE1LP
LINE1LM
LINE1RP
LINE1RM
LINE2LP
LINE2LM
LINE2RP
LINE2RM
MICDET
MIC3L
MICBIAS
MIC3R
Analog Ground
Plane
Digital Ground
Plane
IOVDD
2.7 kΩ
SDA
SCL
2.7 kΩ
IOVDD
Thermal pad connected
to analog ground plane
HPLOUT
12
DRVDD
HPRCOM
0.1 µF
HPROUT
10
9
8
7
6
5
4
3
2
MFP3
1
MFP2
13
48
14
47
MFP1
15
46
MFP0
16
45
17
44
18
43
10 µF
19
42
IOVDD
20
41
SELECT
21
40
DOUT
22
39
DIN
23
38
WCLK
24
26
27
28
29
30
31
32
BCLK
37
TLV320AIC3106-Q1
25
0.1 µF
33
34
35
36
System Processor
HPLCOM
11
MCLK
0.1 µF
10 µF
DVDD
0.1 µF
10 µF
AC
GPIO2
_D
D
AV
D
D
RV
D
D
GPIO1
10 µF
MCLK
RIGHT_LOM
LEFT_LOM
RIGHT_LOP
MONO_LOM
LEFT_LOP
MONO_LOP
Decoupling
Capacitors close
to supply pins
If possible route differential
audio signals differently
Via to analog ground layer
Top layer signal traces
Via to digital layer
Ground layer
Figure 44. Layout Diagram
94
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TLV320AIC3106-Q1
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SLAS663C – AUGUST 2009 – REVISED JUNE 2016
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
6PAIC3106IRGZRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGZ
48
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
AC3106Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2016
OTHER QUALIFIED VERSIONS OF TLV320AIC3106-Q1 :
• Catalog: TLV320AIC3106
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
6PAIC3106IRGZRQ1
Package Package Pins
Type Drawing
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
6PAIC3106IRGZRQ1
VQFN
RGZ
48
2500
336.6
336.6
28.6
Pack Materials-Page 2
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