JM1333KLN-2G
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Description
Placement
The JM1333KLN-2G is a 256M x 64bits DDR3-1333
unbuffered DIMM. The JM1333KLN-2G consists of 8pcs
256Mx8bits DDR3 SDRAMs in FBGA packages and a
2048 bits serial EEPROM on a 240-pin printed circuit
board. The JM1333KLN-2G is a Dual In-Line Memory
Module and is intended for mounting into 240-pin edge
connector sockets.
B
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
E D
programmable latencies allow the same device to be
F
useful for a variety of high bandwidth, high performance
A
memory system applications.
Features
•
RoHS compliant products.
•
JEDEC standard 1.5V ± 0.075V Power supply
•
VDDQ=1.5V ± 0.075V
•
Clock Freq: 667MHZ for 1333Mb/s/Pin.
•
Programmable CAS Latency: 6, 7, 8, 9
•
Programmable Additive Latency (Posted /CAS): 0,
C
I
M
J
K
CL-2 or CL-1 clock
•
Programmable /CAS Write Latency (CWL) = 7
•
8 bit pre-fetch
•
Burst Length: 4, 8
•
Bi-directional Differential Data-Strobe
•
Internal calibration through ZQ pin
•
On Die Termination with ODT pin
•
Serial presence detect with EEPROM
•
Asynchronous reset
Transcend Information Inc.
G
H
L
PCB: 09-2810
1
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Dimensions
Pin Identification
Side
Millimeters
Inches
Symbol
A
133.35±0.15
5.250±0.006
A0~A15, BA0~BA2
B
71
2.795
C
47
1.850
D
5
0.197
E
2.5
0.0980
F
1.5±0.10
0.059±0.039
G
5.175
0.204
H
2.311
0.091
I
3±0.1
0.118±0.00394
J
9.5
0.374
DQS0~DQS7
K
17.3
0.681
/DQS0~/DQS7
L
30±0.15
1.181±0.006
DM0~DM7
M
1.27±0.10
0.050±0.004
CK0, /CK0
Function
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
/S0, /S1
Chip Selects
CKE0, CKE1
Clock Enables
ODT0, ODT1
On-die termination control
DQ0~DQ63
Data Input/Output
Data Strobe
Data Masks
Clocks Input
(Refer Placement)
CK1, /CK1
/RESET
Reset Pin
VDD
Core and I/O Power
VSS
Ground
VREFDQ
Input/Output Reference
VREFCA
VTT
VDDSPD
SPD Clock Input
SDA
SPD Data
NC
2
SPD Power
SCL
SA0~SA2
Transcend Information Inc.
Termination Voltage
SPD Address
No Connection
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Pinouts:
Pin
Pin
No
Name
01 VREFDQ
02
VSS
03
DQ0
04
DQ1
05
VSS
06
/DQS0
07
DQS0
08
VSS
09
DQ2
10
DQ3
11
VSS
12
DQ8
13
DQ9
14
VSS
15
/DQS1
16
DQS1
17
VSS
18
DQ10
19
DQ11
20
VSS
21
DQ16
22
DQ17
23
VSS
24
/DQS2
25
DQS2
26
VSS
27
DQ18
28
DQ19
29
VSS
30
DQ24
31
DQ25
32
VSS
33
/DQS3
34
DQS3
35
VSS
36
DQ26
37
DQ27
38
VSS
39
NC
40
NC
Pin
No
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Transcend Information Inc.
Pin
Name
VSS
NC
NC
VSS
NC
NC
VSS
NC
NC
CKE0
VDD
BA2
NC
VDD
A11
A7
VDD
A5
A4
VDD
A2
VDD
CK1
/CK1
VDD
VDD
VREFCA
NC
VDD
A10
BA0
VDD
WE
/CAS
VDD
/S1
ODT1
VDD
NC
VSS
Pin
No
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin
Name
DQ32
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
/DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
/DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
/DQS7
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
Pin
No
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
3
Pin
Name
VSS
DQ4
DQ5
VSS
DM0
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
VSS
NC
NC
VSS
Pin
No
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Pin
Name
NC
NC
VSS
NC
NC
VSS
NC
/RESET
CKE1
VDD
NC
NC
VDD
A12
A9
VDD
A8
A6
VDD
A3
A1
VDD
VDD
CK0
/CK0
VDD
NC
A0
VDD
BA1
VDD
/RAS
/S0
VDD
ODT0
A13
VDD
NC
VSS
DQ36
Pin
No
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin
Name
DQ37
VSS
DM4
NC
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
NC
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Block Diagram
/S0
/DQS4
DQS4
DQ
DM4
32
DQ
33
DQ
34
DQ
35
DQ
36
DQ
37
DQ
38
/DQS5
DQ
DQS5
DQ
39
DM5
40
/DQS0
DQS0
DM0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
/DQS1
DQS1
DM1
DQ 8
DQ 9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
/DQS2
15
DQ
DQS2
16
DM2
DQ
17
DQ
18
DQ
19
DQ
20
DQ
21
DQ
22
/DQS3
DQ
DQS3
DQ
23
DM3
24
DQ
25
DQ
26
DQ
27
DQ
28
DQ
29
DQ
30
DQ
BA0~BA2
31
A0~A15
CKE0
/RAS
/CAS
/WE
ODT0
CK0
/CK0
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
BA0–BA2: SDRAMs D0–D7
A0-A15: SDRAMs D0–D7
CKE: SDRAMs D0–D7
/RAS: SDRAMs D0–D7
/CAS: SDRAMs D0–D7
/WE: SDRAMs D0–D7
ODT: SDRAMs D0–D7
CK: SDRAMs D0–D7
/CK: SDRAMs D0–D7
SC
L
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQ
41
DQ
42
DQ
43
DQ
44
DQ
45
DQ
46
/DQS6
DQ
DQS6
47
48
DM6
DQ
49
DQ
50
DQ
51
DQ
52
DQ
53
DQ
54
/DQS7
DQ
DQS7
DQ
55
DM7
56
DQ
57
DQ
58
DQ
59
DQ
60
DQ
61
DQ
EEPRO
62
DQ
M
63
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
/C
D
DQS/DQS
S
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
WP
A0 A1 A2
SA0SA1SA2
D7
VDDSP
D
SD VDD/VDDQ
VREFD
A
QVS
S
VREFC
A
EEPRO
M
D0~D7
D0~D7
D0~D7
D0~D7
NOTE:
1. DQ-to-I/O wiring is shown as recommended but may be
2. changed.
DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be
3. maintained as shown.
DQ,DM,DQS,/DQS resistors: Refer to associated topology
diagram
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
Transcend Information Inc.
4
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Operating Temperature
TOPER
0 to 85
°C
Note: 1.Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51.2 standard.
2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be
supported.
Note
1,2
Absolute Maximum DC Ratings
Note
s
Voltage on VDD pin relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
°C
1,2
Note: 1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
Parameter
Symbol
Value
Unit
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Rating
Parameter
Symbol
Unit
Min
Typ.
Max
Supply voltage
VDD
1.425
1.5
1.575
Supply voltage for Output
VDDQ
1.425
1.5
1.575
I/O Reference Voltage (DQ)
VREFDQ(DC) 0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
I/O Reference Voltage (CMD/ADD)
VREFCA(DC)
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
AC Input Logic High
VIH(AC)
VREF+0.175
AC Input Logic Low
VIL(AC)
VREF-0.175
DC Input Logic High
VIH(DC)
VREF+0.1
VDD
DC Input Logic Low
VIL(DC)
VSS
VREF-0.1
Note: There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance.
1.Under all conditions VDDQ must be less than or equal to VDD.
2.VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3.Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
V
V
V
V
V
V
V
V
Note
s
1, 2
1, 2
3, 4
3, 4
AC Input Level for Differential Signals
Parameter
Differential Input Logical High
Differential Input Logical Low
Transcend Information Inc.
Symbol
VIHdiff
VILdiff
5
Value
+200
-200
Unit
mV
Note
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
IDD Specification parameters Definition
( IDD values are for full operating range of Voltage and Temperature)
Parameter
Symbol
Max.
Unit Note
IDD0
400
mA
IDD1
480
mA
IDD2P
120
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2Q
240
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
240
mA
IDD3P
120
mA
IDD3N
280
mA
IDD4R
760
mA
IDD4W
760
mA
IDD5
1,240
mA
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address
IDD6
mA
96
bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
IDD7
mA
1,080
commands;Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R;
Note: 1. Module IDD was calculated on the specific brand DRAM component IDD and can be differently measured
according to DQ loading capacitor.
Transcend Information Inc.
6
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
Timing Parameters & Specifications
Parameter
Symbol
Min
Max
Unit
Average Clock Period, CL=9, CWL=7
tCK
1.5
<1.875
ns
Average high pulse width
tCH
0.47
0.53
tCK
Average low pulse width
tCL
0.47
0.53
tCK
tDQSQ
-
125
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500
250
ps
DQ high-impedance time from CK, /CK
Data setup time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
tHZ(DQ)
-
250
ps
tDS
30
-
ps
tDH
65
-
ps
DQ and DM input pulse width for each input
tDIPW
400
-
ps
DQS, /DQS Write preamble
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-500
250
Ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
250
ps
DQS, /DQS differential input low pulse width
tDQSL
0.45
0.55
tCK
DQS, /DQS differential input high pulse width
tDQSH
0.45
0.55
tCK
DQS, /DQS rising edge to CK, /CK rising edge
DQS, /DQS falling edge setup time to CK, /CK rising
edge
DQS, /DQS falling edge hold time to CK, /CK rising
edge
Delay from start of Internal write transaction to Internal
read command
tDQSS
-0.25
+0.25
tCK
tDSS
0.2
-
tCK
tDSH
0.2
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
tWR
15
-
ns
Mode register set command cycle time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
nCK
Auto precharge write recovery + precharge time
tDAL
nCK
Active to active command period for 1KB page size
tRRD
Active to active command period for 2KB page size
tRRD
tWR+tRP/tck
Max
(4tck, 6)
Max
(4tck, 7.5)
Four Activate Window for 1KB page size products
tFAW
30
-
ns
Four Activate Window for 2KB page size products
tFAW
45
-
ns
tZQinitl
512
-
tCK
DQS, /DQS to DQ skew, per group, per access
Write recovery time
Power-up and RESET calibration time
Transcend Information Inc.
7
ns
ns
Note
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
Normal operation Full calibration time
2048MB With 256Mx8 CL9
tZQoper
256
-
tCK
tZQcs
64
-
tCK
Exit self refresh to commands not requiring a locked
DLL
tXS
Max
(5tCK,
tRFC+10)
-
ns
Exit self refresh to commands requiring a locked DLL
tXSDLL
tDLL(min)
-
tCK
-
ns
-
-
-
-
Normal operation short calibration time
Internal read to precharge command delay
tRTP
Max
(4tCK, 7.5ns)
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCK(min)+1tCK
Exit power down with DLL to any valid command: Exit
Precharge Power Down with DLL
tXP
CKE minimum pulse width (high and low pulse width)
tCKE
Max
(3tCK, 5.625ns)
Asynchronous RTT turn-on delay (Power-Down mode)
tAONPD
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down mode)
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-250
250
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Transcend Information Inc.
Max
(3tCK, 6ns)
8
-
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
2048MB With 256Mx8 CL9
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-59
60
61
Function Described
Standard Specification
CRC:0-116Byte
Number of SPD Bytes written / SPD device size / CRC
SPD
Byte use: 176Byte
coverage during module production
SPD Byte total: 256Byte
SPD Revision
Version 1.0
Key Byte / DRAM Device Type
DDR3 SDRAM
Key Byte / Module Type
UDIMM
SDRAM Density and Banks
2Gb 8banks
SDRAM Addressing
ROW:15, Column:10
Reserved
Module Organization
1Rank / x8
Module Memory Bus Width
Non ECC, 64bit
Fine Timebase Dividend and Divisor
2.5ps
Medium Timebase Dividend
0.125ns
Medium Timebase Divisor
0.125ns
SDRAM Minimum Cycle Time (tCKmin)
1.5ns
Reserved
CAS Latencies Supported, Least Significant Byte
6, 7, 8, 9
CAS Latencies Supported, Most Significant Byte
Minimum CAS Latency Time (tAAmin)
13.125ns
Minimum Write Recovery Time (tWRmin)
15ns
Minimum /RAS to /CAS Delay Time (tRCDmin)
13.125ns
Minimum Row Active to Row Active Delay Time
6ns
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
13.125ns
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
36ns
Minmum Active to Active/Refresh Time (tRCmin)
49.125ns
Minmum Refresh Recovery Time (tRFCmin), Least
160ns
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
160ns
Significant Byte
Minmum Internal Write to Read Command Delay Time
7.5ns
(tWTmin)
Minimum Internal Read to Precharge Command Delay
7.5ns
Time (tRTPmin)
Upper Nibble for tFAW
30ns
Minmum Four Active Window Delay Time (tFAWmin)
30ns
DLL off Mode,
SDRAM Optional Features
RZQ/6, RZQ/7
SDRAM Thermal and Refresh Options
No ODTs, Support ASR
Reserved
Module Nominal Height
30mm
Module Max Thickness
Planar Single Sides
Transcend Information Inc.
9
Vendor Part
92
10
0B
02
03
19
00
01
03
52
01
08
0C
00
3C
00
69
78
69
30
69
11
20
89
00
05
3C
3C
00
F0
83
05
00
0F
01
240PIN DDR3 1333 UDIMM
JM1333KLN-2G
62
63
64-116
117
118
119
120-121
122-125
126-127
2048MB With 256Mx8 CL9
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code
R/C A
Standard
Transcend
Transcend
Taipei-
00
00
00
01
4F
54
00
00
57, 39
4A 4D 31 33 33 33
128-145 Module Part Number
JM1333KLN-2G
4B 4C 4E 2D 32 47
20 20 20 20 20 20
146-147
148-149
150-175
176-255
Revision Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Open for customer use
Transcend Information Inc.
By Manufacturer
By Manufacturer
Undefined
10
00
Variable
Variable
00
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