i.MX 6ULL Applications Processor Data Sheet

i.MX 6ULL Applications Processor Data Sheet
NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6ULLIEC
Rev. 0, 09/2016
MCIMX6YxDxxxxxA
MCIMX6YxCxxxxxA
i.MX 6ULL Applications
Processors for Industrial
Products
Package Information
Plastic Package
MAPBGA 14 x 14 mm, 0.8 mm pitch
MAPBGA 9 x 9 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
1
i.MX 6ULL Introduction
The i.MX 6ULL processors represent NXP’s latest
achievement in integrated multimedia-focused products
offering high performance processing with a high degree
of functional integration, targeted towards the growing
market of connected devices.
The i.MX 6ULL is a high performance, ultra efficient
processor family with featuring NXP’s advanced
implementation of the single ARM Cortex®-A7 core,
which operates at speeds of up to 528 MHz. i.MX 6ULL
includes integrated power management module that
reduces the complexity of external power supply and
simplifies the power sequencing. Each processor in this
family provides various memory interfaces, including
LPDDR2, DDR3, DDR3L, Raw and Managed NAND
flash, NOR flash, eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors.
1. i.MX 6ULL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17
3.2. Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 20
4.2. Power Supplies Requirements and Restrictions . 30
4.3. Integrated LDO Voltage Regulator Parameters . . 31
4.4. PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 33
4.5. On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . 34
4.6. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.7. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8. Output Buffer Impedance Parameters . . . . . . . . . 42
4.9. System Modules Timing . . . . . . . . . . . . . . . . . . . . 44
4.10. General-Purpose Media Interface (GPMI) Timing 61
4.11. External Peripheral Interface Parameters . . . . . . . 69
4.12. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 105
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 105
5.2. Boot Device Interface Allocation . . . . . . . . . . . . . 106
6. Package Information and Contact Assignments . . . . . 113
6.1. 14 x 14 mm Package Information . . . . . . . . . . . . 113
6.2. 9x9 mm Package Information . . . . . . . . . . . . . . . 126
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
NXP reserves the right to change the production detail specifications as may be required to permit
improvements in the design of its products.
i.MX 6ULL Introduction
The i.MX 6ULL processors are specifically useful for applications such as:
• Telematics
• Audio playback
• Connected devices
• IoT Gateway
• Access control panels
• Human Machine Interfaces (HMI)
• Portable medical and health care
• IP phones
• Smart appliances
• eReaders
The features of the i.MX 6ULL processors include:
• Single-core ARM Cortex-A7—The single core A7 provides a cost-effective and power-efficient
solution.
• Multilevel memory system—The multilevel memory system of processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR
Flash, NAND Flash (MLC and SLC), OneNAND™, Quad SPI, and managed NAND, including
eMMC up to rev 4.4/4.41/4.5.
• Smart speed technology—Power management implemented throughout the IC that enables
multimedia features and peripherals to consume minimum power in both active and various low
power modes.
• Dynamic voltage and frequency scaling—The power efficiency of devices by scaling the voltage
and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of processor is enhanced by a multilevel
cache system, NEON™ MPE (Media Processor Engine) co-processor, a programmable smart
DMA (SDMA) controller, an asynchronous audio sample rate converter, an Electrophoretic
Display (EPD) controller, and a Pixel processing pipeline (PXP) to support 2D image processing,
including color-space conversion, scaling, alpha-blending, and rotation.
• 2x Ethernet interfaces—2x 10/100 Mbps Ethernet controllers.
• Human-machine interface—Each processor supports one digital parallel display interface.
• Interface flexibility—Each processor supports connections to a variety of interfaces: two
high-speed USB on-the-go with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), two 12-bit ADC modules with up to 10 total input channels and two CAN ports.
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, AES-128
encryption, SHA-1, SHA-256 HW acceleration engine, and secure software downloads. The
security features are discussed in the i.MX 6ULL Security Reference Manual (IMX6ULLSRM).
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i.MX 6ULL Introduction
•
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
For a comprehensive list of the i.MX 6ULL features, see Section 1.2, “Features”.
1.1
Ordering Information
Table 1 provides examples of orderable part numbers covered by this data sheet.
Table 1. Ordering Information
Part Number
Feature
MCIMX6Y0CVM05AA
Features supports:
• 528 MHz, industrial grade for general purpose
• No security
• No LCD/CSI
• No CAN
• Ethernet x1
• USB OTG x1
• ADC x1
• UART x4
• SAI x1
• No ESAI
• Timer x2
• PWM x4
• I2C x2
• SPI x2
Package
14 x 14 mm, 0.8 pitch
MAPBGA
Junction
Temperature Tj
(C)
-40 to +105
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i.MX 6ULL Introduction
Table 1. Ordering Information
Part Number
Feature
Package
Junction
Temperature Tj
(C)
MCIMX6Y1CVM05AA
Features supports:
• 528 MHz, industrial grade for general purpose
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
14 x 14 mm, 0.8 pitch
MAPBGA
-40 to +105
MCIMX6Y1CVK05AA
Features supports:
• 528 MHz, industrial grade for general purpose
• Basic security
• No LCD/CSI
• CAN x1
• Ethernet x1
• USB OTG x2
• ADC x1
• UART x8
• SAI x3
• ESAI x1
• Timer x4
• PWM x8
• I2C x4
• SPI x4
9 x 9 mm, 0.5 pitch
MAPBGA
-40 to +105
Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number they have (for example, cores, frequency, temperature grade, fuse options, and silicon
revision). The primary characteristic which describes which data sheet applies to a specific part is the
temperature grade (junction) field.
• The i.MX 6ULL Applications Processors for Industrial Products Data Sheet (IMX6ULLIEC)
covers parts listed with a “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there will be any questions, visit the web page
NXP.com/imx6series or contact a NXP representative for details.
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i.MX 6ULL Introduction
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300 MHz
03
500 MHz
05
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Security
3
Package Type
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2
MAPBGA 14 x 14 mm, 0.8 pitch
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General Purpose 1 (Reduced Feature)
1
MAPBGA 9 x 9 mm, 0.5 pitch
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Baseline
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Junction Temperature (Tj)
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Consumer: 0 to + 95 °C
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Industrial: -40 to +105 °C
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Figure 1. Part Number Nomenclature—i.MX 6ULL
1.2
Features
The i.MX 6ULL processors are based on ARM Cortex-A7 MPCore™ Platform, which has the following
features:
• Supports single ARM Cortex-A7 MPCore (with TrustZone) with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Private Timer and Watchdog
— Cortex-A7 NEON Media Processing Engine (MPE) Co-processor
• General Interrupt Controller (GIC) with 128 interrupts support
• Global Timer
• Snoop Control Unit (SCU)
• 128 KB unified I/D L2 cache
• Single Master AXI bus interface output of L2 cache
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i.MX 6ULL Introduction
•
•
Frequency of the core (including Neon and L1 cache), as per Table 10, "Operating Ranges," on
page 23.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
— 32 double-precision VFPv3 floating point registers
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia/shared, fast access RAM (OCRAM, 128 KB)
• External memory interfaces: The i.MX 6ULL processors support latest, high volume, cost effective
handheld DRAM, NOR, and NAND Flash memory standards.
— 16-bit LP-DDR2-800, 16-bit DDR3-800 and LV-DDR3-800
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits.
— 16/8-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 6ULL processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
• Displays:
— One parallel display port, support max 85 MHz display clock and up to WXGA (1366 x 768)
at 60 Hz
— Support 24-bit, 18-bit, 16-bit, and 8-bit parallel display
— Electrophoretic display controller support direct-driver for E-Ink EPD panel, with up to
2048x1536 resolution at 106 Hz
• Camera sensors:
— One parallel camera port, up to 24 bit and 133.3 MHz pixel clock
— Support 24-bit, 16-bit, 10-bit, and 8-bit input
— Support BT.656 interface
• Expansion cards:
— Two MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
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i.MX 6ULL Introduction
•
•
USB:
— Two high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
Miscellaneous IPs and interfaces:
— Three I2S/SAI/AC97, up to 1.4 Mbps each
— ESAI
— Sony Philips Digital Interface Format (SPDIF), Rx and Tx
— Eight UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– Support RTS/CTS for hardware flow control
— Four eCSPI (Enhanced CSPI), up to 52 Mbps each
— Four I2C, supports 400 kbps
— Two 10/100 Ethernet Controller (IEEE1588 compliant)
— Eight Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— One Quad SPI to connect to serial NOR flash
— Two Flexible Controller Area Network (FlexCAN)
— Three Watchdog timers (WDOG)
— 8-bit/10-bit/12-bit/16-bit camera interface
— Two 12-bit Analog to Digital Converters (ADC) with up to 10 input channels in total
The i.MX 6ULL processors integrate advanced power management unit and controllers:
•
•
•
•
•
•
•
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Use Voltage Sensor for monitoring the die voltage
Support DVFS techniques for low power modes
Use SW State Retention and Power Gating for ARM and NEON
Support various levels of system power modes
Use flexible clock gating control scheme
The i.MX 6ULL processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6ULL processors incorporate the following hardware accelerators:
• PXP—Pixel Processing Pipeline for image resize, rotation, overlay and CSC. Off loading key pixel
processing operations are required to support the LCD display applications.
• ASRC—Asynchronous Sample Rate Converter
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i.MX 6ULL Introduction
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock, both active tamper and
passive tamper detection logic has up to 10 tamper inputs. Voltage monitor, temperature monitor,
and clock frequency monitor protects the secure key storage.
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
AES-128 encryption, SHA-1, and SHA-256 HW acceleration engine, 2048-bit RSA key, version
control mechanism, warm boot, CSU, and TZ initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions, such as display and camera interfaces, connectivity interfaces.
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Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6ULL processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6ULL processor system.
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Figure 2. i.MX 6ULL System Block Diagram
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Modules List
3
Modules List
The i.MX 6ULL processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6ULL Modules List
Block Mnemonic
Block Name
Subsystem
ADC1
ADC2
Analog to Digital
Converter
—
The ADC is a 12-bit general purpose analog to digital
converter.
ARM
ARM Platform
ARM
The ARM Core Platform includes 1x Cortex-A7 core. It
also includes associated sub-blocks, such as the Level
2 Cache Controller, SCU (Snoop Control Unit), GIC
(General Interrupt Controller), private timers, watchdog,
and CoreSight debug modules.
ASRC
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC)
converts the sampling rate of a signal associated to an
input clock into a signal associated to a different output
clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about -120dB
THD+N. The sample rate conversion of each channel is
associated to a pair of incoming and outgoing sampling
rates. The ASRC supports up to three sampling rate
pairs.
BCH
Binary-BCH ECC
Processor
System Control
Peripherals
CCM
GPC
SRC
Brief Description
The BCH module provides up to 40-bit ECC
encryption/decryption for NAND Flash controller
(GPMI)
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power Controller,
Power Control
distribution in the system, and also for the system power
System Reset Controller
management.
CSI
Parallel CSI
Multimedia
Peripherals
CSU
Central Security Unit
Security
DAP
Debug Access Port
System Control
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
6ULL platform.
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A7
Core Platform.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCP
Data co-processor
Security
This module provides support for general encryption
and hashing functions typically used for security
functions. Because its basic job is moving data from
memory to memory, it also incorporates a memory-copy
(memcopy) function for both debugging and as a more
efficient method of copying data between memory
blocks than the DMA-based approach.
eCSPI1
eCSPI2
eCSPI3
eCSPI4
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM
memories (sync and async operating modes), at
slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash
memories, at slow frequency
• Multiple chip selects
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EPDC
Electrophoretic Display
Controller
Multimedia
Peripherals
The EPDC is a feature-rich, low power, and high
performance direct-drive active matrix EPD controller. It
is specially designed to drive E-INKTM EPD panels,
supporting a wide variety of TFT backplanes.
EPIT1
EPIT2
Enhanced Periodic
Interrupt Timer
Timer Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler for division of input clock frequency to
get the required time setting for the interrupts to occur,
and counter value can be programmed on the fly.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ESAI
Enhanced Serial Audio
Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and
receiver sections, each section with its own clock
generator. All serial transfers are synchronized to a
clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one
word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words
(time slots) per period. This mode can be used to build
time division multiplexed (TDM) networks. In contrast,
the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high
speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection
to external devices.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports 32 bits of I/O.
GPMI
General Purpose
Memory Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices and
40-bit ECC encryption/decryption for NAND Flash
Controller (GPMI2). GPMI supports separate DMA
channels for each NAND device.
GPT1
GPT2
General Purpose Timer
Timer peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
LCDIF
LCD interface
Connectivity
peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capability. The LCDIF is designed to support dumb
(synchronous 24-bit Parallel RGB interface) and smart
(asynchronous parallel MPU interface) LCD devices.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
Pulse Width Modulation
Connectivity
peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
PXP
Pixel Processing Pipeline Display peripherals A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications, allowing it to interface with the integrated
EPD.
RNGB
Random Number
Generator
Security
Random number generating module.
QSPI
Quad SPI
Connectivity
peripherals
Quad SPI module acts as an interface to external serial
flash devices. This module contains the following
features:
• Flexible sequence engine to support various flash
vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of
operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash
devices
• Multi-master access with priority and flexible and
configurable buffer for each master
SAI1
SAI2
SAI3
—
—
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SDMA
Smart Direct Memory
Access
System Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It
helps in maximizing system performance by off-loading
the various cores in dynamic data routing. It has the
following features:
• Powered by a 16-bit Instruction-Set micro-RISC
engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any
combination of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals between ARM and SDMA
• Very fast Context-Switching with 2-level priority
based preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unit-directional and
bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX 6ULL
processors use JTAG port for production, testing, and
system debugging. In addition, the SJC provides BSR
(Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 6ULL SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
System Counter
—
—
The system counter module is a programmable system
counter which provides a shared time base to the
Cortex A series cores as part of ARM’s generic timer
architecture. It is intended for use in application where
the counter is always powered on and supports
multiple, unrelated clocks.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
TSC
Touch Screen
Touch Controller
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by ARM) provides security
address region control functions required for intended
application. It is used on the path to the DRAM
controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART Interface
Connectivity
Peripherals
Each of the UARTv2 module supports the following
serial data transmit/receive protocols and
configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX 6ULL specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card
System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
However, the SoC level integration and I/O muxing logic
restrict the functionality to the following:
• Instances #1 and #2 are primarily intended to serve
as interfaces to on-board peripherals. These ports
are equipped with “Card detection” and “Write
Protection” pads and do not support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There
are two completely independent I/O power domains
for Ports #1 and #2 in four bit configuration (SD
interface).
With touch controller to support 4-wire and 5-wire
resistive touch panel.
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Modules List
Table 2. i.MX 6ULL Modules List (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
USB
Universal Serial Bus 2.0
Connectivity
Peripherals
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
WDOG1
WDOG3
Watch Dog
Timer Peripherals
The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the ARM
core, and a second point evokes an external event on
the WDOG line.
WDOG2
(TZ)
Watch Dog (TrustZone)
Timer Peripherals
The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such
situation is undesirable as it can compromise the
system’s security. Once the TZ WDOG module is
activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer
times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode.
If it is still not served, the TZ WDOG asserts a security
violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal
mode SW.
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Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6ULL processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are provided in the i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX 6ULL Reference Manual (IMX6ULLRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused, either or both of
the CLK1_N/P pairs may be left floating.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should
be left floating or driven with a complimentary signal. The logic level of this forcing clock should not
exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions.
In case when high accuracy real time clock are not required, system may use internal low
frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO
floating.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80  is recommended. NXP BSP (board support package) software requires
24 MHz on XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI is floated.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
DRAM_VREF
When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the
NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a
1 k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a
closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is
maintained when two DDR3 ICs plus the i.MX 6ULL are drawing current on the resistor divider.
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Modules List
Table 3. Special Signal Considerations (continued)
Signal Name
Remarks
DRAM calibration resistor 240  1% used as reference during DRAM output buffer driver
calibration should be connected between this pad and GND.
ZQPAD
GPANAIO
This signal is reserved for NXP manufacturing use only. User must leave this connection floating.
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an
external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX 6ULL reference manual. Both names refer to
the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC
These signals are No Connect (NC) and should be floated by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the
debounce time, the power off interrupt is generated. Off to on time supports the time it takes to
request power on after a configured button press time has been reached. While in the OFF state,
if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.
Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration
supports the time it takes to request power down after ONOFF button has been pressed for the
defined time.
TEST_MODE
TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
Table 4. JTAG Controller Interface Summary
3.2
JTAG
I/O Type
On-chip Termination
JTAG_TCK
Input
47 kpull-up
JTAG_TMS
Input
47 kpull-up
JTAG_TDI
Input
47 kpull-up
JTAG_TDO
3-state output
Keeper
JTAG_TRSTB
Input
47 kpull-up
JTAG_MOD
Input
100 kpull-up
Recommended Connections for Unused Analog Interfaces
Table 5 shows the recommended connections for unused analog interfaces.
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Modules List
Table 5. Recommended Connections for Unused Analog Interfaces
Module
Pad Name
Recommendations
if Unused
CCM
CCM_CLK1_N, CCM_CLK1_P
Float
USB
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS,
USB_OTG2_DN, USB_OTG2_DP, USB_OTG2_VBUS
Float
ADC
ADC_VREFH
Tie to
VDDA_ADC_3P3
VDDA_ADC_3P3
VDDA_ADC_3P3
must be powered
even if the ADC is
not used.
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Electrical Characteristics
4
Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6ULL processors.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX 6ULL Chip-Level Conditions
For these characteristics
Topic appears
Absolute Maximum Ratings
on page 21
Thermal Resistance
on page 21
Operating Ranges
on page 23
External Clock Sources
on page 25
Maximum Supply Currents
on page 26
Power Modes
on page 27
USB PHY Current Consumption
on page 30
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Electrical Characteristics
4.1.1
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
VDDSOC_IN
-0.3
1.6
V
VDDARM_CAP
VDDSOC_CAP
-0.3
1.4
V
GPIO Supply Voltage
NVCC_CSI
NVCC_ENET
NVCC_GPIO
NVCC_UART
NVCC_LCD
NVCC_NAND
NVCC_SD1
-0.5
3.7
V
DDR IO Supply Voltage
NVCC_DRAM
-0.4
1.675
V
VDD_SNVS_IN Supply Voltage
VDD_SNVS_IN
-0.3
3.6
V
VDDHIGH_IN Supply voltage
VDD_HIGH_IN
-0.3
3.7
V
USB_OTG1_VBUS
USB_OTG2_VBUS
—
5.5
V
USB_OTG1_DP/USB_OTG1_DN
USB_OTG2_DP/USB_OTG2_DN
-0.3
3.63
V
Vin/Vout
-0.5
OVDD+0.31
V
—
—
2000
500
V
-40
150
oC
Core Supply Voltage
Internal Supply Voltage
USB VBUS
Input voltage on USB_OTG_DP and
USB_OTG_DN pins
Input/Output Voltage Range
ESD damage Immunity:
Vesd
Human Body Model (HBM)
Charge Device Model (CDM)
Storage Temperature Range
1
TSTORAGE
OVDD is the I/O supply voltage.
4.1.2
4.1.2.1
Thermal Resistance
14x14 mm (VM) Package Thermal Resistance
Table 8 displays the 14x14 mm (VM) package thermal resistance data.
Table 8. 14x14 (VM) Thermal Resistance Data
Rating
Test Conditions
Symbol
Value
Unit
Notes
Junction to Ambient
Natural convection
Single-layer board (1s)
RJA
58.4
oC/W
1,2
Junction to Ambient
Natural convection
Four-layer board (2s2p)
RJA
37.6
o
C/W
1,2,3
RJMA
48.6
oC/W
1,3
Junction to Ambient (@200 Single layer board (1s)
ft/min)
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Electrical Characteristics
Table 8. 14x14 (VM) Thermal Resistance Data (continued)
Rating
Test Conditions
Junction to Ambient (@200 Four layer board (2s2p)
ft/min)
Symbol
Value
Unit
Notes
RJMA
32.9
o
C/W
1,3
Junction to Board
—
RJB
21.8
o
C/W
4
Junction to Case
—
RJC
19.3
o
C/W
5
Junction to Package Top
Natural Convection
JT
2.3
o
C/W
6
Junction to Package Bottom Natural Convection
JB
12.0
o
C/W
7
1
2
3
4
5
6
7
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JB
4.1.2.2
9x9 MM (VK) Package Thermal Resistance
Table 9 displays the 9x9 MM (VK) thermal resistance data.
Table 9. 9x9 MM (VK) Thermal Resistance Data
Rating
Test Conditions
Symbol
Value
Unit
Notes
Junction to Ambient
Natural Convection
Single-layer board (1s)
RJA
65.6
oC/W
1,2
Junction to Ambient
Natural Convection
Four-layer board (2s2p)
RJA
36.2
oC/W
1,2,3
Junction to Ambient (@200
ft/min)
Single layer board (1s)
RJMA
51.2
oC/W
1,3
Junction to Ambient (@200
ft/min)
Four layer board (2s2p)
RJMA
31.8
oC/W
1,3
Junction to Board
—
RJB
17.1
oC/W
4
Junction to Case
—
RJC
14.5
oC/W
5
Junction to Package Top
Natural Convection
JT
0.6
oC/W
6
JB_CSB
11.1
oC/W
7
Junction to Package Bottom Natural Convection
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
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Electrical Characteristics
2
3
4
5
6
7
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistances between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
4.1.3
Operating Ranges
Table 10 provides the operating ranges of the i.MX 6ULL processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6ULL Reference Manual
(IMX6ULLRM).
Table 10. Operating Ranges
Parameter
Description
Symbol
Operating
Conditions
Min
Typ
Max1
Unit
VDD_SOC_IN
—
1.275
—
1.5
V
VDD_SOC_IN must be 125 mV
higher than the LDO Output Set
Point (VDD_ARM_CAP and
VDD_SOC_CAP) for correct
supply voltage regulation.
VDD_ARM_CAP
A7 core at 528
MHz
1.15
—
1.26
V
A7 core at 396
MHz
1.00
—
1.26
A7 core at 198
MHz
0.925
—
1.26
Output voltage must be set to the
following rules:
• VDD_ARM_CAP <=
VDD_SOC_CAP
• VDD_SOC_CAP VDD_ARM_CAP < 330 mV
VDD_SOC_CAP
—
1.15
—
1.26
V
—
Run Mode: LDO
Bypassed
VDD_SOC_IN
A7 core
operations at 528
MHz or below.
1.15
—
1.26
V
A7 core operation above 528 MHz
is not supported when LDO is
bypassed.
Low Power Run
Mode: LDO
Enabled
VDD_SOC_IN
—
1.275
—
1.5
V
VDD_SOC_IN must be 125 mV
higher than the LDO Output Set
Point (VDD_ARM_CAP and
VDD_SOC_CAP) for correct
supply voltage regulation.
1.15
All PLL
bypassed, all
clocks running at 0.925
24 MHz or below
—
1.26
V
—
1.26
V
Output voltage must be set to the
following rules:
• VDD_ARM_CAP <=
VDD_SOC_CAP
• VDD_SOC_CAP VDD_ARM_CAP < 330 mV
Run Mode: LDO
Enabled
VDD_SOC_CAP
VDD_ARM_CAP
Comment
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Electrical Characteristics
Table 10. Operating Ranges (continued)
Low Power Run
Mode: LDO
Bypassed
VDD_SOC_IN
All PLL
bypassed, all
clocks running at
24 MHz or below
1.15
SUSPEND (DSM)
Mode
VDD_SOC_IN
—
0.9
VDD_HIGH
internal regulator
VDD_HIGH_IN
—
VDD_SNVS_IN2
Backup battery
supply range
USB supply
voltages
DDR I/O supply
GPIO supplies
1.26
V
A7 core operation above 528 MHz
is not supported when LDO is
bypassed.
—
1.26
V
Refer to Table 15 Low Power Mode
Current and Power Consumption
on page -28
2.80
—
3.6
V
Must match the range of voltages
that the rechargeable backup
battery supports.
—
2.40
—
3.6
V
Can be combined with
VDDHIGH_IN, if the system does
not require keeping real time and
other data on OFF state.
USB_OTG1_VBUS
—
4.40
—
5.5
V
—
USB_OTG2_VBUS
—
4.40
—
5.5
V
—
NVCC_DRAM
LPDDR2
1.14
1.2
1.3
V
—
DDR3L
1.28
1.35
1.45
V
—
DDR3
1.43
1.5
1.575
V
—
NVCC_DRAM2P5
—
2.25
2.5
2.75
V
—
NVCC_CSI
—
1.65
1.8,
2.8,
3.3
3.6
V
All digital I/O supplies
(NVCC_xxxx) must be powered
(unless otherwise specified in this
data sheet) under normal
conditions whether the associated
I/O pins are in use or not.
—
3.0
3.15
3.6
V
VDDA_ADC_3P3 must be
powered when chip is in RUN
mode, IDLE mode, or SUSPEND
mode.
VDDA_ADC_3P3 should not be
powered when chip is in SNVS
mode.
NVCC_ENET
NVCC_GPIO
NVCC_UART
NVCC_LCD
NVCC_NAND
NVCC_SD1
A/D converter
VDDA_ADC_3P3
Temperature Operating Ranges
Junction
temperature
1
TJ
Standard
Commercial
-40
—
105
o
C
See i.MX 6ULL Product Lifetime
Usage Estimates for information on
product lifetime (power-on years)
for this processor.
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
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2
In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX 6ULL Hardware Development
Guide (IMX6ULLHDG).
Table 11 shows on-chip LDO regulators that can supply on-chip loads.
Table 11. On-Chip LDOs1 and their On-Chip Loads
1
Voltage Source
Load
Comment
VDD_HIGH_CAP
NVCC_DRAM_2P5
Board-level connection to VDD_HIGH_CAP
On-chip LDOs are designed to supply i.MX 6ULL loads and must not be used to supply external loads.
4.1.4
External Clock Sources
Each i.MX 6ULL processor has two external input system clocks: a low frequency (RTC_XTALI) and a
high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 12 shows the interface frequency requirements.
Table 12. External Input Clock Frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1,2
fckil
—
32.7683/32.0
—
kHz
XTALI Oscillator2,4
fxtal
—
24
—
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
3 Recommended nominal frequency 32.768 kHz.
4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
2
The typical values shown in Table 12 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
• On-chip 40 kHz ring oscillator—this clock source has the following characteristics:
— Approximately 25 µA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
• External crystal oscillator with on-chip support circuit:
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— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
4.1.5
Maximum Supply Currents
The data shown in Table 13 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to
specifically show the worst case power consumption.
See the i.MX 6ULL Power Consumption Measurement Application Note (AN4581) for more details on
typical power consumption under various use case definitions.
Table 13. Maximum Supply Currents
Power Line
Conditions
Max Current
Unit
VDD_SOC_IN
528 MHz ARM clock
based on Dhrystone
test
500
mA
VDD_HIGH_IN
—
1251
mA
VDD_SNVS_IN
—
5002
A
USB_OTG1_VBUS
USB_OTG2_VBUS
—
503
mA
VDDA_ADC_3P3
100 Ohm maximum
loading for touch panel
35
mA
Primary Interface (IO) Supplies
NVCC_DRAM
—
(See4)
—
NVCC_DRAM_2P5
—
50
mA
NVCC_GPIO
N=16
Use maximum IO Equation5
—
NVCC_UART
N=16
Use maximum IO
equation5
—
NVCC_ENET
N=16
Use maximum IO equation5
—
NVCC_LCD
N=29
Use maximum IO equation
5
—
NVCC_NAND
N=17
Use maximum IO equation5
—
5
—
—
NVCC_SD
N=6
Use maximum IO equation
NVCC_CSI
N=12
Use maximum IO equation5
MISC
DRAM_VREF
—
1
mA
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1
2
3
4
5
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_DRAM_2P5 supplies).
The maximum VDD_SNVS_IN current may be higher depending on specific operating configurations, such as
BOOT_MODE[1:0] not equal to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1
mA, if available. VDD_SNVS_CAP charge time will increase if less than 1 mA is available.
This is the maximum current per active USB physical interface.
The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power
calculators are typically available from the memory vendors. They take in account factors, such as signal termination. See
the i.MX 6ULL Power Consumption Measurement Application Note (AN4581) or examples of DRAM power consumption
during specific use case scenarios.
General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
4.1.6
Power Modes
The i.MX 6ULL has the following power modes:
• RUN Mode: CPU is active, some portion of the chip can be clock gated or power gated. Support
multiple voltage/frequency scaling set point for power saving;
• Low Power Mode: CPU in WFI state or power gate, some portion of the chip can be shut off for
power saving. The Suspend, Low Power Idle, System Idle are consider as sub-modes of the RUN
mode;
• LPSR Mode: an extension of SNVS Mode, with DRAM in self-retention mode;
• SNVS Mode: only RTC and tamper detection logic is active, with 12 GPIOs in low power state
retention mode;
• OFF Mode: all power rails are off.
The following table summarizes the external power supply state in all the power modes.
Table 14. Power Supply State in Power Modes
Power Rail
RUN
Low Power
SNVS
OFF
VDD_SOC_IN
ON
ON
OFF
OFF
VDD_HIGH_IN
ON
ON
OFF
OFF
VDD_SNVS
ON
ON
ON
OFF
USB_OTG1_VBUS
USB_OTG2_VBUS
ON / OFF
ON / OFF
OFF
OFF
NVCC_DRAM_2P5
ON
ON
OFF
OFF
VDDA_ADC_3P3
ON / OFF
ON / OFF
OFF
OFF
NVCC_DRAM
ON
ON
OFF
OFF
NVCC_XXX
ON / OFF
ON / OFF
OFF
OFF
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4.1.6.1
RUN Mode
In RUN mode, the CPU is active and running, and the analog / digital peripheral modules inside the
processor will be enabled. In this mode, all the external power rails to the processor have to be ON and the
SoC will be able to draw as many current.
Typically, when the CPU is doing DVFS, it switches the VDD_ARM voltage according to Table 10.
4.1.6.2
Low Power Mode
When the CPU is not running, the processor can enter low power mode. i.MX 6ULL processor supports a
very flexible set of power mode configurations in low power mode.
Typically there are three low power modes used, System IDLE, Low Power IDLE, and SUSPEND:
• System IDLE—This is a mode that the CPU can automatically enter when there is no thread
running. All the peripherals can keep working and the CPU’s state is retained so the interrupt
response can be very short. The cores are able to individually enter the WAIT state.
• Low Power IDLE—This mode is for the case when the system needs to have lower power but still
keep some of the peripherals alive. Most of the peripherals, analog modules, and PHYs are shut
off. The interrupt response in this mode is expected to be longer than the System IDLE, but its
power is much lower.
• Suspend—This mode has the greatest power savings; all clocks, unused analog/PHYs, and
peripherals are off. The external DRAM stays in Self-Refresh mode. The exit time from this mode
is much longer.
Table 15 shows the current core consumption (not including I/O) of i.MX 6ULL processors in selected low
power modes.
Table 15. Low Power Mode Current and Power Consumption
Mode
SYSTEM IDLE:
LDO Enabled
SYSTEM IDLE:
LDO Bypassed
Test Conditions
Supply
Typical
Units
LDO_ARM and LDO_SOC are set to 1.15 V
LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
CPU in WFI, CPU clock gated
DDR is in self refresh
24 MHz XTAL is ON
528 PLL is active, other PLLs are power down
High-speed peripheral clock gated, but remain
powered
VDD_SOC_IN (1.275 V)
9
mA
VDD_HIGH_IN (3.0 V)
9.7
VDD_SNVS_IN (3.0 V)
0.04
Total
40.7
mW
• LDO_ARM and LDO_SOC are set to bypass
mode
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• DDR is in self refresh
• 24 MHz XTAL is ON
• 528 PLL is active, other PLLs are power down
• High-speed peripheral clock gated, but remain
powered
VDD_SOC_IN (1.25 V)
8.5
mA
VDD_HIGH_IN (3.0 V)
8.8
VDD_SNVS_IN (3.0 V)
0.04
Total
37.15
•
•
•
•
•
•
•
mW
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Table 15. Low Power Mode Current and Power Consumption (continued)
LOW POWER IDLE:
LDO Enabled
LOW POWER IDLE:
LDO Bypassed
SUSPEND:
SNVS:
4.1.6.3
• LDO_SOC is set to 1.15 V, LDO_ARM is in PG
mode
• LDO_2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
• High-speed peripheral are powered off
• LDO_SOC is in bypass mode, LDO_ARM is in PG
mode
• LDO-2P5 and LDO_1P1 are set to weak mode
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
• High-speed peripheral are powered off
• LDO_SOC is in bypass mode, LDO_ARM is in PG
mode
• LDO_2P5 and LDO_1P1 are shut off
• CPU in power gate mode
• DDR is in self refresh
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• High-speed peripheral are powered off
• All SOC digital logic, analog module are shut off
• 32 kHz RTC is alive
• Tamper detection circuit remains active
VDD_SOC_IN (1.025 V)
1.6
mA
VDD_HIGH_IN (3.0 V)
1.25
VDD_SNVS_IN (3.0 V)
0.03
Total
5.48
mW
VDD_SOC_IN (0.9 V)
1.5
mA
VDD_HIGH_IN (3.0 V)
0.3
VDD_SNVS_IN (3.0 V)
0.05
Total
2.4
mW
VDD_SOC_IN (0.9 V)
0.3
mA
VDD_HIGH_IN (3.0 V)
0.03
VDD_SNVS_IN (3.0 V)
0.03
Total
0.45
mW
VDD_SOC_IN (0 V)
0
mA
VDD_HIGH_IN (0 V)
0
VDD_SNVS_IN (3.0 V)
0.03
Total
0.09
mW
SNVS Mode
SNVS mode is also called RTC mode, where only the power for the SNVS domain remain on. In this
mode, only the RTC and tamper detection logic is still active.
The power consumption in SNVS model with all the tamper detection logic enabled will be less than 0.03
mA@3.0V on VDD_SNVS for typical silicon at 25C.
In SNVS mode, the supported wakeup source are RTC alarm, ONOFF event, and also the 12 GPIO pads
in VDD_SNVS_IN domain.
In some applications, the SNVS mode is powered by non-rechargeable coin cell battery, so the power
consumption in SNVS mode has to be very low.
4.1.6.4
OFF Mode
In OFF mode, all power rails are shut off.
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4.1.7
4.1.7.1
USB PHY Current Consumption
Power Down Mode
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical
condition. Table 16 shows the USB interface current consumption in power down mode.
Table 16. USB PHY Current Consumption in Power Down Mode
Current
VDD_USB_CAP (3.0 V)
VDD_HIGH_CAP (2.5 V)
NVCC_PLL (1.1 V)
5.1 A
1.7 A
< 0.5 A
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)
4.2.1
Power-Up Sequence
The below restrictions must be followed:
• VDD_SNVS_IN supply must be turned on before any other power supply.
• If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
• VDD_HIGH_IN should be turned on before VDD_SOC_IN.
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for further details and to ensure that all necessary
requirements are being met.
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NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use both the 1.8 V and 3.3 V supplies).
NOTE
USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power
supply sequence and may be powered at any time.
4.2.2
Power-Down Sequence
The following restrictions must be followed:
• VDD_SNVS_IN supply must be turned off after any other power supply.
• If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
• VDD_HIGH_IN should be turned off after VDD_SOC_IN is switched off.
4.2.3
Power Supplies Usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information
and Contact Assignments.”
4.3
Integrated LDO Voltage Regulator Parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for details on the power tree scheme.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO operation only.
4.3.1
Digital Regulators (LDO_ARM, LDO_SOC)
There are two digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of
their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on-die trimming. This translates into more stable voltage for
the on-chip logics.
These regulators have two basic modes:
• Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
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•
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2
4.3.2.1
Analog Regulators (LDO_1P1, LDO_2P5, and LDO_USB)
LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0
V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB PHY, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is
2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the DDR IOs, USB PHY,
E-fuse module, and PLLs. A programmable brown-out detector is included in the regulator that can be
used by the system to determine when the load capability of the regulator is being exceeded, to take the
necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up,
if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 ..
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.3.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
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regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6ULL Applications Processors (IMX6ULLHDG).
For additional information, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
4.4
4.4.1
PLL’s Electrical Characteristics
Audio/Video PLL’s Electrical Parameters
Table 17. Audio/Video PLL’s Electrical Parameters
4.4.2
Parameter
Value
Clock output range
650 MHz ~1.3 GHz
Reference clock
24 MHz
Lock time
<11250 reference cycles
528 MHz PLL
Table 18. 528 MHz PLL’s Electrical Parameters
4.4.3
Parameter
Value
Clock output range
528 MHz PLL output
Reference clock
24 MHz
Lock time
<11250 reference cycles
Ethernet PLL
Table 19. Ethernet PLL’s Electrical Parameters
Parameter
Value
Clock output range
500 MHz
Reference clock
24 MHz
Lock time
<11250 reference cycles
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4.4.4
480 MHz PLL
Table 20. 480 MHz PLL’s Electrical Parameters
4.4.5
Parameter
Value
Clock output range
480 MHz PLL output
Reference clock
24 MHz
Lock time
<383 reference cycles
ARM PLL
Table 21. ARM PLL’s Electrical Parameters
4.5
4.5.1
Parameter
Value
Clock output range
648 MHz ~ 1296 MHz
Reference clock
24 MHz
Lock time
<2250 reference cycles
On-Chip Oscillators
OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.5.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
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connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
• Average Discharge Voltage is 2.5 V
• Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 22. OSC32K Main Characteristics
Min
Typ
Max
Comments
Fosc
—
32.768 KHz
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption
—
4 A
—
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc
in the power_detect block. So, the total current is 6.5 A on vdd_rtc when
the ring oscillator is not running.
Bias resistor
—
14 M
—
This the integrated bias resistor that sets the amplifier into a high gain
state. Any leakage through the ESD network, external board leakage, or
even a scope probe that is significant relative to this value will debias the
amp. The debiasing will result in low gain, and will impact the circuit's ability
to start up and maintain oscillations.
Crystal Properties
4.6
Cload
—
10 pF
ESR
—
50 k
—
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output.
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Figure 3. Circuit for Parameters Voh and Vol for I/O Cells
4.6.1
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
Table 23 shows the DC parameters for the clock inputs.
Table 23. XTALI and RTC_XTALI DC Parameters 1
Parameter
Symbol
Test Conditions
Min
Max
Unit
XTALI high-level DC input voltage
Vih
—
0.8 x NVCC_PLL
NVCC_PLL
V
XTALI low-level DC input voltage
Vil
—
0
0.2
V
RTC_XTALI high-level DC input voltage
Vih
—
0.8
1.1
V
RTC_XTALI low-level DC input voltage
Vil
—
0
0.2
V
1
The DC parameters are for external clock input only.
4.6.2
Single Voltage General Purpose I/O (GPIO) DC Parameters
Table 24 shows DC parameters for GPIO pads. The parameters in Table 24 are guaranteed per the
operating ranges in Table 10, unless otherwise noted.
Table 24. Single Voltage GPIO DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage1
VOH
Ioh= -0.1mA (ipp_dse=001,010) OVDD-0.15
Ioh= -1mA
(ipp_dse=011,100,101,110,111)
–
V
Low-level output voltage1
VOL
Iol= 0.1mA (ipp_dse=001,010)
Iol= 1mA
(ipp_dse=011,100,101,110,111)
–
0.15
V
High-Level input voltage1,2
VIH
—
0.7 x OVDD
OVDD
V
Low-Level input voltage1,2
VIL
—
0
0.3 x
OVDD
V
Input Hysteresis (OVDD= 1.8V)
VHYS_LowVDD
OVDD=1.8V
200
—
mV
Input Hysteresis (OVDD=3.3V
VHYS_HighVDD
OVDD=3.3V
200
—
mV
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Table 24. Single Voltage GPIO DC Parameters (continued)
Parameter
Symbol
Test Conditions
Min
Max
Units
Schmitt trigger VT+2,3
VTH+
—
0.5 x OVDD
—
mV
Schmitt trigger VT-2,3
VTH-
—
—
0.5 x
OVDD
mV
Pull-up resistor (22_k PU)
RPU_22K
Vin=0V
—
212
uA
Pull-up resistor (22_k PU)
RPU_22K
Vin=OVDD
—
1
uA
Pull-up resistor (47_k PU)
RPU_47K
Vin=0V
—
100
uA
Pull-up resistor (47_k PU)
RPU_47K
Vin=oOVDD
—
1
uA
Pull-up resistor (100_k PU)
RPU_100K
Vin=0V
—
48
uA
Pull-up resistor (100_k PU)
RPU_100K
Vin=OVDD
—
1
uA
Pull-down resistor (100_k PD)
RPD_100K
Vin=OVDD
—
48
uA
Pull-down resistor (100_k PD)
RPD_100K
Vin=0V
—
1
uA
Input current (no PU/PD)
IIN
VI = 0, VI = OVDD
-1
1
uA
Keeper Circuit Resistance
R_Keeper
VI =0.3 x OVDD, VI = 0.7 x OVDD
105
175
k
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.6.3
DDR I/O DC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. The Multi-mode DDR
Controller (MMDC) is compatible with JEDEC-compliant SDRAMs.
The i.MX 6ULL MMDC supports the following memory types:
• LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
• DDR3 SDRAM compliant to JESD79-3E DDR3 JEDEC standard release July, 2010
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX 6ULL
Applications Processor (IMX6ULLHDG).
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4.6.3.1
LPDDR2 Mode I/O DC Parameters
Table 25. LPDDR2 I/O DC Electrical Parameters1
1
2
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
VOH
Ioh= -0.1mA
0.9 x OVDD
—
V
Low-level output voltage
VOL
Iol= 0.1mA
—
0.1 x OVDD
V
Input Reference Voltage
Vref
—
0.49 x OVDD
0.51 x OVDD
V
DC High-Level input voltage
Vih_DC
—
Vref+0.13
OVDD
V
DC Low-Level input voltage
Vil_DC
—
OVSS
Vref-0.13
V
Differential Input Logic High
Vih_diff
—
0.26
Note2
—
Differential Input Logic Low
Vil_diff
—
Note3
-0.26
—
Pull-up/Pull-down Impedance Mismatch
Mmpupd
—
-15
15
%
240  unit calibration resolution
Rres
—
—
10

Keeper Circuit Resistance
Rkeep
—
110
175
k
Input current (no pull-up/down)
Iin
VI = 0, VI = OVDD
-2.5
2.5
A
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4.6.3.2
DDR3/DDR3L Mode I/O DC Parameters
The parameters in Table 27 are guaranteed per the operating ranges in Table 10, unless otherwise noted.
Table 27. DDR3/DDR3L I/O DC Electrical Characteristics
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
VOH
Ioh= -0.1mA
Voh (for ipp_dse=001)
0.8 x OVDD1
—
V
Low-level output voltage
VOL
Iol= 0.1mA
Vol (for ipp_dse=001)
0.2 x OVDD
—
V
High-level output voltage
VOH
Ioh= -1mA
Voh (for all except ipp_dse=001)
0.8 x OVDD
—
V
Low-level output voltage
VOL
Iol= 1mA
Vol (for all except ipp_dse=001)
0.2 x OVDD
—
V
Input Reference Voltage
Vref
—
0.49 x OVDD
0.51 x ovdd
V
DC High-Level input voltage
Vih_DC
—
Vref2+0.1
OVDD
V
DC Low-Level input voltage
Vil_DC
—
OVSS
Vref-0.1
V
Differential Input Logic High
Vih_diff
—
0.2
See Note3
V
Differential Input Logic Low
Vil_diff
—
See Note
-0.2
V
Termination Voltage
Vtt
Vtt tracking OVDD/2
0.49 x OVDD
0.51 x OVDD
V
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Table 27. DDR3/DDR3L I/O DC Electrical Characteristics (continued)
Parameters
Symbol
Test Conditions
Min
Max
Unit
—
-10
10
%
Pull-up/Pull-down Impedance Mismatch Mmpupd
240 unit calibration resolution
Rres
—
—
10

Keeper Circuit Resistance
Rkeep
—
105
165
k
Input current (no pull-up/down)
Iin
VI = 0,VI = OVDD
-2.9
2.9
A
1
OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L)
Vref – DDR3/DDR3L external reference voltage
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
2
4.6.4
LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 28 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
Table 28. LVDS I/O DC Characteristics
4.7
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
VOD
Rload-100  Diff
250
350
450
mV
Output High Voltage
VOH
IOH = 0 mA
1.25
1.375
1.6
V
Output Low Voltage
VOL
IOL = 0 mA
0.9
1.025
1.25
V
Offset Voltage
VOS
—
1.125
1.2
1.375
V
I/O AC Parameters
This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and
Figure 5.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
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Output (at pad)
OVDD
80%
80%
20%
0V
20%
tf
tr
Figure 5. Output Transition Time Waveform
4.7.1
General Purpose I/O AC Parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 29 and Table 30,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 29. General Purpose I/O AC Parameters 1.8 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=111)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
2.72/2.79
1.69/1.82
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=101)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
3.99/4.44
2.14/2.50
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=100)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
4.52/5.01
2.52/3.07
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=011)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
5.15/5.68
3.44/3.73
Input Transition Times1
trm
—
—
—
25
ns
Unit
1
Unit
ns
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Table 30. General Purpose I/O AC Parameters 3.3 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=101)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
1.84/2.06
1.09/1.35
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=011)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
2.44/2.75
1.75/2.02
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=010)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
3.26/3.70
2.47/2.92
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=001)
tr, tf
22 pF Cload, slow slew rate
22 pF Cload, fast slew rate
—
—
5.26/6.19
4.88/5.77
ns
Input Transition Times1
trm
—
—
—
25
ns
1
ns
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
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4.7.2
DDR I/O AC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. The Multi-mode DDR
Controller (MMDC) is compatible with JEDEC-compliant SDRAMs.
The i.MX 6ULL MMDC supports the following memory types:
• LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
• DDR3 SDRAM compliant to JESD79-3E DDR3 JEDEC standard release July, 2010
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for the i.MX 6ULL
Applications Processor (IMX6ULLHDG).
Table 31 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
Table 31. DDR I/O LPDDR2 Mode AC Parameters1
Parameter
Symbol
Test Condition
Min
Max
Unit
Vih(ac)
—
Vref + 0.22
OVDD
V
Vil(ac)
—
0
Vref - 0.22
V
Vidh(ac)
—
0.44
—
V
Vidl(ac)
—
—
0.44
V
Vix(ac)
Relative to Vref
-0.12
0.12
V
Over/undershoot peak
Vpeak
—
—
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
400 MHz
—
0.3
V-ns
tsr
50 to Vref.
5 pF load.
Drive impedance = 40 
± 30%
1.5
3.5
V/ns
50 to Vref.
5pF load.Drive
impedance = 60 ±
30%
1
2.5
clk = 400 MHz
—
0.1
AC input logic high
AC input logic low
AC differential input high voltage
2
AC differential input low voltage
Input AC differential cross point
voltage3
Single output slew rate, measured between
Vol (ac) and Voh (ac)
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
ns
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp
is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
2
Table 32 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
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Table 32. DDR I/O DDR3/DDR3L Mode AC Parameters1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
—
Vref + 0.175
—
OVDD
V
Vil(ac)
—
0
—
Vref - 0.175
V
AC differential input voltage
Vid(ac)
—
0.35
—
—
V
Input AC differential cross point voltage3
Vix(ac)
Relative to Vref
Vref - 0.15
—
Vref + 0.15
V
Over/undershoot peak
Vpeak
—
—
—
0.4
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
400 MHz
—
—
0.5
V-ns
Single output slew rate, measured between Vol
(ac) and Voh (ac)
tsr
Driver impedance = 34 
2.5
—
5
V/ns
Skew between pad rise/fall asymmetry + skew
caused by SSN
tSKD
clk = 400 MHz
—
—
0.1
ns
AC input logic high
AC input logic low
2
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr-Vcp | required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
2
4.8
Output Buffer Impedance Parameters
This section defines the I/O impedance parameters of the i.MX 6ULL processors for the following I/O
types:
• Single Voltage General Purpose I/O (GPIO)
• Double Data Rate I/O (DDR) for LPDDR2, and DDR3/DDR3L modes
NOTE
GPIO and DDR I/O output driver impedance is measured with “long”
transmission line of impedance Ztl attached to I/O pad and incident wave
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that
defines specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 6).
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OVDD
PMOS (Rpu)
Ztl , L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
Vin (do)
VDD
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Rpu =
Vovdd - Vref1
 Ztl
Vref1
Rpd =
Vref2
 Ztl
Vovdd - Vref2
Figure 6. Impedance Matching Load for Measurement
4.8.1
Single Voltage GPIO Output Buffer Impedance
Table 33 shows the GPIO output buffer impedance (OVDD 1.8 V).
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Table 33. GPIO Output Buffer Average Impedance (OVDD 1.8 V)
Parameter
Output Driver
Impedance
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
260
130
88
65
52
43
37

Rdrv
Table 34 shows the GPIO output buffer impedance (OVDD 3.3 V).
Table 34. GPIO Output Buffer Average Impedance (OVDD 3.3 V)
Parameter
Output Driver
Impedance
4.8.2
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
157
78
53
39
32
26
23

Rdrv
DDR I/O Output Buffer Impedance
Table 35 shows DDR I/O output buffer impedance of i.MX 6ULL processors.
Table 35. DDR I/O Output Buffer Impedance
Typical
Parameter
Output Driver
Impedance
Symbol
Rdrv
Test Conditions DSE
(Drive Strength)
000
001
010
011
100
101
110
111
NVCC_DRAM=1.5 V
(DDR3)
DDR_SEL=11
NVCC_DRAM=1.2 V
(LPDDR2)
DDR_SEL=10
Hi-Z
240
120
80
60
48
40
34
Hi-Z
240
120
80
60
48
40
34
Unit

Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240  external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.9
System Modules Timing
This section contains the timing and electrical parameters for the modules in each i.MX 6ULL processor.
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4.9.1
Reset Timings Parameters
Figure 7 shows the reset timing and Table 36 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset Timing Diagram
Table 36. Reset Timing Parameters
ID
CC1
4.9.2
Parameter
Min
Max
Unit
1
—
RTC_XTALI cycle
Duration of POR_B to be qualified as valid.
WDOG Reset Timing Parameters
Figure 8 shows the WDOG reset timing and Table 37 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 8. WDOGn_B Timing Diagram
Table 37. WDOGn_B Timing Parameters
ID
CC3
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
4.9.3
External Interface Module (EIM)
The following subsections provide information on the EIM.
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4.9.3.1
EIM Interface Pads Allocation
EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.
Table 38 provides EIM interface pads allocation in different modes.
Table 38. EIM Multiplexing1
Non Multiplexed Address/Data Mode
8 Bit
Setup
A[15:0]
A[25:16]
D[7:0],
EIM_EB0
D[15:8],
EIM_EB1
D[23:16],
EIM_EB2
D[31:24],
EIM_EB3
1
Multiplexed Address/Data mode
16 Bit
16 Bit
32 Bit
MUM = 0,
DSZ = 100
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 001
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
EIM_DA[15:0]
EIM_A[25:16]
EIM_D[7:0]
EIM_DA[15:0]
EIM_A[25:16]
—
EIM_DA[15:0]
EIM_A[25:16]
EIM_D[7:0]
EIM_DA[15:0]
EIM_A[25:16]
EIM_DA[7:0]
EIM_DA[15:0]
EIM_D[9:0]
EIM_DA[7:0]
—
EIM_D[15:8]
EIM_D[15:8]
EIM_DA[15:8]
EIM_DA[15:8]
—
—
—
—
EIM_D[7:0]
—
—
—
—
EIM_D[15:8]
For more information on configuration ports mentioned in this table, see the i.MX 6ULL reference manual.
4.9.3.2
General EIM Timing-Synchronous Mode
Figure 9, Figure 10, and Table 39 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
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,
WE2
...
EIM_BCLK
WE3
WE1
WE4
WE5
EIM_ADDRxx
EIM_CSx_B
EIM_WE_B
WE6
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
EIM_OE_B
EIM_EBx_B
EIM_LBA_B
Output Data
Figure 9. EIM Outputs Timing Diagram
EIM_BCLK
WE18
Input Data
WE19
WE20
EIM_WAIT_B
WE21
Figure 10. EIM Inputs Timing Diagram
4.9.3.3
Examples of EIM Synchronous Accesses
Table 39. EIM Bus Timing Parameters 1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
t
—
2xt
—
3xt
—
4xt
—
WE1
EIM_BCLK Cycle
time2
WE2
EIM_BCLK Low
Level Width
0.4 x t
—
0.8 x t
—
1.2 x t
—
1.6 x t
—
WE3
EIM_BCLK High
Level Width
0.4 x t
—
0.8 x t
—
1.2 x t
—
1.6 x t
—
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Table 39. EIM Bus Timing Parameters (continued)1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
WE4
Clock rise to
address valid3
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE5
Clock rise to
address invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE6
Clock rise to
EIM_CSx_B valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE7
Clock rise to
EIM_CSx_B invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE8
Clock rise to
EIM_WE_B Valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE9
Clock rise to
EIM_WE_B Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE10 Clock rise to
EIM_OE_B Valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE11 Clock rise to
EIM_OE_B Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE12 Clock rise to
EIM_EBx_B Valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE13 Clock rise to
EIM_EBx_B Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE14 Clock rise to
EIM_LBA_B Valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE15 Clock rise to
EIM_LBA_B Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE16 Clock rise to
Output Data Valid
-0.5 x t 1.25
-0.5 x t + 1.75
-t - 1.25
- t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t + 1.75
WE17 Clock rise to
Output Data Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t
+1.75
2xt1.25
2 x t + 1.75
WE18 Input Data setup
time to Clock rise
2
—
4
—
—
—
—
—
WE19 Input Data hold
time from Clock
rise
2
—
2
—
—
—
—
—
WE20 EIM_WAIT_B
setup time to Clock
rise
2
—
4
—
—
—
—
—
WE21 EIM_WAIT_B hold
time from Clock
rise
2
—
2
—
—
—
—
—
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1
t is the maximum EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed
latency configuration, whereas the maximum allowed EIM_BCLK frequency is:
—Fixed latency for both read and write is 132 MHz.
—Variable latency for read only is 132 MHz.
—Variable latency for write only is 52 MHz.
In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz. Write BCD = 1 and
104 MHz axi_clk, will result in an EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses
are impacted which are clocked from this source. See the CCM chapter of the i.MX 6ULL Reference Manual (IMX6ULLRM) for
a detailed clock tree description.
2
EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is
defined as 50% as signal value.
3
For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
Figure 11 to Figure 14 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
EIM_BCLK
EIM_ADDRxx
EIM_CSx_B
WE4
WE5
Address v1
Last Valid Address
WE6
WE7
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_DATAxx
WE14
WE15
WE10
WE11
WE12
WE13
WE18
D(v1)
WE19
Figure 11. Synchronous Memory Read Access, WSC=1
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EIM_BCLK
EIM_ADDRxx Last Valid Address
EIM_CSx_B
EIM_WE_B
WE5
WE4
Address V1
WE6
WE7
WE8
WE9
WE14
EIM_LBA_B
WE15
EIM_OE_B
WE13
WE12
EIM_EBx_B
WE16
EIM_DATAxx
WE17
D(V1)
Figure 12. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0
EIM_BCLK
EIM_ADDRxx/
EIM_ADxx
EIM_CSx_B
EIM_WE_B
WE4
Last Valid Address
WE5
WE17
WE16
Write Data
Address V1
WE6
WE7
WE8
WE9
WE14
WE15
EIM_LBA_B
EIM_OE_B
WE10
WE11
EIM_EBx_B
Figure 13. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
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EIM_BCLK
EIM_ADDRxx/
EIM_ADxx
WE4
WE19
WE5
Last Valid Address Address V1
WE6
Data
WE18
EIM_CSx_B
WE7
EIM_WE_B
WE15
WE14
EIM_LBA_B
WE10
WE11
EIM_OE_B
WE12
WE13
EIM_EBx_B
Figure 14. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0
4.9.3.4
General EIM Timing-Asynchronous Mode
Figure 15 through Figure 19, and Table 40 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read & write access length in cycles may vary from what is shown in Figure 15 through
Figure 18 as RWSC, OEN and CSN is configured differently. See the i.MX 6ULL Reference Manual
(IMX6ULLRM) for the EIM programming model.
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
WE31
EIM_ADxx
Last Valid Address
WE32
Next Address
Address V1
EIM_WE_B
EIM_LBA_B
WE39
WE40
EIM_OE_B
WE35
WE36
EIM_EBx_B
WE37
WE38
EIM_DATAxx[7:0]
WE44
MAXCO
D(V1)
WE43
MAXDI
Figure 15. Asynchronous Memory Read Access (RWSC = 5)
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end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
EIM_ADxx
MAXDI
WE31
D(V1)
Addr. V1
WE32A
WE44
EIM_WE_B
WE39
EIM_LBA_B
WE40A
WE35A
WE36
EIM_OE_B
WE37
WE38
EIM_EBx_B
MAXCO
Figure 16. Asynchronous A/D Muxed Read Access (RWSC = 5)
EIM_CSx_B
WE31
EIM_ADDRxx Last Valid Address
WE33
EIM_WE_B
WE39
EIM_LBA_B
WE32
Address V1
Next Address
WE34
WE40
EIM_OE_B
WE45
WE46
EIM_EBx_B
EIM_DATAxx
WE42
WE41
D(V1)
Figure 17. Asynchronous Memory Write Access
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EIM_CSx_B
EIM_ADDRxx/
WE41
WE31
D(V1)
Addr. V1
EIM_DATAxx
WE32A
WE33
WE34
WE42
EIM_WE_B
WE39
EIM_LBA_B
WE40A
EIM_OE_B
WE45
WE46
EIM_EBx_B
WE42
Figure 18. Asynchronous A/D Muxed Write Access
EIM_CSx_B
EIM_ADDRxx
WE31
Last Valid Address
WE32
Next Address
Address V1
EIM_WE_B
WE39
WE40
WE35
WE36
WE37
WE38
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
WE44
EIM_DATAxx[7:0]
D(V1)
WE43
WE48
EIM_DTACK_B
WE47
Figure 19. DTACK Mode Read Access (DAP=0)
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EIM_CSx_B
WE31
EIM_ADDRxx Last Valid Address
WE32
Next Address
Address V1
EIM_WE_B
WE33
WE34
EIM_LBA_B
WE39
WE40
WE45
WE46
EIM_OE_B
EIM_EBx_B
WE42
EIM_DATAxx
D(V1)
WE41
WE48
EIM_DTACK_B
WE47
Figure 20. DTACK Mode Write Access (DAP=0)
Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select
Ref No.
Parameter
Determination by
Synchronous measured
parameters1
Min
Max
(If 132 MHz is
supported by SoC)
Unit
WE31
EIM_CSx_B valid to Address
Valid
WE4 - WE6 - CSA2
—
3 - CSA
ns
WE32
Address Invalid to EIM_CSx_B
invalid
WE7 - WE5 - CSN3
—
3 - CSN
ns
t4 + WE4 - WE7 + (ADVN5 +
ADVA6 + 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
—
ns
WE32A(m EIM_CSx_B valid to Address
uxed A/D Invalid
WE33
EIM_CSx_B Valid to
EIM_WE_B Valid
WE8 - WE6 + (WEA - WCSA)
—
3 + (WEA - WCSA)
ns
WE34
EIM_WE_B Invalid to
EIM_CSx_B Invalid
WE7 - WE9 + (WEN - WCSN)
—
3 - (WEN_WCSN)
ns
WE35
EIM_CSx_B Valid to
EIM_OE_B Valid
WE10 - WE6 + (OEA - RCSA)
—
3 + (OEA - RCSA)
ns
WE35A
(muxed
A/D)
EIM_CSx_B Valid to
EIM_OE_B Valid
WE10 - WE6 + (OEA + RADVN
-3 + (OEA +
3 + (OEA +
+ RADVA + ADH + 1 - RCSA) RADVN+RADVA+ RADVN+RADVA+AD
ADH+1-RCSA)
H+1-RCSA)
ns
WE36
EIM_OE_B Invalid to
EIM_CSx_B Invalid
WE7 - WE11 + (OEN - RCSN)
—
3 - (OEN - RCSN)
ns
WE37
EIM_CSx_B Valid to
EIM_EBx_B Valid (Read
access)
WE12 - WE6 + (RBEA - RCSA)
—
3 + (RBEA - RCSA)
ns
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Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)
Ref No.
Parameter
WE38
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Read
access)
WE39
EIM_CSx_B Valid to
EIM_LBA_B Valid
WE40
EIM_LBA_B Invalid to
EIM_CSx_B Invalid (ADVL is
asserted)
WE40A
(muxed
A/D)
EIM_CSx_B Valid to
EIM_LBA_B Invalid
Determination by
Synchronous measured
parameters1
Min
Max
(If 132 MHz is
supported by SoC)
Unit
WE7 - WE13 + (RBEN - RCSN)
—
3 - (RBEN- RCSN)
ns
WE14 - WE6 + (ADVA - CSA)
—
3 + (ADVA - CSA)
ns
WE7 - WE15 - CSN
—
3 - CSN
ns
WE14 - WE6 + (ADVN + ADVA
+ 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
3 + (ADVN + ADVA +
1 - CSA)
ns
WE41
EIM_CSx_B Valid to Output
Data Valid
WE16 - WE6 - WCSA
—
3 - WCSA
ns
WE41A
(muxed
A/D)
EIM_CSx_B Valid to Output
Data Valid
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA)
—
3 + (WADVN +
WADVA + ADH + 1 WCSA)
ns
WE17 - WE7 - CSN
—
3 - CSN
ns
10
—
—
ns
10
—
—
ns
WE42
MAXCO
Output Data Invalid to
EIM_CSx_B Invalid
Output maximum delay from
internal driving
EIM_ADDRxx/control FFs to
chip outputs
MAXCSO Output maximum delay from
CSx internal driving FFs to CSx
out
MAXDI
EIM_DATAxx maximum delay
from chip input data to its
internal FF
5
—
—
ns
WE43
Input Data Valid to EIM_CSx_B
Invalid
MAXCO - MAXCSO + MAXDI
MAXCO MAXCSO +
MAXDI
—
ns
WE44
EIM_CSx_B Invalid to Input
Data invalid
0
0
—
ns
WE45
EIM_CSx_B Valid to
EIM_EBx_B Valid (Write
access)
WE12 - WE6 + (WBEA WCSA)
—
3 + (WBEA - WCSA)
ns
WE46
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Write
access)
WE7 - WE13 + (WBEN WCSN)
—
-3 + (WBEN - WCSN)
ns
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Table 40. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)
Ref No.
MAXDTI
1
2
3
4
5
6
Parameter
MAXIMUM delay from
EIM_DTACK_B to its internal
FF + 2 cycles for
synchronization
WE47
EIM_DTACK_B Active to
EIM_CSx_B Invalid
WE48
EIM_CSx_B Invalid to
EIM_DTACK_B Invalid
Determination by
Synchronous measured
parameters1
Min
Max
(If 132 MHz is
supported by SoC)
Unit
10
—
—
—
MAXCO - MAXCSO + MAXDTI
MAXCO MAXCSO +
MAXDTI
—
ns
0
0
—
ns
For more information on configuration parameters mentioned in this table, see the i.MX 6ULL Reference Manual (IMX6ULLRM).
In this table, CSA means WCSA when write operation or RCSA when read operation.
In this table, CSN means WCSN when write operation or RCSN when read operation.
t is axi_clk cycle time.
In this table, ADVN means WADVN when write operation or RADVN when read operation.
In this table, ADVA means WADVA when write operation or RADVA when read operation.
4.9.4
4.9.4.1
DDR SDRAM Specific Parameters (DDR3 and LPDDR2)
DDR3 Parameters
The i.MX 6ULL supports single Chip Select DDR3 memory with CS0_B, ODT0, and SDCKE0.
Figure 21 shows the DDR3 basic timing diagram with the timing parameters provided in Table 41.
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DDR1
DRAM_SDCLKx_N
DRAM_SDCLKx_P
DDR2
DDR4
DRAM_CSx_B
DDR5
DRAM_RAS_B
DDR5
DDR4
DRAM_CAS_B
DDR4
DDR5
DDR5
DRAM_SDWE_B
DRAM_ODTx /
DRAM_SDCKEx
DDR4
DDR6
DRAM_ADDRxx
DDR7
ROW/BA
COL/BA
Figure 21. DDR3 Command and Address Timing Diagram
Table 41. DDR3 Timing Parameters
CK = 400 MHz
ID
1
2
Parameter
Symbol
Unit
Min
Max
DDR1 DRAM_SDCLKx_P clock high-level width
tCH
0.47
0.53
tCK
DDR2 DRAM_SDCLKx_P clock low-level width
tCL
0.47
0.53
tCK
DDR4 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx setup time
tIS
515
—
ps
DDR5 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx hold time
tIH
425
—
ps
DDR6 Address output setup time
tIS
515
—
ps
DDR7 Address output hold time
tIH
425
—
ps
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25  resistor from outputs to VDD_REF.
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Figure 22 shows the DDR3 write timing diagram. The timing parameters for this diagram appear in Table
42.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DDR21
DDR22
DRAM_SDQSx_P
(output)
DDR18
DDR17
DDR23
DDR17
DDR18
DRAM_DATAxx
(output)
Data
Data
Data
Data
Data
Data
Data
Data
DRAM_DQMx
(output)
DM
DM
DM
DM
DM
DM
DM
DM
DDR17
DDR18
DDR17
DDR18
Figure 22. DDR3 Write Cycle
Table 42. DDR3 Write Cycle
CK = 400MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR17
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
tDS
175
—
ps
DDR18
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
(differential strobe)
tDH
200
—
ps
DDR21
DRAM_SDQSx_P latching rising transitions to associated clock edges
tDQSS
-0.25
+0.25
tCK
DDR22
DRAM_SDQSx_P high level width
tDQSH
0.45
0.55
tCK
DDR23
DRAM_SDQSx_P low level width
tDQSL
0.45
0.55
tCK
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P in
the middle of DRAM_DATAxx window.
2 All measurements are in reference to Vref level.
3
Measurements were taken using balanced load and 25  resistor from outputs to DDR_VREF.
1
Figure 23 shows the DDR3 read timing diagram. The timing parameters for this diagram appear in Table
43.
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DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P
(input)
DRAM_DATAxx
(input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DDR26
Figure 23. DDR3 Read Cycle
Table 43. DDR3 Read Cycle
CK = 400 MHz
ID
DDR26
Parameter
Symbol
Minimum required DRAM_DATAxx valid window width
Unit
—
Min
Max
450
—
ps
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
2 All measurements are in reference to Vref level.
3 Measurements were done using balanced load and 25  resistor from outputs to VDD_REF.
4.9.4.2
LPDDR2 Parameters
The i.MX 6ULL supports a maximum of two die loads on the data bus signals: SDCKE0/1 and CS0/1.
Figure 24 shows the LPDDR2 basic timing diagram. The timing parameters for this diagram appear in
Table 44.
DRAM_SDCLKx_P
LP1
LP4
DRAM_CSx_B
LP2
LP3
DRAM_SDCKEx
LP3
LP3
LP4
DRAM_CAS_B
LP3
LP4
Figure 24. LPDDR2 Command and Address Timing Diagram
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Table 44. LPDDR2 Timing Parameter
CK = 400 MHz
ID
1
2
Parameter
Symbol
Unit
Min
Max
LP1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
LP2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
LP3
DRAM_CSx_B, DRAM_SDCKEx setup time
tIS
490
—
ps
LP4
DRAM_CSx_B, DRAM_SDCKEx hold time
tIH
440
—
ps
LP3
DRAM_CAS_B setup time
tIS
490
—
ps
LP4
DRAM_CAS_B hold time
tIH
440
—
ps
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25  resistor from outputs to DDR_VREF.
Figure 25 shows the LPDDR2 write timing diagram. The timing parameters for this diagram appear in
Table 45.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
LP21
DRAM_SDCLKx_P
(output)
LP23
LP18
LP17
LP22
LP17
LP18
DRAM_DATAxx
(output)
Data
Data
Data
Data
Data
Data
Data
Data
DRAM_DQMx
(output)
DM
DM
DM
DM
DM
DM
DM
DM
LP17
LP17
LP18
LP18
Figure 25. LPDDR2 Write Cycle
Table 45. LPDDR2 Write Cycle
CK = 400 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP17
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
tDS
320
—
ps
LP18
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
(differential strobe)
tDH
320
—
ps
LP21
DRAM_SDQSx_P latching rising transitions to associated clock edges
tDQSS
-0.25
+0.25
tCK
LP22
DRAM_SDQSx_P high level width
tDQSH
0.4
—
tCK
LP23
DRAM_SDQSx_P low level width
tDQSL
0.4
—
tCK
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1
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQS in
the middle of DRAM_DATAxx window.
2
All measurements are in reference to Vref level.
3
Measurements were done using balanced load and 25  resistor from outputs to DDR_VREF.
Figure 26 shows the LPDDR2 read timing diagram. The timing parameters for this diagram appear in
Table 46.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P
(input)
LP26
DRAM_DATAxx
(input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 26. LPDDR2 Read Cycle
Table 46. LPDDR2 Read Cycle
CK = 400 MHz
ID
LP26
Parameter
Minimum required DRAM_DATAxx valid window width for LPDDR2
Symbol
—
Unit
Min
Max
270
—
ps
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATA_xx window.
2 All measurements are in reference to Vref level.
3 Measurements were done using balanced load and 25  resistor from outputs to DDR_VREF.
4.10
General-Purpose Media Interface (GPMI) Timing
The i.MX 6ULL GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up
to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following subsections.
4.10.1
Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 27 through Figure 30
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode. Table 47 describes the timing parameters (NF1–NF17) that are shown in the figures.
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Electrical Characteristics
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Figure 30. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)
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Table 47. Asynchronous Mode Timing Parameters1
ID
Parameter
Timing
T = GPMI Clock Cycle
Symbol
Min.
2
3
4
5
Max.
NF1
NAND_CLE setup time
tCLS
(AS + DS)  T - 0.12 [see 2,3]
ns
NF2
NAND_CLE hold time
tCLH
DH  T - 0.72 [see 2]
ns
NF3
NAND_CE0_B setup time
tCS
NF4
NAND_CE0_B hold time
tCH
NF5
NAND_WE_B pulse width
tWP
NF6
NAND_ALE setup time
tALS
(AS + DS + 1)  T [see
3,2]
ns
(DH+1)  T - 1 [see 2]
DS  T [see
ns
2]
ns
(AS + DS)  T - 0.49 [see 3,2]
ns
NF7
NAND_ALE hold time
tALH
(DH  T - 0.42 [see
NF8
Data setup time
tDS
DS  T - 0.26 [see 2]
ns
2]
ns
ns
2]
ns
NF9
Data hold time
tDH
DH  T - 1.37 [see
NF10
Write cycle time
tWC
(DS + DH)  T [see 2]
NF11
NAND_WE_B hold time
tWH
NF12
Ready to NAND_RE_B low
tRR4
DH  T [see
2]
(AS + 2)  T [see 3,2]
ns
—
DS  T [see
2]
ns
NF13
NAND_RE_B pulse width
tRP
NF14
READ cycle time
tRC
(DS + DH)  T [see 2]
ns
DH  T [see ]
ns
NF15
NAND_RE_B high hold time
tREH
NF16
Data setup on read
tDSR
NF17
1
Unit
Data hold on read
tDHR
ns
2
—
0.82/11.83 [see
5,6
]
(DS  T -0.67)/18.38 [see 5,6]
ns
—
ns
GPMI’s Async Mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
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EDO mode, GPMI clock  100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
6
In EDO mode (Figure 30), NF16/NF17 is different from the definition in non-EDO mode (Figure 29).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will
sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The
delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 6ULL
Reference Manual). The typical value of this control register is 0x8 at 50 MT/s EDO mode. But if the board
delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board
delay.
4.10.2
Source Synchronous Mode AC Timing (ONFI 2.x Compatible)
Figure 32 to Figure 34 show the write and read timing of Source Synchronous Mode.
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Figure 34. Source Synchronous Mode Data Read Timing Diagram
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Electrical Characteristics
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Figure 35. NAND_DQS/NAND_DQ Read Valid Window
Table 48. Source Synchronous Mode Timing Parameters1
ID
Parameter
Symbol
Timing
T = GPMI Clock Cycle
Min.
Unit
Max.
NF18 NAND_CE0_B access time
tCE
CE_DELAY  T - 0.79 [see 2]
ns
NF19 NAND_CE0_B hold time
tCH
0.5  tCK - 0.63 [see 2]
ns
NF20 Command/address NAND_DATAxx setup time
tCAS
0.5  tCK - 0.05
ns
NF21 Command/address NAND_DATAxx hold time
tCAH
0.5  tCK - 1.23
ns
tCK
—
ns
NF23 Preamble delay
tPRE
PRE_DELAY  T - 0.29 [see 2]
ns
NF24 Postamble delay
tPOST
POST_DELAY  T - 0.78 [see 2]
ns
NF25 NAND_CLE and NAND_ALE setup time
tCALS
0.5  tCK - 0.86
ns
NF26 NAND_CLE and NAND_ALE hold time
tCALH
0.5  tCK - 0.37
ns
NF27 NAND_CLK to first NAND_DQS latching transition
tDQSS
T - 0.41 [see 2]
ns
NF28 Data write setup
—
0.25  tCK - 0.35
—
NF29 Data write hold
—
0.25  tCK - 0.85
—
NF30 NAND_DQS/NAND_DQ read setup skew
—
—
2.06
—
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
1.95
—
NF22 Clock period
1
GPMI’s source synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2
T = tCK(GPMI clock period) -0.075ns (half of maximum p-p jitter).
For DDR Source sync mode, Figure 35 shows the timing diagram of NAND_DQS/NAND_DATAxx read
valid window. The typical value of tDQSQ is 0.85ns (max) and 1ns (max) for tQHS at 200MB/s. GPMI
will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which
can be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6ULL
Reference Manual). Generally, the typical delay value of this register is equal to 0x7 which means 1/4
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clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
4.10.3
4.10.3.1
Samsung Toggle Mode AC Timing
Command and Address Timing
NOTE
Samsung Toggle Mode command and address timing is the same as ONFI
1.0 compatible Async mode AC timing. See Section 4.10.1, “Asynchronous
Mode AC Timing (ONFI 1.0 Compatible),” for details.
4.10.3.2
Read and Write Timing
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Electrical Characteristics
DEV?CLK
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Table 49. Samsung Toggle Mode Timing Parameters1
ID
Parameter
Symbo
l
Timing
T = GPMI Clock Cycle
Min.
NF1
NAND_CLE setup time
NF2
NAND_CLE hold time
NF3
NAND_CE0_B setup time
tCLS
tCLH
tCS
Uni
t
Max.
(AS + DS)  T - 0.12 [see 2,3]
DH  T - 0.72 [see
—
2]
—
(AS + DS)  T - 0.58 [see 3,2]
NF4
NAND_CE0_B hold time
tCH
DH  T - 1 [see
NF5
NAND_WE_B pulse width
tWP
DS  T [see 2]
—
2]
—
—
NF6
NAND_ALE setup time
tALS
(AS + DS)  T - 0.49 [see
NF7
NAND_ALE hold time
tALH
DH  T - 0.42 [see 2]
—
2]
—
—
NF8
Command/address NAND_DATAxx setup time
tCAS
DS  T - 0.26 [see
NF9
Command/address NAND_DATAxx hold time
tCAH
DH  T - 1.37 [see 2]
NF18
NAND_CEx_B access time
tCE
NF22
clock period
tCK
CE_DELAY  T [see
4,2]
—
3,2]
—
—
ns
—
ns
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Table 49. Samsung Toggle Mode Timing Parameters1 (continued)
ID
Parameter
Symbo
l
Timing
T = GPMI Clock Cycle
Min.
NF23
preamble delay
tPRE
PRE_DELAY  T [see 5,2]
Uni
t
Max.
—
ns
NF24
postamble delay
tPOST
POST_DELAY  T +0.43 [see ]
—
ns
NF28
Data write setup
tDS6
0.25  tCK - 0.32
—
ns
6
tDH
0.25  tCK - 0.79
—
ns
tDQSQ
—
3.18
—
—
3.27
—
NF29
Data write hold
NF30
NAND_DQS/NAND_DQ read setup skew
2
7
NF31
1
2
3
4
5
6
7
NAND_DQS/NAND_DQ read hold skew
tQHS7
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
PRE_DELAY+1)  (AS+DS)
Shown in Figure 36.
Shown in Figure 37.
For DDR Toggle mode, Figure 35 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will
sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6ULL
Reference Manual). Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay
expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger
to compensate the board delay.
4.11
External Peripheral Interface Parameters
The following subsections provide information on external peripheral interfaces.
4.11.1
4.11.1.0.1
CMOS Sensor Interface (CSI) Timing Parameters
Gated Clock Mode Timing
Figure 38 and Figure 39 shows the gated clock mode timings for CSI, and Table 50 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
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(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5
P6
CSI_PIXCLK
P3
P4
CSI_DATA[15:00]
Figure 38. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6
P5
CSI_PIXCLK
P3
P4
CSI_DATA[15:00]
Figure 39. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 50. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
CSI_VSYNC to CSI_HSYNC time
tV2H
33.5
—
ns
P2
CSI_HSYNC setup time
tHsu
1
—
ns
P3
CSI DATA setup time
tDsu
1
—
ns
P4
CSI DATA hold time
tDh
1
—
ns
P5
CSI pixel clock high time
tCLKh
3.75
—
ns
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Table 50. CSI Gated Clock Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min.
Max.
Units
P6
CSI pixel clock low time
tCLKl
3.75
—
ns
P7
CSI pixel clock frequency
fCLK
—
133.3
MHz
4.11.1.0.2
Ungated Clock Mode Timing
Figure 40 shows the ungated clock mode timings of CSI, and Table 51 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4
P5
CSI_PIXCLK
P2
P3
CSI_DATA[15:00]
Figure 40. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 51. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
tVSYNC
33.5
—
ns
P1
CSI_VSYNC to pixel clock time
P2
CSI DATA setup time
tDsu
1
—
ns
P3
CSI DATA hold time
tDh
1
—
ns
P4
CSI pixel clock high time
tCLKh
3.75
—
ns
P5
CSI pixel clock low time
tCLKl
3.75
—
ns
P6
CSI pixel clock frequency
fCLK
—
133.3
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
• Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
• Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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4.11.2
ECSPI Timing Parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
4.11.2.1
ECSPI Master Mode Timing
Figure 41 depicts the timing of ECSPI in master mode. Table 52 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS2
CS3
CS1
CS5
CS6
CS4
ECSPIx_SCLK
CS7 CS3
CS2
ECSPIx_MOSI
CS8
CS9
ECSPIx_MISO
Figure 41. ECSPI Master Mode Timing Diagram
Table 52. ECSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
43
15
—
ns
CS2
ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
21.5
7
—
ns
CS3
ECSPIx_SCLK Rise or Fall1
tRISE/FALL
—
—
ns
CS4
ECSPIx_SS_B pulse width
tCSLH
Half ECSPIx_SCLK period
—
ns
CS5
ECSPIx_SS_B Lead Time (CS setup time)
tSCS
Half ECSPIx_SCLK period - 4
—
ns
CS6
ECSPIx_SS_B Lag Time (CS hold time)
tHCS
Half ECSPIx_SCLK period - 2
—
ns
CS7
ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
tPDmosi
-1
1
ns
CS8
ECSPIx_MISO Setup Time
tSmiso
14
—
ns
CS9
ECSPIx_MISO Hold Time
tHmiso
0
—
ns
tSDRY
5
—
ns
CS10 RDY to ECSPIx_SS_B Time
1
2
2
See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
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4.11.2.2
ECSPI Slave Mode Timing
Figure 42 depicts the timing of ECSPI in slave mode. Table 53 lists the ECSPI slave mode timing
characteristics.
ECSPIx_SS_B
CS2
CS1
CS5
CS6
CS4
ECSPIx_SCLK
CS2
CS9
ECSPIx_MISO
CS7
CS8
ECSPIx_MOSI
Figure 42. ECSPI Slave Mode Timing Diagram
Table 53. ECSPI Slave Mode Timing Parameters
ID
Symbol
Min
Max
Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
tclk
15
43
—
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
7
21.5
—
ns
CS4 ECSPIx_SS_B pulse width
tCSLH
Half ECSPIx_SCLK period
—
ns
CS5 ECSPIx_SS_B Lead Time (CS setup time)
tSCS
5
—
ns
CS6 ECSPIx_SS_B Lag Time (CS hold time)
tHCS
5
—
ns
CS7 ECSPIx_MOSI Setup Time
tSmosi
4
—
ns
CS8 ECSPIx_MOSI Hold Time
tHmosi
4
—
ns
CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
tPDmiso
4
19
ns
4.11.3
Parameter
Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 54 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 43 and Figure 44.
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Electrical Characteristics
Table 54. Enhanced Serial Audio Interface (ESAI) Timing
Characteristics1,2
No.
Symbol
Expression2
Min
Max
Condition3 Unit
tSSICC
4  Tc
4  Tc
30.0
30.0
—
—
i ck
i ck
62
Clock cycle4
63
Clock high period:
• For internal clock
• For external clock
—
—
2  Tc 9.0
2  Tc
6
15
—
—
—
—
Clock low period:
• For internal clock
• For external clock
—
—
2  Tc 9.0
2  Tc
6
15
—
—
—
—
64
ns
ns
ns
65
ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
66
ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
67
ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)
high5
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
68
ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
69
ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high
—
—
—
—
—
—
16.0
6.0
x ck
i ck a
ns
70
ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before ESAI_RX_CLK (SCK in
synchronous mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
ns
72
Data in hold time after ESAI_RX_CLK falling edge
—
—
—
—
3.5
9.0
—
—
x ck
i ck
ns
73
ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK
falling edge5
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
74
ESAI_RX_FS input (wl) high before ESAI_RX_CLK
falling edge
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
75
ESAI_RX_FS input hold time after ESAI_RX_CLK falling
edge
—
—
—
—
2.5
8.5
—
—
x ck
i ck a
ns
76
Flags input setup before ESAI_RX_CLK falling edge
—
—
—
—
0.0
19.0
—
—
x ck
i ck s
ns
77
Flags input hold time after ESAI_RX_CLK falling edge
—
—
—
—
6.0
0.0
—
—
x ck
i ck s
ns
78
ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high
—
—
—
—
—
—
18.0
8.0
x ck
i ck
ns
79
ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
80
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)
high5
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
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Table 54. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics1,2
No.
1
Symbol
Expression2
Min
Max
Condition3 Unit
81
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low5
—
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
82
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high
—
—
—
—
—
—
19.0
9.0
x ck
i ck
ns
83
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
84
ESAI_TX_CLK rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
ns
85
ESAI_TX_CLK rising edge to transmitter #0 drive enable
assertion
—
—
—
—
—
—
17.0
11.0
x ck
i ck
ns
86
ESAI_TX_CLK rising edge to data out valid
—
—
—
—
—
—
18.0
13.0
x ck
i ck
ns
87
ESAI_TX_CLK rising edge to data out high impedance 67
—
—
—
—
—
—
21.0
16.0
x ck
i ck
ns
88
ESAI_TX_CLK rising edge to transmitter #0 drive enable
deassertion7
—
—
—
—
14.0
9.0
x ck
i ck
ns
89
ESAI_TX_FS input (bl, wr) setup time before
ESAI_TX_CLK falling edge5
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
90
ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK
falling edge
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
91
ESAI_TX_FS input hold time after ESAI_TX_CLK falling
edge
—
—
—
—
4.0
5.0
—
—
x ck
i ck
ns
92
ESAI_TX_FS input (wl) to data out enable from high
impedance
—
—
—
21.0
—
ns
93
ESAI_TX_FS input (wl) to transmitter #0 drive enable
assertion
—
—
—
14.0
—
ns
94
Flag output valid after ESAI_TX_CLK rising edge
—
—
—
—
14.0
9.0
x ck
i ck
ns
95
ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle
—
2 x TC
15
—
—
ns
96
ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK
output
—
—
—
18.0
—
ns
97
ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK
output
—
—
—
18.0
—
ns
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)
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Electrical Characteristics
2
3
4
5
6
bl = bit length
wl = word length
wr = word length relative
ESAI_TX_CLK(SCKT pin) = transmit clock
ESAI_RX_CLK(SCKR pin) = receive clock
ESAI_TX_FS(FST pin) = transmit frame sync
ESAI_RX_FS(FSR pin) = receive frame sync
ESAI_TX_HF_CLK(HCKT pin) = transmit high frequency clock
ESAI_RX_HF_CLK(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
62
63
64
ESAI_TX_CLK
(Input/Output)
78
ESAI_TX_FS
(Bit)
Out
79
82
ESAI_TX_FS
(Word)
Out
83
86
86
84
87
First Bit
Data Out
Last Bit
89
91
ESAI_TX_FS
(Bit) In
90
91
ESAI_TX_FS
(Word) In
Figure 43. ESAI Transmitter Timing
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62
63
64
ESAI_RX_CLK
(Input/Output)
65
ESAI_RX_FS
(Bit)
Out
66
69
70
ESAI_RX_FS
(Word)
Out
72
71
Data In
ESAI_RX_FS
(Bit)
In
First Bit
Last Bit
75
73
74
ESAI_RX_FS
(Word)
In
75
Figure 44. ESAI Receiver Timing
ESAI_TX_HF_CLK
ESAI_TX_CLK (output)
95
96
Figure 45. ESAI ESAI_TX_HF_CLK Timing
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Electrical Characteristics
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
4.11.4
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing, eMMC4.4/4.41 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.11.4.1
SD/eMMC4.3 (Single Data Rate) AC Timing
Figure 46 depicts the timing of SD/eMMC4.3, and Table 55 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 46. SD/eMMC4.3 Timing
Table 55. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
3.6
ns
Card Input Clock
SD1
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6
uSDHC Output Delay
tOD
-6.6
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Table 55. SD/eMMC4.3 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD7
uSDHC Input Setup Time
SD8
4
uSDHC Input Hold Time
tISU
2.5
—
ns
tIH
1.5
—
ns
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
4.11.4.2
eMMC4.4/4.41 (Dual Data Rate) AC Timing
Figure 47 depicts the timing of eMMC4.4/4.41. Table 56 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
......
Figure 47. eMMC4.4/4.41 Timing
Table 56. eMMC4.4/4.41 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
fPP
0
52
MHz
SD1
Clock Frequency (SD3.0 DDR)
fPP
0
50
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
uSDHC Output Delay
tOD
2.5
7.1
ns
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD3
uSDHC Input Setup Time
tISU
2.6
—
ns
SD4
uSDHC Input Hold Time
tIH
1.5
—
ns
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4.11.4.3
SDR50/SDR104 AC Timing
Figure 48 depicts the timing of SDR50/SDR104, and Table 57 lists the SDR50/SDR104 timing
characteristics.
6'
6'
6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRFDUG
6'
6'
ELWLQSXWIURPFDUGWRX6'+&
6'
Figure 48. SDR50/SDR104 Timing
Table 57. SDR50/SDR104 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD5SD Clock Frequency Period
1
tCLK
5.0
—
ns
SD6SD Clock Low Time
2
tCL
0.3 x tCLK
0.7 x tCLK
ns
SD7SD Clock High Time
2
tCH
0.3 x tCLK
0.7 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD8SD uSDHC Output Delay
4
tOD
–3
1
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
–1.6
1
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD6
uSDHC Input Setup Time
tISU
2.5
—
ns
SD7
uSDHC Input Hold Time
tIH
1.5
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
SD8
Card Output Data Window
tODW
0.5 x tCLK
—
ns
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1
Data window in SDR100 mode is variable.
4.11.4.4
HS200 Mode Timing
Figure 49 depicts the timing of HS200 mode, and Table 58 lists the HS200 timing characteristics.
6'
6'
6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRFDUG
6'
6'
ELWLQSXWIURPFDUGWRX6'+&
6'
Figure 49. HS200 Mode Timing
Table 58. HS200 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD9SD Clock Frequency Period
1
tCLK
5.0
—
ns
SD10S Clock Low Time
D2
tCL
0.3 x tCLK
0.7 x tCLK
ns
SD11S Clock High Time
D2
tCH
0.3 x tCLK
0.7 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
–1.6
1
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
SD8
1
Card Output Data Window
tODW
0.5 x tCLK
—
ns
HS200 is for 8 bits while SDR104 is for 4 bits.
4.11.4.5
Bus Operation Condition for 3.3 V and 1.8 V Signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 24,
"Single Voltage GPIO DC Parameters," on page 36.
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4.11.5
Ethernet Controller (ENET) AC Electrical Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
4.11.5.1
ENET MII Mode Timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.11.5.1.1
MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 50 shows MII receive signal timings. Table 59 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 50. MII Receive Signal Timing Diagram
Table 59. MII Receive Signal Timing
ID
1
Characteristic1
Min.
Max.
Unit
M1
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
M2
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
ENET_RX_CLK pulse width high
35%
65%
ENET_RX_CLK period
M4
ENET_RX_CLK pulse width low
35%
65%
ENET_RX_CLK period
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
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4.11.5.1.2
MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
Figure 51 shows MII transmit signal timings. Table 60 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 51. MII Transmit Signal Timing Diagram
Table 60. MII Transmit Signal Timing
Characteristic1
ID
Min.
Max.
Unit
M5
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
ENET_TX_CLK pulse width high
35%
65%
ENET_TX_CLK period
M8
ENET_TX_CLK pulse width low
35%
65%
ENET_TX_CLK period
1 ENET_TX_EN,
4.11.5.1.3
ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)
Figure 52 shows MII asynchronous input timings. Table 61 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 52. MII Async Inputs Timing Diagram
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Electrical Characteristics
Table 61. MII Asynchronous Inputs Signal Timing
ID
M91
1
Characteristic
ENET_CRS to ENET_COL minimum pulse width
Min.
Max.
Unit
1.5
—
ENET_TX_CLK period
ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
4.11.5.1.4
MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 53 shows MII asynchronous input timings. Table 62 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 53. MII Serial Management Channel Timing Diagram
Table 62. MII Serial Management Channel Timing
ID
Characteristic
Min.
Max.
Unit
M10
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
ENET_MDIO (input) to ENET_MDC rising edge setup
18
—
ns
M13
ENET_MDIO (input) to ENET_MDC rising edge hold
0
—
ns
M14
ENET_MDC pulse width high
40%
60%
ENET_MDC period
M15
ENET_MDC pulse width low
40%
60%
ENET_MDC period
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4.11.5.2
RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the RMII_CRS_DV in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0], and ENET_RX_ER.
Figure 54 shows RMII mode timings. Table 63 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 54. RMII Mode Signal Timing Diagram
Table 63. RMII Signal Timing
ID
Characteristic
Min.
Max.
Unit
M16
ENET_CLK pulse width high
35%
65%
ENET_CLK period
M17
ENET_CLK pulse width low
35%
65%
ENET_CLK period
M18
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
4
—
ns
M19
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
—
13
ns
M20
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
ns
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
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4.11.6
Flexible Controller Area Network (FLEXCAN) AC Electrical
Specifications
The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing
the CAN protocol according to the CAN 2.0B protocol specification. The processor has two CAN modules
available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See
the IOMUXC chapter of the i.MX 6ULL Reference Manual (IMX6ULLRM) to see which pins expose Tx
and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.
4.11.7
I2C Bus Characteristics
The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is
designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now
NXP Semiconductors).
4.11.8
Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 55 depicts the timing of the PWM, and Table 64 lists the PWM timing parameters.
0
0
07-N?/54
Figure 55. PWM Timing
Table 64. PWM Output Timing Parameters
ID
Parameter
Min
Max
Unit
PWM Module Clock Frequency
0
66
MHz
P1
PWM output pulse width high
15
—
ns
P2
PWM output pulse width low
15
—
ns
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4.11.9
LCD Controller (LCDIF) Timing Parameters
Figure 56 shows the LCDIF timing and Table 65 lists the timing parameters.
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ULVLQJHGJHFDSWXUH
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Figure 56. LCD Timing
Table 65. LCD Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
tCLK(LCD)
—
150
MHz
L1
LCD pixel clock frequency
L2
LCD pixel clock high (falling edge capture)
tCLKH(LCD)
3
—
ns
L3
LCD pixel clock low (rising edge capture)
tCLKL(LCD)
3
—
ns
L4
LCD pixel clock high to data valid (falling edge capture)
td(CLKH-DV)
-1
1
ns
L5
LCD pixel clock low to data valid (rising edge capture)
td(CLKL-DV)
-1
1
ns
L6
LCD pixel clock high to control signal valid (falling edge capture)
td(CLKH-CTRLV)
-1
1
ns
L7
LCD pixel clock low to control signal valid (rising edge capture)
td(CLKL-CTRLV)
-1
1
ns
4.11.10 QUAD SPI (QSPI) Timing Parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
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4.11.10.1 SDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>@
Figure 57. QuadSPI Input/Read Timing (SDR mode with internal sampling)
Table 66. QuadSPI Input Timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
8.67
—
ns
TIH
Hold time requirement for incoming data
0
—
ns
463,[B6&/.
463,[B'$7$>@
7,6
7,+
7,6
7,+
463,[B'46
Figure 58. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Table 67. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
2
—
ns
TIH
Hold time requirement for incoming data
1
—
ns
•
•
NOTE
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
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463,[B6&/.
7&66
7&6+
7&.
463,[B&6
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 59. QuadSPI Output/Write Timing (SDR mode)
Table 68. QuadSPI Output/Write Timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
Output data valid time
—
2
ns
TDHO
Output data hold time
-0.5
—
ns
TCK
SCK clock period
10
—
ns
TCSS
Chip select output setup time
3
—
SCK cycle(s)
TCSH
Chip select output hold time
3
—
SCK cycle(s)
NOTE
Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
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4.11.10.2 DDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>@
Figure 60. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Table 69. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
8.67
—
ns
TIH
Hold time requirement for incoming data
0
—
ns
463,[B6&/.
463,[B'$7$>@
7,6
7,+
7,6
7,+
463,[B'46
Figure 61. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Table 70. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
Setup time for incoming data
2
—
ns
TIH
Hold time requirement for incoming data
1
—
ns
•
NOTE
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
7&66
7&.
7&6+
463,[B&6
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 62. QuadSPI Output/Write Timing (DDR mode)
Table 71. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
Output data valid time
—
(0.25 x TSCLK) + 2
ns
TDHO
Output data hold time
(0.25 x TSCLK) - 0.5
—
ns
TCK
SCK clock period
20
—
ns
TCSS
Chip select output setup time
3
—
SCK cycle(s)
TCSH
Chip select output hold time
3
—
SCK cycle(s)
NOTE
Tcss and Tcsh are configured by the QuadSPIx_FLSHCR register, the default
value of 3 are shown on the timing. Please refer to the i.MX 6ULL Reference
Manual (IMX6ULLRM) for more details.
4.11.11 SAI/I2S Switching Specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 72. Master Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
2 x tsys
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
4 x tsys
—
ns
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
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Table 72. Master Mode SAI Timing (continued)
Num
Characteristic
Min
Max
Unit
S5
SAI_BCLK to SAI_FS output valid
—
15
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
15
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
15
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
Figure 63. SAI Timing — Master Modes
Table 73. Master Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
4 x tsys
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
10
—
ns
S14
SAI_FA input hold after SAI_BCLK
2
—
ns
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
20
ns
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
ns
S17
SAI_RXD setup before SAI_BCLK
10
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
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Figure 64. SAI Timing — Slave Modes
4.11.12 SCAN JTAG Controller (SJC) Timing Parameters
Figure 65 depicts the SJC test clock input timing. Figure 66 depicts the SJC boundary scan timing.
Figure 67 depicts the SJC test access port. Signal parameters are listed in Table 74.
SJ1
SJ2
JTAG_TCK
(Input)
VM
VIH
SJ2
VM
VIL
SJ3
SJ3
Figure 65. Test Clock Input Timing Diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 66. Boundary Scan (JTAG) Timing Diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ8
JTAG_TDI
JTAG_TMS
(Input)
SJ9
Input Data Valid
SJ10
JTAG_TDO
(Output)
Output Data Valid
SJ11
JTAG_TDO
(Output)
SJ10
JTAG_TDO
(Output)
Output Data Valid
Figure 67. Test Access Port Timing Diagram
JTAG_TCK
(Input)
JTAG_TRST_B
(Input)
SJ13
SJ12
Figure 68. JTAG_TRST_B Timing Diagram
Table 74. JTAG Timing
All Frequencies
Parameter1,2
ID
Unit
Min
Max
0.001
22
MHz
45
—
ns
22.5
—
ns
SJ0
JTAG_TCK frequency of operation 1/(3•TDC)1
SJ1
JTAG_TCK cycle time in crystal mode
SJ2
JTAG_TCK clock pulse width measured at VM2
SJ3
JTAG_TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
5
—
ns
SJ5
Boundary scan input data hold time
24
—
ns
SJ6
JTAG_TCK low to output data valid
—
40
ns
SJ7
JTAG_TCK low to output high impedance
—
40
ns
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Table 74. JTAG Timing (continued)
All Frequencies
Parameter1,2
ID
1
2
Unit
Min
Max
SJ8
JTAG_TMS, JTAG_TDI data set-up time
5
—
ns
SJ9
JTAG_TMS, JTAG_TDI data hold time
25
—
ns
SJ10
JTAG_TCK low to JTAG_TDO data valid
—
44
ns
SJ11
JTAG_TCK low to JTAG_TDO high impedance
—
44
ns
SJ12
JTAG_TRST_B assert time
100
—
ns
SJ13
JTAG_TRST_B set-up time to JTAG_TCK low
40
—
ns
TDC = target frequency of SJC
VM = mid-point voltage
4.11.13 SPDIF Timing Parameters
The Sony/Philips Digital Interface Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 75, Figure 69, and Figure 70 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 75. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
40.0
—
ns
SPDIF_SR_CLK high period
srckph
16.0
—
ns
SPDIF_SR_CLK low period
srckpl
16.0
—
ns
Modulating Tx clock (SPDIF_ST_CLK) period
stclkp
40.0
—
ns
SPDIF_ST_CLK high period
stclkph
16.0
—
ns
SPDIF_ST_CLK low period
stclkpl
16.0
—
ns
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srckp
srckpl
srckph
SPDIF_SR_CLK
VM
VM
(Output)
Figure 69. SPDIF_SR_CLK Timing Diagram
stclkp
stclkpl
SPDIF_ST_CLK
stclkph
VM
VM
(Input)
Figure 70. SPDIF_ST_CLK Timing Diagram
4.11.14 UART I/O Configuration and Timing Parameters
4.11.14.1 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.11.14.1.1 UART Transmitter
Figure 71 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 76 lists the UART RS-232 serial mode transmits timing characteristics.
UA1
UARTx_TX_DATA
(output)
Possible
Parity
Bit
UA1
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA1
UA1
Figure 71. UART RS-232 Serial Mode Transmit Timing Diagram
Table 76. RS-232 Serial Mode Transmit Timing Parameters
ID
UA1
1
2
Parameter
Transmit Bit Time
Symbol
Min
Max
Unit
tTbit
1/Fbaud_rate1 - Tref_clk2
1/Fbaud_rate + Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
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4.11.14.1.2 UART Receiver
Figure 72 depicts the RS-232 serial mode receives timing with 8 data bit/1 stop bit format. Table 77 lists
serial mode receive timing characteristics.
UA2
UARTx_RX_DATA
(output)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Next
Start
Bit
Par Bit STOP
BIT
UA2
UA2
Figure 72. UART RS-232 Serial Mode Receive Timing Diagram
Table 77. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16
x Fbaud_rate)
1/Fbaud_rate +
1/(16 x Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.11.14.1.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA Mode Transmitter
Figure 73 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 78 lists
the transmit timing characteristics.
UA3
UA4
UA3
UA3
UA3
RGMII_TXD
(output)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 4
Bit 3
Bit 5
Bit 6
Bit 7
Possible
Parity
Bit
STOP
BIT
Figure 73. UART IrDA Mode Transmit Timing Diagram
Table 78. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA3
Transmit Bit Time in IrDA mode
tTIRbit
1/Fbaud_rate1 Tref_clk2
1/Fbaud_rate + Tref_clk
—
UA4
Transmit IR Pulse Duration
tTIRpulse
(3/16) x (1/Fbaud_rate) (3/16) x (1/Fbaud_rate)
- Tref_clk
+ Tref_clk
—
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1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
UART IrDA Mode Receiver
Figure 74 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 79 lists the
receive timing characteristics.
UA5
UA6
UA5
UA5
UA5
RGMII_RXD
(input)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 4
Bit 3
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 74. UART IrDA Mode Receive Timing Diagram
Table 79. IrDA Mode Receive Timing Parameters
ID
Parameter
UA5
Receive Bit Time1 in IrDA mode
UA6
Receive IR Pulse Duration
Symbol
Min
Max
Unit
tRIRbit
1/Fbaud_rate2 - 1/(16
x Fbaud_rate)
1/Fbaud_rate + 1/(16 x
Fbaud_rate)
—
tRIRpulse
1.41 s
(5/16) x (1/Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.11.15 USB PHY Parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
• USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
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•
•
•
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
— Portable device only
4.12
A/D converter
The following subsections provide information about A/D converter.
4.12.1
12-bit ADC electrical characteristics
4.12.1.1
12-bit ADC operating conditions
Table 80. 12-bit ADC Operating Conditions
Characteristic
Supply voltage
Conditions
Symb
Typ1
Min
Max
Unit
Comment
Absolute
VDDAD
3.0
-
3.6
V
—
Delta to VDD
(VDD-VDDAD)2
VDDAD
-100
0
100
mV
—
Ground voltage
Delta to VSS
(VSS-VSSAD)
VSSAD
-100
0
100
mV
—
Ref Voltage High
—
VREFH
1.13
VDDAD
VDDAD
V
—
Ref Voltage Low
—
VREFL
VSSAD
VSSAD
VSSAD
V
—
Input Voltage
—
VADIN
VREFL
—
VREFH
V
—
Input Capacitance
8/10/12 bit modes
CADIN
—
1.5
2
pF
—
Input Resistance
ADLPC=0, ADHSC=1
RADIN
—
5
7
kohms
—
ADLPC=0, ADHSC=0
—
12.5
15
kohms
—
ADLPC=1, ADHSC=0
—
25
30
kohms
—
RAS
12 bit mode fADCK =
40MHz ADLSMP=0,
ADSTS=10, ADHSC=1
—
—
1
kohms
Tsamp=150
ns
Analog Source
Resistance
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
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Table 80. 12-bit ADC Operating Conditions (continued)
Characteristic
Conditions
ADC Conversion Clock
Frequency
ADLPC=0, ADHSC=1
12 bit mode
Symb
fADCK
Typ1
Min
Max
Unit
Comment
4
—
40
MHz
—
ADLPC=0, ADHSC=0
12 bit mode
4
—
30
MHz
—
ADLPC=1, ADHSC=0
12 bit mode
4
—
20
MHz
—
1
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
DC potential differences
Figure 75. 12-bit ADC Input Impedance Equivalency Diagram
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4.12.1.1.1
12-bit ADC characteristics
Table 81. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic
[L:] Supply Current
Conditions1
ADLPC=1,
ADHSC=0
Symb
IDDAD
Typ2
Min
—
250
ADLPC=0,
ADHSC=0
350
ADLPC=0,
ADHSC=1
400
Max
Unit
Comment
—
µA
ADLSMP=0
ADSTS=10 ADCO=1
[L:] Supply Current
Stop, Reset, Module
Off
IDDAD
—
0.01
0.8
µA
—
ADC Asynchronous
Clock Source
ADHSC=0
fADACK
—
10
—
MHz
tADACK = 1/fADACK
—
20
—
—
2
—
cycles
—
Sample Cycles
ADHSC=1
ADLSMP=0,
ADSTS=00
Csamp
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
ADLSMP=1,
ADSTS=01
16
ADLSMP=1,
ADSTS=10
20
ADLSMP=1,
ADSTS=11
24
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Table 81. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Conversion Cycles
Conversion Time
[P:][C:] Total
Unadjusted Error
[P:][C:] Differential
Non-Linearity
Conditions1
ADLSMP=0
ADSTS=00
Symb
Cconv
Typ2
Min
—
28
ADLSMP=0
ADSTS=01
30
ADLSMP=0
ADSTS=10
32
ADLSMP=0
ADSTS=11
34
ADLSMP=1
ADSTS=00
38
ADLSMP=1
ADSTS=01
42
ADLSMP=1
ADSTS=10
46
ADLSMP=1,
ADSTS=11
50
ADLSMP=0
ADSTS=00
Tconv
—
0.7
ADLSMP=0
ADSTS=01
0.75
ADLSMP=0
ADSTS=10
0.8
ADLSMP=0
ADSTS=11
0.85
ADLSMP=1
ADSTS=00
0.95
ADLSMP=1
ADSTS=01
1.05
ADLSMP=1
ADSTS=10
1.15
ADLSMP=1,
ADSTS=11
1.25
12 bit mode
Comment
cycles
—
—
µs
Fadc=40 MHz
LSB
1 LSB =
(VREFH VREFL)/2
N
—
LSB
—
4.5
—
10 bit mode
—
2
—
8 bit mode
—
1.5
—
—
1
—
10bit mode
—
0.5
—
8 bit mode
—
0.2
—
DNL
Unit
—
—
12 bit mode
TUE
Max
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Table 81. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
[P:][C:] Integral
Non-Linearity
Conditions1
12 bit mode
Zero-Scale Error
Typ2
Max
2.6
—
10bit mode
—
0.8
—
8 bit mode
—
0.3
—
—
-0.3
—
10bit mode
—
-0.15
—
8 bit mode
—
-0.15
—
—
-2.5
—
10bit mode
—
-0.6
—
8 bit mode
—
-0.3
—
10.7
—
12 bit mode
INL
Min
—
12 bit mode
Full-Scale Error
Symb
EZS
EFS
[L:] Effective Number 12 bit mode
of Bits
ENOB
10.1
[L:] Signal to Noise
plus Distortion
SINAD
SINAD = 6.02 x ENOB + 1.76
1
2
See ENOB
Unit
Comment
LSB
—
LSB
—
LSB
—
Bits
—
dB
—
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
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Boot Mode Configuration
5
Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 82 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX 6ULL Fuse
Map document and the System Boot chapter in i.MX 6ULL Reference Manual (IMX6ULLRM).
Table 82. Fuses and Associated Pins Used for Boot
Pin
Direction at reset
eFuse name
Details
BOOT_MODE0
Input with 100 K pull-down
N/A
Boot mode selection
BOOT_MODE1
Input with 100 K pull-down
N/A
Boot mode selection
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Boot Mode Configuration
Table 82. Fuses and Associated Pins Used for Boot (continued)
Pin
5.2
Direction at reset
eFuse name
LCD_DATA00
Input with 100 K pull-down
BT_CFG1[0]
LCD_DATA01
Input with 100 K pull-down
BT_CFG1[1]
LCD_DATA02
Input with 100 K pull-down
BT_CFG1[2]
LCD_DATA03
Input with 100 K pull-down
BT_CFG1[3]
LCD_DATA04
Input with 100 K pull-down
BT_CFG1[4]
LCD_DATA05
Input with 100 K pull-down
BT_CFG1[5]
LCD_DATA06
Input with 100 K pull-down
BT_CFG1[6]
LCD_DATA07
Input with 100 K pull-down
BT_CFG1[7]
LCD_DATA08
Input with 100 K pull-down
BT_CFG2[0]
LCD_DATA09
Input with 100 K pull-down
BT_CFG2[1]
LCD_DATA10
Input with 100 K pull-down
BT_CFG2[2]
LCD_DATA11
Input with 100 K pull-down
BT_CFG2[3]
LCD_DATA12
Input with 100 K pull-down
BT_CFG2[4]
LCD_DATA13
Input with 100 K pull-down
BT_CFG2[5]
LCD_DATA14
Input with 100 K pull-down
BT_CFG2[6]
LCD_DATA15
Input with 100 K pull-down
BT_CFG2[7]
LCD_DATA16
Input with 100 K pull-down
BT_CFG4[0]
LCD_DATA17
Input with 100 K pull-down
BT_CFG4[1]
LCD_DATA18
Input with 100 K pull-down
BT_CFG4[2]
LCD_DATA19
Input with 100 K pull-down
BT_CFG4[3]
LCD_DATA20
Input with 100 K pull-down
BT_CFG4[4]
LCD_DATA21
Input with 100 K pull-down
BT_CFG4[5]
LCD_DATA22
Input with 100 K pull-down
BT_CFG4[6]
LCD_DATA23
Input with 100 K pull-down
BT_CFG4[7]
Details
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
Boot Device Interface Allocation
The following tables list the interfaces that can be used by the boot process in accordance with the
specific boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC
allocation, which are configured during boot when appropriate.
Table 83. QSPI Boot trough QSPI
Ball Name
Signal Name
Mux
Mode
Common
Quad
Mode
NAND_WP_B
qspi.A_SCLK
Alt2
Yes
Yes
NAND_DQS
qspi.A_SS0_B
Alt2
Yes
Yes
+ Port A
DQS
+ Port A
CS1
+ Port
B
+ Port B
DQS
+ Port B
CS1
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Boot Mode Configuration
Table 83. QSPI Boot trough QSPI (continued)
NAND_READY_B
qspi.A_DATA[0]
Alt2
Yes
Yes
NAND_CE0_B
qspi.A_DATA[1]
Alt2
Yes
Yes
NAND_CE1_B
qspi.A_DATA[2]
Alt2
Yes
Yes
NAND_CLE
qspi.A_DATA[3]
Alt2
Yes
Yes
NAND_DATA05
qspi.B_DATA[3]
Alt2
Yes
NAND_DATA04
qspi.B_DATA[2]
Alt2
Yes
NAND_DATA03
qspi.B_DATA[1]
Alt2
Yes
NAND_DATA02
qspi.B_DATA[0]
Alt2
Yes
NAND_WE_B
qspi.B_SS0_B
Alt2
Yes
NAND_RE_B
qspi.B_SCLK
Alt2
Yes
NAND_DATA07
qspi.A_SS1_B
Alt2
NAND_ALE
qspi.A_DQS
Alt2
NAND_DATA00
qspi.B_SS1_B
Alt2
NAND_DATA01
qspi.B_DQS
Alt2
Yes
Yes
Yes
Yes
Table 84. SPI Boot through ECSPI1
Ball Name
Signal Name
Mux
Mode
Common
CSI_DATA07
ecspi1.MISO
Alt 3
Yes
CSI_DATA06
ecspi1.MOSI
Alt 3
Yes
CSI_DATA04
ecspi1.SCLK
Alt 3
Yes
CSI_DATA05
ecspi1.SS0
Alt 3
LCD_DATA05
ecspi1.SS1
Alt 8
LCD_DATA06
ecspi1.SS2
Alt 8
LCD_DATA07
ecspi1.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
[5:4]=00b
[5:4]=01b
[5:4]=10b
[5:4]=11b
Yes
Yes
Yes
Yes
Table 85. SPI Boot through ECSPI2
Ball Name
Signal Name
Mux Mode
Common
CSI_DATA03
ecspi2.MISO
Alt 3
Yes
CSI_DATA02
ecspi2.MOSI
Alt 3
Yes
CSI_DATA00
ecspi2.SCLK
Alt 3
Yes
CSI_DATA01
ecspi2.SS0
Alt 3
LCD_HSYNC
ecspi2.SS1
Alt 8
BOOT_CFG
4[5:4]=00b
BOOT_CFG4 BOOT_CFG4 BOOT_CFG4
[5:4]=01b
[5:4]=10b
[5:4]=11b
Yes
Yes
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Boot Mode Configuration
Table 85. SPI Boot through ECSPI2 (continued)
LCD_VSYNC
ecspi2.SS2
Alt 8
LCD_RESET
ecspi2.SS3
Alt 8
Yes
Yes
Table 86. SPI Boot through ECSPI3
Ball Name
Signal Name
Mux
Mode
Common
UART2_RTS_B
ecspi3.MISO
Alt 8
Yes
UART2_CTS_B
ecspi3.MOSI
Alt 8
Yes
UART2_RX_DATA
ecspi3.SCLK
Alt 8
Yes
UART2_TX_DATA
ecspi3.SS0
Alt 8
NAND_ALE
ecspi3.SS1
Alt 8
NAND_RE_B
ecspi3.SS2
Alt 8
NAND_WE_B
ecspi3.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[ BOOT_CFG4
[5:4]=00b
5:4]=01b
5:4]=10b
[5:4]=11b
Yes
Yes
Yes
Yes
Table 87. SPI Boot through ECSPI4
Ball Name
Signal Name
Mux
Mode
Common
ENET2_TX_CLK
ecspi4.MISO
Alt 3
Yes
ENET2_TX_EN
ecspi4.MOSI
Alt 3
Yes
ENET2_TX_DATA1
ecspi4.SCLK
Alt 3
Yes
ENET2_RX_ER
ecspi4.SS0
Alt 3
NAND_DATA01
ecspi4.SS1
Alt 8
NAND_DATA02
ecspi4.SS2
Alt 8
NAND_DATA03
ecspi4.SS3
Alt 8
BOOT_CFG4 BOOT_CFG4[ BOOT_CFG4[
[5:4]=00b
5:4]=01b
5:4]=10b
BOOT_CFG
4[5:4]=11b
Yes
Yes
Yes
Yes
Table 88. NAND Boot through GPMI
Ball Name
Signal Name
Mux Mode
Common
NAND_CLE
rawnand.CLE
Alt 0
Yes
NAND_ALE
rawnand.ALE
Alt 0
Yes
NAND_WP_B
rawnand.WP_B
Alt 0
Yes
NAND_READY_B
rawnand.READY_B
Alt 0
Yes
NAND_CE0_B
rawnand.CE0_B
Alt 0
Yes
NAND_CE1_B
rawnand.CE1_B
Alt 0
NAND_RE_B
rawnand.RE_B
Alt 0
BOOT_CFG1[3:2]=
01b
BOOT_CFG1[3:2]=
10b
Yes
Yes
Yes
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Boot Mode Configuration
Table 88. NAND Boot through GPMI (continued)
BOOT_CFG1[3:2]=
01b
BOOT_CFG1[3:2]=
10b
Ball Name
Signal Name
Mux Mode
Common
NAND_WE_B
rawnand.WE_B
Alt 0
Yes
NAND_DATA00
rawnand.DATA00
Alt 0
Yes
NAND_DATA01
rawnand.DATA01
Alt 0
Yes
NAND_DATA02
rawnand.DATA02
Alt 0
Yes
NAND_DATA03
rawnand.DATA03
Alt 0
Yes
NAND_DATA04
rawnand.DATA04
Alt 0
Yes
NAND_DATA05
rawnand.DATA05
Alt 0
Yes
NAND_DATA06
rawnand.DATA06
Alt 0
Yes
NAND_DATA07
rawnand.DATA07
Alt 0
Yes
NAND_DQS
rawnand.DQS
Alt 0
Yes
CSI_MCLK
rawnand.CE2_B
Alt 2
Yes
CSI_PIXCLK
rawnand.CE3_B
Alt 2
Yes
Table 89. SD/MMC Boot through USDHC1
Ball Name
Signal Name
Mux
Mode
UART1_RTS_B
usdhc1.CD_B
Alt 2
SD1_CLK
usdhc1.CLK
Alt 0
Yes
SD1_CMD
usdhc1.CMD
Alt 0
Yes
SD1_DATA0
usdhc1.DATA0
Alt 0
Yes
SD1_DATA1
usdhc1.DATA1
Alt 0
Yes
Yes
SD1_DATA2
usdhc1.DATA2
Alt 0
Yes
Yes
SD1_DATA3
usdhc1.DATA3
Alt 0
NAND_READY_B
usdhc1.DATA4
Alt 1
Yes
NAND_CE0_B
usdhc1.DATA5
Alt 1
Yes
NAND_CE1_B
usdhc1.DATA6
Alt 1
Yes
NAND_CLE
usdhc1.DATA7
Alt 1
Yes
GPIO1_IO09
usdhc1.RESET_B
Alt 5
Yes
GPIO1_IO05
usdhc1.VSELECT
Alt 4
Yes
Common
4-bit
8-bit
BOOT_CFG1[1]=1
(SD Power Cycle)
SDMMC
MFG
mode
Yes
Yes
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Boot Mode Configuration
Table 90. SD/MMC Boot through USDHC2
Ball Name
Signal Name
Mux Mode
Commo
n
NAND_RE_B
usdhc2.CLK
Alt 1
Yes
NAND_WE_B
usdhc2.CMD
Alt 1
Yes
NAND_DATA00
usdhc2.DATA0
Alt 1
Yes
NAND_DATA01
usdhc2.DATA1
NAND_DATA02
BOOT_CFG1[1]=1
(SD Power Cycle)
4-bit
8-bit
Alt 1
Yes
Yes
usdhc2.DATA2
Alt 1
Yes
Yes
NAND_DATA03
usdhc2.DATA3
Alt 1
NAND_DATA04
usdhc2.DATA4
Alt 1
Yes
NAND_DATA05
usdhc2.DATA5
Alt 1
Yes
NAND_DATA06
usdhc2.DATA6
Alt 1
Yes
NAND_DATA07
usdhc2.DATA7
Alt 1
Yes
NAND_ALE
usdhc2.RESET_B
Alt 5
Yes
GPIO1_IO08
usdhc2.VSELECT
Alt 4
Yes
Yes
Table 91. NOR/OneNAND Boot through EIM
Ball Name
Signal Name
Mux Mode
Common
CSI_DATA00
weim.AD[0]
Alt 4
Yes
CSI_DATA01
weim.AD[1]
Alt 4
Yes
CSI_DATA02
weim.AD[2]
Alt 4
Yes
CSI_DATA03
weim.AD[3]
Alt 4
Yes
CSI_DATA04
weim.AD[4]
Alt 4
Yes
CSI_DATA05
weim.AD[5]
Alt 4
Yes
CSI_DATA06
weim.AD[6]
Alt 4
Yes
CSI_DATA07
weim.AD[7]
Alt 4
Yes
NAND_DATA00
weim.AD[8]
Alt 4
Yes
NAND_DATA01
weim.AD[9]
Alt 4
Yes
NAND_DATA02
weim.AD[10]
Alt 4
Yes
NAND_DATA03
weim.AD[11]
Alt 4
Yes
NAND_DATA04
weim.AD[12]
Alt 4
Yes
NAND_DATA05
weim.AD[13]
Alt 4
Yes
NAND_DATA06
weim.AD[14]
Alt 4
Yes
NAND_DATA07
weim.AD[15]
Alt 4
Yes
ADL16
Non-Mux
AD16 Mux
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Boot Mode Configuration
Table 91. NOR/OneNAND Boot through EIM (continued)
ADL16
Non-Mux
AD16 Mux
Alt 4
Yes
Yes
weim.ADDR[17]
Alt 4
Yes
Yes
NAND_CE1_B
weim.ADDR[18]
Alt 4
Yes
Yes
SD1_CMD
weim.ADDR[19]
Alt 4
Yes
Yes
SD1_CLK
weim.ADDR[20]
Alt 4
Yes
Yes
SD1_DATA0
weim.ADDR[21]
Alt 4
Yes
Yes
SD1_DATA1
weim.ADDR[22]
Alt 4
Yes
Yes
SD1_DATA2
weim.ADDR[23]
Alt 4
Yes
Yes
SD1_DATA3
weim.ADDR[24]
Alt 4
Yes
Yes
ENET2_RXER
weim.ADDR[25]
Alt 4
Yes
Yes
ENET2_CRS_DV
weim.ADDR[26]
Alt 4
Yes
Yes
CSI_MCLK
weim.CS0_B
Alt 4
LCD_DATA08
weim.DATA[0]
Alt 4
Yes
LCD_DATA09
weim.DATA[1]
Alt 4
Yes
LCD_DATA10
weim.DATA[2]
Alt 4
Yes
LCD_DATA11
weim.DATA[3]
Alt 4
Yes
LCD_DATA12
weim.DATA[4]
Alt 4
Yes
LCD_DATA13
weim.DATA[5]
Alt 4
Yes
LCD_DATA14
weim.DATA[6]
Alt 4
Yes
LCD_DATA15
weim.DATA[7]
Alt 4
Yes
LCD_DATA16
weim.DATA[8]
Alt 4
Yes
LCD_DATA17
weim.DATA[9]
Alt 4
Yes
LCD_DATA18
weim.DATA[10]
Alt 4
Yes
LCD_DATA19
weim.DATA[11]
Alt 4
Yes
LCD_DATA20
weim.DATA[12]
Alt 4
Yes
LCD_DATA21
weim.DATA[13]
Alt 4
Yes
LCD_DATA22
weim.DATA[14]
Alt 4
Yes
LCD_DATA23
weim.DATA[15]
Alt 4
Yes
NAND_RE_B
weim.EB_B[0]
Alt 4
Yes
Yes
NAND_WE_B
weim.EB_B[1]
Alt 4
Yes
Yes
CSI_HSYNC
weim.LBA_B
Alt 4
Ball Name
Signal Name
Mux Mode
NAND_CLE
weim.ADDR[16]
NAND_ALE
Common
Yes
Yes
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Boot Mode Configuration
Table 91. NOR/OneNAND Boot through EIM (continued)
Ball Name
Signal Name
Mux Mode
Common
CSI_PIXCLK
weim.OE
Alt 4
Yes
CSI_VSYNC
weim.RW
Alt 4
Yes
ADL16
Non-Mux
AD16 Mux
Table 92. Serial Download through UART1
Ball Name
Signal Name
Mux Mode
Common
UART1_TX_DATA
uart1.TX_DATA
Alt 0
Yes
UART1_RX_DATA
uart1.RX_DATA
Alt 0
Yes
Table 93. Serial Download through UART2
Ball Name
Signal Name
Mux Mode
Common
UART2_TX_DATA
uart2.TX_DATA
Alt 0
Yes
UART2_RX_DATA
uart2.RX_DATA
Alt 0
Yes
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Package Information and Contact Assignments
6
Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
6.1.1
14 x 14 mm Package Information
14 x 14 mm, 0.8 mm Pitch, Ball Matrix
Figure 76 shows the top, bottom, and side views of the 14 x 14 mm BGA package.
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Package Information and Contact Assignments
Figure 76. 14x14 mm BGA, Case x Package Top, Bottom, and Side Views
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Package Information and Contact Assignments
6.1.2
14x14 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 94 shows the device connection list for ground, sense, and reference contact signals.
Table 94. 14x14 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
M13
—
DRAM_VREF
P4
—
GPANIO
R13
—
NGND_KEL0
M12
—
NVCC_CSI
F4
—
NVCC_DRAM
G6, H6, J6, K6, L6, M6
—
NVCC_DRAM_2P5
N6
—
NVCC_ENET
F13
—
NVCC_GPIO
J13
—
NVCC_LCD
E13
—
NVCC_NAND
E7
—
NVCC_PLL
P13
—
NVCC_SD1
C4
—
NVCC_UART
H13
—
VDD_ARM_CAP
G9, G10, G11, H11
—
VDD_HIGH_CAP
R14
—
VDD_HIGH_IN
N13
—
VDD_SNVS_CAP
N12
—
VDD_SNVS_IN
P12
—
VDD_SOC_CAP
G8, H8, J8, J11, K8, K11, L8, L9, L10, L11
—
VDD_SOC_IN
H9, H10, J9, J10, K9, 10
—
VDD_USB_CAP
R12
—
VDDA_ADC_3P3
L13
—
VSS
A1, A17, C3, C7, C11, C15, E8, E11, F6, F7, F8, F9, F10,F11, F12, G3, G5, G7,
G12, G15, H7, H12, J5, J7, J12, K7, K12, L3, L7, L12, M7, M8, M9, M10, M11,
N3, N5, R3, R5, R7, R11, R16, R17, T14, U1, U14, U17
—
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Package Information and Contact Assignments
Table 95 shows an alpha-sorted list of functional contact assignments for the 14x14 mm package.
Table 95. 14x14 mm Functional Contact Assignments
Out of Reset Condition
14x14
Ball
Power
Group
Ball
Type
BOOT_MODE0
T10
VDD_SNVS_IN
BOOT_MODE1
U10
CCM_CLK1_N
Ball Name
Default
Mode
Default
Function
Input/
Output
GPIO
ALT5
GPIO5_IO10
Input
100 k
pull-down
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO11
Input
100 k
pull-down
P16
VDD_HIGH_CAP
CCM
—
CCM_CLK1_N
—
—
CCM_CLK1_P
P17
VDD_HIGH_CAP
CCM
—
CCM_CLK1_P
—
—
CCM_PMIC_STBY_REQ
U9
VDD_SNVS_IN
CCM
ALT0
CCM_PMIC_VSTBY_REQ
Output
—
CSI_DATA00
E4
NVCC_CSI
GPIO
ALT5
GPIO4_IO21
Input
Keeper
CSI_DATA01
E3
NVCC_CSI
GPIO
ALT5
GPIO4_IO22
Input
Keeper
CSI_DATA02
E2
NVCC_CSI
GPIO
ALT5
GPIO4_IO23
Input
Keeper
CSI_DATA03
E1
NVCC_CSI
GPIO
ALT5
GPIO4_IO24
Input
Keeper
CSI_DATA04
D4
NVCC_CSI
GPIO
ALT5
GPIO4_IO25
Input
Keeper
CSI_DATA05
D3
NVCC_CSI
GPIO
ALT5
GPIO4_IO26
Input
Keeper
CSI_DATA06
D2
NVCC_CSI
GPIO
ALT5
GPIO4_IO27
Input
Keeper
CSI_DATA07
D1
NVCC_CSI
GPIO
ALT5
GPIO4_IO28
Input
Keeper
CSI_HSYNC
F3
NVCC_CSI
GPIO
ALT5
GPIO4_IO20
Input
Keeper
CSI_MCLK
F5
NVCC_CSI
GPIO
ALT5
GPIO4_IO17
Input
Keeper
CSI_PIXCLK
E5
NVCC_CSI
GPIO
ALT5
GPIO4_IO18
Input
Keeper
CSI_VSYNC
F2
NVCC_CSI
GPIO
ALT5
GPIO4_IO19
Input
Keeper
DRAM_ADDR00
L5
NVCC_DRAM
MMDC
ALT0
DRAM_ADDR00
Output
100 k
pull-up
DRAM_ADDR01
H2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR01
Output
100 k
pull-up
DRAM_ADDR02
K1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR02
Output
100 k
pull-up
DRAM_ADDR03
M2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR03
Output
100 k
pull-up
DRAM_ADDR04
K4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR04
Output
100 k
pull-up
DRAM_ADDR05
L1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR05
Output
100 k
pull-up
DRAM_ADDR06
G2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR06
Output
100 k
pull-up
Value
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Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
DRAM_ADDR07
H4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR07
Output
100 k
pull-up
DRAM_ADDR08
J4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR08
Output
100 k
pull-up
DRAM_ADDR09
L2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR09
Output
100 k
pull-up
DRAM_ADDR10
M4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR10
Output
100 k
pull-up
DRAM_ADDR11
K3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR11
Output
100 k
pull-up
DRAM_ADDR12
L4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR12
Output
100 k
pull-up
DRAM_ADDR13
H3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR13
Output
100 k
pull-up
DRAM_ADDR14
G1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR14
Output
100 k
pull-up
DRAM_ADDR15
K5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR15
Output
100 k
pull-up
DRAM_CAS_B
J2
NVCC_DRAM
DDR
ALT0
DRAM_CAS_B
Output
100 k
pull-up
DRAM_CS0_B
N2
NVCC_DRAM
DDR
ALT0
DRAM_CS0_B
Output
100 k
pull-up
DRAM_CS1_B
H5
NVCC_DRAM
DDR
ALT0
DRAM_CS1_B
Output
100 k
pull-up
DRAM_DATA00
T4
NVCC_DRAM
DDR
ALT0
DRAM_DATA00
Input
100 k
pull-up
DRAM_DATA01
U6
NVCC_DRAM
DDR
ALT0
DRAM_DATA01
Input
100 k
pull-up
DRAM_DATA02
T6
NVCC_DRAM
DDR
ALT0
DRAM_DATA02
Input
100 k
pull-up
DRAM_DATA03
U7
NVCC_DRAM
DDR
ALT0
DRAM_DATA03
Input
100 k
pull-up
DRAM_DATA04
U8
NVCC_DRAM
DDR
ALT0
DRAM_DATA04
Input
100 k
pull-up
DRAM_DATA05
T8
NVCC_DRAM
DDR
ALT0
DRAM_DATA05
Input
100 k
pull-up
DRAM_DATA06
T5
NVCC_DRAM
DDR
ALT0
DRAM_DATA06
Input
100 k
pull-up
DRAM_DATA07
U4
NVCC_DRAM
DDR
ALT0
DRAM_DATA07
Input
100 k
pull-up
DRAM_DATA08
U2
NVCC_DRAM
DDR
ALT0
DRAM_DATA08
Input
100 k
pull-up
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Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
DRAM_DATA09
U3
NVCC_DRAM
DDR
ALT0
DRAM_DATA09
Input
100 k
pull-up
DRAM_DATA10
U5
NVCC_DRAM
DDR
ALT0
DRAM_DATA10
Input
100 k
pull-up
DRAM_DATA11
R4
NVCC_DRAM
DDR
ALT0
DRAM_DATA11
Input
100 k
pull-up
DRAM_DATA12
P5
NVCC_DRAM
DDR
ALT0
DRAM_DATA12
Input
100 k
pull-up
DRAM_DATA13
P3
NVCC_DRAM
DDR
ALT0
DRAM_DATA13
Input
100 k
pull-up
DRAM_DATA14
R2
NVCC_DRAM
DDR
ALT0
DRAM_DATA14
Input
100 k
pull-up
DRAM_DATA15
R1
NVCC_DRAM
DDR
ALT0
DRAM_DATA15
Input
100 k
pull-up
DRAM_DQM0
T7
NVCC_DRAM
DDR
ALT0
DRAM_DQM0
Output
100 k
pull-up
DRAM_DQM1
T3
NVCC_DRAM
DDR
ALT0
DRAM_DQM1
Output
100 k
pull-up
DRAM_ODT0
N1
NVCC_DRAM
DDR
ALT0
DRAM_ODT0
Output
100 k
pull-down
DRAM_ODT1
F1
NVCC_DRAM
DDR
ALT0
DRAM_ODT1
Output
100 k
pull-down
DRAM_RAS_B
M5
NVCC_DRAM
DDR
ALT0
DRAM_RAS_B
Output
100 k
pull-up
DRAM_RESET
G4
NVCC_DRAM
DDR
ALT0
DRAM_RESET
Output
100 k
pull-down
DRAM_SDBA0
M1
NVCC_DRAM
DDR
ALT0
DRAM_SDBA0
Output
100 k
pull-up
DRAM_SDBA1
H1
NVCC_DRAM
DDR
ALT0
DRAM_SDBA1
Output
100 k
pull-up
DRAM_SDBA2
K2
NVCC_DRAM
DDR
ALT0
DRAM_SDBA2
Output
100 k
pull-up
DRAM_SDCKE0
M3
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE0
Output
100 k
pull-down
DRAM_SDCKE1
J3
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE1
Output
100 k
pull-down
DRAM_SDCLK0_N
P2
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDCLK0_N
Input
100 k
pull-up
DRAM_SDCLK0_P
P1
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDCLK0_P
Input
100 k
pull-up
DRAM_SDQS0_N
P7
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS0_N
Input
100 k
pull-down
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NXP Semiconductors
Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
P6
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS0_P
Input
100 k
pull-down
DRAM_SDQS1_N
T2
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS1_N
Input
100 k
pull-down
DRAM_SDQS1_P
T1
NVCC_DRAM
DDRCL
K
ALT0
DRAM_SDQS1_P
Input
100 k
pull-down
DRAM_SDWE_B
J1
NVCC_DRAM
DDR
ALT0
DRAM_SDWE_B
Output
100 k
pull-up
DRAM_ZQPAD
N4
NVCC_DRAM
GPIO
—
DRAM_ZQPAD
Input
Keeper
ENET1_RX_DATA0
F16
NVCC_ENET
GPIO
ALT5
GPIO2_IO0
Input
Keeper
ENET1_RX_DATA1
E17
NVCC_ENET
GPIO
ALT5
GPIO2_IO1
Input
Keeper
ENET1_RX_EN
E16
NVCC_ENET
GPIO
ALT5
GPIO2_IO2
Input
Keeper
ENET1_RX_ER
D15
NVCC_ENET
GPIO
ALT5
GPIO2_IO7
Input
Keeper
ENET1_TX_CLK
F14
NVCC_ENET
GPIO
ALT5
GPIO2_IO6
Input
Keeper
ENET1_TX_DATA0
E15
NVCC_ENET
GPIO
ALT5
GPIO2_IO3
Input
Keeper
ENET1_TX_DATA1
E14
NVCC_ENET
GPIO
ALT5
GPIO2_IO4
Input
Keeper
ENET1_TX_EN
F15
NVCC_ENET
GPIO
ALT5
GPIO2_IO5
Input
Keeper
ENET2_RX_DATA0
C17
NVCC_ENET
GPIO
ALT5
GPIO2_IO8
Input
Keeper
ENET2_RX_DATA1
C16
NVCC_ENET
GPIO
ALT5
GPIO2_IO9
Input
Keeper
ENET2_RX_EN
B17
NVCC_ENET
GPIO
ALT5
GPIO2_IO10
Input
Keeper
ENET2_RX_ER
D16
NVCC_ENET
GPIO
ALT5
GPIO2_IO15
Input
Keeper
ENET2_TX_CLK
D17
NVCC_ENET
GPIO
ALT5
GPIO2_IO14
Input
Keeper
ENET2_TX_DATA0
A15
NVCC_ENET
GPIO
ALT5
GPIO2_IO11
Input
Keeper
ENET2_TX_DATA1
A16
NVCC_ENET
GPIO
ALT5
GPIO2_IO12
Input
Keeper
ENET2_TX_EN
B15
NVCC_ENET
GPIO
ALT5
GPIO2_IO13
Input
Keeper
GPIO1_IO00
K13
NVCC_GPIO
GPIO
ALT5
GPIO1_IO00
Input
Keeper
GPIO1_IO01
L15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO01
Input
Keeper
GPIO1_IO02
L14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO02
Input
Keeper
GPIO1_IO03
L17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO03
Input
Keeper
GPIO1_IO04
M16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO04
Input
Keeper
GPIO1_IO05
M17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO05
Input
Keeper
GPIO1_IO06
K17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO06
Input
Keeper
GPIO1_IO07
L16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO07
Input
Keeper
GPIO1_IO08
N17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO08
Input
Keeper
GPIO1_IO09
M15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO09
Input
Keeper
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119
Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
JTAG_MOD
P15
NVCC_GPIO
SJC
ALT0
SJC_MOD
Input
100 k
pull-up
JTAG_TCK
M14
NVCC_GPIO
SJC
ALT0
SJC_TCK
Input
47 k
pull-up
JTAG_TDI
N16
NVCC_GPIO
SJC
ALT0
SJC_TDI
Input
47 k
pull-up
JTAG_TDO
N15
NVCC_GPIO
SJC
ALT0
SJC_TDO
Output
Keeper
JTAG_TMS
P14
NVCC_GPIO
SJC
ALT0
SJC_TMS
Input
47 k
pull-up
JTAG_TRST_B
N14
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
A8
NVCC_LCD
GPIO
ALT5
GPIO3_IO0
Input
Keeper
LCD_DATA00
B9
NVCC_LCD
GPIO
ALT5
GPIO3_IO5
Input
Keeper
LCD_DATA01
A9
NVCC_LCD
GPIO
ALT5
GPIO3_IO6
Input
Keeper
LCD_DATA02
E10
NVCC_LCD
GPIO
ALT5
GPIO3_IO7
Input
Keeper
LCD_DATA03
D10
NVCC_LCD
GPIO
ALT5
GPIO3_IO8
Input
Keeper
LCD_DATA04
C10
NVCC_LCD
GPIO
ALT5
GPIO3_IO9
Input
Keeper
LCD_DATA05
B10
NVCC_LCD
GPIO
ALT5
GPIO3_IO10
Input
Keeper
LCD_DATA06
A10
NVCC_LCD
GPIO
ALT5
GPIO3_IO11
Input
Keeper
LCD_DATA07
D11
NVCC_LCD
GPIO
ALT5
GPIO3_IO12
Input
Keeper
LCD_DATA08
B11
NVCC_LCD
GPIO
ALT5
GPIO3_IO13
Input
Keeper
LCD_DATA09
A11
NVCC_LCD
GPIO
ALT5
GPIO3_IO14
Input
Keeper
LCD_DATA10
E12
NVCC_LCD
GPIO
ALT5
GPIO3_IO15
Input
Keeper
LCD_DATA11
D12
NVCC_LCD
GPIO
ALT5
GPIO3_IO16
Input
Keeper
LCD_DATA12
C12
NVCC_LCD
GPIO
ALT5
GPIO3_IO17
Input
Keeper
LCD_DATA13
B12
NVCC_LCD
GPIO
ALT5
GPIO3_IO18
Input
Keeper
LCD_DATA14
A12
NVCC_LCD
GPIO
ALT5
GPIO3_IO19
Input
Keeper
LCD_DATA15
D13
NVCC_LCD
GPIO
ALT5
GPIO3_IO20
Input
Keeper
LCD_DATA16
C13
NVCC_LCD
GPIO
ALT5
GPIO3_IO21
Input
Keeper
LCD_DATA17
B13
NVCC_LCD
GPIO
ALT5
GPIO3_IO22
Input
Keeper
LCD_DATA18
A13
NVCC_LCD
GPIO
ALT5
GPIO3_IO23
Input
Keeper
LCD_DATA19
D14
NVCC_LCD
GPIO
ALT5
GPIO3_IO24
Input
Keeper
LCD_DATA20
C14
NVCC_LCD
GPIO
ALT5
GPIO3_IO25
Input
Keeper
LCD_DATA21
B14
NVCC_LCD
GPIO
ALT5
GPIO3_IO26
Input
Keeper
LCD_DATA22
A14
NVCC_LCD
GPIO
ALT5
GPIO3_IO27
Input
Keeper
LCD_DATA23
B16
NVCC_LCD
GPIO
ALT5
GPIO3_IO28
Input
Keeper
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NXP Semiconductors
Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
LCD_ENABLE
B8
NVCC_LCD
GPIO
ALT5
GPIO3_IO1
Input
Keeper
LCD_HSYNC
D9
NVCC_LCD
GPIO
ALT5
GPIO3_IO2
Input
Keeper
LCD_RESET
E9
NVCC_LCD
GPIO
ALT5
GPIO3_IO4
Input
Keeper
LCD_VSYNC
C9
NVCC_LCD
GPIO
ALT5
GPIO3_IO3
Input
Keeper
NAND_ALE
B4
NVCC_NAND
GPIO
ALT5
GPIO4_IO10
Input
Keeper
NAND_CE0_B
C5
NVCC_NAND
GPIO
ALT5
GPIO4_IO13
Input
Keeper
NAND_CE1_B
B5
NVCC_NAND
GPIO
ALT5
GPIO4_IO14
Input
Keeper
NAND_CLE
A4
NVCC_NAND
GPIO
ALT5
GPIO4_IO15
Input
Keeper
NAND_DATA00
D7
NVCC_NAND
GPIO
ALT5
GPIO4_IO2
Input
Keeper
NAND_DATA01
B7
NVCC_NAND
GPIO
ALT5
GPIO4_IO3
Input
Keeper
NAND_DATA02
A7
NVCC_NAND
GPIO
ALT5
GPIO4_IO4
Input
Keeper
NAND_DATA03
D6
NVCC_NAND
GPIO
ALT5
GPIO4_IO5
Input
Keeper
NAND_DATA04
C6
NVCC_NAND
GPIO
ALT5
GPIO4_IO6
Input
Keeper
NAND_DATA05
B6
NVCC_NAND
GPIO
ALT5
GPIO4_IO7
Input
Keeper
NAND_DATA06
A6
NVCC_NAND
GPIO
ALT5
GPIO4_IO8
Input
Keeper
NAND_DATA07
A5
NVCC_NAND
GPIO
ALT5
GPIO4_IO9
Input
Keeper
NAND_DQS
E6
NVCC_NAND
GPIO
ALT5
GPIO4_IO16
Input
Keeper
NAND_RE_B
D8
NVCC_NAND
GPIO
ALT5
GPIO4_IO0
Input
Keeper
NAND_READY_B
A3
NVCC_NAND
GPIO
ALT5
GPIO4_IO12
Input
Keeper
NAND_WE_B
C8
NVCC_NAND
GPIO
ALT5
GPIO4_IO1
Input
Keeper
NAND_WP_B
D5
NVCC_NAND
GPIO
ALT5
GPIO4_IO11
Input
Keeper
ONOFF
R8
VDD_SNVS_IN
SRC
ALT0
SRC_RESET_B
Input
100 k
pull-up
POR_B
P8
VDD_SNVS_IN
SRC
ALT0
SRC_POR_B
Input
100 k
pull-up
RTC_XTALI
T11
VDD_SNVS_CAP ANALO
G
—
RTC_XTALI
—
—
RTC_XTALO
U11
VDD_SNVS_CAP ANALO
G
—
RTC_XTALO
—
—
SD1_CLK
C1
NVCC_SD
GPIO
ALT5
GPIO2_IO17
Input
Keeper
SD1_CMD
C2
NVCC_SD
GPIO
ALT5
GPIO2_IO16
Input
Keeper
SD1_DATA0
B3
NVCC_SD
GPIO
ALT5
GPIO2_IO18
Input
Keeper
SD1_DATA1
B2
NVCC_SD
GPIO
ALT5
GPIO2_IO19
Input
Keeper
SD1_DATA2
B1
NVCC_SD
GPIO
ALT5
GPIO2_IO20
Input
Keeper
SD1_DATA3
A2
NVCC_SD
GPIO
ALT5
GPIO2_IO21
Input
Keeper
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Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
T9
VDD_SNVS_IN
GPIO
ALT0
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
SNVS_TAMPER0
R10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO00/SNVS_TAMPE
R01
Input
Keeper/F
loating1,2
SNVS_TAMPER1
R9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO01/SNVS_TAMPE
R11
Input
Keeper/F
loating1,2
SNVS_TAMPER2
P11
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO02/SNVS_TAMPE
R21
Input
Keeper/F
loating1,2
SNVS_TAMPER3
P10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO03/SNVS_TAMPE
R31
Input
Keeper/F
loating1,2
SNVS_TAMPER4
P9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO04/SNVS_TAMPE
R41
Input
Keeper/F
loating1,2
SNVS_TAMPER5
N8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO05/SNVS_TAMPE
R51
Input
Keeper/F
loating1,2
SNVS_TAMPER6
N11
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO06/SNVS_TAMPE
R61
Input
Keeper/F
loating1,2
SNVS_TAMPER7
N10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO07/SNVS_TAMPE
R71
Input
Keeper/F
loating1,2
SNVS_TAMPER8
N9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO08/SNVS_TAMPE
R81
Input
Keeper/F
loating1,2
SNVS_TAMPER9
R6
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO09/SNVS_TAMPE
R91
Input
Keeper/F
loating1,2
TEST_MODE
N7
VDD_SNVS_IN
TCU
ALT0
TCU_TEST_MODE
Input
Keeper
UART1_CTS_B
K15
NVCC_UART
GPIO
ALT5
GPIO1_IO18
Input
Keeper
UART1_RTS_B
J14
NVCC_UART
GPIO
ALT5
GPIO1_IO19
Input
Keeper
UART1_RX_DATA
K16
NVCC_UART
GPIO
ALT5
GPIO1_IO17
Input
Keeper
UART1_TX_DATA
K14
NVCC_UART
GPIO
ALT5
GPIO1_IO16
Input
Keeper
UART2_CTS_B
J15
NVCC_UART
GPIO
ALT5
GPIO1_IO22
Input
Keeper
UART2_RTS_B
H14
NVCC_UART
GPIO
ALT5
GPIO1_IO23
Input
Keeper
UART2_RX_DATA
J16
NVCC_UART
GPIO
ALT5
GPIO1_IO21
Input
Keeper
UART2_TX_DATA
J17
NVCC_UART
GPIO
ALT5
GPIO1_IO20
Input
Keeper
UART3_CTS_B
H15
NVCC_UART
GPIO
ALT5
GPIO1_IO26
Input
Keeper
UART3_RTS_B
G14
NVCC_UART
GPIO
ALT5
GPIO1_IO27
Input
Keeper
UART3_RX_DATA
H16
NVCC_UART
GPIO
ALT5
GPIO1_IO25
Input
Keeper
UART3_TX_DATA
H17
NVCC_UART
GPIO
ALT5
GPIO1_IO24
Input
Keeper
UART4_RX_DATA
G16
NVCC_UART
GPIO
ALT5
GPIO1_IO29
Input
Keeper
UART4_TX_DATA
G17
NVCC_UART
GPIO
ALT5
GPIO1_IO28
Input
Keeper
UART5_RX_DATA
G13
NVCC_UART
GPIO
ALT5
GPIO1_IO31
Input
Keeper
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Package Information and Contact Assignments
Table 95. 14x14 mm Functional Contact Assignments (continued)
UART5_TX_DATA
F17
NVCC_UART
GPIO
ALT5
GPIO1_IO30
Input
Keeper
USB_OTG1_CHD_B
U16
OPEN DRAIN
GPIO
—
USB_OTG1_CHD_B
—
—
USB_OTG1_DN
T15
VDD_USB_CAP
ANALO
G
—
USB_OTG1_DN
—
—
USB_OTG1_DP
U15
VDD_USB_CAP
ANALO
G
—
USB_OTG1_DP
—
—
USB_OTG1_VBUS
T12
USB_VBUS
VBUS
POWE
R
—
USB_OTG1_VBUS
—
—
USB_OTG2_DN
T13
VDD_USB_CAP
ANALO
G
—
USB_OTG2_DN
—
—
USB_OTG2_DP
U13
VDD_USB_CAP
ANALO
G
—
USB_OTG2_DP
—
—
USB_OTG2_VBUS
U12
USB_VBUS
VBUS
POWE
R
—
USB_OTG2_VBUS
—
—
XTALI
T16
NVCC_PLL
ANALO
G
—
XTALI
—
—
XTALO
T17
NVCC_PLL
ANALO
G
—
XTALO
—
—
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2 SNVS_TAMPER0 to SNVS_TAMPER9 is input floating in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
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NXP Semiconductors
123
124
5
6
7
8
9
10
11
12
13
14
NAND_CLE
NAND_DATA07
NAND_DATA06
NAND_DATA02
LCD_CLK
LCD_DATA01
LCD_DATA06
LCD_DATA09
LCD_DATA14
LCD_DATA18
LCD_DATA22
NAND_ALE
NAND_CE1_B
NAND_DATA05
NAND_DATA01
LCD_ENABLE
LCD_DATA00
LCD_DATA05
LCD_DATA08
LCD_DATA13
LCD_DATA17
LCD_DATA21
NVCC_SD1
NAND_CE0_B
NAND_DATA04
VSS
NAND_WE_B
LCD_VSYNC
LCD_DATA04
VSS
LCD_DATA12
LCD_DATA16
LCD_DATA20
CSI_DATA04
NAND_WP_B
NAND_DATA03
NAND_DATA00
NAND_RE_B
LCD_HSYNC
LCD_DATA03
LCD_DATA07
LCD_DATA11
LCD_DATA15
LCD_DATA19
CSI_DATA00
CSI_PIXCLK
NAND_DQS
NVCC_NAND
VSS
LCD_RESET
LCD_DATA02
VSS
LCD_DATA10
NVCC_LCD
ENET1_TX_DATA1
ENET1_TX_DATA0 ENET1_RX_ER
NVCC_CSI
CSI_MCLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NVCC_ENET
ENET1_TX_CLK
ENET1_TX_EN
DRAM_RESET
VSS
NVCC_DRAM
VSS
VDD_SOC_CAP
VDD_ARM_CAP
VDD_ARM_CAP
VDD_ARM_CAP
VSS
UART5_RX_DATA
UART3_RTS_B
VSS
G
UART4_TX_DATA
F
UART5_TX_DATA
ENET2_RX_ER ENET2_RX_DATA1
LCD_DATA23
E
D
C
B
ENET1_RX_DATA1 ENET2_TX_CLK ENET2_RX_DATA0 ENET2_RX_EN
ENET1_RX_EN
4
NAND_READY_B
SD1_DATA0
VSS
CSI_DATA05
CSI_DATA01
CSI_HSYNC
VSS
UART4_RX_DATA ENET1_RX_DATA0
3
SD1_DATA3
SD1_DATA1
SD1_CMD
CSI_DATA06
CSI_DATA02
CSI_VSYNC
DRAM_ADDR06
A
VSS
17
ENET2_TX_DATA1 16
ENET2_TX_EN ENET2_TX_DATA0 15
2
VSS
SD1_DATA2
SD1_CLK
CSI_DATA07
CSI_DATA03
DRAM_ODT1
DRAM_ADDR14
VSS
1
A
B
C
D
E
F
6.1.3
G
Package Information and Contact Assignments
14x14 mm, 0.8 mm Pitch, Ball Map
Table 96 shows the 14x14 mm, 0.8 mm pitch ball map for the i.MX 6ULL.
Table 96. 14x14 mm, 0.8 mm Pitch, Ball Map
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
NXP Semiconductors
NXP Semiconductors
DRAM_ADDR13
DRAM_ADDR07
DRAM_CS1_B
NVCC_DRAM
DRAM_SDCKE1
DRAM_ADDR08
VSS
NVCC_DRAM
DRAM_ADDR11
DRAM_ADDR04
DRAM_ADDR15
NVCC_DRAM
DRAM_ADDR10 DRAM_ADDR12
DRAM_ADDR00
NVCC_DRAM
DRAM_RAS_B
NVCC_DRAM
VSS
DRAM_ZQPAD
VSS
DRAM_DATA13
DRAM_VREF
DRAM_DATA12
VDD_SOC_IN
VDD_SOC_IN
VDD_ARM_CAP
VSS
NVCC_UART
UART2_RTS_B
UART3_CTS_B
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_CAP
VSS
NVCC_GPIO
UART1_RTS_B
UART2_CTS_B
VDD_SOC_IN
VDD_SOC_CAP
VSS
GPIO1_IO00
UART1_TX_DATA
UART1_CTS_B
UART1_RX_DATA UART2_RX_DATA UART3_RX_DATA
UART2_TX_DATA UART3_TX_DATA
VDD_SOC_IN
GPIO1_IO06
K
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
VDDA_ADC_3P3
GPIO1_IO02
GPIO1_IO01
GPIO1_IO07
GPIO1_IO03
L
VSS
VSS
VSS
NGND_KEL0
ADC_VREFH
JTAG_TCK
GPIO1_IO09
GPIO1_IO04
GPIO1_IO05
M
SNVS_TAMPER8
SNVS_TAMPER7
SNVS_TAMPER6
VDD_SNVS_CAP
VDD_HIGH_IN
JTAG_TRST_B
JTAG_TDO
JTAG_TDI
GPIO1_IO08
N
SNVS_TAMPER4
SNVS_TAMPER3
SNVS_TAMPER2
VDD_SNVS_IN
NVCC_PLL
JTAG_TMS
JTAG_MOD
CCM_CLK1_N
CCM_CLK1_P
P
H
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
SNVS_TAMPER5
POR_B
J
VSS
VSS
VSS
VSS
VSS
TEST_MODE
DRAM_SDQS0_N
DRAM_SDQS0_P NVCC_DRAM_2P5
DRAM_ADDR01
DRAM_CAS_B
DRAM_SDBA2
DRAM_ADDR03 DRAM_ADDR09
DRAM_CS0_B
DRAM_SDCLK0_N
VSS
DRAM_SDBA1
DRAM_SDWE_B
DRAM_ADDR02
DRAM_ADDR05
DRAM_SDBA0
DRAM_ODT0
DRAM_SDCLK0_P
DRAM_SDCKE0
H
J
K
L
M
N
P
Package Information and Contact Assignments
Table 96. 14x14 mm, 0.8 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
125
6.2
6.2.1
126
DRAM_DATA15
DRAM_DATA14
VSS
DRAM_DATA11
VSS
SNVS_TAMPER9
VSS
ONOFF
DRAM_SDQS1_P
DRAM_SDQS1_N
DRAM_DQM1
DRAM_DATA00
DRAM_DATA06
DRAM_DATA02
DRAM_DQM0
DRAM_DATA05
VSS
DRAM_DATA08
DRAM_DATA09
DRAM_DATA07
DRAM_DATA10
DRAM_DATA01
DRAM_DATA03
DRAM_DATA04
1
2
3
4
5
6
7
8
GPANAIO
VDD_HIGH_CAP
VDD_HIGH_CAP2
VSS
VSS
USB_OTG2_DN
VSS
USB_OTG1_DN
XTALI
XTALO
USB_OTG2_DP
VSS
USB_OTG1_DP
USB_OTG1_CHD_B
VSS
13
14
15
16
17
R
VDD_USB_CAP
USB_OTG1_VBUS
USB_OTG2_VBUS
12
T
VSS
RTC_XTALI
RTC_XTALO
11
U
SNVS_TAMPER0
BOOT_MODE0
BOOT_MODE1
10
9 CCM_PMIC_STBY_REQ SNVS_PMIC_ON_REQ SNVS_TAMPER1
R
T
U
Package Information and Contact Assignments
Table 96. 14x14 mm, 0.8 mm Pitch, Ball Map (continued)
9x9 mm Package Information
9x9 mm, 0.5 mm Pitch, Ball Matrix
Figure 77 shows the top, bottom, and side views of the 9x9 mm BGA package.
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
NXP Semiconductors
Package Information and Contact Assignments
Figure 77. 9X9 mm BGA, Case x Package Top, Bottom, and Side Views
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
NXP Semiconductors
127
Package Information and Contact Assignments
6.2.2
9x9 mm Supplies Contact Assignments and Functional Contact
Assignments
Table 97 shows the device connection list for ground, sense, and reference contact signals.
Table 97. 9x9 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
ADC_VREFH
N13
—
DRAM_VREF
T1
—
GPANAIO
T11
—
NGND_KEL0
M10
—
NVCC_CSI
E5
—
NVCC_DRAM
G5, L5, M5, N6
—
NVCC_DRAM_2P5
K6
—
NVCC_ENET
G13
—
NVCC_GPIO
M13
—
NVCC_LCD
E13
—
NVCC_NAND
E11
—
NVCC_PLL
T13
—
NVCC_SD1
E7
—
NVCC_UART
L13
—
VDD_ARM_CAP
G9, G10, G11, H9, H10, H11
—
VDD_HIGH_CAP
U11
—
VDD_HIGH_IN
U15
—
VDD_SNVS_CAP
N12
—
VDD_SNVS_IN
P12
—
VDD_SOC_CAP
G7, G8, H7, H8, J7, J8, K7, K8, L7, L8
—
VDD_SOC_IN
J9, J10, J11, K9, K10, K11, L9, L10, L11
—
VDD_USB_CAP
N11
—
VDDA_ADC_3P3
T17
—
VSS
A2, A7, A12, A17, B1, C15, F1, F3, F8, F10, F17, H6, H12, J3, J15, K12, M1, M3,
M8, M17, R3, R9, R12, R15, U1, U6, U13, U17
—
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NXP Semiconductors
Package Information and Contact Assignments
Table 98 shows an alpha-sorted list of functional contact assignments for the 9x9 mm package.
Table 98. 9x9 mm Functional Contact Assignments
Out of Reset Condition
9x9
Ball
Power
Group
Ball
Type
BOOT_MODE0
T8
VDD_SNVS_IN
BOOT_MODE1
U8
CCM_CLK1_N
Ball Name
Default
Mode
Default
Function
Input/
Output
GPIO
ALT5
GPIO5_IO10
Input
100 k
pull-down
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO11
Input
100 k
pull-down
U16
VDD_HIGH_CAP
LVDS
—
CCM_CLK1_N
—
—
CCM_CLK1_P
T16
VDD_HIGH_CAP
LVDS
—
CCM_CLK1_P
—
—
CCM_PMIC_STBY_REQ
U7
VDD_SNVS_IN
GPIO
ALT0
CCM_PMIC_VSTBY_REQ
Output
—
CSI_DATA00
C3
NVCC_CSI
GPIO
ALT5
GPIO4_IO21
Input
Keeper
CSI_DATA01
D4
NVCC_CSI
GPIO
ALT5
GPIO4_IO22
Input
Keeper
CSI_DATA02
B2
NVCC_CSI
GPIO
ALT5
GPIO4_IO23
Input
Keeper
CSI_DATA03
D1
NVCC_CSI
GPIO
ALT5
GPIO4_IO24
Input
Keeper
CSI_DATA04
C4
NVCC_CSI
GPIO
ALT5
GPIO4_IO25
Input
Keeper
CSI_DATA05
B3
NVCC_CSI
GPIO
ALT5
GPIO4_IO26
Input
Keeper
CSI_DATA06
A3
NVCC_CSI
GPIO
ALT5
GPIO4_IO27
Input
Keeper
CSI_DATA07
C2
NVCC_CSI
GPIO
ALT5
GPIO4_IO28
Input
Keeper
CSI_HSYNC
D2
NVCC_CSI
GPIO
ALT5
GPIO4_IO20
Input
Keeper
CSI_MCLK
C1
NVCC_CSI
GPIO
ALT5
GPIO4_IO17
Input
Keeper
CSI_PIXCLK
D5
NVCC_CSI
GPIO
ALT5
GPIO4_IO18
Input
Keeper
CSI_VSYNC
D3
NVCC_CSI
GPIO
ALT5
GPIO4_IO19
Input
Keeper
DRAM_ADDR00
G1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR00
Output
100 k
pull-up
DRAM_ADDR01
G2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR01
Output
100 k
pull-up
DRAM_ADDR02
H1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR02
Output
100 k
pull-up
DRAM_ADDR03
J2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR03
Output
100 k
pull-up
DRAM_ADDR04
M4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR04
Output
100 k
pull-up
DRAM_ADDR05
H2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR05
Output
100 k
pull-up
DRAM_ADDR06
E4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR06
Output
100 k
pull-up
Value
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
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129
Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
DRAM_ADDR07
J4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR07
Output
100 k
pull-up
DRAM_ADDR08
J5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR08
Output
100 k
pull-up
DRAM_ADDR09
J1
NVCC_DRAM
DDR
ALT0
DRAM_ADDR09
Output
100 k
pull-up
DRAM_ADDR10
M2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR10
Output
100 k
pull-up
DRAM_ADDR11
K5
NVCC_DRAM
DDR
ALT0
DRAM_ADDR11
Output
100 k
pull-up
DRAM_ADDR12
L3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR12
Output
100 k
pull-up
DRAM_ADDR13
H4
NVCC_DRAM
DDR
ALT0
DRAM_ADDR13
Output
100 k
pull-up
DRAM_ADDR14
E3
NVCC_DRAM
DDR
ALT0
DRAM_ADDR14
Output
100 k
pull-up
DRAM_ADDR15
E2
NVCC_DRAM
DDR
ALT0
DRAM_ADDR15
Output
100 k
pull-up
DRAM_CAS_B
G4
NVCC_DRAM
DDR
ALT0
DRAM_CAS_B
Output
100 k
pull-up
DRAM_CS0_B
L1
NVCC_DRAM
DDR
ALT0
DRAM_CS0_B
Output
100 k
pull-up
DRAM_CS1_B
H5
NVCC_DRAM
DDR
ALT0
DRAM_CS1_B
Output
100 k
pull-up
DRAM_DATA00
T3
NVCC_DRAM
DDR
ALT0
DRAM_DATA00
Input
100 k
pull-up
DRAM_DATA01
N5
NVCC_DRAM
DDR
ALT0
DRAM_DATA01
Input
100 k
pull-up
DRAM_DATA02
T4
NVCC_DRAM
DDR
ALT0
DRAM_DATA02
Input
100 k
pull-up
DRAM_DATA03
T5
NVCC_DRAM
DDR
ALT0
DRAM_DATA03
Input
100 k
pull-up
DRAM_DATA04
U5
NVCC_DRAM
DDR
ALT0
DRAM_DATA04
Input
100 k
pull-up
DRAM_DATA05
T6
NVCC_DRAM
DDR
ALT0
DRAM_DATA05
Input
100 k
pull-up
DRAM_DATA06
R4
NVCC_DRAM
DDR
ALT0
DRAM_DATA06
Input
100 k
pull-up
DRAM_DATA07
U3
NVCC_DRAM
DDR
ALT0
DRAM_DATA07
Input
100 k
pull-up
DRAM_DATA08
P1
NVCC_DRAM
DDR
ALT0
DRAM_DATA08
Input
100 k
pull-up
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NXP Semiconductors
Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
DRAM_DATA09
U2
NVCC_DRAM
DDR
ALT0
DRAM_DATA09
Input
100 k
pull-up
DRAM_DATA10
P3
NVCC_DRAM
DDR
ALT0
DRAM_DATA10
Input
100 k
pull-up
DRAM_DATA11
R2
NVCC_DRAM
DDR
ALT0
DRAM_DATA11
Input
100 k
pull-up
DRAM_DATA12
P4
NVCC_DRAM
DDR
ALT0
DRAM_DATA12
Input
100 k
pull-up
DRAM_DATA13
N2
NVCC_DRAM
DDR
ALT0
DRAM_DATA13
Input
100 k
pull-up
DRAM_DATA14
N1
NVCC_DRAM
DDR
ALT0
DRAM_DATA14
Input
100 k
pull-up
DRAM_DATA15
P2
NVCC_DRAM
DDR
ALT0
DRAM_DATA15
Input
100 k
pull-up
DRAM_DQM0
U4
NVCC_DRAM
DDR
ALT0
DRAM_DQM0
Output
100 k
pull-up
DRAM_DQM1
R1
NVCC_DRAM
DDR
ALT0
DRAM_DQM1
Output
100 k
pull-up
DRAM_ODT0
K2
NVCC_DRAM
DDR
ALT0
DRAM_ODT0
Output
100 k
pull-down
DRAM_ODT1
E1
NVCC_DRAM
DDR
ALT0
DRAM_ODT1
Output
100 k
pull-down
DRAM_RAS_B
L4
NVCC_DRAM
DDR
ALT0
DRAM_RAS_B
Output
100 k
pull-up
DRAM_RESET
F2
NVCC_DRAM
DDR
ALT0
DRAM_RESET
Output
100 k
pull-down
DRAM_SDBA0
H3
NVCC_DRAM
DDR
ALT0
DRAM_SDBA0
Output
100 k
pull-up
DRAM_SDBA1
F5
NVCC_DRAM
DDR
ALT0
DRAM_SDBA1
Output
100 k
pull-up
DRAM_SDBA2
G3
NVCC_DRAM
DDR
ALT0
DRAM_SDBA2
Output
100 k
pull-up
DRAM_SDCKE0
L2
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE0
Output
100 k
pull-down
DRAM_SDCKE1
K1
NVCC_DRAM
DDR
ALT0
DRAM_SDCKE1
Output
100 k
pull-down
DRAM_SDCLK0_N
K4
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDCLK0_N
Input
100 k
pull-up
DRAM_SDCLK0_P
K3
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDCLK0_P
Input
100 k
pull-up
DRAM_SDQS0_N
R5
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS0_N
Input
100 k
pull-down
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131
Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
DRAM_SDQS0_P
P5
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS0_P
Input
100 k
pull-down
DRAM_SDQS1_N
N4
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS1_P
Input
100 k
pull-down
DRAM_SDQS1_P
N3
NVCC_DRAM
DDRC
LK
ALT0
DRAM_SDQS1_N
Input
100 k
pull-down
DRAM_SDWE_B
F4
NVCC_DRAM
DDR
ALT0
DRAM_SDWE_B
Output
100 k
pull-up
DRAM_ZQPAD
T2
NVCC_DRAM
GPIO
—
DRAM_ZQPAD
Input
Keeper
ENET1_RX_DATA0
G17
NVCC_ENET
GPIO
ALT5
GPIO2_IO0
Input
Keeper
ENET1_RX_DATA1
F16
NVCC_ENET
GPIO
ALT5
GPIO2_IO1
Input
Keeper
ENET1_RX_EN
G16
NVCC_ENET
GPIO
ALT5
GPIO2_IO2
Input
Keeper
ENET1_RX_ER
G14
NVCC_ENET
GPIO
ALT5
GPIO2_IO7
Input
Keeper
ENET1_TX_CLK
G15
NVCC_ENET
GPIO
ALT5
GPIO2_IO6
Input
Keeper
ENET1_TX_DATA0
E16
NVCC_ENET
GPIO
ALT5
GPIO2_IO3
Input
Keeper
ENET1_TX_DATA1
F13
NVCC_ENET
GPIO
ALT5
GPIO2_IO4
Input
Keeper
ENET1_TX_EN
F15
NVCC_ENET
GPIO
ALT5
GPIO2_IO5
Input
Keeper
ENET2_RX_DATA0
E17
NVCC_ENET
GPIO
ALT5
GPIO2_IO8
Input
Keeper
ENET2_RX_DATA1
D17
NVCC_ENET
GPIO
ALT5
GPIO2_IO9
Input
Keeper
ENET2_RX_EN
D16
NVCC_ENET
GPIO
ALT5
GPIO2_IO10
Input
Keeper
ENET2_RX_ER
H13
NVCC_ENET
GPIO
ALT5
GPIO2_IO15
Input
Keeper
ENET2_TX_CLK
H14
NVCC_ENET
GPIO
ALT5
GPIO2_IO14
Input
Keeper
ENET2_TX_DATA0
E14
NVCC_ENET
GPIO
ALT5
GPIO2_IO11
Input
Keeper
ENET2_TX_DATA1
F14
NVCC_ENET
GPIO
ALT5
GPIO2_IO12
Input
Keeper
ENET2_TX_EN
E15
NVCC_ENET
GPIO
ALT5
GPIO2_IO13
Input
Keeper
GPIO1_IO00
M14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO00
Input
Keeper
GPIO1_IO01
M15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO01
Input
Keeper
GPIO1_IO02
M16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO02
Input
Keeper
GPIO1_IO03
N16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO03
Input
Keeper
GPIO1_IO04
N17
NVCC_GPIO
GPIO
ALT5
GPIO1_IO04
Input
Keeper
GPIO1_IO05
P15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO05
Input
Keeper
GPIO1_IO06
N15
NVCC_GPIO
GPIO
ALT5
GPIO1_IO06
Input
Keeper
GPIO1_IO07
N14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO07
Input
Keeper
GPIO1_IO08
P14
NVCC_GPIO
GPIO
ALT5
GPIO1_IO08
Input
Keeper
GPIO1_IO09
P16
NVCC_GPIO
GPIO
ALT5
GPIO1_IO09
Input
Keeper
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Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
JTAG_MOD
R13
NVCC_GPIO
SJC
ALT0
SJC_MOD
Input
100 k
pull-up
JTAG_TCK
R17
NVCC_GPIO
SJC
ALT0
SJC_TCK
Input
47 k
pull-up
JTAG_TDI
P17
NVCC_GPIO
SJC
ALT0
SJC_TDI
Input
47 k
pull-up
JTAG_TDO
R16
NVCC_GPIO
SJC
ALT0
SJC_TDO
Output
Keeper
JTAG_TMS
R14
NVCC_GPIO
SJC
ALT0
SJC_TMS
Input
47 k
pull-up
JTAG_TRST_B
P13
NVCC_GPIO
SJC
ALT0
SJC_TRSTB
Input
47 k
pull-up
LCD_CLK
C11
NVCC_LCD
GPIO
ALT5
GPIO3_IO0
Input
Keeper
LCD_DATA00
D11
NVCC_LCD
GPIO
ALT5
GPIO3_IO5
Input
Keeper
LCD_DATA01
B12
NVCC_LCD
GPIO
ALT5
GPIO3_IO6
Input
Keeper
LCD_DATA02
D10
NVCC_LCD
GPIO
ALT5
GPIO3_IO7
Input
Keeper
LCD_DATA03
B11
NVCC_LCD
GPIO
ALT5
GPIO3_IO8
Input
Keeper
LCD_DATA04
A11
NVCC_LCD
GPIO
ALT5
GPIO3_IO9
Input
Keeper
LCD_DATA05
D12
NVCC_LCD
GPIO
ALT5
GPIO3_IO10
Input
Keeper
LCD_DATA06
D13
NVCC_LCD
GPIO
ALT5
GPIO3_IO11
Input
Keeper
LCD_DATA07
C12
NVCC_LCD
GPIO
ALT5
GPIO3_IO12
Input
Keeper
LCD_DATA08
B13
NVCC_LCD
GPIO
ALT5
GPIO3_IO13
Input
Keeper
LCD_DATA09
A13
NVCC_LCD
GPIO
ALT5
GPIO3_IO14
Input
Keeper
LCD_DATA10
D14
NVCC_LCD
GPIO
ALT5
GPIO3_IO15
Input
Keeper
LCD_DATA11
C13
NVCC_LCD
GPIO
ALT5
GPIO3_IO16
Input
Keeper
LCD_DATA12
C14
NVCC_LCD
GPIO
ALT5
GPIO3_IO17
Input
Keeper
LCD_DATA13
A14
NVCC_LCD
GPIO
ALT5
GPIO3_IO18
Input
Keeper
LCD_DATA14
B14
NVCC_LCD
GPIO
ALT5
GPIO3_IO19
Input
Keeper
LCD_DATA15
A16
NVCC_LCD
GPIO
ALT5
GPIO3_IO20
Input
Keeper
LCD_DATA16
A15
NVCC_LCD
GPIO
ALT5
GPIO3_IO21
Input
Keeper
LCD_DATA17
D15
NVCC_LCD
GPIO
ALT5
GPIO3_IO22
Input
Keeper
LCD_DATA18
B15
NVCC_LCD
GPIO
ALT5
GPIO3_IO23
Input
Keeper
LCD_DATA19
E12
NVCC_LCD
GPIO
ALT5
GPIO3_IO24
Input
Keeper
LCD_DATA20
B17
NVCC_LCD
GPIO
ALT5
GPIO3_IO25
Input
Keeper
LCD_DATA21
C16
NVCC_LCD
GPIO
ALT5
GPIO3_IO26
Input
Keeper
LCD_DATA22
B16
NVCC_LCD
GPIO
ALT5
GPIO3_IO27
Input
Keeper
LCD_DATA23
C17
NVCC_LCD
GPIO
ALT5
GPIO3_IO28
Input
Keeper
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
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Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
LCD_ENABLE
A10
NVCC_LCD
GPIO
ALT5
GPIO3_IO1
Input
Keeper
LCD_HSYNC
B10
NVCC_LCD
GPIO
ALT5
GPIO3_IO2
Input
Keeper
LCD_RESET
E10
NVCC_LCD
GPIO
ALT5
GPIO3_IO4
Input
Keeper
LCD_VSYNC
C10
NVCC_LCD
GPIO
ALT5
GPIO3_IO3
Input
Keeper
NAND_ALE
D8
NVCC_NAND
GPIO
ALT5
GPIO4_IO10
Input
Keeper
NAND_CE0_B
E8
NVCC_NAND
GPIO
ALT5
GPIO4_IO13
Input
Keeper
NAND_CE1_B
B6
NVCC_NAND
GPIO
ALT5
GPIO4_IO14
Input
Keeper
NAND_CLE
B7
NVCC_NAND
GPIO
ALT5
GPIO4_IO15
Input
Keeper
NAND_DATA00
D7
NVCC_NAND
GPIO
ALT5
GPIO4_IO2
Input
Keeper
NAND_DATA01
A9
NVCC_NAND
GPIO
ALT5
GPIO4_IO3
Input
Keeper
NAND_DATA02
C9
NVCC_NAND
GPIO
ALT5
GPIO4_IO4
Input
Keeper
NAND_DATA03
C7
NVCC_NAND
GPIO
ALT5
GPIO4_IO5
Input
Keeper
NAND_DATA04
C8
NVCC_NAND
GPIO
ALT5
GPIO4_IO6
Input
Keeper
NAND_DATA05
A6
NVCC_NAND
GPIO
ALT5
GPIO4_IO7
Input
Keeper
NAND_DATA06
B9
NVCC_NAND
GPIO
ALT5
GPIO4_IO8
Input
Keeper
NAND_DATA07
B8
NVCC_NAND
GPIO
ALT5
GPIO4_IO9
Input
Keeper
NAND_DQS
E6
NVCC_NAND
GPIO
ALT5
GPIO4_IO16
Input
Keeper
NAND_RE_B
D9
NVCC_NAND
GPIO
ALT5
GPIO4_IO0
Input
Keeper
NAND_READY_B
E9
NVCC_NAND
GPIO
ALT5
GPIO4_IO12
Input
Keeper
NAND_WE_B
A8
NVCC_NAND
GPIO
ALT5
GPIO4_IO1
Input
Keeper
NAND_WP_B
D6
NVCC_NAND
GPIO
ALT5
GPIO4_IO11
Input
Keeper
ONOFF
R6
VDD_SNVS_IN
SRC
ALT0
SRC_RESET_B
Input
100 k
pull-up
POR_B
R10
VDD_SNVS_IN
SRC
ALT0
SRC_POR_B
Input
100 k
pull-up
RTC_XTALI
T12
VDD_SNVS_CA
P
ANAL
OG
—
RTC_XTALI
—
—
RTC_XTALO
U12
VDD_SNVS_CA
P
ANAL
OG
—
RTC_XTALO
—
—
SD1_CLK
C5
NVCC_SD
GPIO
ALT5
GPIO2_IO17
Input
Keeper
SD1_CMD
C6
NVCC_SD
GPIO
ALT5
GPIO2_IO16
Input
Keeper
SD1_DATA0
A5
NVCC_SD
GPIO
ALT5
GPIO2_IO18
Input
Keeper
SD1_DATA1
A4
NVCC_SD
GPIO
ALT5
GPIO2_IO19
Input
Keeper
SD1_DATA2
B5
NVCC_SD
GPIO
ALT5
GPIO2_IO20
Input
Keeper
SD1_DATA3
B4
NVCC_SD
GPIO
ALT5
GPIO2_IO21
Input
Keeper
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NXP Semiconductors
Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
SNVS_PMIC_ON_REQ
T7
VDD_SNVS_IN
GPIO
ALT0
SNVS_PMIC_ON_REQ
Output
100 k
pull-up
SNVS_TAMPER0
R8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO00/SNVS_TAMPE
R01
Input
Keeper1,
SNVS_TAMPER1
P6
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO01/SNVS_TAMPE
R11
Input
Keeper/F
loating1,2
SNVS_TAMPER2
N10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO02/SNVS_TAMPE
R21
Input
Keeper/F
loating1,2
SNVS_TAMPER3
P10
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO03/SNVS_TAMPE
R31
Input
Keeper/F
loating1,2
SNVS_TAMPER4
P7
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO04/SNVS_TAMPE
R41
Input
Keeper/F
loating1,2
SNVS_TAMPER5
P8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO05/SNVS_TAMPE
R51
Input
Keeper/F
loating1,2
SNVS_TAMPER6
R7
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO06/SNVS_TAMPE
R61
Input
Keeper/F
loating1,2
SNVS_TAMPER7
N9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO07/SNVS_TAMPE
R71
Input
Keeper/F
loating1,2
SNVS_TAMPER8
N8
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO08/SNVS_TAMPE
R81
Input
Keeper/F
loating1,2
SNVS_TAMPER9
P9
VDD_SNVS_IN
GPIO
ALT5
GPIO5_IO09/SNVS_TAMPE
R91
Input
Keeper/F
loating1,2
TEST_MODE
N7
VDD_SNVS_IN
TCU
ALT0
TCU_TEST_MODE
Input
Keeper
UART1_CTS_B
L14
NVCC_UART
GPIO
ALT5
GPIO1_IO18
Input
Keeper
UART1_RTS_B
K14
NVCC_UART
GPIO
ALT5
GPIO1_IO19
Input
Keeper
UART1_RX_DATA
L17
NVCC_UART
GPIO
ALT5
GPIO1_IO17
Input
Keeper
UART1_TX_DATA
L15
NVCC_UART
GPIO
ALT5
GPIO1_IO16
Input
Keeper
UART2_CTS_B
J17
NVCC_UART
GPIO
ALT5
GPIO1_IO22
Input
Keeper
UART2_RTS_B
J14
NVCC_UART
GPIO
ALT5
GPIO1_IO23
Input
Keeper
UART2_RX_DATA
K16
NVCC_UART
GPIO
ALT5
GPIO1_IO21
Input
Keeper
UART2_TX_DATA
L16
NVCC_UART
GPIO
ALT5
GPIO1_IO20
Input
Keeper
UART3_CTS_B
H16
NVCC_UART
GPIO
ALT5
GPIO1_IO26
Input
Keeper
UART3_RTS_B
H15
NVCC_UART
GPIO
ALT5
GPIO1_IO27
Input
Keeper
UART3_RX_DATA
K15
NVCC_UART
GPIO
ALT5
GPIO1_IO25
Input
Keeper
UART3_TX_DATA
K17
NVCC_UART
GPIO
ALT5
GPIO1_IO24
Input
Keeper
UART4_RX_DATA
H17
NVCC_UART
GPIO
ALT5
GPIO1_IO29
Input
Keeper
UART4_TX_DATA
J16
NVCC_UART
GPIO
ALT5
GPIO1_IO28
Input
Keeper
UART5_RX_DATA
J13
NVCC_UART
GPIO
ALT5
GPIO1_IO31
Input
Keeper
2
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
NXP Semiconductors
135
Package Information and Contact Assignments
Table 98. 9x9 mm Functional Contact Assignments (continued)
UART5_TX_DATA
K13
NVCC_UART
GPIO
ALT5
GPIO1_IO30
Input
Keeper
USB_OTG1_CHD_B
T15
OPEN DRAIN
GPIO
—
USB_OTG1_CHD_B
—
—
USB_OTG1_DN
R11
VDD_USB_CAP
ANAL
OG
—
USB_OTG1_DN
—
—
USB_OTG1_DP
P11
VDD_USB_CAP
ANAL
OG
—
USB_OTG1_DP
—
—
USB_OTG1_VBUS
T9
USB_VBUS
VBUS
POWE
R
—
USB_OTG1_VBUS
—
—
USB_OTG2_DN
T10
VDD_USB_CAP
ANAL
OG
—
USB_OTG2_DN
—
—
USB_OTG2_DP
U10
VDD_USB_CAP
ANAL
OG
—
USB_OTG2_DP
—
—
USB_OTG2_VBUS
U9
USB_VBUS
VBUS
POWE
R
—
USB_OTG2_VBUS
—
—
XTALI
T14
NVCC_PLL
ANAL
OG
—
XTALI
—
—
XTALO
U14
NVCC_PLL
ANAL
OG
—
XTALO
—
—
1
SNVS_TAMPER0 to SNVS_TAMPER9 can be configured as GPIO or tamper detection pin, it is depending on the fuse setting
TAMPER_PIN_DISABLE[1:0]. When the pad is configured as GPIO, the value is keeper out of reset.
2 SNVS_TAMPER0 to SNVS_TAMPER9 is input floating in the following conditions.
—SNVS low power mode when configured as GPIO
—Tamper functions are not used when configured as TAMPER detection pins
It is required to connect external 1M Ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two
conditions above.
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NXP Semiconductors
NXP Semiconductors
NAND_DATA02 NAND_DATA06 NAND_DATA01 9
LCD_ENABLE 10
11
12
13
14
15
16
17
LCD_DATA04
VSS
LCD_DATA09
LCD_DATA13
LCD_DATA16
LCD_DATA15
VSS
A
LCD_HSYNC
LCD_DATA03
LCD_DATA01
LCD_DATA08
LCD_DATA14
LCD_DATA18
LCD_DATA22
LCD_DATA20
B
LCD_VSYNC
LCD_CLK
LCD_DATA07
LCD_DATA11
LCD_DATA12
VSS
LCD_DATA21
LCD_DATA23
C
NAND_RE_B
LCD_DATA02
LCD_DATA00
LCD_DATA05
LCD_DATA06
LCD_DATA10
LCD_DATA17
ENET2_RX_EN
NAND_READY_B
LCD_RESET
NVCC_NAND
LCD_DATA19
NVCC_LCD
ENET2_TX_EN
VSS
F
G
E
D
ENET2_RX_DATA0 ENET2_RX_DATA1
ENET1_RX_DATA1 ENET1_TX_DATA0
ENET1_TX_EN
ENET2_TX_DATA1 ENET2_TX_DATA0
ENET1_TX_DATA1
VSS
ENET1_RX_DATA0
ENET1_RX_EN
ENET1_TX_CLK
ENET1_RX_ER
NVCC_ENET
VDD_ARM_CAP
VDD_ARM_CAP
VDD_ARM_CAP
8
NAND_DATA04 NAND_DATA07
NAND_ALE
NAND_CE0_B
VDD_SOC_CAP
NAND_WEB
NAND_DATA03
NAND_DATA00
NVCC_SD1
VSS
NAND_CE1_B NAND_DATA05 6
SD1_CMD
NAND_WP_B
NAND_DQS
7
5
SD1_DATA0
SD1_DATA2
SD1_CLK
CSI_PIXCLK
NVCC_CSI
DRAM_SDBA1
NVCC_DRAM
VSS
4
SD1_DATA1
SD1_DATA3
CSI_DATA04
CSI_DATA01
DRAM_ADDR06
DRAM_SDWE_B
DRAM_CAS_B
NAND_CLE
3
CSI_DATA06
CSI_DATA05
CSI_DATA00
CSI_VSYNC
DRAM_ADDR14
VSS
DRAM_SDBA2
VDD_SOC_CAP
2
VSS
CSI_DATA02
CSI_DATA07
CSI_HSYNC
DRAM_ADDR15
DRAM_RESET
DRAM_ADDR01
1
VSS
CSI_MCLK
CSI_DATA03
DRAM_ODT1
VSS
DRAM_ADDR00
A
B
C
D
E
F
6.2.3
G
Package Information and Contact Assignments
9x9 mm, 0.5 mm Pitch, Ball Map
Table 99 shows the 9x9 mm, 0.5 mm pitch ball map for the i.MX 6ULL.
Table 99. 9x9 mm, 0.5 mm Pitch, Ball Map
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
137
138
VSS
GPIO1_IO04
JTAG_TDI
M
GPIO1_IO02
GPIO1_IO03
GPIO1_IO09
N
GPIO_IO01
GPIO1_IO06
GPIO1_IO05
P
UART1_CTS_B
GPIO1_IO00
GPIO1_IO07
GPIO1_IO08
UART1_RTS_B
L
K
J
UART2_CTS_B
H
UART4_RX_DATA
UART3_CTS_B
UART3_RTS_B
VSS
UART2_RX_DATA UART4_TX_DATA
UART1_RX_DATA UART3_TX_DATA
UART2_TX-DATA
ENET2_TX_CLK
ENET2_RX_ER
UART2_RTS_B
UART5_TX_DATA UART5_RX_DATA
UART1_TX_DATA UART3_RX_DATA
NVCC_UART
NVCC_GPIO
ADC_VREFH
JTAG_TRST_B
VSS
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VSS
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VDD_SNVS_CAP
VDD_ARM_CAP
VDD_SOC_IN
VDD_SOC_IN
VDD_SOC_IN
VDD_SNVS_IN
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VDD_USB_CAP
NGND_KEL0
VSS
VDD_SOC_CAP
VDD_SOC_CAP
VDD_SOC_CAP
VSS
VDD_SOC_CAP
USB_OTG1_DP
SNVS_TAMPER3 SNVS_DAMPER2
SNVS_TAMPER9 SNVS_TAMPER7
SNVS_TAMPER5 SNVS_TAMPER8
TEST_MODE
SNVS_TAMPER4
NVCC_DRAM_2P5
DRAM_CSI_B
DRAM_ADDR08
DRAM_ADDR11
NVCC_DRAM
NVCC_DRAM
DRAM_ADDR13
DRAM_ADDR07
DRAM_SDCLK0_N
DRAM_RAS_B
DRAM_SDQS1_N DRAM_ADDR04
DRAM_DATA12
SNVS_TAMPER1
DRAM_SDBA0
VSS
DRAM_SDCLK0_P
DRAM_ADDR12
VSS
DRAM_SDQS1_P
DRAM_DATA10
NVCC_DRAM
DRAM_ADDR05
DRAM_ADDR03
DRAM_ODT0
DRAM_SDCKE0
DRAM_ADDR10
DRAM_DATA13
DRAM_DATA15
DRAM_DATA01
DRAM_ADDR02
DRAM_ADDR09
DRAM_SDCKE1
DRAM_CS0_B
VSS
DRAM_DATA14
DRAM_DATA08
DRAM_SDQS0_P
H
J
K
L
M
N
P
Package Information and Contact Assignments
Table 99. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
NXP Semiconductors
NXP Semiconductors
DRAM_DM1
DRAM_DATA11
VSS
DRAM_DATA06
DRAM_SDQS0_N
ONOFF
DRAM_VREF
DRAM_ZQPAD
DRAM_DATA00
DRAM_DATA02
DRAM_DATA03
DRAM_DATA05
VSS
DRAM_DATA09
DRAM_DATA07
DRAM_DQM0
DRAM_DATA04
VSS
1
2
3
4
5
6
SNVS_TAMPER0
VSS
POR_B
USB_OTG1_DN
VSS
JTAG_MOD
JTAG_TMS
VSS
JTAG_TDO
JTAG_TCK
R
BOOT_MODE0
USB_OTG1_VBUS
USB_OTG2_DN
GPANAIO
RTC_XTALI
NVCC_PLL
XTALI
USB_OTG1_CHD_B
CCM_CLK1_P
VDDA_ADC_3P3
T
BOOT_MODE1
USB_OTG2_VBUS
USB_OTG2_DP
VDD_HIGH_CAP
RTC_XTALO
VSS
XTALO
VDD_HIGH_IN
CCM_CLK1_N
VSS
U
8
9
10
11
12
13
14
15
16
17
7 CCM_PMIC_STBY_REQ SNVS_PMIC_ON_REQ SNVS_TAMPER6
R
T
U
Package Information and Contact Assignments
Table 99. 9x9 mm, 0.5 mm Pitch, Ball Map (continued)
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
139
Revision History
7
Revision History
Table 100 provides a revision history for this data sheet.
Table 100. i.MX 6ULL Data Sheet Document Revision History
Rev.
Number
Date
0
09/2016
Substantive Change(s)
• Initial public release
i.MX 6ULL Applications Processors for Industrial Products, Rev. 0, 09/2016
140
NXP Semiconductors
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© 2016 NXP B.V.
Document Number: IMX6ULLIEC
Rev. 0
09/2016
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