ARM®Cortex - STMicroelectronics

ARM®Cortex - STMicroelectronics
STM32F378xx
ARM®Cortex®-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM,
timers, 4 ADCs(16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 1.8 V
Datasheet - production data
Features
)%*$
• Core: ARM® 32-bit Cortex®-M4 CPU (72 MHz
max), single-cycle multiplication and HW
division, DSP instruction with FPU (floatingpoint unit) and MPU (memory protection unit)
• 1.25 DMIPS/MHz (Dhrystone 2.1)
• Memories
– 256 Kbytes of Flash memory
– 32 Kbytes of SRAM with HW parity check
• CRC calculation unit
• Reset and power management
– Supply: VDD= 1.8 V ± 8%,
VDDA= 1.65 - 3.6 V
– External POR pin
– Low power modes: Sleep and Stop
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x16 PLL option
– Internal 40 kHz oscillator
• Up to 84 fast I/Os
– All mappable on external interrupt vectors
– Up to 45 I/Os with 5 V tolerant capability
• 12-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply from 2.4 up to 3.6
• Up to three 16-bit Sigma Delta ADC
– Separate analog supply from 2.2 to 3.6 V,
up to 21 single/ 11 diff channels
• Up to three 12-bit DAC channels
– Separate analog supply from 2.2 to 3.6 V
• Two fast rail-to-rail analog comparators with
programmable input and output with analog
supply from 1.65 to 3.6 V
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
WLCSP66
(0.400 mm)
UFBGA100
(7 x 7 mm)
• 17 timers
– Two 32-bit timers and three 16-bit timers
with up to 4 IC/OC/PWM or pulse counters
– Two 16-bit timers with up to 2 IC/OC/PWM
or pulse counters
– Four 16-bit timers with up to 1 IC/OC/PWM
or pulse counter
– Independent and system watchdog timers
– SysTick timer: 24-bit down counter
– Three 16-bit basic timers to drive the DAC
• Calendar RTC with Alarm and periodic wakeup
from Stop
• Communication interfaces
– CAN interface (2.0B Active)
– Two I2Cs supporting Fast Mode Plus
(1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, wakeup from STOP
– Three USARTs supporting synchronous
mode, modem control, ISO/IEC 7816, LIN,
IrDA, auto baud rate, wakeup feature
– Three SPIs (18 Mbit/s) with 4 to 16
programmable bit frames, muxed I2S
– HDMI-CEC bus interface
• Serial wire devices, JTAG, Cortex®-M4 ETM
• 96-bit unique ID
Table 1. Device summary
Reference
STM32F378xx
Part numbers
STM32F378CC, STM32F378RC,
STM32F378VC
• Up to 24 capacitive sensing channels
June 2016
This is information on a product in full production.
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Contents
STM32F378xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
ARM® Cortex®-M4 core with embedded Flash and SRAM . . . . . . . . . . . 13
3.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 14
3.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12
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3.7.1
3.11.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.11.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
12-bit analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.13
16-bit sigma delta analog-to-digital converters (SDADC) . . . . . . . . . . . . . 18
3.14
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.15
Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.16
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17.1
General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19) . . . . . 22
3.17.2
Basic timers (TIM6, TIM7, TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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3.17.3
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.4
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.5
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.19
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.20
Universal synchronous/asynchronous receiver transmitter (USART) . . . 25
3.21
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 26
3.22
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.23
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.24
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.25
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 58
6.3.3
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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STM32F378xx
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.14
NRST and NPOR pins characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.15
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.16
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.17
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.18
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.19
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.20
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.21
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.22
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.23
SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.1
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.2
WLCSP66 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.3
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
7.4
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7.5
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.6.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 126
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Capacitive sensing GPIOs available on STM32F378xx devices . . . . . . . . . . . . . . . . . . . . 19
No. of capacitive sensing channels available on STM32F378xx devices. . . . . . . . . . . . . . 20
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F378xx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F378xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F378xx SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F378xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Alternate functions for port PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Alternate functions for port PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Alternate functions for port PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Alternate functions for port PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Alternate functions for port PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate functions for port PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F378xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical and maximum current consumption from VDD supply at VDD = 1.8V . . . . . . . . . . 60
Typical and maximum current consumption from VDDA supply . . . . . . . . . . . . . . . . . . . . . 62
Typical and maximum VDD consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical and maximum VDDA consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 63
Typical current consumption in Run mode, code with data processing running from Flash 64
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 66
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
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I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
RSRC max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SDADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
VREFSD+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 112
WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
DocID025608 Rev 4
STM32F378xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM32F378xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F378xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32F378xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM32F378xx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F378xx WLCSP66 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F378xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0]='00') . . . . . . . . . . . . 63
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . 102
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch,
ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch,
ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . 112
UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
WLCSP66 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 116
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 119
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 122
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8
List of figures
Figure 44.
Figure 45.
Figure 46.
8/131
STM32F378xx
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
DocID025608 Rev 4
STM32F378xx
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F378xx microcontrollers.
This STM32F378xx datasheet should be read in conjunction with the RM0313 reference
manual. The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Cortex®-M4 with FPU core, please refer to:
•
Cortex®-M4 with FPU Technical Reference Manual, available from www.arm.com.
•
STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214) available
from www.st.com.
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47
Description
2
STM32F378xx
Description
The STM32F378xx family is based on the high-performance ARM® Cortex®-M4 32-bit RISC
core operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a
memory protection unit (MPU) and an Embedded Trace Macrocell™ (ETM). The family
incorporates high-speed embedded memories (up to 256 Kbyte of Flash memory, up to
32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected
to two APB buses.
The STM32F378xx devices offer one fast 12-bit ADC (1 Msps), up to three 16-bit Sigma
delta ADCs, up to two comparators, up to two DACs (DAC1 with 2 channels and DAC2 with
1 channel), a low-power RTC, 9 general-purpose 16-bit timers, two general-purpose 32-bit
timers, three basic timers.
They also feature standard and advanced communication interfaces: up to two I2Cs, three
SPIs, all with muxed I2Ss, three USARTs and CAN.
The STM32F378xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges from a 1.8 V ± 8% power supply. A comprehensive set of power-saving mode allows
the design of low-power applications.
The STM32F378xx family offers devices in five packages ranging from 48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
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DocID025608 Rev 4
STM32F378xx
Description
Table 2. Device overview
Peripheral
STM32F
378Cx
STM32F
378Rx
Flash (Kbytes)
256
SRAM (Kbytes)
32
Timers
General
purpose
9 (16-bit)
2 (32 bit)
Basic
3 (16-bit)
SPI/I2S
Comm.
interfaces
3
2
I C
2
USART
3
CAN
1
Capacitive sensing
channels
14
17
12-bit ADCs
1
16-bit ADCs Sigma- Delta
3
12-bit DACs outputs
3
Analog comparator
2
Max. CPU frequency
24
72 MHz
Main operating voltage
1.8 V +/- 8%
16-bit SDADC operating voltage
2.2 to 3.6 V
Ambient operating temperature:
−40 to 85 °C / −40 to 105 °C
Junction temperature:
−40 to 105 °C / −40 to 125 °C
Operating temperature
Packages
STM32F
378Vx
LQFP48
DocID025608 Rev 4
LQFP64,
WLCSP66
LQFP100,
UFBGA100
11/131
47
Description
STM32F378xx
Figure 1. Block diagram
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DocID025608 Rev 4
069
STM32F378xx
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 core with embedded Flash and SRAM
The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded
systems. It was developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F378xx family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32F378xx family.
3.2
Memory protection unit
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
The Cortex-M4 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
•
Outstanding processing performance combined with fast interrupt handling
•
Enhanced system debug with extensive breakpoint and trace capabilities
•
Efficient processor core, system and memories
•
Ultralow power consumption with integrated sleep modes
•
Platform security robustness with optional integrated memory protection unit (MPU).
With its embedded ARM core, the STM32F378xx devices are compatible with all ARM
development tools and software.
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47
Functional overview
3.3
STM32F378xx
Embedded Flash memory
All STM32F378xx devices feature up to 256 Kbytes of embedded Flash memory available
for storing programs and data. The Flash memory access time is adjusted to the CPU clock
frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states
above).
3.4
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.5
Embedded SRAM
All STM32F378xx devices feature up to 32 Kbytes of embedded SRAM with hardware parity
check. The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6
Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PD5/PD6) or I2C (PB6/PB7).
3.7
Power management
3.7.1
Power supply schemes
14/131
•
VDD: external power supply for I/Os and core. It is provided externally through VDD pins,
and can be 1.8 V +/- 8%.
•
VDDA = 1.65 to 3.6 V:
–
external analog power supplies for Reset blocks, RCs and PLL
–
supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be
applied to VDDA is 2.4 V when the 12-bit ADC and DAC are used).
•
VDDSD12 and VDDSD3 = 2.2 to 3.6 V: supply voltages for SDADC1/2 and SDADCD3
sigma delta ADCs. Independent from VDD/VDDA.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers when VDD is not present.
DocID025608 Rev 4
STM32F378xx
3.7.2
Functional overview
Power supply supervisor
Device power on reset is controlled through the external NPOR pin. The device remains in
reset mode when NPOR is held low. NPOR pin has an internal pull-up resistor so the
external driver can be open drain type.
To guarantee a proper power-on reset, the NPOR pin must be held low until VDD is stable.
When VDD is stable, the reset state can be exited by:
3.7.3
•
either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.
•
or forcing the pin to high level by connecting it to VDDA.
Low-power modes
The STM32F378xx supports two low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USARTs, the I2Cs, the
CEC the COMPx and the RTC alarm.
3.8
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
3.9
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
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47
Functional overview
STM32F378xx
Do not reconfigure GPIO pins which are not present on 48 and 64 pin packages to the
analog mode. Additional current consumption in the range of tens of µA per pin can be
observed if VDDA is higher than VDDIO.
3.10
Direct memory access (DMA)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The two DMAs can be used with the main peripherals: SPIs, I2Cs, USARTs, DACs, ADC,
SDADCs, general-purpose timers.
3.11
Interrupts and events
3.11.1
Nested vectored interrupt controller (NVIC)
The STM32F378xx devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 60 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.11.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 29 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 84
GPIOs can be connected to the 16 external interrupt lines.
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3.12
Functional overview
12-bit analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter is based on a successive approximation register
(SAR) architecture. It has up to 16 external channels (AIN15:0) and 3 internal channels
(temperature sensor, voltage reference, VBAT voltage measurement) performing
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the timers (TIMx) can be internally connected to the ADC start and
injection trigger, respectively, to allow the application to synchronize A/D conversion and
timers.
3.12.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode. See Table 64:
Temperature sensor calibration values on page 103.
3.12.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
3.12.3
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a divider by 2.
As a consequence, the converted digital value is half the VBAT voltage.
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Functional overview
3.13
STM32F378xx
16-bit sigma delta analog-to-digital converters (SDADC)
Up to three 16-bit sigma-delta analog-to-digital converters are embedded in the
STM32F378xx. They have up to two separate supply voltages allowing the analog function
voltage range to be independent from the STM32F378xx power supply. They share up to 21
input pins which may be configured in any combination of single-ended (up to 21) or
differential inputs (up to 11).
The conversion speed is up to 16.6 ksps for each SDADC when converting multiple
channels and up to 50 ksps per SDADC if single channel conversion is used. There are two
conversion modes: single conversion mode or continuous mode, capable of automatically
scanning any number of channels. The data can be automatically stored in a system RAM
buffer, reducing the software overhead.
A timer triggering system can be used in order to control the start of conversion of the three
SDADCs and/or the 12-bit fast ADC. This timing control is very flexible, capable of triggering
simultaneous conversions or inserting a programmable delay between the ADCs.
Up to two external reference pins (VREFSD+, VREFSD-) and an internal 1.2/1.8 V
reference can be used in conjunction with a programmable gain (x0.5 to x32) in order to
fine-tune the input voltage range of the SDADC. VREFSD - pin is used as negative signal
reference in case of single-ended input mode.
3.14
Digital-to-analog converter (DAC)
The devices feature up to two 12-bit buffered DACs with three output channels that can be
used to convert three digital signals into three analog voltage signal outputs. The internal
structure is composed of integrated resistor strings and an amplifier in inverting
configuration.
This digital Interface supports the following features:
•
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Up to two DAC converters with three output channels:
–
DAC1 with two output channels
–
DAC2 with one output channel.
•
8-bit or 10-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation (DAC1 only)
•
Triangular wave generation (DAC1 only)
•
Dual DAC channel independent or simultaneous conversions (DAC1 only)
•
DMA capability for each channel
•
External triggers for conversion
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STM32F378xx
3.15
Functional overview
Fast comparators (COMP)
The STM32F378xx embeds up to 2 comparators with rail-to-rail inputs and high-speed
output. The reference voltage can be internal or external (delivered by an I/O).
The threshold can be one of the following:
•
DACs channel outputs
•
External I/O
•
Internal reference voltage (VREFINT) or submultiple (1/4 VREFINT, 1/2 VREFINT and 3/4
VREFINT)
The comparators can be combined into a window comparator.
Both comparators can wake up the device from Stop mode and generate interrupts and
breaks for the timers.
3.16
Touch sensing controller (TSC)
The devices provide a simple solution for adding capacitive sensing functionality to any
application. Capacitive sensing technology is able to detect the presence of a finger near an
electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The
capacitive variation introduced by the finger (or any conductive object) is measured using a
proven implementation based on a surface charge transfer acquisition principle. It consists
of charging the electrode capacitance and then transferring a part of the accumulated
charges into a sampling capacitor until the voltage across this capacitor has reached a
specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by
the hardware touch sensing controller and only requires few external components to
operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Up to 24 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are
organized in 8 acquisition groups, with up to 4 I/Os in each group.
Table 3. Capacitive sensing GPIOs available on STM32F378xx devices
Group
1
2
Capacitive sensing
signal name
Pin name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
PA3
Group
5
(1)
TSC_G2_IO1
PA4
TSC_G2_IO2
PA5(1)
TSC_G2_IO3
PA6(1)
TSC_G2_IO4
PA7
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6
Capacitive sensing
signal name
Pin
name
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
TSC_G5_IO4
PB7
TSC_G6_IO1
PB14
TSC_G6_IO2
PB15
TSC_G6_IO3
PD8
TSC_G6_IO4
PD9
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Functional overview
STM32F378xx
Table 3. Capacitive sensing GPIOs available on STM32F378xx devices (continued)
Group
3
4
Capacitive sensing
signal name
Pin name
Capacitive sensing
signal name
Pin
name
TSC_G3_IO1
PC4
TSC_G7_IO1
PE2
TSC_G3_IO2
PC5
TSC_G7_IO2
PE3
TSC_G3_IO3
PB0
TSC_G7_IO3
PE4
TSC_G3_IO4
PB1
TSC_G7_IO4
PE5
TSC_G4_IO1
PA9
TSC_G8_IO1
PD12
TSC_G4_IO2
PA10
TSC_G8_IO2
PD13
TSC_G4_IO3
PA13
TSC_G8_IO3
PD14
TSC_G4_IO4
PA14
TSC_G8_IO4
PD15
Group
7
8
1. This GPIO offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling
capacitor I/O.
Table 4. No. of capacitive sensing channels available on STM32F378xx devices
Number of capacitive sensing channels
Analog I/O group
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STM32F378Cx
STM32F378Rx
STM32F378Vx
G1
3
3
3
G2
2
3
3
G3
1
3
3
G4
3
3
3
G5
3
3
3
G6
2
2
3
G7
0
0
3
G8
0
0
3
Number of capacitive
sensing channels
14
17
24
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STM32F378xx
3.17
Functional overview
Timers and watchdogs
The STM32F378xx includes two 32-bit and nine 16-bit general-purpose timers, three basic
timers, two watchdog timers and a SysTick timer. The table below compares the features of
the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/
compare
channels
Complementary
outputs
Generalpurpose
TIM2
TIM5
32-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
0
Generalpurpose
TIM3,
TIM4,
TIM19
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
0
Generalpurpose
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
0
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
Generalpurpose
TIM13,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
0
Generalpurpose
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6,
TIM7,
TIM18
16-bit
Up
Any integer
between 1
and 65536
Yes
0
0
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Functional overview
3.17.1
STM32F378xx
General-purpose timers (TIM2 to TIM5, TIM12 to TIM17, TIM19)
There are eleven synchronizable general-purpose timers embedded in the STM32F378xx
(see Table 5 for differences). Each general-purpose timer can be used to generate PWM
outputs, or act as a simple time base.
•
TIM2, 3, 4, 5 and 19
These five timers are full-featured general-purpose timers:
–
TIM2 and TIM5 have 32-bit auto-reload up/downcounters and 32-bit prescalers
–
TIM3, 4, and 19 have 16-bit auto-reload up/downcounters and 16-bit prescalers
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM12, 13, 14, 15, 16, 17
These six timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM12 has 2 channels
–
TIM13 and TIM14 have 1 channel
–
TIM15 has 2 channels and 1 complementary channel
–
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.17.2
Basic timers (TIM6, TIM7, TIM18)
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
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3.17.3
Functional overview
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stopmode. It can be used either as a watchdog to reset the
device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.17.4
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB1 clock (PCLK1) derived from the main clock. It has an early warning
interrupt capability and the counter can be frozen in debug mode.
3.17.5
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.18
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source
Real-time clock (RTC) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either
from VDD supply when present or through the VBATpin. The backup registers are thirty two
32-bit registers used to store 128 bytes of user application data.
They are not reset by a system or power reset.
The RTC is an independent BCD timer/counter. Its main features are the following:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28th, 29th (leap year), 30th and 31st day of the month.
•
2 programmable alarms with wake up from Stop mode capability.
•
Periodic wakeup unit with programmable resolution and period.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
3 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop mode on tamper event detection.
•
Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop mode on timestamp event detection.
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47
Functional overview
•
STM32F378xx
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The RTC clock sources can be:
3.19
•
A 32.768 kHz external crystal
•
A resonator or oscillator
•
The internal low-power RC oscillator (typical frequency of 40 kHz)
•
The high-speed external clock divided by 32
Inter-integrated circuit interface (I2C)
Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support
standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes with
20 mA output drive. They support 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask). They also include programmable
analog and digital noise filters.
Table 6. Comparison of I2C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeout verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the application to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller
Refer to Table 7 for the differences between I2C1 and I2C2.
Table 7. STM32F378xx I2C implementation
I2C features(1)
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I2C1
I2C2
7-bit addressing mode
X
X
10-bit addressing mode
X
X
Standard mode (up to 100 kbit/s)
X
X
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
X
Independent clock
X
X
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Functional overview
Table 7. STM32F378xx I2C implementation (continued)
I2C features(1)
I2C1
I2C2
SMBus
X
X
Wakeup from STOP
X
X
1. X = supported.
3.20
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F378xx embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
All USARTs interfaces are able to communicate at speeds of up to 9 Mbit/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode, Smartcard mode (ISO/IEC 7816 compliant), autobaudrate feature
and have LIN Master/Slave capability. The USART interfaces can be served by the DMA
controller.
Refer to Table 8 for the features of USART1, USART2 and USART3.
Table 8. STM32F378xx USART implementation
USART modes/features(1)
USART1
USART2
USART3
Hardware flow control for modem
X
X
X
Continuous communication using DMA
X
X
X
Multiprocessor communication
X
X
X
Synchronous mode
X
X
X
Smartcard mode
X
X
X
Single-wire half-duplex communication
X
X
X
IrDA SIR ENDEC block
X
X
X
LIN mode
X
X
X
Dual clock domain and wakeup from Stop mode
X
X
X
Receiver timeout interrupt
X
X
X
Modbus communication
X
X
X
Auto baud rate detection
X
X
X
Driver Enable
X
X
X
1. X = supported.
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Functional overview
3.21
STM32F378xx
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available, that can
be operated in master or slave mode. These interfaces can be configured to operate with
16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up
to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in
master mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency. All I2S interfaces can operate in half-duplex mode only.
Refer to Table 9 for the features between SPI1, SPI2 and SPI3.
Table 9. STM32F378xx SPI/I2S implementation
SPI features(1)
SPI1
SPI2
SPI3
Hardware CRC calculation
X
X
X
Rx/Tx FIFO
X
X
X
NSS pulse mode
X
X
X
I2S mode
X
X
X
TI mode
X
X
X
I2S full-duplex mode
-
-
-
1. X = supported.
3.22
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.23
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
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STM32F378xx
3.24
Functional overview
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.25
Embedded trace macrocell™
The ARM embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F378xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
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47
Pinouts and pin description
4
STM32F378xx
Pinouts and pin description
9''B
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Figure 2. STM32F378xx LQFP48 pinout
,1&0
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28/131
DocID025608 Rev 4
3)
3)
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3'
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STM32F378xx
Pinouts and pin description
9''B
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Figure 3. STM32F378xx LQFP64 pinout
,1&0
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3)26&B,1
3)26&B287
1567
3&
3&
3&
3&
966$95()
9''$
3$
3$
3$
-36
1. The above figure shows the package top view.
DocID025608 Rev 4
29/131
47
Pinouts and pin description
STM32F378xx
6$$?
633?
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 4. STM32F378xx LQFP100 pinout
,1&0
6$$?
633?
0&
0! 0! 0! 0! 0! 0! 0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
62%&3$
6$$3$
0!
0&
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
.0/2
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
62%&3$
6333$
6$$3$
0%
0%
0%
0%
0%
6"!4
0#
0#/3#?).
0#/3#?/54
0&
0&
0&/3#?).
0&/3#?/54
.234
0#
0#
0#
0#
0&
633!62%&
6$$!
62%&
0!
0!
0!
069
1. The above figure shows the package top view.
30/131
DocID025608 Rev 4
STM32F378xx
Pinouts and pin description
Figure 5. STM32F378xx UFBGA100 ballout
!
0%
0%
0"
"//4
0$
0$
0"
0"
0!
0!
0!
0!
"
0%
0%
0"
0"
0"
0$
0$
0$
0$
0#
0#
0!
#
0#
0%
0%
0$
0$
0#
0&
0!
$
0#
0%
633?
0!
0!
0#
0#
6"!4
0#
0#
0#
&
0&
0&
633?
6333$
'
0&
0&
6$$?
6$$3$
(
0#
.234
*
0&
+
%
6$$?
0"
0&
6$$?
0$
0$
0$
0#
0#
0$
0$
0$
633!
62%&
0#
0!
0!
0#
0"
62%&3$
,
62%&
0!
0!
0!
0#
.0/2
-
6$$!
0!
0!
0!
0"
0"
0$
0$
0"
0%
0%
0%
0"
0%
0%
0%
0%
62%&3$ 6$$3$
0%
0%
-36
1. The above figure shows the package top view.
DocID025608 Rev 4
31/131
47
Pinouts and pin description
STM32F378xx
Figure 6. STM32F378xx WLCSP66 ballout
$
3$
3$
3&
3'
3%
3%
3%
9%$7
%
3)
3)
3&
3&
3%
3%
3%
3&
&
3$
3$
3$
3$
3%
966B
%227
3&
3$
3&
3$
9''B
3)
3&
3&
3&
3&
3&
1567
3)
3%
3%
3'
3&
3&
3&
95()6'
1325
3$
966B
966B
95()
9''$
95()
966$
9''6'
3(
3%
3&
3$
3$
3$
3$
9666'
95()6'
3(
3%
3&
3$
3$
9''B
3$
'
(
)
*
+
-
06Y9
1. The above figure shows the package top view.
32/131
DocID025608 Rev 4
STM32F378xx
Pinouts and pin description
Table 10. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Notes
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC or SDADC
POR
External power on reset pin with embedded weak pull-up
resistor, powered from VDDA
TC
Standard 3.3V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
DocID025608 Rev 4
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47
Pinouts and pin description
STM32F378xx
Table 11. STM32F378xx pin definitions
BGA100
LQFP64
LQFP48
WLCSP66
(function after
reset)
1
B2
-
-
-
PE2
Pin
type
I/O
I/O structure
LQFP100
Pin name
Pin functions
Notes
Pin numbers
Alternate function
Additional functions
(1)
FT
TSC_G7_IO1, TRACECLK
-
FT
TSC_G7_IO2, TRACED0
-
2
A1
-
-
-
PE3
I/O
(1)
3
B1
-
-
-
PE4
I/O
(1)
FT
TSC_G7_IO3, TRACED1
-
FT
TSC_G7_IO4, TRACED2
-
TRACED3
WKUP3,
RTC_TAMPER3
4
C2
-
-
-
PE5
I/O
(1)
5
D2
-
-
-
PE6
I/O
(1)
FT
6
E2
1
1
A8
VBAT
S
-
-
Backup power supply
7
C1
2
2
B8
PC13(2)
I/O
-
TC
-
WKUP2,
ALARM_OUT,
CALIB_OUT,
TIMESTAMP,
RTC_TAMPER1
8
D1
3
3
C8
PC14 OSC32_IN(2)
I/O
-
TC
-
OSC32_IN
9
E1
4
4
D8
PC15 OSC32_OUT(2)
I/O
-
TC
-
OSC32_OUT
10
F2
-
-
-
PF9
I/O
(1)
FT
TIM14_CH1
-
FT
-
-
11
G2
-
-
-
PF10
I/O
(1)
12
F1
5
5
D7
PF0 - OSC_IN
I/O
-
FTf
I2C2_SDA
OSC_IN
13
G1
6
6
E8
PF1 OSC_OUT
I/O
-
FTf
I2C2_SCL
OSC_OUT
14
H2
7
7
E7
NRST
I/O
-
RST Device reset input / internal reset output (active low)
15
H1
8
-
E6
PC0
I/O
(1)
TTa
TIM5_CH1_ETR
ADC_IN10
TTa
TIM5_CH2
ADC_IN11
16
J2
9
-
F8
PC1
I/O
(1)
17
J3
10
-
F7
PC2
I/O
(1)
TTa
SPI2_MISO/I2S2_MCK,
TIM5_CH3
ADC_IN12
18
K2
11
-
F6
PC3
I/O
(1)
TTa
SPI2_MOSI/I2S2_SD,
TIM5_CH4
ADC_IN13
19
J1
-
-
-
PF2
I/O
(1)
FT
I2C2_SMBA
-
20
K1
12
8
G8
VSSA/ VREF-
S
-
-
Analog ground
-
-
-
9
-
VDDA/ VREF+
S
(1)
-
Analog power supply / Reference voltage for ADC,
COMP, DAC
-
G7
VDDA
S
(1)
-
Analog power supply
S
(1)
-
Reference voltage for ADC, COMP, DAC
21
M1 13
22
34/131
L1
17
-
G6
VREF+
DocID025608 Rev 4
STM32F378xx
Pinouts and pin description
23
24
25
L2
K3
L3
27
E3
28
H3
30
31
16 12 J8
18 13 H6
-
-
-
19 17 J7
M3 20 14 J6
K4
L4
21 15 H5
22 16 J5
Pin name
(function after
reset)
PA0
PA1
PA2
Pin
type
I/O
I/O
I/O
Notes
WLCSP66
LQFP48
14 10 H8
M2 15 11 H7
26
29
LQFP64
BGA100
LQFP100
Pin numbers
-
-
-
I/O structure
Table 11. STM32F378xx pin definitions (continued)
Pin functions
Alternate function
Additional functions
TTa
USART2_CTS,
TIM2_CH1_ETR,
TIM5_CH1_ETR,
TIM19_CH1, TSC_G1_IO1,
COMP1_OUT
RTC_ TAMPER2,
WKUP1, ADC_IN0,
COMP1_INM
TTa
SPI3_SCK/I2S3_CK,
USART2_RTS, TIM2_CH2,
TIM15_CH1N, TIM5_CH2,
TIM19_CH2, TSC_G1_IO2,
RTC_REF_IN
ADC_IN1,
COMP1_INP
TTa
COMP2_OUT,
TSC_G1_IO3,
SPI3_MISO/I2S3_MCK,
USART2_TX, TIM2_CH3,
TIM15_CH1, TIM5_CH3,
TIM19_CH3
ADC_IN2,
COMP2_INM
ADC_IN3,
COMP2_INP
-
PA3
I/O
-
TTa
SPI3_MOSI, I2S3_SD,
USART2_RX, TIM2_CH4,
TIM15_CH2, TIM5_CH4,
TIM19_CH4, TSC_G1_IO4
PF4
I/O
(1)
FT
-
VDD_2
S
-
-
PA4
PA5
PA6
I/O
I/O
-
-
Digital power supply
TTa
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, TIM3_CH2,
TIM12_CH1, TSC_G2_IO1
ADC_IN4,
DAC1_OUT1
TTa
SPI1_SCK/I2S1_CK, CEC,
TIM2_CH1_ETR,
TIM14_CH1, TIM12_CH2,
TSC_G2_IO2
ADC_IN5,
DAC1_OUT2
TTa
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM13_CH1,
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3
ADC_IN6,
DAC2_OUT1
SPI1_MOSI/I2S1_SD,
TIM14_CH1, TIM17_CH1,
TIM3_CH2, COMP2_OUT,
TSC_G2_IO4
ADC_IN7
I/O
-
TTa
32
M4 23
-
G3
PA7
I/O
(1)
33
K5
24
-
H4
PC4
I/O
(1)
TTa
34
L5
25
-
J4
PC5
I/O
(1)
TTa USART1_RX, TSC_G3_IO2
USART1_TX, TIM13_CH1,
DocID025608 Rev 4
TSC_G3_IO1
ADC_IN14
ADC_IN15
35/131
47
Pinouts and pin description
STM32F378xx
Table 11. STM32F378xx pin definitions (continued)
Notes
I/O structure
PB0
I/O
-
TTa
SPI1_MOSI/I2S1_SD,
TIM3_CH3, TSC_G3_IO3
ADC_IN8,
SDADC1_AIN6P
36
M6 27 19 J3
PB1
I/O
-
TTa
TIM3_CH4, TSC_G3_IO4
ADC_IN9,
SDADC1_AIN5P,
SDADC1_AIN6M
37
L6
NPOR
I
(3)
POR
PE7
I/O
(1)(4)
TC
-
SDADC1_AIN3P,
SDADC1_AIN4M,
SDADC2_AIN5P,
SDADC2_AIN6M
PE8
I/O
(4)
TC
-
SDADC1_AIN8P,
SDADC2_AIN8P
(4)
TC
-
SDADC1_AIN7P,
SDADC1_AIN8M,
SDADC2_AIN7P,
SDADC2_AIN8M
(1)
TC
-
SDADC1_AIN2P
38
M7
39
L7
WLCSP66
M5 26 18 H3
LQFP48
35
LQFP64
BGA100
Pin functions
LQFP100
Pin numbers
28 20 G2
-
-
-
29 21 H2
Pin name
(function after
reset)
Pin
type
Alternate function
Additional functions
Power-on reset
40
M8 30 22 J2
PE9
I/O
41
L8
-
-
-
PE10
I/O
42
M9
-
-
-
PE11
I/O
(1)(4)
TC
-
SDADC1_AIN1P,
SDADC1_AIN2M,
SDADC2_AIN4P
43
L9
-
-
-
PE12
I/O
(1)(4)
TC
-
SDADC1_AIN0P,
SDADC2_AIN3P,
SDADC2_AIN4M
44 M10
-
-
-
PE13
I/O
(1)(4)
TC
-
SDADC1_AIN0M,
SDADC2_AIN2P
45 M11
-
-
-
PE14
I/O
(1)(4)
TC
-
SDADC2_AIN1P,
SDADC2_AIN2M
46 M12
-
-
-
PE15
I/O
(1)(4)
TC
USART3_RX
SDADC2_AIN0P
47
L10
-
-
-
PB10
I/O
(1)(4)
TC
SPI2_SCK/I2S2_CK, CEC,
USART3_TX, TSC_SYNC
TIM2_CH3,
SDADC2_AIN0M
48
L11
-
-
-
VREFSD-
S
(1)
-
External reference voltage for SDADC1, SDADC2,
SDADC3 (negative input), negative SDADC analog
input in SDADC single ended mode
49
F12
-
-
-
VSSSD
S
(1)
-
SDADC1, SDADC2, SDADC3 ground
-
SDADC1, SDADC2, SDADC3 ground / External
reference voltage for SDADC1, SDADC2, SDADC3
(negative input), negative SDADC analog input in
SDADC single ended mode
-
36/131
-
31 23 J1
VSSSD/
VREFSD-
S
(4)
-
DocID025608 Rev 4
STM32F378xx
Pinouts and pin description
Table 11. STM32F378xx pin definitions (continued)
(1)
-
SDADC1 and SDADC2 power supply
VDDSD
S
-
-
SDADC1, SDADC2, SDADC3 power supply
VDDSD3
S
(1)
-
SDADC3 power supply
VREFSD+
S
-
-
External reference voltage for SDADC1, SDADC2,
SDADC3 (positive input)
WLCSP66
(function after
reset)
-
-
-
VDDSD12
32 24 H1
51
L12
52
K12 33 25 G1
53
I/O structure
-
Notes
-
S
LQFP48
50 G12
-
-
-
K11 34 26 F2
Pin functions
Pin
type
Pin name
LQFP64
BGA100
LQFP100
Pin numbers
PB14
Alternate function
Additional functions
TC
SPI2_MISO/I2S2_MCK,
USART3_RTS,
TIM15_CH1, TIM12_CH1,
TSC_G6_IO1
SDADC3_AIN8P
SDADC3_AIN7P,
SDADC3_AIN8M
I/O
(5)
TC
SPI2_MOSI/I2S2_SD,
TIM15_CH1N, TIM15_CH2,
TIM12_CH2, TSC_G6_IO2,
RTC_REFIN
TC
SPI2_SCK/I2S2_CK,
USART3_TX, TSC_G6_IO3
SDADC3_AIN6P
(1)
TC
USART3_RX, TSC_G6_IO4
SDADC3_AIN5P,
SDADC3_AIN6M
54
K10 35 27 F1
PB15
I/O
(5)
55
K9
PD8
I/O
(5)
56
K8
-
-
-
PD9
I/O
57
J12
-
-
-
PD10
I/O
(1)(5)
TC
USART3_CK
SDADC3_AIN4P
58
J11
-
-
-
PD11
I/O
(1)(5)
TC
USART3_CTS
SDADC3_AIN3P,
SDADC3_AIN4M
59
J10
-
-
-
PD12
I/O
(1)(5)
TC
USART3_RTS, TIM4_CH1,
TSC_G8_IO1
SDADC3_AIN2P
60
H12
-
-
-
PD13
I/O
(1)(5)
TC
TIM4_CH2, TSC_G8_IO2
SDADC3_AIN1P,
SDADC3_AIN2M
61
H11
-
-
-
PD14
I/O
(1)(5)
TC
TIM4_CH3, TSC_G8_IO3
SDADC3_AIN0P
TC
TIM4_CH4, TSC_G8_IO4
SDADC3_AIN0M
36 28 F3
(5)
-
-
PD15
I/O
(1)(5)
E12 37
-
E2
PC6
I/O
(1)
FT
SPI1_NSS/I2S1_WS,
TIM3_CH1
-
64
E11 38
-
E1
PC7
I/O
(1)
FT
SPI1_SCK/I2S1_CK,
TIM3_CH2
-
65
E10 39
-
E3
PC8
I/O
(1)
FT
SPI1_MISO/I2S1_MCK,
TIM3_CH3
-
66
D12 40
-
D2
PC9
I/O
(1)
FT
SPI1_MOSI/I2S1_SD,
TIM3_CH4
-
62
H10
63
-
DocID025608 Rev 4
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47
Pinouts and pin description
STM32F378xx
67
68
69
70
71
D11 41 29 D1
D10 42 30 D3
C12 43 31 C2
B12 44 32 C1
A12 45 33 C3
Pin name
(function after
reset)
PA8
PA9
PA10
PA11
PA12
Pin
type
I/O
I/O
I/O
I/O
I/O
Notes
WLCSP66
LQFP48
LQFP64
BGA100
LQFP100
Pin numbers
-
-
-
-
-
I/O structure
Table 11. STM32F378xx pin definitions (continued)
Pin functions
Alternate function
Additional functions
FT
SPI2_SCK/I2S2_CK,
I2C2_SMBA, USART1_CK,
TIM4_ETR,
TIM5_CH1_ETR,
CLK_CLKOUT
-
FTf
SPI2_MISO/I2S2_MCK,
I2C2_SCL, USART1_TX,
TIM2_CH3, TIM15_BKIN,
TIM13_CH1, TSC_G4_IO1
-
FTf
SPI2_MOSI/I2S2_SD,
I2C2_SDA, USART1_RX,
TIM2_CH4, TIM17_BKIN,
TIM14_CH1, TSC_G4_IO2
-
FT
SPI2_NSS/I2S2_WS,
SPI1_NSS/I2S1_WS,
USART1_CTS, CAN_RX,
TIM4_CH1, TIM5_CH2,
COMP1_OUT
-
FT
SPI1_SCK/I2S1_CK,
USART1_RTS, CAN_TX,
TIM16_CH1, TIM4_CH2,
TIM5_CH3, COMP2_OUT
-
-
-
72
A11 46 34 C4
PA13
I/O
-
FT
SPI1_MISO/I2S1_MCK,
USART3_CTS, IR_OUT,
TIM16_CH1N, TIM4_CH3,
TIM5_CH4, G4_IO3,
SWDIO-JTMS
73
C11 47 35 B2
PF6
I/O
-
FTf
SPI1_MOSI, I2S1_SD,
USART3_RTS, TIM4_CH4,
I2C2_SCL
74
F11
VSS_3
S
(1)
-
Ground
VDD_3
S
(1)
-
Digital power supply
48 36 B1
PF7
I/O
-
FTf
I2C2_SDA, USART2_CK
-
A10 49 37 A1
PA14
I/O
-
FTf
I2C1_SDA, TIM12_CH1,
TSC_G4_IO4, SWCLKJTCK
-
FTf
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
I2C1_SCL,
TIM2_CH1_ETR,
TIM12_CH2, TSC_SYNC,
JTDI
-
75
G11
-
-
76
77
A9
38/131
-
-
-
50 38 A2
PA15
I/O
-
DocID025608 Rev 4
STM32F378xx
Pinouts and pin description
Table 11. STM32F378xx pin definitions (continued)
LQFP48
WLCSP66
(function after
reset)
Notes
I/O structure
78
B11 51
-
B3
PC10
I/O
(1)
FT
SPI3_SCK/I2S3_CK,
USART3_TX, TIM19_CH1
-
79
C10 52
-
A3
PC11
I/O
(1)
FT
SPI3_MISO/I2S3_MCK,
USART3_RX, TIM19_CH2
-
80
B10 53
-
B4
PC12
I/O
(1)
FT
SPI3_MOSI/I2S3_SD,
USART3_CK, TIM19_CH3
-
81
C9
-
-
PD0
I/O
(1)
FT
CAN_RX, TIM19_CH4
-
I/O
(1)
FT
CAN_TX, TIM19_ETR
-
FT
TIM3_ETR
-
82
B9
LQFP64
BGA100
Pin functions
LQFP100
Pin numbers
-
-
-
Pin name
PD1
Pin
type
Alternate function
Additional functions
83
C8
54
-
A4
PD2
I/O
(1)
84
B8
-
-
-
PD3
I/O
(1)
FT
SPI2_MISO/I2S2_MCK,
USART2_CTS
-
85
B7
-
-
-
PD4
I/O
(1)
FT
SPI2_MOSI/I2S2_SD,
USART2_RTS
-
86
A6
-
-
-
PD5
I/O
(1)
FT
USART2_TX
-
87
B6
-
-
-
PD6
I/O
(1)
FT
SPI2_NSS/I2S2_WS,
USART2_RX
-
88
A5
-
-
-
PD7
I/O
(1)
FT
SPI2_SCK/I2S2_CK,
USART2_CK
-
FT
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART2_TX, TIM2_CH2,
TIM3_ETR, TIM4_ETR,
TIM13_CH1, TSC_G5_IO1,
JTDO-TRACESWO
-
FT
SPI1_MISO/I2S1_MCK,
SPI3_MISO/I2S3_MCK,
USART2_RX,
TIM162_CH1, TIM3_CH1,
TIM17_BKIN,
TIM15_CH1N,
TSC_G5_IO2, NJTRST
-
FT
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
I2C1_SMBA, USART2_CK,
TIM16_BKIN, TIM3_CH2,
TIM17_CH1, TIM19_ETR
-
FTf
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM3_CH3,
TIM4_CH1, TIM19_CH1,
TIM15_CH1, TSC_G5_IO3
-
89
90
91
92
A8
A7
C5
B5
55 39 C5
56 40 B5
57 41 A5
58 42 B6
PB3
PB4
PB5
PB6
I/O
I/O
I/O
I/O
-
-
-
-
DocID025608 Rev 4
39/131
47
Pinouts and pin description
STM32F378xx
Pin name
(function after
reset)
Pin
type
Notes
WLCSP66
LQFP48
LQFP64
BGA100
LQFP100
Pin numbers
I/O structure
Table 11. STM32F378xx pin definitions (continued)
93
B4
59 43 A6
PB7
I/O
-
FTf
94
A4
60 44 C7
BOOT0
I
-
B
95
A3
96
B3
97
C3
98
A2
99
D3
61 45 B7
62 46 A7
-
-
-
63 47 C6
PB8
I/O
-
Pin functions
Alternate function
Additional functions
I2C1_SDA, USART1_RX,
TIM17_CH1N, TIM3_CH4,
TIM4_CH2, TIM19_CH2,
TIM15_CH2, TSC_G5_IO4
-
Boot memory selection
FTf
SPI2_SCK/I2S2_CK,
I2C1_SCL, USART3_TX,
CAN_RX, CEC,
TIM16_CH1, TIM4_CH3,
TIM19_CH3, COMP1_OUT,
TSC_SYNC
-
-
PB9
I/O
-
FTf
SPI2_NSS/I2S2_WS,
I2C1_SDA, USART3_RX,
CAN_TX, IR_OUT,
TIM17_CH1, TIM4_CH4,
TIM19_CH4, COMP2_OUT
PE0
I/O
(1)
FT
USART1_TX, TIM4_ETR
-
PE1
I/O
(1)
FT
USART1_RX
-
VSS_1
S
-
-
Ground
-
Ground
-
-
-
-
G5
VSS_1
S
(1)
-
-
-
-
G4
VSS_1
S
(1)
-
Ground
100
C4
64 48 D6
VDD_1
S
-
-
Digital power supply
1. When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must
not be configured in analog mode.
2.
PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED)
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the RM0313 reference manual.
3. These pins are powered by VDDA.
4. These pins are powered by VDDSD12.
5. These pins are powered by VDDSD3.
40/131
DocID025608 Rev 4
Pin
Name
AF0
AF1
PA0
-
TIM2_
CH1_
ETR
PA1
RTC_
REFIN
PA2
AF2
DocID025608 Rev 4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF14
AF15
TIM5_
TSC_
CH1_
G1_IO1
ETR
-
-
-
USART2_CTS
COMP1
_OUT
-
-
TIM19
_CH1
-
EVENT
OUT
TIM2_
CH2
TIM5_ TSC_
CH2 G1_IO2
-
-
SPI3_SCK/
I2S3_CK
USART2_RTS
-
TIM15_
CH1N
-
TIM19
_CH2
-
EVENT
OUT
-
TIM2_
CH3
TIM5_ TSC_
CH3 G1_IO3
-
-
SPI3_MISO/
I2S3_MCK
USART2_TX
COMP2
_OUT
TIM15_
CH1
-
TIM19
_CH3
-
EVENT
OUT
PA3
-
TIM2_
CH4
TIM5_ TSC_
CH4 G1_IO4
-
-
SPI3_MOSI
/I2S3_SD
USART2_RX
-
TIM15_
CH2
-
TIM19
_CH4
-
EVENT
OUT
PA4
-
-
TIM3_ TSC_
CH2 G2_IO1
-
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART2_CK
-
-
TIM12
_CH1
-
-
EVENT
OUT
PA5
-
TIM2_
CH1_
ETR
TSC_
G2_IO2
-
SPI1_SCK/
I2S1_CK
-
CEC
-
TIM14_
CH1
TIM12
_CH2
-
-
EVENT
OUT
PA6
-
TIM16_
CH1
TIM3_ TSC_
CH1 G2_IO3
-
SPI1_MISO
/I2S1_MCK
-
-
COMP1
_OUT
TIM13_
CH1
-
-
-
EVENT
OUT
PA7
-
TIM17_
CH1
TIM3_ TSC_
CH2 G2_IO4
-
SPI1_MOSI
/I2S1_SD
-
-
COMP2
_OUT
TIM14_
CH1
-
-
-
EVENT
OUT
PA8
MCO
-
TIM5_
CH1_
ETR
I2C2_
SMBA
SPI2_SCK/
I2S2_CK
-
USART1_CK
-
-
TIM4_
ETR
-
-
EVENT
OUT
PA9
-
-
TIM13 TSC_
_CH1 G4_IO1
I2C2_
SCL
SPI2_MISO
/I2S2_MCK
-
USART1_TX
-
TIM15_
BKIN
TIM2_
CH3
-
-
EVENT
OUT
PA10
-
TIM17_
BKIN
-
TSC_
G4_IO2
I2C2_
SDA
SPI2_MOSI
/I2S2_SD
-
USART1_RX
-
TIM14_
CH1
TIM2_
CH4
-
-
EVENT
OUT
PA11
-
-
TIM5_
CH2
-
-
SPI2_NSS/
I2S2_WS
SPI1_NSS/
I2S1_WS
USART1_CTS
COMP1
_OUT
CAN_
RX
TIM4_
CH1
-
-
EVENT
OUT
PA12
-
TIM16_
CH1
TIM5_
CH3
-
-
-
SPI1_SCK/
I2S1_CK
USART1_RTS
COMP2
TIM4_
CAN_TX
_OUT
CH2
-
-
EVENT
OUT
-
STM32F378xx
AF4
-
AF3
Pinouts and pin description
41/131
Table 12. Alternate functions for port PA
Pin
Name
AF0
AF1
PA13
SWDIO
-JTMS
TIM16_
CH1N
PA14
SWCLK
-JTCK
-
-
PA15
JTDI
TIM2_
CH1_ETR
-
AF2
AF3
AF4
AF5
-
IR-OUT
TSC_
G4_IO4
I2C1_
SDA
-
-
TSC_
SYNC
I2C1_
SCL
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
TIM5_ TSC_
CH4 G4_IO3
AF6
AF7
AF8
AF9
AF10
AF11
AF14
AF15
-
-
TIM4_
CH3
-
-
EVENT
OUT
-
-
-
TIM12
_CH1
-
-
EVENT
OUT
-
-
-
TIM12
_CH2
-
-
EVENT
OUT
SPI1_MISO
USART3_CTS
/I2S1_MCK
Pinouts and pin description
42/131
Table 12. Alternate functions for port PA (continued)
DocID025608 Rev 4
STM32F378xx
Pin
Name
DocID025608 Rev 4
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF15
PB0
-
-
TIM3_CH3
TSC_
G3_IO3
-
SPI_MOSI/
I2S1_SD
-
-
-
-
TIM3_
CH2
-
EVENTOUT
PB1
-
-
TIM3_CH4
TSC_
G3_IO4
-
-
-
-
-
-
-
-
EVENTOUT
TIM4_ETR
TSC_
G5_IO1
-
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
USART2_TX
-
TIM13_ TIM3_
CH1
ETR
-
EVENTOUT
TIM16_
TSC_
TIM3_CH1
CH1
G5_IO2
-
SPI1_MISO SPI3_MISO/
USART2_RX
/I2S1_MCK I2S3_MCK
-
TIM15_ TIM17
CH1N _BKIN
-
EVENTOUT
I2C1_
SMBA
SPI1_MOSI SPI3_MOSI
USART2_CK
/I2S1_SD
/I2S3_SD
-
PB3
JTDOTIM2_
TRACESWO CH2
PB4
NJTRST
PB5
-
TIM16_
TIM3_CH2
BKIN
PB6
-
TIM16_
TSC_
I2C1_
TIM4_CH1
CH1N
G5_IO3 SCL
-
-
USART1_TX
PB7
-
TIM17_
TSC_
I2C1_
TIM4_CH2
CH1N
G5_IO4 SDA
-
-
USART1_RX
PB8
-
TIM16_
TSC_
TIM4_CH3
CH1
SYNC
I2C1_
SCL
SPI2_SCK/
I2S2_CK
CEC
USART3_TX
COMP1 CAN_
_OUT
RX
-
TIM19
EVENTOUT
_CH3
PB9
-
TIM17_
TIM4_CH4
CH1
I2C1_
SDA
SPI2_NSS/
I2S2_WS
IR-OUT
USART3_RX
COMP2 CAN_
_OUT
TX
-
TIM19
EVENTOUT
_CH4
PB10
-
TIM2_
CH3
-
TSC_
SYNCH
-
SPI2_SCK/
I2S2_CK
CEC
USART3_TX
-
-
-
-
EVENTOUT
PB14
-
TIM15_
CH1
-
TSC_
G6_IO1
-
SPI2_MISO
/I2S2_MCK
-
USART3_RTS
-
TIM12_
CH1
-
-
EVENTOUT
PB15
RTC_REFIN
TSC_
G6_IO2
-
SPI2_MOSI
/I2S2_SD
-
-
-
TIM12_
CH2
-
-
EVENTOUT
TIM15_ TIM15_
CH2
CH1N
-
-
TIM17
_CH1
TIM19
EVENTOUT
_ETR
-
TIM15_ TIM3_
CH1
CH3
TIM19
EVENTOUT
_CH1
-
TIM15_ TIM3_
CH2
CH4
TIM19
EVENTOUT
_CH2
-
Pinouts and pin description
43/131
Table 13. Alternate functions for port PB
STM32F378xx
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
DocID025608 Rev 4
PC0
-
EVENTOUT
TIM5_CH1_ETR
-
-
-
-
-
PC1
-
EVENTOUT
TIM5_CH2
-
-
-
-
-
PC2
-
EVENTOUT
TIM5_CH3
-
-
SPI2_MISO/I2S2_MCK
-
-
PC3
-
EVENTOUT
TIM5_CH4
-
-
SPI2_MOSI/I2S2_SD
-
-
PC4
-
EVENTOUT
TIM13_CH1
PC5
-
EVENTOUT
PC6
-
EVENTOUT
TIM3_CH1
-
-
SPI1_NSS/I2S1_WS
-
-
PC7
-
EVENTOUT
TIM3_CH2
-
-
SPI1_SCK/I2S1_CK
-
-
PC8
-
EVENTOUT
TIM3_CH3
-
-
SPI1_MISO/I2S1_MCK
-
-
PC9
-
EVENTOUT
TIM3_CH4
-
-
SPI1_MOSI/I2S1_SD
-
-
PC10
-
EVENTOUT
TIM19_CH1
-
-
-
SPI3_SCK/I2S3_CK
USART3_TX
PC11
-
EVENTOUT
TIM19_CH2
-
-
-
SPI3_MISO/I2S3_MCK
USART3_RX
PC12
-
EVENTOUT
TIM19_CH3
-
-
-
SPI3_MOSI/I2S3_SD
USART3_CK
PC13
-
-
-
-
-
-
-
-
PC14
-
-
-
-
-
-
-
-
PC15
-
-
-
-
-
-
-
-
-
TSC_G3_IO1
-
-
-
USART1_TX
TSC_G3_IO2
-
-
-
USART1_RX
Pinouts and pin description
44/131
Table 14. Alternate functions for port PC
STM32F378xx
Pin Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
DocID025608 Rev 4
PD0
-
EVENTOUT
TIM19_CH4
-
-
-
-
CAN_RX
PD1
-
EVENTOUT
TIM19_ETR
-
-
-
-
CAN_TX
PD2
-
EVENTOUT
TIM3_ETR
-
-
-
-
-
PD3
-
EVENTOUT
-
-
-
SPI2_MISO/I2S2_MCK
-
USART2_CTS
PD4
-
EVENTOUT
-
-
-
SPI2_MOSI/I2S2_SD
-
USART2_RTS
PD5
-
EVENTOUT
-
-
-
-
USART2_TX
PD6
-
EVENTOUT
-
-
-
SPI2_NSS/I2S2_WS
-
USART2_RX
PD7
-
EVENTOUT
-
-
-
SPI2_SCK/I2S2_CK
-
USART2_CK
PD8
-
EVENTOUT
-
TSC_G6_IO3
-
SPI2_SCK/I2S2_CK
-
USART3_TX
PD9
-
EVENTOUT
-
TSC_G6_IO4
-
-
-
USART3_RX
PD10
-
EVENTOUT
-
-
-
-
-
USART3_CK
PD11
-
EVENTOUT
-
-
-
-
-
USART3_CTS
PD12
-
EVENTOUT
TIM4_CH1
TSC_G8_IO1
-
-
-
USART3_RTS
PD13
-
EVENTOUT
TIM4_CH2
TSC_G8_IO2
-
-
-
-
PD14
-
EVENTOUT
TIM4_CH3
TSC_G8_IO3
-
-
-
-
PD15
-
EVENTOUT
TIM4_CH4
TSC_G8_IO4
-
-
-
-
-
Pinouts and pin description
45/131
Table 15. Alternate functions for port PD
STM32F378xx
Pin Name
AF0
AF1
AF2
TIM4_ETR
AF3
AF4
AF5
AF6
-
-
-
-
USART1_TX
USART1_RX
PE0
-
EVENTOUT
PE1
-
EVENTOUT
-
-
-
-
-
AF7
PE2
TRACECLK
EVENTOUT
-
TSC_G7_IO1
-
-
-
-
PE3
TRACED0
EVENTOUT
-
TSC_G7_IO2
-
-
-
-
PE4
TRACED1
EVENTOUT
-
TSC_G7_IO3
-
-
-
-
PE5
TRACED2
EVENTOUT
-
TSC_G7_IO4
-
-
-
-
PE6
TRACED3
EVENTOUT
-
-
-
-
-
-
DocID025608 Rev 4
PE7
-
EVENTOUT
-
-
-
-
-
-
PE8
-
EVENTOUT
-
-
-
-
-
-
PE9
-
EVENTOUT
-
-
-
-
-
-
PE10
-
EVENTOUT
-
-
-
-
-
-
PE11
-
EVENTOUT
-
-
-
-
-
-
PE12
-
EVENTOUT
-
-
-
-
-
-
PE13
-
EVENTOUT
-
-
-
-
-
-
PE14
-
EVENTOUT
-
-
-
-
-
-
PE15
-
EVENTOUT
-
-
-
-
-
Pinouts and pin description
46/131
Table 16. Alternate functions for port PE
USART3_RX
STM32F378xx
Pin Name
AF0
AF1
AF2
AF3
PF0
-
-
-
-
PF1
-
-
-
PF2
-
EVENTOUT
PF4
-
EVENTOUT
PF6
-
EVENTOUT
AF5
AF6
AF7
I2C2_SDA
-
-
-
-
I2C2_SCL
-
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
-
PF7
-
EVENTOUT
PF9
-
PF10
-
TIM4_CH4
AF4
-
-
I2C2_SCL
-
-
I2C2_SDA
EVENTOUT
TIM14_CH1
-
EVENTOUT
-
-
SPI1_MOSI/I2S1_SD
-
USART3_RTS
-
-
USART2_CK
-
-
-
-
-
-
-
-
Pinouts and pin description
47/131
Table 17. Alternate functions for port PF
DocID025608 Rev 4
STM32F378xx
Memory mapping
5
STM32F378xx
Memory mapping
Figure 7. STM32F378xx memory map
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48/131
DocID025608 Rev 4
STM32F378xx
Memory mapping
Table 18. STM32F378xx peripheral register boundary addresses(1)
Bus
AHB2
-
AHB1
-
Boundary address
Size
Peripheral
0x4800 1400 - 0x4800 17FF
1KB
GPIOF
0x4800 1000 - 0x4800 13FF
1KB
GPIOE
0x4800 0C00 - 0x4800 0FFF
1KB
GPIOD
0x4800 0800 - 0x4800 0BFF
1KB
GPIOC
0x4800 0400 - 0x4800 07FF
1KB
GPIOB
0x4800 0000 - 0x4800 03FF
1KB
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 MB
0x4002 4000 - 0x4002 43FF
1 KB
TSC
0x4002 3400 - 0x4002 3FFF
3 KB
Reserved
0x4002 3000 - 0x4002 33FF
1 KB
CRC
0x4002 2400 - 0x4002 2FFF
3 KB
Reserved
0x4002 2000 - 0x4002 23FF
1 KB
FLASH memory interface
0x4002 1400 - 0x4002 1FFF
3 KB
Reserved
0x4002 1000 - 0x4002 13FF
1 KB
RCC
0x4002 0800- 0x4002 0FFF
2 KB
Reserved
0x4002 0400 - 0x4002 07FF
1 KB
DMA2
0x4002 0000 - 0x4002 03FF
1 KB
DMA1
0x4001 6C00 - 0x4001 FFFF
37 KB
Reserved
DocID025608 Rev 4
Reserved
49/131
51
Memory mapping
STM32F378xx
Table 18. STM32F378xx peripheral register boundary addresses(1) (continued)
Bus
APB2
-
APB1
50/131
Boundary address
Size
Peripheral
0x4001 6800 - 0x4001 6BFF
1 KB
SDADC3
0x4001 6400 - 0x4001 67FF
1 KB
SDADC2
0x4001 6000 - 0x4001 63FF
1 KB
SDADC1
0x4001 5C00 - 0x4001 5FFF
1 KB
TIM19
0x4001 4C00 - 0x4001 5BFF
4 KB
Reserved
0x4001 4800 - 0x4001 4BFF
1 KB
TIM17
0x4001 4400 - 0x4001 47FF
1 KB
TIM16
0x4001 4000 - 0x4001 43FF
1 KB
TIM15
0x4001 3C00 - 0x4001 3FFF
1 KB
Reserved
0x4001 3800 - 0x4001 3BFF
1 KB
USART1
0x4001 3400 - 0x4001 37FF
1 KB
Reserved
0x4001 3000 - 0x4001 33FF
1 KB
SPI1/I2S1
0x4001 2800 - 0x4001 2FFF
1 KB
Reserved
0x4001 2400 - 0x4001 27FF
1 KB
ADC
0x4001 0800 - 0x4001 23FF
7 KB
Reserved
0x4001 0400 - 0x4001 07FF
1 KB
EXTI
0x4001 0000 - 0x4001 03FF
1 KB
SYSCFG + COMP
0x4000 4000 - 0x4000 FFFF
24 KB
Reserved
0x4000 9C00 – 0x4000 9FFF
1 KB
TIM18
0x4000 9800 - 0x4000 9BFF
1 KB
DAC2
0x4000 7C00 - 0x4000 97FF
8 KB
Reserved
0x4000 7800 - 0x4000 7BFF
1 KB
CEC
0x4000 7400 - 0x4000 77FF
1 KB
DAC1
0x4000 7000 - 0x4000 73FF
1 KB
PWR
0x4000 6800 - 0x4000 6FFF
2 KB
Reserved
0x4000 6400 - 0x4000 67FF
1 KB
CAN
0x4000 5C00 - 0x4000 63FF
2 KB
Reserved
DocID025608 Rev 4
STM32F378xx
Memory mapping
Table 18. STM32F378xx peripheral register boundary addresses(1) (continued)
Bus
APB1
Boundary address
Size
Peripheral
0x4000 5800 - 0x4000 5BFF
1 KB
I2C2
0x4000 5400 - 0x4000 57FF
1 KB
I2C1
0x4000 4C00 - 0x4000 53FF
2 KB
Reserved
0x4000 4800 - 0x4000 4BFF
1 KB
USART3
0x4000 4400 - 0x4000 47FF
1 KB
USART2
0x4000 4000 - 0x4000 43FF
1 KB
Reserved
0x4000 3C00 - 0x4000 3FFF
1 KB
SPI3/I2S3
0x4000 3800 - 0x4000 3BFF
1 KB
SPI2/I2S2
0x4000 3400 - 0x4000 37FF
1 KB
Reserved
0x4000 3000 - 0x4000 33FF
1 KB
IWDG
0x4000 2C00 - 0x4000 2FFF
1 KB
WWDG
0x4000 2800 - 0x4000 2BFF
1 KB
RTC
0x4000 2400 - 0x4000 27FF
1 KB
Reserved
0x4000 2000 - 0x4000 23FF
1 KB
TIM14
0x4000 1C00 - 0x4000 1FFF
1 KB
TIM13
0x4000 1800 - 0x4000 1BFF
1 KB
TIM12
0x4000 1400 - 0x4000 17FF
1 KB
TIM7
0x4000 1000 - 0x4000 13FF
1 KB
TIM6
0x4000 0C00 - 0x4000 0FFF
1 KB
TIM5
0x4000 0800 - 0x4000 0BFF
1 KB
TIM4
0x4000 0400 - 0x4000 07FF
1 KB
TIM3
0x4000 0000 - 0x4000 03FF
1 KB
TIM2
1. Cells in gray indicate Reserved memory locations.
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51
Electrical characteristics
STM32F378xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD =1.8 V, VDDA =
VDDSDx = 3.3 V. They are given only as design guidelines and are not tested.
Typical ADC and SDADC accuracy values are determined by characterization of a batch of
samples from a standard diffusion lot over the full temperature range, where 95% of the
devices have an error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
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9,1
069
52/131
DocID025608 Rev 4
069
STM32F378xx
6.1.6
Electrical characteristics
Power supply scheme
Figure 10. Power supply scheme
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1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply
pins.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
DocID025608 Rev 4
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110
Electrical characteristics
6.1.7
STM32F378xx
Current consumption measurement
Figure 11. Current consumption measurement scheme
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54/131
DocID025608 Rev 4
STM32F378xx
6.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 19. Voltage characteristics(1)
Symbol
Ratings
Min
Max
VDDA–VSS
External main supply voltage (including VDDA, VDDSDx, VBAT)
− 0.3
4.0
VDD–VSS
External supply voltage VDD
− 0.3
1.95
Allowed voltage difference for VDD > VDDA
-
0.4
Allowed voltage difference for VDDSDx > VDDA
-
0.4
Allowed voltage difference for VREFSD+ > VDDSD3
-
0.4
Allowed voltage difference for VREF+ > VDDA
-
0.4
Input voltage on FT and FTf pins
VSS −0.3
VDD + 4.0
Input voltage on POR pins
VSS −0.3
VDDA + 4.0
VSS −0.3
4.0
Input voltage on TC pins on SDADCx channels inputs
VSS − 0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
-
50
mV
-
50
mV
VDD–VDDA
VDDSDx – VDDA
VREFSD+ –
VDDSD3
VREF+ – VDDA
VIN
(2)
Input voltage on TTa pins
(3)
|VSSX - VSS|
|VREFSD- - VSSx|
VESD(HBM)
Variations between all the different ground pins
Electrostatic discharge voltage (human body model)
Unit
V
see Section 6.3.11:
Electrical sensitivity
characteristics
-
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2.
VIN maximum must always be respected. Refer to Table 20: Current characteristics for the maximum allowed injected
current values.
3. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected
to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally
connected to VSS).
All main power (VDD, VDDSD12, VDDSD3 and VDDA) and ground (VSS, VSSSD, and VSSA) pins
must always be connected to the external power supply, in the permitted range.
The following relationship must be respected between VDDA and VDD: VDDA must power on
before or at the same time as VDD in the power up sequence. VDDA must be greater than or
equal to VDD.
The following relationship must be respected between VDDA and VDDSD12: VDDA must power
on before or at the same time as VDDSD12 or VDDSD3 in the power up sequence. VDDA must
be greater than or equal to VDDSD12 or VDDSD3.
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110
Electrical characteristics
STM32F378xx
The following relationship must be respected between VDDSD12 and VDDSD3: VDDSD3 must
power on before or at the same time as VDDSD12 in the power up sequence.
After power up (VDDSD12 > Vrefint = 1.2 V) VDDSD3 can be higher or lower than VDDSD12.
The following relationship must be respected between VREFSD+ and VDDSD12, VDDSD3:
VREFSD+ must be lower than VDDSD3.
Depending on the SDADCx operation mode, there can be more constraints between
VREFSD+, VDDSD12 and VDDSD3 which are described in reference manual RM0313.
Table 20. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD_x and VDDSDx power lines
(source)(1)
160
ΣIVSS
Total current out of sum of all VSS_x and VSSSD ground lines
(sink)(1)
-160
Maximum current into each VDD_x or VDDSDx power pin (source)(1)
100
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
ΣIIO(PIN)
Maximum current out of each VSS_x or VSSSD ground pin
25
Output current source by any I/O and control pin
-25
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control
pins(2)
pins(3)
mA
80
-80
-5/+0
Injected current on TC and RST pin(4)
Injected current on TTa
ΣIINJ(PIN)
-100
Output current sunk by any I/O and control pin
Injected current on FT, FTf, POR and B
IINJ(PIN)
(sink)(1)
Unit
±5
pins(5)
±5
Total injected current (sum of all I/O and control
pins)(6)
± 25
1. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected
to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally
connected to VSS). VDD (VDD_x) is the external power supply for all remaining I/O pins (the I/O pin ground is internally
connected to VSS).
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 19: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 61.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
TSTG
TJ
56/131
Ratings
Storage temperature range
Maximum junction temperature
DocID025608 Rev 4
Value
Unit
–65 to +150
°C
150
°C
STM32F378xx
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
72
fPCLK1
Internal APB1 clock frequency
-
0
36
fPCLK2
Internal APB2 clock frequency
-
0
72
VDD
Standard operating voltage
Must have a potential equal to
or lower than VDDA
1.65
1.95
2.4
3.6
1.65
3.6
2.2
3.6
1.65
3.6
2.2
3.6
1.65
3.6
2.4
3.6
1.65
3.6
(1)
VDDA
VDDSD12
VDDSD3
VREF+
Analog operating voltage
(ADC and DAC used)
Must have a potential equal to
or higher than VDD
Analog operating voltage
(ADC and DAC not used)
VDDSD12 operating voltage
(SDADC used)
Must have a potential equal to
or lower than VDDA
VDDSD12 operating voltage
(SDADC not used)
VDDSD3 operating voltage
(SDADC used)
Must have a potential equal to
or lower than VDDA
VDDSD3 operating voltage
(SDADC not used)
Positive reference voltage (ADC
and DAC used)
Positive reference voltage (ADC
and DAC not used)
Must have a potential equal to
or lower than VDDA
Unit
MHz
V
V
V
V
V
VREFSD+
SDADCx positive reference
voltage
Must have a potential equal to
or lower than any VDDSDx
1.1
3.6
V
VBAT
Backup operating voltage
-
1.65
3.6
V
Input voltage on FT, FTf and POR
pins(2)
- 0.3
5.2
Input voltage on TTa pins
- 0.3
VDDA + 0.3
- 0.3
VDDSDx + 0.3
Input voltage on BOOT0 pin
0
5.5
Input voltage on any other pin
- 0.3
VDD
+ 0.3
VIN
Input voltage on TC pins on
SDADCx channels inputs(3)
-
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110
Electrical characteristics
STM32F378xx
Table 22. General operating conditions (continued)
Symbol
PD
Parameter
Min
Max
WLCSP66
-
376
LQFP100
-
434
LQFP64
-
444
LQFP48
-
364
BGA100
-
338
–40
85
–40
105
–40
105
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix
7(4)
Ambient temperature for 6 suffix
version
Maximum power dissipation
Ambient temperature for 7 suffix
version
Maximum power dissipation
TA
TJ
Conditions
Junction temperature range
Low power dissipation
Low power dissipation
(5)
(5)
Unit
mW
°C
°C
°C
1. When the ADC is used, refer to Table 59: ADC characteristics.
2. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
3. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected
to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally
connected to VSS).
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 23 are derived from tests performed under the ambient
temperature condition summarized in Table 22.
Table 23. Operating conditions at power-up / power-down
Symbol
tVDD
tVDDA
58/131
Parameter
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
Conditions
-
-
DocID025608 Rev 4
Min
Max
0
∞
20
∞
0
∞
20
∞
Unit
µs/V
STM32F378xx
6.3.3
Electrical characteristics
Embedded reference voltage
The parameters given in Table 25 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 22.
Table 24. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
VREFINT_CAL
0x1FFF F7BA - 0x1FFF F7BB
Table 25. Embedded internal reference voltage
Symbol
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.20
1.23
1.25
V
-
17.10
-
-
µs
VDD = 3 V ±10 mV
-
-
10
mV
Temperature coefficient
-
-
-
100
ppm/°C
Startup time
-
-
-
10
µs
tVREFINT_RD Internal reference voltage
(3)
temporization
Y
-
1.50
2.50
4.50
ms
VREFINT
TS_vrefint(1)
Parameter
Internal reference voltage
ADC sampling time when
reading the internal reference
voltage
Internal reference voltage
VREFINT_s(2) spread over the temperature
range
TCoeff(2)
tSTART
(2)
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
3. Guaranteed by design. Latency between the time when the NPOR pin is set to 1 by the application and the
time when the VREFINTRDYF bit is set to 1 by the hardware.
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110
Electrical characteristics
6.3.4
STM32F378xx
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz)
•
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fAPB1 = fAHB/2 , fAPB2 = fAHB
•
When fHCLK > 8 MHz PLL is ON and PLL inputs is equal to HSI/2 = 4 MHz (if internal
clock is used) or HSE = 8 MHz (if HSE bypass mode is used)
The parameters given in Table 26 to Table 32 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 22.
Table 26. Typical and maximum current consumption from VDD supply at VDD = 1.8V(1)
All peripherals enabled
Symbol Parameter Conditions
HSE
bypass,
PLL on
IDD
Supply
current in
Run mode,
code
executing
from Flash
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
60/131
fHCLK
Max @ TA(2)
Typ
All peripherals disabled
Max @ TA(2)
Typ
25 °C
85 °C
105 °C
72 MHz 64.9
75.3
77.1
84.0
64 MHz 58.3
67.0
68.7
48 MHz 44.8
50.5
32 MHz 30.7
Unit
25 °C
85 °C 105 °C
31.0
34.0
35.0
36.7
74.4
27.8
30.4
31.2
32.7
52.0
55.5
21.3
23.1
23.9
24.8
33.9
35.1
36.7
14.6
15.8
16.4
17.1
24 MHz 23.4
25.6
26.6
27.5
11.3
12.1
12.7
13.3
8 MHz
8.1
8.9
9.3
9.9
4.0
4.4
4.8
5.3
1 MHz
1.3
1.7
2.0
2.5
0.9
1.2
1.6
2.0
64 MHz 54.0
61.6
63.2
68.2
27.5
30.1
30.9
32.3
48 MHz 41.5
46.6
47.9
51.0
21.1
22.9
23.6
24.5
32 MHz 28.4
31.3
32.5
33.9
14.5
15.6
16.2
16.9
24 MHz 21.8
23.8
24.8
25.6
7.6
8.2
8.8
9.3
8 MHz
8.4
8.9
9.5
4.0
4.4
4.8
5.3
7.7
DocID025608 Rev 4
mA
STM32F378xx
Electrical characteristics
Table 26. Typical and maximum current consumption from VDD supply at VDD = 1.8V(1) (continued)
All peripherals enabled
Symbol Parameter Conditions
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
executing
from RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
IDD
HSE
bypass,
PLL on
Supply
current in
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
fHCLK
Max @ TA(2)
Typ
All peripherals disabled
Max @ TA(2)
Typ
25 °C
85 °C
105 °C
72 MHz 65.5
77.8
78.1
86.6
64 MHz 58.7
69.0
69.5
48 MHz 44.8
51.6
32 MHz 30.4
Unit
25 °C
85 °C 105 °C
31.6
35.1
35.6
38.0
76.5
28.2
31.2
31.7
33.7
52.2
56.6
21.4
23.3
23.9
25.1
34.2
34.9
37.1
14.4
15.6
16.1
16.8
24 MHz 23.1
25.7
26.2
27.6
10.9
11.8
12.2
12.8
8 MHz
7.7
8.4
8.9
9.5
3.6
4.0
4.4
5.0
1 MHz
1.0
1.3
1.7
2.2
0.5
0.7
1.1
1.7
64 MHz 54.3
63.3
63.9
70.1
27.9
30.8
31.2
33.2
48 MHz 41.5
47.3
48.0
51.9
21.1
23.0
23.5
24.7
32 MHz 28.2
31.5
32.2
34.1
14.2
15.3
15.9
16.5
24 MHz 21.4
23.6
24.3
25.5
7.2
7.8
8.2
8.8
8 MHz
7.3
7.9
8.4
9.1
3.6
4.0
4.4
4.9
72 MHz 46.4
54.0
54.8
59.5
7.2
7.9
8.4
9.0
64 MHz 41.5
48.0
48.8
52.6
6.5
7.1
7.5
8.1
48 MHz 31.6
35.9
36.7
39.0
4.9
5.3
5.8
6.4
32 MHz 21.4
23.8
24.7
25.7
3.3
3.7
4.2
4.7
24 MHz 16.2
17.9
18.6
19.4
2.5
2.8
3.3
3.8
8 MHz
5.4
5.9
6.5
7.0
0.8
1.1
1.6
2.1
1 MHz
0.7
1.0
1.4
1.9
0.1
0.3
0.7
1.3
64 MHz 37.0
42.4
43.3
46.4
6.1
6.7
7.2
7.7
48 MHz 28.2
31.8
32.7
34.5
4.6
5.0
5.5
6.1
32 MHz 19.1
21.2
22.0
22.9
3.1
3.5
4.0
4.5
24 MHz 14.5
16.0
16.7
17.4
1.7
2.0
2.4
2.9
8 MHz
5.5
6.0
6.6
0.8
1.1
1.5
2.0
5.0
mA
1. To calculate complete device consumption there must be added consumption from VDDA (Table 27).
2. Guaranteed by characterization results.
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110
Electrical characteristics
STM32F378xx
Table 27. Typical and maximum current consumption from VDDA supply
VDDA= 2.4 V
Symbol Parameter
Conditions
(1)
HSE
bypass,
PLL on
IDDA
Supply
current in
Run or
Sleep
mode,
code
executing
from Flash
or RAM
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
fHCLK
VDDA= 3.6 V
Max @ TA(2)
Typ
Max @ TA(2)
Typ
25 °C
85 °C
105 °C
72 MHz 226
250
272
279
247
268
302
308
64 MHz 200
223
245
250
218
240
267
273
48 MHz 150
172
189
194
163
182
207
210
32 MHz 103
122
137
139
111
130
147
148
24 MHz
80
99
109
111
86
102
117
117
8 MHz
1
3
3
3
1
3
3
4
1 MHz
1
3
3
4
1
3
4
4
64 MHz 268
293
319
325
296
321
351
358
48 MHz 219
242
263
267
241
263
290
296
32 MHz 171
193
210
213
189
209
230
234
24 MHz 148
169
181
184
165
182
200
203
8 MHz
84
86
87
80
93
95
97
68
25 °C
Unit
85 °C 105 °C
µA
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Guaranteed by characterization results.
Table 28. Typical and maximum VDD consumption in Stop mode
Max
Symbol
Parameter
Conditions
[email protected]
(VDD=1.8 V, VDDA=3.3 V)
IDD
Supply current
in Stop mode
All oscillators OFF
5.19
Note:
TA=
25 °C
TA=
85 °C
TA=
105 °C
29.2
485.7
1052.2
Unit
µA
To calculate complete device consumption there must be added consumption from VDDA (Table 29.
Table 29. Typical and maximum VDDA consumption in Stop mode
Symbol Parameter
IDDA
[email protected] (VDD= 1.8 V)
Max(1)
1.8 V 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
TA=
TA=
TA=
25 °C 85 °C 105 °C
Conditions
Supply
All oscillators
current in
OFF
Stop mode
0.74
0.76
0.78
0.81
0.86
1. Data based on characterization results and tested in production.
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0.92
1
8.8
10.1
11.6
Unit
µA
STM32F378xx
Electrical characteristics
Table 30. Typical and maximum current consumption from VBAT supply(1)
Max(2)
IDD_
VBAT
Backup
domain
supply
current
= 3.6 V
= 3.3 V
= 2.7 V
= 2.4 V
= 2.0 V
Conditions
= 1.8 V
Symbol Parameter
= 1.65 V
Typ @ VBAT
TA=
25 °C
LSE & RTC ON;
"Xtal mode" lower
0.50 0.52 0.55 0.63 0.70 0.87 0.95
driving capability;
LSEDRV[1:0] = '00'
1.1
LSE & RTC ON;
"Xtal mode" higher
0.85 0.90 0.93 1.02 1.10 1.27 1.38
driving capability;
LSEDRV[1:0] = '11'
1.6
TA=
TA=
85 °C 105 °C
1.6
Unit
2.2
µA
2.4
3.0
1. Crystal used: Abracon ABS07-120-32.768kHz-T with 6 pF of CL for typical values.
2. Guaranteed by characterization results.
Figure 12. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0]='00')
9
)
6"!4—!
9
9
9
9
9
9
9
ƒ&
ƒ&
ƒ&
4! #
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ƒ&
-36
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110
Electrical characteristics
STM32F378xx
Typical current consumption
The MCU is placed under the following conditions:
•
VDD = 1.8 V, VDDA = VDDSD12 = VDDSD3 = 3.3 V
•
All I/O pins are in analog input configuration
•
The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz)
•
Prefetch is ON
•
When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
•
PLL is used for frequencies greater than 8 MHz
•
AHB prescaler of 2, 4, 8, 16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively
Table 31. Typical current consumption in Run mode, code with data processing running from
Flash
Typ
Symbol
Parameter
Conditions
Running from HSE
crystal clock 8 MHz,
code executing
from Flash, PLL on
IDD
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing
from Flash, PLL off
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fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
61.0
28.6
64 MHz
54.7
25.7
48 MHz
42.0
20.0
32 MHz
28.5
13.7
24 MHz
21.8
10.5
16 MHz
14.6
7.3
8 MHz
7.5
3.8
4 MHz
4.3
2.2
2 MHz
2.5
1.4
1 MHz
1.6
1.0
500 kHz
1.2
0.8
125 kHz
0.9
0.6
DocID025608 Rev 4
Unit
mA
STM32F378xx
Electrical characteristics
Table 31. Typical current consumption in Run mode, code with data processing running from
Flash (continued)
Typ
Symbol
Parameter
Conditions
Running from HSE
crystal clock 8 MHz,
code executing
from Flash, PLL on
IDDA(1)(2)
Supply current in
Run mode from
VDDA supply
Running from HSE
crystal clock 8 MHz,
code executing
from Flash, PLL off
ISDADC12 +
ISDADC3
Supply currents in
Run mode from
VDDSD12 and
VDDSD3 (SDADCs
are off)
-
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
243.1
243.1
64 MHz
214.1
214.1
48 MHz
159.4
159.4
32 MHz
109.1
109.1
24 MHz
84.7
84.7
16 MHz
60.6
60.6
8 MHz
1.0
1.0
4 MHz
1.0
1.0
2 MHz
1.0
1.0
1 MHz
1.0
1.0
500 kHz
1.0
1.0
125 kHz
1.0
1.0
-
2.5
1
Unit
µA
µA
1. VDDA monitoring is off, VDDSD12 monitoring is off.
2. When peripherals are enabled, power consumption of the analog part of peripherals such as ADC, DACs, Comparators,
etc. is not included. Refer to those peripherals characteristics in the subsequent sections.
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110
Electrical characteristics
STM32F378xx
Table 32. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol
Parameter
Conditions
Running from HSE
crystal clock 8 MHz,
code executing
from Flash or RAM,
PLL on
IDD
Supply current in
Sleep mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing
from Flash or RAM,
PLL off
Running from HSE
crystal clock 8 MHz,
code executing
from Flash or RAM,
PLL on
IDDA(1)
Supply current in
Sleep mode from
VDDA supply
Running from HSE
crystal clock 8 MHz,
code executing
from Flash or RAM,
PLL off
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
42.6
6.7
64 MHz
38.0
6.0
48 MHz
28.7
4.5
32 MHz
19.3
3.1
24 MHz
14.6
2.4
16 MHz
9.8
1.7
8 MHz
4.8
0.8
4 MHz
3.0
0.7
2 MHz
1.9
0.6
1 MHz
1.3
0.6
500 kHz
1.0
0.6
125 kHz
0.8
0.5
72 MHz
243.1
243.1
64 MHz
214.1
214.1
48 MHz
159.4
159.4
32 MHz
109.1
109.1
24 MHz
84.7
84.7
16 MHz
60.6
60.6
8 MHz
1.0
1.0
4 MHz
1.0
1.0
2 MHz
1.0
1.0
1 MHz
1.0
1.0
500 kHz
1.0
1.0
125 kHz
1.0
1.0
1. VDDA monitoring is off, VDDSD12 monitoring is off.
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Unit
mA
µA
STM32F378xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC and SDADC input pins which
should be configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode. Under reset conditions all I/Os are configured in input floating mode so if some inputs do not have a defined voltage level then they can generate additional
consumption. This consumption is visible on VDD supply and also on VDDSDx supply
because some I/Os are powered from SDADCx supply (all I/Os which have SDADC analog
input functionality).
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 34: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+ CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F378xx
Table 33. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDD = 1.8 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 1.8 V
Cext = 10 pF
C = CINT + CEXT+ CS
ISW
I/O current
consumption
VDD = 1.8 V
Cext = 22 pF
C = CINT + CEXT+ CS
VDD = 1.8 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 1.8 V
Cext = 47 pF
C = CINT + CEXT+ CS
1. CS = 5 pF (estimated value).
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I/O toggling
frequency (fSW)
Typ
2 MHz
0.09
4 MHz
0.17
8 MHz
0.34
18 MHz
0.79
36 MHz
1.50
48 MHz
2.06
2 MHz
0.13
4 MHz
0.26
8 MHz
0.50
18 MHz
1.18
36 MHz
2.27
48 MHz
3.03
2 MHz
0.18
4 MHz
0.36
8 MHz
0.69
18 MHz
1.60
36 MHz
3.27
2 MHz
0.23
4 MHz
0.45
8 MHz
0.87
18 MHz
2.0
36 MHz
3.7
2 MHz
0.29
4 MHz
0.55
8 MHz
1.09
18 MHz
2.43
Unit
mA
mA
STM32F378xx
Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input configuration.
•
All peripherals are disabled unless otherwise mentioned.
•
The given value is calculated by measuring the current consumption
•
–
with all peripherals clocked off;
–
with only one peripheral clocked on.
Ambient operating temperature at 25°C and VDD = 1.8 V, VDDA = VDDSD12 = VDDSD3 =
3.3 V.
Table 34. Peripheral current consumption
Typical consumption(1)
Peripheral
AHB peripherals
-
BusMatrix(2)
6.9
DMA1
18.3
DMA2
4.8
CRC
2.6
GPIOA
12.2
GPIOB
11.9
GPIOC
4.3
GPIOD
12.0
GPIOE
4.4
GPIOF
3.7
TSC
5.7
APB2 peripherals
APB2-Bridge
(3)
4.2
SYSCFG & COMP
2.8
ADC1
17.7
SPI1
12.3
USART1
22.9
TIM15
15.7
TIM16
12.2
TIM17
12.1
TIM19
18.5
SDAC1
10.8
SDAC2
10.5
SDAC3
10.3
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110
Electrical characteristics
STM32F378xx
Table 34. Peripheral current consumption (continued)
Typical consumption(1)
Peripheral
Unit
APB1 peripherals
APB1-Bridge(3)
6.9
TIM2
47.9
TIM3
36.8
TIM4
36.9
TIM5
45.5
TIM6
8.4
TIM7
8.2
TIM12
21.3
TIM13
14.2
TIM14
14.4
TIM18
10.1
WWDG
4.7
SPI2
24.3
SPI3
25.3
USART2
45.3
USART3
43.1
I2C1
14.0
I2C2
13.9
CAN
38.1
DAC2
7.7
PWR
5.4
DAC1
14.8
CEC
5.4
µA/MHz
1. When peripherals are enabled, power consumption of the analog part of peripherals such as ADC, DACs,
Comparators, etc. is not included. Refer to those peripherals characteristics in the subsequent sections.
2. The BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus.
6.3.5
Wakeup time from low-power mode
The wakeup times given in Table 44 are measured from the wakeup event trigger to the first
instruction executed by the CPU. The clock source used to wake up the device depends
from the current operating mode:
•
Stop or sleep mode: the wakeup event is WFE.
•
The WKUP1 (PA0) pin is used to wakeup from stop and sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 22.
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Electrical characteristics
Table 35. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ @VDD = 1.8 V,
VDDA = 3.3 V
Max
Unit
3.6
5.21
µs
tWUSTOP
Wakeup from Stop mode
-
tWUSLEEP
Wakeup from Sleep mode
After WFE instruction
tWUPOR
Wakeup from Power off state
Startup after NPOR
pin release
6.3.6
CPU
clock
cycles
6
62.6
100
µs
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.
Table 36. High-speed external user clock characteristics
Symbol
Parameter(1)
User external clock source
fHSE_ext
frequency
Conditions
Min
CSS is on or
PLL is used
1
CSS is off,
PLL not used
0
Typ
Max
Unit
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
-
0.7 VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
-
VSS
-
0.3 VDD
-
15
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
V
ns
-
-
-
20
1. Guaranteed by design.
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Electrical characteristics
STM32F378xx
Figure 13. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
W
WZ+6(/
7+6(
069
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 14.
Table 37. Low-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User External clock source
frequency
-
-
32.768
1000
VLSEH
OSC32_IN input pin high level
voltage
-
0.7VDD
-
VDD
VLSEL
OSC32_IN input pin low level
voltage
-
VSS
-
0.3VDD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
-
450
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
ns
1. Guaranteed by design.
72/131
V
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-
-
-
50
STM32F378xx
Electrical characteristics
Figure 14. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+
9/6(/
WU/6(
WI/6(
W
WZ/6(/
7/6(
069
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 38. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 38. HSE oscillator characteristics
Conditions(1)
Min(2)
Typ
Max(2)
Unit
Oscillator frequency
-
4
8
32
MHz
Feedback resistor
-
-
200
-
kΩ
During startup(3)
-
-
8.5
VDD = 1.8 V, Rm= 30 Ω,
CL= 10 [email protected] MHz
-
0.4
-
VDD = 1.8 V, Rm= 45 Ω,
CL= 10 [email protected] MHz
-
0.5
-
VDD = 1.8 V, Rm= 30 Ω,
CL=5 [email protected] MHz
-
0.8
-
VDD = 1.8 V, Rm= 30 Ω,
CL= 10 [email protected] MHz
-
1
-
VDD = 1.8 V, Rm= 30 Ω,
CL= 20 [email protected] MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
Symbol
Parameter
fOSC_IN
RF
HSE current consumption
IDD
Oscillator transconductance
gm
tSU(HSE)
(4)
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
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Electrical characteristics
STM32F378xx
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Typical application with an 8 MHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1
0+]
UHVRQDWRU
&/
5(;7 I+6(
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
1. REXT value depends on the crystal characteristics.
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Electrical characteristics
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 39. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
gm
Parameter
LSE current consumption
Oscillator
transconductance
tSU(LSE)(3) Startup time
Conditions(1)
Min(2)
Typ
Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]= 10
medium low driving capability
-
-
1
LSEDRV[1:0] = 01
medium high driving capability
-
-
1.3
LSEDRV[1:0]=11
higher driving capability
-
-
1.6
LSEDRV[1:0]=00
lower driving capability
5
-
-
LSEDRV[1:0]= 10
medium low driving capability
8
-
-
LSEDRV[1:0] = 01
medium high driving capability
15
-
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
VDD is stabilized
-
2
-
µA
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
STM32F378xx
Figure 16. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
I/6(
26&B,1
'ULYH
SURJUDPPDEOH
DPSOLILHU
N+ ]
UHVRQDWRU
26&B28 7
&/
069
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.7
Internal clock source characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22.
The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Table 40. HSI oscillator characteristics(1)
Symbol
fHSI
TRIM
DuCy(HSI)
ACCHSI
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
-
-
8
-
MHz
HSI user trimming step
-
-
-
1(2)
%
-
45(2)
%
-
55(2)
TA = –40 to 105 °C
–3.8(3)
-
4.6(3)
%
TA = –10 to 85 °C
–2.9(3)
-
2.9(3)
%
TA = 0 to 70 °C
–2.3(3)
-
–2.2(3)
%
–1
-
1
%
Duty cycle
Accuracy of the HSI
oscillator (factory
calibrated)
TA = 25 °C
tsu(HSI)
HSI oscillator startup
time
-
1(3)
-
2(3)
µs
IDD(HSI)
HSI oscillator power
consumption
-
-
80
100(3)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
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Electrical characteristics
Figure 17. HSI oscillator accuracy characterization results
-!8
-).
4; #=
!
-36
Low-speed internal (LSI) RC oscillator
Table 41. LSI oscillator characteristics(1)
Symbol
fLSI
tsu(LSI)
Parameter
Min
Typ
Max
Unit
30
40
60
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
1.2
µA
Frequency
(2)
IDD(LSI)(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
6.3.8
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22.
Table 42. PLL characteristics
Symbol
Parameter
Value
Unit
Min
Typ
Max
1(2)
-
24(2)
MHz
PLL input clock duty cycle
(2)
40
-
60(2)
%
fPLL_OUT
PLL multiplier output clock
16(2)
-
72
MHz
tLOCK
PLL lock time
-
-
200(2)
µs
-
(2)
ps
fPLL_IN
Jitter
PLL input clock(1)
Cycle-to-cycle jitter
-
300
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
2. Guaranteed by design.
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6.3.9
STM32F378xx
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 43. Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
53.5
60
µs
Page (2 kB) erase time
TA = –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design.
Table 44. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
1 kcycle
10
(2)
at TA = 105 °C
kcycles(2)
at TA = 55 °C
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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Min(1)
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10
20
Unit
kcycles
Years
STM32F378xx
6.3.10
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Table 45. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 1.8 V, LQFP100, TA = +25 °C,
Voltage limits to be applied on any I/O pin
fHCLK = 72 MHz
to induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 1.8 V, LQFP100, TA = +25 °C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
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Electrical characteristics
STM32F378xx
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Symbol Parameter
SEMI
6.3.11
Conditions
Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/72 MHz
0.1 to 30 MHz
VDD - 1.8 V, TA - 25 °C,
30 to 130 MHz
LQFP100 package
Peak level
compliant with IEC
130 MHz to 1 GHz
61967-2
SAE EMI Level
16
20
dBµV
26
4
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
value(1)
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C,
conforming to JESD22A114
2
2000
TA = +25 °C,
conforming to
ANSI/ESD STM5.3.1,
LQFP100, LQFP64,
LQFP48 and BGA100
packages
II
500
TA = +25 °C,
conforming to JESD22C101, WLCSP66
package
II
250
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
1. Guaranteed by characterization results.
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V
STM32F378xx
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The test results are given in Table 49.
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Table 49. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
IINJ
Note:
82/131
Injected current on BOOT0 pin
-0
NA
Injected current on PC0 pin
-0
+5
Injected current on TC type I/O pins on VDDSD12 power
domain: PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14,
PE15, PB10 with induced leakage current on other pins from
this group less than -50 µA
-5
+5
Injected current on TC type I/O pins on VDDSD3 power
domain: PB14, PB15, PD8, PD9, PD10, PD12, PD13, PD14,
PD15 with induced leakage current on other pins from this
group less than -50 µA
-5
+5
Injected current on TTa type pins: PA4, PA5, PA6 with induced
leakage current on adjacent pins less than -10 µA
-5
+5
Injected current NPOR pin and on any other FT and FTf pins
-5
NA
Injected current on any other pins
-5
+5
mA
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
DocID025608 Rev 4
STM32F378xx
6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics (1)
Symbol
VIL
Parameter
Low level input
voltage
Conditions
High level input
voltage
Vhys
Ilkg
Input leakage
current (3)
Max
Unit
(2)
-
-
0.3VDD+0.07
FT and FTf I/O
-
-
0.475VDD–0.2(2)
BOOT0
-
-
0.3VDD–0.3(2)
All I/Os except BOOT0 pin
-
-
0.3VDD
+0.398(2)
-
-
0.445VDD
FT and FTf I/O
0.5VDD+0.2(2)
-
-
BOOT0
0.2VDD+0.95(2)
-
-
All I/Os except BOOT0 pin
0.7VDD
-
-
-
200(2)
-
FT and FTf I/O
-
100(2)
-
BOOT0
-
300(2)
-
TC, FT, FTf and POR I/O
TTa in digital mode
VSS ≤ VIN ≤ VDD
-
-
±0.1
TTa in digital mode
VDD ≤VIN ≤VDDA
-
-
1
TTa in analog mode
VSS ≤VIN ≤VDDA
-
-
±0.2
FT and FTf I/O (3)
VDD ≤VIN ≤5 V
-
-
10
POR
VDDA ≤ VIN ≤ 5 V
-
-
10
25
40
55
TC and TTa I/O
Schmitt trigger
hysteresis
Typ
TC and TTa I/O
TC and TTa I/O
VIH
Min
RPU
Weak pull-up
equivalent
resistor(4)
VIN = VSS
RPD
Weak pull-down
equivalent
resistor(4)
VIN = VDD
25
40
55
CIO
I/O pin capacitance
-
-
5
-
V
mV
µA
kΩ
pF
1. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is internally connected
to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15 I/O pins (the I/O pin ground is internally
connected to VSS). For those pins all VDD supply references in this table are related to their given VDDSDx power supply.
2. Guaranteed by design.
3. Leakage could be higher than maximum value, if negative current is injected on adjacent pins.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
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Electrical characteristics
Note:
STM32F378xx
I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs:
- The PB10 and PE7 to PE15 I/O pins are powered from VDDSD12.
- PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is
internally connected to VSS.
VDD mentioned in the Table 50 represents power voltage for a given I/O pin (VDD or
VDDSD12 or VDDSD3).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology parameters. The coverage of
these requirements is shown in Figure 18 for standard I/Os, and in Figure 19 for 5 V tolerant
I/Os. The following curves are design simulation results, not tested in production.
Figure 18. TC and TTa I/O input characteristics
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Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
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STM32F378xx
Electrical characteristics
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on all VDD_x and VDDSDx, plus the
maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute
maximum rating SIVDD (see Table 20).
•
The sum of the currents sunk by all the I/Os on all VSS_x and VSSSD, plus the
maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute
maximum rating SIVSS (see Table 20).
Output voltage levels
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 22. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).
Table 51. Output voltage characteristics (1)
Symbol
Parameter
Conditions
Min
Max
VOL(2)
Output low level voltage for an I/O pin
IIO = +4 mA
1.65 V < VDD < 1.95 V
-
0.4
VOH(3)
Output high level voltage for an I/O
pin
IIO = +4 mA
1.65 V < VDD < 1.95 V
VDD–0.4
-
VOL(2)(4)
Output low level voltage for an I/O pin
powered by VDDSDx(1)
VOH(3)(4)
Output high level voltage for an I/O
pin powered by VDDSDx(1)
VOL(2)(4)
Output low level voltage for an I/O pin
powered by VDDSDx(1)
VOH(3)(4)
Output high level voltage for an I/O
pin powered by VDDSDx(1)
VOLFM+(2)
Output low level voltage for a FTf I/O
pins in FM+ mode
IIO = +8 mA
2.7 V < VDDSDx < 3.6 V VDDSDx
–0.4
0.4
IIO = +20 mA
2.7 V < VDDSDx < 3.6 V VDDSDx
–1.3
1.3
IIO = +10 mA
1.65 V < VDD < 1.95 V
-
Unit
V
-
0.4
1. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is
internally connected to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15
I/O pins (the I/O pin ground is internally connected to VSS). For those pins all VDD supply references in this
table are related to their given VDDSDx power supply.
2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 20
and the sum of IIO (I/O ports and control pins) must not exceed IVSS(Σ) .
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 20 and the sum of IIO (I/O ports and control pins) must not exceed IVDD(Σ) .
4. Guaranteed by design.
Note:
I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs:
- The PB10 and PE7 to PE15 I/O pins are powered from VDDSD12.
- PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is
internally connected to VSS.
VDD mentioned in the Table 51 represents power voltage for a given I/O pin (VDD or
VDDSD12 or VDDSD3).
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 20 and
Table 52, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 22.
Table 52. I/O AC characteristics(1)
OSPEEDRy
[1:0] value(1)
x0
01
Symbol
Conditions
Min
Max
Unit
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
1
MHz
-
125(3)
-
125(3)
-
4
-
62.5
-
62.5
Maximum frequency(2)(3) CL = 50 pF, VDD = 1.65 V to 1.95 V
-
10
tf(IO)out
Output high to low level
fall time
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
25
tr(IO)out
Output low to high level
rise time
CL = 50 pF, VDD = 1.65 V to 1.95 V
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out
11
FM+
configuration
(4)
-
Parameter
CL = 50 pF, VDD = 1.65 V to 1.95 V
CL = 50 pF, VDD = 1.65 V to 1.95 V
ns
CL = 50 pF, VDD = 1.65 V to 1.95 V
ns
MHz
ns
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
-
25
-
0.5
-
16
-
44
10
-
2. The maximum frequency is defined in Figure 20.
3. Guaranteed by design.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F37xx reference manual RM0313 for a
description of FM+ I/O mode configuration
DocID025608 Rev 4
MHz
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0313 reference manual for a description of
GPIO Port configuration register.
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MHz
ns
STM32F378xx
Electrical characteristics
Figure 20. I/O AC characteristics definition
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6.3.14
NRST and NPOR pins characteristics
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 50).
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 22.
Table 53. NRST pin characteristics
Symbol
Conditions
Min
Typ
Max
VIL(NRST)(1) NRST Input low level voltage
-
-
-
0.3VDD + 0.07(1)
VIH(NRST)(1) NRST Input high level voltage
-
0.445VDD + 0.398(1)
-
-
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
VIN = VSS
25
40
55
kΩ
NRST Input filtered pulse
-
-
-
100
ns
NRST Input not filtered pulse
-
700
-
-
ns
Vhys(NRST)(1)
Weak pull-up equivalent resistor(2)
RPU
VF(NRST)(1)
VNF(NRST)
Parameter
(1)
Unit
V
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
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Figure 21. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset will not be taken into account by the device.
NPOR pin characteristics
The NPOR pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor to the VDDA, RPU (see Table 50).
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature and VDDA supply voltage conditions summarized in
Table 22.
Table 54. NPOR pin characteristics
Symbol
Conditions
Min
Typ
Max
-
-
-
0.475VDDA
- 0.2
VIH(NPOR)(1) NPOR Input high level voltage
-
0.5VDDA
+ 0.2
-
-
NPOR Schmitt trigger voltage
hysteresis
-
-
100
-
mV
VIN = VSS
25
40
55
kΩ
VIL(NPOR)(1)
Vhys(NPOR)(1)
RPU
Parameter
NPOR Input low level voltage
Weak pull-up equivalent resistor(2)
Unit
V
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
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6.3.15
Electrical characteristics
Communications interfaces
I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 55. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 55. I2C characteristics(1)
Standard
Symbol
Fast mode
Fast mode +
Parameter
Unit
Min
Max
Min
Max
Min
Max
0
100
0
400
0
1000
KHz
fSCL
SCL clock frequency
tLOW
Low period of the SCL clock
4.7
-
1.3
-
0.5
-
µs
tHIGH
High Period of the SCL clock
4
-
0.6
-
0.26
-
µs
tr
Rise time of both SDA and SCL
signals
-
1000
-
300
-
120
ns
tf
Fall time of both SDA and SCL
signals
-
300
-
300
-
120
ns
Data hold time
0
-
0
-
0
-
µs
-
3.45(2)
-
0.9(2)
-
0.45(2)
µs
-
3.45(2)
-
0.9(2)
-
0.45(2)
µs
tHD;DAT
tVD;DAT
Data valid time
tVD;ACK
Data valid acknowledge time
tSU;DAT
Data setup time
250
-
100
-
50
-
ns
tHD;STA
Hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
µs
tSU;STA
Set-up time for a repeated
START
condition
4.7
-
0.6
-
0.26
-
µs
tSU;STO
Set-up time for STOP condition
4.0
-
0.6
-
0.26
-
µs
Bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
µs
-
400
-
400
-
550
pF
tBUF
Cb
Capacitive load for each bus line
1. The I2C characteristics are the requirements from the I2C bus specification rev03. They are guaranteed by
design when the I2Cx_TIMING register is correctly programmed (refer to reference manual). These
characteristics are not tested in production.
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode
plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time.
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STM32F378xx
Table 56. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes that are
suppressed by the analog filter
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes width below tAF(min) are filtered.
3. Spikes width above tAF(max) are not filtered.
Figure 22. I2C bus AC waveforms and measurement circuit
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1. Legend: Rs: Series protection resistors. Rp: Pull-up resistors. VDD_I2C: I2C bus supply.
90/131
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STM32F378xx
Electrical characteristics
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 57 for SPI or in Table 58 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 22.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 57. SPI characteristics
Symbol
fSCK
1/tc(SCK)(1)
Parameter
SPI clock frequency
Conditions
Min
Max
Master mode (C = 30 pF)
-
18
Slave mode
-
18
-
8
ns
%
tr(SCK)
tf(SCK)(1)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)(1)
SPI slave input clock
duty cycle
Slave mode
30
70
tsu(NSS)(1)
NSS setup time
Slave mode
2Tpclk
-
th(NSS)(1)
NSS hold time
Slave mode
4Tpclk
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 Tpclk/2
-3
+3
(1)
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
th(MI)
Data input setup time
(1)
th(SI)(1)
Data input hold time
Master mode
5.5
-
Slave mode
6.5
-
Master mode
5
-
Slave mode
5
-
ta(SO)(1)(2)
Data output access time Slave mode, fPCLK = 24 MHz
0
4Tpclk
tdis(SO)(1)(3)
Data output disable time Slave mode
0
24
(1)
Data output valid time
Slave mode (after enable edge)
-
39
tv(MO)(1)
Data output valid time
Master mode (after enable edge)
-
3
Slave mode (after enable edge)
15
-
Master mode (after enable edge)
4
-
tv(SO)
th(SO)(1)
th(MO)(1)
Data output hold time
Unit
MHz
ns
1. Guaranteed by characterization results.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
DocID025608 Rev 4
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110
Electrical characteristics
STM32F378xx
Figure 23. SPI timing diagram - slave mode and CPHA = 0
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Figure 24. SPI timing diagram - slave mode and CPHA = 1(1)
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1. Measurement points are done at 0.5VDD level and with external CL = 30 pF.
92/131
DocID025608 Rev 4
STM32F378xx
Electrical characteristics
Figure 25. SPI timing diagram - master mode(1)
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1. Measurement points are done at 0.5VDD level and with external CL = 30 pF.
DocID025608 Rev 4
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110
Electrical characteristics
STM32F378xx
Table 58. I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
30
70
%
1.528
1.539
Slave mode
0
12.288
DuCy(SCK)(1)
I2S slave input clock duty
cycle
fCK(1)
1/tc(CK)
I2S clock frequency
tr(CK)(1)
tf(CK)
I2S clock rise and fall time
Capacitive load CL = 30 pF
-
8
tv(WS) (1)
WS valid time
Master mode
4
-
(1)
WS hold time
Master mode
4
-
WS setup time
Slave mode
2
-
-
-
306
-
312
-
Master receiver
6
-
Slave receiver
3
-
Master receiver
1.5
-
Slave receiver
1.5
-
th(WS)
tsu(WS) (1)
(1)
Slave mode
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
WS hold time
Slave mode
tw(CKH)
(1)
I2S clock high time
tw(CKL)
(1)
I2S clock low time
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
th(WS)
tsu(SD_MR) (1)
tsu(SD_SR)
(1)
th(SD_MR)
(1)
th(SD_SR)
(1)
Data input setup time
Data input hold time
MHz
tv(SD_ST) (1)
Data output valid time
Slave transmitter
(after enable edge)
-
16
th(SD_ST) (1)
Data output hold time
Slave transmitter
(after enable edge)
16
-
tv(SD_MT) (1)
Data output valid time
Master transmitter
(after enable edge)
-
2
th(SD_MT) (1)
Data output hold time
Master transmitter
(after enable edge)
0
-
1. Guaranteed by characterization results.
94/131
DocID025608 Rev 4
ns
STM32F378xx
Electrical characteristics
Figure 26. I2S slave timing diagram (Philips protocol)(1)
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1. Measurement points are done at 0.5 VDD level and with external CL = 30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 27. I2S master timing diagram (Philips protocol)(1)
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1. Measurement points are done at 0.5 VDD level and with external CL = 30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID025608 Rev 4
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110
Electrical characteristics
6.3.16
STM32F378xx
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 59 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply
voltage conditions summarized in Table 22.
Note:
It is recommended to perform a calibration after each power-up.
Table 59. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
-
2.4
-
3.6
V
VREF+
Positive reference voltage
-
2.4
-
VDDA
V
Negative reference voltage
-
0
-
-
V
VDDA = 3.3 V
-
0.9
-
mA
220(2)
µA
VREFIDDA(ADC)
(1)
Current consumption from VDDA
IVREF
Current on the VREF input pin
-
-
160(2)
fADC
ADC clock frequency
-
0.6
-
14
MHz
fS(3)
Sampling rate
-
0.05
-
1
MHz
fADC = 14 MHz
-
-
823
kHz
-
-
-
17
1/fADC
fTRIG(3)
External trigger frequency
VAIN
Conversion voltage range
-
0 (VSSA or VREFtied to ground)
-
VREF+
V
RSRC(3)
Signal source impedance
See Equation 1 and
Table 60 for details
-
-
50
kΩ
RADC(3)
Sampling switch resistance
-
-
-
1
kΩ
CADC(3)
Internal sample and hold
capacitor
-
-
-
8
pF
tCAL(3)
Calibration time
fADC = 14 MHz
5.9
µs
-
83
1/fADC
tlat(3)
Injection trigger conversion
latency
fADC = 14 MHz
-
tlatr(3)
Regular trigger conversion
latency
fADC = 14 MHz
tS(3)
Sampling time
tSTAB(3)
Power-up time
tCONV(3)
Total conversion time (including
sampling time)
-
-
0.214
µs
-
-
2(4)
1/fADC
-
-
0.143
µs
1/fADC
-
-
-
2(4)
fADC = 14 MHz
0.107
-
17.1
µs
-
1.5
-
239.5
1/fADC
-
-
-
1
µs
fADC = 14 MHz
1
-
18
µs
-
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD is present
2. Guaranteed by characterization results.
3. Guaranteed by design.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59
96/131
DocID025608 Rev 4
STM32F378xx
Electrical characteristics
Equation 1: RSRC max formula
TS
- – R ADC
R SRC < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external signal source
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 60. RSRC max for fADC = 14 MHz(1)
Ts (cycles)
tS (µs)
RSRC max (kΩ)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
50
239.5
17.1
50
1. Guaranteed by design.
Table 61. ADC accuracy(1)(2) (3)
Symbol
Parameter
Test conditions
Typ
Max(4)
±1.3
±3
±1
±2
±0.5
±1.5
±0.7
±1
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
±0.8
±1.5
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
fADC = 14 MHz, RSRC < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
fADC = 14 MHz, RSRC < 10 kΩ,
VDDA = 2.7 V to 3.6 V
TA = -40 to 105 °C
fADC = 14 MHz, RSRC < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Unit
LSB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
DocID025608 Rev 4
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110
Electrical characteristics
STM32F378xx
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should
be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Guaranteed by characterization results.
Figure 28. ADC accuracy characteristics
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Figure 29. Typical connection diagram using the ADC
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1. Refer to Table 59 for the values of RSRC, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
98/131
DocID025608 Rev 4
STM32F378xx
6.3.17
Electrical characteristics
DAC electrical specifications
Table 62. DAC characteristics
Symbol
Parameter
Conditions
Min Typ
Max
Unit
2.4
-
3.6
V
2.4
-
3.6
V
0
-
0
V
Connected to VSSA
5
-
-
Connected to VDDA
25
-
-
VDDA
Analog supply voltage
VREF+
Reference supply voltage VREF+ must always be below VDDA
VSSA
Ground
RLOAD(1)
Resistive load
DAC
output
buffer ON
RO(1)
Output Impedance
DAC output buffer OFF
-
-
15
kΩ
CLOAD(1)
Capacitive load
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
-
-
50
pF
0.2
-
-
V
-
-
VDDA – 0.2
V
-
0.5
-
mV
-
-
VREF+ – 1LSB
V
-
-
220
µA
-
-
380
µA
-
-
480
µA
Given for the DAC in 10-bit
configuration
-
-
± 0.5
LSB
Given for the DAC in 12-bit
configuration
-
-
±2
LSB
Given for the DAC in 10-bit
configuration
-
-
±1
LSB
Given for the DAC in 12-bit
configuration
-
-
±4
LSB
DAC_OUT
min(1)
DAC_OUT
max(1)
DAC_OUT
min(1)
DAC_OUT
max(1)
-
-
It gives the maximum output excursion
Lower DAC_OUT voltage of the DAC.
with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
Higher DAC_OUT
and (0x155) and (0xEAB) at VREF+ =
voltage with buffer ON
2.4 V
Lower DAC_OUT voltage
with buffer OFF
It gives the maximum output excursion
of the DAC.
Higher DAC_OUT
voltage with buffer OFF
DAC DC current
With no load, worst code (0xF1C) at
IDDVREF+(3) consumption in quiescent VREF+ = 3.6 V in terms of DC
consumption on the inputs
mode (Standby mode)
With no load, middle code (0x800) on
the inputs
IDDA(3)
DNL(3)
INL(3)
DAC DC current
consumption in quiescent With no load, worst code (0xF1C) at
mode(2)
VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
Difference between two
consecutive code-1LSB)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i
on a line drawn between
Code 0 and last Code
1023)
DocID025608 Rev 4
kΩ
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110
Electrical characteristics
STM32F378xx
Table 62. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
Max
Unit
-
-
-
±10
mV
Given for the DAC in 10-bit at VREF+ =
3.6 V
-
-
±3
LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
-
-
±12
LSB
Given for the DAC in 12bit
configuration
-
-
±0.5
%
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
-
3
4
µs
Update
rate(3)
Max frequency for a
correct DAC_OUT
change when small
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
variation in the input code
(from code i to i+1LSB)
-
-
1
MS/s
tWAKEUP(3)
Wakeup time from off
state (Setting the ENx bit
in the DAC Control
register)
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
-
6.5
10
µs
PSRR+ (1)
Power supply rejection
ratio (to VDDA) (static DC
measurement
No RLOAD, CLOAD = 50 pF
-
-67
-40
dB
Offset(3)
Gain
error(3)
Offset error
(difference between
measured value at Code
(0x800) and the ideal
value = VREF+/2)
Gain error
Settling time (full scale:
for a 10-bit input code
transition between the
tSETTLING(3) lowest and the highest
input codes when
DAC_OUT reaches final
value ±1LSB
1. Guaranteed by design.
2. Quiescent mode refers to the state of the DAC keeping a steady value on the output, so no dynamic consumption is
involved.
3. Guaranteed by characterization.
Figure 30. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
100/131
DocID025608 Rev 4
STM32F378xx
6.3.18
Electrical characteristics
Comparator characteristics
Table 63. Comparator characteristics
Symbol
Parameter
VDDA
Analog supply voltage
VIN
Conditions
Max(1)
Unit
-
3.6
V
Min Typ
VREFINT scaler not in use
1.65
VREFINT scaler in use
2
Comparator
input voltage range
-
0
-
VDDA
V
VBG
VREFINT scaler
input voltage
-
-
1.2
-
V
VSC
VREFINT scaler
offset voltage
-
-
±5
±10
mV
tS_SC
Scaler startup time
from power down
First VREFINT scaler activation after device
power on
-
-
tSTART
Comparator startup time
Propagation delay for
200 mV step with 100 mV
overdrive
Next activations
Propagation delay for full
range step with 100 mV
overdrive
-
-
60
Ultra-low power mode
-
2
4.5
Low power mode
-
0.7
1.5
Medium power mode
-
0.3
0.6
VDDA ≥ 2.7 V
-
50
100
VDDA < 2.7 V
-
100
240
Ultra-low power mode
-
2
7
Low power mode
-
0.7
2.1
Medium power mode
-
0.3
1.2
VDDA ≥ 2.7 V
-
90
180
VDDA < 2.7 V
-
110
300
High speed mode
ms
0.2
Startup time to reach propagation delay
specification
High speed mode
tD
1000(2)
µs
µs
ns
µs
ns
Voffset
Comparator offset error
-
-
±4
±10
mV
dVoffset/dT
Offset error temperature
coefficient
-
-
18
-
µV/°C
Ultra-low power mode
-
1.2
1.5
Low power mode
-
3
5
Medium power mode
-
10
15
High speed mode
-
75
100
IDD(COMP)
COMP current
consumption
DocID025608 Rev 4
µA
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110
Electrical characteristics
STM32F378xx
Table 63. Comparator characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
No hysteresis
(COMPxHYST[1:0]=00)
Low hysteresis
(COMPxHYST[1:0]=01)
Vhys
Comparator hysteresis
Medium hysteresis
(COMPxHYST[1:0]=10)
High hysteresis
(COMPxHYST[1:0]=11)
-
-
High speed mode
3
All other power
modes
5
High speed mode
7
All other power
modes
9
High speed mode
18
All other power
modes
19
Max(1)
0
Unit
13
8
10
mV
26
15
19
49
31
40
1. Guaranteed by design.
2. For more details and conditions see Figure 31: Maximum VREFINT scaler startup time from power down
Figure 31. Maximum VREFINT scaler startup time from power down
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STM32F378xx
6.3.19
Electrical characteristics
Temperature sensor characteristics
Table 64. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C ± 5 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C ± 5 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
Table 65. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
-
±1
±2
°C
TL
VSENSE linearity with temperature
Avg_Slope(1)
Average slope
4.0
4.3
4.6
mV/°C
V25
Voltage at 25 °C
1.34
1.43
1.52
V
tSTART(1)
Startup time
4
-
10
µs
TS_temp(2)(1)
ADC sampling time when reading the
temperature
17.1
-
-
µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.20
VBAT monitoring characteristics
Table 66. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
R
Resistor bridge for VBAT
-
50
-
KΩ
Q
Ratio on VBAT measurement
-
2
-
-
Error on Q
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
5
-
-
µs
Er(1)
TS_vbat(2)
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.21
Timer characteristics
The parameters given in Table 67 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
DocID025608 Rev 4
103/131
110
Electrical characteristics
STM32F378xx
Table 67. TIMx(1) (2)characteristics
Symbol
tres(TIM)
Parameter
Timer resolution time
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 72 MHz
13.9
-
ns
0
fTIMxCLK/2
MHz
0
24
MHz
TIMx (except
TIM2)
-
16
TIM2
-
32
-
1
65536
tTIMxCLK
fTIMxCLK = 72 MHz
0.0139
910
µs
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 72 MHz
-
59.65
s
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
fEXT
ResTIM
tCOUNTER
Timer resolution
16-bit counter clock period
tMAX_COUN Maximum possible count
with 32-bit counter
T
bit
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14,
TIM15, TIM16 , TIM17, TIM18 and TIM19 timers.
2. Guaranteed by characterization results.
Table 68. IWDG min/max timeout period at 40 kHz (LSI) (1)(2)
Prescaler divider
PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
7
6.4
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
2. Guaranteed by characterization results.
Table 69. WWDG min-max timeout value @72 MHz (PCLK)
104/131
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.05687
3.6409
2
1
0.1137
7.2817
4
2
0.2275
14.564
8
3
0.4551
29.127
DocID025608 Rev 4
STM32F378xx
6.3.22
Electrical characteristics
CAN (controller area network) interface
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.23
SDADC characteristics
Table 70. SDADC characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Note
-
VDDSDx
Power
supply
Slow mode (fADC = 1.5 MHz)
2.2
-
VDDA
Normal mode (fADC = 6 MHz)
2.4
-
VDDA
SDADC
clock
frequency
Slow mode (fADC = 1.5 MHz)
0.5
1.5
1.65
fADC
Normal mode (fADC = 6 MHz)
0.5
6
6.3
VREFSD+
Positive
ref. voltage
-
1.1
-
VDDSDx
V
-
VREFSD-
Negative
ref. voltage
-
-
VSSA
-
V
-
Normal mode (fADC = 6 MHz)
-
800
1200
-
Slow mode (fADC = 1.5 MHz)
-
-
600
-
Standby
-
-
200
Power down
-
-
2.5
-
SD_ADC off
-
-
1
-
VREFSD-
-
VREFSD+
/gain
VREFSD-
-
VREFSD+/
(gain*2)
VSSA
-
VDDSDx
IDDSDx
VAIN
Supply
current
(VDDSDx =
3.3 V)
Common
input
voltage
range
Single ended mode (zero reference)
Single ended offset mode
Differential mode
VDIFF
fS
tCONV
Differential
input
Differential mode only
voltage
Sampling
rate
Conversio
n time
V
-
MHz
µA
-
-
V
Voltage on
AINP or
AINN pin
-
Differential
voltage
between
AINP and
AINN
-VREFSD+/
(gain*2)
-
VREFSD+/
(gain*2)
Slow mode (fADC = 1.5 MHz)
-
4.166
-
fADC/360
Slow mode one channel only
(fADC = 1.5 MHz)
-
12.5
-
fADC/120
Normal mode multiplexed channel
(fADC = 6 MHz)
-
16.66
-
kHz f
ADC/360
Normal mode one channel only,
FAST= 1
(fADC = 6 MHz)
-
50
-
fADC/120
-
1/fs
-
-
DocID025608 Rev 4
s
-
105/131
110
Electrical characteristics
STM32F378xx
Table 70. SDADC characteristics (continued)(1)
Symbol
Parameter
Conditions
One channel, gain = 0.5,
fADC = 1.5 MHz
Rain
Analog
input
One channel, gain = 0.5, fADC = 6
impedance MHz
One channel, gain = 8, fADC = 6 MHz
tCALIB
Calibration
fADC = 6 MHz, one offset calibration
time
tSTAB
Stabilizatio
From power down fADC = 6 MHz
n time
tSTANDBY
Wakeup
from
standby
time
EG
106/131
540
-
-
135
-
-
47
-
-
5120
-
fADC = 6 MHz
-
50
-
fADC = 1.5 MHz
-
50
-
VREFSD+
= 3.3
-
-
110
VREFSD+
= 1.2
-
-
110
VREFSD+
= 3.3
-
-
100
VREFSD+
= 1.2
-
-
70
VREFSD+
= 3.3
-
-
100
fADC =
6 MHz
VDDSDx
= 3.3
VREFSD+
fADC =
1.5 MHz
= 3.3
gain = 1
gain = 1
gain = 8
fADC =
6 MHz
gain = 8
Offset
error
-
-
90
VREFSD+
= 1.2
-
-
2100
VREFSD+
= 3.3
-
-
2000
VREFSD+
= 1.2
-
-
1500
VREFSD+
= 3.3
-
-
1800
-
10
15
Offset drift
with
Differential or single ended mode,
temperatur gain = 1, VDDSDx = 3.3 V
e
Gain error
-
-
Differential mode
p
Max
100
Single ended mode
Dvoffsettem
Typ
-
fADC =
1.5 MHz
EO
Min
All gains, differential mode, single
ended mode
DocID025608 Rev 4
-2.4
-2.7
-3.1
Unit
Note
kΩ
see
reference
manual for
detailed
description
µs
30720/fADC
µs
600/fADC,
75/fADC if
SLOWCK
=1
300/fADC
µs
75/fADC if
SLOWCK
=1
uV
after offset
calibration
uV/K
-
%
negative
gain error =
data result
are greater
than ideal
STM32F378xx
Electrical characteristics
Table 70. SDADC characteristics (continued)(1)
Conditions
gain = 1
gain = 8
gain = 1
gain = 8
Differential mode
Differential
linearity
error
gain = 1
VDDSDx = 3.3
gain = 1
VDDSDx = 3.3
Single ended mode
ED
gain = 8
Integral
linearity
error(2)
Single ended mode
EL
Min
Typ
Max
Unit
Note
-
0
-
ppm
/K
-
VREFSD+
= 1.2
-
-
16
VREFSD+
= 3.3
-
-
14
VREFSD+
= 1.2
-
-
26
VREFSD+
= 3.3
-
-
14
VREFSD+
= 1.2
LSB
-
-
-
31
VREFSD+
= 3.3
-
-
23
VREFSD+
= 1.2
-
-
80
VREFSD+
= 3.3
-
-
35
VREFSD+
= 1.2
-
-
2.4
VREFSD+
= 3.3
-
-
1.8
VREFSD+
= 1.2
-
-
3.6
VREFSD+
= 3.3
-
-
2.9
VREFSD+
= 1.2
LSB
-
-
-
3.2
VREFSD+
= 3.3
-
-
2.8
VREFSD+
= 1.2
-
-
4.1
VREFSD+
= 3.3
-
-
3.3
Gain drift
with
gain = 1, differential mode, single
temperatur ended mode
e
Differential mode
EGT
Parameter
gain = 8
Symbol
DocID025608 Rev 4
107/131
110
Electrical characteristics
STM32F378xx
Table 70. SDADC characteristics (continued)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
VREFSD+
= 3.3(3)
84
85
-
VREFSD+
= 1.2(4)
86
88
-
VREFSD+
= 3.3
88
92
-
VREFSD+
= 1.2(4)
76
78
-
VREFSD+
= 3.3
82
86
-
fADC =
VDDSDx VREFSD+
1.5 MHz = 3.3
= 3.3(3)
76
80
-
fADC =
1.5 MHz
VREFSD+
= 3.3
80
84
-
VREFSD+
= 1.2(4)
77
81
-
VREFSD+
= 3.3
85
90
-
VREFSD+
= 1.2(4)
66
71
-
VREFSD+
= 3.3
74
78
-
108/131
gain = 1
gain = 8
gain = 1
Signal to
noise ratio
Single ended mode
SNR(5)
gain = 8
Differential mode
fADC =
1.5 MHz
fADC =
6 MHz
fADC =
6 MHz
fADC =
6 MHz
fADC =
6 MHz
DocID025608 Rev 4
Unit
Note
dB
-
STM32F378xx
Electrical characteristics
Table 70. SDADC characteristics (continued)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
VREFSD+
= 3.3(3)
76
77
-
VREFSD+
= 1.2(4)
75
76
-
VREFSD+
= 3.3
76
77
-
VREFSD+
= 1.2(4)
70
74
-
VREFSD+
= 3.3
79
85
-
fADC =
VDDSDx VREFSD+
1.5 MHz = 3.3
= 3.3(3)
75
81
-
fADC =
1.5MHz
VREFSD+
= 3.3
72
73
-
VREFSD+
= 1.2(4)
68
71
-
VREFSD+
= 3.3
72
73
-
VREFSD+
= 1.2(4)
60
64
-
VREF =
3.3
67
72
-
VREFSD+
= 3.3(3)
-
-77
-76
VREFSD+
= 1.2(4)
-
-77
-76
VREFSD+
= 3.3
-
-77
-76
VREFSD+
= 1.2(4)
-
-85
-70
VREFSD+
= 3.3
-
-93
-80
gain =1
gain =8
gain =1
Single ended mode
SINAD(5)
Signal to
noise and
distortion
ratio
gain =8
Differential mode
fADC =
1.5 MHz
fADC = 6
MHz
fADC = 6
MHz
fADC =
6 MHz
fADC =
6 MHz
gain =1
gain =8
gain =1
Single ended mode
THD(5)
Total
harmonic
distortion
gain =8
Differential mode
fADC =
1.5 MHz
fADC =
6 MHz
fADC =
6 MHz
VDDSDx
= 3.3
VREFSD+
fADC =
1.5 MHz
= 3.3(3)
fADC =
6 MHz
fADC =
6 MHz
-
-93
-83
VREFSD+
= 1.2(4)
-
-72
-68
VREFSD+
= 3.3
-
-74
-72
VREFSD+
= 1.2(4)
-
-66
-61
VREFSD+
= 3.3
-
-75
-70
DocID025608 Rev 4
Unit
Note
dB
ENOB =
SINAD/
6.02 - 0.292
dB
-
109/131
110
Electrical characteristics
STM32F378xx
1. Guaranteed by characterization results.
2. Integral linearity error can be improved by software calibration of SDADC transfer curve (2-nd order polynomial calibration).
3. For fADC lower than 5 MHz, there will be a performance degradation of around 2 dB due to flicker noise increase.
4. If the reference value is lower than 2.4 V, there will be a performance degradation proportional to the reference supply drop,
according to this formula: 20*log10(VREF/2.4) dB
5. SNR, THD, SINAD parameters are valid for frequency bandwidth 20Hz - 1kHz. Input signal frequency is 300Hz (for
fADC=6MHz) and 100Hz (for fADC=1.5MHz).
Table 71. VREFSD+ pin characteristics(1)
Symbol
VREFINT
CVREFSD+(2)
RVREFSD+
Parameter
Internal reference
voltage
Reference voltage
filtering capacitor
Reference voltage
input impedance
Conditions
Min
Typ
Max
Unit
Note
Buffered embedded
reference voltage (1.2 V)
-
1.2
-
V
See Section 6.3.3:
Embedded
reference voltage on
page 59
Embedded reference
voltage amplified by
factor 1.5
-
1.8
-
V
-
1000
-
10000
nF
-
Normal mode
(fADC = 6 MHz)
-
238
-
Slow mode
(fADC = 1.5 MHz)
kΩ
-
See RM0313
reference manual for
detailed description
VREFSD+ = VREFINT
952
-
1. Guaranteed by characterization results.
2.
If internal reference voltage is selected then this capacitor is charged through internal resistance - typ. 300 ohm. If internal
reference source is selected through the reference voltage selection bits (REFV<>”00” in SDADC_CR1 register), the
application must first configure REFV bits and then wait for capacitor charging. Recommended waiting time is 3 ms if 1 µF
capacitor is used.
110/131
DocID025608 Rev 4
STM32F378xx
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
UFBGA100 package information
Figure 32. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch,
ultra fine pitch ball grid array package outline
= 6HDWLQJSODQH
GGG =
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1. Drawing is not to scale.
Table 72. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
-
0.130
-
-
0.0051
-
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
DocID025608 Rev 4
111/131
128
Package information
STM32F378xx
Table 72. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.450
5.500
5.550
0.2146
0.2165
0.2185
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.450
5.500
5.550
0.2146
0.2165
0.2185
e
-
0.500
-
-
0.0197
-
F
0.700
0.750
0.800
0.0276
0.0295
0.0315
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 33. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch,
ultra fine pitch ball grid array package recommended footprint
'SDG
'VP
$&B)3B9
Table 73. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension
112/131
Recommended values
Pitch
0.5
Dpad
0.280 mm
Dsm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.280 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
DocID025608 Rev 4
STM32F378xx
Package information
Device Marking for UFBGA100
The following figure gives an example of topside marking orientation versus ball 1 identifier
location.
Figure 34. UFBGA100 marking example (package top view)
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5
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025608 Rev 4
113/131
128
Package information
7.2
STM32F378xx
WLCSP66 package information
Figure 35. WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch wafer level chip scale
package outline
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1. Drawing is not to scale.
Table 74. WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
114/131
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.540
0.570
0.600
0.0213
0.0224
0.0236
A1
-
0.190
-
-
0.0075
-
A2
-
0.380
-
-
0.0150
-
b(2)
0.240
0.270
0.300
0.0094
0.0106
0.0118
D
3.732
3.767
3.802
0.1469
0.1483
0.1497
E
4.194
4.229
4.264
0.1651
0.1665
0.1679
e
-
0.400
-
-
0.0157
-
e1
-
2.800
-
-
0.1102
-
e2
-
3.200
-
-
0.1260
-
DocID025608 Rev 4
STM32F378xx
Package information
Table 74. WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch wafer level chip scale
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
F
-
0.484
-
-
0.0191
-
G
-
0.515
-
-
0.0203
-
aaa
-
-
0.100
-
-
0.0039
bbb
-
-
0.100
-
-
0.0039
ccc
-
-
0.100
-
-
0.0039
ddd
-
-
0.050
-
-
0.0020
eee
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Device Marking for WLCSP66
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 36. WLCSP66 marking example (package top view)
WŝŶϭŝĚĞŶƚŝĨŝĞƌ
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025608 Rev 4
115/131
128
Package information
7.3
STM32F378xx
LQFP100 package information
Figure 37. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
MM
C
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1. Drawing is not to scale.
116/131
%
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DocID025608 Rev 4
,?-%?6
STM32F378xx
Package information
Table 75. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
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-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
STM32F378xx
Figure 38. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 39. LQFP100 marking example (package top view)
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qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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LQFP64 package information
Figure 40. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
PP
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1. Drawing is not to scale.
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Package information
STM32F378xx
Table 76. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
Figure 41. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 42. LQFP64 marking example (package top view)
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qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
7.5
STM32F378xx
LQFP48 package information
Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
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1. Drawing is not to scale.
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DocID025608 Rev 4
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STM32F378xx
Package information
Table 77. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
STM32F378xx
Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
AID
1. Dimensions are expressed in millimeters.
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 45. LQFP48 marking example (package top view)
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1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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7.6
Package information
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 22: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x QJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
QJA is the package junction-to-ambient thermal resistance, in °C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = S (VOL × IOL) + S((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 78. Package thermal characteristics
Symbol
ΘJA
7.6.1
Parameter
Value
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
BGA100 - 7 x 7 mm
59
Thermal resistance junction-ambient
WLCSP66 - 0.400 mm
53
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
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Package information
7.6.2
STM32F378xx
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F378xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 1.8 V, maximum 3 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 2 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 1.8 V= 90 mW
PIOmax = 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW
This gives: PINTmax = 90 mW and PIOmax = 61.6 mW:
PDmax = 90 + 61.6 = 151.6 mW
Thus: PDmax = 151.6 mW
Using the values obtained in Table 78 TJmax is calculated as follows:
–
For LQFP64, 45°C/W
TJmax = 82 °C + (45°C/W × 151.6 mW) = 82 °C + 6.8 °C = 88.8 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 1.8 V, maximum 9 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 1.8 V= 36 mW
PIOmax = 9 × 8 mA × 0.4 V = 28.8 mW
This gives: PINTmax = 36 mW and PIOmax = 28.8 mW:
PDmax = 36+ 28.8 = 64.8 mW
Thus: PDmax = 64.8 mW
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Package information
Using the values obtained in Table 78 TJmax is calculated as follows:
–
For LQFP100, 46°C/W
TJmax = 115 °C + (46°C/W × 64.8 mW) = 115 °C + 2.98 °C = 118 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering).
Figure 46. LQFP64 PD max vs. TA
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Part numbering
8
STM32F378xx
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 79. Ordering information scheme
Example:
STM32
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
378 = STM32F378xx
Pin count
C = 48 pins
R = 64/66 pins
V = 100 pins
Code size
C = 256 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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378
R
C
T
6
x
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9
Revision history
Revision history
Table 80. Document revision history
Date
Revision
04-Mar-2014
1
Initial release.
09-Apr-2014
2
Removed sub-set part number (64KB and 128KB).
Updated Part numbering on page 128
3
Updated Section 7
Updated Section 3.13
Updated Section 3.7.1, Section 3.7.3
Updated Table 2: Device overview, Table 11: STM32F378xx pin
definitions, Table 22: General operating conditions, Table 47: ESD
absolute maximum ratings, Table 70: SDADC characteristics,
Table 74: WLCSP66 - 66-pin, 3.767 x 4.229 mm, 0.4 mm pitch
wafer level chip scale package mechanical data and Table 75:
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data, Table 78: Package thermal characteristics and
Table 79: Ordering information scheme
Updated Figure 5: STM32F378xx UFBGA100 ballout, Figure 10:
Power supply scheme, Figure 35: WLCSP66 - 66-pin, 3.767 x
4.229 mm, 0.4 mm pitch wafer level chip scale package outline,
Figure 36: WLCSP66 marking example (package top view),
Figure 38: LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint, Figure 39: LQFP100 marking example
(package top view), Figure 40: LQFP64 - 64-pin, 10 x 10 mm lowprofile quad flat package outline, Figure 41: LQFP64 - 64-pin, 10 x
10 mm low-profile quad flat package recommended footprint,
Figure 42: LQFP64 marking example (package top view),
Figure 44: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat
package recommended footprint, Figure 45: LQFP48 marking
example (package top view).
Added Table 30: Typical and maximum current consumption from
VBAT supply, Table 63: Comparator characteristics, Table 73:
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Added Figure 12: Typical VBAT current consumption (LSE and
RTC ON/LSEDRV[1:0]='00'), Figure 31: Maximum VREFINT
scaler startup time from power down and Figure 33: UFBGA100 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package recommended footprint.
21-Jul-2015
Changes
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Revision history
STM32F378xx
Table 80. Document revision history (continued)
Date
10-Jun-2016
130/131
Revision
Changes
4
Updated:
– Table 3: Capacitive sensing GPIOs available on STM32F378xx
devices
– Table 19: Voltage characteristics
– Table 25: Embedded internal reference voltage
– Table 39: LSE oscillator characteristics (fLSE = 32.768 kHz)
– Table 47: ESD absolute maximum ratings
– Table 59: ADC characteristics
– Table 62: DAC characteristics
– Table 64: Temperature sensor calibration values
– Table 70: SDADC characteristics
– Table 78: Package thermal characteristics
– Figure 18: TC and TTa I/O input characteristics
– Figure 19: Five volt tolerant (FT and FTf) I/O input
characteristics
Removed:
– Figure 19: TC and TTa I/O input characteristics - TTL port
– Figure 21: Five volt tolerant (FT and FTf) I/O input
characteristics - TTL port
DocID025608 Rev 4
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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