05 VGA

05 VGA
VGA Display Port
Task:
Generate a video output signal, which displays some simple picture or textual information
on the monitor screen. The background should not be black. Test the design on FPGA
development board.
Additional Information
Both Spartan-3 and Spartan-3E Starter Kit boards feature a VGA Display Port and DB15
connector. It may be connected directly to most PC monitors or flat-panel LCD displays
using a standard monitor cable. The FPGA device controls five VGA signals: Red, Green,
Blue, Horizontal Sync and Vertical Sync. Eight possible colors can be generated (Table 1).
Table 1: VGA Color Codes
Red
Green Blue Color
0
0
0
Black
0
0
1
Blue
0
1
0
Green
0
1
1
Cyan
1
0
0
Red
1
0
1
Magenta
1
1
0
Yellow
1
1
1
White
The major component inside VGA monitor is color Cathode Ray Tube (CRT). The electron
beam must be scanned over the viewing screen in a sequence of horizontal lines to generate
an image. Light is generated when the beam is turned on by a video signal and it strikes a
color phosphor dot on the face of the CRT. The video signal must redraw the entire screen
at least 60 times per second to provide motion in the image and to reduce flicker.
The beam moves on the display surface in a “raster” pattern, horizontally from left to right
and vertically from top to bottom. Information is displayed only when it moves in forward
direction. Thus, much of the time is lost in blank periods, when beam is reset and stabilized
to begin a new pass. VGA controller generates two synchronizing signals – Horizontal Sync
(HS) and Vertical Sync (VS) to control the raster pattern and video data delivery.
The VS signal defines the refresh frequency of the display (the frequency at which all
information is redrawn). The HS signal defines the number of horizontal lines displayed at
a given refresh rate. Both signals have the same waveform (Figure 1), but their timing is
different. The pixel clock defines the time available to display one pixel of information.
Figure 1: Sync Signal Waveform
Table 2 provides timing information for driving a CRT monitor in 640-pixels by 480-rows
mode, using 25MHz pixel clock and 60Hz refresh frequency. LCD displays can also be
controlled using the same synchronization timing. Note that during the front and back porch
intervals information can not be displayed (RGB signals must be set to zero).
Generally, a counter clocked by the pixel clock could control the horizontal timing. From
its value current pixel display location on a given row can be easily tracked, as well as the
correct time for HS signal transitions. A separate counter can could do the same to control
the vertical timing. It increments with each HS pulse, tracks the current display row and can
be used to control the VS signal transitions. Values of these two constantly running counters
can be used to form a Video Memory address for the currently displayed pixel.
Table 2: 640x480 60Hz Mode Synchronization Timing
Vertical Sync
Horizontal Sync
Parameter
Time
Clocks Lines Time Clocks
Sync Pulse Time
Display time
16.7 ms
416800
521
32 µs
800
15.36 ms 384000
480
25.6 µs
640
Pulse Width
64 µs
1600
2
3.84 µs
96
Front Porch
320 µs
8000
10.
640 ns
16
Back Porch
928 µs
23200
29
1.92 µs
48
In order to test the design, connect FPGA development board to the VGA input of the
monitor and set the source of video signal to “VGA”. If generated image is out of place,
either run an automatic calibration or correct image position manually.
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