Port Integration Module

Port Integration Module
Port Integration Module
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
80 Pin QFP bond-out version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Overview
The Port Integration Module establishes the interface between the
peripheral modules and the I/O pins for all ports except A, B, E and K.
Those ports are handled by the HC12 multiplexed bus interface and
described in Bus Control and Input/Output, due to their tight link with the
external bus interface and special modes.
The two 8-bit ports associated with the ATD are included in the ATD
module due to their sensitivity to electrical noise, requiring special care
on routing and design.
This section covers port T connected to the timer module, the serial
port S associated with 2 SCI and 1 SPI module, the multiplex ports M,
associated with 4 CAN and 1 BDLC module, and P, connected to the
PWM and 2 SPI modules, the standard I/O port H, and finally the port J
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Port Integration Module
associated with the fifth CAN module and the IIC interface1. Ports P, H
and J can also be used as external interrupt sources.
Each I/O pin can be configured by several registers: Input/output
selection, drive strength reduction, enable and select of pull resistors,
interrupt enable and status flags.
The port integration module is device dependant which is reflected in its
naming.
A standard port has the following minimum features:
•
Input/output selection
•
5V output drive with two selectable drive strength
•
5V digital and analog input
•
Input with selectable pull-up or pull-down device
Optional features:
•
Open drain for wired-or connections
•
Interrupt inputs with glitch filtering
Table 41 Port Reset State and Priority Summary
Reset States
Port
Priority
Data
Direction
Pull Mode
Red. Drive
Wired-Or
Mode
Interrupt
T
input
hiz
disabled
n/a
n/a
ECT > GPIO
S
input
pull-up
disabled
disabled
n/a
SCI, SPI > GPIO
M
input
hiz
disabled
disabled
n/a
CAN > BDLC > GPIO
P
input
hiz
disabled
n/a
disabled
PWM > SPI > GPIO
H
input
hiz
disabled
n/a
disabled
GPIO
J
input
pull-up
disabled
n/a
disabled
CAN > IIC > GPIO
1. The port control register addresses are allocated in the order of their most likely occurrence,
i.e. almost all STAR12 derivatives will have a timer port, and a very limited number will have a
IIC module. This allows best consistency in the address allocation.
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Block Diagram
Block Diagram
INTJ
INTH
INTP
IP-Bus
PM1
Port M
PM2
PM3
PM4
PM5
PM6
PM7
RXD
TXD
RXD
SCI1
TXD
SDI/MISO
SDO/MOSI
SCK
SPI0
SS
Interrupt Logic
Timer
RxB
BDLC
TxB
RxCAN
CAN0
TxCAN
RxCAN
CAN1
TxCAN
RxCAN
CAN2
TxCAN
RxCAN
CAN3
TxCAN
SDI/MISO
SDO/MOSI
SCK
SPI1
SS
SDI/MISO
SDO/MOSI
SS
SPI2
SCK
Port T
PM0
PW0
PW1
PW2
PW3
PW4
PW5
PW6
PW7
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
Port P
PJ7
SCL
IIC
SDA
RxCAN
CAN4
TxCAN
PWM
Port J
PJ6
Interrupt Logic
PJ0
PJ1
Interrupt Logic
Port H
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
Port S
Port Integration Module
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
Figure 24 PIM_9DP256 Block Diagram
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External Pin Descriptions
All ports start up as general purpose inputs on reset.
80 Pin QFP bond-out version
In case the port pins are not bonded out in the chosen package the user
should initialize the registers to be inputs with enabled pull resistance to
avoid excess current consumption. This applies to the following pins:
•
All port K and H.
•
Port PP6, PJ1–0, PM7–4.
•
PAD15–8. The A/D converter associated with those pins (ATD1)
should be disabled.
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Register Map
Register Map
Register name
Bit 7
6
5
4
3
2
1
Bit 0
Addr.
Offset
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
$0000
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
PTT
Read:
PTT7
Write:
PTIT
Read: PTIT7
Write:
DDRT
Read:
DDRT7
Write:
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0 $0002
RDRT
Read:
RDRT7
Write:
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0 $0003
PERT
Read:
PERT7
Write:
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0 $0004
PPST
Read:
PPST7
Write:
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0 $0005
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
PTS
Read:
PTS7
Write:
PTIS
Read: PTIS7
Write:
$0001
$0006
$0007
$0008
$0009
DDRS
Read:
DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 $000A
Write:
RDRS
Read:
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 $000B
Write:
PERS
Read:
PERS7
Write:
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0 $000C
= Unimplemented or reserved
Figure 25 PIM_912DP256 Register Map
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Port Integration Module
Register name
PPSS
WOMS
Unimplemented
Bit 7
Read:
PPSS7
Write:
6
5
4
3
2
1
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
Bit 0
Addr.
Offset
PPSS0 $000D
Read:
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 $000E
Write:
Read:
Write:
0
PTM
Read:
PTM7
Write:
PTIM
Read: PTIM7
Write:
0
0
0
0
0
0
0
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
$000F
$0010
$0011
DDRM
Read:
DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 $0012
Write:
RDRM
Read:
RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 $0013
Write:
PERM
Read:
PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 $0014
Write:
PPSM
Read:
PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 $0015
Write:
WOMM
Read:
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 $0016
Write:
Unimplemented
Read:
Write:
0
PTP
Read:
PTP7
Write:
PTIP
Read: PTIP7
Write:
0
0
0
0
0
0
0
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
$0017
$0018
$0019
= Unimplemented or reserved
Figure 25 PIM_912DP256 Register Map
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Register Map
Register name
Bit 7
6
5
4
3
2
1
Bit 0
Addr.
Offset
DDRP
Read:
DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 $001A
Write:
RDRP
Read:
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 $001B
Write:
PERP
Read:
PERP7
Write:
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0 $001C
PPSP
Read:
PPSP7
Write:
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0 $001D
PIEP
Read:
PIEP7
Write:
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0 $001E
PIFP
Read:
PIFP7
Write:
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
$001F
PTH
Read:
PTH7
Write:
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
$0020
PTIH
Read: PTIH7
Write:
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
$0021
DDRH
Read:
DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 $0022
Write:
RDRH
Read:
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 $0023
Write:
PERH
Read:
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 $0024
Write:
PPSH
Read:
PPSH7
Write:
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0 $0025
PIEH
Read:
PIEH7
Write:
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
$0026
PIFH
Read:
PIFH7
Write:
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
$0027
= Unimplemented or reserved
Figure 25 PIM_912DP256 Register Map
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Port Integration Module
Register name
Bit 7
PTJ
Read:
PTJ7
Write:
PTIJ
Read: PTIJ7
Write:
6
PTJ6
PTIJ6
DDRJ
Read:
DDRJ7
Write:
DDRJ6
RDRJ
Read:
RDRJ7
Write:
RDRJ6
PERJ
Read:
PERJ7
Write:
PERJ6
PPSJ
Read:
PPSJ7
Write:
PPSJ6
PIEJ
Read:
PIEJ7
Write:
PIEJ6
PIFJ
Read:
PIFJ7
Write:
PIFJ6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit 0
Addr.
Offset
PTJ1
PTJ0
$0028
PTIJ1
PTIJ0
$0029
DDRJ1
DDRJ0 $002A
RDRJ1
RDRJ0 $002B
PERJ1
PERJ0 $002C
PPSJ1
PPSJ0 $002D
PIEJ1
PIEJ0
$002E
PIFJ1
PIFJ0
$002F
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
$0030
$0031
$0032
$0033
$0034
= Unimplemented or reserved
Figure 25 PIM_912DP256 Register Map
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Port Integration Module
Register Map
Register name
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Unimplemented
Read:
Write:
0
0
0
0
0
0
0
0
Addr.
Offset
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
= Unimplemented or reserved
Figure 25 PIM_912DP256 Register Map
NOTE:
Register Address = Base Address + Address Offset, where the Base
Address is defined at the MCU level and the Address Offset is defined
at the module level.
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Port Integration Module
Register Descriptions
The following table summarizes the effect on the various configuration
bits, data direction (DDR), output level (I/O), reduced drive (RDR), pull
enable (PE), polarity select (PS) and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt
is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Table 42 Pin Configuration Summary
DDR
IO
RDR
PE
PS
IE(1)
Function
Pull Device
Interrupt
0
X
X
0
X
0
Input
Disabled
Disabled
0
X
X
1
0
0
Input
Pull Up
Disabled
0
X
X
1
1
0
Input
Pull Down
Disabled
0
X
X
0
0
1
Input
Disabled
falling edge
0
X
X
0
1
1
Input
Disabled
rising edge
0
X
X
1
0
1
Input
Pull Up
falling edge
0
X
X
1
1
1
Input
Pull Down
rising edge
1
0
0
X
X
0
Output, full drive to 0
Disabled
Disabled
1
1
0
X
X
0
Output, full drive to 1
Disabled
Disabled
1
0
1
X
X
0
Output, reduced drive to 0
Disabled
Disabled
1
1
1
X
X
0
Output, reduced drive to 1
Disabled
Disabled
1
0
0
X
0
1
Output, full drive to 0
Disabled
falling edge
1
1
0
X
1
1
Output, full drive to 1
Disabled
rising edge
1
0
1
X
0
1
Output, reduced drive to 0
Disabled
falling edge
1
1
1
X
1
1
Output, reduced drive to 1
Disabled
rising edge
1. Applicable only on port P, H and J.
NOTE:
All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
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Register Descriptions
Port T I/O
Register (PTT)
Address Offset: $0000
Read:
Write:
ECT:
Bit 7
6
5
4
3
2
1
Bit 0
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
I/OC7
I/OC6
I/OC5
I/OC4
I/OC3
I/OC2
I/OC1
I/OC0
0
0
0
0
0
0
0
0
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
Port T Input
Register (PTIT)
Address Offset: $0001
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
-
-
-
-
-
-
-
-
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
This register always reads back the status of the associated pins. This
can also be used to detect overload or short circuit conditions on output
pins.
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Port T Data
Direction Register
(DDRT)
Address Offset: $0002
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port
associated with an enabled output compare. In these cases the data
direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the
associated timer output compare is disabled.
The timer input capture always monitors the state of the pin.
DDRT[7:0] — Data Direction Port T
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTT or PTIT registers, when
changing the DDRT register.
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Register Descriptions
Port T Reduced
Drive Register
(RDRT)
Address Offset: $0003
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port T output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRT[7:0] — Reduced Drive Port T
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Port T Pull Device
Enable Register
(PERT)
Address Offset: $0004
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input. This bit has no effect if the port is
used as output. Out of reset no pull device is enabled.
PERT[7:0] — Pull Device Enable Port T
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
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Port Integration Module
Port T Polarity
Select Register (PPST)
Address Offset: $0005
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is
connected to the pin.
PPST[7:0] — Pull Select Port T
1 = A pull-down device is connected to the associated port T pin, if
enabled by the associated bit in register PERT and if the port
is used as input.
0 = A pull-up device is connected to the associated port T pin, if
enabled by the associated bit in register PERT and if the port
is used as input.
Port S I/O Register
(PTS)
Address Offset: $0008
Read:
Write:
SPI/SCI:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
SS0
SCK0
MOSI0
MISO0
TxD1
RxD1
TxD0
RxD0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
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Port Integration Module
Register Descriptions
The SPI pins (PS[7:4]) configuration is determined by several status bits
in the SPI module. See Serial Peripheral Interface (SPI) section for
details.
The SCI ports associated with transmit pins 3 and 1 are configured as
outputs if the transmitter is enabled.
The SCI pins associated with receive pins 2 and 0 are configured as
inputs if the receiver is enabled. See Serial Communications Interface
(SCI) section for details.
Port S Input
Register (PTIS)
Address Offset: $0009
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
-
-
-
-
-
-
-
-
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
This register always reads back the status of the associated pins. This
also can be used to detect overload or short circuit conditions on output
pins.
Port S Data
Direction Register
(DDRS)
Address Offset: $000A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
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This register configures each port S pin as either input or output.
If SPI is enabled, the SPI determines the pin direction. For details see
Serial Peripheral Interface (SPI) section.
If the associated SCI transmit or receive channel is enabled this register
has no effect on the pins. The pin is forced to be an output if a SCI
transmit channel is enabled, it is forced to be an input if the SCI receive
channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the
associated channel is disabled.
DDRS[7:0] — Data Direction Port S
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTS or PTIS registers, when changing
the DDRS register.
Port S Reduced
Drive Register
(RDRS)
Address Offset: $000B
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRS[7:0] — Reduced Drive Port S
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
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Register Descriptions
Port S Pull Device
Enable Register
(PERS)
Address Offset: $000C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
1
1
1
1
1
1
1
1
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input or as output in wired-or (open drain)
mode. This bit has no effect if the port is used as push-pull output. Out
of reset a pull-up device is enabled.
PERS[7:0] — Pull Device Enable Port S
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
Port S Polarity
Select Register
(PPSS)
Address Offset: $000D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is
connected to the pin.
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PPSS[7:0] — Pull Select Port S
1 = A pull-down device is connected to the associated port S pin, if
enabled by the associated bit in register PERS and if the port
is used as input.
0 = A pull-up device is connected to the associated port S pin, if
enabled by the associated bit in register PERS and if the port
is used as input or as wired-or output.
Port S Wired-Or
Mode Register
(WOMS)
Address Offset: $000E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-or. If enabled the output
is driven active low only (open-drain). A logic level of ‘1’ is not driven. It
applies also to the SPI and SCI outputs and allows a multipoint
connection of several serial modules. This bit has no influence on pins
used as inputs.
WOMS[7:0] — Wired-Or Mode Port S
1 = Output buffers operate as open-drain outputs.
0 = Output buffers operate as push-pull outputs.
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Register Descriptions
Port M I/O
Register (PTM)
Address Offset: $0010
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
RxCAN3
TxCAN2
RxCAN2
TxCAN1
RxCAN1
TxCAN0
RxCAN0
TxBDLC
RxBDLC
0
0
CAN: TxCAN3
J1850:
Reset:
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
The CAN function (TxCAN and RxCAN) takes precedence over the
general purpose I/O function if the associated CAN module is enabled.
See MSCAN section.
The BDLC function takes precedence over the general purpose I/O
function associated with if enabled. See Byte Data Link Controller
Module section.
If both CAN0 and BDLC are enabled the CAN functionality takes
precedence.
Port M Input
Register (PTIM)
Address Offset: $0011
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
-
-
-
-
-
-
-
-
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
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This register always reads back the status of the associated pins. This
can also be used to detect overload or short circuit conditions on output
pins.
Port M Data
Direction Register
(DDRM)
Address Offset: $0012
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN/BDLC forces the I/O state to be an output for each port line
associated with an enabled output (TxCAN[3:0], TxBDLC). It also forces
the I/O state to be an input for each port line associated with an enabled
input (RxCAN[3:0], RxBDLC). In those cases the data direction bits will
not change.
The DDRM bits revert to controlling the I/O direction of a pin when the
associated peripheral module is disabled.
DDRM[7:0] — Data Direction Port M
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTM or PTIM registers, when changing
the DDRM register.
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Register Descriptions
Port M Reduced
Drive Register
(RDRM)
Address Offset: $0013
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port M output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRM[7:0] — Reduced Drive Port M
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Port M Pull Device
Enable Register
(PERM)
Address Offset: $0014
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input or wired-or output. This bit has no
effect if the port is used as push-pull output. Out of reset no pull device
is enabled.
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PERM[7:0] — Pull Device Enable Port M
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
Port M Polarity
Select Register
(PPSM)
Address Offset: $0015
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is
connected to the pin. If CAN is active a pull-up device can be activated
on the RxCAN[3:0] inputs, but not a pull-down. If BDLC is active a
pull-down device can be activated on the RxBDLC pin but not a pull-up.
PPSM[7:0] — Pull Select Port M
1 = A pull-down device is connected to the associated port M pin,
if enabled by the associated bit in register PERM and if the port
is used as a general purpose or BDLC input but not as RxCAN.
0 = A pull-up device is connected to the associated port M pin, if
enabled by the associated bit in register PERM and if the port
is used as general purpose or RxCAN input but not as BDLC.
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Register Descriptions
Port M Wired-Or
Mode Register
(WOMM)
Address Offset: $0016
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
WOMM7
WOMM6
WOMM5
WOMM4
WOMM3
WOMM2
WOMM1
WOMM0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-or. If enabled the output
is driven active low only (open-drain). A logic level of ‘1’ is not driven. It
applies also to the CAN and BDLC outputs and allows a multipoint
connection of several serial modules. This bit has no influence on pins
used as inputs.
WOMM[7:0] — Wired-Or Mode Port M
1 = Output buffers operate as open-drain outputs.
0 = Output buffers operate as push-pull outputs.
Port P I/O Register
(PTP)
Address Offset: $0018
Bit 7
6
5
4
3
2
1
Bit 0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PWM:
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SPI:
SCK2
SS2
MOSI2
MISO2
SS1
SCK1
MOSI1
MISO1
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
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read.
The PWM function takes precedence over the general purpose I/O
function if the associated PWM channel is enabled. While channels 6–0
are output only if the respective channel is enabled, channel 7 can be
PWM output or input if the shutdown feature is enabled. See Chapter
PWM.
The SPI function takes precedence over the general purpose I/O
function associated with if enabled. See Chapter SPI.
If both PWM and SPI are enabled the PWM functionality takes
precedence.
Port P Input
Register (PTIP)
Address Offset: $0019
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
-
-
-
-
-
-
-
-
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
This register always reads back the status of the associated pins. This
can be also used to detect overload or short circuit conditions on output
pins.
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Port Integration Module
Register Descriptions
Port P Data
Direction Register
(DDRP)
Address Offset: $001A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register
has no effect on the pins.
The PWM forces the I/O state to be an output for each port line
associated with an enabled PWM7–0 channel. Channel 7 can force the
pin to input if the shutdown feature is enabled.
If a SPI module is enabled, the SPI determines the pin direction. For
details see SPI specification.
The DDRM bits revert to controlling the I/O direction of a pin when the
associated PWM channel is disabled.
DDRP[7:0] — Data Direction Port P
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTP or PTIP registers, when changing
the DDRP register.
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Port P Reduced
Drive Register (RDRP)
Address Offset: $001B
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port P output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRP[7:0] — Reduced Drive Port P
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Port P Pull Device
Enable Register
(PERP)
Address Offset: $001C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input. This bit has no effect if the port is
used as output. Out of reset no pull device is enabled.
PERP[7:0] — Pull Device Enable Port P
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
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Register Descriptions
Port P Polarity
Select Register
(PPSP)
Address Offset: $001D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if
enabled.
PPSP[7:0] — Polarity Select Port P
1 = Rising edge on the associated port P pin sets the associated
flag bit in the PIFP register.
A pull-down device is connected to the associated port P pin,
if enabled by the associated bit in register PERP and if the port
is used as input.
0 = Falling edge on the associated port P pin sets the associated
flag bit in the PIFP register.
A pull-up device is connected to the associated port P pin, if
enabled by the associated bit in register PERP and if the port
is used as input.
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Port P Interrupt
Enable Register
(PIEP)
Address Offset: $001E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive
external interrupt associated with port P.
PIEP[7:0] — Interrupt Enable Port P
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
Port P Interrupt
Flag Register (PIFP)
Address Offset: $001F
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could
be a rising or a falling edge based on the state of the PPSP register. To
clear this flag, write ‘1’ to the corresponding bit in the PIFP register.
Writing a ‘0’ has no effect.
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Register Descriptions
PIFP[7:0] — Interrupt Flags Port P
1 = Active edge on the associated bit has occurred (an interrupt will
occur if the associated enable bit is set).
Writing a ‘1’ clears the associated flag.
0 = No active edge pending.
Writing a ‘0’ has no effect.
Port H I/O Register
(PTH)
Address Offset: $0020
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
Port H Input
Register (PTIH)
Address Offset: $0021
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
-
-
-
-
-
-
-
-
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
This register always reads back the status of the associated pins. This
can also be used to detect overload or short circuit conditions on output
pins.
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Port H Data Direction
Register (DDRH)
Address Offset: $0022
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
DDRH[7:0] — Data Direction Port H
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTH or PTIH registers, when changing
the DDRH register.
Port H Reduced Drive
Register (RDRH)
Address Offset: $0023
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port H output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRH[7:0] — Reduced Drive Port H
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
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Register Descriptions
Port H Pull Device
Enable Register
(PERH)
Address Offset: $0024
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input. This bit has no effect if the port is
used as output. Out of reset no pull device is enabled.
PERH[7:0] — Pull Device Enable Port H
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
Port H Polarity
Select Register
(PPSH)
Address Offset: $0025
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if
enabled.
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PPSH[7:0] — Polarity Select Port H
1 = Rising edge on the associated port H pin sets the associated
flag bit in the PIFH register.
A pull-down device is connected to the associated port H pin,
if enabled by the associated bit in register PERH and if the port
is used as input.
0 = Falling edge on the associated port H pin sets the associated
flag bit in the PIFH register.
A pull-up device is connected to the associated port H pin, if
enabled by the associated bit in register PERH and if the port
is used as input.
Port H Interrupt
Enable Register
(PIEH)
Address Offset: $0026
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive
external interrupt associated with port H.
PIEH[7:0] — Interrupt Enable Port H
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
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Register Descriptions
Port H Interrupt
Flag Register
(PIFH)
Address Offset: $0027
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
0
0
0
0
0
0
0
0
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could
be a rising or a falling edge based on the state of the PPSH register. To
clear this flag, write ‘1’ to the corresponding bit in the PIFH register.
Writing a ‘0’ has no effect.
PIFH[7:0] — Interrupt Flags Port H
1 = Active edge on the associated bit has occurred (an interrupt will
occur if the associated enable bit is set).
Writing a ‘1’ clears the associated flag.
0 = No active edge pending.
Writing a ‘0’ has no effect.
Port J I/O
Register (PTJ)
Address Offset: $0028
Read:
Write:
Bit 7
6
PTJ7
PTJ6
CAN: TxCAN4
IIC:
Reset:
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
PTJ1
PTJ0
0
0
RxCAN4
SCL
SDA
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
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If the data direction bits of the associated I/O pins are set to 1, a read
returns the value of the port register, otherwise the value at the pins is
read.
The CAN function (TxCAN and RxCAN) takes precedence over the
general purpose I/O function if the associated CAN module is enabled.
See Chapter CAN.
The IIC function takes precedence over the general purpose I/O function
associated with if enabled.
If both CAN4 and IIC are enabled the CAN functionality takes
precedence. See Chapter IIC.
If the IIC module is enabled the SDA and SCL outputs are configured as
open-drain outputs.
Port J Input
Register (PTIJ)
Address Offset: $0029
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PTIJ7
PTIJ6
0
0
0
0
PTIJ1
PTIJ0
–
–
0
0
0
0
-
–
Write:
Reset:
= Reserved or unimplemented
Read: Anytime.
Write: Never; writes to this register have no effect.
This register always reads back the status of the associated pins. This
can be used to detect overload or short circuit conditions on output pins.
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Register Descriptions
Port J Data
Direction Register
(DDRJ)
Address Offset: $002A
Read:
Write:
Reset:
Bit 7
6
DDRJ7
DDRJ6
0
0
5
4
3
2
0
0
0
0
–f
–f
–f
–f
1
Bit 0
DDRJ1
DDRJ0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TxCAN4) and an
input on pin PJ6 (RxCAN4). The IIC forces the I/O state to be an output
or input dependent on the state of the IIC bus if enabled. In these cases
the data direction bits will not change. The DDRJ bits revert to controlling
the I/O direction of a pin when the associated timer output compare is
disabled.
DDRJ[7:6][1:0] — Data Direction Port J
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTJ or PTIJ registers, when changing
the DDRJ register.
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Port J Reduced Drive
Register (RDRJ)
Address Offset: $002B
Read:
Write:
Reset:
Bit 7
6
RDRJ7
RDRJ6
0
0
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
RDRJ1
RDRJ0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as
either full or reduced. If the port is used as input this bit is ignored.
RDRJ[7:6][1:0] — Reduced Drive Port J
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Port J Pull Device
Enable Register (PERJ)
Address Offset: $002C
Read:
Write:
Reset:
Bit 7
6
PERJ7
PERJ6
1
1
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
PERJ1
PERJ0
1
1
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is
activated, if the port is used as input or as wired-or output. This bit has
no effect if the port is used as push-pull output. Out of reset a pull-up
device is enabled.
PERJ[7:6][1:0] — Pull Device Enable Port J
1 = Either a pull-up or pull-down device is enabled.
0 = Pull-up or pull-down device is disabled.
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Register Descriptions
Port J Polarity
Select Register
(PPSJ)
Address Offset: $002D
Read:
Write:
Reset:
Bit 7
6
PPSJ7
PPSJ6
0
0
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
PPSJ1
PPSJ0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if
enabled.
PPSJ[7:6][1:0] — Polarity Select Port H
1 = Rising edge on the associated port J pin sets the associated
flag bit in the PIFJ register.
A pull-down device is connected to the associated port J pin, if
enabled by the associated bit in register PERJ and if the port
is used as input.
0 = Falling edge on the associated port J pin sets the associated
flag bit in the PIFJ register.
A pull-up device is connected to the associated port J pin, if
enabled by the associated bit in register PERJ and if the port
is used as general purpose input, general purpose output in
wired-or configuration or as IIC port.
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Port J Interrupt
Enable Register
(PIEJ)
Address Offset: $002E
Read:
Write:
Reset:
Bit 7
6
PIEJ7
PIEJ6
0
0
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
PIEJ1
PIEJ0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive
external interrupt associated with port J.
PIEJ[7:6][1:0] — Interrupt Enable Port J
1 = Interrupt is enabled.
0 = Interrupt is disabled (interrupt flag masked).
Port J Interrupt Flag
Register (PIFJ)
Address Offset: $002F
Read:
Write:
Reset:
Bit 7
6
PIFJ7
PIFJ6
0
0
5
4
3
2
0
0
0
0
0
0
0
0
1
Bit 0
PIFJ1
PIFJ0
0
0
= Reserved or unimplemented
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could
be a rising or a falling edge based on the state of the PPSJ register. To
clear this flag, write ‘1’ to the corresponding bit in the PIFJ register.
Writing a ‘0’ has no effect.
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Reset Initialization
PIFH[7:6][1:0] — Interrupt Flags Port J
1 = Active edge on the associated bit has occurred (an interrupt will
occur if the associated enable bit is set).
Writing a ‘1’ clears the associated flag.
0 = No active edge pending.
Writing a ‘0’ has no effect.
Reset Initialization
All registers including the data registers get set/reset asynchronously.
Functional Description
General
Each pin can act as general purpose I/O. In addition the pin can act as
an output from a peripheral module or an input to a peripheral module.
A set of configuration registers is common to all ports. All registers can
be written at any time, however a specific configuration might not
become active.
Example:
Selecting a pull-up resistor. This resistor does not become active while
the port is used as a push-pull output.
I/O register
This register holds the value driven out to the pin if the port is used as a
general purpose I/O. Writing to this register has only an effect on the pin
if the port is used as general purpose output. When reading this address,
the value of the pins is returned if the data direction register bits are set
to 0. If the data direction register bits are set to 1, the contents of the I/O
register is returned. This is independent of any other configuration.
Input register
This is a read-only register and always returns the value of the pin.
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Data direction
register
This register defines whether the pin is used as an input or an output. If
a peripheral module controls the pin the contents of the data direction
register is ignored.
PTI
0
PT
1
0
I/O
PAD
1
0
DDR
1
MOD
do
obe
mod_en
Figure 26 Illustration of I/O pin functionality
Reduced drive
register
If the port is used as an output the register allows the configuration of the
drive strength.
Pull device enable
register
This register turns on a pull-up or pull-down device. It becomes only
active if the pin is used as an input or as a wired-or output.
Polarity select
register
This register selects either a pull-up or pull-down device if enabled. It
becomes only active if the pin is used as an input. A pull-up device can
be activated if the pin is used as a wired-or output.
Port T
This port is associated with the Enhanced Capture Timer module. In all
modes, port T pins PT[7:0] can be used for either general-purpose I/O,
or with the channels of the Enhanced Capture Timer. During reset, port
T pins are configured as high-impedance inputs.
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Functional Description
Port S
This port is associated with the serial SCI and SPI modules. In all modes,
port S pins PS[7:0] can be used either for general-purpose I/O, or with
the SCI and SPI subsystems. During reset, port S pins are configured as
inputs with pull-up.
Port M
This port is associated with the J1850 and 4 CAN modules. In all modes,
port M pins PM[7:0] can be used for either general purpose I/O, or with
the CAN and J1850 subsystems. Pins PM0 and PM1 are shared
between the CAN0 and the BDLC (J1850) module. If CAN0 is enabled
the pins become CAN transmit and receive pins. If BLDC is enabled and
CAN0 is disabled, pins become active BDLC transmit and receive pins.
During reset, port M pins are configured as high-impedance inputs.
Port P
This port is associated with the PWM and 2 SPI modules. In all modes,
port P pins PP[7:0] can be used for either general purpose I/O, or with
the PWM and SPI subsystems. The pins are shared between the PWM
channels and the SPI1 and SPI2 modules. If the PWM is enabled the
pins become PWM output channels with the exception of pin 7 which can
be PWM input or output. If SPI1 or SPI2 are enabled and PWM is
disabled, the respective pin configuration is determined by several
status bits in the SPI modules. During reset, port P pins are configured
as high-impedance inputs.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-or
fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All 8 bits/pins
share the same interrupt vector. Interrupts can be used with the pins
configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and
its corresponding port interrupt enable bit are both set.
This external interrupt feature is capable to wake up the CPU when it is
in STOP or WAIT mode.
A digital filter on each pin prevents pulses shorter than a specified time
from generating an interrupt (see Pulse Detection Criteria). Four
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consecutive samples have to be either low or high in order to detect a
valid low or high input.
The filters are continuously clocked by the bus clock in RUN and WAIT
mode. In STOP mode the clock is generated by a single RC oscillator in
the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Active level at the input as defined by the port polarity select register
(PPS)
and port interrupt enabled (PIE=1)
and port interrupt flag not set (PIF=0).
Glitch, Filtered out, no Interrupt Flag setting
Valid Pulse, Interrupt flag set
tifmin
tifmax
Figure 27 Interrupt Glitch Filter on Port P, H and J
Table 43 Pulse Detection Criteria
Mode
tif
Unit
tpulse <= 3
Ignored
Uncertain
Valid
STOP(1)
STOP
Pulse
3 < tpulse
bus clocks
<4
bus clocks
tpulse >= 4
bus clocks
tif
Unit
tpulse <= 3.2
µs
< 10
µs
tpulse >= 10
µs
3.2 < tpulse
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
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Low Power Options
tpulse
Figure 28 Pulse Illustration
Port H
Port H offers 8 I/O ports with the same interrupt features as port P.
Port J
This port is associated with the fifth CAN and the IIC module. In all
modes, port J pins PJ[7:6] and PJ[1:0] can be used for either general
purpose I/O, or with the CAN and IIC subsystems. Pins PJ6 and PJ7 are
shared between the CAN4 and the IIC module. If CAN4 is enabled the
pins become CAN transmit and receive pins. If IIC is enabled and CAN4
is disabled, the pins become IIC open-drain output pins. During reset,
port J pins are configured as inputs with pull-up.
Port J offers 4 I/O ports with the same interrupt features as port P.
Low Power Options
Run Mode
No low power options exist for this module in run mode.
Wait Mode
No low power options exist for this module in wait mode.
Stop Mode
All clocks are stopped. There are however asynchronous paths to
generate interrupts from STOP on port P, H and J.
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Interrupt Operation
Port P, H and J generate a separate edge sensitive interrupt if enabled.
Interrupt Sources
Table 44 Port Integration Module Interrupt Sources
NOTE:
Recovery from
STOP
Interrupt Source
Interrupt Flag
Local Enable
Global (CCR)
Mask
Port P
PIFP[7:0]
PIEP[7:0]
I Bit
Port H
PIFH[7:0]
PIEH[7:0]
I Bit
Port J
PIFJ[7:6][1:0]
PIFJ[7:6][1:0]
I Bit
Vector addresses and their relative interrupt priority are determined at
the MCU level.
This module can generate wake-up interrupts from STOP on port P, H
and J. For other sources of external interrupts refer to the respective
module specification.
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