Does FPGA-based prototyping really have to be this difficult?

Does FPGA-based prototyping really have to be this difficult?
Embedded Conference Finland
Andrew Marshall
May 2017
What is FPGA-Based Prototyping?
• Primary platform for pre-silicon software
development and validation
• Maps a digital ASIC, ASSP, SoC design or part thereof
into one or more FPGAs
• Allows SW to simulate in real world
environments
• Provides pre-silicon execution speeds in MHz
• Enables connectivity to real peripherals
• Runs real world traffic flows including interrupts and
unpredictable events
• Runs error conditions and handling errata with other system
components
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FPGA-Based Prototyping as part of your verification solution
• Ever-increasing verification requirements driven by growing hardware and software complexity
• Fast time to results is essential to ensure projects can meet schedules
Main core engine usage
• Right tools for the right job: Combination of formal, simulation, emulation and FPGA prototyping
FPGA Prototyping
…
Emulation
…
Simulation
…
Formal
Project timeline
3
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…
Tapeout
Silicon
FPGA-based prototyping is hard to do
Interfaces
Clocking
Debug
4
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Memories
Software
Really, really hard to do
FPGA-based prototyping has become the methodology of choice for early software
development.
BUT …
Prototyping implementation and bring-up takes too long and there has, so far, not been any
easy transition from simulation and emulation into FPGA-based prototyping.
4-6 weeks
RTL
preparation
Memory
remodeling
Compile
Synthesis
4-6 weeks
4 weeks
2 weeks
Automatic / manual
Multi-FPGA partitioning
FPGA timing closure (P&R)
In-circuit
bring-up
3 months … and more!
5
© 2017 Cadence Design Systems, Inc. All rights reserved.
Or is it?
Protium S1 – Addressing the prototyping challenges
RTL
preparation
Memory
remodeling
Compile
Synthesis
Automatic / manual
Multi-FPGA partitioning
Functional model validation
In-circuit
bring-up
▲
Traditional
◄ Protium™ S1
• No RTL modifications needed
– Clocking / number of clocks
– Automated memory compilation and modeling
• Fully automatic, multi-FPGA partitioning
– Optional manual optimization
6
© 2017 Cadence Design Systems, Inc. All rights reserved.
• Pre-FPGA P&R model validation
– Multiple design integrations per day
– Avoids time-consuming FPGA P&R
• Fully integrated FPGA P&R
– Automatic constraint generation
– Guaranteed P&R success
Advanced clocking – any type and number
• Traditional imitations:
–
–
–
–
–
Gated clock, multiplexed clocks
# of clocks
Difficult to achieve FPGA timing closure
Long iteration times / long FPGA P&R times
Unpredictable results & prototype behavior
Clock distribution on the board
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Clock generation in the FPGA
© 2017 Cadence Design Systems, Inc. All rights reserved.
• Protium™ benefits:
–
–
–
–
–
No hold-time violations in user clock domains
Removes any FPGA-specific clock limitations
Supports unlimited # of design clocks
Improves FPGA timing closure
Accelerates FPGA P&R times
Comprehensive memory support
• FPGA built in & XSRAM
– Benefits:
– Automatic mapping of any memory type
– Support for multi-port memories
– Support for backdoor upload/download
– XSRAM adds:
– Increases FPGA internal memory from 80Mbits to 128MBytes
• XDRAM
– Benefits:
–
–
–
–
–
Adds DDRx bulk memories
Supports LPDDR2/3/4; DDR3/4; HBM
No change to design memory controller and firmware
Support for backdoor upload/download
Acts as memory speed bridge (timing, refresh, etc.)
Protium FPGA X
XDRAM Board
DUT DDRn
Controller
DDRn
I/f
Logic
DDR3
Ctrl
UD Module
Upload/Download
• Directly Connected or Full Custom
– Daughter cards available for more custom approaches if required
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© 2017 Cadence Design Systems, Inc. All rights reserved.
K7
S
O
D
I
M
M
Hardware and software debug
Software
Applications
Middleware
Operating Systems (OS)
Drivers
Firmware / HAL
• Waveforms across partitions
• Backdoor memory access
SoC, Sub-System or IP
• Design-centric view vs. FPGA-centric
ARM V8 CPUSubsystem
• Force/release
Cortex Cortex
Cortex Cortex
-A57 A57
Compute
-A53 -A53
• Predefined signals (at compile time) to “0”
or “1” during runtime
• Monitor signal
L2 cache
L2
cache
Sub
System
Boot
Customer’s
Modem
3D
DSP
processo
Application-Specific
GFX
A/V
r Components
ARM M0
Cache coherent fabric
SoC interconnect fabric
DDR
3
• Real-time monitoring of predefined (at
compile time) signals
• Quickly change boot code, software, etc.
Application Specific Components
PHY
USB3.0
PCIe
Gen 2,3
Ethe
r
net
HDMI
GPI
O
UAR
T
INTC
High Speed,
GeneralPMU
I2C
MIPI
Low-Speed
3.
2.
Wired
Purpose
0
0 Interface
MIPI
SPI
WLAN
PHY
PHY
Peripherals
JTA
Time
Low-speed
peripheral
Peripherals
Peripherals
LTE
G
r
subsystem
P
H
Y
SATA
Display
P
H
Y
High speed, wired interface peripherals
Other peripherals
Low speed peripherals
• Clock control
• Start/stop the clock on demand
• Fully scriptable runtime environment
• Remote access
• Network resource anytime from anywhere
• High-performance link to software model
Hardware Debug: RTL
Software Debug: C Code
Probes
9
JTAG
UART – to peripherals
© 2017 Cadence Design Systems, Inc. All rights reserved.
Scalable performance
Performance
(single board, multi-FPGA)
Prototyping
design
100MHz
Automatic mode
Further Optimization
…
Phase 3
Phase 2
10MHz
Phase 1
5MHz
3MHz
10
Automatic
for quick
functionality
© 2017 Cadence Design Systems, Inc. All rights reserved.
Higher effort
performance
optimization
Design-based
user manual
refinement
Fast Time-to-Prototype (TTP)
Networking
“Protium™ has incredibly simplified our prototyping
flow. It allowed us to significantly improve
prototyping bring-up time.”
Riad Ben Mouhoub
PhD/Tech Leader, Microsemi Corporation
◄ 81%
Networking
◄ 85%
Consumer
Traditional
◄ 88%
CPU
ProtiumS1
◄ 91%
Consumer
◄ 89%
Networking
◄ 91%
Mobile
◄ 79%
0
5
10
15
20
25
Bring-up time (weeks)
Note: Sample customer bring-up gains over traditional FPGA-based Prototyping solutions
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© 2017 Cadence Design Systems, Inc. All rights reserved.
30
35
Microsemi @ CDNLive … challenges & requirements
12
© 2017 Cadence Design Systems, Inc. All rights reserved.
… and this is what our customers are saying!
Amlogic @ DAC 2016
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© 2017 Cadence Design Systems, Inc. All rights reserved.
… and Xilinx likes it too
“The Cadence Protium S1 platform ensures scalability to hundreds of software developers at the
earliest possible point during the development flow, and allows developers to focus on design
validation and software development rather than prototype bring-up. The common flow with the
Cadence Palladium Z1 emulation platform enables a smooth transition from emulation to prototyping,
which greatly improves productivity.”
-Peter Ryser, Senior Director for System Software, Integration, and Validation, Xilinx
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© 2017 Cadence Design Systems, Inc. All rights reserved.
Industry’s most comprehensive hardware portfolio
Protium G1
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Protium S1-SC
Protium S1-MC (2H 2017)
Single board
Single chassis system
Multi-chassis configuration
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 FPGA
Up to 25M ASIC gates
Affordable and scalable
Highest performance
Early software development
IP verification
© 2017 Cadence Design Systems, Inc. All rights reserved.
2-8 FPGAs
Up to 200M ASIC gates
Flexible and scalable
Fastest bring-up
Unique SW debug capabilities
Early software development
HW/SW integration
8-24 FPGAs
Up to 600M ASIC gates
Highest capacity
Flexible use modes
Advanced debug
High performance regression
Full system validation
Protium S1 System and Environment
Comprehensive prototyping solution: High-performance and optimized
Software
Multi-Fabric Compiler
Accessories
Debug probes
and trigger
conditions
ASIC RTL
(Verilog / VHDL /
SV)
600MG
B
o
a
r
d
f
i
l
e
M
e
m
o
r
y
c
o
m
p
i
l
e
r
Integrated Compile
Engine
HDL-ICE
for fast
compile
D
e
b
u
g
i
n
s
e
r
t
e
r
Partitioni
ng
Board router
FPGA P&R
FPGA bit files
SpeedBridge®
Interfaces
Hardware
Transaction Interface
Memory Cards
25MG
200MG
Memory Models
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© 2017 Cadence Design Systems, Inc. All rights reserved.
Protium S1 – the Most Efficient Way to Prototype Your ASIC
• Fast time-to-prototyping (months down to weeks)
– No RTL changes
– Automatic partitioning/memory compilation
– Fully integrated FPGA place-and-route
• Scalable performance (3-100MHz)
– From fully automatic to fully manual
– Advanced black-box methodology
• Advanced software debug
– Memory upload/download
– Force and release
– SCE-MI transaction interface
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© 2017 Cadence Design Systems, Inc. All rights reserved.
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