3D Analog Front End: Migrating From

Application Report
SCBA032 – August 2012
3D Analog Front End: Migrating From TMS37122 and
TMS37127 to TMS37126D3
Siegfried Langner .............................................................................................................................
ABSTRACT
The TMS37122, TMS37127 and TMS37126 devices belong to the Passive Entry and Passive Start
(PEPS) product family used mainly for automotive applications. These devices are also usable in industrial
applications for similar functionality.
Since the TMS37122 and TMS37127 devices are becoming obsolete, this application report describes
how to migrate to the TMS37126D3 device as a replacement.
1
2
Contents
Introduction .................................................................................................................. 1
Comparison Overview ...................................................................................................... 2
List of Figures
1
Pin Assignment Comparison .............................................................................................. 2
2
TMS37122 and 127 Wakeup Without Wake Pattern ................................................................... 4
3
126 Wakeup Without Wake Pattern ...................................................................................... 4
4
Wakeup With 8-Bit Wake Pattern (1010 1010) LS-bit First
5
6
7
8
9
10
11
12
...........................................................
TMS37122 (5 Nibbles, 3 Rows) ...........................................................................................
TMS37127 (5 Nibbles, 4 Rows) ...........................................................................................
TMS37126 (5 Bytes, 3 Rows) .............................................................................................
Schematic TMS37122 and TMS37127...................................................................................
Test Interface Pin Assignment TMS37122 and TMS37127 (4 V Level) ............................................
Replacement Schematic for TMS37122 and TMS37127 ..............................................................
Test Interface Pin Assignment TMS37126 (5 V Level) ................................................................
Function Definition Byte B ................................................................................................
5
5
6
6
7
7
8
8
9
List of Tables
1
1
Comparison Table
..........................................................................................................
2
Introduction
The IC consists basically of a three dimensional analog frontend with internal Wake Pattern detection; two
16-bit wake patterns can be freely programmed and a sensitivity threshold assigned for each pattern.
In standby mode, all three channels are active and waiting for an RF field containing the specific
programmed wake pattern. During this phase, the current consumption of the analog frontend is extremely
low and the microcontroller can be put in low-power mode to extend battery life.
The reception of a correct wake pattern is indicated by the wake signal that wakes up the microcontroller
for further communications.
From a functional standpoint, the TMS37126D3 device is a superset of the TMS37122 and TMS37127
devices, but with additional features.
All trademarks are the property of their respective owners.
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1
Comparison Overview
2
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Comparison Overview
Table 1. Comparison Table
Parameter and Function
Unit
TMS37122
TMS37127
TMS37126D3
by Micro
by Micro
yes
3
Embedded passive TRP
functionality
Compatibility
Number of RF inputs
(antennas)
No.
3
3
Antenna inductance (PEPS)
[mH]
2.66 to 10
2.66 to 10
2.66 to 10
√
Antenna inductance ( TRP)
[mH]
2.66
2.66
4.6 and 7.2
no
√√
Sensitivity
√
[mVpp]
5
5
3.7
Wake pattern
No.
A and B
A and B
A and B
√
Wake pattern length
[bit]
16
4, 8, 16
4, 8, 16
no
Adjustable sensitivity steps
No.
16
16
32
√√
-
yes
yes
√
5
5
3.8
√√
Watch dog selectable
Standby current
[μA]
RSSI (current sink)
Programmer
Test interface EEPROM
programming voltage
no
no
yes
no
RI-ACC-PBOX-20
RI-ACC-PBOX-20
PTB2
no
16
16
Internal
Charge
Pump
no
TSSOP 16
pitch0.65mm
TSSOP 16
pitch0.65mm
TSSOP 30
pitch0.5mm
no
no
no
yes
-
[V]
Package
SPI
2.1
Pin Assignment
The gray pins are additional signals that are available on the TMS37126 device.
TSSOP 30
TSSOP 16
1
TDAT
TCLK
30
1
GND
VCL
2
TEN
RF1
29
2
VCCO
RF1
3
RF2
VCL
28
3
RF3
4
nc
nc
27
4
TDAT
TCLK
5
NPOR
AMMOD
26
5
TEN
MOD
6
RF3
GND
25
6
VBAT
TX
7
VCC_CU
RSSI
24
7
EOBA
WDEEN
8
WDEEN
WAKE
23
8
CLKA/M
9
VBAT
BUSY
22
10
VBATI
EOBA
21
11
nc
CLKA/M
20
12
nc
nc
19
13
nc
SPI_SIMO
18
14
MOD
SPI_SOMI
17
15
TX
SPI_CLK
16
RF2
WAKE
TMS37122/127
TMS37126
Figure 1. Pin Assignment Comparison
2
3D Analog Front End: Migrating From TMS37122 and TMS37127 to
TMS37126D3
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Comparison Overview
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2.2
SPI Interface Signals
The TMS37126x devices have an SPI interface for accessing EEPROM memory as well as for using
different functionalities like hardware (HW) encryption or the block check character (BCC) generator.
If the SPI interface is not used, the clock input should be connected to GND in order to avoid spurious
clock pulses (for example, electrostatic discharge).
2.3
Programmer Box
The TMS122 and TMS37127 programmer box cannot be used for TMS37126x. Since the TMS37126 is
equipped with an internal charge pump to program the EEPROM cells, the test interface needs 5 V signal
levels. Probe test box (PTB or PTB2) is used for programming.
2.4
Watchdog
The TMS37127 and TMS37126x both have an integrated watchdog that can be enabled by the
configuration registers. The watchdog is not available in the TMS37122 device.
In case the device operates without Wake Pattern detection, the watchdog resets the device if no clock is
received by the RF inputs.
2.5
Wake Pattern
The TMS37126x can be configured for a 4-, 8-, or 16-bit Wake Pattern.
2.6
Wakeup Without Wake Pattern Detection
The front end can be configured to operate with or without Wake Pattern detection.
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Comparison Overview
2.6.1
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TMS37122 and TMS37127
If a continuous carrier is present for about 2 ms to 5 ms, the device will wake up and set the Wake output
to high (see Figure 2).
A
The EOBA signal (blue trace) is the demodulated LF signal.
Figure 2. TMS37122 and 127 Wakeup Without Wake Pattern
2.6.2
TMS37126
In the TMS37126 device, the wake output is only set high if the continuous LF carrier is switched off and
on again (see Figure 3).
Figure 3. 126 Wakeup Without Wake Pattern
4
3D Analog Front End: Migrating From TMS37122 and TMS37127 to
TMS37126D3
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Comparison Overview
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2.7
Wakeup With Wake Pattern Detection
If the Wake pattern detection is enabled, the behavior of the TMS37126 device is identical to the
TMS37122 and TMS37127 devices (see Figure 4).
Figure 4. Wakeup With 8-Bit Wake Pattern (1010 1010) LS-bit First
2.8
Configuration Memory
Since the TMS37122 and TMS37127 devices have different configurable features, the configuration
memory contains an additional row. One row consists of five Nibbles. The TMS37126 device has 5 bytes
per row.
2.8.1
TMS37122 (5 Nibbles, 3 Rows)
Figure 5 shows the memory configuration of the TMS37122 device.
NIBBLE
2
3
4
Bit 3
Bit 0 Bit 3
NO
CLKA
NO
WIDE3
NO
WIDE2
NO
WAKE
0
0
0
Bit 0 Bit 3
1
PPM THRESHOLD
0
1
1
1
1
1
Bit 0 Bit 3
VWAKE B/ 2/3
1
1
1
1
0
Bit 0 Bit 3
VWAKE B/ 1
1
1
1
1
Bit 0
VWAKE A/ 1
1
1
1
0
C_TELEGR
0
0
0
0
0
0
0
0
PASSIVE ENTRY WAKE PATTERN
0
0
0
0
0
0
0
0
0
0
0
0
C_WAIT
0
0
0
0
0
0
0
0
PASSIVE START WAKE PATTERN
0
0
0
0
0
0
0
0
0
0
0
Bit 3
0
1 ROW
2
Bit 0
Bit 0 Bit 15
Figure 5. TMS37122 (5 Nibbles, 3 Rows)
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Comparison Overview
2.8.2
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TMS37127 (5 Nibbles, 4 Rows)
Figure 6 shows the memory configuration of the TMS37127 device. The TMS37127 has one more row for
configuration than the additional features.
Bit 3
NO
CLKA
VWAKE
SINGLE
NIBBLE
2
3
4
Bit 0 Bit 3
NO
WIDE3
NO
WIDE2
NO
WAKE
1
Bit 0 Bit 3
VWAKE B/ 2/3
PPM THRESHOLD
0
Bit 0 Bit 3
Bit 0 Bit 3
VWAKE B/ 1
Bit 0
VWAKE A/ 1
0
C_TELEGR
PASSIVE ENTRY WAKE PATTERN
1 ROW
C_WAIT
PASSIVE START WAKE PATTERN
2
WDG
ON
BIT_NO.
VWAKE B/ 3
VWAKE B/ 2
VWAKE A/ 3
VWAKE A/ 2
Bit 0 Bit 15
Bit 3
3
Bit 0
Figure 6. TMS37127 (5 Nibbles, 4 Rows)
2.8.3
TMS37126 (5 Bytes, 3 Rows)
Figure 7 shows the memory configuration of the TMS37126 device. The configuration is byte wise
organized in comparison to the TMS37122 and TMS37127. Note that the TMS37122 and TMS37127
programmers cannot be used for the TMS37126 device (also see Section 2.3).
BYTE 3
BYTE 4
ROW 0
INTERNAL USE
BYTE 2
BYTE 1
BYTE 0
AFE CNTR DEF
AFE FUNCTION
DEFINITION B
AFE FUNCTION
DEFINITION A
ROW 1
VWAKE A1
VWAKE A2
VWAKE A3
PE WAKE PATTERN
PE WAKE PATTERN
ROW 2
VWAKE B1
VWAKE B2
VWAKE B3
PS WAKE PATTERN
PS WAKE PATTERN
Figure 7. TMS37126 (5 Bytes, 3 Rows)
6
3D Analog Front End: Migrating From TMS37122 and TMS37127 to
TMS37126D3
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2.9
Principle Schematic TMS37122 and TMS37127
VCC
Figure 8 shows the principle schematic for the wake-up receiver. For details, see the device-specific
reference manual: Spec# 11-07-21-002.
L3
L2
C2
L1
C3
C4
IC2
1
2
3
4
5
6
7
8
TDAT
TEN
EOBA
GND
VCC0
RF3
TDAT
TEN
VBAT
EOBA
CLKA/M
VCL
RF1
RF2
TCLK
MOD
TX
WDEEN
WAKE
16
15
14
13
12
11
10
9
TCLK
WDEEN
WAKE
CBAT
CL
TMS3712x
GND
GND
GND
GND
Figure 8. Schematic TMS37122 and TMS37127
2.9.1
Programmer Box Signal Connections (TMS37122 and TMS37127)
For configuration and resonance tuning (tuning capacitor programming) of the TMS37122 and TMS37127,
the tool RI-ACC-PBOX-20 is used. The programmer supports all necessary signals with a 4 V level and
provides the 16 V EEPROM programming voltage at the TEN input.
Test Interface
CON1
VCL
TCLK
WDEEN
SPARE1
1
3
5
7
2
4
6
8
TDAT
TEN
VBAT
GND
(2x4pin)
Figure 9. Test Interface Pin Assignment TMS37122 and TMS37127 (4 V Level)
For programming the EEPROM cells at the end of the telegram, the TEN signal is switched to 16 V during
programming time.
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Comparison Overview
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2.10 Principle Replacement Schematic
3V
Figure 10 shows the principle schematic for the wake-up receiver. For details, see the device-specific
reference manual: Spec# 11-09-21-046
L2
L3
C2
L1
C3
C1
TMS37126
TDAT
TEN
WDEEN
VBati
CL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TDAT
TCLK
TEN
RF1
RF2
VCL
NPOR
AM_MOD
GND
RF3
RSSI
VCC_CU
WAKE
WDEEN
BUSY
VBAT
VBATI
EOBA
NC1
CLKA/M
NC2
NC6
NC3
NC5
NC4
SPI_SIMO
MOD
SPI_SOMI
TX
SPI_CLK
CBAT
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TCLK
WAKE
EOBA
RAID
CL
GND
GND
GND GND GND
Figure 10. Replacement Schematic for TMS37122 and TMS37127
2.10.1
Programmer Board Signal Connections (TMS37126)
For configuration and resonance tuning (tuning capacitor programming) of the TMS37126, the tool RIACC-PTB2-00 is used. The programmer supports all necessary signals with a 5 V level. The EEPROM
programming voltage is provided internal to the IC.
Test Interface
CON1
VCL
TCLK
WDEEN
SPARE1
1
3
5
7
2
4
6
8
TDAT
TEN
VBAT
GND
(2x4pin)
Figure 11. Test Interface Pin Assignment TMS37126 (5 V Level)
8
3D Analog Front End: Migrating From TMS37122 and TMS37127 to
TMS37126D3
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2.10.2
Function Definition Byte B
Figure 12 shows the content of the Function Definition Byte B located in the Memory Block 2 Byte 1.
BIT 7
NOT USED
DEFAULT = 0
BIT 5
BIT 6
VAR. tWRX ON NO_BACKUP
DEFAULT = 0
DEFAULT = 0
BIT 4
Bit 3
BIT 2
BIT 1
NO_IMMOB
BWM THRESHOLD
DEFAULT = 0
DEFAULT = 0111
BIT 0
NOT AVAILABLE IN TMS37122
Figure 12. Function Definition Byte B
2.11 3D Antenna
Connect the 3D antenna in such a way as to have the lowest mutual coupling between the three channels.
To accomplish that, contact the antenna supplier or test it by interchanging the winding sense. An
indication for high coupling is when the resonance of the already tuned channel is changed after tuning
one of the other channels.
2.12 ESD
For a higher ESD immunity additional ESD protection diodes must be added.
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