Si4730/31-D50 - Silicon Labs

Si4730/31-D50
B ROADCAST AM/FM R ADIO R ECEIVER
Features



 Wide range of ferrite loop sticks and
air loop antennas supported


Cellular handsets
 MP3 players
 Portable navigation

Mobile Internet Devices  Tablets
 USB FM radio
 eBooks

1
20
19
18
17
16
The Si4730/31-D50 is the fourth generation digtial CMOS AM/FM radio receiver
IC from Silicon Labs. The Si4730/31-D50 integrates the complete tuner function
from antenna input to audio output.
Functional Block Diagram
Si473x
AMI
RDS
(Si4731)
LNA
AGC
ADC
AMI 4
13 ROUT
AFC
RCLK
LDO
DFS
12 GND
6
7
8
9
10
11 VA
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
7,272,373;
7,272,375;
7,321,324;
7,355,476;
7,426,376;
7,471,940;
7,339,503; 7,339,504.
DAC
ROUT
DAC
LOUT
CONTROL
INTERFACE
VD
1.62–3.6 V
RST
VA
SEN
AGC
GND
14 LOUT
GND
PAD
DSP
LNA
SCLK
FMI
RFGND 3
GPO/DCLK
LOW-IF
ADC
FM
ANT
DOUT
DIGITAL
AUDIO
SDIO
RFGND
15 DOUT
RST 5
Description
Rev. 1.0 2/11
NC
FMI 2
Applications
2.7– 5.5 V
Si4730/31
RoHS compliant
Not suitable for wall-plugged
consumer electronic applications*
*Note: For consumer electronics applications, use Si4730/31-D60 for worldwide
CE and EN compliance.
AM
ANT
Pin Assignments
 QFN package
DFS

 Integrated LDO regulator
Ordering Information:
See page 26.
GPO3/DCLK

 2-wire and 3-wire control interface
VD

 I2S digital audio out
GPO2/INT

 RDS/RBDS processor (Si4731 only)
RCLK

 Adjustable soft mute control
GPO1

 Volume control
SDIO

 Programmable reference clock
SCLK

 No manual alignment necessary
SEN

(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
Excellent real-world performance
Integrated VCO
Advanced AM/FM seek tuning
AM/FM digital tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable AVC max gain
Programmable de-emphasis
Seven selectable AM channel filters
Advanced audio processing
NC
 Worldwide FM band support
Copyright © 2011 by Silicon Laboratories
Si4730/31-D50
Si4730/31-D50
2
Rev. 1.0
Si4730/31-D50
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.5. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.12. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.13. RDS/RBDS Processor (Si4731 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.14. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.15. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.16. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.17. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.18. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.19. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.20. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.21. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Pin Descriptions: Si4730/31-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1. Si4730/31 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Package Outline: Si4730/31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9. PCB Land Pattern: Si4730/31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.0
3
Si4730/31-D50
1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Analog Supply Voltage
VA
2.7
—
5.5
V
Digital and I/O Supply Voltage
VD
1.62
—
3.6
V
Analog Power Supply Powerup Rise
Time
VARISE
10
—
—
µs
Digital Power Supply Powerup Rise
Time
VDRISE
10
—
—
µs
TA
–20
25
85
C
Ambient Temperature
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Analog Supply Voltage
VA
–0.5 to 5.8
V
Digital and I/O Supply Voltage
VD
–0.5 to 3.9
V
Current3
IIN
10
mA
Input Voltage3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
C
Storage Temperature
TSTG
–55 to 150
C
0.4
VpK
Input
RF Input
Level4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4730/31 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pins FMI and AMI.
4
Rev. 1.0
Si4730/31-D50
Table 3. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
7.5
9.7
mA
FM Mode
VA Supply Current
IFMVA
VD Supply Current
IFMVD
Digital Output Mode1
—
8.5
11.1
mA
VD Supply Current
IFMVD
Analog Output Mode
—
8.4
11.1
mA
AM Mode
VA Supply Current
IAMVA
—
7.5
8.5
mA
1
—
8.5
11.0
mA
—
8.0
10.2
mA
—
4
15
µA
—
3
10
µA
VD Supply Current
IAMVD
Digital Output Mode
VD Supply Current
IAMVD
Analog Output Mode
Powerdown and Interface
VA Powerdown Current
IAPD
VD Powerdown Current
IDOPD
SCLK, RCLK inactive
High Level Input Voltage2
VIH
0.7 x VD
—
VD + 0.3
V
2
VIL
–0.3
—
0.3 x VD
V
High Level Input Current2
IIH
VIN = VD = 3.6 V
–10
—
10
µA
2
IIL
VIN = 0 V,
VD = 3.6 V
–10
—
10
µA
High Level Output Voltage3
VOH
IOUT = 500 µA
0.8 x VD
—
—
V
3
VOL
IOUT = –500 µA
—
—
0.2 x VD
V
Low Level Input Voltage
Low Level Input Current
Low Level Output Voltage
Notes:
1. Guaranteed by characterization.
2. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
3. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4730/31-D50
Table 4. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST
tSRST
100
—
—
µs
GPO1, GPO2/INT Hold from RST
tHRST
30
—
—
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tSRST
RST
tHRST
70%
30%
GPO1
70%
GPO2/
INT
70%
30%
30%
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4730/31-D50
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO  Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO  Hold
(START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK  Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK  Hold4,5
tHD:DAT
0
—
900
ns
SCLK input to SDIO  Setup
(STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
—
250
ns
—
300
ns
Cb
20 + 0.1 ----------1pF
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
Cb
20 + 0.1 ----------1pF
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.0
7
Si4730/31-D50
SCLK
SDIO
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
70%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
STOP
Si4730/31-D50
Table 6. 3-Wire Control Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN
10
—
—
ns
SCLKto SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLKSetup
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tS
SEN
SDIO
tR
tF
70%
tHSDIO
tHIGH
tLOW
tHSEN
tS
30%
70%
30%
A7
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
30%
tHSDIO
tS
SEN
70%
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4730/31-D50
Table 7. Digital Audio Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
DCLK Cycle Time
tDCT
26
—
1000
ns
DCLK Pulse Width High
tDCH
10
—
—
ns
DCLK Pulse Width Low
tDCL
10
—
—
ns
DFS Set-up Time to DCLK Rising Edge
tSU:DFS
5
—
—
ns
DFS Hold Time from DCLK Rising Edge
tHD:DFS
5
—
—
ns
tPD:DOUT
0
—
12
ns
DOUT Propagation Delay from DCLK Falling
Edge
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
10
Rev. 1.0
Si4730/31-D50
Table 8. FM Receiver Characteristics1,2
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
76
—
108
MHz
(S+N)/N = 26 dB
—
2.2
3.5
µV EMF
f = 2 kHz,
RDS BLER < 5%
—
11
—
µV EMF
3
4
5
k
4
5
6
pF
100
105
—
dBµV EMF
m = 0.3
40
50
—
dB
Adjacent Channel Selectivity
±200 kHz
35
50
—
dB
Alternate Channel Selectivity
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
72
80
90
mVRMS
—
—
1
dB
Input Frequency
fRF
Sensitivity3,4,5
RDS
Test Condition
Sensitivity6
LNA Input Resistance6,7
6,7
LNA Input Capacitance
Input IP36,8
AM
Suppression3,4,6,7
Spurious Response Rejection6
3,4,7
Audio Output Voltage
3,7,9
Audio Output L/R Imbalance
Audio Frequency Response Low6
–3 dB
—
—
30
Hz
Audio Frequency Response High6
–3 dB
15
—
—
kHz
35
42
—
dB
55
63
—
dB
—
58
—
dB
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
f = ±400 kHz
—
34
—
dBµV
f = ±4 MHz
—
30
—
dBµV
Audio Stereo Separation
Audio Mono
7,9
S/N3,4,5,7
Audio Stereo S/N4,5,6,7
Audio THD3,7,9
6
De-emphasis Time Constant
3,4,5,6,12,13
Blocking Sensitivity
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
Rev. 1.0
11
Si4730/31-D50
Table 8. FM Receiver Characteristics1,2 (Continued)
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
f = ±400 kHz, ±800 kHz
—
40
—
dBµV
f = ±4 MHz, ±8 MHz
—
35
—
dBµV
RL
Single-ended
10
—
—
k
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV at RF Input
–3
—
3
dB
Intermod Sensitivity3,4,5,6,12,13
Audio Output Load
Resistance6,10
Audio Output Load Capacitance6,10
Seek/Tune Time6
Powerup Time6
14
RSSI Offset
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
12
Rev. 1.0
Si4730/31-D50
Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
64
—
75.9
MHz
—
3.5
—
µV EMF
3
4
5
k
4
5
6
pF
—
105
—
dBµV EMF
m = 0.3
—
50
—
dB
Adjacent Channel Selectivity
±200 kHz
—
50
—
dB
Alternate Channel Selectivity
±400 kHz
—
70
—
dB
Audio Output Voltage3,4,7
72
80
90
mVRMS
Audio Output L/R Imbalance3,7,9
—
—
1
dB
Input Frequency
fRF
Sensitivity3,4,5
LNA Input
Test Condition
(S+N)/N = 26 dB
Resistance7
7
LNA Input Capacitance
Input IP3
8
AM Suppression3,4,7
Audio Frequency Response Low
–3 dB
—
—
30
Hz
Audio Frequency Response High
–3 dB
15
—
—
kHz
Audio Mono S/N3,4,5,7,10
—
63
—
dB
Audio THD3,7,9
—
0.1
—
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
De-emphasis Time Constant
Audio Output Load Resistance10
RL
Single-ended
10
—
—
k
Audio Output Load Capacitance10
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV EMF
–3
—
3
dB
Seek/Tune Time
Powerup Time
11
RSSI Offset
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. At temperature (25 °C).
Rev. 1.0
13
Si4730/31-D50
Table 10. AM Receiver Characteristics1,2
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Input Frequency
Sensitivity
Test Condition
Min
Typ
Max
Unit
520
—
1710
kHz
(S+N)/N = 26 dB
—
25
35
µV EMF
THD < 8%
—
300
—
mVRMS
∆VA = 100 mVRMS, 100 Hz
—
40
—
dB
54
60
67
mVRMS
50
60
—
dB
—
0.1
0.5
%
180
—
450
µH
—
—
110
ms
fRF
3,5,6
Large Signal Voltage Handling6,7
Power Supply Rejection Ratio6
Audio Output Voltage
Symbol
3,8
Audio S/N3,5,8
3,8
Audio THD
Antenna Inductance6,9
6
Powerup Time
From powerdown
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. Analog audio output mode.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
8. VIN = 5 mVrms.
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
14
Rev. 1.0
Si4730/31-D50
Table 11. Reference Clock and Crystal Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
31.130
32.768
40,000
kHz
–100
—
100
ppm
1
—
4095
31.130
32.768
34.406
kHz
—
32.768
—
kHz
–100
—
100
ppm
Board Capacitance
—
—
3.5
pF
ESR
—
40
—

CL Single-ended
—
12
—
pF
Reference Clock
RCLK Supported Frequencies1
RCLK Frequency Tolerance
2
REFCLK_PRESCALE
REFCLK
Crystal Oscillator
Crystal Oscillator Frequency
Crystal Frequency Tolerance2
Notes:
1. The Si4730/31 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
Rev. 1.0
15
Si4730/31-D50
2. Typical Application Schematic
Optional: Digital Audio Out
OPMODE: 0xB0, 0xB5
C9
GPO1
GPO2/INT
R3
GPO3/DCLK
AMI
17
16
ROUT
GND
D50
VA
15
14
LOUT
13
ROUT
12
2.7 to 5.5 V
11
VA
VD
C1
10
6
DOUT
DFS
19
18
GPO2/INT
GPO3/DCLK
LOUT
RSTB
SENB
5
DFS
R1
DOUT
Si473x
RCLK
C3
RFGND
9
4
L1
FMI
SDIO
3
8
2
SCLK
C2
FM Antenna
NC
7
1
GPO1
NC
20
R2
1.62 to 3.6 V
C4
RSTB
VD
RCLK
SDIO
SCLK
SENB
Optional: AM Air Loop Antenna
1
GPO3
T1
1
C3
RCLK
X1
AMI
C5
3
2
L2
C6
RFGND
Optional: For Crystal OSC
Notes:
1. Place C1 close to VA pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible.
16
Rev. 1.0
Si4730/31-D50
3. Bill of Materials
Table 12. Si4730/31-D50 Bill of Materials
Component
Value/Description
Supplier
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
C2
Coupling capacitor, 1 nF, ±20%, Z5U/X7R
Murata
C3
Coupling capacitor, 0.47 μF, ±20%, Z5U/X7R
Murata
C4
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R
Murata
L1
Ferrite loop stick, 180–450 μH
Jiaxin
U1
Si4730/31 AM/FM Radio Tuner
Silicon Laboratories
R1
Resistor, 600 
(Optional for digital audio)
Venkel
R2
Resistor, 2 k
(Optional for digital audio)
Venkel
R3
Resistor, 2 k
(Optional for digital audio)
Venkel
Crystal load capacitors, 22 pF, ±5%, COG
(Optional for crystal oscillator option)
Venkel
C9
Noise mitigating capacitor, 2~5 pF
(Optional for digital audio)
Murata
L2
Air Loop, 10–20 μH
(Optional for AM Input)
Jiaxin
T1
Transformer, 1:5 turns ratio
(Optional for AM Input)
X1
32.768 kHz crystal
(Optional for crystal oscillator option)
C5, C6
Jiaxin, UMEC
Rev. 1.0
Epson
17
Si4730/31-D50
4. Functional Description
4.1. Overview
Si473x
AMI
RDS
(Si4731)
LNA
AGC
ADC
VA
LDO
AFC
RCLK
GND
ROUT
DAC
LOUT
DSP
AGC
2.7– 5.5 V
DAC
CONTROL
INTERFACE
VD
1.62–3.6 V
RST
LNA
SEN
FMI
DFS
GPO/DCLK
LOW-IF
ADC
FM
ANT
DOUT
DIGITAL
AUDIO
SDIO
RFGND
SCLK
AM
ANT
Figure 7. Functional Block Diagram
The Si4730/31-D50 is Silicon Labs’ fourth generation
fully integrated, 100% CMOS AM/FM radio receiver IC.
Offering unmatched integration and PCB space
savings, the Si4730/31 requires only two external
components and less than 15 mm2 of board area,
excluding the antenna inputs. The Si4730/31 AM/FM
radio provides the space savings and low power
consumption necessary for portable devices while
delivering the high performance and design simplicity
desired for all AM/FM solutions.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4730/31 delivers
superior RF performance and interference rejection in
both AM and FM bands. The high integration and
complete system production test simplifies design-in,
increases
system
quality,
and
improves
manufacturability.
The Si4730/31 is a feature-rich solution that includes
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, FM stereo processing, and advanced
audio processing.
In addition, the Si4730/31 provides analog and digital
audio outputs and a programmable reference clock. The
device supports I2C-compatible 2-wire control interface,
SPI, and a Si4700/01 backwards-compatible 3-wire
control interface.
The Si4730/31 utilizes digital processing to achieve high
18
fidelity, optimal performance, and design flexibility. The
chip provides excellent pilot rejection, selectivity, and
unmatched audio performance, and offers both the
manufacturer
and
the
end-user
extensive
programmability and flexibility in the listening
experience.
The Si4731 incorporates a digital processor for the
European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS)
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using this feature, the Si4731 enables
broadcast data such as station identification and song
name to be displayed to the user.
4.2. Operating Modes
The Si4730/31 operates in either an FM receive or an
AM receive mode. In FM mode, radio signals are
received on FMI and processed by the FM front-end
circuitry. In AM mode, radio signals are received on AMI
and processed by the AM front-end circuitry. In addition
to the receiver mode, there is an audio output mode to
choose between an analog and/or digital audio output.
In the analog audio output mode, ROUT and LOUT are
used for the audio output pins. In the digital audio mode,
DOUT, DFS, and DCLK pins are used. Concurrent
analog/digital audio output mode is also available
requiring all five pins.
Rev. 1.0
Si4730/31-D50
4.3. FM Receiver
4.5. Digital Audio Interface
The Si4730/31 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture allowing the elimination of external
components and factory adjustments. The Si4730/31
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (64 to 108 MHz). An
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An imagereject mixer downconverts the RF signal to low-IF. The
quadrature mixer output is amplified, filtered, and
digitized with high resolution analog-to-digital
converters (ADCs). This advanced architecture allows
the Si4730/31 to perform channel selection, FM
demodulation, and stereo audio processing to achieve
superior performance compared to traditional analog
architectures.
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I2S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit
synchronization input clock (DCLK). The Si473x
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
4.4. AM Receiver
4.5.1. Audio Data Formats
The digital audio interface operates in slave mode and
supports three different audio data formats:
I2S
 Left-Justified
 DSP Mode

The highly-integrated Si4730/31 supports worldwide AM
band reception from 520 to 1710 kHz using a digital
low-IF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering offering excellent selectivity and SNR with
minimum variation across the AM band. The DSP also
provides adjustable channel step sizes in 1 kHz
increments, AM demodulation, soft mute, seven
different channel bandwidth filters, and additional
features, such as a programmable automatic volume
control (AVC) maximum gain allowing users to adjust
the level of background noise.
In I2S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
Similar to the FM receiver, the integrated LNA and AGC
optimize sensitivity and rejection of strong interferers
allowing better reception of weak stations.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
The Si4730/31 provides highly-accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–450 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor, the inductance is increased by 25 times
and easily supports all typical AM air loop antennas
which generally vary between 10 and 20 µH.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. If preferred,
the user can configure the MSB to be captured on the
falling edge of DCLK via properties. The number of
audio bits can be configured for 8, 16, 20, or 24 bits.
4.5.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
Rev. 1.0
19
Si4730/31-D50
(OFALL = 1)
INVERTED
DCLK
(OFALL = 0)
DCLK
LEFT CHANNEL
DFS
I2S
(OMODE = 0000)
RIGHT CHANNEL
1 DCLK
1 DCLK
1
DOUT
2
n-2
3
n-1
MSB
n
1
LSB
MSB
2
n-2
3
n-1
n
LSB
Figure 8. I2S Digital Audio Format
(OFALL = 1)
INVERTED
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
Left-Justified
(OMODE = 0110)
1
DOUT
2
3
n-2
n-1
MSB
n
1
LSB
MSB
2
n-2
3
n-1
n
LSB
Figure 9. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
LEFT CHANNEL
(OMODE = 1100)
DOUT
(MSB at 1st rising edge)
1
2
3
n-2
n-1
MSB
(OMODE = 1000)
1
LSB
MSB
n-1
n
1
LSB
MSB
2
1
2
3
n-2
MSB
Rev. 1.0
n-1
n
LSB
RIGHT CHANNEL
2
Figure 10. DSP Digital Audio Format
20
n-2
3
LEFT CHANNEL
1 DCLK
DOUT
(MSB at 2nd rising edge)
n
3
n-2
n-1
n
LSB
Si4730/31-D50
4.7. Received Signal Qualifiers
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 11 below.
The quality of a tuned signal can vary depending on
many factors including environmental conditions, time of
day, and position of the antenna. To adequately manage
the audio output and avoid unpleasant audible effects to
the end-user, the Si473x monitors and provides
indicators of the signal quality. The Si473x monitors
signal quality metrics including RSSI, SNR, and
multipath interference on FM signals. These metrics are
used to optimize audio and signal processing and are
also reported to the host processor. The signal
processing algorithms can use either Silicon Labs'
optimized settings (recommended) or be customized to
modify performance.
Modulation Level
4.6. Stereo Audio Processing
Mono Audio
Left + Right
0
Stereo
Pilot
15 19 23
Stereo Audio
Left - Right
38
RDS/
RBDS
53
4.8. De-emphasis
57
Frequency (kHz)
Figure 11. MPX Signal Spectrum
4.6.1. Stereo Decoder
The
Si4730/31's
integrated
stereo
decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4731 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
4.6.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Three metrics, received signal
strength indicator (RSSI), signal-to-noise ratio (SNR),
and
multipath
interference,
are
monitored
simultaneously in forcing a blend from stereo to mono.
The metric which reflects the minimum signal quality
takes precedence and the signal is blended
appropriately.
All three metrics have programmable stereo/mono
thresholds and attack/release rates detailed in “AN332:
Si47xx Programming Guide.” If a metric falls below its
mono threshold, the signal is blended from stereo to full
mono. If all metrics are above their respective stereo
thresholds, then no action is taken to blend the signal. If
a metric falls between its mono and stereo thresholds,
then the signal is blended to the level proportional to the
metric’s value between its mono and stereo thresholds,
with an associated attack and release rate.
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4730/31
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The deemphasis time constant is programmable to 50 or
75 µs.
4.9. Volume Control
The audio output may be muted. Volume is adjusted
digitally by the RX_VOLUME property.
4.10. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted.
4.11. Soft Mute
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute feature is triggered by the
SNR metric. The SNR threshold for activating soft mute
is programmable, as are soft mute attenuation levels
and attack and release rates.
Rev. 1.0
21
Si4730/31-D50
4.12. FM Hi-Cut Control
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or
multipath interference. Two metrics, SNR and multipath
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. Attack and release
rates for hi-cut are programmable for both metrics from
a range of 2 ms to 64 s. The level of hi-cut applied can
be monitored with the FM_RSQ_STATUS command.
Hi-cut can be disabled by setting the hi-cut filter to audio
bandwidth of 15 kHz.
4.13. RDS/RBDS Processor (Si4731 Only)
The Si4731 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4731 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
The Si4731 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
4.14. Tuning
The tuning frequency is directly programmed using the
FM_TUNE_FREQ and AM_TUNE_FREQ commands.
The Si4730/31 supports channel spacing steps of
10 kHz in FM mode and 1 kHz in AM mode.
4.15. Seek
The Si4730/31 seek functionality is performed
completely on-chip and will search up or down the
selected frequency band for a valid channel. A valid
channel is qualified according to a series of
programmable signal indicators and thresholds. The
seek function can be made to stop at the band edge and
provide an interrupt, or wrap the band and continue
seeking until arriving at the original departure frequency.
The device sets interrupts with found valid stations or, if
the seek results in zero found valid stations, the device
indicates failure and again sets an interrupt. Refer to
“AN332: Si47xx Programming Guide”.
22
The Si4730/31 uses RSSI, SNR, and AFC to qualify
stations. Most of these variables have programmable
thresholds for modifying the seek function according to
customer needs.
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations. The Si4730/31 defaults set RSSI to
a mid-level threshold and add an SNR threshold set to a
level delivering acceptable audio performance. This
trade-off will eliminate very low RSSI stations while
keeping the seek time to acceptable levels. Generally,
the time to auto-scan and store valid channels for an
entire FM band with all thresholds engaged is very short
depending on the band content. Seek is initiated using
the FM_SEEK_START command. The RSSI, SNR, and
AFC threshold settings are adjustable using properties.
4.16. Reference Clock
The Si4730/31 reference clock is programmable,
supporting RCLK frequencies listed in Table 11,
“Reference Clock and Crystal Characteristics,” on
page 15. Refer to Table 3, “DC Characteristics,” on
page 5 for switching voltage levels and Table 11 for
frequency tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 16. This mode is enabled using the
POWER_UP command. Refer to “AN332: Si47xx
Programming Guide”.
The Si4730/31 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4730/31 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4730/31 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Rev. 1.0
Si4730/31-D50
4.17. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4730/31
and receive responses from the device. The serial port
can operate in two bus modes: 2-wire mode and 3-wire
mode. The Si4730/31 selects the bus mode by sampling
the state of the GPO1 and GPO2 pins on the rising
edge of RST. The GPO1 pin includes an internal pull-up
resistor, which is connected while RST is low, and the
GPO2 pin includes an internal pull-down resistor, which
is connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 13.
Table 13. Bus Mode Select on Rising Edge of
RST
Bus Mode
2-Wire
3-Wire
GPO1
1
0 (must drive)
GPO2
0
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
described in Section “4.18. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied.
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4730/31 acknowledges each
data byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
For read operations, after the Si4730/31 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4730/31. A 2-wire
transaction ends with the STOP condition, which occurs
when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,”
on page 8.
4.17.2. 3-Wire Control Interface Mode
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4.17.1. 2-Wire Control Interface Mode
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4730/31 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4730/31 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). Refer to “AN332: Si47xx Programming
Guide”
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4730/31 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
Rev. 1.0
23
Si4730/31-D50
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.18. GPO Outputs
The Si4730/31 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode.
4.19. Firmware Upgrades
The Si4730/31 contains on-chip program RAM to
accommodate minor changes to the firmware. This
allows Silicon Labs to provide future firmware updates
to optimize the characteristics of new radio designs and
those already deployed in the field.
4.20. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
4.21. Programming with Commands
To ease development time and offer maximum
customization, the Si4730/31 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses.
To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
the given command. Commands control an action such
as powerup the device, shut down the device, or tune to
a station. Arguments are specific to a given command
and are used to modify the command.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a 1-byte status update,
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4730/31, see “AN332: Si47xx
Programming Guide.”
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
24
Rev. 1.0
Si4730/31-D50
GPO2/INT
GPO3/DCLK
DFS
1
GPO1
NC
NC
5. Pin Descriptions: Si4730/31-GM
20
19
18
17
16
FMI 2
15 DOUT
RFGND 3
14 LOUT
GND
PAD
AMI 4
13 ROUT
6
7
8
9
10
SCLK
SDIO
RCLK
VD
12 GND
SEN
RST 5
11 VA
Pin Number(s)
Name
Description
1, 20
NC
No connect. Leave floating.
2
FMI
FM RF inputs. FMI should be connected to the antenna trace.
3
RFGND
4
AMI
AM RF input. AMI should be connected to the AM antenna.
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
External reference oscillator input.
10
VD
Digital and I/O supply voltage.
11
VA
Analog supply voltage. May be connected directly to battery.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
13
ROUT
Right audio line output in analog output mode.
14
LOUT
Left audio line output in analog output mode.
15
DOUT
Digital output data in digital output mode.
16
DFS
17
GPO3/DCLK
18
GPO2/INT
19
GPO1
RF ground. Connect to ground plane on PCB.
Digital frame synchronization input in digital output mode.
General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
General purpose output or interrupt pin.
General purpose output.
Rev. 1.0
25
Si4730/31-D50
6. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature/Voltage
Si4730-D50-GM
AM/FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
Si4731-D50-GM
AM/FM Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
26
Rev. 1.0
Si4730/31-D50
7. Package Markings (Top Marks)
7.1. Si4730/31 Top Mark
3050
DTTT
YWW
3150
DTTT
YWW
7.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
30 = Si4730, 31 = Si4731.
Firmware Revision
50 = Firmware Revision 5.0.
Die Revision
D = Revision D Die.
TTT = Internal Code
Internal tracking code.
Line 2 Marking:
Line 3 Marking:
Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and work week of the mold date.
Rev. 1.0
27
Si4730/31-D50
8. Package Outline: Si4730/31
Figure 12 illustrates the package details for the Si4730/31. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 12. 20-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions
Symbol
Millimeters
Symbol
Min
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.20
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
D
D2
1.65
1.70
1.75
0.50 BSC
E
E2
Min
3.00 BSC
e
3.00 BSC
1.65
1.70
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
28
Millimeters
Rev. 1.0
Nom
Max
2.53 BSC
Si4730/31-D50
9. PCB Land Pattern: Si4730/31
Figure 13 illustrates the PCB land pattern details for the Si4730/31-D50-GM QFN. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 13. PCB Land Pattern
Rev. 1.0
29
Si4730/31-D50
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.71 REF
1.60
1.80
Min
Max
GE
2.10
—
W
—
0.34
—
e
0.50 BSC
X
E
2.71 REF
Y
E2
f
GD
1.60
1.80
2.53 BSC
2.10
Millimeters
0.28
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
30
Rev. 1.0
Si4730/31-D50
10. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
 AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
 Si47xx EVB User’s Guide
 Customer Support Site: www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software.
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.


Rev. 1.0
31
Si4730/31-D50
DOCUMENT CHANGE LIST:
Revision 0.2 to Revision 1.0
Updated functional block diagram.
Updated specification tables.
 Updated “2. Typical Application Schematic”.
 Updated“Table 3. DC Characteristics”.
 Added Section “4.6. Stereo Audio Processing”.


32
Rev. 1.0
Si4730/31-D50
NOTES:
Rev. 1.0
33
Si4730/31-D50
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
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Email: FMinfo@silabs.com
Internet: www.silabs.com
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Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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34
Rev. 1.0
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