MicroZed™ Embedded Vision Carrier Card Hardware

MicroZed™
Embedded Vision Carrier Card
Hardware User Guide
Version 1.0
Page 1
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LIT# 5188-UG-AES-MBCC-EMBV-DEV-G-V1
Document Control
Document Version:
1.0
Document Date:
1/16/2015
Prior Version History
Version
Date
Comment
1.0
1/16/2015
Initial Release
Page 2
Contents
1
Introduction ........................................................................................................... 4
2
Functional Description .......................................................................................... 6
2.1
Embedded Vision Carrier Card Block Diagram ......................................................... 6
2.2
Memory .................................................................................................................... 7
2.3
Reset Sources ......................................................................................................... 7
2.3.1
Power On Reset – POR# button – BTN3 ...................................................................... 7
2.3.2
Processor Subsystem Reset: PS_RESET# button – BTN2 ........................................... 7
2.4
User Interfaces ......................................................................................................... 7
2.4.1
User Push Buttons ....................................................................................................... 7
2.4.2
User LEDs ................................................................................................................... 8
2.4.3
PJTAG Switch.............................................................................................................. 8
2.4.4
PUDC Jumper.............................................................................................................. 8
2.5
User Headers ........................................................................................................... 9
2.5.1
Digilent Pmod™ Compatible Expansion Headers (2x6) ................................................ 9
2.5.2
JX1 and JX2 MicroZed™ Micro Headers .................................................................... 10
2.6
10/100/1000 PL Ethernet PHY ............................................................................... 15
2.7
HDMI Input ............................................................................................................. 16
2.8
HDMI Output .......................................................................................................... 18
2.9
JTAG Interface ....................................................................................................... 20
2.10 Audio Interfaces ..................................................................................................... 21
2.11 Camera Interface ................................................................................................... 22
2.11.1
Camera Connector..................................................................................................... 22
2.11.2
Mapping the Camera Interface ................................................................................... 23
2.11.3
Camera Implementation ............................................................................................. 24
2.12 I2C SWITCH Interface............................................................................................ 27
2.13 I2C I/O Expander Interface ..................................................................................... 28
2.14 Power Supplies ...................................................................................................... 29
3
2.14.1
Voltage Rails and Sources ......................................................................................... 29
2.14.2
Voltage Regulators..................................................................................................... 30
2.14.3
Power LEDs ............................................................................................................... 31
2.14.4
Power-On-Reset ........................................................................................................ 31
2.14.5
Power-Over-Ethernet ................................................................................................. 32
Mechanical.......................................................................................................... 33
Page 3
1 Introduction
The MicroZed™ Embedded Vision Carrier Card builds on the MicroZed SOM by providing a video specific
carrier card which includes on-board HDMI input/output interfaces and a camera connector for optional
camera modules.
The features provided by the MicroZed™ Embedded Vision Carrier Card consist of:
–
–
–
–
–
–
Support for MicroZed™ 7010 or 7020 System on Module
– Two 100-pin board-to-board Micro Headers
Video/Audio
– Image Sensor Interface supporting Optional Camera Modules
– Micro-HDMI Input featuring Analog Devices ADV7611
– Micro-HDMI Output featuring Analog Devices ADV7511
– Audio Codec featuring Analog Devices ADAU1761 (Requires MicroZed™ 7020)
Interfaces
– 10/100/1000 Zynq PL Ethernet featuring Marvell PHY
– 3x - Digilent Pmod™ compatible interfaces
– Access to 24 User I/O
– 1x - Connected to Zynq PS MIO
– 2x - Connection to Zynq PL IO (Requires MicroZed™ 7020)
– 2x - User Push Buttons
– 2x - User LEDs
– Power-On and System Reset Push Buttons
– Xilinx PC4 Header – JTAG
– 5x - Status LEDs
Memory
– 2-Kb Ethernet MAC ID EEPROM (MicroZed™ PS Ethernet)
– 2-Kb Ethernet MAC ID EEPROM (On-Board PL Ethernet)
Power
– Primary Supply
– Power Over Ethernet (PoE) +5V Interface featuring ST Microelectronics
– Secondary Supply
– +5V/2A Wall Adapter
– On-Board Regulators featuring ST Microelectronics
– +3.3V @ 4A
– +2.5V @ 4A
– +1.8V @ 500mA
Software
– Vivado Design Suite
– Download from www.xilinx.com/support/download.html
– Request a free DVD from www.xilinx.com/onlinestore/dvd_fulfillment_request.htm
Page 4
Figure 1 – MicroZed™ Embedded Vision Carrier Card Topology – Front
Figure 2 – MicroZed™ Embedded Vision Carrier Card Topology – Rear
Page 5
2 Functional Description
The MicroZed™ Embedded Vision Carrier Card is an expansion board for the MicroZed™ that will help
engineers to quickly develop solutions targeting custom video-specific applications with camera
connections to optional add-on camera modules. In support of embedded vision applications the carrier
card also includes on-board HDMI input and output connections, audio input and output connections, as
well as a Power over Ethernet (PoE) port. Finally, design customization is supported through Digilent
Pmod™ compatible expansion interfaces.
2.1
Embedded Vision Carrier Card Block Diagram
The following figure shows how the Embedded Vision Carrier Card makes its connections to the
MicroZed™ System-On-Module via the Micro Headers, JX1 and JX2
Figure 3 – Functional Connections to MicroZed™
Page 6
2.2
Memory
The MicroZed™ Ethernet interface and the Embedded Vision Carrier Card PoE Ethernet interface
does not have a permanently assigned MAC ID. A MAC ID can be assigned independently on the
MicroZed™ by users who have their own EUI-64 assignments granted to them by the IEEE. Using
a MAC ID EEPROM is another alternative to this method. The EEPROM comes with a unique, preassigned EUI-64 identifier which can be associated to the Ethernet ports.
A pair of Microchip 11AA02E48 Ethernet MAC ID EEPROMs is implemented on the MicroZed™
Embedded Vision Carrier Card. One of the Ethernet MAC ID EEPROMs is connected to the
MicroZed™ Zynq PS. The 2nd Ethernet MAC ID EEPROM is connected to the MicroZed™ Zynq
PL. This provides two pre-assigned EUI-64 identifiers that can be associated with the MicroZed™
Ethernet interface and the Embedded Vision Carrier Card PoE interface.
Carrier Net Name
Micro Header Connection
Zynq AP SoC Connection
MAC_ID1
JX1 - 9
Bank 34 - R19
MAC_ID0
JX1 - 10
Bank 34 - T19
Table 1 – MAC ID EEPROM Connections
2.3
2.3.1
Reset Sources
Power On Reset – POR# button – BTN3
The POR# button provides an active low signal to the PG_CARRIER net on the JX2 Micro Header
pin 11. When asserted, this signal resets the MicroZed™ USB UART, USB OTG circuit and turns
off MicroZed™ power supplies. It is used to invoke a MicroZed™ total system power reset. The
PS and PL are reset to power on default settings and the selected boot process is initiated.
Carrier Net Name
Micro Header Connection
Zynq AP SoC Connection
PG_CARRIER
JX2 - 11
PG_MODULE
Table 2 – POR Push Button – BTN3
2.3.2
Processor Subsystem Reset: PS_RESET# button – BTN2
The PS_RESET# button provides an active low signal to net CARRIER_SRST# which allows
the user to reset all of the functional logic within the device without disturbing the debug
environment. For example, the previous break points set by the user remain valid after system
reset. Due to security concerns, system reset erases all memory content within the PS,
including the OCM. The PL is also reset in system reset. System reset does not re-sample the
boot mode strapping pins.
Carrier Net Name
Micro Header Connection
Zynq AP SoC Connection
CARRIER_SRST#
JX1 - 6
PS_SRST#
Table 3 – SYS_RST# Push Button – BTN2
2.4
2.4.1
User Interfaces
User Push Buttons
The Embedded Vision Carrier Card provides 2 user GPIO push buttons that connects to the
MicroZed™. Pull-down resistors provide a known low default state. Pushing a button connects
+3.3V to assert logic high.
In order to access the User Push Buttons, the end user must setup the proper mode for the
PJTAG/USER IO switch, SW1.
Page 7
SW1 - ON implies User Leds and User Push Buttons
SW1 - OFF implies PJTAG using MicroZed™ Pmod™ compatible interface
Carrier Net Name
Micro Header Connection
Zynq AP SoC Connection
PB_0
JX2 - 2
Bank 500 - E9
PB_1
JX2 - 4
Bank 500 - D9
Table 4 – User Push Button Connections
2.4.2
User LEDs
The Carrier has 2 user LEDs. Logic high from the MicroZed™ I/O turns the LED on. LED’s are
sourced from +3.3V through current limiting resistors.
In order to access the User Push Buttons, the end user must setup the proper mode for the
PJTAG/USER IO switch, SW1.
SW1 - ON implies User Leds and User Push Buttons
SW1 - OFF implies PJTAG using MicroZed™ Pmod™ compatible interface
Carrier Net Name
Micro Header Connection
Zynq AP SoC Connection
LED0
JX2 - 1
Bank 500 - E8
LED1
JX2 - 3
Bank 500 - C6
Table 5 – User LED Connections
2.4.3
PJTAG Switch
The Embedded Vision Carrier card contains a switch, SW1 that allows you to select between
on LEDs and PUSHBUTTONS on board the carrier card or to remove these from circuit by
toggling the switch. This allows the end user to access a PMOD™ on board the MicroZed™
and not have circuit contention that may be caused by the additional components attached to
those shared pins. The following table shows how toggling the switch affects the circuit.
SW1 Setting
I/O Connection
ON
USER LEDS & PUSH BUTTONS
OFF
PJTAG/PMOD on MicroZed™
Table 6 – PJTAG Switch Settings
2.4.4
PUDC Jumper
The PUDC jumper, J2, controls the PULL UP DURING CONFIGURATION (PUDC) pin of the
Zynq device on the MicroZed™. There are two ways to set this to jumper that either enables
or disables PULL UPs on the Zynq I/O during configuration. The following table describes the
setting of the jumper.
J2 JUMPER SETTING
PULL UP DURING CONFIGURATION
SHORT 1-2 (PULL UP)
DISABLED
SHORT 2-3(PULL DOWN)
ENABLED
Table 7– PUDC Jumper Setting
NOTE: The PUDC Jumper affects the state of the PER_RST# signal. This signal is level
translated and controls the I2C_MUX_RST# and CAM_RST# signals. Be aware that this jumper
is active during configuration only and depending of the setting of the jumper, this may hold the
interfaces in reset or release the interface from reset prior to when the end user desires.
Page 8
2.5
User Headers
2.5.1
Digilent Pmod™ Compatible Expansion Headers (2x6)
The Carrier has three Digilent Pmod™ right angle 0.1” female
sockets (2x6). These connections include eight user I/O plus
+3.3V and GND. +3.3V is required so the electrical connection
becomes Pmod™ compliant. All Pmod™ connections are
matched differential Pmod™ connections that are routed
differentially within the connector and with reference to one
another to ensure high speed signal integrity.
–
–
–
JY Pmod™
JD Pmod™
JC Pmod™
Pmod™
The Digilent Pmod™ compatible interfaces connect to
MicroZed™ Zynq Bank 34 and Bank 13. Bank 13 is only
available on the 7Z020 version MicroZed™.
Pmods™ JC and JD are sourced by Bank 34 and are
common to any MicroZed™ SOM.
Pmod™ JY is sourced by Bank 13 and thus is only available
when the MicroZed™ SOM is populated with a 7Z020
device.
FPGA I/O
1
FPGA I/O
2
FPGA I/O
3
FPGA I/O
4
5
3.3V
6
FPGA I/O
7
FPGA I/O
8
FPGA I/O
9
FPGA I/O
10
11
3.3V
12
Figure 4 –
Digilent Pmod™
Compatible Interface
Connections
Carrier Net Name
Pmod Pin Number
Micro Header Connection
Zynq AP SoC Connection
JC0-1 P
Pin 1
JX1 - 47
Bank 34 - N18
JC0-1 N
Pin 2
JX1 - 49
Bank 34 - P19
JC2-3 P
Pin 3
JX1 - 48
Bank 34 - N20
JC2-3 N
Pin 4
JX1 - 50
Bank 34 - P20
JC4-5 P
Pin 7
JX1 - 53
Bank 34 - T20
JC4-5 N
Pin 8
JX1 - 55
Bank 34 - U20
JC6-7 P
Pin 9
JX1 - 54
Bank 34 - V20
JC6-7 N
Pin 10
JX1 - 56
Bank 34 - W20
JD0-1 P
Pin 1
JX1 - 67
Bank 34 - R16
JD0-1 N
Pin 2
JX1 - 69
Bank 34 - R17
JD2-3 P
Pin 3
JX1 - 68
Bank 34 - T17
JD2-3 N
Pin 4
JX1 - 70
Bank 34 - R18
JD4-5 P
Pin 7
JX1 - 73
Bank 34 - V17
JD4-5 N
Pin 8
JX1 - 75
Bank 34 - V18
JD6-7 P
Pin 9
JX1 - 74
Bank 34 - W18
JD6-7 N
Pin 10
JX1 - 76
Bank 34 - W19
JY0-1 P
Pin 1
JX1 - 87
Bank 13 - U7
JY0-1 N
Pin 2
JX1 - 89
Bank 13 - V7
JY2-3 P
Pin 3
JX1 - 88
Bank 13 - T9
JY2-3 N
Pin 4
JX1 - 90
Bank 13 - U10
JY4-5 P
Pin 7
JX1 - 91
Bank 13 - V8
JY4-5 N
Pin 8
JX1 - 93
Bank 13 - W8
JY6-7 P
Pin 9
JX1 - 92
Bank 13 - T5
JY6-7 N
Pin 10
JX1 - 94
Bank 13 - U5
Table 8 – Digilent Pmod™ Compatible Interface Connections
Page 9
2.5.2
JX1 and JX2 MicroZed™ Micro Headers
The Embedded Vision Carrier Card features two Micro Headers, FCI PN: FCI_61083101400LF for connection to the MicroZed™ SOM. The Micro Headers connect to interfaces
that map to the Zynq PL I/O, Zynq PS-MIO*, and Zynq dedicated JTAG* pins.
* NOTE: There are eight PS-MIO and four JTAG signals that are shared on MicroZed™ SOM
and the Embedded Vision Carrier Card. For each interface, only access these signals from the
MicroZed™ or the Embedded Vision Carrier Card. Do not access these signals simultaneously.
–
–
–
–
The connectors are FCI BERGSTAK 0.8mm pitch. These have variable stack heights from
5mm to 20mm, making it easy to connect to a variety of expansion or system boards.
Each connector has 100 pins which include I/O, analog signals, as well as power and
ground. Each power pin can carry 500mA of current.
MicroZed™ does not power the PL Banks VCCIO; the Embedded Vision Carrier Card is
required to provide power for the PL Banks VCCIO. The 7Z010 has two PL I/O banks,
Banks 34 and 35. Bank 34 is powered by +3.3V and Bank 35 is powered by +2.5V.
The 7Z020 has a third I/O bank, Bank 13, which is powered on the Embedded Vision
Carrier Card by +3.3V.
Page 10
Carrier Net Name
JTAG_TCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
PWR_EN
CARRIER_SRST#
VBAT
FPGA_DONE
MAC_ID1
MAC_ID0
HDMII_Y7
HDMII_Y5
HDMII_Y6
HDMII_Y4
GND
GND
PUDC#/PER_RST#
HDMII_Y3
HDMI_IO_INT#
HDMII_Y2
GND
GND
HDMII_CBCR7
HDMII_Y1
HDMII_CBCR6
HDMII_Y0
GND
GND
HDMII_CBCR3
HDMII_CBCR5
HDMII_CBCR2
HDMII_CBCR4
GND
GND
HDMIO_Y7
HDMII_CBCR1
HDMIO_Y6
HDMII_CBCR0
GND
GND
HDMIO_CLK
HDMII_CLK
HDMIO_Y5
HDMIO_Y4
GND
GND
JC0-1_P
JC2-3_P
JC0-1_N
JC2-3_N
GND
Pmod Pin Number
JX1 – 1
JX1 – 2
JX1 – 3
JX1 – 4
JX1 – 5
JX1 – 6
JX1 – 7
JX1 – 8
JX1 – 9
JX1 – 10
JX1 – 11
JX1 – 12
JX1 – 13
JX1 – 14
JX1 – 15
JX1 – 16
JX1 – 17
JX1 – 18
JX1 – 19
JX1 – 20
JX1 - 21
JX1 – 22
JX1 – 23
JX1 – 24
JX1 – 25
JX1 – 26
JX1 – 27
JX1 – 28
JX1 – 29
JX1 – 30
JX1 – 31
JX1 – 32
JX1 – 33
JX1 – 34
JX1 – 35
JX1 – 36
JX1 – 37
JX1 – 38
JX1 – 39
JX1 – 40
JX1 – 41
JX1 – 42
JX1 – 43
JX1 – 44
JX1 – 45
JX1 – 46
JX1 – 47
JX1 – 48
JX1 – 49
JX1 – 50
JX1 – 51
Micro Header Connection
JTAG_TCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
PWR_ENABLE
CARRIER_SRST#
FPGA_VBATT
FPGA_DONE
JX1_SE_0
JX1_SE_1
JX1_LVDS_0_P
JX1_LVDS_1_P
JX1_LVDS_0_N
JX1_LVDS_1_N
GND
GND
JX1_LVDS_2_P
JX1_LVDS_3_P
JX1_LVDS_2_N
JX1_LVDS_3_N
GND
GND
JX1_LVDS_4_P
JX1_LVDS_5_P
JX1_LVDS_4_N
JX1_LVDS_5_N
GND
GND
JX1_LVDS_6_P
JX1_LVDS_7_P
JX1_LVDS_6_N
JX1_LVDS_7_N
GND
GND
JX1_LVDS_8_P
JX1_LVDS_9_P
JX1_LVDS_8_N
JX1_LVDS_9_N
GND
GND
JX1_LVDS_10_P
JX1_LVDS_11_P
JX1_LVDS_10_N
JX1_LVDS_11_N
GND
GND
JX1_LVDS_12_P
JX1_LVDS_13_P
JX1_LVDS_12_N
JX1_LVDS_13_N
GND
Page 11
Zynq AP SoC Connection
F9
J6
F6
G6
B10 *
F11
R11
R19
T19
T11
T12
T10
U12
U13
V12
V13
W13
T14
P14
T15
R14
Y16
W14
Y17
Y14
T16
V15
U17
W15
U14
U18
U15
U19
N18
N20
P19
P20
-
Carrier Net Name
GND
JC4-5_P
JC6-7_P
JC4-5_N
JC6-7_N
5V
5V
5V
5V
HDMIO_Y3
HDMIO_Y1
HDMIO_Y2
HDMIO_Y0
GND
GND
JD0-1_P
JD2-3_P
JD0-1_N
JD2-3_N
GND
GND
JD4-5_P
JD6-7_P
JD4-5_N
JD6-7_N
GND
3V3
3V3
3V3
HDMIO_CBCR1
HDMIO_CBCR3
HDMIO_CBCR0
HDMIO_CBCR2
GND
GND
JY0-1_P
JY2-3_P
JY0-1_N
JY2-3_N
JY4-5_P
JY6-7_P
JY4-5_N
JY6-7_N
GND
GND
GND
GND
GND
GND
Pmod Pin Number
JX1 – 52
JX1 – 53
JX1 - 54
JX1 – 55
JX1 – 56
JX1 – 57
JX1 – 58
JX1 – 59
JX1 – 60
JX1 – 61
JX1 – 62
JX1 – 63
JX1 – 64
JX1 – 65
JX1 – 66
JX1 – 67
JX1 – 68
JX1 – 69
JX1 – 70
JX1 – 71
JX1 – 72
JX1 – 73
JX1 – 74
JX1 – 75
JX1 – 76
JX1 – 77
JX1 – 78
JX1 – 79
JX1 – 80
JX1 – 81
JX1 – 82
JX1 – 83
JX1 – 84
JX1 – 85
JX1 – 86
JX1 – 87
JX1 – 88
JX1 – 89
JX1 – 90
JX1 – 91
JX1 – 92
JX1 – 93
JX1 – 94
JX1 – 95
JX1 – 96
JX1 – 97
JX1 – 98
JX1 – 99
JX1 – 100
Micro Header Connection
GND
JX1_LVDS_14_P
JX1_LVDS_15_P
JX1_LVDS_14_N
JX1_LVDS_15_N
VIN_HDR
VIN_HDR
VIN_HDR
VIN_HDR
JX1_LVDS_16_P
JX1_LVDS_17_P
JX1_LVDS_16_N
JX1_LVDS_17_N
GND
GND
JX1_LVDS_18_P
JX1_LVDS_19_P
JX1_LVDS_18_N
JX1_LVDS_19_N
GND
GND
JX1_LVDS_20_P
JX1_LVDS_21_P
JX1_LVDS_20_N
JX1_LVDS_21_N
GND
VCCO_34
VCCO_34
VCCO_34
JX1_LVDS_22_P
JX1_LVDS_23_P
JX1_LVDS_22_N
JX1_LVDS_23_N
GND
GND
BANK13_LVDS_0_P
BANK13_LVDS_1_P
BANK13_LVDS_0_N
BANK13_LVDS_1_N
BANK13_LVDS_2_P
BANK13_LVDS_3_P
BANK13_LVDS_2_N
BANK13_LVDS_3_N
GND
GND
VP_0_P
DXP_0_P
VP_0_N
DXP_0_N
Zynq AP SoC Connection
T20
V20
U20
W20
Y18
V16
Y19
W16
R16
T17
R17
R18
V17
W18
V18
W19
N17
P15
P18
P16
U7
T9
V7
U10
V8
T5
W8
U5
K9
M9
L10
M10
Table 9 – Embedded Vision Carrier Card to MicroZed™ JX1 Connections
Page 12
Carrier Net Name
LED_0/PJTAG
PB_0/PJTAG
LED_1/PJTAG
PB_1/PJTAG
USER_IO1
USER_IO2
I2C_MUX_SCL
I2C_MUX_SDA
VCCIO_EN
PG_CARRIER
5V
CAM_TRIGGER_0
CAM_TRIGGER_1
GND
GND
CAM_REF_CLK
CAM_MONITOR_0
CAM_TRIGGER_2
CAM_MONITOR_1
GND
GND
CAM_D7_P
CAM_D6_P
CAM_D7_N
CAM_D6_N
GND
GND
CAM_D5_P
CAM_D4_P
CAM_D5_N
CAM_D4_N
GND
GND
CAM_D3_P
CAM_D2_P
CAM_D3_N
CAM_D2_N
GND
GND
CAM_D0_P
CAM_D1_P
CAM_D0_N
CAM_D1_N
GND
GND
ETH_RX_CLK
CAM_SYN_P
ETH_RX_CTRL
CAM_SYN_N
GND
Pmod Pin Number
JX2-1
JX2-2
JX2-3
JX2-4
JX2-5
JX2-6
JX2-7
JX2-8
JX2-9
JX2-10
JX2-11
JX2-12
JX2-13
JX2-14
JX2-15
JX2-16
JX2-17
JX2-18
JX2-19
JX2-20
JX2-21
JX2-22
JX2-23
JX2-24
JX2-25
JX2-26
JX2-27
JX2-28
JX2-29
JX2-30
JX2-31
JX2-32
JX2-33
JX2-34
JX2-35
JX2-36
JX2-37
JX2-38
JX2-39
JX2-40
JX2-41
JX2-42
JX2-43
JX2-44
JX2-45
JX2-46
JX2-47
JX2-48
JX2-49
JX2-50
JX2-51
Micro Header Connection
PMOD_D0
PMOD_D1
PMOD_D2
PMOD_D3
PMOD_D4
PMOD_D5
PMOD_D6
PMOD_D7
INIT#
PG_1V8
PG_MODULE
VIN_HDR
JX2_SE_0
JX2_SE_1
GND
GND
JX2_LVDS_0_P
JX2_LVDS_1_P
JX2_LVDS_0_N
JX2_LVDS_1_N
GND
GND
JX2_LVDS_2_P
JX2_LVDS_3_P
JX2_LVDS_2_N
JX2_LVDS_3_N
GND
GND
JX2_LVDS_4_P
JX2_LVDS_5_P
JX2_LVDS_4_N
JX2_LVDS_5_N
GND
GND
JX2_LVDS_6_P
JX2_LVDS_7_P
JX2_LVDS_6_N
JX2_LVDS_7_N
GND
GND
JX2_LVDS_8_P
JX2_LVDS_9_P
JX2_LVDS_8_N
JX2_LVDS_9_N
GND
GND
JX2_LVDS_10_P
JX2_LVDS_11_P
JX2_LVDS_10_N
JX2_LVDS_11_N
GND
Page 13
Zynq AP SoC Connection
E8
E9
C6
D9
E6
B5
C5
C8
R10
C7
G14
J15
C20
B19
B20
A20
E17
D19
D18
D20
E18
F16
E19
F17
L19
M19
L20
M20
M17
K19
M18
J19
L16
K17
L17
K18
-
Carrier Net Name
GND
CAM_CLK_P
ETH_TX_CLK
CAM_CLK_N
ETH_TX_CTRL
5V
5V
5V
5V
ETH_RX_D3
ETH_TXD3
ETH_RX_D2
ETH_TXD2
GND
GND
ETH_RX_D1
ETH_TXD1
ETH_RX_D0
ETH_TXD0
GND
GND
HDMIO_CBCR5
HDMIO_CBCR7
HDMIO_CBCR4
HDMIO_CBCR6
GND
2V5
2V5
2V5
CAM_SPI_CS
HDMII_SPDIF
CAM_SPI_MISO
HDMIO_SPDIF
GND
GND
CAM_SPI_CLK
ETH_MDC
CAM_SPI_MOSI
ETH_MDIO
GND
GND
AUD_GPIO_0
AUD_GPIO_2
AUD_GPIO_1
AUD_GPIO_3
AUD_MCLK
3V3
AUD_ADR_1
AUD_ADR_0
Pmod Pin Number
JX2-52
JX2-53
JX2-54
JX2-55
JX2-56
JX2-57
JX2-58
JX2-59
JX2-60
JX2-61
JX2-62
JX2-63
JX2-64
JX2-65
JX2-66
JX2-67
JX2-68
JX2-69
JX2-70
JX2-71
JX2-72
JX2-73
JX2-74
JX2-75
JX2-76
JX2-77
JX2-78
JX2-79
JX2-80
JX2-81
JX2-82
JX2-83
JX2-84
JX2-85
JX2-86
JX2-87
JX2-88
JX2-89
JX2-90
JX2-91
JX2-92
JX2-93
JX2-94
JX2-95
JX2-96
JX2-97
JX2-98
JX2-99
JX2-100
Micro Header Connection
GND
JX2_LVDS_12_P
JX2_LVDS_13_P
JX2_LVDS_12_N
JX2_LVDS_13_N
VIN_HDR
VIN_HDR
VIN_HDR
VIN_HDR
JX2_LVDS_14_P
JX2_LVDS_15_P
JX2_LVDS_14_N
JX2_LVDS_15_N
GND
GND
JX2_LVDS_16_P
JX2_LVDS_17_P
JX2_LVDS_16_N
JX2_LVDS_17_N
GND
GND
JX2_LVDS_18_P
JX2_LVDS_19_P
JX2_LVDS_18_N
JX2_LVDS_19_N
GND
VCCO_35
VCCO_35
VCCO_35
JX2_LVDS_20_P
JX2_LVDS_21_P
JX2_LVDS_20_N
JX2_LVDS_21_N
GND
GND
JX2_LVDS_22_P
JX2_LVDS_23_P
JX2_LVDS_22_N
JX2_LVDS_23_N
GND
GND
BANK13_LVDS_4_P
BANK13_LVDS_5_P
BANK13_LVDS_4_N
BANK13_LVDS_5_N
BANK13_LVDS_6_P
VCCO_13
BANK13_LVDS_6_N
BANK13_SE_0
Zynq AP SoC Connection
H16
J18
H17
H18
G17
F19
G18
F20
G19
J20
G20
H20
K14
H15
J14
G15
N15
L14
N16
L15
M14
K16
M15
J16
Y12
V11
Y13
V10
V6
W6
V5
Table 10 – Embedded Vision Carrier Card to MicroZed™ JX2 Connections
Page 14
2.6
10/100/1000 PL Ethernet PHY
The MicroZed™ Embedded Vision Carrier Card implements a second 10/100/1000 Ethernet port
for network connectivity using a Marvell 88E1512 PHY. This Ethernet port also supports Power
over Ethernet (PoE). PoE is documented in the Power Section of this user guide. The primary
Ethernet port exists on the MicroZed™ SOM.
The Marvell PHY connects to the MicroZed™ SOM through the JX2 Micro Header. The pins utilized
on the Micro Header attach the Marvell PHY to the Zynq-7000 AP SoC through the Programmable
Logic via the IO Bank 35 which has a 2.5V fixed IO voltage. The physical connection to the Zynq7000 AP SoC is accomplished through an RGMII interface.
A design engineer can implement one of two MAC Controllers in the Zynq-7000 AP SoC and utilize
a GMII-to-RGMII shim to add network connectivity to the Embedded Vision Carrier Card PL
Ethernet port.
A high-level block diagram the 10/100/1000 Ethernet interface is shown in the following figure.
Figure 5 – Digilent Pmod™ Compatible Interface Connections
The 88E1512 requires a 25 MHz input clock. An ABRACON ASDMB-25.000MHZ-LC-T is used as
this reference.
Page 15
Signal
Name
Description
Micro Header
Connection
Zynq Pin
88E1512
Pin
RX_CLK
Receive Clock
JX2 – 47
Bank 35 – L16
46
RX_CTRL
Receive Control
JX2 – 49
Bank 35 – L17
43
RXD[3:0]
Receive Data
RXD3: JX2 - 61
RXD2: JX2 - 63
RXD1: JX2 - 67
RXD0: JX2 - 69
Bank 35 – G17
Bank 35 – G18
Bank 35 – G19
Bank 35 – G20
44
45
47
48
TX_CLK
Transmit Clock
JX2 – 54
Bank 35 - J18
53
TX_CTRL
Transmit Control
JX2 – 56
Bank 35 – H18
56
TXD[3:0]
Transmit Data
TXD3: JX2 - 62
TXD2: JX2 - 64
TXD1: JX2 - 68
TXD0: JX2 - 70
Bank 35 – F19
Bank 35 – F20
Bank 35 – J20
Bank 35 – H20
50
51
54
55
MDIO
Management Data
JX2 – 90
Bank 35 – J16
8
MDC
Management Clock
JX2 – 88
Bank 35 – K16
7
ETH_RST#
PHY Reset
** I2C SWITCH
N/A
16
Table 11– Ethernet PHY Pin Assignment and Definitions
** I2C accesses required in order to toggle PHY Reset. See I2C Multiplexer section of user guide.
The datasheet for the Marvell 88E1512 is not available publicly. An NDA is required for this
information. Please contact your local Avnet or Marvell representatives for assistance.
2.7
HDMI Input
The HDMI input interface is implemented using the Analog Devices ADV7611 device. This device’s
output video interface supports YCbCr mode with embedded syncs, which significantly reduce the
number of I/O required for the MicroZed™ interface.
The decision to use the YCbCr 4:2:2 modes save interface pins because the pixels are 16 bits
instead of 24 bits. This is acceptable since the many of the available video reference designs use
the YCbCr 4:2:2 video formats.
The following block diagram illustrates the connections between the micro-HDMI connector, the
HDMI Receiver, and the MicroZed™.
Page 16
Figure 6 – HDMI Input Block Diagram
The HDMII_SCL/SDA signals are connected to an I2C SWITCH device. The HDMII_RST# and
HPD signals are connected to an I2C IO Expander device. See the relevant sections for the I2C
SWITCH and I2C IO Expander for details on asserting the signals connected to these devices.
The MicroZed™ I/O connections for the HDMI Input is described in the following table.
Page 17
Signal
Name
Description
Micro Header
Connection
Zynq
Pin
ADV7611
Pin
HDMII_CBCR0
HDMI Input Data Bus
JX1 – 38
Bank 34 – W15
43
HDMII_CBCR1
HDMI Input Data Bus
JX1 – 36
Bank 34 – V15
42
HDMII_CBCR2
HDMI Input Data Bus
JX1 – 31
Bank 34 – Y17
41
HDMII_CBCR3
HDMI Input Data Bus
JX1 – 29
Bank 34 – Y16
39
HDMII_CBCR4
HDMI Input Data Bus
JX1 – 32
Bank 34 – Y14
38
HDMII_CBCR5
HDMI Input Data Bus
JX1 – 30
Bank 34 – W14
37
HDMII_CBCR6
HDMI Input Data Bus
JX1 – 25
Bank 34 – T15
36
HDMII_CBCR7
HDMI Input Data Bus
JX1 – 23
Bank 34 – T14
35
HDMII_Y0
HDMI Input Data Bus
JX1 – 26
Bank 34 – R14
33
HDMII_Y1
HDMI Input Data Bus
JX1 – 24
Bank 34 – P14
32
HDMII_Y2
HDMI Input Data Bus
JX1 – 20
Bank 34 – W13
31
HDMII_Y3
HDMI Input Data Bus
JX1 – 18
Bank 34 – V12
30
HDMII_Y4
HDMI Input Data Bus
JX1 – 14
Bank 34 – U12
29
HDMII_Y5
HDMI Input Data Bus
JX1 – 12
Bank 34 – T12
28
HDMII_Y6
HDMI Input Data Bus
JX1 – 13
Bank 34 – T10
27
HDMII_Y7
HDMI Input Data Bus
JX1 – 11
Bank 34 – T11
26
HDMII_CLK
HDMI Input Clock
JX1 – 42
Bank 34 – U18
25
HDMI_IO_INT#
HDMI Shared Interrupt
JX1 – 19
Bank 34 – V13
55
HDMII_SPDIF_H
HDMI Input Digital Audio
JX2 – 82
Bank 35 – L14
48
HDMII_SCL
HDMI Input I2C Clock
** I2C SWITCH
N/A
53
HDMII_SDA
HDMI Input I2C Data
** I2C SWITCH
N/A
54
HDMII_RST#
HDMI Input Reset
** I2C EXPANDER
N/A
56
HDMII_HPD_CTRL
HDMI Hot Plug Detect
** I2C EXPANDER
N/A
1
Table 12 – HDMI Input MicroZed™ I/O Connections
More detailed information on the ADV7611, including a hardware user guide and recommended
schematic/layout/BOM, can be found on the Analog Devices Engineer Zone:
http://ez.analog.com/docs/DOC-1745
2.8
HDMI Output
The HDMI output interface is implemented using the Analog Devices ADV7511 device. This
device’s input video interface supports YCbCr mode with embedded syncs, which significantly
reduce the number of I/O required for the MicroZed™ interface.
The decision to use the YCbCr 4:2:2 modes save interface pins because the pixels are 16 bits
instead of 24 bits. This is acceptable since the many of the available video reference designs use
the YCbCr 4:2:2 video formats.
The following block diagram illustrates the connections between the micro-HDMI connector, the
HDMI Transmitter, and the MicroZed™.
Page 18
Figure 7 – HDMI Output Block Diagram
The HDMIO_SCL/SDA and HDMIO_DDC_SCL/SDA signals are connected to an I2C SWITCH
device. The HDMIO_PD and HDMIO_HPD signals connected to an I2C IO Expander device. See
the relevant sections for the I2C SWITCH and I2C IO Expander for details on asserting the signals
connected to these devices.
The MicroZed™ I/O connections for the HDMI Output is described in the following table.
Page 19
Signal
Name
Description
Micro Header
Connection
Zynq
Pin
ADV7611
Pin
HDMIO_CBCR0
HDMI Output Data Bus
JX1 - 83
Bank 34 – P18
64
HDMIO_CBCR1
HDMIO_CBCR2
HDMI Output Data Bus
HDMI Output Data Bus
JX1 - 81
JX1 - 84
Bank 34 – N17
Bank 34 – P16
63
62
HDMIO_CBCR3
HDMIO_CBCR4
HDMI Output Data Bus
HDMI Output Data Bus
JX1 - 82
JX2 - 75
Bank 34 – P15
Bank 35 – J14
61
60
HDMIO_CBCR5
HDMI Output Data Bus
JX2 - 73
Bank 35 – K14
59
HDMIO_CBCR6
HDMI Output Data Bus
JX2 - 76
Bank 35 – G15
58
HDMIO_CBCR7
HDMI Output Data Bus
JX2 - 74
Bank 35 – H15
57
HDMIO_Y0
HDMI Output Data Bus
JX1 - 64
Bank 34 – W16
72
HDMIO_Y1
HDMI Output Data Bus
JX1 - 62
Bank 34 – V16
71
HDMIO_Y2
HDMI Output Data Bus
JX1 - 63
Bank 34 – Y19
70
HDMIO_Y3
HDMI Output Data Bus
JX1 - 61
Bank 34 – Y18
69
HDMIO_Y4
HDMI Output Data Bus
JX1 - 44
Bank 34 – U19
68
HDMIO_Y5
HDMIO_Y6
HDMI Output Data Bus
HDMI Output Data Bus
JX1 - 43
JX1 - 36
Bank 34 – U15
Bank 34 – V15
67
66
HDMIO_Y7
HDMI Output Data Bus
JX1 - 35
Bank 34 – T16
65
HDMIO_CLK
HDMI Output Clock
JX1 - 41
Bank 34 – U14
79
HDMI_IO_INT#
HDMI Shared Interrupt
JX1 - 19
Bank 34 – V13
45
HDMIO_SPDIF
HDMIO Output Digital Audio
JX2 - 84
Bank 35 – L15
10
HDMIO_SCL
HDMIO_SDA
HDMI Output I2C Clock
HDMI Output I2C Data
** I2C SWITCH
** I2C SWITCH
N/A
N/A
55
56
HDMIO_DDC_SCL
HDMIO_DDC_SDA
HDMI Output DDC I2C Clock
HDMI Output DDC I2C Data
** I2C SWITCH
** I2C SWITCH
N/A
N/A
53
54
HDMIO_PD
TX_HPD_FPGA
HDMI Output Power Down
HDMI Hot Plug Detect
** I2C EXPANDER
** I2C EXPANDER
N/A
N/A
38
30
Table 13 – HDMI Output MicroZed™ I/O Connections
More detailed information on the ADV7511, including a hardware user guide and example
schematics/layout/BOM, can be found on the Analog Devices Engineer Zone:
http://ez.analog.com/docs/DOC-1740
2.9
JTAG Interface
The Embedded Vision Carrier Card requires an external JTAG cable connector populated on the
carrier card for JTAG operations. JTAG signals are routed from Bank 0 of the Zynq to the
MicroZed™ Micro Header JX1. The Embedded Vision Carrier Card then routes the JTAG signals
on Micro Header JX1 to the Xilinx Compatible JTAG Header, J1. The following table shows the
JTAG signal connections between the Micro Header JX1 and JTAG Connector J1.
Carrier Card Net Name
Micro Header JX1 Pin #
JTAG Connector J1 Pin #
JTAG_TCK
1
6
JTAG_TMS
2
4
JTAG_TDO
3
8
JTAG_TDI
4
10
Table 14 – Carrier Card JTAG Connections
Page 20
The Zynq Bank 0 reference voltage, Vcco_0, is connected to 3.3V. The JTAG Vref on the Embedded
Vision Carrier Card is also connected to 3.3V to ensure compatibility between the interfaces.
2.10 Audio Interfaces
The Embedded Vision Carrier Card implements an audio codec circuit to drive the audio jacks
available on board.
The Analog Devices ADAU1761 is a low power, stereo audio codec with integrated digital audio
processing that supports stereo 48 kHz record and playback. The stereo audio ADCs and DACs
support sample rates from 8 kHz to 96 kHz as well as a digital volume control.
The audio jack interface consists of two Kycon STX4235-3/3-N dual 3.5mm audio jacks CON4 (A
and B) and CON5 (A and B) for a total of four audio jacks.
CON4A (top jack) is a headphone output, CON4B (bottom jack) is Stereo single-ended output,
CON5A (top jack) is configured as a differential input to the codec and CON5B (bottom jack) is a
stereo single-ended input.
The figure below shows the appearance of the audio jacks.
Figure 8 – Audio Jack Connector
The table below shows the signal connections to the MicroZed™ JX2 Micro Header connector.
Signal
Name
AUD_GPIO_0
AUD_GPIO_1
AUD_GPIO_2
AUD_GPIO_3
AUD_MCLK
Description
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
MCLK
Micro Header
Connection
JX2 – 93
JX2 – 95
JX2 – 94
JX2 – 96
JX2 – 97
Zynq
Pin
Bank 13 – Y12
Bank 13 – Y13
Bank 13 – V11
Bank 13 – V10
Bank 13 – V6
ADAU1761
Pin
27
26
28
29
2
AUD_ADR_0
AUD_ADR_1
AUD_SCL
AUD_SDA
ADDR0/CLATCH#
ADDR1/CDATA
SCL/CCLK
SDA/COUT
JX2 – 100
JX2 – 99
** I2C SWITCH
** I2C SWITCH
Bank 13 – V5
Bank 13 – W6
N/A
N/A
3
30
32
31
Table 15 – Audio Codec Pin Assignments
** The AUD_SCL/SDA signals are connected to an I2C SWITCH device. See the relevant
sections for the I2C SWITCH for details on asserting the signals connected to the ADAU1761.
Page 21
2.11 Camera Interface
The Embedded Vision Carrier Card can accommodate a variety of camera modules with its camera
interface, which defines pins for the following functions:
–
–
–
2.11.1
Configuration & Control (single-ended signals)
– I2C
– SPI
– Reset/Reference Clock
– Trigger
– Monitor
– LED control
Video (differential signals)
– CLK
– SYNC
– DATA[7:0]
Power
– 5V, used by camera modules to create on-board voltages
– 2.5V, same as VCCO used for single-ended I/O
Camera Connector
The connector used to house the Camera Modules is a standard PCI Express connector. The
x4 connector is chosen in order to support all the signals required by the camera interface (10
differential pairs, 16 single-ended signals).
The connector chosen for the PCI Express connector is a right-angle (RA) version depicted in
the image below, PCIE-064-02-F-D-RA. The right-angle (RA) connector is used with additional
standoffs to hold the camera board in parallel to the carrier card.
More information is available for the PCI Express connectors at Samtec’s website:
http://www.samtec.com/documents/webfiles/pdf/pcie.pdf
Figure 9 – PCIEx4 Camera Connector
Although not included in the kit(s), it is possible to use an extender cable for the PCI Express
x4 connector.
More information is available for the PCIex4 extender cable at Samtec’s website:
http://www.samtec.com/technical-specifications/Default.aspx?SeriesMaster=PCIEC
Page 22
2.11.2
Mapping the Camera Interface
The following table describes the proprietary camera interface pin assignment on the Right
Angle PCIe x4 Lane Connector (Samtec: PCIE-064-02-F-D-RA).
Zynq Pin
Micro Header
Connection
Mapping for Camera Interface
Side B
Side A
Micro Header
Connection
Zynq Pin
PCI Express x1
-
-
GND
GND
-
-
-
VIN_HDR
+5V
CAM_REFCLK
JX2 – 17
Bank 35 – C20
-
VIN_HDR
+5V
GND
-
-
-
VIN_HDR
+5V
CAM_CLK_P
JX2 – 53
Bank 35 – H16
-
VIN_HDR
+5V
CAM_CLK_N
JX2 – 55
Bank 35 – H17
-
** I2C SWITCH
CAM_I2C_SCL
GND
-
-
-
VCCO_35
+2.5V
CAM_D0_P
JX2 – 41
Bank 35 – M17
-
VCCO_35
+2.5V
CAM_D0_N
JX2 – 43
Bank 35 – M18
-
** I2C SWITCH
CAM_I2C_SDA
GND
-
-
-
VCCO_35
+2.5V
CAM_D1_P
JX2 – 42
Bank 35 – K19
-
VCCO_35
+2.5V
CAM_D1_N
JX2 – 44
Bank 35 – J19
Key Notch
Bank 35 - M14
JX2 – 87
CAM_SPI_CLK
GND
-
-
-
-
GND
CAM_D2_P
JX2 – 36
Bank 35 – M19
Bank 35 - N15
JX2 – 81
CAM_SPI_CS
CAM_D2_N
JX2 – 38
Bank 35 – M20
Bank 35 - N16
JX2 – 83
CAM_SPI_MISO
GND
-
-
-
-
GND
CAM_D3_P
JX2 – 35
Bank 35 – L19
-
-
GND
CAM_D3_N
JX2 – 37
Bank 35 – L20
Bank 35 - M15
JX2 – 89
CAM_SPI_MOSI
GND
-
-
-
-
GND
CAM_D4_P
JX2 – 30
Bank 35 – F16
Bank 34 - U13
JX1 – 17
CAM_RST#
CAM_D4_N
JX2 – 32
Bank 35 – F17
-
** I2C EXPAND
CAM_PWDN
GND
-
-
-
-
GND
CAM_D5_P
JX2 – 29
Bank 35 – E18
Bank 35 - G14
JX2 – 13
CAM_TRIGGER0
CAM_D5_N
JX2 – 31
Bank 35 – E19
Bank35 - B19
JX2 – 18
CAM_MONITOR0
GND
-
-
PCI Express x4
Bank 35 - J15
JX2 – 14
CAM_TRIGGER1
CAM_D6_P
JX2 – 24
Bank 35 – D19
Bank 35 - B20
JX2 – 19
CAM_TRIGGER2
CAM_D6_N
JX2 – 26
Bank 35 – D20
Bank 35 - A19
JX2 – 20
CAM_MONITOR1
GND
-
-
-
-
GND
CAM_D7_P
JX2 – 23
Bank 35 – E17
Bank 500 – E6
JX2 – 5
CAM_TORCH_EN
CAM_D7_N
JX2 – 25
Bank 35 – D18
Bank 500 – B5
JX2 – 6
CAM_TORCH_PWM
GND
-
-
-
-
GND
CAM_SYN_P
JX2 – 48
Bank 35 – K17
-
-
GND
CAM_SYN_N
JX2 – 50
Bank 35 – K18
Table 16 – Camera Interface Pin Assignments
Page 23
2.11.3
Camera Implementation
SINGLED-ENDED SIGNALS
All of the single-ended signals on the camera interface are 2.5V.
All of the CAM_* signals on the camera connector are directly connected to the Zynq device
on a common 2.5V I/O bank. If the camera module requires these signals to be at a different
voltage level, they need to be voltage level translated on the camera module, as illustrated in
the following figure.
Figure 10 – Camera Module Block Diagram
Note: On the Embedded Vision Carrier Card, the CAM_TORCH_EN and CAM_TORCH_PWM
(USER IO1 and USER_IO2) signals are driven from the Zynq’s PS MIO pins (3.3V). They are
therefore voltage level translated to 2.5V.
I2C CONFIGURATION INTERFACE
The Embedded Vision Carrier Card uses an I2C multiplexer that is configured at I2C address
0xE0/0xE1. For this reason, the camera module MUST NOT implement any I2C device at I2C
address 0xE0/0xE1.
The Embedded Vision Carrier Card implements the I2C pull-ups. For this reason, the camera
module WILL NOT implement any pull-ups on the I2C interface (if used).
Page 24
Figure 11 – Camera I2C Interface
LED ILLUMINATION CONTROL
There are several ways to control LED illumination on a camera module.
Basic configuration can be achieved using one of the two configuration interfaces (I2C or SPI).
In addition, two USER_IO can be used to control the LED illumination:
CAM_TORCH_EN (USER_IO1): Can be used to enabled/disable the LED illumination.
CAM_TORCH_PWM (USER_IO2): Can be used to control the intensity of the LED illumination
using PWM.
If the image sensor supports external triggering, one of the three signals, CAM_TRIGGER[2:0],
can be used to trigger the LED illumination in order to implement a “camera flash” type
illumination.
DIFFERENTIAL SIGNALS
Image sensors may use any of the following electrical signaling:
–
–
–
–
LVDS
Sub-LVDS
HiSPI
MIPI CSI-2
The Embedded Vision Carrier Card does not contain any special circuitry for these I/O
standards. All I/O standard specific circuitry should be placed on the camera modules.
LVDS EXAMPLE
LVDS has a common mode voltage of 1.25V, and a swing of 350mV.
The following circuit illustrates how the differential pairs of an LVDS image sensor can be
directly connected to the Zynq device.
Page 25
Figure 12 – Camera LVDS Interface
In this case the Zynq device would use the “LVDS_25” I/O standard, with internal differential
termination “DIFF_TERM = TRUE”, on a 2.5V I/O bank.
Examples of image sensor using LVDS include:
– ON Semiconductor: VITA, PYTHON
CAMERA MODULE EXAMPLE DESIGNS
Many sensor types can be implemented to function with the camera interface on the Embedded
Vision Carrier Card. Two such examples of implementation of camera modules are the Avnet –
ON Python Camera Module and the Avnet – Toshiba 1080P Camera Module.
TOSHIBA INDUSTRIAL 1080P60 CAMERA MODULE:
http://microzed.org/product/toshiba-industrial-1080p60-camera-module
ON PYTHON-1300-C CAMERA MODULE:
http://microzed.org/product/python-1300-c-camera-module
CAMERA MODULE DESIGN GUIDE
If the Avnet – ON Python Camera Module or the Avnet – Toshiba 1080P Camera Module do
not fit your final solutions requirements, a custom camera module can be generated.
Leveraging Avnet’s MicroZed™ Embedded vision Camera Design Guide for direction in
development of a supported camera module is recommended.
Please visit the following website for the latest version of the MicroZed™ Embedded vision
Camera Design Guide:
(INSERT WEB LINK TO THE CAMERA DESIGN GUIDE – ARE WE POSTING THIS)
Page 26
2.12 I2C SWITCH Interface
The Embedded Vision Carrier Card interfaces to several on-board I2C compatible devices and
interfaces. These devices and interfaces include the I2C IO Expander, HDMI Input, HDMI Output,
HDMI DDC, Audio Codec, and the Camera Interface. Communication between the devices on the
Embedded Vision Carrier Card and the Zynq-7000 AP SoC on the MicroZed™ is done through a
Texas Instruments PCA9548A 8-chanel I2C multiplexer or switch. Only six of the channels are used.
The I2C switch is driven by an I2C Master that resides in the PS of the Zynq-7000 AP SoC on
MicroZed™.
The figure below shows a high level diagram of the I2C Switch circuit on the Embedded Vision
Carrier Card.
Figure 13 – I2C Switch Block Diagram
The Texas Instruments PCA9548A I2C Multiplexer serves two purposes:
– Support for MicroZed™ 7010 or 7020 System on Module
– Support for MicroZed™ 7010 or 7020 System on Module
Page 27
The following table lists the I2C addresses that may be present on each of the I2C switch ports.
Notice that the I2C Multiplexer’s address is always visible regardless of which port is enabled.
SW1 Setting
I2C Multiplexer
I/O Connection
0xE0 (PCA9548)
Mux Port 1
I2C I/O Expander
0x40 (PCA9534)
Mux Port 2
HDMI Input
0x98 (ADV7611) *
Mux Port 3
HDMI Output
0x72 (ADV7511) *
Mux Port 4
HDMI Output DDC EDID
0xA0
Mux Port 5
Audio Codec
0x74 or 0x76 (ADAU1761) **
Mux Port 6
Camera Interface
Module Dependent ***
Table 17 – I2C Peripheral Device Summary
* See the ADV7611/ADV7511 datasheets for other register addresses
** ADAU1761 address is programmable. See data sheet.
*** Camera Interface address depends on camera module design
2.13 I2C I/O Expander Interface
The Embedded Vision Carrier Card implements many features that require additional I/Os outside
the available I/Os provided via the MicroZed™ Micro Headers. To accomplish the requirement for
the additional I/Os, an I2C I/O Expander was implemented to handle various controls signals
attached to peripherals.
Communication between the Zynq-7000 AP
SoC and the I2C I/O Expander is facilitated
by passing an I2C interface through one of
the six channels of the Texas Instruments
PCA9548A 8-chanel I2C switch. See the
previous section, I2C Switch Interface, for
details on accessing the I2C Switch.
The I2C I/O Expander is accomplished with
the use of a Texas Instruments PCA9534.
The I2C I/O Expander takes an I2C interface
from the I2C Switch and decodes that to
provide 8 USER GPIO on its outputs. This is
an ideal device for the control signal support
that was required by the peripherals.
The figure below shows a high level diagram
of the I2C I/O Expander circuit on the
Embedded Vision Carrier Card.
Page 28
Figure 14 – I2C I/O Expander Block Diagram
The table below shows the signals that the I2C I/O Expander circuit on the Embedded Vision
Carrier Card can control.
Control Signal
Function
Default Value
Direction
Expander Port
HDMII_RST#
HDMI Input Reset
Pulled-High
Output
P0
TP2
Test Point – 2
Open
I/O
P1
HDMII_HPD_CTRL
HDMI Input Hot Plug Detect Control
Pulled-Low
Output
P2
TX_HPD_FPGA
HDMI Output Hot Plug Detect
Pulled-Low
Input
P3
HDMIO_PD
HDMI Output Power Down
Pulled-Low
Output
P4
ETH_RST#
Gigabit Ethernet Reset
Pulled-High
Output
P5
CAM_PWDN_H
Camera Interface Power Down
Pulled-High
Output
P6
TP54
Test Point – 54
Open
I/O
P7
Table 18 – I2C IO Expander Signal Summary
2.14 Power Supplies
2.14.1
Voltage Rails and Sources
The Embedded Vision Carrier Card is powered through the two physical connections to the
board. The primary board power is +5V and is supplied via the Power Supply Jack, CON8. This
connector is a CUI PJ-002BH. It is a 2.5mm Center Pin, 5.0A, right angle through-hole DC
power jack connector. The outer-hole diameter is 6.5mm. Another source for the primary board
power is +5V supplied through a Power-Over-Ethernet circuit. The reference design for the
Power-Over-Ethernet circuit is provided by STMicroelectronics. More details of the PowerOver-Ethernet circuitry will follow later in this section.
There are three regulators that reside on the Embedded Vision Carrier Card that provide 1.8V,
2.5V and 3.3V power rails. These voltages are used to power the peripheral devices on the
Embedded Vision Carrier Card as well as provide bank voltages to the MicroZed™. The
regulators are provided by STMicroelectronics. A 500mA very low drop voltage regulator,
LDFM, is used to generate 1.8V. The other two regulators are ST1S32 devices. These are 4A
DC step-down switching regulators and are used to generate 3.3V and 2.5V.
These regulators are powered from the selected +5V source. The +5V source selection is
determined by the position of Single Pole Switch, SW2. The Single Pole Switch is a C&K 1103M2-S3-C-Q-E-2. It supports three positions, ON-OFF-ON. The default is the center position,
OFF. Moving the switch to the LEFT ON position will select the PoE as the source of the +5V.
Moving the switch to the RIGHT ON position will select the Power Jack as the source of
the +5V.
Page 29
The diagram below shows a high level depiction of the power scheme for Embedded Vision
Carrier Card.
Figure 15 – Embedded Vision Carrier Card Power Scheme
2.14.2
Voltage Regulators
The following power solution provides the power rails of the Embedded Vision Carrier Card.
Control of the supply enables is implemented by utilizing the POWER GOOD outputs of each
supply to the ENABLE the next supply in the sequence.
3.3V is the first supply to come up on the Embedded Vision Carrier Card after the MicroZed™
1.8V is valid and it pulls up it 1.8V POWER GOOD. This signal becomes VCCIO_EN on the
Embedded Vision Carrier Card and it is used to enable the 3.3V power rail. Once the carrier
card 3.3V power rail is valid, it pulls up its power good, PG_3V3.
PG_3V3 is used to enable the 2.5V power rail on the Embedded Vision Carrier Card. PG_3V3
comes from the POWER GOOD on the 3.3V power rail. Once the 2.5V power rail is valid, it
pulls up its power good, PG_CARRIER. PG_CARRIER is shared with the MicroZed™ net
PG_MODULE. These signals being released allows the net to be pulled high indicated all
power supplies are valid on the combination of the MicroZed™ and the Embedded Vision
Carrier Card. This is signaled via a GREEN LED, LED6.
The last regulator, the 1.8V regulator, is enabled by 2.5V rail.
Page 30
The table below shows the maximum output current for each of the STMicroelectronics
regulators on the Embedded Vision Carrier Card.
ST Part Number
Input Voltage Range (V)
Input Voltage (V)
Output Voltage (V)
Max Current (mA)
ST1S32
2.8V to 5.5V
5V
3.3V
4000mA
ST1S32
2.8V to 5.5V
5V
2.5V
4000mA
LDFM
2.5 to 16V
2.5V
1.8V
500mA
Table 19 – Voltage Rails w/ Max Output Current
2.14.3
Power LEDs
Three GREEN power status LEDs are provided on the Embedded Vision Carrier Card: LED4,
LED5, and LED6. The first two LEDs, LED4 and LED5, illuminate based on the +5V input
source selection. LED4 illuminates when PoE is selected as the +5V source and LED 5
illuminates when the Power Jack is selected as the +5V source. The final LED, LED6,
illuminates when the Embedded Vision Carrier Card power is good. This is controlled by the
PG signal out of the 2.5V power rail.
2.14.4
Power-On-Reset
The POR# button, BTN3, provides an active low signal to the PG_CARRIER net on the JX2
Micro Header pin 11. When asserted, this signal resets the MicroZed™ USB UART, USB OTG
circuit and turns off MicroZed™ power supplies. It is used to invoke a MicroZed™ total system
power reset. The PS and PL are reset to power on default settings and the selected boot
process is initiated.
Carrier Card Net Name
Micro Header JX1 Pin #
JTAG Connector J1 Pin #
JTAG_TCK
1
6
JTAG_TMS
2
4
JTAG_TDO
3
8
JTAG_TDI
4
10
Table 20 – POR Push Button – BTN3
Page 31
2.14.5
Power-Over-Ethernet
The reference design for the Power-Over-Ethernet circuit is provided by STMicroelectronics.
The Power-Over-Ethernet design features STMicroelectronics PM8803 Power-Over-Ethernet
interface and STL65N3LLH5 StripFET™ V Power MOSFET.
The output result of the Power-Over-Ethernet conversion is the +5V power supply that sources
the regulators in the Embedded Vision Carrier Card and serves as the main supply rail to the
MicroZed™.
The PM8803 integrates a standard compliant Power over Ethernet (PoE) interface and a
current mode PWM controller to simplify the design of the power supply sections of all powered
devices. The PoE/PoE+ interface incorporates all the functions required by the IEEE 802.3at
including detection, classification, under-voltage lockout (UVLO) and in-rush current limitation.
The PM8803 specifically performs IEEE802.3at Layer1 hardware classification, providing an
indication of Type 2 PSE successful detection to the rest of the system.
The PM8803 should provide up to 25.5W of power as it meets IEEE 802.3at requirements. This
translates to approximately 5.1A @ 5V.
Property
802.3at Type 2
Power available at PD
25.50 W
Maximum power delivered
by PSE
30.0 W
Voltage range (at PSE)
50.0–57.0 V
Voltage range (at PD)
42.5–57.0 V
Maximum current
600 mA per mode
Maximum cable resistance
12.5 Ω (Category 5)
Power management
Four power class levels negotiated at initial
connection or 0.1 W steps negotiated continuously
De-rating of maximum cable
ambient operating temperature
5°C with one mode (two pairs) active
Supported cabling
Category 5
Supported modes
Mode A, Mode B
Table 21 – Power-Over-Ethernet Parameters
Page 32
3 Mechanical
The Embedded Vision Carrier Card measures 2.25” x 4.00” (57.15 mm x 101.6 mm). Other pertinent
dimensions are presented in the following figure.
Figure 16 – Embedded Vision Carrier Card Top View Mechanical Dimensions
The Embedded Vision Carrier Card has a maximum vertical dimension of 0.366” (9.3mm)
Figure 17 – Embedded Vision Carrier Card Side View Vertical Dimension
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