LT8710 - Synchronous SEPIC/ Inverting/Boost

LT8710
Synchronous SEPIC/
Inverting/Boost Controller with
Output Current Control
Description
Features
Wide Input Range: 4.5V to 80V
Rail-to-Rail Output Current Monitor and Control
Input Voltage Regulation for High Impedance Inputs
C/10 or Power Good Indication Pin
MODE Pin for Forced CCM or Pulse-Skipping
Operation
n Switching Frequency Up to 750kHz
n Easily Configurable as a Boost, SEPIC, Inverting or
Flyback Converter with Single Feedback Pin
n Can Be Synchronized to External Clock
n High Gain EN/FBIN Pin Accepts Slowly Varying Input
Signals
n20-Lead TSSOP Package
n
n
n
n
The LT®8710 is a synchronous PWM DC/DC controller
with a rail-to-rail output current monitor and control. The
LT8710 is ideal for many types of power supply topologies
and can be easily configured for boost, SEPIC, inverting,
or flyback configurations.
n
The LT8710’s rail-to-rail output current monitor and control
allows the part to be configured in current limited applications such as battery charging. The FLAG pin can be used
as a power good indication or C/10 indication allowing for
accurate bulk and float battery voltages.
The LT8710’s switching frequency range can be set between 100kHz and 750kHz using an external resistor or
synchronized to an external clock.
Applications
n
n
n
n
n
The LT8710 also features innovative EN/FBIN pin circuitry that allows for slowly varying input signals and
an adjustable undervoltage lockout function. The pin is
also used for input voltage regulation to avoid collapsing
a high impedance input supply. Additional features such
as frequency foldback and soft-start are integrated. The
LT8710 is available in a 20-lead TSSOP package.
High Power Local Power Supply
Wide Input Voltage Range SEPIC/Inverting
Lead Acid Battery Charger
Automotive Engine Control Unit (ECU) Power
Solar Panel Power Converter
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, Including 7579816.
Typical Application
300kHz Inverter Generates –5V from a 4.5V to 25V Input
2.2µH
VOUT
–5V
7A
•
2.2µH
•
VIN
4.5V TO 25V
Efficiency and Power Loss
+
0.47µF
+
BG
VIN
ISN
ISP
LT8710
EN/FBIN
10µF
×4
10k
2.2µF
BIAS
INTVEE
MODE
2.2µF
INTVCC
60.4k
FBX
INTVCC
7
80
6
70
5
65
4
50
3
40
2
30
20
1
VIN = 5V
VIN = 12V
0
1
2
3
4
5
LOAD CURRENT (A)
6
7
0
8710 TA01b
FLAG
VC
RT
118k
SYNC
100µF
×2
CSN CSP TG
13.3k
120µF
90
330µF
1.5m
4m
8
POWER LOSS (W)
499Ω
100
EFFICIENCY (%)
10µF ×2
GND
IMON
SS
47nF
100pF
220nF
11.5k
3.3nF
8710 TA01a
8710f
For more information www.linear.com/LT8710
1
LT8710
Absolute Maximum Ratings
(Note 1)
VIN Voltage ................................................. –0.3V to 80V
BIAS Voltage............................................... –0.3V to 80V
EN/FBIN Voltage.......................................... –0.3V to 80V
BG Voltage.............................................................Note 5
TG Voltage.............................................................Note 5
RT Voltage.................................................... –0.3V to 5V
SS Voltage.................................................... –0.3V to 3V
FBX Voltage..................................................................5V
FBX Current.............................................................–1mA
VC Voltage..................................................... –0.3V to 2V
SYNC Voltage............................................. –0.3V to 5.5V
FLAG Voltage................................................ –0.3V to 7V
FLAG Current.......................................................... ±1mA
MODE Voltage............................................. –0.3V to 40V
INTVCC Voltage............................................. –0.3V to 7V
INTVEE Voltage......................................................Note 5
CSP Voltage.................................................. –0.3V to 2V
CSN Voltage.................................................. –0.3V to 2V
ISP Voltage.................................. ISN – 0.4V to ISN + 2V
ISN Voltage................................................. –0.3V to 80V
IMON Voltage............................................. –0.3V to 2.5V
Operating Junction Temperature Range
LT8710E.............................................. –40°C to 125°C
LT8710I............................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Pin Configuration
TOP VIEW
FBX
1
20 GND
VC
2
19 SYNC
SS
3
18 RT
FLAG
4
IMON
5
ISN
6
ISP
7
14 CSN
BIAS
8
13 VIN
INTVEE
9
12 INTVCC
17 MODE
21
GND
TG 10
16 EN/FBIN
15 CSP
11 BG
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8710EFE#PBF
LT8710EFE#TRPBF
LT8710FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8710IFE#PBF
LT8710IFE#TRPBF
LT8710FE
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
8710f
For more information www.linear.com/LT8710
LT8710
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
MIN
Minimum Operating Input Voltage
VIN OR VBIAS
VIN if VBIAS ≥ 4.5V
Quiescent Current, IVIN
VBIAS = VISN = 7.5V, Not Switching
VBIAS = 6.3V, VINTVEE = VISN = 0V, Not Switching
Quiescent Current in Shutdown
VEN/FBIN = 0V
EN/FBIN Active Mode
EN/FBIN Chip Enable
l
0
TYP
MAX
UNITS
4.25
4.5
V
V
4
5.5
5.5
7.5
mA
mA
0
1
µA
EN/FBIN Rising
l
1.64
1.7
1.76
V
EN/FBIN Rising
EN/FBIN Falling
l
l
1.22
1.18
1.3
1.26
1.38
1.34
V
V
EN/FBIN Chip Enable Hysteresis
44
EN/FBIN Input Voltage Low
Shutdown Mode
EN/FBIN Pin Bias Current
VEN/FBIN = 3V
VEN/FBIN = 1.7V
VEN/FBIN = 1.6V
VEN/FBIN = 0V
SS Charge Current
VSS = 0V, Current Flows Out of SS Pin
SS Low Detection Voltage
Part Exiting Undervoltage Lockout
SS Hi Detection Voltage
SS Rising
SS Falling
l
mV
0.3
V
µA
µA
µA
µA
14
13
44
19.5
17.5
0
60
25
22.5
0.1
l
7
10.1
13.8
µA
l
18
50
82
mV
1.5
1.3
1.8
1.7
2.1
2.05
SS Hi Detection Hysteresis
100
V
V
mV
Low Dropout Regulators, INTVCC and INTVEE
INTVCC Voltage
IINTVCC = 10mA
l
6.2
6.3
6.4
V
INTVCC Undervoltage Lockout
INTVCC Rising
INTVCC Falling
l
l
3.88
3.5
4
3.73
4.12
3.95
V
V
INTVCC Undervoltage Lockout Hysteresis
270
mV
255
280
mV
mV
INTVCC Dropout Voltage
VIN – INTVCC, VIN = 6V, VBIAS = 0V, IINTVCC = 10mA
VBIAS – VINTVCC, VIN = 0V, VBIAS = 6V, IINTVCC = 10mA
INTVCC Load Regulation
VIN = 12V, VBIAS = 0V, IINTVCC = 0mA to 80mA
VIN = 0V, VBIAS = 12V, IINTVCC = 0mA to 40mA
–0.44
–0.34
–2
–2
INTVCC Line Regulation
10V ≤ VIN ≤ 80V, VBIAS = 0V, IINTVCC = 10mA
10V ≤ VBIAS ≤ 80V, VIN = 0V, IINTVCC = 10mA
–0.003
–0.006
–0.03
–0.03
%/V
%/V
5
mA
INTVCC Maximum External Load Current
INTVEE Voltage, VBIAS – VINTVEE
IINTVEE = 10mA
l
INTVEE Undervoltage Lockout,
VBIAS – VINTVEE
VBIAS – VINTVEE Rising
VBIAS – VINTVEE Falling
l
l
6.03
6.18
6.33
V
3.24
2.94
3.42
3.22
3.6
3.48
V
V
INTVEE Undervoltage Lockout
Hysteresis, VBIAS – VINTVEE
INTVEE Dropout Voltage, VINTVEE
%
%
VBIAS = 6V, IINTVEE = 10mA
200
mV
0.75
V
Control Loops (Refer to Block Diagram to Locate Amplifiers)
Current Limit Voltage, VCSP – VCSN
VFBX = 1.1V, Minimum Duty Cycle
VFBX = 1.1V, Maximum Duty Cycle
l
l
46
23
50
31
54
38
mV
mV
VFBX = 1.4V, MODE = 0V, Minimum Duty Cycle
VFBX = 1.4V, MODE = 0V, Maximum Duty Cycle
l
l
–23
–38
–32
–51
–41
–65
mV
mV
FBX Positive Output Regulation Voltage,
EA1
l
1.191
1.213
1.237
FBX Negative Output Regulation Voltage,
EA2
l
–2
9.6
21
V
mV
8710f
For more information www.linear.com/LT8710
3
LT8710
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
Positive FBX Pin Bias Current
VFBX = Positive FBX Reg Voltage, Current into Pin
Negative FBX Pin Bias Current
VFBX = Negative FBX Reg Voltage, Current Out of Pin
FBX Amp Transconductance,
EA1 or EA2
ΔI = 2μA
MIN
TYP
MAX
UNITS
l
81.9
83.7
85.6
µA
l
81.1
83.1
85.2
µA
FBX Amp Voltage Gain, EA1 or EA2
200
µmhos
70
V/V
FBX Line Regulation
4.5V ≤ VIN ≤ 80V, VBIAS = 0V
–0.02
–0.001
0.02
%/V
Output Current Sense Regulation
Voltage, VISP – VISN
VISN = 80V, VFBX = 1V
VISN = 12V, VFBX = 1V
VISN = 0V, VFBX = 1V
VISN = 12V, VFBX = 1V, INTVEE in UVLO and VSS > 1.8V
l
l
l
l
43
43
40
17
50
50
50
25
57
57
60
34
mV
mV
mV
mV
IMON Regulation Voltage, EA3
VFBX = 1V
VFBX = 1V, INTVEE in UVLO and VSS > 1.8V
l
l
1.184
0.885
1.213
0.916
1.24
0.947
Output Current Sense Amp
Transconductance, A6
ΔI = 10μA
Output Current Sense Amp Voltage
Gain, A6
Output Current Sense Amp Input
Dynamic Range, A6
Negative Input Range, VISP – VISN
Positive Input Range, VISP – VISN
IMON Amp Transconductance, EA3
ΔI = 2μA, VFBX = 1V
IMON Amp Voltage Gain, EA3
VFBX = 1V
EN/FBIN Input Regulation Voltage, EA4
VFBX = 1V
500
1000
µmhos
11.9
V/V
–51.8
mV
mV
165
µmhos
65
l
1.55
V
V
1.607
V/V
1.662
V
EN/FBIN Amp Transconductance, EA4
ΔI = 2µA, VFBX = 1V
140
µmhos
EN/FBIN Amp Voltage Gain, EA4
VFBX = 1V
55
V/V
MODE Forced CCM Threshold
To Exit Forced CCM Mode, MODE Rising
To Enter Forced CCM Mode, MODE Falling
l
l
1.19
1.125
MODE Forced CCM Threshold
Hysteresis
1.224
1.175
1.258
1.23
49
V
V
mV
DCM Comparator Threshold in
Pulse-Skipping Mode, MODE = 2V
VISN = 80V, To Enter DCM Mode, VISP – VISN Falling
VISN = 12V, To Enter DCM Mode, VISP – VISN Falling
VISN = 0V, To Enter DCM Mode, VISP – VISN Falling
l
l
l
–4.5
–4.5
–7.5
2.8
2.8
2.8
10
10
13
mV
mV
mV
DCM Comparator Threshold in
Forced CCM, MODE =0V
VISN = 80V, To Enter DCM Mode, VISP – VISN Falling
VISN = 12V, To Enter DCM Mode, VISP – VISN Falling
VISN = 0V, To Enter DCM Mode, VISP – VISN Falling
l
l
l
–220
–220
–220
–300
–300
–300
–380
–380
–380
mV
mV
mV
Switching Frequency, fOSC
RT = 46.4k
RT = 357k
l
l
640
85
750
100
860
115
kHz
kHz
Switching Frequency in Foldback
Compared to Normal fOSC
Switching Frequency Range
Free-Running or Synchronizing
Oscillator
1/5
l
100
SYNC High Level for Sync
l
1.5
SYNC Low Level for Sync
l
SYNC Clock Pulse Duty Cycle
VSYNC = 0V to 3V
750
kHz
V
20
0.4
V
80
%
3/4
Recommended Min SYNC Ratio
fSYNC/fOSC
4
ratio
8710f
For more information www.linear.com/LT8710
LT8710
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers, BG and TG
BG Rise Time
CBG = 3300pF (Note 3)
24
ns
BG Fall Time
CBG = 3300pF (Note 3)
21
ns
TG Rise Time
CTG = 3300pF (Note 3)
15
ns
TG Fall Time
CTG = 3300pF (Note 3)
16
ns
BG and TG Non-Overlap Time
TG Rising to BG Rising, CBG = CTG = 3300pF (Note 3)
BG Falling to TG Falling, CBG = CTG = 3300pF (Note 3)
80
45
BG Minimum On-Time
CBG = CTG = 3300pF
BG Minimum Off-Time
TG Minimum On-Time
TG Minimum Off-Time
140
90
220
150
ns
ns
150
420
ns
CBG = CTG = 3300pF
100
480
ns
CBG = CTG = 3300pF
0
150
ns
CBG = CTG = 3300pF
290
770
ns
16
23
mV
mV
C/10 and Power Good Indicators, FLAG
FLAG C/10 Indicator Threshold
VISP – VISN Falling, VFBX = 1.215V
VISP – VISN Rising, VFBX = 1.215V
l
l
1
4
FLAG C/10 Indicator Hysteresis
5
10
5
mV
FLAG Power Good Threshold for
Positive FBX Voltage
VFBX Rising, VISP – VISN = 0V
VFBX Falling, VISP – VISN = 0V
l
l
1.127
1.062
1.153
1.095
1.184
1.126
FLAG Power Good Threshold for
Negative FBX Voltage
VFBX Falling, VISP – VISN = 0V
VFBX Rising, VISP – VISN = 0V
l
l
46
103
68.5
126
90
152
FLAG Power Good Hysteresis for
Positive or Negative FBX Voltage
58
FLAG Anti-Glitch
Delay from C/10 or Power Good
Threshold Trip to FLAG Toggle
FLAG Output Voltage Low
100µA into FLAG Pin
FLAG Leakage Current
VFLAG = 7V, FLAG Off
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8710E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8710I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
mV
mV
mV
100
l
V
V
µs
9
50
mV
0.01
1
µA
Note 3: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 5: Do not apply a positive or negative voltage or current source to the
BG, TG, and INTVEE pins, otherwise permanent damage may occur.
8710f
For more information www.linear.com/LT8710
5
LT8710
Typical Performance Characteristics
Max Current Limit vs Duty Cycle
(CSP - CSN)
–25
–30
45
–35
40
–40
35
–45
30
–50
25
–55
–60
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
60
54
–28
50
52
–30
50
–32
48
–34
46
–36
44
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
1.2175
10.0
1.2150
7.5
1.2125
5.0
1.2100
2.5
POSITIVE FBX CURRENT INTO PIN (µA)
12.5
POSITIVE FBX VOLTAGE (V)
1.2200
100
85
85
84
84
83
83
82
82
81
81
80
–50
0
125
55.0
1.7
1.6
1.5
1.3
8710 G07
6
1.4
–25
0
25
50
75
TEMPERATURE (°C)
100
1.61
1.60
1.59
1.58
1.57
–50
80
125
–25
0
25
50
75
TEMPERATURE (°C)
52.5
1.2175
60
1.2150
55
1.2100
AVE ISP-ISN
47.5
1.2075
45.0
1.2050
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Output Current Sense Regulation
Voltage vs FBX (ISP-ISN and IMON)
1.2125
50.0
100
8710 G06
IMON
42.5
–50
1.6
1.2025
125
8710 G08
1.30
1.25
IMON
50
1.20
AVE ISP-ISN
45
1.15
40
1.10
35
1.05
30
0.6
0.7
0.8
0.9
1
FBX (V)
1.1
1.2
IMON (V)
EN/FBIN (V)
1.8
1.2
1.2
1.62
IMON (V)
AVERAGE ISP-ISN (mV)
1.9
1.1
0.8
1
SS (V)
1.63
Output Current Sense Regulation
Voltage (ISP-ISN and IMON)
57.5
0.9
1
FBX (V)
0.6
8710 G05
2.0
0.8
0.4
Input Voltage Regulation
(EN/FBIN)
86
Input Voltage Regulation vs FBX
(EN/FBIN)
0.7
0.2
8710 G03
86
8710 G04
1.4
0.6
0
0.0
–38
125
NEGATIVE FBX CURRENT OUT OF PIN (µA)
15.0
NEGATIVE FBX VOLTAGE (mV)
1.2225
0
25
50
75
TEMPERATURE (°C)
20
Positive and Negative FBX
Current at Output Voltage
Regulation
Positive and Negative Output
Voltage Regulation (FBX)
–25
30
8710 G02
8710 G01
1.2075
–50
40
10
EN/FBIN VOLTAGE (V)
0
–26
AVERAGE ISP-ISN (mV)
20
56
MAX NEGATIVE CSP-CSN (mV)
50
MAX NEGATIVE CSP-CSN (mV)
MAX POSITIVE CSP-CSN (mV)
55
–20
Max Current Limit vs SS
(CSP - CSN)
CSP-CSN (mV)
fOSC = 300kHz
Max Current Limit vs Temperature
at Min DC (CSP - CSN)
MAX POSITIVE CSP-CSN (mV)
60
TA = 25°C, unless otherwise noted.
1.00
1.3
8710 G09
8710f
For more information www.linear.com/LT8710
LT8710
Typical Performance Characteristics
DCM Thresholds (ISP-ISN)
Power Good Thresholds (FBX)
–280
5
–290
14
1.15
130
12
3
–310
MODE = 2V, DCM
2
–320
POSITIVE FBX (V)
–300
1.13
110
1.12
100
1.11
90
FALLING
1.10
1
–330
0
25
50
75
TEMPERATURE (°C)
100
80
–340
125
1.08
–50
–25
50
75
0
25
TEMPERATURE (°C)
8710 G10
1.23
1.38
1.73
EN/FBIN CHIP ENABLE (V)
1.20
1.19
1.18
FALLING, ENTER FCM
1.16
1.15
1.36
1.71
RISING ONLY
1.34
1.69
1.32
1.67
RISING
1.30
1.65
1.28
1.63
1.26
1.61
FALLING
1.24
1.59
1.22
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1.20
–50
RT = 46.4kΩ
700
fOSC (kHz)
600
500
400
300
200
RT = 357kΩ
100
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
8710 G16
–40°C
25°C
125°C
30
25
20
15
10
5
–25
0
25
50
75
TEMPERATURE (°C)
0
1.55
125
100
0
0.25 0.5 0.75 1 1.25 1.5 1.75
EN/FBIN VOLTAGE (V)
Oscillator Frequency During
Soft-Start
BG and TG Transition Time
1
80
BG RISING
BG FALLING
TG RISING
TG FALLING
70
1/2
1/3
1/4
1/5
0
INVERTING
CONFIGURATIONS
0
0.2
NONINVERTING
CONFIGURATIONS
0.4
0.6
0.8
FBX VOLTAGE (V)
1
2
8710 G15
TRANSITION TIME (ns)
800
125
100
8710 G14
NORMALIZED OSCILLATOR FREQUENCY (FSW/FNOM)
900
0
25
50
75
TEMPERATURE (°C)
1.57
8710 G13
Oscillator Frequency vs
Temperature
35
EN/FBIN ACTIVE MODE (V)
RISING, EXIT FCM
1.21
–25
EN/FBIN Pin Current
1.75
1.14
–50
0
–50
EN/FBIN Chip Enable and Active
Mode Thresholds
1.40
1.17
4
8710 G12
1.24
1.22
FALLING
6
8710 G11
MODE Forced CCM Thresholds
MODE (V)
60
125
100
8
2
70
1.09
RISING
10
EN/FBIN PIN CURRENT (µA)
–25
120
RISING
NEGATIVE FBX (V)
4
ISP-ISN (mV)
ISP-ISN (mV)
140
1.14
MODE = 0V, FCM
C/10 Thresholds (ISP-ISN)
1.16
AVERAGE ISP-ISN (mV)
6
0
–50
TA = 25°C, unless otherwise noted.
60
50
40
30
20
10
1.2
8710 G17
0
0
2
4
6
CAP LOAD (nF)
8
10
8710 G18
8710f
For more information www.linear.com/LT8710
7
LT8710
Typical Performance Characteristics
Minimum Operating Input Voltage
4.35
6.40
INTVCC vs Temperature
4.25
4.23
6.32
INTVCC (V)
4.27
6.28
4.21
6.24
4.15
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6.20
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
8710 G19
FALLING
3.5
–50
125
VIN
50
INTVCC > 3.5V
VIN OR BIAS
25
10
20
400
BIAS
350
VIN
300
30
40
50
60
INPUT VOLTAGE (V)
70
80
200
0
10
8710 G22
6.20
6.16
20 30 40 50 60 70
INTVCC LOAD CURRENT (mA)
80
6.08
–50
INTVEE UVLO vs Temperature
BIAS - INTVEE = 5V
3.3
FALLING
3.2
3.1
60
125
–40°C
25°C
125°C
1.0
45
INTVEE (V)
INTVEE CURRENT LIMIT (mA)
3.4
100
INTVEE Dropout (BIAS = 6V)
1.2
1.1
RISING
25
50
75
0
TEMPERATURE (°C)
8710 G24
INTVEE Current Limit vs BIAS
75
3.5
–25
8710 G23
3.6
3.0
–50
IINTVEE = 10mA
6.12
250
INTVCC < 3.5V
125
6.24
BIAS - INTVEE (V)
INPUT - INTVCC (V)
BIAS
6.28
450
INTVCC > 3.5V
75
100
INTVEE vs Temperature
500
100
0
25
50
75
TEMPERATURE (°C)
8710 G21
INTVCC Dropout from VIN
or BIAS
150
125
–25
8710 G20
INTVCC Current Limit vs VIN
or BIAS
INTVCC CURRENT LIMIT (mA)
3.8
3.6
4.17
BIAS - INTVEE (V)
3.9
3.7
4.19
30
0.9
0.8
0.7
0.6
15
0.5
–25
25
50
75
0
TEMPERATURE (°C)
100
125
8710 G25
8
RISING
4.0
4.29
0
INTVCC UVLO vs Temperature
4.1
6.36
INTVCC (V)
VIN OR VBIAS (V)
4.2
IINTVCC = 10mA
4.33
4.31
TA = 25°C, unless otherwise noted.
0
10
20
30
40
50
BIAS (V)
60
70
80
8710 G26
0.4
0
40
10
20
30
INTVEE LOAD CURRENT (mA)
50
8710 G27
8710f
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LT8710
Pin Functions
FBX (Pin 1): Positive and Negative Feedback Pin. For a
boost, SEPIC, or inverting converter, tie a resistor from
the FBX pin to VOUT according to the following equations:
RFBX =
 VOUT – 1.213V 
 83.7µA
 ; Boost or SEPIC Converter
RFBX =
|VOUT |+9.6mV
; Inverting Converter
 83.1µA 
VC (Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin.
SS (Pin 3): Soft-Start Pin. Place a soft-start capacitor here
that is greater than 5x the IMON capacitor. Upon start-up,
the SS pin will be charged by a (nominally) 260k resistor
to ~2.7V. During a current overload as seen by ISP - ISN,
overtemperature, or UVLO condition, the SS pin will be
quickly discharged to reset the part. Once those conditions
are clear, the part will attempt to restart.
FLAG (Pin 4): Power Good or C/10 Indication Pin. The
FLAG pin functions as an active high power good pin if
C/10 is true. Alternatively, the FLAG pin functions as an
active high C/10 indication pin if power is good. Power
is good when FBX < 68.5mV or FBX > 1.153V and has
58mV of hysteresis. When FBX = 1.153V, it’s 5% below
regulation which corresponds to ~10% below regulation
on VOUT (for VOUT > 8V). Active high C/10 indication is
when the charge current seen by the ISP and ISN pins is
less than 10% of full current (VISP – VISN < 5mV) as the
charge current decreases. For increasing charge currents,
the C/10 threshold has to reach 20% of full current (VISP
– VISN > 10mV). The C/10 indication can be used to set
the bulk and float voltage when charging a battery. For
either C/10 or power good indicators, there is a 100µs
anti-glitch delay. A pull-up resistor or some other form
of pull-up network needs to exist on this pin to use these
features. See the Block Diagram and Applications section
for more information.
IMON (Pin 5): Output Current Sense Monitor Output Pin.
Outputs a voltage that is proportional to the voltage seen
across the ISP and ISN pins.
VIMON = 11.9 • (VISP – ISN + 51.8mV)
Since the voltage across the ISP and ISN pins is AC, a
filtering capacitor is needed on the IMON pin to average
out the ISP and ISN voltage. Recommended capacitor
value is 10nF to 100nF. A 51.8mV offset is added to the
amplifier, so when the average ISP – ISN voltage is 0V,
the IMON voltage is 616mV. When the average voltage
across the ISP and ISN pins is 50mV, the IMON pin will
output 1.213V. Do not resistively load down this pin.
ISN, ISP (Pins 6, 7): Output Current Sense Negative and
Positive Input Pins Respectively. Kelvin connect ISN and
ISP pins to a sense resistor to limit the output current. The
commanded NFET current will limit the voltage difference
across the sense resistor to 50mV.
BIAS (Pin 8): Alternate Input Supply and PFET Bias Pin.
Must be locally bypassed. The BIAS pin sets the top rail for
the TG gate driver. Must connect to the converter’s VOUT
for a positive output voltage or INTVCC for a converter’s
negative output voltage.
INTVEE (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must
be locally bypassed with a minimum capacitance of
2.2µF to BIAS. This pin sets the bottom rail for the TG
gate driver. The TG gate driver can begin switching when
BIAS – INTVEE exceeds 3.42V (typical). Connect pin to
ground for an inverting converter.
TG (Pin 10): PFET Gate Drive Pin. Low and high levels are
BIAS – INTVEE and BIAS respectively.
BG (Pin 11): NFET Gate Drive Pin. Low and high levels
are GND and INTVCC respectively.
INTVCC (Pin 12): 6.3V Dual Input LDO Regulator Pin. Must
be locally bypassed with a minimum capacitance of 2.2µF
to GND. Logic will choose to run INTVCC from the VIN or
BIAS pins. A maximum 5mA external load can connect
to the INTVCC pin. The undervoltage lockout on INTVCC is
4V (typical). The BG gate driver can begin switching when
INTVCC exceeds 4V (typical).
VIN (Pin 13): Input Supply Pin. Must be locally bypassed.
Can run down to 0V as long as BIAS > 4.5V.
CSN, CSP (Pins 14, 15): NFET Current Sense Negative
and Positive Input Pins Respectively. Kelvin connect these
pins to a sense resistor to limit the NFET switch current.
The maximum sense voltage at low duty cycle is 50mV.
EN/FBIN (Pin 16): Enable and Input Voltage Regulation
Pin. In conjunction with the UVLO (undervoltage lockout)
circuit, this pin is used to enable/disable the chip and
restart the soft-start sequence. The EN/FBIN pin is also
8710f
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9
LT8710
Pin Functions
RT (Pin 18): Timing Resistor Pin. Adjusts the LT8710’s
switching frequency. Place a resistor from this pin to
ground to set the frequency to a fixed free-running level.
Do not float this pin.
used to limit the NFET current to avoid collapsing the
input supply. Drive below 0.3V to disable the chip with
very low quiescent current. Drive above 1.7V (typical) to
activate the chip and restart the soft-start sequence. The
commanded NFET current will adjust when the EN/FBIN pin
voltage drops between 1.55V and 1.662V. See the Block
Diagram and Applications section for more information.
Do not float this pin.
SYNC (Pin 19): To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock. The
high voltage level of the clock must exceed 1.5V, and the
low level must be less than 0.4V. Drive this pin to less
than 0.4V to revert to the internal free running clock. See
the Applications Information section for more information.
MODE (Pin 17): Forced CCM Mode Pin. Drive below 1.175V
(typical) to operate in forced CCM. Drive above 1.224V
(typical) to operate in DCM and/or pulse-skipping mode
at light loads. If SS < 1.8V (typical) or INTVEE is in UVLO,
the part will operate in DCM at light load.
Block Diagram
•
C1
L1
CIN
L2
VOUT
•
VIN
GND (Pin 20, Exposed Pad Pin 21): Ground. Must be
soldered directly to local ground plane.
COUT
MP
MN
R1
D1
C2
RSENSE1
RSENSE2
RFBX
CSP
VIN
BIAS
DRIVER
BIAS
SR1
–
+A5
LDO
RIN1
DCM_EN ISP ISN
IMON
EN/FBIN
EN/FBIN
LOGIC
A7
+
1.213V
REFERENCE
666.5mV
+
–
100µs
ANTI-GLITCH
CHRG
PG
–
UVLO
FLAG
DCM_EN
INTVCC
CVCC
+
IMON
–
1.38V
–
+
DIE TEMP
+
–
175°C
+
1.3V
1.8V
1.7V
CSS
–
DCM_EN
+
÷N
–
+
START-UP
AND RESET
LOGIC
–
260k
FBX
ADJUSTABLE
OSCILLATOR
+
SS
SYNC
BLOCK
FBX
DCM_EN
FREQUENCY
FOLDBACK
SOFT-START
EA2
14.5k
–
DRIVER
DISABLE
GND
14.5k
EA1
SLOPE
COMPENSATION
–
2.7V 50mV
SS
+
+
EN/FBIN
1.607V
+
+
1.224V
–EA4
EA3
1.213V
A6
11.9k
SYNC
RT
VC
IMON
RC
RT
CC
ISN
+–
ISP
51.8mV
8710 BD
CF
Figure 1. Block Diagram
10
68.5mV
1.213V
–
MODE
1.153V
–
51.5k
RIN2
INTVEE
BIAS – 6.18V
UVLO
INTVCC
CVEE
LDO
+
6.3V
TG DRIVER
DISABLE
Q
R
S
BIAS
TG
DRIVER
LEVEL
SHIFT
–
LDO LOGIC
INTVCC
BG
CSN
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CIMON
8710f
LT8710
STATE Diagram
EN/FBIN < 1.3V (TYP)
OR
VIN AND BIAS < 4.5V (MAX)
CHIP OFF
• ALL SWITCHES DISABLED
1.3V < EN/FBIN < 1.7V (TYP)
AND
VIN OR BIAS > 4.5V
INITIALIZE
• SS PULLED LOW
• INTVCC CHARGES UP
RESET
EN/FBIN > 1.7V
AND
VIN OR BIAS > 4.5V
AND
INTVCC > 4V (TYP)
ACTIVE MODE
• SS SLOWLY CHARGES UP
• VC PULLED LOW
RESET
RESET DETECTED
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED
BEGIN SWITCHING
• NFET BEGINS SWITCHING
• PFET STARTS SWITCHING
WHEN INTVEE REGULATOR
IS OUT OF UVLO
SS < 50mV
RESET
RESET OVER
MODE < 1.175V (TYP)
AND
SS > 1.8V (TYP)
• NO RESET CONDITIONS
DETECTED
MODE > 1.224V (TYP)
FORCED CCM OPERATION
• BG AND TG SWITCH AT
CONSTANT FREQUENCY
• INDUCTOR CURRENT CAN
REVERSE
• IF ISP-ISN VOLTAGE
GOES BELOW –300mV (TYP),
PFET TURNS OFF SO
INDUCTOR CURRENT
GOES MORE POSITIVE
DCM AT LIGHT LOAD
REGULATION
• PFET TURNS OFF FOR
REMAINDER OF CYCLE IF
ISP-ISN VOLTAGE FALLS
BELOW 2.8mV (TYP)
• FOR VERY LIGHT LOAD,
PART MAY SKIP PULSES
• VC COMMANDS PEAK
INDUCTOR CURRENT TO
MAINTAIN REGULATION
RESET
RESET
INTVEE REGULATOR
IN UVLO
AND
SS > 1.8V (TYP)
OUTPUT CURRENT FOLDBACK
• OUTPUT CURRENT LIMITED
TO 25mV (TYP) AVERAGE
ACROSS THE ISP-ISN PINS
RESET
8710 SD
REGULATION = OUTPUT VOLTAGE (FBX)
INPUT VOLTAGE (EN/FBIN)
OUTPUT CURRENT (ISP-ISN AND IMON)
RESET = UVLO ON VIN OR BIAS ( < 4.5V (MAX))
UVLO ON INTVCC ( < 4V (TYP))
EN/FBIN < 1.7V (TYP) AT 1ST POWER-UP
EN/FBIN < 1.26V (TYP) AFTER ACTIVE MODE SET
OVERCURRENT (ISP – ISN > 63.6mV AVERAGE (TYP))
OVERTEMPERATURE (TJ > 175°C (TYP))
Figure 2. State Diagram
8710f
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11
LT8710
Operation
OPERATION – OVERVIEW
ACTIVE MODE THRESHOLD
(TOLERANCE)
1.64V
NORMAL OPERATION IF ACTIVE MODE SET
1.662V
INPUT VOLTAGE REGULATION
(ONLY IF ACTIVE MODE SET)
1.55V
SWITCH OFF, INTVCC AND INTVEE ENABLED, SS CAP
DISCHARGED IF ACTIVE MODE NOT SET
1.38V
CHIP ENABLE THRESHOLD
(HYSTERSIS AND TOLERANCE)
1.18V
LOCKOUT
(SWITCH OFF, SS CAP DISCHARGED, INTVCC AND
INTVEE DISABLED)
0.3V
SHUTDOWN
(LOW QUIESCENT CURRENT)
0V
8710 F03
Figure 3. EN/FBIN Modes of Operation
OPERATION – START-UP
Several functions are provided to enable a very clean
start-up of the LT8710.
Precise Turn-On Voltages
The EN/FBIN pin has two voltage levels for activating the
part; one that enables the part and allows internal rails
to operate and a 2nd voltage threshold which activates
a soft-start cycle and switching can begin. To enable the
part, take the EN/FBIN pin above 1.3V (typical). This comparator has 44mV of hysteresis to protect against glitches
and slow ramping. To activate a soft-start cycle and allow
switching, take EN/FBIN above 1.7V (typical). When EN/
FBIN exceeds 1.7V (typical), the logic state is latched so
that if EN/FBIN drops between 1.3V to 1.7V (typical), the
SS pin is not pulled low by the EN/FBIN pin. The EN/FBIN
pin is also used for input voltage regulation which is at
1.607V (typical). Input voltage regulation is explained in
more detail in the Operation – Regulation section. Taking
the EN/FBIN pin below 0.3V shuts down the chip, resulting in extremely low quiescent current. See Figure 3 that
illustrates the different EN/FBIN voltage thresholds.
12
1.76V
EN/FBIN (V)
The LT8710 uses a constant frequency, current mode
control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function,
together with soft-start and frequency foldback, offers a
controlled means of starting up. Output voltage, output
current, and input voltage have control over the commanded
peak current which allows a wide range of applications to
be built using the LT8710. Synchronous switching makes
high efficiency and high output current applications possible. When operating at light currents with the MODE pin
> 1.224V (typical), the LT8710 will disable synchronous
operation for part of the cycle to prevent negative switch
currents. Refer to the Block Diagram (Figure 1) and the
State Diagram (Figure 2) for the following description of
the part’s operation.
ACTIVE MODE
(NORMAL OPERATION)
(MODE LATCHED UNTIL EN/FBIN DROPS BELOW
CHIP ENABLE TRESHOLD)
Undervoltage Lockout (UVLO)
The LT8710 has internal UVLO circuitry that disables the
chip when the greater of VIN or BIAS < 4.5V (maximum)
or INTVCC < 4V (typical). The EN/FBIN pin can also be
used to create a configurable UVLO. See the Applications
section for more information.
Soft-Start of Switch Current
The soft-start circuitry provides for a gradual ramp-up
of the switch current (refer to Max Current Limit vs SS
in Typical Performance Characteristics). When the part
is brought out of shutdown, the external SS capacitor
is first discharged which resets the states of the logic
circuits in the chip. Once INTVCC comes out of UVLO
(> 4V typical) and the chip is in active mode, an integrated
260k resistor pulls the SS pin to ~2.7V at a ramp rate set
by the external capacitor connected to the pin. Typical
values for the soft-start capacitor range from 100nF to
1µF. The soft-start capacitor should also be at least 5x
greater than the external capacitor connected to the IMON
pin to avoid start-up issues.
8710f
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LT8710
Operation
Frequency Foldback
The frequency foldback circuitry reduces the switching
frequency when 175mV < FBX < 1.01V (typical). This
feature lowers the minimum duty cycle that the part can
achieve, thus allowing better control of the inductor current
at start-up. When the FBX voltage is pulled outside of this
range, the switching frequency returns to normal. If the part
is configured to be in forced continuous conduction mode
(MODE pin is driven below 1.175V), then the frequency
foldback circuitry is disabled as long as INTVEE is not in
UVLO and the SS pin is higher than the SS Hi threshold.
mode of regulation will be described independently so
that only one of the modes of regulation is in command
of the LT8710.
Output Voltage Regulation
Note that the peak inductor current at start-up is a function
of many variables including load profile, output capacitance,
target VOUT, VIN, switching frequency, etc.
A single external resistor is used to set the target output
voltage. See the Pin Functions section for selecting the
feedback resistor for a desired output voltage. The VC
pin voltage (negative input of A7) is set by EA1 (or EA2),
which is simply an amplified difference between the FBX
pin voltage and the reference voltage (1.213V if the LT8710
is configured as a noninverting converter or 9.6mV if
configured as an inverting converter). In this manner, the
FBX error amplifier sets the correct peak current level to
maintain output voltage regulation.
OPERATION – REGULATION
Input Voltage Regulation
Use the Block Diagram when stepping through the following
description of the LT8710 operating in regulation. Also,
assume the converter’s load current is high enough such
that the part is operating in synchronous switching. The
LT8710 has three modes of regulation:
A single resistor or resistor divider from the EN/FBIN pin
to the converter’s input voltage sets the input voltage
regulation. It is recommended to use a resistor divider for
improved accuracy as described in the Setting the Input
Voltage Regulation or Undervoltage Lockout section.
The EN/FBIN pin voltage connects to the positive input of
amplifier EA4. The VC pin voltage is set by EA4, which is
simply an amplified difference between the EN/FBIN pin
voltage and a 1.607V reference voltage. In this manner,
the EN/FBIN error amplifier sets the correct peak current
level to maintain input voltage regulation.
1. Output Voltage (via FBX pin)
2. Input Voltage (via EN/FBIN pin)
3. Output Current (via ISP, ISN, and IMON pins)
All three of these regulation loops control the peak commanded current through the external NFET, MN. This
operation is the same regardless of the regulation mode,
so that will be described first.
At the start of each oscillator cycle, the SR latch (SR1)
is set, which first turns off the external PFET, MP, and
then turns on the external NFET, MN. The NFET’s source
current flows through an external current sense resistor
(RSENSE1) generating a voltage proportional to the NFET
switch current. This voltage is then amplified by A5 and
added to a stabilizing ramp. The resulting sum is fed into
the positive terminal of the PWM comparator A7. When the
voltage on the positive input of A7 exceeds the voltage on
the negative input (VC pin), the SR latch is reset, turning
off the NFET and then turning on the PFET. The voltage
on the VC pin is controlled by one of the regulation loops,
or a combination of regulation loops. For simplicity, each
Output Current Regulation
An external sense resistor connected between the ISP and
ISN pins (RSENSE2) sets the maximum output current of the
converter when placed in the source of the PFET, MP. A
built-in 51.8mV offset is added to the voltage seen across
RSENSE2. That voltage is then amplified and outputs to
the IMON pin. An external capacitor must be placed from
IMON to ground to filter the amplified chopped voltage
that’s sensed across RSENSE2. The voltage at the IMON pin
is fed to the negative input of the IMON error amplifier,
EA3. The VC pin voltage is set by EA3, which is simply an
amplified difference between the IMON pin voltage and the
1.213V reference voltage. In this manner, the IMON error
amplifier sets the correct peak current level to maintain
output current regulation.
8710f
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13
LT8710
Operation
Note that if the INTVEE LDO is in UVLO and SS > 1.8V
(typical), then the voltage reference at the positive input
of EA3 is 916mV (typical), resulting in limiting the output
current to about half of its set limit.
Light Load Current (MODE Pin)
The MODE pin can be used to tell the LT8710 to operate
in forced CCM regardless of load current, or operate in
DCM at light loads.
• MODE < 1.175V (typical) = Forced CCM or FCM
OPERATION – RESET CONDITIONS
The LT8710 has three reset cases. When the part is in
reset, the SS pin is pulled low and both power switches,
MN and MP, are forced off. Once all of the reset conditions
are gone, the part is allowed to begin a soft-start sequence
and switching can commence. Each of the following events
can cause the LT8710 to be in reset:
1. UVLO
a. The greater of VIN and BIAS is < 4.5V (maximum)
• MODE > 1.224V (typical) = DCM or Pulse-Skipping
The forced continuous mode (FCM) allows the inductor
current to reverse directions without any switches being
forced off. At very light load currents, the inductor current will swing positive and negative as the appropriate
average current is delivered to the output. There are some
exceptions that negate the MODE pin and force the part
to operate in DCM at light loads:
b. INTVCC < 4V (typical)
1. The INTVEE LDO is in UVLO (BIAS – INTVEE < 3.42V
typical).
c. EN/FBIN < 1.7V (typical) at first power-up
2. SS < 1.8V (typical).
2. Overcurrent sensed by IMON > 1.38V (typical)
3. The part is in a reset condition.
3. Die Temperature > 175°C
When the LT8710 is in discontinuous mode (DCM), synchronous switch MP is held off whenever MP’s current
falls near 0 current (less than 2.8mV (typical) across
RSENSE2). This is to prevent current draw from the output
and/or feeding current to the input supply. Under very
light loads, the current comparator A7, may also remain
tripped for several cycles (i.e. skipping pulses). Since MP
is held off during the skipped pulses, the inductor current
will not reverse.
OPERATION – POWER SWITCH CONTROL
The main power switch is the external NFET (MN in Block
Diagram) and the synchronous power switch is the external PFET (MP in Block Diagram). The two switches
are never on at the same time, and there is a non-overlap
time of ~140ns and ~90ns on the rising and falling edges
respectively (see Electrical Characteristics) to prevent
cross conduction. Figure 4 below shows the BG and TG
(BIAS–TG) signals:
140ns
The FLAG pin is an open-drain pin that functions as an active high C/10 and power good pin. The FLAG pin changes
states 100µs (typical) after the internal comparators tell
the FLAG pin to change states to reject glitches or transient events.
90ns
BG
ON
OPERATION – C/10 AND POWER GOOD (FLAG PIN)
TG
ON
8710 F04
Figure 4. Synchronous Switching
14
8710f
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LT8710
Operation
C/10 Indication
OPERATION – LDO REGULATORS (INTVCC AND INTVEE)
If power is good, then the FLAG pin will function as an
active high C/10 indication pin. C/10 is when the charging
current (output current) has dropped to 1/10 its maximum
and is useful in battery charging applications. The C/10
comparator monitors the voltage at the IMON pin, and when
the average ISP-ISN voltage drops below 5mV (typical),
the FLAG pin pull-down device is turned off, and the FLAG
pin voltage is allowed to pull high. The FLAG pin will pull
low again if the average ISP-ISN voltage rises above 10mV
(typical). The IMON voltage corresponding to 5mV and
10mV on ISP – ISN is 666.5mV and 727.5mV respectively.
The INTVCC LDO regulates at 6.3V (typical) and is used
as the top rail for the BG gate driver. The INTVCC LDO can
run from VIN or BIAS and will intelligently select to run
from the best for minimizing power loss in the chip, but
at the same time, select the proper input for maintaining
INTVCC as close to 6.3V as possible. The INTVCC regulator
also has safety features to limit the power dissipation in
the internal pass device and also to prevent it from damage if the pin is shorted to ground. The UVLO threshold
on INTVCC is 4V (typical), and the LT8710 will be in reset
until the LDO comes out of UVLO.
Note that if the LT8710 is set to operate in FCM (MODE
pin low), then the C/10 comparator is disabled and the
FLAG pin operates only as a power good pin. See the Applications section for more information.
The INTVEE regulator regulates to 6.18V (typical) below
the BIAS pin voltage. The BIAS and INTVEE voltages are
used for the top and bottom rails of the TG gate driver
respectively. Just like the INTVCC regulator, the INTVEE
regulator has a safety feature to limit the power dissipation
in the internal pass device. The TG pin can begin switching after the INTVEE regulator comes out of UVLO (3.42V
typical across the BIAS and INTVEE pins) and the part is
not in a reset condition.
Power Good Indication
If C/10 is detected (average ISP-ISN < 5mV typical), then the
FLAG pin functions as an active high power good (PG) pin.
Power is good when the FBX voltage is greater than 95%
of its regulation target, which corresponds to ~90% of the
VOUT regulation target (for VOUT > ~8V). This corresponds
to FBX > 1.153V (typical) for noninverting converters and
FBX < 68.5mV (typical) for inverting converters. The PG
comparators have 58mV of hysteresis to reject glitches.
8710f
For more information www.linear.com/LT8710
15
LT8710
Applications Information
BOOST CONVERTER COMPONENT SELECTION
L1
1.3µH
VIN
4.5V TO
9V
+
MP
1m
CIN2
330µF
BG
VIN
RIN1
13.3k
+
VOUT
12V
6A
COUT2
330µF
COUT1
22µF
×4
CSN CSP TG
ISP
LT8710
ISN
INTVEE
MODE
Step 1: Inputs
Step 2: DCMAX
Step 3: VCSPN
Step 4: RSENSE1
BIAS
2.2µF
RFBX
130k
Step 5: RSENSE2
FBX
INTVCC
CIN1
22µF
×4
Parameters/Equations
RSENSE2
5m
MN
×2
RSENSE1
EN/FBIN
RIN2
10k
2.2µF
Table 1. Boost Design Equations
FLAG
RT
VC
RT
88.7k
Step 6: L
RC
18k
SYNC
GND IMON
SS
CIMON
47nF
CSS
220nF
CF
100pF
CC
3.3nF
8710 F05
Figure 5. Boost Converter – The Component Values Given are
Typical Values for a 400kHz, 4.5V to 9V to 12V/6A Boost.
The LT8710 can be configured as a boost converter as in
Figure 5. This topology generates a positive output voltage
where the input voltage is lower than the output voltage.
A single feedback resistor sets the output voltage.
For a desired output current and output voltage over a
given input voltage range, Table 1 is a step-by-step set of
equations to calculate component values for the LT8710
when operating as a boost converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 1.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
16
Pick VIN, VOUT, IOUT, and f to calculate equations
below.
DCMAX ≅ 1–
VIN(MIN)
VOUT
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
RSENSE1 ≤ 0.58 •
RSENSE2 ≤
VCSPN
•(1– DCMAX )
IOUT
0.05
1.6 • IOUT
RSENSE1 • VIN(MIN)  VIN(MIN) 
• 1–

VOUT 
12.5m• f
VIN(MIN)
•V
R


LMIN = SENSE1 OUT • 1–
 VOUT – VIN(MIN) 
40m• f
(1)
L TYP =
LMAX1 =
RSENSE1 • VIN(MIN)  VIN(MIN) 
• 1–

VOUT 
5m• f
LMAX2 =
RSENSE1 • VIN(MAX)  VIN(MAX) 
• 1–

VOUT 
5m • f
(2)
(3)
(4)
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range is
the lower of LMAX1 and LMAX2.
Step 7: COUT
Step 8: CIN
Step 9: CIMON
Step 10: RFBX
Step 11: RT
COUT ≥
CIN ≥
IOUT •DCMAX
f • 0.005 • VOUT
DCMAX
8 •L • f 2 • 0.005
CIMON ≥
RFBX =
RT =
100µ•DCMAX
0.005• f
VOUT – 1.213V
83.7µA
35,880
– 1; f in kHz and R T in kΩ
f
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
8710f
For more information www.linear.com/LT8710
LT8710
Applications Information
SEPIC CONVERTER COMPONENT SELECTION –
COUPLED OR UNCOUPLED INDUCTORS
•
VIN
3V TO 40V(OPERATING)
4.5V TO 40V(START-UP)
C1
10µF ×2
L1
2.9µH
CIN1
10µF
×6
MP
MN
1.5m
BG
RSENSE1
MODE
Step 4: RSENSE1
2.2µF
RFBX
45.3k
Step 5: RSENSE2
FBX
DCMAX ≅
RSENSE1 ≤ 0.58 •
RSENSE2 ≤
Step 6: L
VC
RT
178k
CF
100pF
SYNC
GND IMON
SS
CIMON
47nF
VOUT
VIN(MIN) + VOUT
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
FLAG
RT
+
Step 2: DCMAX
Pick VIN, VOUT, IOUT, and f to calculate equations
below.
BIAS
INTVEE
INTVCC
CIN2
220µF
COUT1
100µF
×4
ISP
LT8710
COUT2
330µF
Step 1: Inputs
Step 3: VCSPN
TG
ISN
EN/FBIN
RIN2
10k
2.2µF
VOUT
5V
5A
+
•
VIN
RIN1
4.02k
Parameters/Equations
RSENSE2
6m
L2
2.9µH
CSN CSP
Table 2. SEPIC Design Equations
CSS
220nF
RC
8.87k
CC
6.8nF
The LT8710 can also be configured as a SEPIC as in
Figure 6. This topology generates a positive output voltage where the input voltage can be lower, equal, or higher
than the output voltage. Output disconnect is inherently
built into the SEPIC topology, meaning no DC path exists
between the input and output due to capacitor C1.
For a desired output current and output voltage over a
given input voltage range, Table 2 is a step-by-step set of
equations to calculate component values for the LT8710
when operating as a SEPIC converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 2.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
0.05
1.6 •IOUT
L TYP =
RSENSE1 • VOUT  VIN(MIN) 
•
 VIN(MIN) + VOUT 
12.5m • f
LMIN =
2
RSENSE1 • VOUT   VIN(MIN) 
 
• 1– 
40m • f
  VOUT  
8710 F06
RSENSE1 • VOUT  VIN(MIN) 
•
 VIN(MIN) + VOUT 
5m• f
LMAX =
Figure 6. SEPIC Converter – The Component Values Given Are
Typical Values for a 200kHz, 3V to 40V to 5V/5A SEPIC Topology
Using Coupled Inductors.
VCSPN
•(1–DCMAX )
IOUT
(1)
(2)
(3)
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
Step 7: C1
Step 8: COUT
Step 9: CIN
Step 10: CIMON
Step 11: RFBX
Step 12: RT
C1≥10µF ( TYPICAL );VRATING > VIN
COUT ≥
CIN ≥
IOUT •DCMAX
f • 0.005 • VOUT
DCMAX
8 •L • f 2 • 0.005
CIMON ≥
RFBX =
RT =
100µ•DCMAX
0.005• f
VOUT – 1.213V
83.7µA
35,880
– 1; f in kHz and R T in kΩ
f
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
8710f
For more information www.linear.com/LT8710
17
LT8710
Applications Information
DUAL INDUCTOR INVERTING COMPONENT SELECTION
– COUPLED OR UNCOUPLED INDUCTORS
CIN1
10µF
×4
L2
2.2µH
MN
1.5m
RSENSE1
D1
C2
0.47µF
BG
RIN1
13.3k
Step 3: VCSPN
Step 4: RSENSE1
ISN
LT8710
BIAS
INTVEE
MODE
INTVCC
2.2µF
Step 5: RSENSE2
RFBX
60.4k
| VOUT |
VIN(MIN)+ |VOUT |
See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
RSENSE1 ≤ 0.58 •
RSENSE2 ≤
Step 6: L
FLAG
RT
VC
RT
118k
CC
100pF
SYNC
GND IMON
SS
CIMON
47nF
CSS
220nF
CC
3.3nF
0.05
1.6 •IOUT
VIN(MIN)
RSENSE1•| VOUT | 

•

V
12.5m• f
IN(MIN)+ |VOUT | 
LMIN =
2
RSENSE1• |VOUT |   VIN(MIN) 
 
• 1– 
40m • f
  VOUT  
(1)
(2)
8710 F07
Due to its unique FBX pin, the LT8710 can work in a dual
inductor inverting configuration as in Figure 7. Changing
the connections of L2 and the PFET in the SEPIC topology, results in generating negative output voltages. This
solution results in very low output voltage ripple due to
inductor L2 in series with the output. Output disconnect is
inherently built into this topology due to the capacitor C1.
For a desired output current and output voltage over a
given input voltage range, Table 3 is a step-by-step set of
equations to calculate component values for the LT8710
when operating as a dual inductor inverting converter. Refer
to more detail in this section and the Appendix for further
information on the design equations presented in Table 3.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
VCSPN
•(1–DCMAX )
IOUT
L TYP =
RC
11.5k
VIN(MIN)
RSENSE1• |VOUT| 

•

V
5m • f
IN(MIN)+ |VOUT | 
LMAX =
Figure 7. Dual Inductor Inverting Converter – The Component
Values Given Are Typical Values for a 300kHz, 4.5V to 25V to
–5V/7A Inverting Topology Using Coupled Inductors.
18
DCMAX ≅
FBX
INTVCC
+
Step 2: DCMAX
Pick VIN, VOUT, IOUT, and f to calculate equations
below.
ISP
EN/FBIN
CIN2
120µF
COUT2
330µF
COUT1
100µF
×2
RSENSE2
4m
CSN CSP TG
VIN
RIN2
10k
2.2µF
MP
R1
499Ω
Parameters/Equations
Step 1: Inputs
VOUT
–5V
7A
•
C1
10µF ×2
L1
2.2µH
+
•
VIN
4.5V TO
25V
Table 3. Dual Inductor Inverting Design Equations
(3)
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
Step 7: C1
Step 8: COUT
Step 9: CIN
Step 10: CIMON
Step 11: RFBX
Step 12: RT
C1≥10µF ( TYPICAL );VRATING > VIN+|VOUT |
COUT ≥
CIN ≥
VIN(MAX)
1


•
8 • f 2 • 0.005  VIN(MAX) + |VOUT | 
DCMAX
8 •L • f 2 • 0.005
CIMON ≥
RFBX =
RT =
100µ•DCMAX
0.005• f
|VOUT | +9. 6mV
83.1µA
35,880
– 1; f in kHz and R T in kΩ
f
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
8710f
For more information www.linear.com/LT8710
LT8710
Applications Information
SETTING THE OUTPUT VOLTAGE REGULATION
The LT8710 output voltage is set by connecting an external
resistor (RFBX) from the converter’s output, VOUT, to the
FBX pin. The equations below determines RFBX:
VIN
RIN1
SETTING THE INPUT VOLTAGE REGULATION OR
UNDERVOLTAGE LOCKOUT
By connecting a resistor divider between VIN, EN/FBIN,
and GND, the EN/FBIN pin provides a mean to regulate
the input voltage or to create an undervoltage lockout
function. Referring to error amplifier EA4 in the block
diagram, when EN/FBIN is lower than the 1.607V reference, VC is pulled low. For example, if VIN is provided by
a relatively high impedance source (e.g. a solar panel) and
the current draw pulls VIN below a preset limit, VC will be
reduced, thus reducing current draw from the input supply
and limiting the input voltage drop. Note that using this
function in forced continuous mode (MODE pin low) can
result in current being drawn from the output and forced
into the input. If this behavior is not desired then set the
MODE pin high to prevent reverse current flow.
To set the minimum or regulated input voltage use:
 R 
VIN(MIN– REG) = 1.607V • 1+ IN1 +17.6µA •RIN1
 RIN2 
R IN1 =
VIN(MIN–REG) – 1.607V
1.607V
+17.6µA

 RIN2 
where RIN1 and RIN2 are shown in Figure 8. For increased
accuracy, set RIN2 ≤ 10k. The resistor RIN2 is optional, but
it is recommended to be used to increase the accuracy of
the input voltage regulation by making the RIN1 current
much higher than the EN/FBIN pin current.
EN/FBIN
17.6µA
AT 1.607V
V
– 1.213V
R FBX = OUT
; Boost or SEPIC Converter
83.7µA
| V | –9.6mV
R FBX = OUT
; Inverting Converter
83.1µA
See the Electrical Characteristics for tolerances on the FBX
regulation voltage and current.
1.7V
1.3V
VIN
RIN2
(OPTIONAL)
51.5k
1.607V
EN/FBN
LOGIC
ACTIVE MODE
CHIP ENABLE
+
EA4
–
VC
GND
8710 F08
Figure 8. Configurable UVLO
This same technique can be used to create an undervoltage
lockout if the LT8710 is NOT in forced continuous mode.
When in discontinuous mode, forcing VC low will stop all
switching activity. Note that this does not reset the soft
start function, therefore resumption of switching activity
will not be accompanied by a soft-start.
Note that for very low input impedance supplies, a capacitor from EN/FBIN to ground may be needed to prevent
oscillations from the input voltage regulation control loop.
At start-up, the minimum voltage on EN/FBIN must exceed
1.7V (typical) to begin a soft-start cycle. Afterwards, the
EN/FBIN voltage can drop below 1.7V and the input can
be regulated such that the EN/FBIN voltage is at ~1.607V.
So the equation below gives the start-up VIN for a desired
input regulation voltage:
VIN(START-UP) =
1.7V
• VIN(MIN – REG) +0.78µA •RIN1
1.607V
OUTPUT CURRENT MONITORING AND LIMITING
(RSENSE2 AND ISP-ISN AND IMON Pins)
The LT8710 has an output current monitor circuit that
can be used to monitor and/or limit the output current.
The current monitor circuit works as shown in Figure 9.
If it is not desirable to monitor and limit the output current, simply connect the IMON pin to ground. Note that
the current sense resistor connected to the ISP and ISN
pins must still be used, and the value should follow the
guidelines in the next couple sections.
8710f
For more information www.linear.com/LT8710
19
LT8710
Applications Information
RSENSE2
MP
TG
voltage. Assume the current through RSENSE2 is steady
state and that its time average current is approximately
equal to the converter’s load current:
TO SYSTEM
VOUT
VIMON =11.9 • (IRSENSE2(AVE) •R SENSE2 +51.8mV )
ISN
ISP
–
+
VIMON
– 51.8mV
IOUT ≈IRSENSE2(AVE) = 11.9
RSENSE2
–
+
51.8mV
1mA/V
A7
1.38V
1.213V
+
+
EA3
–
Output Current Limiting
IMON
As shown in Figure 9, IMON voltages exceeding 1.213V
(typical) causes the VC voltage to reduce, thus limiting
the inductor current. This voltage on IMON corresponds
to an average voltage of 50mV across RSENSE2. Below is
the equation for selecting the RSENSE2 resistor for limiting
the output current at steady state:
+
–
CHRG
–
OVER
CURRENT
666.5mV
11.9K
GND
VC
CIMON
8710 F09
Figure 9. Output Current Monitor and Control
The current through RSENSE2 is sensing the current through
MP which is turning on and off every clock cycle. Since
the current through RSENSE2 is chopped, a filter capacitor
connected from the IMON pin to ground is needed to filter
the voltage at the IMON pin before heading to EA3. Below is
the equation to calculate the required IMON pin capacitor:
C IMON ≥
100µA •DCMAX
5mV • f
where DCMAX is the maximum duty cycle of the converter’s
application (VIN at the lowest of its input range) and f is
the switching frequency.
To prevent start-up issues, the IMON capacitor should
charge up faster than the SS capacitor. It is recommended
to size the SS capacitor at least 5x greater than the IMON
capacitor.
Output Current Monitoring
The voltage at the IMON pin is a gained up version of the
voltage seen across the ISP and ISN pins. Below are the
equations relating the RSENSE2 current to the IMON pin
20
R SENSE2 =
50mV
IOUT(LIMIT)
If it is not desirable to limit the output current, size
RSENSE2 by setting IOUT(LIMIT) at least 60% higher than
the maximum output current of the converter. This current
sense resistor is needed if using the synchronous PFET
in the converter. If the PFET is replaced with a Schottky,
then RSENSE2 is not needed if output current limiting or
monitoring isn’t required.
Note that if the INTVEE LDO is in UVLO and SS > 1.8V (typical), then the reference voltage at EA3 reduces to 916mV,
and the output current is limited to about half its set point.
Output Overcurrent
As shown in Figure 9, a comparator monitors the voltage
at the IMON pin and triggers a reset condition if the IMON
pin voltage exceeds 1.38V (typical). This corresponds to
an average voltage of 63.6mV (typical) across the ISP
and ISN pins:
63.6mV
RSENSE2
IOUT(OVERCURRENT) =1.27 •IOUT(LIMIT)
IOUT(OVERCURRENT) =
8710f
For more information www.linear.com/LT8710
LT8710
Applications Information
Battery Charging and C/10
Capacitor Charging
A useful application for limiting the output current is to
charge a battery. When charging a battery such as a 12V
lead acid battery, it may be useful to charge to a bulk and
float voltage, in which case, the C/10 function of the FLAG
pin can be used. For decreasing charge currents, C/10
is detected when the IMON voltage falls below 666.5mV
(typical) and corresponds to an average ISP – ISN voltage
of 5mV (typical). For increasing charge currents, C/10 is
cleared when IMON gets above 727.5mV (typical) which
corresponds to an average ISP – ISN voltage of 10mV
(typical).
When the application is to charge a bank of capacitors
such as SuperCaps, the charging current is set by RSENSE2
and the FLAG pin isn’t necessarily needed as in the case
of charging a battery.
To set a bulk and float battery voltage, simply connect
a resistor from the FLAG pin to the FBX pin. When the
battery charging current is high (C/10 not detected), the
target output voltage is the bulk battery voltage as set by
the resistor connected between the FLAG and FBX pins.
Once the charging current drops such that C/10 is detected,
the target output voltage drops to the float battery voltage
as set by the external FBX resistor. See Figure 10 below
on the FLAG pin connections and equations for setting the
bulk and float battery voltages. Note that in order to use
the C/10 feature, the MODE pin must be high to operate
in DCM at light loads.
FROM
CONTROLLER
VOUT
RFLAG
FLAG
PG
COUT
RFBX
+
Temperature Dependent Output Voltage Using NTC
Resistor
It may be desirable to regulate the converter’s output based
on the ambient temperature. The INTVCC LDO regulated
voltage is 6.3V ± 1.6% (see Electrical Characteristics), and
a negative temperature coefficient (NTC) resistor can be
used to sum into the FBX pin to create an output voltage
that decreases with temperature. See Figure 11 for the
necessary connections.
The FBX voltages regulates to 1.213V (typical) for positive output voltages. For an accurate room temperature
output voltage, size the resistor divider off the INTVCC
pin to give 1.213V such that the current through R2 is
~0 at room temperature. Choose RNTC(25) ≤ 10kΩ and
use the equations below to calculate R1, RFBX, and VOUT
at room temperature and R2 for a desired VOUT change
over temperature.
R 1=RNTC(25)
VOUT
R
VOUT(25) ≅ 1.213V +83.7µA •RFBX + FBX •
R2
LEAD ACID
BATTERY
R1


1.213V – 6.3V • R +R

1 NTC(25)

FBX
1.213V
100µs
ANTI-GLITCH
6.3 – 1.213V
1.213V
83.7µA
CHRG
–
DCM_EN
666.5mV
+
IMON
RNTC =RNTC(25) • e
GND
1
1
–
T T25
1
1


–
R +R

 1 NTC(T(MAX)) R1+RNTC(T(MIN))
V
– 1.213V
RFBX = OUT(FLOAT)
83.7µA
1.213V
RFLAG =RFBX •
VOUT(BULK) – VOUT(FLOAT)
Figure 10. FLAG Pin Connections and Equations
for Battery Charging
( )
R
∆VOUT = –6.3V • FBX •R1•
R2
8710 F10
β•
–6.3V
•R • R •
∆VOUT FBX 1
1
1


–
R +R

 1 NTC(T(MAX)) R1+RNTC(T(MIN))
R2=
For more information www.linear.com/LT8710
8710f
21
LT8710
Applications Information
where:
RNTC(25) = Resistance of the NTC resistor at 25°C
b = Material-specific constant of NTC resistor.
Specified at two temperatures such as b25/85.
If more than two bs are specified, use the most
appropriate for the application.
T
To provide a desired load current for any given application,
RSENSE1 must be sized appropriately. The switch current
will be at its highest when the input voltage is at the lowest
of its range. The equation below calculates RSENSE1 for a
desired output current:
= Absolute temperature in Kelvin
V
 i

RSENSE1≤ 0.74 • η• CSPN • (1–DCMAX ) •  1– RIPPLE 

IOUT
2 
where
T25 = Room temperature in Kelvin (298.15k)
η
VCSPN = Max current limit voltage (see Max Current Limit vs Duty Cycle (CSP-CSN) plot in the Typical Performance Characteristics)
1.213V
FROM SYSTEM
VOUT
+
EA1
14.5k
RFBX
–
IOUT = Converter load current
+
DCMAX = Switching duty cycle at minimum VIN (see Power Switch Duty Cycle in Appendix)
FBX
R2
6.3V
RNTC
INTVCC
= Converter efficiency (assume ~90%)
EA2
14.5k
–
GND
VC
iRIPPLE = Peak-to-peak inductor ripple current percent
age at minimum VIN (recommended to use 25%)
R1
Reverse Current Applications (MODE Pin Low)
8710 F11
Figure 11. Temperature Dependent Output Using an NTC
Resistor Divider
SWITCH CURRENT LIMIT (RSENSE1 AND CSP-CSN
PINS)
The external current sense resistor (RSENSE1) sets the
maximum peak current though the external NFET switch
(MN). The maximum voltage across RSENSE1 is 50mV
(typical) at very low switch duty cycles, and then slope
compensation decreases the current limit as the duty cycle
increases (see the Max Current Limit vs Duty Cycle (CSPCSN) plot in the Typical Performance Characteristics). The
equation below gives the switch current limit for a given
duty cycle and current sense resistor (find VCSPN at the
operating duty cycle in the plot mentioned).
ISW(LIMIT) =
22
When the forced continuous mode is selected (MODE pin
low), inductor current is allowed to reverse directions and
flow from the VOUT side to the VIN side. This can lead to
current sinking from the output and being forced into the
input. The reverse current is at a maximum magnitude
when VC is lowest. The graph of Max Current Limit vs Duty
Cycle (CSP – CSN) in the Typical Performance Characteristics section can help to determine the maximum reverse
current capability.
The IMON pin voltage will indicate negative inductor currents. Refer to the equation for IMON in the Pin Functions.
Note that the IMON voltage is only accurate if the dynamic
voltage across RSENSE2 stays within –51.8mV to 500mV.
If the valley inductor current goes more negative than
–300mV as sensed by RSENSE2, the external PFET will turn
off, and the inductor current will start going more positive.
VCSPN
RSENSE1
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LT8710
Applications Information
Backup Power
With the use of reverse current control and input voltage
regulation, the LT8710 can be used as a backup power
converter as shown in Figure 12 below. With the MODE pin
low to operate in FCM, when the input source is removed,
the output can supply current into the input and keep the
input regulated for some amount of time. The amount
of time depends on the output capacitance and the load
current at the input.
IDEAL
DIODE
C1
L1
CIN1
INPUT POWER
SOURCE CAN BE
REMOVED
RSENSE2
MP
•
VPWR
12V ± 5%
VSYSTEM
VPWR IF VPWR IS PRESENT
10.5V IF VPWR IS REMOVED
L2
RSENSE1
+
•
BG
VIN
RIN1
49.9k
CSN CSP
ISN
LT8710
BIAS
INTVEE
MODE
CIN2
CAP
BANK
TG
ISP
EN/FBIN
RIN2
10k
+
VOUT
MN
RFBX
FBX
GND
8710 F12
Figure 12. Backup Power Converter
Once VOUT drops low enough to put the INTVEE LDO in
UVLO (VOUT at ~4.25V), the PFET will stop switching and
the current will stop flowing from VOUT to VSYSTEM. For this
type of application, it is recommended to use a PFET that is
in the linear mode of operation with only 4V of gate drive.
approach, as VIN approaches the OVP point, the MODE pin
approaches the MODE FCM threshold (1.224V typical) and
the LT8710 won't allow reverse current flow, preventing
VIN to go above the OVP point.
CURRENT SENSE FILTERING
Certain applications may require filtering of the inductor
current sense signals due to excessive switching noise that
can appear across RSENSE1 and/or RSENSE2. Higher operating voltages, higher values of RSENSE, and more capacitive
MOSFETs will all contribute additional noise across RSENSE
when MOSFETs transition. The CSP/CSN and/or the ISP/
ISN sense signals can be filtered by adding one of the RC
networks shown in Figure 14. The filter shown in Figure
14a filters out differential noise, whereas the filter in Figure
14b filters out the differential and common mode noise at
the expense of an additional capacitor and approximately
twice the capacitance value. It is recommended to Kelvin
the ground connection directly to the paddle of the LT8710
if using the filter in Figure 14b. The filter network should
be placed as close as possible to the LT8710. Resistors
greater than 10Ω should be avoided as this can increase
the offset voltages at the CSP/CSN and ISP/ISN pins.
5.1Ω
RSENSE1, RSENSE2
CSP OR ISP
2.2nF
LT8710
CSN OR ISN
5.1Ω
8710 F014a
Input Overvoltage Protection
Whenever the MODE pin is low to allow current to flow
from output to input, it is strongly recommended to add
a couple external components to protect the input from
overvoltage as shown in Figure 13 below. With either
VIN
Figure 14a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins
5.1Ω
VIN
4.7nF
1k
VIN_OVP = VZ + 1.224V
OR
LT8710
RSENSE1, RSENSE2
ROVP2
MODE
CSP OR ISP
4.7nF
MODE
ROVP1
(
VIN_OVP = 1.224V • 1 +
ROVP2
ROVP1
5.1Ω
)
8710 F13
Figure 13. Input Overvoltage Protection
CSN OR ISN
8710 F014b
Figure 14b. Differential and Common Mode RC Filter on CSP/
CSN and/or ISP/ISN Pins
8710f
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23
LT8710
Applications Information
The RC product should be kept less than 30ns, which is
simply the total series R (5.1Ω+5.1Ω in this case) times
the equivalent capacitance seen across the sense pins
(2.2nF for Figure 14a and 2.35nF for Figure 14b).
SWITCHING FREQUENCY
The LT8710 uses a constant frequency architecture between
100kHz and 750kHz. The frequency can be set using the
internal oscillator or can be synchronized to an external
clock source. Selection of the switching frequency is a
trade-off between efficiency and component size. Low
frequency operation increases efficiency by reducing
MOSFET switching losses, but requires larger inductance
and/or capacitance to maintain low output ripple voltage.
For high power applications, consider operating at lower
frequencies to minimize MOSFET heating from switching
losses. The switching frequency can be set by placing an
appropriate resistor from the RT pin to ground and tying
the SYNC pin low. The frequency can also be synchronized
to an external clock source driven into the SYNC pin. The
following sections provide more details.
Oscillator Timing Resistor (RT)
The operating frequency of the LT8710 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
resistor from the RT pin to ground. The oscillator frequency
is calculated using the following formula:
f=
35,880
(RT +1)
35,880
–1
f
Clock Synchronization
An external source can set the operating frequency of the
LT8710 by providing a digital clock signal into the SYNC
pin (RT resistor still required). The LT8710 will operate at
the SYNC clock frequency. The LT8710 will revert to its
internal free-running oscillator clock when the SYNC pin
is driven below 0.4V for a few free-running clock periods.
24
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
1.SYNC may not toggle outside the frequency range of
100kHz to 750kHz unless it is stopped below 0.4V
to enable the free-running oscillator.
2.The SYNC frequency can always be higher than the
free-running oscillator frequency (as set by the RT
resistor), fOSC, but should not be less than 25%
below fOSC.
After SYNC begins toggling, it is recommended that switching activity is stopped before the SYNC pin stops toggling.
Excess negative inductor current can result when SYNC
stops toggling as the LT8710 transitions from the external
SYNC clock source to the internal free-running oscillator
clock. Switching activity can be stopped by driving the
EN/FBIN pin low.
LDO REGULATORS
The LT8710 has two linear regulators to run the BG and
TG gate drivers. The INTVCC LDO regulates 6.3V (typical)
above ground, and the INTVEE regulator regulates 6.18V
(typical) below the BIAS pin.
INTVCC LDO Regulator
where f is in kHz and RT is in k. Conversely, RT (in k) can
be calculated from the desired frequency (in kHz) using:
RT =
Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1
from becoming set (see Block Diagram). As a result, the
switching operation of the LT8710 will stop.
The INTVCC LDO is used as the top rail for the BG gate
driver for positive output converters. In the case of a negative output converter, the INTVCC LDO is used as the top
rail for both the BG and TG gate drivers (BIAS and INTVEE
must tie to INTVCC and GND respectively). An external
capacitor greater than 2.2µF must be placed from the
INTVCC pin to ground. The UVLO threshold on INTVCC is
4V (typical), and the LT8710 will be in reset until the LDO
comes out of UVLO.
The INTVCC LDO can run off VIN or BIAS and will intelligently select to run off the best for minimizing chip
power loss, but at the same time, select the proper input
for maintaining INTVCC as close to 6.3V as possible. For
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8710f
LT8710
Applications Information
VOLTAGE
24V
INTVEE LDO Regulator
VIN
BIAS
12V
11.2V
8.5V
8V
VIN
BIAS
VIN
BIAS
SELECTED INPUT
TIME
8710 F15
Figure 15. INTVCC Input Voltage Selection
example, Figure 15 is a plot that shows an application
where VOUT/BIAS is regulated to 12V and VIN starts at
24V and ramps down to 5V and indicates that INTVCC is
regulating from VIN or BIAS.
Overcurrent protection circuitry typically limits the maximum current draw from the LDO to ~125mA and ~65mA
when running from VIN and BIAS respectively. When INTVCC
is below ~3.5V during start-up or an overload condition,
the typical current limit is reduced to ~25mA when running
from either VIN or BIAS. If the selected input voltage is
greater than 20V (typical), then the current limit of the LDO
reduces linearly with input voltage to limit the maximum
power in the INTVCC pass device. See the INTVCC Current
Limit vs VIN or BIAS plot in the Typical Performance Characteristics. If the die temperature exceeds 175°C (typical),
the current limit of the LDO drops to 0.
Power dissipated in the INTVCC LDO should be minimized to
improve efficiency and prevent overheating of the LT8710.
The current limit reduction with input voltage circuit helps
prevent the part from overheating, but these guidelines
should be followed. The maximum current drawn through
the INTVCC LDO occurs under the following conditions:
1.Large (capacitive) MOSFETs being driven at high
frequencies.
2.The converter’s switch voltage (VOUT for boost or
VIN + |VOUT| for dual inductor converters) is high,
thus requiring more charge to turn the MOSFET
gates on and off.
In general, use appropriately sized MOSFETs and lower
the switching frequency for higher voltage applications to
keep the INTVCC current at a minimum.
The BIAS and INTVEE voltages are used for the top and
bottom rails of the TG gate driver respectively. An external capacitor greater than 2.2µF must be placed between
the BIAS and INTVEE pins. The UVLO threshold on the
regulator (BIAS-INTVEE) is 3.42V (typical) as long as the
BIAS voltage is greater than ~3.36V. The TG pin can begin
switching after the INTVEE regulator comes out of UVLO.
For positive output converters, BIAS must be tied to the
converter’s output voltage. For negative output converters,
BIAS must connect to the INTVCC pin and the INTVEE pin
ties to ground. In this manner, the voltage of the INTVEE
regulator is driven to the INTVCC voltage of 6.3V and hence
the TG gate driver will have levels of 0V and 6.3V.
Overcurrent protection circuitry typically limits the maximum current draw from the regulator to ~70mA. If the
BIAS voltage is greater than 20V (typical), then the current
limit of the regulator reduces linearly with input voltage
to limit the maximum power in the INTVEE pass device.
See the INTVEE Current Limit vs BIAS plot in the Typical
Performance Characteristics.
The same thermal guidelines from the INTVCC LDO Regulator section apply to the INTVEE regulator as well.
NON-SYNCHRONOUS CONVERTER
It may be desirable in some applications to replace the
external PFET with a Schottky diode to make a nonsynchronous converter. One example would be a high
output voltage application because the voltage drop
across the rectifier has a small affect on the efficiency of
the converter. In fact, for high output voltage applications,
replacing the PFET with a Schottky may result in higher
efficiency because the LT8710 doesn’t have to supply gate
drive to the PFET. Figure 16 shows the recommended
connections for using the LT8710 as a non-synchronous
boost converter, however the same concept can be used
for any other converter.
Note that the MODE pin must be tied high if using the
LT8710 as a non-synchronous converter or else the output might not be regulated at light load. Also, the TG pin
8710f
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25
LT8710
Applications Information
must be left floating or permanent damage could occur to
the TG gate driver. The schematic of Figure 16 could be
modified if needed. If it is not desirable to monitor and/
or control the output current, RSENSE2 is not needed and
simply tie the ISP and ISN pins to INTVCC. The IMON pin
can be left floating or can connect to ground. The BIAS and
INTVEE pins can tie to ground if the dual input feature of
the INTVCC LDO is not needed and VIN stays above 4.5V.
L1
RSENSE2
VIN
MN
CIN1
VOUT
COUT1
COUT2
RIN1
EN/FBIN
CSN CSP
LT8710
CIN2
INTVCC
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
ISN
INTVEE
MODE
+
TG
ISP
BIAS
RIN2
• Place bypass capacitors for the INTVCC and INTVEE
(between BIAS and INTVEE) pins (2.2µF or greater) as
close as possible to the LT8710.
• Keep length of loop (high speed switching path) governing RSENSE1, MN, MP, RSENSE2, COUT, and ground return
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
RSENSE1
BG
VIN
• Place bypass capacitors for the VIN and BIAS pins (1µF
or greater) as close as possible to the LT8710.
VIN
VOUT
RFBX
L1
FBX
GND
IMON
MP
8710 F16
Figure 16. Simplified Schematic of a Non-Synchronous
Boost Converter
MN
RSENSE2
CIN
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
COUT
RSENSE1
General Layout Guidelines
LT8710
CKT
GND
• To optimize thermal performance, solder the exposed
pad of the LT8710 to the ground plane with multiple
vias around the pad connecting to additional ground
planes.
Figure 17. Suggested Component Placement for Boost Topology
• High speed switching path (see specific topology below
for more information) must be kept as short as possible.
SEPIC Topology Specific Layout Guidelines
• The FBX, VC, IMON, and RT components should be
placed as close to the LT8710 as possible, while being
far away as practically possible from switching nodes.
The ground for these components should be separated
from the switch current path.
26
8705 F17
• Keep length of loop (high speed switching path) governing RSENSE1, MN, C1, MP, RSENSE2, COUT, and ground
return as short as possible to minimize parasitic inductive spikes at the switch node during switching.
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Applications Information
VIN
•
L1 L2
VOUT
C1
VIN
• L1
•
•
VOUT
L2
C1
MP
MN
MN
CIN
RSENSE2
CIN
MP
C2
R1
COUT
D1
RSENSE1
RSENSE1
RSENSE2
LT8710
CKT
LT8710
CKT
COUT
GND
GND
8705 F19
8705 F18
Figure 19. Suggested Component Placement for Dual Inductor
Inverting Topology
Figure 18. Suggested Component Placement for SEPIC Topology
Dual Inductor Inverting Topology Specific Layout
Guidelines
• Keep ground return path from the low side of RSENSE1
and RSENSE2 (to chip) separated from CIN’s and COUT’s
ground return path (to chip) in order to minimize switching noise coupling into the input and output. Notice the
cuts in the ground return for the low side of RSENSE1
and RSENSE2.
• Keep length of loop (high speed switching path) governing RSENSE1, MN, C1, MP, RSENSE2, and ground return
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
Current Sense Resistor Layout Guidelines
• Route the CSP/CSN and ISP/ISN lines differentially
(close together) from the chip to the current sense
resistor as shown in Figure 20.
• Place the vias that connect the CSP/CSN and ISP/ISN
lines directly at the terminals of the current sense resistor as shown in Figure 20.
RSENSE1, 2
TO
CURRENT
SENSE
PINS
8705 F20
Figure 20. Suggested Routing and Connections of CSP/CSN
and ISP/ISN Lines
THERMAL CONSIDERATIONS
Overview
The primary components on the board that consume the
most power and produce the most heat are the power
switches, MN and MP, the power inductor, and the LT8710
IC. It is imperative that a good thermal path be provided
for these components to dissipate the heat generated
within the packages. This can be accomplished by taking
advantage of the thermal pads on the underside of the
packages. It is recommended that multiple vias in the
printed circuit board be used to conduct heat away from
each of these components and into a copper plane with as
much area as possible. For the case of the power switches,
the copper area of the drain connections shouldn’t be too
big as to create a large EMI surface that can radiate noise
around the board.
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LT8710
Applications Information
Power MOSFET Loss and Thermal Calculations
The LT8710 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. Important parameters for estimating
the power dissipation in the MOSFETs are:
1. On-resistance (RDSON)
2. Gate-to-drain charge (QGD)
3. PFET body diode forward voltage (VBD)
4. VDS of the FETs during their Off-Time
PMOSFET = PI2R + PSWITCHING
PMN = IN2 •RDSON + VDS •IN • f • tRF + PRR – N
I

PMP =IP2 •RDSON +VBD• IPK + VY • f•140ns+PRR – P

1.6
I
i
i
ISW = OUT ; IPK =ISW + RIPPLE ; IVY =ISW – RIPPLE
(1– DC)
2
2
2
i

IN = DC • ISW 2 + RIPPLE 

12 
IP =
5. Switch current (ISW)
6. Switching frequency (f)
The power loss in each power switch has a DC and AC
term. The DC term is when the power switch is fully on,
and the AC term is when the power switch is transitioning
from on-off or off-on.
The following applies for both the NFET and PFET power
switches. For a boost application, the average current
through the MOSFET (ISW) during its on-time, is the same
as the average input current. The magnitude of the drainto-source voltage, VDS, during its off-time is approximately
VOUT. For a SEPIC or dual inductor inverting application,
the average current through each MOSFET (ISW) during
its on-time, is the sum of the average input current and
the output current. The |VDS| voltage during the off-time
is approximately VIN + |VOUT|. During the non-overlap time
of the gate drivers, the peak and valley inductor current
is flowing through the body diode of the PFET. Below are
the equations for the power loss in MN and MP.
(1–DC) • ISW 2 +
iRIPPLE2 
12 
V •I • t • f
PRR – N ≈ DS RR RR
2
V •I • t • f
PRR – P ≈ DS RR RR
2
where:
f
= Switching Frequency
IN = NFET RMS Current
IP = PFET RMS Current
tRF =Average of the rise and fall times of the NFET’s
drain voltage
ISW=
Average switch current during its on-time
IPK = Peak inductor current
IVY = Valley inductor current
iRIPPLE = Inductor ripple current
DC = Switch duty cycle (see Power Switch Duty
Cycle section in Appendix)
VBD = PFET body diode forward voltage at ISW
VDS = Voltage across the FET when it’s off. VOUT for
a boost, VIN + |VOUT| for a dual inductor
inverting or SEPIC converter
PRR-N = PFET body diode reverse recovery power loss
in the NFET
PRR-P=PFET body diode reverse recovery power loss
in the PFET
28
8710f
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LT8710
Applications Information
IRR = Current needed to remove the PFET body diode
charge
VSELECT=INTVCC LDO selected input voltage, VIN or
BIAS (see LDO REGULATORS section)
tRR=
Reverse recovery time of PFET body diode
Higher of VIN and BIAS.
VMAX=
Typical values for tRF are 10ns to 40ns depending on the
MOSFET capacitance and drain voltage. In general, the
lower the QGD of the MOSFET, the faster the rise and fall
times of its drain voltage. For best calculations, measure
the rise and fall times in the application.
PFET body diode reverse recovery power loss is dependent on many factors and can be difficult to quantify in
an application. In general, this power loss increases with
higher VDS and/or higher switching frequency.
Chip Power and Thermal Calculations
Power dissipation in the LT8710 chip comes from three
primary sources: INTVCC and INTVEE LDOs providing gate
drive to the BG and TG pins and additional input quiescent
current. The average current through each LDO is determined by the gate charge of the power switches, MN and
MP, and the switching frequency. Below are the equations
for calculating the chip power loss followed by examples.
Noninverting Converter: The INTVCC LDO primarily supplies voltage for the BG gate driver. The BIAS and INTVEE
voltages supply the top and bottom rails of the TG gate
driver respectively. The chip Q current comes from the
higher of VIN and BIAS. Below are the chip power equations for a noninverting converter:
PVCC = 1.04 • QMN • f • VSELECT
PVEE1 = QMP • f • VBIAS
PVEE2 = 3.1mA • (1 – DC) • VBIAS
PQ = 4mA • VMAX
PVCC = 1.04 • QMN • f • VIN
PVEE1 = QMP • f • VIN
PVEE2 = 3.15mA • (1 – DC) • VIN
PQ = 5.5mA • VIN
where:
f=
Switching frequency
DC=
Switch duty cycle (see Power Switch Duty Cycle
section in Appendix)
QMN=Total gate charge of NFET power switch (MN)
at 6.3VGS
QMP=Total gate charge of PFET power switch (MP)
at 6.3VSG
Chip Power Calculations Example
Table 4 calculates the power dissipation of the LT8710 for
a 200kHz, 3V – 40V to 5V SEPIC application when VIN is
12V. From PCHIP in Table 4, the die junction temperature
can be calculated using the appropriate thermal resistance
and worst-case ambient temperature:
where:
f
Inverting Converter: Due to BIAS connecting to INTVCC
and INTVEE connecting to ground (see Typical Applications), all the chip power comes from the VIN pin. The
INTVCC LDO primarily supplies voltage for both the BG
and TG gate drivers. The chip Q current comes from
VIN. For consistency, the power that’s needed to run
the TG gate driver is still labeled as PVEE even though
the power is coming from INTVCC. Below are the chip
power equations for an inverting converter:
=Switching frequency
DC =Switch duty cycle (see Power Switch Duty
Cycle section in Appendix)
QMN =Total gate charge of NFET power switch (MN)
at 6.3VGS
QMP =Total gate charge of PFET power switch (MP)
at 6.18VSG
TJ = TA + QJA • PCHIP
where TJ = die junction temperature, TA = ambient temperature and θJA is the thermal resistance from the silicon
junction to the ambient air.
The published θJA value is 38°C/W for the TSSOP exposed
pad package. In practice, lower θJA values are realizable
if board layout is performed with appropriate grounding
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29
LT8710
Applications Information
(accounting for heat sinking properties of the board) and
other considerations listed in the Layout Guidelines section. For instance, a θJA value of ~22°C/W was consistently
achieved when board layout was optimized as per the
suggestions in the Layout Guidelines section.
Thermal Lockout
If the die temperature reaches ~175°C, the part will go into
reset, so the power switches turn off and the soft-start
capacitor will be discharged. The LT8710 will come out of
reset when the die temperature drops by ~5°C (typical).
Table 4. Power Calculations Example for a 200kHz, 3V to 40V to 5V/5A SEPIC (VIN = 12V, MN = FDMS86500L and MP = SUD50P06-15)
DEFINITION OF VARIABLES
DC = Switch Duty Cycle
PVCC = INTVCC LDO Power Driving
the BG Gate Driver
EQUATION
DC ≅
VOUT
VIN + VOUT
DESIGN EXAMPLE
DC ≅
5V
12V + 5V
VALUE
DC ≅ 29.4%
PVCC = 1.04 • QMN • f • VSELECT
PVCC = 1.04 • 73nC • 200kHz • 12V
PVCC = 182.2mW
PVEE1 = QMP • f • VBIAS
PVEE1 = 55nC • 200kHz • 5V
PVEE1 = 55mW
PVEE2 = Additional TG Gate Driver
Power Loss
PVEE2 = 3.1mA • (1 – DC) • VBIAS
PVEE2 = 3.1mA • (1– 0.294) • 5V
PVEE2 = 10.9mW
PQ = Chip Bias Loss
VMAX = Higher Voltage of VIN and
BIAS
PQ = 4mA • VMAX
PQ = 4mA • 12V
PQ = 48mW
QMN = NFET Total Gate Charge at
VGS = 6.3V
f = Switching Frequency
VSELECT = LDO Chooses VIN
PVEE1 = INTVEE LDO Power
Driving the TG Gate Driver
QMP = PFET Total Gate Charge at
VSG = 4.25V
PCHIP = 296.1mW
30
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LT8710
AppENDIX
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the external power NFET (MN in the
Block Diagram) cannot remain on for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC MAX
( T –MinOffTime) •100%
= P
TP
where TP is the clock period and MinOffTime (found in the
Electrical Characteristics) is a maximum of 480ns.
Conversely, the external power NFET (MN in the Block
Diagram) cannot remain off for 100% of each clock cycle,
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum allowable duty cycle given by:
DC MIN =
(MinOnTime)
•100%
TP
where TP is the clock period and MinOnTime (found in the
Electrical Characteristics) is a maximum of 420ns.
The application should be designed such that the operating
duty cycle is between DCMIN and DCMAX.
Duty cycle equations for several common topologies are
given below where VON_MP is the voltage drop across the
external power PFET (MP) when it is on, and VON_MN is
the voltage drop across the external power NFET (MN)
when it is on.
VOUT – VIN + VON_MP
VOUT + VON_MP – VON_MN
For the SEPIC or dual inductor inverting topology (see
Figures 6 and 7):
DC SEPIC_&_INVERT ≅
INDUCTOR SELECTION
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. Also
to improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low DCR
(copper-wire resistance) to reduce I2R losses, and must be
able to handle the peak inductor current without saturating. Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology where each inductor carries a fraction of
the total switch current. Molded chokes or chip inductors
do not have enough core area to support peak inductor
currents in the 5A to 15A range. To minimize radiated
noise, use a toroidal or shielded inductor. See Table 5 for
a list of inductor manufacturers.
Table 5. Inductor Manufacturers
Coilcraft
MSS1278, XAL1010, and
MSD1278 Series
www.coilcraft.com
Cooper
Bussmann
DRQ127, DR127, and
HCM1104 Series
www.cooperbussmann.com
Vishay
IHLP Series
www.vishay.com
Würth
WE-DCT Series
WE-CFWI Series
www.we-online.com
Minimum Inductance
For the boost topology (see Figure 5):
DC BOOST ≅
The LT8710 can be used in configurations where the duty
cycle is higher than DCMAX, but it must be operated in the
discontinuous conduction mode (MODE pin must be high)
so that the effective duty cycle is reduced.
| VOUT |+VON_MP
VIN+ | VOUT |+VON_MP – VON_MN
Although there can be a trade-off with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance; (1) providing
adequate load current, and (2) avoidance of subharmonic
oscillation, and (3) supplying a minimum ripple current to
avoid false tripping of the current comparator.
8710f
For more information www.linear.com/LT8710
31
LT8710
AppENDIX
Adequate Load Current
Avoiding Subharmonic Oscillations
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load. In
order to provide adequate load current, L should be at least:
The LT8710’s internal slope compensation circuit will
prevent subharmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that
operate with duty cycles greater than 50%, the inductance
must be at least:
L BOOST ≥
VIN •DC
•I
V
V

2 • f •  CSPN – OUT OUT 
VIN • η 
RSENSE1
Boost
Topology
or
SEPIC
VIN •DC
or
L DUAL ≥
|V |•I
V
 Inverting
2 • f •  CSPN – OUT OUT –IOUT 
VIN • η
RSENSE1
 Topologies
where:
L1 for boost topologies (see Figure 5)
LBOOST=
L1 = L2 for coupled dual inductor topologies
LDUAL=
(see Figures 6 and 7)
L1 || L2 for uncoupled dual inductor topoloLDUAL=
gies (see Figures 6 and 7)
DC=
Switch duty cycle (see previous section)
Current limit voltage at the operating switch
VCSPN=
duty cycle (see Max Current Limit vs Duty
Cycle (CSP – CSN) plot in the Typical Per
formance Characteristics)
RSENSE1=Current sense resistor connected across
the CSP-CSN pins (see Block Diagram)
η=
Power conversion efficiency (assume 90%)
f=
Switching frequency
where
LMIN=L1 for boost topologies (see Figure 5)
LMIN=L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
LMIN=L1 || L2 for uncoupled dual inductor topologies
(see Figures 6 and 7)
Maximum Inductance
Excessive inductance can reduce ripple current to levels
that are difficult for the current comparator (A5 in the Block
Diagram) to cleanly discriminate, thus causing duty cycle
jitter and/or poor regulation. The maximum inductance
can be calculated by:
V •R
•DC
L MAX ≤ IN SENSE1
5m • f
where:
LMAX=L1 for boost topologies (see Figure 5)
LMAX=L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
LMAX=L1 || L2 for uncoupled dual inductor topologies
(see Figures 6 and 7)
Maximum output current
IOUT=
Negative values of LBOOST or LDUAL indicate that the output load current, IOUT, exceeds the switch current limit
capability of the converter. Decrease RSENSE1 to increase
the switch current limit.
32
V •R
•(2 •DC – 1)
L MIN ≥ IN SENSE1
40m •DC • f •(1–DC)
Inductor Current Rating
The inductor(s) must have a rating greater than its (their)
peak operating current to prevent inductor saturation,
which would result in efficiency losses. The maximum
8710f
For more information www.linear.com/LT8710
LT8710
AppENDIX
inductor current (considering start-up and steady-state
conditions) is given by:
IL_PEAK =
54mV – 16mV •DC2
RSENSE1
V •T
+ IN MIN_PROP
L
where
Peak inductor current in L1 for a boost
IL_PEAK=
topology, or the sum of the peak inductor
currents for dual inductor topologies.
TMIN_PROP=100ns (propagation delay through the
current feedback loop).
For wide input voltage range applications, as the input voltage increases, the max peak inductor current also increases
due to the duty cycle decreasing. It is recommended to
utilize the output current limiting feature to reduce the
max peak inductor current given by the following equation:
IL_PEAK =
VISPN
V •DC
+ IN
RSENSE2 •(1–DC) 2 • f •L
where….
VISPN = 57mV max for noninverting converters and
60mV max for inverting converters.
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads, and if
the SS capacitor is sized appropriately to limit inductor
currents at start-up.
POWER MOSFET SELECTION
The LT8710 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. It is important to select MOSFETs for
optimizing efficiency. For choosing an NFET and PFET,
the important device parameters are:
1. Breakdown voltage (BVDSS)
2. Gate threshold voltage (VGSTH)
3. On-resistance (rDSON)
4. Total gate charge (QG)
5. Turn-off delay time (tD(OFF))
6. Package has exposed paddle
The drain-to-source breakdown voltage of the NFET and
PFET power MOSFETs must exceed:
• BVDSS > VOUT for boost converter
• BVDSS > VIN+|VOUT| for SEPIC or dual inductor
inverting converter
If operating close to the BVDSS rating of the MOSFET, check
the leakage specifications on the MOSFET because leakage
can decrease the efficiency of the converter.
The NFET and PFET gate-to-source drive is approximately
6.3V and 6.18V respectively, so logic level MOSFETs are
required. The BG gate driver can begin switching when
the INTVCC voltage exceeds ~4V, so ensure the selected
NFET is in the linear mode of operation with 4V of gateto-source drive to prevent possible damage to the NFET.
The TG gate driver can begin switching when the BIASINTVEE voltage exceeds ~3.42V, so it is optimal that the
PFET be in the linear mode of operation with 3.42V of
gate-to-source drive. However, the PFET is less likely to
get damaged if it’s not operating in the linear region since
the drain-to-source voltage is clamped by its body diode
during the NFET’s off-time. Having said that, try to choose
a PFET with a low body diode reverse recovery time to
minimize stored charge in the PFET. The stored charge in
the PFET body diode gets removed when the NFET switch
turns on and can lead to efficiency hits especially in applications where the VDS of the PFET (during off-time) is
high. For these applications, it may be beneficial to put a
Schottky diode across the PFET to reduce the amount of
charge in the PFET body diode. In applications where the
output voltage is high in magnitude, it may be better to
replace the PFET with a Schottky diode since the converter
may be more efficient with a Schottky.
Power MOSFET on-resistance and total gate charge go
hand-in-hand and are typically inversely proportional to
each other; the lower the on-resistance, the higher total
gate charge. Choose MOSFETs with an on-resistance to
give a voltage drop to be less than 300mV at the peak
8710f
For more information www.linear.com/LT8710
33
LT8710
AppENDIX
current. At the same time, choose MOSFETs with a lower
total gate charge to reduce LT8710 power dissipation and
MOSFET switching losses.
The turn-off delay time (tD(OFF)) of available NFETs is
generally smaller than the LT8710’s non-overlap time.
However, the turn-off time of the available PFETs should
be looked at before deciding on a PFET for a given application. The turn-off time must be less than the non-overlap
time of the LT8710 or else the NFET and PFET could be
on at the same time and damage to external components
may occur. If the PFET turn-off delay time as specified in
the data sheet is less than the LT8710 non-overlap time,
then the PFET is good to use. If the turn-off delay time is
longer than the non-overlap time, it doesn’t necessarily
mean it can’t be used. It may be unclear how the PFET
manufacturer measures the turn-off delay time, so it is
best to measure the PFET turn-off delay time with respect
to the PFET gate voltage.
Finally, both the NFET and PFET power MOSFETs should
be in a package with an exposed paddle for the drain
connection to be able to dissipate heat. The on-resistance
of MOSFETs is proportional to temperature, so it’s more
efficient if the MOSFETs are running cool with the help
of the exposed paddle. See Table 6 for a list of power
MOSFET manufacturers.
Table 6. Power MOSFET (NFET and PFET) Manufacturers
Fairchild Semiconductor
www.fairchildsemi.com
On-Semiconductor
www.onsemi.com
Vishay
www.vishay.com
Diodes Inc.
www.diodes.com
INPUT AND OUTPUT CAPACITOR SELECTION
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and
low ESR (equivalent series resistance). Tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
34
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
noise. A minimum 1µF ceramic capacitor should also be
placed from VIN to GND and from BIAS to GND as close
to the LT8710 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce ripple voltage and help reduce power loss in the
higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
Input Capacitor, CIN
The input capacitor, CIN, sees the ripple current of the input
inductor, L1, which eases the capacitance requirements of
CIN. Below is the equation for calculating the capacitance
of CIN for 0.5% input voltage ripple:
CIN >
DC
8 •L • f2 • 0.005
where:
DC=Switch duty cycle (see Power Switch Duty Cycle
section)
L=
LBOOST or LDUAL (see Inductor Selection section)
f=
Switching frequency
The worst-case for the input capacitor (largest capacitance
needed) is when the input voltage is at its lowest because
the duty cycle is the highest. Keep in mind that the voltage rating of the input capacitor needs to be greater than
the maximum input voltage. This equation calculates the
capacitance value during steady-state operation and may
need to be adjusted for desired transient response. Also,
this assumes no ESR, so the input capacitance may need
to be larger depending on the equivalent ESR of the input
capacitor(s).
Output Capacitor, COUT
The output capacitor, COUT, in a boost or SEPIC topology
has chopped current flowing through it, whereas the output
capacitor in a dual inductor inverting topology sees the
8710f
For more information www.linear.com/LT8710
LT8710
AppENDIX
inductor ripple current. Below is the equation for calculating
the capacitance of COUT for 0.5% output voltage ripple:
Boost or
IOUT •DC
COUT >
SEPIC
f • 0.005 • VOUT
Topologies
or
Dual Inductor
1–DC
COUT >
Inverting
8 •L • f 2 • 0.005
Topology
where:
IOUT=Maximum output current of converter
Switch duty cycle (see Power Switch Duty Cycle
DC=
section)
L=
LBOOST or LDUAL (see Inductor Selection section)
f=
Switching frequency
The worst-case for the output capacitor (largest capacitance
needed) is when the output regulation voltage is relatively
low. This equation calculates the capacitance value during
steady-state operation and may need to be adjusted for
desired transient response. Also, this assumes no ESR, so
the output capacitance may need to be larger depending on
the equivalent ESR of the output capacitor(s). See Table 7
for a list of ceramic capacitor manufacturers.
Table 7. Ceramic Capacitor Manufacturers
TDK
www.tdk.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
the optimum value for RC can be found. The series capacitor can be reduced or increased from 4.7nF to speed up
the converter or slow down the converter, respectively.
For the circuit in Figure 7, a 3.3nF series cap was used.
Figures 21a to 21c illustrate this process for the circuit
of Figure 7 with a load current stepped between 2A and
5.5A with an input voltage of 9V. Figure 21a shows the
transient response with RC equal to 1k. The phase margin is poor as evidenced by the excessive ringing in the
output voltage and inductor current. In Figure 21b, the
value of RC is increased to 4k, which results in a more
damped response. Figure 21c shows the results when RC is
increased further to 11.5k. The transient response is nicely
damped and the compensation procedure is complete.
VOUT
200mV/DIV
AC-COUPLED
LOAD STEP
5A/DIV
IL1 + IL2
5A/DIV
RC = 1k
200µs/DIV
8705 F21a
Figure 21a. Transient Response Shows Excessive Ringing
VOUT
200mV/DIV
AC-COUPLED
LOAD STEP
5A/DIV
IL1 + IL2
5A/DIV
COMPENSATION – ADJUSTMENT
To compensate the feedback loop of the LT8710, a series
resistor capacitor network in parallel with an optional
single capacitor should be connected from the VC pin to
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 4.7nF being a good starting
value. The optional parallel capacitor should range in value
from 47pF to 220pF with 100pF being a good starting
value. The compensation resistor, RC, is usually in the
range of 5k to 50k. A good technique to compensate a
new application is to use a 100k potentiometer in place
of the series resistor RC. With the series and parallel
capacitors at 4.7nF and 100pF respectively, adjust the
potentiometer while observing the transient response and
RC = 4k
200µs/DIV
8705 F21b
Figure 21b. Transient Response is Better
VOUT
200mV/DIV
AC-COUPLED
LOAD STEP
5A/DIV
IL1 + IL2
5A/DIV
RC = 11.5k
200µs/DIV
8705 F21c
Figure 21c. Transient Response is Well Damped
For more information www.linear.com/LT8710
8710f
35
LT8710
AppENDIX
COMPENSATION – THEORY
Like all other current mode switching regulators, the
LT8710 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT8710: a
fast current loop which does not require compensation,
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 22 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the IC, inductor and PFET have been replaced by a combination of the equivalent transconductance
amplifier gmp and the current controlled current source
ηV
(which converts IVIN to V IN I VIN ). Gmp acts as a current
OUT
source where the peak input current, IVIN, is proportional
to the VC voltage and current sense resistor, RSENSE1.
+
VOUT
IVIN
η • VIN
VOUT
• IVIN
RL
CPL
CF
RC
CC
RO
+
gma
RFBX
R2
FBX
–
8710 F22
R2
CC: COMPENSATION CAPACITOR
COUT: OUTPUT CAPACITOR
CPL: PHASE LEAD CAPACITOR
CF: HIGH FREQUENCY FILTER CAPACITOR
gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC
gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
RC: COMPENSATION RESISTOR
RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOADMAX
RO: OUTPUT RESISTANCE OF gma
R2, RFBX: FEEDBACK RESISTOR DIVIDER NETWORK
RESR: OUTPUT CAPACITOR ESR
η: CONVERTER EFFICIENCY (~90% AT HIGHER CURRENTS)
Figure 22. Boost Converter Equivalent Model
36
RL
COUT
1.213V
REFERENCE
VC
RESR
The error amplifier, gma, is nominally about 200µmhos
with a source and sink current of about 12µA and 19µA
respectively.
From Figure 22, the DC gain, poles and zeros can be
calculated as follows:
DC GAIN:
VIN RL
0.5 •R2
• •
VOUT 2 RFBX +0.5 •R2
2
Output Pole: P1=
2 • π •RL •COUT
1
Error Amp Pole: P2 =
2 • π •(R O+R C)•CC
ADC = gma •RO • gmp • η•
1
2 • π •R C •C C
1
ESR Zero: Z2 =
2 • π •RESR •COUT
VIN2 •R L
RHP Zero: Z3 =
2 • π • VOUT2 •L
f
High Frequency Pole: P3 > S
3
1
Phase Lead Zero: Z4 =
2 • π •RFBX •CPL
1
Phase Lead Pole: P4 =
R • 0.5 •R2
2 • π • FBX
•C
RFBX +0.5 •R2 PL
1
C
Error Amp Filter Pole: P5 =
,CF < C
R •R
10
2 • π • C O •CF
RC +RO
Error Amp Zero: Z1=
–
gmp
Note that the maximum output currents of gmp and gma
are finite. The external current sense resistor, RSENSE1,
sets the value of:
1
gmp ≈
6 •RSENSE1
The current mode zero (Z3) is a right half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
8710f
For more information www.linear.com/LT8710
LT8710
AppENDIX
Using the circuit in Figure 24 with a 4A load as an example,
Table 9 shows the parameters used to generate the bode
plot shown in Figure 23.
Table 9: Bode Plot Parameters
From Figure 23, the phase is –135° when the gain reaches
0dB giving a phase margin of 45°. The crossover frequency is 20kHz, which is about three times lower than
the frequency of the RHP zero Z3 to achieve adequate
phase margin.
VALUE
UNITS
COMMENT
RL
3
Ω
Application Specific
COUT
88
µF
Application Specific
RESR
2
mΩ
Application Specific
RO
350
kΩ
Not Adjustable
100
CC
3300
pF
Adjustable
80
100
pF
Optional/Adjustable
0
pF
Optional/Adjustable
RC
18
kΩ
Adjustable
RFBX
130
kΩ
Adjustable
R2
14.5
kΩ
Not Adjustable
VOUT
12
V
Application Specific
VIN
5
V
Application Specific
gma
200
µmho
Not Adjustable
gmp
167
mho
Application Specific
L
1.3
µH
Application Specific
fOSC
400
kHz
Adjustable
120
–45
–135
60
GAIN
–180
40
–225
20
–270
0
–315
100
1k
10k
FREQUENCY (Hz)
100k
–360
1M
Figure 23. Bode Plot for Example Boost Converter
MP
BG
RIN1
13.3k
RSENSE2
5m
VOUT
12V
6A
MN
×2
RSENSE1
COUT
22µF
×4
CSN CSP
TG
ISP
VIN
ISN
EN/FBIN
CIN1
22µF
×4
45° AT
20kHz
8710 F23
1m
CIN2
330µF
–90
PHASE
–20
10
L1
1.3µH
+
0
GAIN (dB)
CF
CPL
VIN
5V
140
PHASE (DEG)
PARAMETER
RIN2
10k
2.2µF
LT8710
BIAS
INTVEE
MODE
2.2µF
RFBX
130k
FBX
INTVCC
FLAG
RT
VC
RT
88.7k
RC
18k
SYNC
GND
IMON
SS
CIMON
47nF
CSS
220nF
CF
100pF
CC
3.3nF
8710 F24
Figure 24. 5V to 12V Boost Converter
8710f
For more information www.linear.com/LT8710
37
LT8710
Typical Application
300kHz, 4.5V to 25V Input to –5V Output Delivers Up to 7A Output Current
CIN1
10µF
×4
MP
MN
1.5m
499Ω
RSENSE1
D1
4m
0.47µF
BG
VIN
CIN2
120µF
RSENSE2
COUT2
330µF
COUT1
100µF
×2
CSN CSP TG
ISN
13.3k
+
VOUT
–5V
7A
•
L2
2.2µH
+
•
VIN
4.5V TO 25V
C1
10µF ×2
L1
2.2µH
ISP
EN/FBIN
10k
2.2µF
MODE
BIAS
LT8710
INTVEE
INTVCC
60.4k
FBX
INTVCC
RT
FLAG
118k
SYNC
GND
2.2µF
VC
IMON
SS
47nF
100pF
220nF
11.5k
3.3nF
8710 TA02a
L1, L2: WÜRTH 2.2µH WE-CFWI 74485540220
MN: FAIRCHILD FDMS8333L
MP: FAIRCHILD FDD4141
RSENSE1: 1.5mΩ 2010
RSENSE2: 4mΩ 2512
D1: NXP PMEG2010EA
Transient Response with 2A to 5.5A to 2A
Output Load Step (VIN = 12)
Efficiency and Power Loss
90
7
80
6
70
5
65
4
50
3
40
2
30
1
EFFICIENCY (%)
8
VIN = 5V
VIN = 12V
0
1
2
3
4
5
LOAD CURRENT (A)
6
7
VOUT
200mV/DIV
AC-COUPLED
POWER LOSS (W)
100
20
CIN1: 10µF, 50V, 1210, X7S
CIN2: OSCON 120µF, 35V, 35SVPF120M
COUT1: 100µF, 6.3V, 1812, X5R
COUT2: OSCON 330µF, 16V, 16SEQP330M
C1: 10µF, 50V, 1210, X7S
LOAD STEP
5A/DIV
IL1 + IL2
5A/DIV
200µs/DIV
8710 TA02c
0
8710 TA02b
38
8710f
For more information www.linear.com/LT8710
LT8710
Typical Application
300kHz, SuperCap Backup Power
VIN WHEN VIN IS PRESENT
10.5V WHEN VIN IS REMOVED
VSYSTEM =
DIN
L1, 10µH
C1, 10µF
CIN1
22µF
×2
INPUT POWER
SOURCE CAN BE
REMOVED
MN
5m
RSENSE1
RSENSE2
50m
MP
•
VIN
12V ±5%
L2
10µH
COUT
22µF
×2
5.1Ω 5.1Ω
•
4.7nF 4.7nF
BG
VIN
49.9k
CSN CSP
TG
ISP
LT8710
ISN
EN/FBIN
+
CIN2
120µF
RT
118k
1.2k
165k
FBX
RT
SYNC
GND
1.2k
INTVEE
MODE
1k
1.2k
2.2µF
INTVCC
D1
15V
1.2k
BIAS
10k 2.2µF
1.2k
1.2k
FLAG
+
+
+
+
+
+
VOUT
15V
CS1
60F
CS2
60F
CS3
60F
CS4
60F
CS5
60F
CS6
60F
VC
IMON
SS
47nF
100pF
220nF
14.3k
2.2nF
8710 TA03a
L1, L2: COILCRAFT 10µH MSD1278-103ML
MN: FAIRCHILD FDMC8327L
MP: VISHAY Si7611DN
RSENSE1: 5mΩ 2010
RSENSE2: 50mΩ 2512
DIN: APPROPRIATE SCHOTTKY DIODE OR IDEAL
DIODE SUCH AS LTC4358, LTC4352, LTC4412, ETC.
CIN1: 22µF, 25V, 1812, X7R
COUT: 22µF, 25V, 1812, X7R
C1: 10µF, 25V, 1210, X7R
CS1-6: POWERSTOR HB1840-2R5606-R
D1: CENTRAL SEMI CMDZ5245B-LTZ
SuperCaps Charging When VIN Is Applied
VIN
10V/DIV
System Hold-Up Time vs
System Load Current
200
VOUT
10V/DIV
VIMON
1V/DIV
VSYSTEM = 10.5V
DURING HOLD-UP
175
IL1 + IL2
5A/DIV
HOLD-UP TIME (s)
150
30s/DIV
8710 TA03c
125
SuperCaps Hold-Up System at 10.5V for ~83s
When VIN Is Removed (ISYSTEM = 1A)
100
75
50
VIN
10V/DIV
25
VOUT
10V/DIV
0
0
0.5
1
1.5
2
LOAD CURRENT (A)
2.5
3
8710 TA03b
VIMON
1V/DIV
IL1 + IL2
5A/DIV
30s/DIV
8710 TA03d
8710f
For more information www.linear.com/LT8710
39
LT8710
Typical Application
400kHz, 12V Boost Converter Delivers Up to 6A from a 4.5V to 9V Input
L1
1.3µH
VIN
4.5 TO 9V
CIN1
22µF
×4
1m
BG
VIN
MN
×2
RSENSE1
COUT2
330µF
COUT1
22µF
×4
CSN CSP
TG
ISP
LT8710
ISN
13.3k
+
RSENSE2
5m
MP
EN/FBIN
COUT2
330µF
BIAS
10k
2.2µF
MODE
2.2µF
+
VOUT
12V
6A
INTVEE
INTVCC
130k
FBX
RT
FLAG
88.7k
SYNC
GND
VC
IMON
100pF
SS
47nF
220nF
18k
3.3nF
8710 TA04a
L1: WÜRTH 1.3µH WE-HCI 7443551130
MN: VISHAY SiR802DP
MP: VISHAY Si7635DP
RSENSE1: 1mΩ 2512
RSENSE2: 5mΩ 2512
CIN1: 22µF, 16V, 1206, X5R
CIN2: OSCON 330µF, 16V, 16SEQP330M
COUT1: 22µF, 25V, 1812, X7R
COUT2: OSCON 330µF, 16V, 16SEQP330M
Transient Response with 2A to 5A to 2A
Output Load Step (VIN = 5V)
Efficiency and Power Loss
90
7
80
6
70
5
60
4
50
3
40
2
EFFICIENCY (%)
8
30
20
1
2
3
4
LOAD CURRENT (A)
5
LOAD STEP
2A/DIV
IL1 + IL2
5A/DIV
1
VIN = 5V
VIN = 8V
0
VOUT
200mV/DIV
AC-COUPLED
POWER LOSS (W)
100
6
200µs/DIV
8710 TA04c
0
8710 TA04b
40
8710f
For more information www.linear.com/LT8710
LT8710
Typical Application
300kHz, –5V to 5V Output Cleanly Transitions Through 0V with 3A Source and Sink Capability*
RSENSE2
10m
•
VIN
11V TO
13V
TG
C1
10µF ×2
L1
4.4µH
CIN1
22µF
×4
RSENSE1
BG
VIN
+
TG
CSN CSP
TG
ISP
LT8710
ISN
EN/FBIN
2.2µF
VOUT
–5V TO 5V
±3A
MN
3m
CIN2
330µF
L2
4.4µH
•
ISN
ISP
MP
ISP ISN
BIAS
MODE
INTVEE
COUT
100µF
×3
RT
FLAG
118k
2VIN – VOUT
FET BVDSS > 2VIN – VOUT
CIVRATING > VIN – VOUT
60.4k
VIN
2.2µF
FBX
INTVCC
VIN – VOUT
DC =
6.04k
VCNTL=
D1
10nF
0V FOR VOUT = –5V
–0.5V FOR VOUT = 0V
–1V FOR VOUT = 5V
VC
SYNC
GND
IMON
SS
47nF
100pF
220nF
39.2k
Schematic and Equations for Calculating VOUT
2.2nF
VOUT
8710 TA05a
L1, L2: WÜRTH 4.4µH WE-CFWI 74485540440
MN: FAIRCHILD FDMS8333L
MP: FAIRCHILD FDD4141
RSENSE1: 3mΩ 2010
RSENSE2: 10mΩ 2512
CIN1: 22µF, 25V, 1812, X7R
CIN2: OSCON 330µF, 16V, 16SEQP330M
COUT: 100µF, 6.3V, 1812, X5R
C1: 10µF, 25V, 1210, X7R
D1: CENTRAL SEMI CMPD1001
LT8710
FBX
~9.6mV
RFBX
RCNTL
VCNTL
~83.1µA
8710 TA05b
* PATENT PENDING
VOUT = 9.6mV –83.1µA • RFBX –
VOUT Cleanly Transitions Through 0V with a 1V,
100Hz Sine Wave CNTL Signal (RLOAD = 2Ω)
RFBX
RCNTL
(VCNTL – 9.6mV)
Transient Response with Stepping VCNTL from 0V to
–1V to 0V with 2Ω Output Load
VCNTL
1V/DIV
VCNTL
1V/DIV
VOUT
5V/DIV
VOUT
5V/DIV
IL1 + IL2
10A/DIV
IL1 + IL2
10A/DIV
5ms/DIV
8710 TA05c
500µs/DIV
8710 TA05d
8710f
For more information www.linear.com/LT8710
41
LT8710
Typical Application
300kHz, 3A Sealed Lead Acid Battery Charger with an Optional Negative Temp-Co Bulk and Float Battery Voltage
•
VIN
5V TO
30V
C1
10µF ×2
L1
3.5µH
CIN1
10µF
×4
MP1
MN
1.5m
RSENSE1
RSENSE2
16m
L2
3.5µH
COUT
22µF
×4 +
5.1Ω 5.1Ω
•
VOUT
14.7V BULK
13.77V FLOAT
3A CHARGE
SEALED
LEAD ACID
BATTERY
4.7nF 4.7nF
BG
VIN
+
CIN2
100µF
CSN CSP
TG
ISP
LT8710
ISN
13.3k
EN/FBIN
10k
2.2µF
BIAS
INTVEE
MODE
FBX
INTVCC
RT
FLAG
118k
*OPTIONAL
GND
IMON
150k
RNTC
10k
196k
47nF
L1, L2: WÜRTH 3.5µH WE-CFWI 74485540350
MN: FAIRCHILD FDMS86500L
MP1: VISHAY SUD50P06-15
RSENSE1: 1.5mΩ 2010
RSENSE2: 16mΩ 2512
CIN1: 10µF, 50V, 1210, X7S
COUT: 22µF, 25V, 1812, X7R
C1: 10µF, 50V, 1210, X7S
MP2: VISHAY Si2343CDS
RNTC: MURATA NCP18XH103F03RB
100nF
100pF
2.37k
6.8nF
220nF
SEE THE BATTERY CHARGING AND C/10 SECTION
IN APPLICATIONS INFORMATION FOR MORE
INFORMATION ON BATTERY CHARGING
* MP2 DISCONNECTS FBX PIN CURRENT
DRAW FROM BATTERY WHEN LT8710 IS IN
SHUTDOWN
** PLACE 316kΩ AND 100nF AS CLOSE
TO THE FBX PIN AS POSSIBLE. ALSO,
CONNECT ALL GROUNDS OF THESE
COMPONENTS TO THE LT8710 GROUND
8710 TA06a
Bulk and Float Output Voltage
with **Optional Components
Efficiency vs Input Voltage
95
16.0
VOUT = 12V
IOUT = 3A
15.5
90
15.0
14.5
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
220nF
316k
6.19k
SS
INTVCC
2.2µF
VC
SYNC
**OPTIONAL
MP2
BULK
14.0
FLOAT
13.5
85
80
13.0
12.5
12.0
–40
75
–20
0
20
40
TEMPERATURE (°C)
60
80
5
10
15
20
INPUT VOLTAGE (V)
25
30
8710 TA06c
8710 TA06b
42
8710f
For more information www.linear.com/LT8710
LT8710
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV J 1012
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
8710f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8710
43
LT8710
Typical Application
200kHz, Wide Input Range SEPIC Converter Generates a 5V Output with Up to 5A Output Current
MN
CIN1
10µF
×6
1.5m
BG
VIN
+
RSENSE1
+
L2
2.9µH
COUT1
100µF
×4
TG
ISP
ISN
LT8710
EN/FBIN
BIAS
10k
2.2µF
2.2µF
MODE
INTVEE
INTVCC
RT
Efficiency and Power Loss
45.3k
100
6.00
90
5.25
80
4.50
70
3.75
60
3.00
50
2.25
40
1.50
VC
IMON
100pF
SS
47nF
220nF
8.87k
6.8nF
8710 TA07a
L1, L2: WÜRTH 2.9µH WE-CFWI 74485540290
MN: FAIRCHILD FDMS86500L
MP: VISHAY SUD50P06-15
RSENSE1: 1.5mΩ 2010
RSENSE2: 6mΩ 2512
CIN1: 10µF, 50V, 1210, X7S
COUT1: 100µF, 6.3V, 1812, X5R
COUT2: OSCON 330µF, 16V, 16SEQP330M
C1: 10µF, 50V, 1210, X7S
VIN = 5V
VIN = 12V
30
20
0
1
2
3
LOAD CURRENT (A)
4
POWER LOSS (W)
FBX
FLAG
178k
SYNC
GND
COUT2
330µF
VOUT
5V
5A
•
CSN CSP
4.02k
CIN2
220µF
RSENSE2
6m
MP
EFFICIENCY (%)
•
VIN
3V TO 40V (OPERATING)
4.5V TO 40V (START-UP)
C1
10µF ×2
L1
2.9µH
0.75
5
0
8710 TA07b
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT3757A
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3758A
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3759
Boost, SEPIC and Inverting Controller
1.6V ≤ VIN ≤ 42V, 100kHz to 1MHz Programmable Operating Frequency,
MSOP-12E Package
LT3957A
Boost, Flyback, SEPIC and Inverting Converter
with 5A, 40V Switch
3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
5mm × 6mm QFN Package
LT3958
Boost, Flyback, SEPIC and Inverting Converter
with 3.3A, 84V Switch
5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
5mm × 6mm QFN Package
LT3959
Boost, SEPIC and Inverting Converter with 6A,
40V Switch
1.6V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
5mm × 6mm QFN Package
LTC3786
Low IQ Synchronous Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 55µA
Quiescent Current, 3mm × 3mm QFN-16, MSOP-16E
44 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT8710
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/8710
8710f
LT 0114 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2014
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