BD8162AEKV : Power Management

Datasheet
Power Supply IC Series for TFT-LCD Panels
Multi-channel
System Power Supply IC + Gamma Buffer
BD8162AEKV
General Description
The BD8162AEKV is a system power supply IC that
provides control 6 power supply channels and 4 gamma
output channels + VCOM required for TFT-LCD panels on
a single chip. All channels have built-in control input and
Power-Good output functions, enabling free sequence
control setting just by changing channels. In addition, the
BD8162AEKV is a user-friendly IC incorporating input
switch, short-circuit protection, and protection detection
output circuits.
Key Specifications



Power Supply Voltage 1 Range:
4.2V to 14V
Oscillating Frequency: 200kHz to 800kHz(Variable)
Operating Temperature Range:
-40°C to +105°C
Package
W(Typ) x D(Typ) x H(Max)
Features








Step-up DC/DC Converter with Built-in 3A FET
Step-down DC/DC Converter with Built-in 2A FET
Synchronous Rectification Step-down DC/DC
Converter with Built-in 2A FET
3ch LDO Regulator (500mA, 200mA, 20mA)
Positive/Negative Charge Pumps
4ch Gamma Buffer Amplifier + VCOM
Protection Circuits:
 Under-Voltage Lockout Protection Circuit
 Thermal Shutdown Circuit
 Timer Latch Type Short-Circuit Protection Circuit
Controllable Startup Sequence
HTQFP64V
12.00mm x 12.00mm x 1.00mm
Applications
LCD TV power supplies
○Product structure:Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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BD8162AEKV
Typical Application Circuit (1)
1. Application used to input VCC12V:
BD8162AEKV
Figure 1. Typical 12V Input Application Diagram
2. Startup Sequence
VCC input
VDD3
(Sync rectification)
VDD1
(Step-down)
VDD2
(LDO2)
AVCC
(Step-up)
VOL
(Negative charge pump)
LDO3
VOH
(Positive charge pump)
AMP+VCOM
3. Sequence Image Chart
VOH
AVCC
VCC(12V)
LDO3
VDD3
AMP
+
VCOM
VDD1
VDD2
VOL
Figure 2. Sequence Chart
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BD8162AEKV
Typical Application Circuit (2)
1. Application used to input 5V:
BD8162AEKV
Figure 3. Typical 5V Input Application Circuit Diagram
2. Startup Sequence
VCC input
VDD3
(Sync rectification)
VDD1
(LDO1)
VDD2
(LDO2)
AVCC
(Step-up)
VOL
(Negative charge pump)
LDO3
VOH
(Positive charge pump)
AMP+VCOM
3. Sequence Image Chart
VOH
AVCC
LDO3
VCC(5V)
VDD3
AMP
+
VCOM
VDD1
VDD2
VOL
Figure 4. Sequence Chart
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BD8162AEKV
SW1
PGATE
DTC1
COMP1
FB1
VREF
CTL1
FAULT
SCP
VCC
降圧
STEP-DOWN
コンバータ
CONVERTER
SW2
UVLO
VREF
FB2
COMP2
DTC2
PVCC2
BOOT2
Block Diagram
PG1
昇圧
STEP-UP
コンバータ
CONVERTER
PROTECT
PGND1
CTL2
PGND1
CPFB1
CPPG
PG2
REG
正チャージ
POSITIVE
CHARGE
ポンプ
PUMP
REG
HGND
C1
LDFB1
VCP1
LDCTL1
LDO 1
LDPG1
HVCC
PVCC2
VCP2
LDO1
NEGATIVE
負チャージ
CHARGE
PUMP
ポンプ
GND
OSC
RT
C2
HGND
CPCTL
LDFB2
CPFB2
LDO 2
HGND
LDO 3
LDO2
OUT1
LDVCC2
OUT2
SYNC RECTIFICATION
同期整流
STEP-DOWN
降圧コンバータ
CONVERTER
CTL3
OUT3
OUT4
SW3
HVCC
BOOT3
VCOM
IN-
IN4
IN+
IN3
IN2
IN1
LDO3
LDFB3
LDCTL3
PVCC3
COMP3
FB3
DTC3
PG3
PGND3
Pin Description
PIN
NO.
1
Pin
name
PGND3
Function
Ground pin
Power Good output
3 pin
2
PG3
3
DTC3
4
COMP3
5
FB3
6
PVCC3
7
LDFB3
8
LDCTL3
9
LDO3
Error amp output 3
pin
Feedback input 3
pin
Power supply input
pin
LDO
feedback
input 3 pin
LDO3 control input
pin
LDO output 3 pin
10
IN1
11
PIN
NO.
23
Pin
name
CPCTL
24
C2
25
VCP2
26
HVCC
27
VCP1
28
C1
29
CPPG
30
CPFB1
31
PGND1
AMP input 1 pin
32
PG1
IN2
AMP input 2 pin
33
SW1
12
IN3
AMP input 3 pin
34
PGATE
13
14
15
16
IN4
IN+
INVCOM
AMP input 4 pin
COM input + pin
COM input  pin
COM output pin
35
36
37
38
DTC1
COMP1
FB1
CTL1
17
OUT4
AMP output 4 pin
39
FAULT
18
OUT3
AMP output 3 pin
40
SCP
19
OUT2
AMP output 2 pin
41
UVLO
20
OUT1
AMP output 1 pin
42
VCC
21
HGND
Ground pin
43
VREF
22
CPFB2
Charge pump
feedback 2 pin
44
FB2
Duty limit pin 3 pin
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Function
CP control input pin
Charge pump output 2
pin
Charge pump LDO
output 2 pin
Power supply input pin
Charge pump LDO
output 1 pin
Charge pump output 1
pin
CP
Power
Good
output pin
Charge
pump
feedback 1 pin
Ground pin
Power Good output 1
pin
Switching output 1 pin
Pch gate drive output
pin
Duty limit pin 1 pin
Error amp output 1 pin
Feedback input 1 pin
Control input 1 pin
Protection
detection
output pin
Short-circuit protection
delay pin
Under-voltage lockout
protection setting pin
Power supply input pin
Reference
voltage
output pin
PIN
NO.
45
Pin
name
COMP2
Function
Error amp output 2 pin
46
DTC2
Duty limit pin 2 pin
47
PVCC2
Power supply input pin
48
BOOT2
Switch boot pin 2 pin
49
SW2
Switching output 2 pin
50
CTL2
Control input 2 pin
51
PG2
Power Good output 2
pin
52
REG
Boot LDO output pin
53
LDFB1
LDO feedback 1 pin
54
LDCTL1
LDO1 control input pin
55
LDPG1
LDO1 Power
output pin
56
LDO1
LDO output 1 pin
57
58
59
60
GND
RT
LDFB2
LDO2
Ground pin
Frequency setting pin
LDO feedback 2 pin
LDO output 2 pin
61
LDVCC2
Power supply input pin
62
CTL3
Control input 3 pin
63
SW3
Switching output 3 pin
64
BOOT3
Switch boot pin 3 pin
Good
Feedback input 2 pin
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BD8162AEKV
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage 1
VCC, VPVCC2, 3
15
V
Power Supply Voltage 2
VLDVCC2
7
V
Power Supply Voltage 3
VHVCC
20
V
SW1 Pin Voltage
VSW1
20
V
Tjmax
150
°C
Pd
5.20 (Note 1)
W
Operating Temperature Range
Topr
-40 to +105
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Maximum Junction Temperature
Power Dissipation
(Note 1) To use the IC at temperatures over Ta25°C, derate power rating by 41.6mW/°C.
When mounted on a four-layer glass epoxy board measuring 70 mm x 70 mm x 1.6 mm (with reverse side of copper foil measuring 70mm x 70 mm).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta-40°C to +105°C)
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage 1
VCC, VPVCC2, 3
4.2
14
V
Power Supply Voltage 2
VLDVCC2
-
5.5
V
Power Supply Voltage 3
VHVCC
6
18
V
SW1 Pin Voltage
VSW1
-
18
V
SW1 Pin Current
ISW1
-
3
A
SW2, 3 Pin Current
ISW2,3
-
2
A
Fault Detection Pull-up Voltage
VFAULT
-
5.5
V
Power Good Pull-up Voltage
VPG
-
5.5
V
Switching Frequency
fSW
200
800
kHz
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Electrical Characteristics (Unless otherwise noted, Ta25°C, VCC12V, VHVCC15V )
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Conditions
[DC/DC Converter Controller Block]
Step-up Feedback Voltage
VFB1
1.230
1.250
1.270
V
Step-down Feedback Voltage
VFB2
1.225
1.250
1.275
V
Sync Rectification Feedback Voltage
VFB3
0.882
0.900
0.918
V
Input Bias Current
IFB
-1.2
-0.1
+1.2
µA
COMP Source Current
ICSO
15
40
65
µA
COMP Sink Current
ICSI
-65
-40
-15
µA
MDT
85
92
99
%
DTC at 0% Duty
VDTCMIN
-
0.1
-
V
VFB=0V
DTC at Max Duty
VDTCMAX
-
0.9
-
V
VFB=0V
DTC Bias Current
IDTC
-1.2
-0.1
+1.2
µA
VDTC=0V
DTC Sink Current
IDTC
1
2
4
mA
SW1 On Resistance
RON1
-
0.2
-
Ω
SW1 Current Limit
ISW1OCP
3
-
-
A
SW2 High Level On Resistance
RON2H
-
0.2
-
Ω
ISW=1A
SW2 Low Level On Resistance
RON2L
-
2
-
Ω
ISW=20mA
SW3 High Level On Resistance
RON3H
-
0.2
-
Ω
ISW=1A
SW3 Low Level On Resistance
RON3L
-
0.2
-
Ω
ISW=1A
SW1, 2, 3 Leak Current
ISWLEAK
-5
0
+5
µA
PGATE Sink Current
IPGTSI
4
9
14
µA
VPG=5V
PGATE Source Current
IPGTSO
4
8
15
mA
VPG=5V
PG On Resistance
RONPG
0.5
1.0
1.5
kΩ
PG Leak Current
IPGLEAK
-5
0
+5
µA
PG1, 2, 3 On Voltage
PGH
-
90
-
%
PG1, 2, 3 Off Voltage
PGL
-
60
-
%
Feedback Voltage 1, 2 ,3
VLDFB123
1.231
1.250
1.269
V
Input Bias Current
ILDFB123
-1.2
-0.1
+1.2
µA
LDO1 Output Voltage Range 1
VLDO1
0
-
VPVCC2
V
LDO1 Output Voltage Range 2
VLDO2
0
-
VLDVCC2
V
LDO1 Output Voltage Range 3
VLDO3
0
-
VHVCC
V
I/O Voltage Difference 1
VDPLD1
0.3
0.75
1.6
V
VLDFB1=0V, IO=500mA
I/O Voltage Difference 2
VDPLD2
0.1
0.33
0.75
V
VLDFB2=0V, IO=200mA
I/O Voltage Difference 3
VDPLD3
0.14
0.3
0.65
V
VLDFB3=0V, IO=20mA
LDPG1 ON Voltage
LDPG1H
-
90
-
%
LDPG1 OFF Voltage
LDPG1L
-
60
-
%
SW1, 2, 3 Max Duty Ratio
VFB=1.5V
ISW=1A
[LDO1, 2, 3 Block]
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BD8162AEKV
Electrical Characteristics – continued (Unless otherwise noted, Ta25°C, VCC12V, VHVCC15V )
Limit
Parameter
Symbol
Unit
Min
Typ
Max
Conditions
[Charge Pump Block]
Positive/Negative Feedback Voltage
VCPFB12
1.225
1.250
1.275
V
Input Bias Current
ICPFB12
-1.2
-0.1
+1.2
µA
VCP I/O Voltage Difference
VDPCP12
0.28
0.7
1.55
V
C1, 2 High Level On Resistance
RONCH
-
3
-
Ω
C1, 2 Low Level On Resistance
RONCL
-
3
-
Ω
CPPG1 On Voltage
CPPGH
-
80
-
%
CPPG1 Off Voltage
CPPGL
-
60
-
%
Input Offset Voltage
VOFF
-15
0
+15
mV
Input Bias Current
IBAMP
-1.2
0
+1.2
µA
AMP Output Current Capability
IAMP
30
50
200
mA
VCOMP Output Current Capability
ICOM
60
150
400
mA
AMP Slew Rate
SRAMP
-
4
-
V/ µs
VCOM Slew Rate
SRCOM
-
4
-
V/ µs
Load Stability
ΔVo
-15
0
+15
mV
Max Output Voltage
VOH
-
V
IO=-1mA, VIN=VHVCC-0.8V
Min Output Voltage
VOL
-
0.1
0.16
V
IO=1mA, VIN=0V
Reference Output Voltage
VVREF
2.44
2.50
2.66
V
REG Output Voltage
VREG
4.7
5.0
5.3
V
Oscillating Frequency
fSW
450
550
650
kHz
UVLO Pin ON Voltage
VUVLOON
0.88
1.00
1.12
V
UVLO Pin OFF Voltage
IO=100mA
[Operation Amplifier Block]
VHVCC-1.0 VHVCC-0.8
IO=+1mA to -1mA
[Overall]
RRT=51kΩ
VUVLOOFF
0.93
1.05
1.17
V
VCC Under-Voltage Lockout Protection
ON/OFF Voltage
HVCC Under-Voltage Lockout
Protection ON/OFF Voltage
VCCUV
3.5
-
4.2
V
VHVUV
4.3
-
5.3
V
CTL ON Voltage
VCTLON
2
-
-
V
CTL OFF Voltage
VCTLOF
-
-
0.2
V
CTL Bias Current
ICTL
-20
-12.5
-5
µA
SCP Source Current
ISCPSO
2
5
8
µA
SCP Sink Current
ISCPSI
2
5
10
mA
SCP Threshold Voltage
VSCP
-
1.25
-
V
RONFLT
0.5
1
1.5
kΩ
ICC
-
5
11
mA
No Switching
IHICC
-
2.8
6
mA
No Switching
Fault Detection ON Resistance
Average Consumption Current 1
(VCC, PVCC2, 3)
Average Consumption Current 2 (HVCC)
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BD8162AEKV
Description of Operation of Each Block and Procedure for Selecting Application Components
VCC
(1) Step-up DC/DC Converter Block
CI1
M1
PGATE
CTL1
CTL
PGATE
D1
Control
PG1
SW1
Power
good
PWM
Power Good
VO
CO1
DRV
PGND1
-
ERR
DTC
+
1.25
FB1
R11
COMP1
DTC1
VREF (2.5V)
R13
R15
R14
C11
C12
R12
C13
R16
Figure 5. Step-up DC/DC Converter Block
This is a step-up DC/DC converter block that outputs a step-up voltage upon receipt of a signal from CTL1.
When the high-level signal is input to CTL1, a current will be pulled up from PGATE to turn ON input switch M1. At the
time of startup, since the switching duty is limited by the DTC1 pin voltage, a soft start is operated. When output
reaches 90% of the set voltage, the Power Good signal will be output from PG1.
(1.1) Selecting input switch M1
Input switch M1 will serve as a switch to block the path from VCC to output when a low-level control signal is input to
CTL1. Select the input switch with careful attention paid to the following conditions.
Recommended ICs: RSQ and RTQ Series
⊿IL
Maximum inductor current:
Power supply voltage:
Power supply voltage:
IINMAX +
VCC
VCC
2
< Rated current of FET
< Rated voltage of FET
< ON voltage of FET gate
When the CTL1 control input is switched to the high level, a 9µA (Typ) sink current will be pulled from the PGATE pin
to turn ON the input switch.
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BD8162AEKV
(1.2) Selecting the output L constant
The coil L to be used for output is determined by the rated current ILR and the maximum input current value IINMAX of
the coil.
Figure 6. Coil Current Waveform (Step-up DC/DC Converter)
Make adjustments so that IINMAX + ΔIL / 2 will not reach the rated current ILR. At this time, ΔIL is obtained by the
following equation.
1
V  VCC 1
ΔI L 
VCC  O

[ A]
L
VO
f
Where:
f = Switching frequency
In addition, since the coil L value may have variations in the range of approximately ±30%, set this value with
sufficient margin.
If the coil current exceeds the rated current ILR, the internal IC element may be damaged.
(1.3) Output capacitor setting
For capacitor C to be used for output, set it to the permissible value of the ripple voltage VPP or that of the drop
voltage at the time of a sudden load change, whichever is larger.
The output ripple voltage is obtained by the following equation.
1
V
ΔI L
ΔVPP  I LMAX  RESR 
 CC  ( I LMAX 
)
fCO
VO
2
Make this setting so that the voltage will fall within the permissible ripple voltage range.
For the drop voltage VDR during a sudden load change, estimate the VDR with the following equation.
ΔI
VDR 
 10 sec [V ]
CO
Wherein, 10 μsec is the estimate of DC/DC response speed.
Set CO so that these two values will fall within the limit values.
Since the DC/DC converter causes a peak current to flow between input and output, capacitors must also be
mounted on the input side. For this reason, it is recommended to use low-ESR capacitors above 10µF and below
100mΩ as the input capacitors. Using input capacitors outside of this range may superimpose excess ripple voltage
upon the input voltage, causing the IC to malfunction.
However, since the aforementioned conditions vary with load current, input voltage, output voltage, inductor value,
and switching frequency, be sure to verify the margin using the actual product.
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(1.4) Output rectifier diode setting
For the rectifier diodes to be used as the output stage of the DC/DC converter, it is recommended to use Schottky
diodes. Select diodes with careful attention paid to the maximum inductance current, maximum output voltage, and
power supply voltage.
Maximum inductance current:
Maximum output voltage:
IINMAX +
ΔIL
2
VOMAX
<
Rated current of diode
<
Rated voltage of diode
In addition, since each parameter has variations in current and voltage of 30% to 40%, design systems with sufficient
margin.
(1.5) Output voltage setting
Set output voltage using the following equation with feedback resistance composed of R11 and R12.
VO 
R11  R12
 1.25 [V ]
R12
Set the maximum output voltage to not more than 18V so that it will not exceed the rating of the SW1 pin.
It is recommended to apply a setting range of 10kΩ to 330kΩ. Setting the feedback resistance to not more than 10kΩ
will result in degraded voltage efficiency, while setting it to not less than 330kΩ will result in higher offset voltage due
to an input bias current of 0.1µA (Typ) of the internal error amplifier.
(1.6) Phase compensation setting
Phase setting procedure:
The following conditions are required to ensure the stability of the negative feedback system.
・When the gain is set to “1” (0 dB), the phase lag should not be more than 150° (i.e., phase margin should not be
less than 30°).
In addition, since DC/DC converter applications are sampled according to the switching frequency, the overall system
GBW should be set to not more than 1/10 of the switching frequency. The targeted characteristics of the applications
can be summarized as follows.
・When the gain is set to “1” (0 dB), the phase lag should not be more than 150° (i.e., phase margin should not be
less than 30°).
・The GBW at that time (i.e., frequency when the gain is set to “0 dB”) should not be more than 1/10 of the
switching frequency.
The responsiveness is determined by the GBW limitation. Consequently, to raise the responsiveness, higher
switching frequencies are required.
To ensure the stability through the phase compensation, it is necessary to cancel the secondary phase delay (-180°)
caused by LC resonance with the secondary phase lead (in other words, by adding two phase leads).
The GBW (i.e., frequency when the gain is set to “0 dB”) is determined by phase compensation capacitance
connected to the error amplifier. If GBW needs to be reduced, increase the capacitance of the capacitor.
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BD8162AEKV
( i ) Ordinary integrator (Low-pass filter)
( ii ) Open loop characteristics of integrator
(a)
A
+
Feedback
-20dB/decade
Gain
【dB】
COMP
GBW(b)
A
R
0
-
F
FB
0
C
-90°
Phase
-90
【°】
Phase margin
-180°
-180
F
Figure 7
Po i n at )( fa 
Figure 8
1
[ Hz]
2RCA
Po i n bt) ( fb  GBW 
1
2RC
[ Hz]
Since the phase compensation like that shown in (a) and (b) applies to the error amplifier, it will act as a low-pass
filter.
For DC/DC converter applications, R represents feedback resistors connected in parallel.
According to the LC resonance of the output, two phase leads should be added.
Vo
LC resonant frequency
R4
R1
C1
-
+
COMP
Phase lead
R3
Phase lead
A
R2
C2
fp 
1
2 LC
[ Hz]
1
[ Hz]
2C1R1
1
fz 2 
[ Hz]
2C 2 R3
fz1 
Figure 9
Set the lead frequency of one of the phases close to the LC resonant frequency for the purpose of canceling the LC
resonance.
Note: If high-frequency noise occurs in output, it will pass through capacitor C1 and affect the feedback. To avoid this problem, add resistor R4 of
approximately 1kΩ in series with capacitor C1.
(1.7) Duty cycle limit setting
Applying a voltage to the DTC pin makes it possible to fix the maximum duty cycle. Furthermore, since the upper limit
value of the maximum duty cycle is fixed within the IC, it will not increase beyond the upper limit value. Figure 10
shows the relationship between the DTC voltage and the maximum duty cycle. Refer to this figure to make the DTC
voltage setting. Subsequently, set R15 and R16 so that the DTC voltage will reach the level shown in the figure.
100
Duty[%]
80
60
40
20
0
0
0.2
0.4
0.6
0.8
1
DTC [V]
Figure 10. Characteristics of DTC Voltage vs Duty Cycle
Set the maximum duty cycle with sufficient margin so that it will not reach the maximum duty cycle for normal use.
For step-up converters, the range normally used is as follows.
VOMAX - VCCMIN
Max On duty cycle =
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(1.8) Soft-start time setting
Adding capacitor C13 to DTC resistive dividers R15 and R16 makes it possible to use the soft-start function. The
soft-start function is needed to prevent an excessive increase in coil current and output voltage overshoot at startup.
The capacitance and soft-start time are obtained by the following equation.
R15  R16
tss  C13 
 ln (1 
R15  R16
VO  VCC
 0.62  0.28
VO
) [sec]
R16
2.5 
R15  R16
(1.9) Control and Power Good functions
When the control pin (CTL) is set to low-level input, the relevant block will stop operation. The control pin voltage is
internally pulled up to the reference voltage VREF, whereby operating the relevant block in the open state.
The Power Good terminal (PG) is designed in an open-drain pattern to use as the control pin of a different block or an
external power-good signal. The PG pin outputs a low-level signal while in the rising mode and, when the output
voltage reaches 90% of the set voltage, will enter a high impedance state. At this time, the CTL pin at the destination
will be switched to high-level input by the use of a pull-up resistor. In contrast, when the output voltage falls below
60% of the set voltage, the CTL pin will switch to low-level output.
To use the PG pin output as an external signal, connect a pull-up resistor.
A pull-up resistance ranging from 51kΩ to 200kΩ is recommended.
Typical application:
Step-up DC/DC
Connect
LDO3
PG1
LDCTL3
90%
Step-up output
PG1
(LDCTL3)
LOW
Switched to HIGH by pull-up resistor
LDO3
Output
Figure 11.
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VCC
(2) Step-down DC/DC Converter Block and
Sync Rectification Step-down DC/DC Converter Block
CI2
PVCC2,3
CTL2,3
BOOT2,3
CTL
CTL
5V
Control
C24
PG2,3
L2
Power
good
PWM
Power Good
SW2,3
ERR
-
VO
DRV
D2
CO2
DTC
+
1.25/0.9V
FB2,3
VO
COMP2,3
DTC2,3
R23
R21
R25
C21
R24
C22
R22
Figure 12.
PGND1,3
VREF (2.5V)
C23
R26
Step-down DC/DC Converter Block and Sync Rectification Step-down DC/DC Converter Block
The step-down DC/DC converter block and the sync rectification step-down DC/DC converter block differ in the
feedback voltage and SW low-level On resistance, but have about the same configuration.
While the control signal remains at low level, the low-level SW turns ON to output a low voltage. When the control
signal is switched to a high level, output voltage will start rising with the soft start function in operation.
When the output voltage reaches 90% of the set voltage, the Power Good signal will be output.
(2.1) Selecting the output L constant
The inductance L to be used for output is determined by the rated current ILR and the maximum output current value
IOMAX of the inductor.
IOMAX+ΔIL should not
IL
2
reach the rated value level.
ILR
IOMAX
mean current
t
Figure 13. Coil Current Waveform (Step-down DC/DC Converter)
Make adjustments so that IOMAX + ΔIL / 2 will not reach the rated current ILR. At this time, ΔIL is obtained by the
following equation.
1
V
1
 (VCC  VO )  O 
[ A]
L
VCC f
In addition, since the inductance L value may have variations in the range of approximately ±30%, set this value with
sufficient margin.
If the coil current exceeds the rated current ILR, the internal IC element may be damaged.
ΔI L 
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(2.2) Selecting I/O capacitors
To select I/O capacitors, refer to information in Section (1.3).
However, the output ripple voltage of the step-down DC/DC converter is obtained by the following equation.
ΔVPP  ΔI L  RESR 
ΔI L VO 1


2CO VCC f
[V ]
(2.3) Output rectifier diode setting
For the rectifier diodes to be used as the output stage of the DC/DC converter, it is recommended to use Schottky
diodes. Select diodes with careful attention paid to the maximum inductance current, maximum output voltage, and
power supply voltage.
Maximum inductance current:
IOMAX +
Power supply voltage:
VCC
ΔIL
2
<
Rated current of diode
<
Rated voltage of diode
In addition, since each parameter has variations in current and voltage of 30% to 40%, design systems with sufficient
margin.
(2.4) Output voltage setting
Set output voltage using the following equation with feedback resistance composed of R21 and R22.
VO 
R21  R22
 VFB [V ]
R22
Where:
VFB: Set to 1.25 for the step-down DC/DC converter (FB2) and 0.9 for the sync rectification step-down DC/DC
converter (FB3).
It is recommended to apply a setting range of 10kΩ to 330kΩ. Setting the feedback resistance to not more than 10kΩ
will result in degraded voltage efficiency, while setting it to not less than 330kΩ will result in higher offset voltage due
to an input bias current of 0.1µA (Typ) of the internal error amplifier.
(2.5) Phase compensation setting
For details of phase compensation setting, refer to information in Section (1.6).
(2.6) Duty cycle limit setting
For details of duty cycle limit setting, refer to information in Section (1.7).
For step-down converters, however, the range normally used comes to the following:
VOMAX
Max On duty cycle =
VCCMIN
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(2.7) Soft start time setting
Adding the capacitor C23 to the DTC resistive dividers R25 and R26 makes it possible to use the soft start function.
The soft start function is needed to prevent an excessive increase in coil current at startup and output voltage
overshoot at startup. The capacitance and soft start time are obtained by the following equation:
VO
 0.62  0.28
R 25  R 26
VCC
tss  C 23 
 ln (1 
) [sec]
R 26
R 25  R 26
2.5 
R 25  R 26
(2.8) Control and Power Good functions
For details of the control and Power Good functions, refer to information in Section (1.9).
(3) LDO1 to LDO3 blocks
VCC
LDCTL1
VDD
CI2
CI4
CTL
Control
PVCC2
LDPG1
Power Good
LDVCC2
Power
good
VO
LDO1
ERR
ERR
Co4
+
VO
LDO2
Co5
+
R41
-
R51
-
1.25V
1.25V
R42
LDFB1
R52
LDFB2
Figure 14. LDO1 Block
Figure 15. LDO2 Block
HVCC
CI5
LDCTL3
HVCC
CTL
Control
VO
LDO3
ERR
+
Co6
R61
-
1.25V
R62
LDFB1
Figure 16. LDO3 Block
(3.1) Selecting I/O capacitors
The LDO1 to LDO3 blocks are ceramic capacitor compatible.
Capacitance in the range of 1µF to 100µF is recommended.
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(3.2) Output voltage setting
Set output voltage using the following equation with feedback resistance composed of R1 and R2.
VO 
R 1  R  2
 1.25 [V ]
R2
:4 to 6
It is recommended to apply a setting range of 10kΩ to 330kΩ. Setting the feedback resistance to not more than 10kΩ
will result in degraded voltage efficiency, while setting it to not less than 330kΩ will result in higher offset voltage due
to an input bias current of 0.1µA (Typ) of the internal error amplifier.
The following table shows the output voltage setting ranges and current capabilities.
Minimum
setting
LDO1
1.5V
LDO2
1.5V
LDO3
1.5V
Maximum setting
(with maximum output current)
VCC (Max 14V)
-1.6V
LDVCC2 (Max 5.5V)
-0.75V
Output current
capability
Up to 500mA
Up to 200mA
HVCC (Max 18V)
-0.65V
Up to 20mA
(3.3) Control and Power Good functions
For details of the control and Power Good functions, refer to information in Section (1.9).
For the LDO3 block, however, set output voltage so that the signal will be input into the control pin after HVCC, which
serves as a power source, starts up.
(4) Charge Pump Block
CPFB1
CIN7
HVCC
C71
C72
CPCTL
CTL
VCP1
Control
1.25V
CPPG
D71
D72
D73
C74
C73
Power
Good
D74
VoH
C75
R71
C1
Power Good
R72
C81
HVCC
VREF
VCP2
C82
1.25V
C2
D81
D82
R81
R82
VoL
C83
CPFB2
HGND
Figure 17. Charge Pump Block
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When the charge pimp block receives the control input signal, the negative-side charge pump will start operation. The
startup sequences are internally fixed. Consequently, when the negative-side charge pump reaches 80% of the set
voltage, the positive-side charge pump will start operation. When both negative- and positive-side charge pumps
reach 80% of the set voltage, the power-good signal will be output from the CPPG pin.
(4.1) Selecting output diodes
For diodes D71 to D74, and D81 and D82, select Schottky diodes having a current capability three times (positive
side) or two times (negative side) as high as the maximum output current and a withstand voltage higher than the
output voltage.
Due to the aforementioned requirements, it is recommended to use the RB550EA dual Schottky barrier diode.
(4.2) Selecting output capacitors
Capacitors C73 and C81 serve as output capacitors for the charge pump regulators; a capacitance in the range of
1μF to 10μF is recommended. Capacitors C71, C72, and C82 serve as flying capacitors; a capacitance in the range
of 0.1μF to 1μF is recommended. Capacitors C74, C75, and C83 serve as charge pump output capacitors; a
capacitance in the range of 0.1μF to 10μF is recommended.
(4.3) Output voltage setting
Set output voltage using the following equation with feedback resistance.
VO H 
R71  R72
 1.25 [V ]
R72
VO L  VREF 
 2.5 
R81  R82
R81
VREF  1.25
R81  R82
 1.25 [V ]
R81
It is recommended to apply a setting range of 10kΩ to 330kΩ. Setting the feedback resistance to not more than 10kΩ
will result in degraded voltage efficiency, while setting it to not less than 330kΩ will result in higher offset voltage due
to an input bias current of 0.1µA (Typ) of the internal error amplifier.
(4.4) Control and Power Good functions
Make the sequence setting by inputting the power-good signal output from a different block. However, make this
setting so that the signal will be input into the CPCTL control pin after HVCC, which serves as a power source, starts
up. For example, to generate HVCC in the step-up DC/DC converter block, do not set the sequence so that the same
Power Good pin is connected to CTL1 and CPCTL. Since the sequences of the negative- and positive-side charge
pumps are internally fixed, the sequence of the negative-side pump starts up first and is followed by that of the
positive-side pump. When both negative- and positive-side charge pumps reach 80% of the set voltage, the
power-good signal will be output from the CPPG pin. The power-good signal output pattern is the same as that of
different blocks. For details, refer to information in Section (1.9).
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(5) Common Amplifier + 4ch Buffer Amplifier
The AMP and VCOM amplifiers operate in the range of 0.1V to HVCC0.8V (Typ). Normally, use the VCOM amplifier
as a buffer type amplifier as shown in (a). Use the output voltage of the LDO3 block for power supply on the reference
side.
To increase the current drive capability, use the PNP and NPN transistors as shown in (b).
When the VCOM amplifier is not used, set the block to the buffer type as shown in (a) and ground the V+ pin. In this
case, it is recommended to set the R3 and R4 resistors in the range of 10kΩ to 100kΩ. Setting them to not more than
10kΩ may increase current consumption, thus resulting in degraded power efficiency. Setting them to not less than
100kΩ may result in higher offset voltage due to the input bias current of 0.1µA (Typ).
LDO3
(a)
(b)
LDO3
RCOM1
V+
+
IN+
+
VCOM
VCOM
-
IN-
-
V-
30kΩ
RCOM1
30kΩ
RCOM2
-
RCOM2
VCOM
1000pF
Vo1
VCOM
RCOM3
1kΩ
Figure 18 VCOM Block
VCOM 
RCOM 2
 LDO3 [V ]
RCOM 1  RCOM 2
Resistance of approximately 1kΩ is recommended for RCOM3.
(6) Common Block
(6.1) UVLO function
VCC
RU1
UVLO
RU2
1.0V
Figure 19. UVLO Block
Set the UVLO voltage with RU1 and RU2. The UVLO protection function will be implemented when the UVLO pin
voltage falls below 1.0V (Typ) and canceled when it exceeds 1.05V (Typ). The VCC voltage at which the UVLO
function is activated is expressed by the following equation.
VUVLO 
RU 1  RU 2
[V ]
RU 2
It is recommended to set resistance in the range of 10kΩ to 200kΩ.
In addition, the VCC pin incorporates a fixed UVLO function. Consequently, when the UVLO pin voltage falls below
3.8V (Typ), the UVLO protection function will be operated even if the external UVLO voltage is set below 3.8V (Typ).
(6.2) SCP function
5µA
SCP
Latch
CSCP
1.25V
Figure 20. SCP Block
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The SCP function protects against short-circuits in the outputs of the step-up DC/DC converter, step-down DC/DC
converter, sync rectification step-down DC/DC converter, LDO1, and charge pump blocks. When any one of these
outputs falls below 60% of the set voltage, it will be regarded as a short-circuit in output, thus activating the
short-circuit protection function.
If a short-circuit is detected, source current of 5µA (Typ) will be output from the SCP pin. Then, delay time will be set
with external capacitance. When the SCP pin voltage exceeds 1.25V (Typ), the state will be latched to shut down all
outputs. Once the state has been latched, it will not be canceled unless VCC restarts. The delay time setting is
obtained by using the following equation.
TL [s]  (CSCP  1.25) /(5  106 )
Even if none of the output startup sequences is complete at startup of the IC, short-circuits will be detected and the
SCP function activated. For this reason, set the delay time substantially longer than the startup time.
(6.3) Fault detection function
This IC has the built-in fault detection function that alerts the operating status of protection circuits.
If any of the protection circuits turns ON, the FAULT pin will be pulled up to output low voltage.
In stable operating status, the pin outputs high voltage. In this case, resistance ranging from 10kΩ to 220kΩ is
recommended. Setting resistance to not more than 10kΩ may generate offset voltage due to the internal On
resistance, thus disabling proper output of low voltage. In contrast, setting it to not less than 220kΩ may not output
proper high-level voltage due to leak current.
The FAULT pin is switched to low voltage output under any of the following conditions.
・ When the UVLO (under-voltage protection) function is activated;
・ When the TSD (thermal shutdown circuit) function is activated;
・ When the OCP (overcurrent protection circuit) function is activated, or;
・ When the SCP (short-circuit protection) function is activated.
(6.4) Variable oscillator
Changing the timing resistance RT enables switching frequency adjustment. Set resistance referring to Figure 21. Set
frequency in the range of 200kHz to 800kHz.
Frequency [khZ]
Frequency [khZ]
1000
100
10
100
1000
RT [kΩ]
Figure 21. RT vs Switching Frequency
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I/O Equivalent Circuits
2.PG3
3.DTC3
VPVCC3
5.FB3 22.CPFB2
44.FB2 53.LDFB1
VVREF
8.LDCTL3
23.CPCTL
VHVCC
10.IN1
13.IN4
VHVCC
27.VCP1
VHVCC
11.IN2 12.IN3
14.IN+ 15.IN-
51.PG2 55.LDPG1
VHVCC
30.CPFB1
VHVCC
VHVCC
33.SW1
34.PGATE
VCC
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VVREF
16.VCOM 17.OUT4 18.OUT3
19.OUT2 20.OUT1 24.C2
28.C1
VHVCC
29.CPPG
VHVCC
32.PG1
7.LDFB3
59.LDFB2
9.LDO3
25.VCP2
36.COMP1
45.COMP2
VPVCC3
4.COMP3
40.SCP
VVREF
VCC
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I/O Equivalent Circuits - Continued
35.DTC1
46.DTC2
37.FB1
VCC
VVREF
39.FAULT
41.UVLO
64.BOOT3
50.CTL2
54.LDCTL1
VVREF
43.VREF
VCC
48.BOOT2
38.CTL1
62.CTL3
VCC
VVREF
49.SW2 63.SW3
VCC
52.REG
VPVCC2
VREG
56.LDO1
58.RT
VPVCC2
VPVCC2
60.LDO2
VCC
61.LDVCC2
VCC
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may
result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the
board size and copper area to prevent exceeding the maximum junction temperature rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 22. Example of monolithic IC structure
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
15. Discontinuous mode
The step-up and step-down DC/DC converters used in this IC have been designed on the assumption that the converters
are used in continuous mode. Using the IC constantly while in discontinuous mode may result in malfunctions. To avoid this
problem, make coil adjustments or insert a resistor between output and GND to prevent the IC from entering discontinuous
mode while in use.
16. PCB layout for open-drain pin (SW1) of step-up DC/DC converter
Connect the open-drain pin of the FET built in the step-up DC/DC converter to the coil / diode with as thick and short of a
line as possible. Particularly, making the line distance between the open-drain pin and the external diode longer or routing it
with the use of a through-hole may form parasitic impedance due to patterns and cause the open-drain pin to generate a
high surge voltage, thus leading to IC destruction. For this reason, ensure that the open-drain pin voltage (direct mounting
to IC pin) will never exceed the absolute maximum ratings in practical applications of this IC.
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© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
23/26
TSZ02201-0323AAF00690-1-2
15.Feb.2016 Rev.001
BD8162AEKV
Ordering Information
B
D
8
1
6
2
Part number
A
E
K
V
Package
EKV:HTQFP64V
Packaging and forming specification
None: Tray
Marking Diagram
HTQFP64V (TOP VIEW)
Part Number Marking
BD8162EKV
A
LOT Number
1PIN MARK
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© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
24/26
TSZ02201-0323AAF00690-1-2
15.Feb.2016 Rev.001
BD8162AEKV
Physical Dimension, Tape and Reel Information
Package Name
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
HTQFP64V
25/26
TSZ02201-0323AAF00690-1-2
15.Feb.2016 Rev.001
BD8162AEKV
Revision History
Date
Revision
15.Feb.2016
001
Changes
New Release
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© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
26/26
TSZ02201-0323AAF00690-1-2
15.Feb.2016 Rev.001
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
BD8162AEKV - Web Page
Part Number
Package
Unit Quantity
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
BD8162AEKV
HTQFP64V
1000
1000
Tray
inquiry
Yes
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