Implementation of Ethernet Interface based on

IJECT Vol. 2, SP-1, Dec. 2011
ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)
Implementation of Ethernet Interface based on
Embedded Systems
1
Kota. Srinivas, 2M.Srinivasa Rao, 3Ch. Madhava Rao, 4N. Sarath Babu, 5Shaffyvullah Mohd.
1,2,3,4,5
Dept. of ECE, Sir C.R.R. College of Engineering, Eluru, India
Abstract
Embedded systems are pervasive in the infrastructure of
our society for diverse tasks such as studying environmental
phenomena, mapping and managing large-scale systems,
aiding security and other fields, but masses of them do not have
the capacity of network interconnection, these greatly limits
the use of equipment, control and data exchange performance,
therefore we proposed an method of embedded system interface
based on Ethernet which combined with the latest computer
technology, network technology, communication technology.
We introduce the Ethernet technology and embedded system
theory, using Ethernet controller CS8900A and S3C2410_net
to design the Ethernet interface module, while given the system
flow chart. The system interface will widely use in various
applications and has good prospects.
based on Ethernet, we use Ethernet controller CS8900A and
S3C2410_net to design the Ethernet interface module, while
given the system flow chart. The system interface will widely
use in various applications and has good prospects
II. Hardware Design of Ethernetnetwork Interface
Module
The Ethernet network interface module mainly composed by
three parts as shown in Fig.2: Cirrus Logic company’s Cirrus
Logic, Samsung company’s S3C2410_NET, RJ45
Keywords
Embedded system; Ethernet; network interface; ARM;
I. Introduction
Embedded systems are pervasive in the infrastructure of
our society for diverse tasks such as studying environmental
phenomena, mapping and managing large-scale systems, aiding
security and other fields [1]. And market demands for innovative,
high quality products, aggressive competition at a global scale,
increasing productivity through highly optimized production
processes, and environmental/societal pressures are some
of the challenges faced by the manufacturing industry today
[2]. Rapid changes in process technology demand production
systems that are themselves easily upgradeable, and into which
new technologies and new functions can be readily integrated
[3]. While Ethernet is the most widely used LAN technology,
it can conveniently set up Ethernet LAN and access to the
Internet [4]. With the development of embedded operating
systems and platforms, embedded controllers, smart field
instrumentation and sensors can be easily access to Ethernet
control network. Using technology for embedded systems, it
enables Ethernet communication directly to the scene device
level. The Ethernet access to embedded systems usually have
two kinds of method: First, using the embedded processor of
integrated Ethernet interface; second, embedded processor
is used with Ethernet controller chip [5].the former requires
embedded processor has general network interface, usually
it was designed for network application and embed the curing
network protocol in internal, processor and network rapidly
exchange data through the internal bus, but the curing network
protocol in internal can easily use in different occasions, but
it easily generate unnecessary waste and the cost is relatively
high. The later, has not special requirements and only connect
the Ethernet control chip to the processor bus, but processors
and network exchange data through the external bus (usually a
parallel bus),it will slow network speed and the reliability is not
high [6]. In this paper, we analysis the embedded system theory
and Ethernet technology and combine with the latest computer
technology, network technology, communication technology,
then proposed an method of embedded system interface
70 International Journal of Electronics & Communication Technology
Fig. 1: Network interface module block diagram
A. Ethernet interface controller
Ethernet interface controller includes two parts of MAC and
PHY, MAC layer controller as a logic control easily integrated in
the processor itself, the embedded processors in many network
control applications integrated MAC layer controller, in MAC
controller architecture which integrated in ARM-chip, ARM core
access register interface through the advanced peripheral\
bus (APB), and MAC controller can exchange data with the
memory through DMA channel [7]. MAC controller connects to
PHY through the media independent interface (MII), reduced
MII (RMII) interface. In the IEEE802 protocol standards, data
link layer includes logical two sub-layer of link control (LLC) and
medium access control (MAC), MAC layer responsible for the
completion of one MAC data frame packaging, closing, sending
and receiving functions. The structure of physical layer PHY has
a certain level of difference with the different transfer rate. MII
is the interfaces of data link layer and physical layer. According
to the agreement, the functions of MII interface are: clock
synchronization for reading /writing data and frame delimiter,
independent read / write data channel, providing corresponding
management signals and supporting full-duplex mode for MAC
layer and PHY layer. The embedded processor which has not
integrated MAC controller, a more common method is to use
the Ethernet controller, they usually need the Host Bus Interface
Ethernet controller in the embedded systems and CS8900 is
one of the most commonly used.
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ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)
B. CS8900A Function and Working Principle
CS8900A is a superior performance 16-bit low power
consumption Ethernet controller which produced by Cirrus
Logic. Its internal structure block diagram is shown in Fig.
2 [8]. The major function module is 802.3 MAC. It supports
full duplex operation,, it is responsible for handling Ethernet
data frames to send and receive according to the IEEE 802.
3 Ethernet standards (ISO / IEC 8802-3, 1993), including:
conflict detection, header generation and detection, CRC
check sum generation and verification. MAC can automatically
complete the post-conflict frame retransmission through
initializing the control register (TxCMD), if the frame’s
data is less than 46 bytes, it can generate field data to
fill the data frame to reach the shortest length required
Fig. 2 : The internal structire block diafgram CS8900A
CS8900A is a full-duplex 10Mb / s Ethernet controller produced,
but also for designed for the ISA bus interface Ethernet
controller. Its characteristics are: 16-bit bus width, procedures
supported under Linux, the two kinds of access pattern are I/O
and memory, 3.3V interface-level, and easy directly connect to
most embedded processors [5]. When the CS8900A receiving
data packet which sent by S3C2410_NET, listening network
lines, if the line is busy, they waiting, or immediately sends
the data frame. In sending, first to add Ethernet header, and
then generate CRC checksum, last, the data frame is sent to
the Ethernet. In receiving, it decoding the data frame which
received from the Ethernet, removing the frame head and
address, then store the data in buffers, when the checksum in
the CRC is passed, according to the initialization configuration,
it will inform S3C2410_NET have received data frame, and then
S3C2410_NET will use I / O transfer mode to store the data
in S3C2410_NET storage. C. S3C2410 Processor S3C2410
is a 16/32 bit RISC embedded microprocessor based on
ARM9200T kernel which produced by Samsung Company.
ATM920T kernel is composed of ATM920TDMI, MMU and
cache, MMU can manage virtual memory, cache is composed
of independent 16KB address and 16KB data cache. ATM920T
have two coprocessors: CPI4 and CPI5.
IJECT Vol. 2, SP-1, Dec. 2011
In the design of network communication, we should handle
Ethernet frame accepting and Ethernet frame transmitting,
According to the received packet type, choose a different
approach; the length of frame can not exceed the IEEE802. 3
standards (1 514 bytes) in accepting, when transmit Ethernet
frame, we should add 14 bit Ethernet header logo on the
transmission data, namely, increase the packet length [10,11].
The typical Ethernet frame are shown in table 1 [5]. Network
interface communication is completed by CS8900A, so it is
necessary to program sending and receiving data function
for CS8900A.
A. Driver design of Ethernet chip CS8900A
The I/O mode of CS8900A have method: disruption and inquiry,
in his paper, we use disruption to deal with data sending and
receiving of CS8900A, the system first initialize to determine
its operating mode. In the exchange data process of host and
network, it needs successively read and write internal registers.
In I/O mode, S3C2410_NET use CS8900A-CQ3 extend the
Ethernet communication module AND can operate registers to
achieve read and write all registers in CS8900A. Because the
CPU chip select line of nGCS3 has been used by CS8900, so
the CS8900 register address space is 0X6000000+300H.The
network driver interface flow chart was shown in Fig.3.
LINECTL (0112H): it decides the basic configuration and
physical interface of CS8900A .The initial value is 00D3H,
the physical interface is 10Base-T. RXCTL (0104H): it can
control CS8900A to receive specific data, the initial value is
0D05H, it can receive broadcasting on the network or the right
data packet which the destination addresses is same with
physical address. RXCFG (0102H): it controls CS8900A to
receive specific data and trigger the interruption, it can be set to
0103H.when CS8900 receives a data will engender a receiver
interruption. BUSCT (0116H): it controls the operation of I / O
interface, the initial value is 8017H, and open the disruption
control bit of CS8900A. ISQ (0120H): it is CS8900A's interrupt
status register, it internal mapping the contents of receiving
interrupt status register and sending interrupt status register.
PORT0 (0000H): when sending and receiving data, S3C2410_
NET transmits data through PORT0
TXCMD (0004H): it is a sending control register, if rite data
00C0H, then the network card will send data after writing all
data. TXLENG (0006H): it is a sending data length register,
when sending data, first write the length, then write data to
the chip through PORT0.
III. Ethernet Frame Reception and Transmission
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International Journal of Electronics & Communication Technology 71
IJECT Vol. 2, SP-1, Dec. 2011
ISSN : 2230-7109(Online) | ISSN : 2230-9543(Print)
IV. Conclusions
In this paper, we analysis the embedded system theory and
Ethernet technology and combine with the latest computer
technology, network technology, communication technology,
then proposed an method of embedded system interface
based on Ethernet, we use Ethernet controller CS8900A and
S3C2410_net to design the Ethernet interface module, while
given the system flow chart. The system interface will widely
use in various applications and has good prospects
Fig. 3 : The network driver interface flowchart
B. Algorithm description
We first initialize the network card in system working; namely,
write the register of LINECTL, RXCTL, and RCCFG AND BUSCT
[7]. When sending data, we should write register TXCMD,
and write the data length to TXLENG, then write the data
to PORT0 in turn, such as write the first byte to 300H, write
the second byte to 301H, third byte to 300H and followed by
analogy. Network card chip will organize the data to link layer
type and add the fill-bit and CRC checksum to the network. At
the same time, CPU query ISO data, when have data arrive,
read the receiving data, CPU read the 300H,301H,300H,301H
in turn. The follow respectively gives the algorithm .
72 International Journal of Electronics & Communication Technology
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