Express-SL/SLE
User’s Manual
Manual Revision:
0.10
Revision Date:
December 8, 2015
Part Number:
50-1J064-1000
Revision History
Revision
Description
Date
By
0.10
Preliminary release
2015-12-08
JC
Page 2
Express-SL/SLE
Preface
Copyright 2015 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
Express-SL/SLE
Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1.
Introduction.............................................................................................. 8
2.
Specifications............................................................................................ 9
2.1.
Core System .....................................................................................................................9
2.2.
Expansion Busses .............................................................................................................9
2.3.
Video ............................................................................................................................. 10
2.4.
Audio............................................................................................................................. 10
2.5.
LAN................................................................................................................................ 10
2.6.
Multi I/O and Storage ................................................................................................... 10
2.7.
Serial I/O on Module..................................................................................................... 11
2.8.
Trusted Platform Module (TPM)................................................................................... 11
2.9.
SEMA Board Controller ................................................................................................. 11
2.10.
Debug Headers.............................................................................................................. 11
2.11.
Power Specifications..................................................................................................... 12
2.12.
Power Consumption ..................................................................................................... 12
2.13.
Operating Temperatures .............................................................................................. 12
2.14.
Environmental............................................................................................................... 12
2.15.
Specification Compliance.............................................................................................. 12
2.16.
Operating Systems ........................................................................................................ 12
2.17.
Functional Diagram....................................................................................................... 13
2.18.
Mechanical Dimensions ................................................................................................ 14
3.
Page 4
Pinouts and Signal Descriptions........................................................... 15
3.1.
AB/CD Pin Definitions ................................................................................................... 15
3.2.
Signal Description Terminology .................................................................................... 18
3.3.
AB Signal Descriptions .................................................................................................. 19
3.3.1.
Audio Signals ...............................................................................................................................19
3.3.2.
Analog VGA .................................................................................................................................19
3.3.3.
LVDS ............................................................................................................................................20
3.3.4.
eDP ..............................................................................................................................................20
3.3.5.
Gigabit Ethernet ..........................................................................................................................21
3.3.6.
SATA ............................................................................................................................................21
3.3.7.
PCI Express ..................................................................................................................................22
3.3.8.
Express Card ................................................................................................................................22
Express-SL/SLE
3.3.9.
LPC Bus ........................................................................................................................................23
3.3.10.
USB ..............................................................................................................................................23
3.3.11.
USB Root Segmentation ..............................................................................................................24
3.3.12.
SPI (BIOS only) .............................................................................................................................24
3.3.13.
Miscellaneous..............................................................................................................................25
3.3.14.
SMBus..........................................................................................................................................25
3.3.15.
I2C Bus.........................................................................................................................................25
3.3.16.
General Purpose I/O (GPIO) ........................................................................................................26
3.3.17.
Serial Interface Signals ................................................................................................................26
3.3.18.
Power and System Management ................................................................................................26
3.3.19.
Power and Ground ......................................................................................................................27
3.4.
CD Signal Descriptions .................................................................................................. 28
3.4.1.
USB 3.0 Extension .......................................................................................................................28
3.4.2.
PCI Express x1..............................................................................................................................28
3.4.3.
DDI Channels ...............................................................................................................................29
3.4.4.
DDI to DP/HDMI Mapping...........................................................................................................31
3.4.5.
PCI Express Graphics x16 (PEG)...................................................................................................32
3.4.6.
Module Type Definition ..............................................................................................................33
3.4.7.
Power and Ground ......................................................................................................................33
4.
Module Interfaces and Configuration ................................................. 34
4.1.
4.1.1.
Connector, Switch and LED Locations........................................................................... 34
Express-SL/SLE and the DB40 Module connected.......................................................................34
4.2.
40-pin Multipurpose Connector ................................................................................... 35
4.3.
Status LEDs.................................................................................................................... 36
4.4.
Fan Connector............................................................................................................... 37
4.5.
BIOS Setup Defaults Reset Button ................................................................................ 38
4.6.
Express-SL/SLE Switch Settings ..................................................................................... 39
4.6.1.
Switch Locations..........................................................................................................................39
4.6.2.
SW1: PCI Express Configuration Switch. .....................................................................................40
4.6.3.
SW2: BIOS Select and Mode Configuration Switch .....................................................................40
4.7.
5.
PCIe x16-to-two-x8 Adapter Card ................................................................................. 41
Smart Embedded Management Agent (SEMA) .................................. 42
5.1.
Board Specific SEMA Functions .................................................................................... 43
5.1.1.
Voltages.......................................................................................................................................43
5.1.2.
Main Current ...............................................................................................................................43
5.1.3.
BMC Status ..................................................................................................................................43
5.1.4.
Exception Codes ..........................................................................................................................44
5.1.5.
BMC Flags....................................................................................................................................44
Express-SL/SLE
Page 5
6.
System Resources................................................................................... 45
6.1.
System Memory Map.................................................................................................... 45
6.2.
Direct Memory Access Channels .................................................................................. 45
6.3.
I/O Map......................................................................................................................... 46
6.4.
Interrupt Request (IRQ) Lines ....................................................................................... 47
6.4.1.
PIC Mode .....................................................................................................................................47
6.4.2.
APIC Mode...................................................................................................................................48
6.5.
PCI Configuration Space Map ....................................................................................... 49
6.6.
PCI Interrupt Routing Map............................................................................................ 50
6.7.
SMBus Address Table.................................................................................................... 50
7.
BIOS Setup .............................................................................................. 51
7.1.
Menu Structure............................................................................................................. 51
7.2.
Main .............................................................................................................................. 52
7.2.1.
System Information.....................................................................................................................52
7.2.2.
Processor Information.................................................................................................................52
7.2.3.
PCH Information..........................................................................................................................52
7.2.4.
System Management ..................................................................................................................53
7.2.5.
System Date and Time.................................................................................................................56
7.3.
7.3.1.
CPU..............................................................................................................................................57
7.3.2.
Memory.......................................................................................................................................59
7.3.3.
Graphics ......................................................................................................................................60
7.3.4.
SATA ............................................................................................................................................61
7.3.5.
USB ..............................................................................................................................................63
7.3.6.
Network.......................................................................................................................................64
7.3.7.
PCI and PCIe ................................................................................................................................65
7.3.8.
Super IO.......................................................................................................................................69
7.3.9.
ACPI and Power Management ....................................................................................................70
7.3.10.
Sound ..........................................................................................................................................70
7.3.11.
Serial Port Console ......................................................................................................................70
7.3.12.
Thermal .......................................................................................................................................72
7.3.13.
Miscellaneous..............................................................................................................................73
7.4.
7.4.1.
7.5.
7.5.1.
7.6.
7.6.1.
Page 6
Advanced ...................................................................................................................... 57
Boot............................................................................................................................... 74
Boot Configuration......................................................................................................................74
Security ......................................................................................................................... 75
Password Description..................................................................................................................75
Save & Exit .................................................................................................................... 75
Reset Options ..............................................................................................................................75
Express-SL/SLE
7.6.2.
8.
Save Options ...............................................................................................................................75
BIOS Checkpoints, Beep Codes............................................................. 76
8.1.
Status Code Ranges....................................................................................................... 77
8.2.
Standard Status Codes .................................................................................................. 77
8.2.1.
SEC Status Codes .........................................................................................................................77
8.2.2.
SEC Beep Codes...........................................................................................................................78
8.2.3.
PEI Status Codes ..........................................................................................................................78
8.2.4.
PEI Beep Codes............................................................................................................................80
8.2.5.
DXE Status Codes ........................................................................................................................80
8.2.6.
DXE Beep Codes ..........................................................................................................................83
8.2.7.
ACPI/ASL Checkpoint...................................................................................................................83
8.3.
OEM-Reserved Checkpoint Ranges............................................................................... 83
Mechanical Information ........................................................................ 84
9.
9.1.
Board-to-Board Connectors.......................................................................................... 84
9.2.
Thermal Solution (for reference only) .......................................................................... 85
9.2.1.
Heat Spreaders............................................................................................................................85
9.2.2.
Heat Sinks....................................................................................................................................85
9.2.3.
Installation...................................................................................................................................85
9.3.
Mounting Methods ....................................................................................................... 89
9.4.
Standoff Types .............................................................................................................. 90
Safety Instructions ...................................................................................................... 91
Getting Service ............................................................................................................ 92
Express-SL/SLE
Page 7
1. Introduction
The Express-SL/SLE is a COM Express® COM.0 R2.1 Basic Size Type 6 module supporting the 64-bit 6th Generation Intel® Core™ and
Xeon® E3-and Celeron® processors (codename “Skylake-H”) with Intel® QM170, HM170, CM236 Chipset. The Express-SL/SLE is
specifically designed for customers who need excellent graphics performance and high-level processing performance in a long product life
solution.
The Express-SL/SLE features Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and DDR4 dual-channel memory at 1866/2133
MHz with ECC/non-ECC support determined by CPU/chipset combination to provide excellent overall performance. Intel® Flexible Display
Interface and Direct Media Interface provide high speed connectivity from the CPU to the Intel® QM170, HM170, CM236 Chipset.
Integrated Intel® Generation 9 Graphics includes features such as OpenGL 4.4/4.3/4.2, DirectX 11, Intel® Clear Video HD Technology,
Advanced Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full H.265/HEVC, MPEG2 hardware codec.
Graphics outputs include LVDS and three DDI ports supporting HDMI/DVI/DisplayPort and eDP as a build option. The Express-SL/SLE is
specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of
their systems for reduced development time.
The Express-SL/SLE has dual stacked SODIMM sockets supporting up to 32 GB of DDR4 ECC/non-ECC memory. In addition to the
onboard integrated graphics, a multiplexed PCIe x16 graphics bus is available for discrete graphics expansion. Input/output features include
a single onboard Gigabit Ethernet port, eight PCIe x1 Gen3 lanes, USB 3.0 ports and USB 2.0 ports, and SATA 6 Gb/s ports. Support is
provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as
remote console, hardware monitor, and watchdog timer.
Page 8
Express-SL/SLE
2. Specifications
2.1.
¾
Core System
CPU: 6th Generation Intel® Core™, Celeron® and Xeon® E3-15xx v5 processor (formerly “Skylake-H”)
•
•
•
•
•
•
•
•
•
•
Intel® Xeon® E3-15xx v5 45W/35W(cTDP) (4C/GT4e)
Intel® Xeon® E3-1505M v5 2.8/3.7GHz (Turbo), 0.35/1.0GHz (Turbo), 45W/35W(cTDP) (4C/GT2)
Intel® Xeon® E3-1505L v5 2/2.8GHz (Turbo), 0.35/1.0GHz (Turbo), 25W (4C/GT2)
Intel® Core™ i7-6820EQ 2.8/3.5GHz (Turbo), 0.35/1.0GHz (Turbo), 45W/35W(cTDP) (4C/GT2)
Intel® Core™ i7-6822EQ 2/2.8GHz (Turbo), 0.35/1.0GHz (Turbo), 25W(4C/GT2)
Intel® Core™ i5-6440EQ 2.7/3.4GHz (Turbo), 0.35/1.0GHz (Turbo), 45W/35W(cTDP) (4C/GT2)
Intel® Core™ i5-6442EQ 1.9/2.7GHz (Turbo), 0.35/1.0GHz (Turbo), 25W (4C/GT2)
Intel® Core™ i3-6100E 2.7GHz, 0.35/1.0GHz (Turbo), 35W (4C/GT2)
Intel® Core™ i3-6102E 1.9GHz, 0.35/1.0GHz (Turbo), 25W (4C/GT2)
Intel® Celeron® TBD (2C/GT1)
Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology
2.0, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure Key, Intel® TSXNI
Note: Availability of features may vary between processor SKUs.
¾
Cache: 8MB for Xeon®/Core™ i7, 6MB for Core™ i5, 3MB for Core™ i3 and 2MB for Celeron®
¾
Memory: Dual channel ECC/non-ECC 1866/2133 MHz DDR4 memory up to 32GB in dual stacked SODIMM sockets
¾
Chipset: Mobile Intel® QM170, HM170 and CM236 Chipset (HM170 does not support Intel® AMT)
¾
Embedded BIOS: AMI EFI with CMOS backup in 8 MB SPI BIOS with Intel® AMT 11 support
¾
CPU and Chipset Combination
•
•
2.2.
Express-SL (non-ECC memory support)
ƒ
Core™ i7/i5 with QM170 Chipset
ƒ
Core™ i3/Celeron® with HM170 Chipset
Express-SLE (ECC memory support)
ƒ
Xeon® with CM236 Chipset
ƒ
Core™ i3/Celeron® with CM236 Chipset (available with MOQ)
Expansion Busses
¾
PCI Express x 16 Gen3 (can be configured to 1x16, 2 x8 or 1 x8 with 2 x4)
¾
6 PCI Express x1 Gen3 (AB): Lanes 0/1/2/3/4/5
¾
2 PCI Express x1 Gen3 (CD): Lane 6/7
Note: PCIe lanes 0/1/2/3 can also be configured to x2, x4 PCIe lanes 4/5/6/7 can also be configured to x2, x4.
¾
LPC bus, SMBus (system), I2C (user)
Express-SL/SLE
Page 9
2.3.
Video
¾
Integrated on Processor: Intel® Generation 9 Graphics core architecture
¾
GPU Feature Support:
•
•
•
•
•
•
•
•
•
•
3 independent and simultaneous combinations of DisplayPort/HDMI/LVDS graphics outputs (eDP optional in place of LVDS)
Encode/transcode HD content
Playback of high definition content including Blu-ray Disc
Playback of Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D)
DirectX Video Acceleration (DXVA) support for accelerated video processing
HEVC/H.265, H.264, M/JPEG, MPEG2, VC1, WMV9, VP8/VP9 HW decode
HEVC/H.265, M/JPEG, MPEG2 HW encode
Advanced Scheduler 2.0, 1.0, XPDM support
DirectX 12, DirectX 11.3, DirectX 11, DirectX 10.1, DirectX 10, DirectX 9 support
OpenGL up to 4.4, OpenCL up to 2.1 support
Note: Availability of features may vary between OS (Win 10/8.1/7, Linux, VxWorks)
¾
Display Interface support
•
LVDS: single/dual channel 18/24-bit LVDS through eDP to LVDS (NXP IC)
•
eDP: up to 4 lane support, in place of LVDS (BOM option)
•
Digital Display Ports x3:
ƒ
2.4.
DDI1/2/3 support DisplayPort/HDMI/DVI
Audio
¾
Integrated: Intel® HD Audio integrated in QM170/HM170/CM236 Chipset
¾
Audio Codec: located on carrier Express-BASE6 (ALC886 standard support)
2.5.
LAN
¾
Integrated: MAC integrated in QM170/HM170/CM236 Chipset
¾
Intel PHY: Intel® i219LM Ethernet controller
¾
Interface: 10/100/1000 Mbit/s connection
2.6.
Multi I/O and Storage
¾
Integrated: Intel® QM170/HM170/CM236 Chipset
¾
USB: 4x USB 3.0 (USB 0,1,2,3), 4x USB 2.0 (USB 4,5,6,7)
¾
SATA*: 4x SATA 6Gb/s (SATA 0,1,2,3)
¾
GPIO: 4 GPO and 4 GPI (interrupt support is TBD)
*Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board.
Page 10
Express-SL/SLE
2.7.
Serial I/O on Module
¾
Chipset: Nuvoton NCT5104D
¾
Ports: 2x UARTs Rx/Tx only
¾
Console Redirection: COM 1 or COM 2 selectable in BIOS
COM Port
2.8.
Description
IRQ
Address
Console redirection support
COM 1
Supported by module (SER0, A98/A99), via NCT5104D
10
0x240
Yes
COM 2
Supported by module (SER1, A101/A102), via NCT5104D
11
0x248
Yes
COM 3
Supported by Super I/O (W83627DHG) on carrier board
4
0x3F8
Yes
COM 4
Supported by Super I/O (W83627DHG) on carrier board
3
0x2F8
Yes
Trusted Platform Module (TPM)
¾
Chipset: Atmel AT97SC3204
¾
Type: TPM 1.2
2.9.
SEMA Board Controller
¾
Type: ADLINK Smart Embedded Management Agent (SEMA)
¾
Supports:
•
•
•
•
•
•
•
•
Voltage/Current monitoring
Power sequence debug support
AT/ATX mode control
Logistics and Forensic information
Flat Panel Control
General Purpose I2C
Failsafe BIOS (dual BIOS )
Watchdog Timer and Fan Control
2.10. Debug Headers
¾
40-pin multipurpose flat cable connector, used in combination with DB-40 debug module providing BIOS POST code LED, BMC
access, SPI BIOS flashing, power testpoints, debug LEDs
¾
60-pin XDP header for ICE debug of CPU/chipset
Express-SL/SLE
Page 11
2.11. Power Specifications
¾
Power Modes:
AT and ATX mode (AT mode startup controlled by SEMA)
¾
Standard Voltage Input: ATX @ 12V±5%,/ 5Vsb ±5% or AT @ 12V ±5%
¾
Wide Voltage Input:
ATX @ 8.5-20V, 5Vsb ±5% or AT @ 8.5-20V
¾
Power Management:
ACPI 5.0 compliant, Smart Battery support
¾
Power States:
supports C1-C6, S0, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WOL S3/S4/S5)
¾
ECO mode:
supports deep S5 for 5Vsb power saving
2.12. Power Consumption
Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.
2.13. Operating Temperatures
¾
Standard:
°C to 60°C (wide voltage input)
¾
Extreme Rugged™:
-40°C to 85°C (standard voltage input)
2.14. Environmental
¾
Humidity:
5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾
Shock and Vibration:
IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾
Halt:
Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.15. Specification Compliance
¾
PICMG COM.0: Rev 2.1 Type 6, Basic size 125 x 95 mm
2.16. Operating Systems
¾
Standard Support:
¾
Extended Support (BSP): Windows 10 Enterprise (64-bit), WES 7 (32/64-bit), , Linux 64-bit, VxWorks
Page 12
Windows 10/8.1 (64-bit), Windows 7 (32/64-bit),, Linux (64-bit), VxWorks
Express-SL/SLE
Express-SL/SLE
CD
AB
UMI
2.17. Functional Diagram
Page 13
2.18.
Page 14
Mechanical Dimensions
Express-SL/SLE
3. Pinouts and Signal Descriptions
3.1.
AB/CD Pin Definitions
The Express-SL/SLE is a Type 6 module supporting USB 3.0 and DDI channels on the CD connector. In the table below, all standard pins of
the COM Express specification are described, including those not supported on the Express-SL/SLE.
Note: Signals not supported on the Express-SL/SLE module are crossed out.
Row A
Pin
Name
A1
A2
Row B
Row C
Pin
Name
Pin
Name
GND (fixed)
B1
GND (fixed)
C1
GBE0_MDI3-
B2
GBE0_ACT#
C2
A3
GBE0_MDI3+
B3
LPC_FRAME#
A4
GBE0_LINK100#
B4
LPC_AD0
A5
GBE0_LINK1000#
B5
A6
GBE0_MDI2-
B6
A7
GBE0_MDI2+
A8
GBE0_LINK#
A9
A10
A11
Row D
Pin
Name
GND (fixed)
D1
GND (fixed)
GND
D2
GND
C3
USB_SSRX0-
D3
USB_SSTX0-
C4
USB_SSRX0+
D4
USB_SSTX0+
LPC_AD1
C5
GND
D5
GND
LPC_AD2
C6
USB_SSRX1-
D6
USB_SSTX1-
B7
LPC_AD3
C7
USB_SSRX1+
D7
USB_SSTX1+
B8
LPC_DRQ0#
C8
GND
D8
GND
GBE0_MDI1-
B9
LPC_DRQ1#
C9
USB_SSRX2-
D9
USB_SSTX2-
GBE0_MDI1+
B10
LPC_CLK
C10
USB_SSRX2+
D10
USB_SSTX2+
GND (fixed)
B11
GND (fixed)
C11
GND (fixed)
D11
GND (fixed)
A12
GBE0_MDI0-
B12
PWRBTN#
C12
USB_SSRX3-
D12
USB_SSTX3-
A13
GBE0_MDI0+
B13
SMB_CK
C13
USB_SSRX3+
D13
USB_SSTX3+
A14
GBE0_CTREF
B14
SMB_DAT
C14
GND
D14
GND
A15
SUS_S3#
B15
SMB_ALERT#
C15
DDI1_PAIR6+
D15
DDI1_CTRLCLK_AUX+
A16
SATA0_TX+
B16
SATA1_TX+
C16
DDI1_PAIR6-
D16
DDI1_CTRLDATA_AUX
A17
SATA0_TX-
B17
SATA1_TX-
C17
RSVD
D17
RSVD
A18
SUS_S4#
B18
SUS_STAT#
C18
RSVD
D18
RSVD
A19
SATA0_RX+
B19
SATA1_RX+
C19
PCIE_RX6+
D19
PCIE_TX6+
A20
SATA0_RX-
B20
SATA1_RX-
C20
PCIE_RX6-
D20
PCIE_TX6-
A21
GND (fixed)
B21
GND (fixed)
C21
GND (fixed)
D21
GND (fixed)
A22
SATA2_TX+
B22
SATA3_TX+
C22
PCIE_RX7+
D22
PCIE_TX7+
A23
SATA2_TX-
B23
SATA3_TX-
C23
PCIE_RX7-
D23
PCIE_TX7-
A24
SUS_S5#
B24
PWR_OK
C24
DDI1_HPD
D24
RSVD
A25
SATA2_RX+
B25
SATA3_RX+
C25
DDI1_PAIR4+
D25
RSVD
A26
SATA2_RX-
B26
SATA3_RX-
C26
DDI1_PAIR4-
D26
DDI1_PAIR0+
A27
BATLOW#
B27
WDT
C27
RSVD
D27
DDI1_PAIR0-
A28
(S)ATA_ACT#
B28
AC/HDA_SDIN2
C28
RSVD
D28
RSVD
A29
AC/HDA_SYNC
B29
AC/HDA_SDIN1
C29
DDI1_PAIR5+
D29
DDI1_PAIR1+
A30
AC/HDA_RST#
B30
AC/HDA_SDIN0
C30
DDI1_PAIR5-
D30
DDI1_PAIR1-
A31
GND (fixed)
B31
GND (fixed)
C31
GND (fixed)
D31
GND (fixed)
A32
AC/HDA_BITCLK
B32
SPKR
C32
DDI2_CTRLCLK_AUX+
D32
DDI1_PAIR2+
A33
AC/HDA_SDOUT
B33
I2C_CK
C33
DDI2_CTRLDATA_AUX-
D33
DDI1_PAIR2-
A34
BIOS_DIS0#
B34
I2C_DAT
C34
DDI2_DDC_AUX_SEL
D34
DDI1_DDC_AUX_SEL
A35
THRMTRIP#
B35
THRM#
C35
RSVD
D35
RSVD
Express-SL/SLE
Page 15
Row A
Row B
Row C
Pin
Name
Pin
Name
Pin
Name
A36
USB6-
B36
USB7-
C36
A37
USB6+
B37
USB7+
C37
A38
USB_6_7_OC#
B38
USB_4_5_OC#
A39
USB4-
B39
USB5-
A40
Row D
Pin
Name
DDI3_CTRLCLK_AUX+
D36
DDI1_PAIR3+
DDI3_CTRLDATA_AUX-
D37
DDI1_PAIR3-
C38
DDI3_DDC_AUX_SEL
D38
RSVD
C39
DDI3_PAIR0+
D39
DDI2_PAIR0+
USB4+
B40
USB5+
C40
DDI3_PAIR0-
D40
DDI2_PAIR0-
A41
GND (fixed)
B41
GND (fixed)
C41
GND (fixed)
D41
GND (fixed)
A42
USB2-
B42
USB3-
C42
DDI3_PAIR1+
D42
DDI2_PAIR1+
A43
USB2+
B43
USB3+
C43
DDI3_PAIR1-
D43
DDI2_PAIR1-
A44
USB_2_3_OC#
B44
USB_0_1_OC#
C44
DDI3_HPD
D44
DDI2_HPD
A45
USB0-
B45
USB1-
C45
RSVD
D45
RSVD
A46
USB0+
B46
USB1+
C46
DDI3_PAIR2+
D46
DDI2_PAIR2+
A47
VCC_RTC
B47
EXCD1_PERST#
C47
DDI3_PAIR2-
D47
DDI2_PAIR2-
A48
EXCD0_PERST#
B48
EXCD1_CPPE#
C48
RSVD
D48
RSVD
A49
EXCD0_CPPE#
B49
SYS_RESET#
C49
DDI3_PAIR3+
D49
DDI2_PAIR3+
A50
LPC_SERIRQ
B50
CB_RESET#
C50
DDI3_PAIR3-
D50
DDI2_PAIR3-
A51
GND (fixed)
B51
GND (fixed)
C51
GND (fixed)
D51
GND (fixed)
A52
PCIE_TX5+
B52
PCIE_RX5+
C52
PEG_RX0+
D52
PEG_TX0+
A53
PCIE_TX5-
B53
PCIE_RX5-
C53
PEG_RX0-
D53
PEG_TX0-
A54
GPI0
B54
GPO1
C54
TYPE0#
D54
PEG_LANE_RV#
A55
PCIE_TX4+
B55
PCIE_RX4+
C55
PEG_RX1+
D55
PEG_TX1+
A56
PCIE_TX4-
B56
PCIE_RX4-
C56
PEG_RX1-
D56
PEG_TX1-
A57
GND
B57
GPO2
C57
TYPE1#
D57
TYPE2#
A58
PCIE_TX3+
B58
PCIE_RX3+
C58
PEG_RX2+
D58
PEG_TX2+
A59
PCIE_TX3-
B59
PCIE_RX3-
C59
PEG_RX2-
D59
PEG_TX2-
A60
GND (fixed)
B60
GND (fixed)
C60
GND (fixed)
D60
GND (fixed)
A61
PCIE_TX2+
B61
PCIE_RX2+
C61
PEG_RX3+
D61
PEG_TX3+
A62
PCIE_TX2-
B62
PCIE_RX2-
C62
PEG_RX3-
D62
PEG_TX3-
A63
GPI1
B63
GPO3
C63
RSVD
D63
RSVD
A64
PCIE_TX1+
B64
PCIE_RX1+
C64
RSVD
D64
RSVD
A65
PCIE_TX1-
B65
PCIE_RX1-
C65
PEG_RX4+
D65
PEG_TX4+
A66
GND
B66
WAKE0#
C66
PEG_RX4-
D66
PEG_TX4-
A67
GPI2
B67
WAKE1#
C67
RSVD
D67
GND
A68
PCIE_TX0+
B68
PCIE_RX0+
C68
PEG_RX5+
D68
PEG_TX5+
A69
PCIE_TX0-
B69
PCIE_RX0-
C69
PEG_RX5-
D69
PEG_TX5-
A70
GND (fixed)
B70
GND (fixed)
C70
GND (fixed)
D70
GND (fixed)
A71
LVDS_A0+
B71
LVDS_B0+
C71
PEG_RX6+
D71
PEG_TX6+
A72
LVDS_A0-
B72
LVDS_B0-
C72
PEG_RX6-
D72
PEG_TX6-
A73
LVDS_A1+
B73
LVDS_B1+
C73
GND
D73
GND
A74
LVDS_A1-
B74
LVDS_B1-
C74
PEG_RX7+
D74
PEG_TX7+
A75
LVDS_A2+
B75
LVDS_B2+
C75
PEG_RX7-
D75
PEG_TX7-
A76
LVDS_A2-
B76
LVDS_B2-
C76
GND
D76
GND
A77
LVDS_VDD_EN
B77
LVDS_B3+
C77
RSVD
D77
RSVD
A78
LVDS_A3+
B78
LVDS_B3-
C78
PEG_RX8+
D78
PEG_TX8+
A79
LVDS_A3-
B79
LVDS_BKLT_EN
C79
PEG_RX8-
D79
PEG_TX8-
Page 16
Express-SL/SLE
Row A
Row B
Row C
Row D
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A80
GND (fixed)
B80
GND (fixed)
C80
GND (fixed)
D80
GND (fixed)
A81
LVDS_A_CK+
B81
LVDS_B_CK+
C81
PEG_RX9+
D81
PEG_TX9+
A82
LVDS_A_CK-
B82
LVDS_B_CK-
C82
PEG_RX9-
D82
PEG_TX9-
A83
LVDS_I2C_CK
B83
LVDS_BKLT_CTRL
C83
RSVD
D83
RSVD
A84
LVDS_I2C_DAT
B84
VCC_5V_SBY
C84
GND
D84
GND
A85
GPI3
B85
VCC_5V_SBY
C85
PEG_RX10+
D85
PEG_TX10+
A86
RSVD
B86
VCC_5V_SBY
C86
PEG_RX10-
D86
PEG_TX10-
A87
RSVD
B87
VCC_5V_SBY
C87
GND
D87
GND
A88
PCIE0_CK_REF+
B88
BIOS_DIS1#
C88
PEG_RX11+
D88
PEG_TX11+
A89
PCIE0_CK_REF-
B89
VGA_RED
C89
PEG_RX11-
D89
PEG_TX11-
A90
GND (fixed)
B90
GND (fixed)
C90
GND (fixed)
D90
GND (fixed)
A91
SPI_POWER
B91
VGA_GRN
C91
PEG_RX12+
D91
PEG_TX12+
A92
SPI_MISO
B92
VGA_BLU
C92
PEG_RX12-
D92
PEG_TX12-
A93
GPO0
B93
VGA_HSYNC
C93
GND
D93
GND
A94
SPI_CLK
B94
VGA_VSYNC
C94
PEG_RX13+
D94
PEG_TX13+
A95
SPI_MOSI
B95
VGA_I2C_CK
C95
PEG_RX13-
D95
PEG_TX13-
A96
TPM_PP
B96
VGA_I2C_DAT
C96
GND
D96
GND
A97
TYPE10#
B97
SPI_CS#
C97
RSVD
D97
RSVD
A98
SER0_TX / CAN_TX
B98
RSVD
C98
PEG_RX14+
D98
PEG_TX14+
A99
SER0_RX / CAN_RX
B99
RSVD
C99
PEG_RX14-
D99
PEG_TX14-
A100
GND (fixed)
B100
GND (fixed)
C100
GND (fixed)
D100
GND (fixed)
A101
SER1_TX
B101
FAN_PWMOUT
C101
PEG_RX15+
D101
PEG_TX15+
A102
SER1_RX
B102
FAN_TACHIN
C102
PEG_RX15-
D102
PEG_TX15-
A103
LID# **
B103
SLEEP# **
C103
GND
D103
GND
A104
VCC_12V
B104
VCC_12V
C104
VCC_12V
D104
VCC_12V
A105
VCC_12V
B105
VCC_12V
C105
VCC_12V
D105
VCC_12V
A106
VCC_12V
B106
VCC_12V
C106
VCC_12V
D106
VCC_12V
A107
VCC_12V
B107
VCC_12V
C107
VCC_12V
D107
VCC_12V
A108
VCC_12V
B108
VCC_12V
C108
VCC_12V
D108
VCC_12V
A109
VCC_12V
B109
VCC_12V
C109
VCC_12V
D109
VCC_12V
A110
GND (fixed)
B110
GND (fixed)
C110
GND (fixed)
D110
GND (fixed)
Note: 4-lane eDP is available as BOM option in place of LVDS. *
Express-SL/SLE
Page 17
3.2.
Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
Page 18
I
Input to the Module
O
Output from the Module
I/O
Bi-directional input/output signal
OD
Open drain output
I 3.3V
Input 3.3V tolerant
I 5V
Input 5V tolerant
O 3.3V
Output 3.3V signal level
O 5V
Output 5V signal level
I/O 3.3V
Bi-directional signal 3.3V tolerant
I/O 5V
Bi-directional signal 5V tolerant
I/O 3.3Vsb
Input 3.3V tolerant active in standby state
P
Power Input/Output
REF
Reference voltage output that may be sourced from a module power plane.
PDS
Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU
ADLINK implemented pull-up resistor on module
PD
ADLINK implemented pull-down resistor on module
Express-SL/SLE
3.3.
AB Signal Descriptions
3.3.1.
Audio Signals
Signal
Pin #
Description
I/O
AC_RST# /
HDA_RST#
A30
Reset output to CODEC, active low.
O 3.3VSB
AC_SYNC /
HDA_SYNC
A29
Sample-synchronization signal to the CODEC(s).
O 3.3VSB
AC_BITCLK /
HDA_BITCLK
A32
Serial data clock generated by the external
CODEC(s).
I/O 3.3VSB
AC _SDOUT /
HDA_SDOUT
A33
Serial TDM data output to the CODEC.
O 3.3VSB
Boot strap pin, no external pull-up or
pull-down resistor on carrier board is
recommended to avoid change the
configuration of this signal
AC _SDIN[2:0]
HDA_SDIN[2:0]
B28
B29
B30
Serial TDM data inputs from up to 3 CODECs.
I 3.3VSB
AC_SDIN0: supported
AC_SDIN1: supported
AC_SDIN2: supported
3.3.2.
PU/PD
Comment
Analog VGA
Note: No VGA support on this product.
Signal
Pin #
Description
I/O
PU/PD
Comment
VGA_RED
B89
Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
VGA_GRN
B91
Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
VGA_BLU
B92
Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
VGA_HSYNC
B93
Horizontal sync output to VGA monitor
O 5V
VGA_VSYNC
B94
Vertical sync output to VGA monitor
O 5V
VGA_I2C_CK
B95
DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
I/O OD 3.3V
PU 2k2 3.3V
VGA_I2C_DAT
B96
DDC data line.
I/O OD 3.3V
PU 2k2 3.3V
Express-SL/SLE
Page 19
3.3.3.
LVDS
Signal
Pin #
Description
I/O
LVDS_A0+ / eDP_TX2+
LVDS_A0- / eDP_TX2LVDS_A1+ / eDP_TX1+
LVDS_A1- / eDP_TX1LVDS_A2+ / eDP_TX0+
LVDS_A2- / eDP_TX0LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs
O LVDS
LVDS_A_CK+ / eDP_TX3+
LVDS_A_CK- / eDP_TX3-
A81
A82
LVDS Channel A differential clock
O LVDS
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3-
B71
B72
B73
B74
B75
B76
B77
B78
LVDS Channel B differential pairs
O LVDS
LVDS_B_CK+
LVDS_B_CK-
B81
B82
LVDS Channel B differential clock
O LVDS
LVDS_VDD_EN
A77
LVDS panel power enable
O 3.3V
PD 10K
LVDS_BKLT_EN
B79
LVDS panel backlight enable
O 3.3V
PD 10K
LVDS_BKLT_CTRL
B83
LVDS panel backlight brightness control
O 3.3V
PD 100K
LVDS_I2C_CK
A83
DDC lines used for flat panel detection and
control.
I/O OD
3.3V
PU 2k2 3.3V
LVDS_I2C_DAT
A84
DDC lines used for flat panel detection and
control.
I/O OD
3.3V
PU 2k2 3.3V
3.3.4.
PU/PD
Comment
eDP
Note: eDP is a BOM option, in place of LVDS.
Signal
Pin #
Description
I/O
eDP_TX2+
eDP_TX2eDP_TX1+
eDP_TX1eDP_TX0+
eDP_TX0--
A71
A72
A73
A74
A75
A76
eDP differential pairs
O PCIE
AC coupled off module
eDP_TX3+
eDP_TX3--
A81
A82
eDP differential pairs
O PCIE
AC coupled off module
eDP_VDD_EN
A77
eDP power enable
O 3.3V
PD 10K
eDP_BKLT_EN
B79
eDP backlight enable
O 3.3V
PD 10K
eDP_BKLT_CTRL
B83
eDP backlight brightness control
O 3.3V
PD 100K
eDP_AUX+
A83
eDP AUX+
I/O PCIE
AC coupled off module
eDP_AUX-
A84
eDP AUX-
I/O PCIE
AC coupled off module
eDP_HPD
A87
Detection of Hot Plug / Unplug and notification of
the link layer
I 3.3V
Page 20
PU/PD
PD 100K
Comment
PD 100K on this pin when
eDP is supported
Express-SL/SLE
3.3.5.
Gigabit Ethernet
Gigabit Ethernet
Pin #
Description
I/O
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3-
A13
A11
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
1000
100
10
MDI[0]+/B1_DA+/TX+/TX+/MDI[1]+/B1_DB+/RX+/RX+/MDI[2]+/B1_DC+/MDI[3]+/B1_DD+/-
I/O Analog
GBE0_ACT#
B2
Gigabit Ethernet Controller 0 activity indicator, active low.
O 3.3VSB
GBE0_LINK#
A8
Gigabit Ethernet Controller 0 link indicator, active low.
O 3.3VSB
GBE0_LINK100#
A4
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
O 3.3VSB
GBE0_LINK1000#
A5
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.
O 3.3VSB
GBE0_CTREF
A14
Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The reference
voltage output shall be current limited on the Module. In the case in which
the reference is shorted to ground, the current shall be 250 mA or less.
GND min
3.3V max
3.3.6.
PU/PD
Comment
Twisted pair
signals for
external
transformer.
NC pin
SATA
Signal
Pin #
Description
I/O
SATA0_TX+
SATA0_TX-
A16
A17
Serial ATA channel 0, Transmit Output differential pair.
O SATA
AC coupled on Module
SATA0_RX+
SATA0_RX-
A19
A20
Serial ATA channel 0, Receive Input differential pair.
I SATA
AC coupled on Module
SATA1_TX+
SATA1_TX-
B16
B17
Serial ATA channel 1, Transmit Output differential pair.
O SATA
AC coupled on Module
SATA1_RX+
SATA1_RX-
B19
B20
Serial ATA channel 1, Receive Input differential pair.
I SATA
AC coupled on Module
SATA2_TX+
SATA2_TX-
A22
A23
Serial ATA channel 2, Transmit Output differential pair.
O SATA
AC coupled on Module
SATA2_RX+
SATA2_RX-
A25
A26
Serial ATA channel 2, Receive Input differential pair.
I SATA
AC coupled on Module
SATA3_TX+
SATA3_TX-
B22
B23
Serial ATA channel 3, Transmit Output differential pair.
O SATA
AC coupled on Module
SATA3_RX+
SATA3_RX-
B25
B26
Serial ATA channel 3, Receive Input differential pair.
I SATA
AC coupled on Module
(S)ATA_ACT#
A28
ATA (parallel and serial) or SAS activity indicator, active low.
O 3.3V
Express-SL/SLE
PU/PD
Comment
PU 10K
3.3V
Page 21
3.3.7.
PCI Express
Signal
Pin #
Description
I/O
PCIE_TX0+
PCIE_TX0-
A68
A69
PCI Express channel 0, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX0+
PCIE_RX0-
B68
B69
PCI Express channel 0, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_TX1+
PCIE_TX1-
A64
A65
PCI Express channel 1, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX1+
PCIE_RX1-
B64
B65
PCI Express channel 1, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_TX2+
PCIE_TX2-
A61
A62
PCI Express channel 2, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX2+
PCIE_RX2-
B61
B62
PCI Express channel 2, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_TX3+
PCIE_TX3-
A58
A59
PCI Express channel 3, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX3+
PCIE_RX3-
B58
B59
PCI Express channel 3, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_TX4+
PCIE_TX4-
A55
A56
PCI Express channel 4, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX4+
PCIE_RX4-
B55
B56
PCI Express channel 4, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_TX5+
PCIE_TX5-
A52
A53
PCI Express channel 5, Transmit Output
differential pair.
O PCIE
AC coupled on Module
PCIE_RX5+
PCIE_RX5-
B52
B53
PCI Express channel 5, Receive Input
differential pair.
I PCIE
AC coupled off Module
PCIE_CLK_REF+
PCIE_CLK_REF-
A88
A89
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
O PCIE
3.3.8.
PU/PD
Comment
Express Card
Signal
Pin #
Description
I/O
PU/PD
EXCD0_CPPE#
EXCD1_CPPE#
A49
B48
PCI ExpressCard: PCI Express capable card request
I 3.3V
PU 10k 3.3V
EXCD0_PERST#
EXCD1_PERST#
A48
B47
PCI ExpressCard: reset
O 3.3V
Page 22
Comment
Express-SL/SLE
3.3.9.
LPC Bus
Signal
Pin #
Description
I/O
PU/PD
LPC_AD[0:3]
B4-B7
LPC multiplexed address, command and data bus
I/O 3.3V
LPC_FRAME#
B3
LPC frame indicates the start of an LPC cycle
O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request
I 3.3V
LPC_SERIRQ
A50
LPC serial interrupt
I/O OD 3.3V
LPC_CLK
B10
LPC clock output –33MHz nominal
O 3.3V
Comment
Chipset has internal pull-up
PU 10 3.3V
3.3.10. USB
Signal
Pin #
Description
I/O
USB0+
USB0-
A46
A45
USB differential data pairs for Port 0
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB1+
USB1-
B46
B45
USB differential data pairs for Port 1
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB2+
USB2-
A43
A42
USB differential data pairs for Port 1
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB3+
USB3-
B43
B42
USB differential data pairs for Port 2
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB4+
USB4-
A40
A39
USB differential data pairs for Port 3
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB5+
USB5-
B40
B39
USB differential data pairs for Port 4
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB6+
USB6-
A37
A36
USB differential data pairs for Port 5
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB7+
USB7-
B37
B37
USB differential data pairs for Port 6
I/O 3.3VSB
USB 1.1/ 2.0 compliant
USB_0_1_OC#
B44
USB over-current sense, USB ports 0 and 1. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB
PU 10k 3.3VSB
Do not pull high on carrier
USB_2_3_OC#
A44
USB over-current sense, USB ports 2 and 3. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
I 3.3VSB
PU 10k 3.3VSB
Do not pull high on carrier
USB_4_5_OC#
B38
USB over-current sense, USB ports 4 and 5. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB
PU 10k 3.3VSB
Do not pull high on carrier
USB_6_7_OC#
A38
USB over-current sense, USB ports 6 and 7. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB
PU 10k 3.3VSB
Do not pull high on carrier
Express-SL/SLE
PU/PD
Comment
Page 23
3.3.11. USB Root Segmentation
All USB from XHCI controller
3.3.12. SPI (BIOS only)
Signal
Pin #
Description
I/O
PU/PD
SPI_CS#
B97
Chip select for Carrier Board SPI BIOS Flash.
O 3.3VSB
PU 10K 3.3VSB
SPI_MISO
A92
Data in to module from carrier board SPI BIOS flash.
I 3.3VSB
SPI_MOSI
A95
Data out from module to carrier board SPI BIOS flash.
O 3.3VSB
SPI_CLK
A94
Clock from module to carrier board SPI BIOS flash.
O 3.3VSB
SPI_POWER
A91
Power supply for Carrier Board SPI – sourced from Module
– nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on
the Carrier
O P 3.3VSB
BIOS_DIS0#
A34
Selection strap to determine the BIOS boot device.
I
PU 10K 3.3VSB
Carrier shall pull to GND
or leave not- connected.
BIOS_DIS1#
B88
Selection strap to determine the BIOS boot device.
I
PU 10K 3.3VSB
Carrier shall pull to GND
or leave not- connected
Page 24
Comment
Express-SL/SLE
3.3.13. Miscellaneous
Signal
Pin #
Description
I/O
PU/PD
SPKR
B32
Output for audio enunciator, the “speaker” in PC-AT
systems
O 3.3V
WDT
B27
Output indicating that a watchdog time-out event has
occurred.
O 3.3V
THRM#
B35
Input from off-module temp sensor indicating an over-temp
situation.
I 3.3VSB
THRMTRIP#
A35
Active low output indicating that the CPU has entered
thermal shutdown.
O 3.3V
FAN_PWMOUT
B101
Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
O OD 3.3V
PU 2.2K 3.3V
FAN_TACHIN
B102
Fan tachometer input for a fan with a two pulse output.
I OD 3.3V
PU 10k 3.3V
TPM_PP
A96
Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the TPM.
I 3.3V
PD 1k
Comment
PD only when TPM on
module
3.3.14. SMBus
Signal
Pin #
Description
I/O
PU/PD
SMB_CK
B13
System Management Bus bidirectional clock line. Power
sourced through 5V standby rail and main power rails.
I/O OD 3.3VSB
PU 8.2K 3.3VSB
SMB_DAT#
B14
System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
I/O OD 3.3VSB
PU 8.2K 3.3VSB
SMB_ALERT#
B15
System Management Bus Alert – active low input can
be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced
through 5V standby rail and main power rails.
I 3.3VSB
PU 2k2 3.3VSB
Comment
3.3.15. I2C Bus
Signal
Pin #
Description
I/O
PU/PD
Comment
I2C_CK
B33
General purpose I²C port clock output/input
I/O OD 3.3VSB
PU 2k2 3.3VSB
Source SEMA BMC
I2C_DAT
B34
General purpose I²C port data I/O line
I/O OD 3.3VSB
PU 2k2 3.3VSB
Source SEMA BMC
Express-SL/SLE
Page 25
3.3.16. General Purpose I/O (GPIO)
Signal
Pin #
Description
I/O
PU/PD
Comment
GPO[0]
A93
General purpose output pins.
O 3.3V
PU 10K 3.3V
After hardware RESET
output low
GPO[1]
B54
General purpose output pins.
O 3.3V
PU 10K 3.3V
After hardware RESET
output low
GPO[2]
B57
General purpose output pins.
O 3.3V
PU 10K 3.3V
After hardware RESET
output low
GPO[3]
B63
General purpose output pins.
O 3.3V
PU 10K 3.3V
After hardware RESET
output low
GPI[0]
A54
General purpose input pins.
Pulled high internally on the module.
I 3.3V
PU 10K 3.3V
GPI[1]
A63
General purpose input pins.
Pulled high internally on the module.
I 3.3V
PU 10K 3.3V
GPI[2]
A67
General purpose input pins.
Pulled high internally on the module.
I 3.3V
PU 10K 3.3V
GPI[3]
A85
General purpose input pins.
Pulled high internally on the module.
I 3.3V
PU 10K 3.3V
PU/PD
3.3.17. Serial Interface Signals
Signal
Pin #
Description
I/O
SER0_TX
A98
General purpose serial port transmitter (TTL level output)
O CMOS
SER0_RX A99
General purpose serial port receiver (TTL level input)
I CMOS
SER1_TX
General purpose serial port transmitter (TTL level output)
O CMOS
General purpose serial port receiver (TTL level input)
I CMOS
A101
SER1_RX A102
Comment
Power rail tolerance 5V, 12V
PU 47K 3.3V
Power rail tolerance 5V, 12V
Power rail tolerance 5V, 12V
PU 47K 3.3V
Power rail tolerance 5V, 12V
3.3.18. Power and System Management
Signal
Pin #
Description
I/O
PU/PD
PWRBTN#
B12
Power button to bring system out of S5 (soft off), active on falling edge.
I 3.3VSB
PU 10k
3.3VSB
SYS_RESET#
B49
Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used.
I 3.3V
PU 10k 3.3V
CB_RESET#
B50
Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
O 3.3V
PD 100K
PWR_OK
B24
Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
based FPGAs or other configurable devices time to be programmed.
I 3.3V
PU 100k
3.3VSB
SUS_STAT#
B18
Indicates imminent suspend operation; used to notify LPC devices.
O 3.3VSB
SUS_S3#
A15
Indicates system is in Suspend to RAM state. Active-low output. An inverted
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
O 3.3VSB
Page 26
Comment
Should have
weak pull up
Express-SL/SLE
Signal
Pin #
Description
I/O
PU/PD
SUS_S4#
A18
Indicates system is in Suspend to Disk state. Active low output.
O 3.3VSB
SUS_S5#
A24
Indicates system is in Soft Off state.
O 3.3VSB
WAKE0#
B66
PCI Express wake up signal.
I 3.3VSB
PU 10k
3.3VSB
WAKE1#
B67
General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
I 3.3VSB
PU 10k
3.3VSB
BATLOW#
A27
Battery low input. This signal may be driven low by external circuitry to
signal that the system battery is low, or may be used to signal some other
external power-management event.
I 3.3VSB
PU 10k
3.3VSB
LID#
A103
LID button. Low active signal used by the ACPI operating system for a LID
switch.
I OD
3.3VSB
PU 10k
3.3VSB
SLEEP#
B103
Sleep button. Low active signal used by the ACPI operating system to bring
the system to sleep state or to wake it up again.
I OD
3.3VSB
PU 10K
3.3VSB
Comment
Connect to
WAKE 1#
3.3.19. Power and Ground
Signal
Pin #
Description
I/O
VCC_12V
A104-A109
B104-B109
Primary power input: +12V nominal (wide range 5 ~ 20V).
All available VCC_12V pins on the connector(s) shall be used.
P
8.5~20 V
VCC_5V_SBY
B84-B87
Standby power input: +5.0V nominal. See section 7 “Electrical
Specifications“ for allowable input range. If VCC5_SBY is used,
all available VCC_5V_SBY pins on the connector(s) shall be
used. Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.
P
5Vsb ±5%
VCC_RTC
A47
Real-time clock circuit-power input. Nominally +3.0V.
P
GND
A1, A11, A21, A31, A41, A51,
A57, A66, A80, A90, A96, A100,
A110, B1, B11, B21,B31, B41,
B51, B60, B70, B80, B90, B100,
B110
Ground - DC power and signal and AC signal return path.
P
Express-SL/SLE
PU/PD
Comment
Page 27
3.4.
CD Signal Descriptions
3.4.1.
USB 3.0 Extension
Signal
Pin #
Description
I/O
USB_SSRX0USB_SSRX0+
C3
C4
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB0
I PCIE
AC coupled off module
USB_SSTX0USB_SSTX0+
D3
D4
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB0
O PCIE
AC coupled on module
USB_SSRX1USB_SSRX1+
C6
C7
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB1
I PCIE
AC coupled off module
USB_SSTX1USB_SSTX1+
D6
D7
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB1
O PCIE
AC coupled on module
USB_SSRX2USB_SSRX2+
C9
C10
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB2
I PCIE
AC coupled off module
USB_SSTX2USB_SSTX2+
D9
D10
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB2
O PCIE
AC coupled on module
USB_SSRX3USB_SSRX3+
C12
C13
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB3
I PCIE
AC coupled off module
USB_SSTX3USB_SSTX3+
D12
D13
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB3
O PCIE
AC coupled on module
3.4.2.
PU/PD
Comment
PCI Express x1
Signal
Pin #
Description
I/O
PCIE_TX6+
PCIE_TX6-
D19
D20
PCI Express channel 6, Transmit Output differential pair.
O PCIE
AC coupled on module
PCIE_RX6+
PCIE_RX6-
C19
C20
PCI Express channel 6, Receive Input differential pair.
I PCIE
AC coupled off module
PCIE_TX7+
PCIE_TX7-
D22
D23
PCI Express channel 7, Transmit Output differential pair.
O PCIE
AC coupled on module
PCIE_RX7+
PCIE_RX7-
C22
C23
PCI Express channel 7, Receive Input differential pair.
I PCIE
AC coupled off module
Page 28
PU/PD
Comment
Express-SL/SLE
3.4.3.
DDI Channels
DDI 1
Signal
Pin
Description
I/O
DDI1_PAIR0+
DDI1_PAIR0DDI1_PAIR1+
DDI1_PAIR1DDI1_PAIR2+
DDI1_PAIR2DDI1_PAIR3+
DDI1_PAIR3DDI1_PAIR4+
DDI1_PAIR4DDI1_PAIR5+
DDI1_PAIR5DDI1_PAIR6+
DDI1_PAIR6-
D26
D27
D29
D30
D32
D33
D36
D37
C25
C26
C29
C30
C15
C16
Digital Display Interface1 differential pairs
O PCIE
DDI1_HPD
C24
Digital Display Interface Hot-Plug Detect
I 3.3V
PD 100K
DDI1_CTRLCLK_AUX+
D15
IF DDI1_DDC_AUX_SEL is floating
I/O PCIE
PD 100K
IF DDI1_DDC_AUX_SEL pulled high
I/O OD 3.3V
IF DDI1_DDC_AUX_SEL is floating
I/O PCIE
IF DDI1_DDC_AUX_SEL pulled high
I/O OD 3.3V
Selects the function of
DDI1_CTRLCLK_AUX+ and
DDI1_CTRLDATA_AUX-. This pin shall
have a 1M pull-down to logic ground on
the Module. If this input is floating the
AUX pair is used for the DP AUX+/signals. If pulled-high the AUX pair
contains the CRTLCLK and CTRLDATA
signals.
I 3.3V
DDI1_CTRLCLK_AUX-
DDI1_DDC_AUX_SEL
Express-SL/SLE
D16
D34
PU/PD
Comment
Pair 4 to Pair 6
Not supported
DP1_AUX+
HDMI1_CTRLCLK
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PU 100K
3.3V
DP1_AUXHDMI1_CTRLDATA
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PD 1M
Page 29
DDI 2
Signal
Pin
Description
I/O
DDI2_PAIR0+
DDI2_PAIR0DDI2_PAIR1+
DDI2_PAIR1DDI2_PAIR2+
DDI2_PAIR2DDI2_PAIR3+
DDI2_PAIR3-
D39
D40
D42
D43
D46
D47
D49
D50
Digital Display Interface2 differential pairs
O PCIE
DDI2_HPD
D44
DDI2_CTRLCLK_AUX+
C32
PU/PD
I 3.3V
PD 100K
IF DDI2_DDC_AUX_SEL is floating
I/O PCIE
PD 100K
IF DDI2_DDC_AUX_SEL pulled high
I/O OD 3.3V
IF DDI2_DDC_AUX_SEL is floating
I/O PCIE
IF DDI2_DDC_AUX_SEL pulled high
I/O OD 3.3V
C34
Selects the function of DDI2_CTRLCLK_AUX+ and
DDI2_CTRLDATA_AUX-. This pin shall have a 1M
pull-down to logic ground on the Module. If this input
is floating the AUX pair is used for the DP AUX+/signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
I 3.3V
Signal
Pin
Description
I/O
DDI3_PAIR0+
DDI3_PAIR0DDI3_PAIR1+
DDI3_PAIR1DDI3_PAIR2+
DDI3_PAIR2DDI3_PAIR3+
DDI3_PAIR3-
C39
C40
C42
C43
C46
C47
C49
C50
Digital Display Interface3 differential pairs
O PCIE
DDI3_HPD
C44
DDI3_CTRLCLK_AUX+
C36
DDI2_CTRLCLK_AUX-
DDI2_DDC_AUX_SEL
C33
Comment
DP2_AUX+
HDMI2_CTRLCLK
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PU 100K
3.3V
DP2_AUXHDMI2_CTRLDATA
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PD 1M
DDI 3
DDI3_CTRLCLK_AUX-
DDI3_DDC_AUX_SEL
Page 30
C37
C38
PU/PD
I 3.3V
PD 100K
IF DDI3_DDC_AUX_SEL is floating
I/O PCIE
PD 100K
IF DDI3_DDC_AUX_SEL pulled high
I/O OD 3.3V
IF DDI3_DDC_AUX_SEL is floating
I/O PCIE
IF DDI3_DDC_AUX_SEL pulled high
I/O OD 3.3V
Selects the function of DDI3_CTRLCLK_AUX+
and DDI3_CTRLDATA_AUX-. This pin shall
have a 1M pull-down to logic ground on the
Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high
the AUX pair contains the CRTLCLK and
CTRLDATA signals.
I 3.3V
Comment
DP2_AUX+
HDMI2_CTRLCLK
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PU 100K
3.3V
DP2_AUXHDMI2_CTRLDATA
PU 2.2K 3.3V when
DDC_AUX_SEL is high
PD 1M
Express-SL/SLE
3.4.4.
DDI to DP/HDMI Mapping
Pin
Pin Name
DP
HDMI \ DVI
D26
DDI1_PAIR0+
DP1_LANE0+
TMDS1_DATA2+
D27
DDI1_PAIR0-
DP1_LANE0-
TMDS1_DATA2-
D29
DDI1_PAIR1+
DP1_LANE1+
TMDS1_DATA1+
D30
DDI1_PAIR1-
DP1_LANE1-
TMDS1_DATA1-
D32
DDI1_PAIR2+
DP1_LANE2+
TMDS1_DATA0+
D33
DDI1_PAIR2-
DP1_LANE2-
TMDS1_DATA0-
D36
DDI1_PAIR3+
DP1_LANE3+
TMDS1_CLK+
D37
DDI1_PAIR3-
DP1_LANE3-
TMDS1_CLK-
C25
DDI1_PAIR4+
C26
DDI1_PAIR4-
C29
DDI1_PAIR5+
C30
DDI1_PAIR5-
C15
DDI1_PAIR6+
C16
DDI1_PAIR6-
C24
DDI1_HPD
DP1_HPD
HDMI1_HPD
D15
DDI1_CTRLCLK_AUX+
DP1_AUX+
HMDI1_CTRLCLK
D16
DDI1_CTRLDATA_AUX-
DP1_AUX-
HMDI1_CTRLDATA
D34
DDI1_DDC_AUX_SEL
D39
DDI2_PAIR0+
DP2_LANE0+
TMDS2_DATA2+
D40
DDI2_PAIR0-
DP2_LANE0-
TMDS2_DATA2-
D42
DDI2_PAIR1+
DP2_LANE1+
TMDS2_DATA1+
D43
DDI2_PAIR1-
DP2_LANE1-
TMDS2_DATA1-
D46
DDI2_PAIR2+
DP2_LANE2+
TMDS2_DATA0+
D47
DDI2_PAIR2-
DP2_LANE2-
TMDS2_DATA0-
D49
DDI2_PAIR3+
DP2_LANE3+
TMDS2_CLK+
D50
DDI2_PAIR3-
DP2_LANE3-
TMDS2_CLK-
D44
DDI2_HPD
DP2_HPD
HDMI2_HPD
C32
DDI2_CTRLCLK_AUX+
DP2_AUX+
HDMI2_CTRLCLK
C33
DDI2_CTRLDATA_AUX-
DP2_AUX-
HDMI2_CTRLDATA
C34
DDI2_DDC_AUX_SEL
C39
DDI3_PAIR0+
DP3_LANE0+
TMDS3_DATA2+
C40
DDI3_PAIR0-
DP3_LANE0-
TMDS3_DATA2-
C42
DDI3_PAIR1+
DP3_LANE1+
TMDS3_DATA1+
C43
DDI3_PAIR1-
DP3_LANE1-
TMDS3_DATA1-
C46
DDI3_PAIR2+
DP3_LANE2+
TMDS3_DATA0+
C47
DDI3_PAIR2-
DP3_LANE2-
TMDS3_DATA0-
C49
DDI3_PAIR3+
DP3_LANE3+
TMDS3_CLK+
C50
DDI3_PAIR3-
DP3_LANE3-
TMDS3_CLK-
C44
DDI3_HPD
DP3_HPD
HDMI3_HPD
C36
DDI3_CTRLCLK_AUX+
DP3_AUX+
HDMI3_CTRLCLK
C37
DDI3_CTRLDATA_AUX-
DP3_AUX-
HDMI3_CTRLDATA
C38
DDI3_DDC_AUX_SEL
Express-SL/SLE
Page 31
3.4.5.
PCI Express Graphics x16 (PEG)
Signal
Pin
Description
I/O
PEG_RX0+
PEG_RX0PEG_RX1+
PEG_RX1PEG_RX2+
PEG_RX2PEG_RX3+
PEG_RX3PEG_RX4+
PEG_RX4PEG_RX5+
PEG_RX5PEG_RX6+
PEG_RX6PEG_RX7+
PEG_RX7PEG_RX8+
PEG_RX8PEG_RX9+
PEG_RX9PEG_RX10+
PEG_RX10PEG_RX11+
PEG_RX11PEG_RX12+
PEG_RX12PEG_RX13+
PEG_RX13PEG_RX14+
PEG_RX14PEG_RX15+
PEG_RX15
PEG_TX0+
PEG_TX0PEG_TX1+
PEG_TX1PEG_TX2+
PEG_TX2PEG_TX3+
PEG_TX3PEG_TX4+
PEG_TX4PEG_TX5+
PEG_TX5PEG_TX6+
PEG_TX6PEG_TX7+
PEG_TX7PEG_TX8+
PEG_TX8PEG_TX9+
PEG_TX9PEG_TX10+
PEG_TX10PEG_TX11+
PEG_TX11PEG_TX12+
PEG_TX12PEG_TX13+
PEG_TX13PEG_TX14+
PEG_TX14PEG_TX15+
PEG_TX15PEG_LANE_RV#
C52
C53
C55
C56
C58
C59
C61
C62
C65
C66
C68
C69
C71
C72
C74
C75
C78
C79
C81
C82
C85
C86
C88
C89
C91
C92
C94
C95
C98
C99
C101
C102
D52
D53
D55
D56
D58
D57
D61
D62
D65
D66
D68
D69
D71
D72
D74
D75
D78
D79
D81
D82
D85
D86
D88
D89
D91
D92
D94
D95
D98
D99
D101
D102
D54
PCI Express Graphics transmit differential pairs.
I PCIE
AC couple off module
PCI Express Graphics receive differential pairs.
O PCIE
AC couple on module
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order.
I 3.3V
Page 32
PU/PD
Comment
PU 10K 3.3V
Express-SL/SLE
3.4.6.
Module Type Definition
Signal
Pin #
Description
TYPE0#
TYPE1#
TYPE2#
C54
C57
D57
The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on
the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are don’t care (X).
TYPE2# TYPE1# TYPE0#
X
X
X
Pinout Type 1
NC
NC
NC
Pinout Type 2
NC
NC
GND
Pinout Type 3 (no IDE)
NC
GND
NC
Pinout Type 4 (no PCI)
NC
GND
GND
Pinout Type 5 (no IDE, no PCI)
GND
NC
NC
Pinout Type 6 (no IDE, no PCI)
The Carrier Board should implement combinatorial logic that monitors the module
TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power
supply) if an incompatible module pin-out type is detected. The Carrier Board logic
may also implement a fault indicator such as an LED.
3.4.7.
I/O
Comment
Type 6
Power and Ground
Signal
Pin #
Description
I/O
VCC_12V
C104-C109
D104-D109
Primary power input: +12V nominal (wide range 5 ~ 20V).
All available VCC_12V pins on the connector(s) shall be used
P
GND
C1, C11, C21, C31, C41,
C51, C60, C70, C76, C80,
C84, C87, C90, C93, C96,
C100, C103, C110, D1,
D11, D21, D31, D41, D51,
D60, D67, D70, D76, D80,
D84, D87, D90, D93, D96,
D100, D103, D110
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to carrier
board GND plane.
P
Express-SL/SLE
PU/PD
Comment
8.5 ~ 20V
Page 33
4. Module Interfaces and Configuration
This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the standard PICMG
specification.
4.1.
Connector, Switch and LED Locations
BIOS
Defaults
Reset
Switch
CD
AB
Fan
4-pin
Fan
4.1.1.
40-pin MultiPurpose
Express-SL/SLE and the DB40 Module connected
For illustration purposes only.
Page 34
Express-SL/SLE
4.2.
40-pin Multipurpose Connector
¾
FPC Connector type: FCI 59GF Flex 10042867
¾
Pin Orientation:
1
40
Pin Definitions (on COMe module)
¾
Pin
Interface
Signal
Remark
Pin
Interface
Signal
1
SPI
Program
interface
VCC_SPI_IN
SPI Power Input from flash tool to
module. HW need add MOS FET
to switch SPI power for SPI ROM
21
BMC Program
interface
(continued)
TXD6
Remark
2
GND
22
RXD6
3
SPI_BIOS_CS0#
23
FUMD0
4
SPI_BIOS_CS1#
24
RESET_IN#
5
SPI_BIOS_MISO
25
DATA
6
SPI_BIOS_MOSI
26
CLK
7
SPI_BIOS_CLK
27
OCD0A
Include a jumper to connect
OCD0A via 1K0 pull-up to
3.3V_BMC
28
OCD0B
Include a jumper to connect
OCD0A via 1K0 pull-up to
3.3V_BMC
8
LPC Bus
3V3_LPC
System power 3.3V provide from
COM module
Test points
9
GND
29
10
BIOS_DIS0
30
SYS_RESET#
11
RST#
31
CB_RESET#
12
CLK33_LPC
32
CB_PWROK
13
LPC_FRAME#
33
SUS_S3#
14
LPC_AD3
34
SUS_S4#
15
LPC_AD2
35
SUS_S5#
16
LPC_AD1
17
LPC_AD0
18
19
BMC
Program
interface
20
always power 3.3V provide from
COM module
36
BMC Debug
signals
PWRBTN#
POSTWDT_DIS# Connect to Jumper for
Debug
37
SEL_BIOS
Connect to Jumper for
Debug
Connect to Jumper for
Debug
3.3V_BMC
always power 3.3V provide from
COM module
38
BIOS_MODE
3.3V_BMC
always power 3.3V provide from
COM module
39
BMC_STATUS
GND
40
Reserved
Note: The pin description on the Debug Module is the inverse of that on the COM Express module.
Express-SL/SLE
Page 35
4.3.
Status LEDs
To facilitate easier maintenance, status LED’s are mounted on the board.
LED1 LED2 LED3
¾
LED Descriptions:
Name
Color
Connection
Function
LED1
Blue
BMC output
Power Sequence Status Code (BMC)
Power Changes, RESET
(see 5.1.4 Exception Codes below)
LED2
Green
Power Source 3Vcc
S0
S3/S4/S5
ECO mode
LED ON
LED OFF
LED OFF
LED3
Red
BMC output
Module power up
Watchdog counting
Watchdog timed out
Watchdog RESET
Rebooted after WD RESET
Rebooted after PWRBTN
Rebooted after RESET BTN
LED OFF
Keep last state
LED ON
LED ON
LED ON
LED OFF
LED OFF
and same signal as WDT
(B27) on BtB connector
Note: only a RESET not initiated by the BMC can clear the WD LED (user action)
Page 36
Express-SL/SLE
4.4.
Fan Connector
¾
Connector Type: JVE 24W1125A-04M00
¾
Pin Orientation:
1 2 3 4
Pin Definitions:
¾
Pin
Signal
1
FAN_PWMOUT
2
FAN_TACHIN
3
Ground
4
5V
Express-SL/SLE
Page 37
4.5.
BIOS Setup Defaults Reset Button
To perform a hardware reset of BIOS default settings, perform the following steps:
1.
Shut down the system.
2.
Press the BIOS Setup Defaults Reset Button continuously and boot up the system. You can release the button when the BIOS
prompt screen appears
3.
The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.
Page 38
Express-SL/SLE
4.6.
Express-SL/SLE Switch Settings
4.6.1.
Switch Locations
SW2
SW1
Express-SL/SLE
Page 39
4.6.2.
SW1: PCI Express Configuration Switch.
Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4.
Mode
Pin 1
Pin 2
1x PCIe x16 (default)
Off
Off
2x PCIe x8
On
Off
1x PCIe x8 + 2x PCIe x4
On
On
Reserved
Off
On
4.6.3.
SW2: BIOS Select and Mode Configuration Switch
The module has two BIOS chips and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using SW1, Pin 2.
Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be
placed in the SPI0 slot on the carrier.
In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any
given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In
Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.
In either mode, SW1 Pin 1 is used to select whether to boot from SPI0 or SPI1.
Mode
Pin 1
Pin 2
Boot from SPI0 (default)
On
—
Boot from SPI1
Off
—
Set BIOS to PICMG mode
—
On
Set BIOS to Failsafe BIOS mode (default)
—
Off
Page 40
Express-SL/SLE
4.7.
PCIe x16-to-two-x8 Adapter Card
The Express-BE can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE6 Reference Carrier to support bifurbication of
the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards
with x8/x4/x2/x1 width. To use the card, set BIOS > Advanced > Graphics > GFX LINK CFG to "2 x8 " as described in Error! Reference
source not found. .Error! Reference source not found. on page Error! Bookmark not defined..
PCIex16-to-two-x8 Adapter Card
(Model: P16TO28, Part No.: 91-79301-0010)
Express-SL/SLE
Page 41
5. Smart Embedded Management Agent (SEMA)
The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality.
The microcontroller communicates via the System Management Bus with the CPU/chipset.
The following functions are implemented
¾
Total operating hours counter counts the number of hours the module has been run in minutes.
¾
On-time minutes counter counts the seconds since last system start.
¾
Temperature monitoring of CPU and board temperature minimum and maximum temperature values of CPU and board are stored in
flash.
¾
Power cycles counter
¾
Boot counter counts the number of boot attempts.
¾
Watchdog Timer (Type-II) Set, Reset, Disable Watchdog Timer. Features auto-reload at power-up.
¾
System Restart Cause Power loss, BIOS Fail, Watchdog, Internal Reset, External Reset
¾
Fail-safe BIOS support In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS.
¾
Flash area 1kB Flash area for customer data
¾
128 Bytes Protected Flash area Keys, IDs, etc. can be stored in a write- and clear-protectable region.
¾
Board Identify Vendor, Board, Serial number, Production Date
¾
Main-current & voltage monitors drawn current and main voltages
For a detailed description of SEMA features and functionality, please refer to the SEMA Technical Manual and SEMA Software Manual,
downloadable at: http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1274
Page 42
Express-SL/SLE
5.1.
Board Specific SEMA Functions
5.1.1.
Voltages
The BMC of the Express-BL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the
SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).
5.1.2.
ADC Channel
Voltage Name
Voltage Formula [V]
0
Not used
1
+V3.3V
(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
2
+V1.05S
(MSB<<8 + LSB) x 3.3 / 1024
3
+V3.3V
(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
4
+VMEM
(MSB<<8 + LSB) x 3.3 / 1024
5
+V5.0V
(MSB<<8 + LSB) x 1.833 x 3.3 / 1024
6
+VIN
(MSB<<8 + LSB) x 6.000 x 3.3 / 1024
7
(MAIN CURRENT)
Use Main Current Function
Main Current
The BMC of the Express-BL implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The
function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the
board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the
drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.
Main Current = (MSB_n<<8 + LSB_n) x 8.06mA
5.1.3.
BMC Status
This register shows the status of BMC controlled signals on the Express-BL.
Express-SL/SLE
Status Bit
Signal
0
WDT_OUT
1
LVDS_VDDEN
2
Reserved
3
BIOS_MODE
4
POSTWDT_DISn
5
SEL_BIOS
6
BIOS_DIS0n
7
BIOS_DIS1n
Page 43
5.1.4.
Exception Codes
In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags
register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception
Code” command is not needed or supported.
5.1.5.
Exception Code
Error Message
0
NOERROR
2
NO_SUSCLK
3
NO_SLP_S5
4
NO_SLP_S4
5
NO_SLP_S3
6
NO_CB_PWRGD
7
BIOS_FAIL
8
RESET_FAIL
9
RESETIN_FAIL
10
CRITICAL_TEMP
11
POWER FAIL
12
VOLTAGE_FAIL
13
NO_SYS_GD
14
NO_3V3_A_PGD
15
NO_VDDQ_PG
16
NO_P_5V_3V3_S0_PG
17
NO_1V0_A_PG
18
NO_VCORE_PG
19
MEMORY_ERROR
BMC Flags
The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.
Page 44
Bit
Description
[0~4]
Exception Code
[6]
0 = AT mode
1 = ATX mode
[7]
0 = Standard BIOS
1 = Fail-safe BIOS.
Express-SL/SLE
6. System Resources
6.1.
System Memory Map
Address Range (decimal)
Address Range (hex)
Size
Description
(4GB-2MB)
FFE00000 – FFFFFFFF
2 MB
High BIOS Area
(4GB-18MB) – (4GB-17MB-1)
FEE00000 – FEEFFFFF
1 MB
MSI Interrupts
(4GB-20MB) – (4GB-19MB-1)
FEC00000 – FECFFFFF
1 MB
APIC Configuration Space
15MB – 16MB
F00000 – FFFFFF
1 MB
ISA Hole
1MB -15MB
100000 - EFFFFF
14 MB
Main Memory
0K –1MB
00000 – FFFFFF
1 MB
DOS Compatibility Memory
6.2.
Direct Memory Access Channels
Channel Number
Data Width
System Resource
0
8-bits
Generic
1
8-bits
Generic
2
8-bits
Generic
3
8-bits
Generic
4
Reserved - cascade channel
5
16-bits
Generic
6
16-bits
Generic
7
16-bits
Generic
Express-SL/SLE
Page 45
6.3.
I/O Map
Hex Range
Device
000-01F
DMA Controller
020-02D and 030-03F
Interrupt controller 1, 8259 equivalent
02E-02F
LPC SIO () configuration index/data registers
040-043
Timer, 8254-2 equivalent
04e-04f
LPC SIO () configuration index/data registers
050-053
Timer, 8254-2 equivalent
060, 064,
8742 equivalent (keyboard)
061
NMI control and status
070-077
Real Time Clock Controller( bit 7 -NMI mask)
080-090
DMA Controller and LPC,PCI, or PCIe
092
Reset (Bit 0)/ Fast Gate A20 (Bit 1)
091,93-9F
DMA Controller
0A0-0B1 and 0B4-0BD
Interrupt controller 2, 8259 equivalent
0B2 and 0B3
APM control and status port respectively
0C0-0DF
DMA Controller
0E0-0EF
N/A
0F0
Co-processor error register
0F1-0FF
N/A
100-169
N/A
170-177
Sata Controller
178-1EF
N/A
1F0-1F7
Sata Controller
1F8-2DF
N/A
2E0 -2F7
Serial Port 3/4
2F8-2FF
Serial Port 2
300-36F
Available
376
Sata Controller
378-37F
Available
380-3AF
Available
3B0-3BB and 3BF
Mono/VGA mode video
3BC-3BE
Reserved for parallel port
3C0-3DF
VGA registers
3E0-3EF
Available
3F0-3F5
Available
3F6
Sata Controller
3F7
Available
3F8-3FF
Serial port 1
Page 46
Express-SL/SLE
Hex Range
Device
4D0,4D1
Interrupt controller
CF8-CFB
PCI configuration address register (32 bit I/O only)
CF9
Reset Control register (8 bit I/O)
CFC-CFF
PCI configuration data register
F040
Smbus base address for SB.
1C00
GPIO Base Address for SB
1800
PM (ACPI) Base Address for SB
1860
Alias for ICH TCO base address.
0A00~0AFF
Reserved for SIO functions base address (ex: PME /GPIO etc)
6.4.
Interrupt Request (IRQ) Lines
6.4.1.
PIC Mode
IRQ#
Typical Intterupt Resource
Connected to Pin
Available
0
Counter 0
N/A
No
1
Keyboard controller
IRQ1 via SERIRQ
No
2
Cascade interrupt from slave PIC
N/A
No
3
Serial Port 2 (COM2)
IRQ3 via SERIRQ / PIRQ
Note (1)
4
Serial Port 1 (COM1)
IRQ4 via SERIRQ / PIRQ
Note (1)
5
Generic
IRQ5 via SERIRQ / PIRQ
Note (1)
6
Generic
IRQ6 via SERIRQ / PIRQ
No
7
Generic
IRQ7 via SERIRQ / PIRQ
Note (1)
8
Real-time clock
N/A
No
9
Generic
N/A
Note (1)
10
Serial Port 3 (COM3)
IRQ10 via SERIRQ / PIRQ
Note (1)
11
Serial Port 4 (COM4)
IRQ11 via SERIRQ / PIRQ
Note (1)
12
PS/2 Mouse
IRQ12 via SERIRQ / PIRQ
Note (1)
13
FERR# logic
N/A
No
14
SATA Primary
IRQ14 via SERIRQ / PIRQ
Note (1)
15
SATA Secondary
IRQ15 via SERIRQ / PIRQ
Note (1)
Note (1): These IRQs can be used for PCI devices when onboard device is disabled.
Express-SL/SLE
Page 47
6.4.2.
APIC Mode
IRQ#
Typical Intterupt Resource
Connected to Pin
Available
0
Counter 0
N/A
No
1
Keyboard controller
IRQ1 via SERIRQ
No
2
Cascade interrupt from slave PIC
N/A
No
3
Serial Port 2 (COM2)
IRQ3 via SERIRQ
Note (1)
4
Serial Port 1 (COM1
IRQ4 via SERIRQ
Note (1)
5
N/A
N/A
Note (1)
6
N/A
N/A
Note (1)
7
N/A
N/A
Note (1)
8
Real-time clock
N/A
No
9
N/A
IRQ9 via SERIRQ
Note (1)
10
Serial Port 3 (COM3)
IRQ10 via SERIRQ
Note (1)
11
Serial Port 4 (COM4)
IRQ11 via SERIRQ
Note (1)
12
PS/2 Mouse
IRQ12 via SERIRQ
Note (1)
13
FERR# logic
N/A
Note (1)
14
SATA Primary
IRQ14 via SERIRQ
Note (1)
15
SATA Secondary
IRQ15 via SERIRQ
Note (1)
16
N/A
P.E.G Root Port,Intel HDA, PCIE Port
0/1/2/3/4/5/6,I.G.D ,XHCI Controller
Note (1)
17
N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,
Note (1)
18
N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus
Controller
Note (1)
19
N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,
Note (1)
20
N/A
Gbe Controller
Note (1)
21
N/A
N/A
Note (1)
22
N/A
Intel HDA
Note (1)
23
N/A
N/A
Note (1)
Note (1): These IRQs can be used for PCI devices when onboard device is disabled.
Page 48
Express-SL/SLE
6.5.
PCI Configuration Space Map
Bus Number Device Number
Function Number Routing
Description
00h
00h
00h
N/A
Intel host Bridge
00h
02h
00h
Internal
Intel I.G.D
00h
08h
00h
Internal
Gaussian Mixture Model
00h
14h
00h
Internal
xHCI Controller
00h
16h
00h
Internal
Intel Management Engine Interface
00h
17h
00h
Internal
Intel AHCI controller
00h
1Ch
00h
Internal
Intel PCI Express Root port 1
00h
1Ch
01h
Internal
Intel PCI Express Root port 2
00h
1Ch
02h
Internal
Intel PCI Express Root port 3
00h
1Ch
03h
Internal
Intel PCI Express Root port 4
00h
1Ch
05h
Internal
Intel PCI Express Root port 6
00h
1Ch
06h
Internal
Intel PCI Express Root port 7
00h
1Fh
00h
N/A
Intel LPC Interface Bridge
00h
1Fh
02h
Internal
Memory Controller
00h
1Fh
03h
Internal
HDA Controller
00h
1Fh
04h
Internal
SMBUS Controller
00h
1Fh
06h
Internal
Ethernet Controller
Express-SL/SLE
Page 49
6.6.
INT
Line
PCI Interrupt Routing Map
P.E.G Root
Port
xHCI
Controller
ME
Controller #1
GbE
Controller
HD Audio
Controller
Int0
INTA:16
Int1
INTB:17
INTD:19
Int2
INTC:18
INTC:18
Int3
INTD:19
INT
Line
PCIE
Port1
PCIE
Port 2
PCIE
Port 3
PCIE
Port 4
PCIE
Port 5
PCIE
Port 6
PCIE
Port 7
PCIE
Port 8
Int0
INTA:16
INTB:17
INTC:18
INTD:19
INTA:16
INTB:17
INTC:18
INTD:19
Int1
INTB:17
INTC:18
INTD:19
INTA:16
INTB:17
INTC:18
INTD:19
INTA:16
Int2
INTC:18
INTD:19
INTA:16
INTB:17
INTC:18
INTD:19
INTA:16
INTB:17
Int3
INTD:19
INTA:16
INTB:17
INTC:18
INTD:19
INTA:16
INTB:17
INTC:18
INT
Line
INTA:16
Int1
INTB:17
Int2
INTC:18
Int3
INTD:19
INTA:16
INTD:19
LPC
SATA
Controller Controller
Int0
6.7.
INTA:16
INTA:16
INTA:16
INTA:16
INTB:17
SMBus
Controller
Thermal
Subsystem
INTA:16
INTC:18
SMBus Address Table
Device
Address
DIMMA
A0h
DIMMB
A4h
BMC
50h
Extend GPIO
40h
NXP
C0h
(eDP to LVDS transmitter)
Page 50
Express-SL/SLE
7. BIOS Setup
7.1.
Menu Structure
This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the
BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting
options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
Main
Advanced
- System Information
- CPU
- Processor Information
- PCH Information
- System
Management
- System Date
- System Time
►
Security
Boot
►
- Password Description ►
- Boot Configuration ► - Reset Options
►
- Memory
►
- Secure Boot Menu
- CSM Configuration ► - Save Options
►
- Graphics
►
- SATA
►
- USB
►
- Network
►
- PCI and PCIe
►
- Super IO
►
►
Save & Exit
- ACPI and
►
Power Management
Express-SL/SLE
- Sound
►
- Serial Port
Console
►
- ICC
►
- Thermal
►
- Miscellaneous
►
Page 51
7.2.
Main
The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer
to the tables below the screen shot of this menu for details of the submenus and settings.
7.2.1.
System Information
Feature
Options
Description
BIOS Version
Info only
ADLINK BIOS version.
Board Revision
Info only
Hardware revision.
Build Date and Time
Info only
ADLINK date the BIOS was build.
7.2.2.
Processor Information
Feature
Options
Description
CPU Brand String
Info only
Display CPU Brand Name.
Frequency
Info only
Display CPU Frequency.
Processor ID
Info only
Display CPU ID.
Stepping
Info only
Display CPU Stepping.
Number of Processors
Info only
Display number of Processors.
GT Info
Info only
Display GT info of Intel Graphics.
IGFX VBIOS Version
Info only
Display VBIOS Version.
Total Memory
Info only
Display installed memory size.
Feature
Options
Description
PCH Name
Info only
Display PCH name.
PCH SKU
Info only
Display PCH SKU.
Stepping
Info only
Display PCH stepping.
ME FW Version
Info only
Display version of ME.
ME Firmware SKU
Info only
Display ME Firmware Kit SKU number.
System Management
Submenu
7.2.3.
PCH Information
7.2.3.1.
PCH Information System Management
Feature
Options
System Management
Info only
Version
Page 52
Info only
Description
Display version.
Express-SL/SLE
7.2.4.
System Management
7.2.4.1.
System Management > Board Information
Board Information
Info only
Description
SMC Firmware
Read only
Display SMC Firmware.
Read only
Display SMC firmware build date.
Read only
Display SMC boot loader.
Read only
Display SMC boot loader build date.
Hardware Version
Read only
Display SMC hardware Version.
Serial Number
Read only
Display SMC serial Number.
Manufacturing Date
Read only
Display SMC manufacturing date.
Last Repair Date
Read only
Display SMC last repair date.
MAC ID
Read only
Display SMC MAC ID
Build Date
SMC Boot loader
Build Date
7.2.4.2.
System Management > Temperatures and Fan Speed
Feature
Options
Temperatures and Fan
Info only
CPU Temperature
Info only
Current
Read only
Display CPU current temperature.
Startup
Read only
Display CPU startup temperature.
Min
Read only
Display CPU min temperature.
Max
Read only
Display CPU max temperature.
Board Temperatures
7.2.4.3.
Description
Info only
Current
Read only
Display board current temperature.
Startup
Read only
Display board startup temperature.
Min
Read only
Display board min temperature.
Max
Read only
Display board max temperature.
CPU Fan Speed
Read only
Display CPU fan speed.
System Fan Speed
Read only
Display system fan speed.
System Management > Power Consumption
Feature
Options
Power Consumption
Info only
Description
Current Input Current
Read only
Display input current.
Current Input Power
Read only
Display input power.
V3.30
Read only
Display actual voltage of the V3.30.
Express-SL/SLE
Page 53
Feature
7.2.4.4.
Options
Description
V1.05
Read only
Display actual voltage of the V1.05.
Vtt
Read only
Display actual voltage of the VTT.
V1.35
Read only
Display actual voltage of the V1.35.
V5.00
Read only
Display actual voltage of the V5.00.
V3.30
Read only
Display actual voltage of the V3.30.
AIN7
Read only
Display actual voltage of the AIN7.
System Management > Runtime Statistics
Feature
Options
Runtime Statistics
Info only
7.2.4.5.
Total Runtime
Read only
The returned value specifies the total time in minutes the system
is running in S0 state.
Current Runtime
Read only
The returned value specifies the time in seconds the system is
running in S0 state.
This counter is cleared when the system is removed from the
external power supply.
Power Cycles
Read only
The returned value specifies the number of times the external
power supply has been shut down
Boot Cycles
Read only
The Bootcounter is increased after a HW- or SW-Reset or after a
successful power-up.
Boot Reason
Read only
The boot reason is the event which causes the reboot of the
system.
System Management > Flags
Feature
Options
Flags
Info only
BMC Flags
Page 54
Description
Description
Read only
BIOS Select
Read only
Display the selection of current BIOS ROM.
ATX/AT-Mode
Read only
Display ATX/AT-Mode.
Exception Code
Read only
System exception reason.
Express-SL/SLE
7.2.4.6.
System Management > Power Up
Feature
Options
Power Up
Info only
Power Up watchdog
Attention: F12 disables the Power Up
Watchdog.
Enabled
Disabled
The Power-Up Watchdog resets the system after a certain
amount of time after power-up.
Disabled
Enable
Reduces the power consumption of the system.
Turn on
Remain off
Last State
Turn On: The machine starts automatically when the power
supply is turned on.
Remain Off :To start the machine the power button has to be
pressed.
Last State: when powered on during a power failure the system
will automatically power on when power is restored
ECO Mode
Power-up Mode
Attention: The Power-Up Mode only has effect,
if the module is in ATX-Mode.
7.2.4.7.
System Management > LVDS Backlight
Feature
Options
LVDS Backlight
Info only
LVDS Backlight Bright
7.2.4.8.
Description
255
Description
The value range starts by 0 and ends by 255.
System Management > Smart Fan
Feature
Options
Smart Fan
Info only
Description
CPU Smart FanTemperature Source
CPU Sensor
System Sensor
Select CPU smart fan source.
CPU Fan Mode
AUTO (Smart Fan)
Fan Off
Fan On
Select CPU Fan Mode.
CPU Trigger Point 1
Read only
Trigger Temperature
15
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
PWM Level
30
Select PWM level.
CPU Trigger Point 2
Trigger Temperature
60
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
PWM Level
40
Select PWM level.
CPU Trigger Point 3
Read only
Trigger Temperature
70
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
PWM Level
63
Select PWM level.
CPU Trigger Point 4
Express-SL/SLE
Read only
Read only
Trigger Temperature
80
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
PWM Level
100
Select PWM level.
Page 55
7.2.5.
System Date and Time
Feature
Options
Description
System Date
Weekday, MM/DD/YYYY
Requires the alpha-numeric entry of the day of the week, day of the
month, calendar month, and all 4 digits of the year, indicating the
century and year (Fri XX/XX/20XX)
System Time
HH/MM/SS
Presented as a 24-hour clock setting in hours, minutes, and seconds
Page 56
Express-SL/SLE
7.3.
Advanced
This menu contains the settings for most of the user interfaces in the system
7.3.1.
CPU
Feature
Options
Description
CPU
Info only
Manufacturer, model, speed
CPU Signature
Info only
Display CPU Signature.
Processor Family
Info only
Display Processor Family.
Microcode Patch
Info only
Display Microcode Patch.
Max CPU speed
Info only
Display Max CPU speed.
Min CPU speed
Info only
Display Min CPU speed.
CPU Speed
Info only
Display CPU Speed.
Processor Cores
Info only
Display Processor Cores.
Intel HT Technology
Info only
Display Intel HT Technology support or not.
Intel VT-x Technology
Info only
Display Intel VT-x Technology support or not.
EIST Technology
Info only
Display EIST Technology support or not
CPU C3 state
Info only
Display CPU C3 state support or not
CPU C6 state
Info only
Display CPU C6 state support or not
CPU C7 state
Info only
Display CPU C7 state support or not
Intel SMX Technology
Info only
Display Intel SMX Technology support or not.
64-bit
Info only
Display 64-bit support or not.
L1 Data Cache
Info only
Display cache info.
L1 Code Cache
Info only
Display cache info.
L2 Cache
Info only
Display cache info.
L3 Cache
Inf o only
Display cache info.
L4 Cache
Inf o only
Display cache info.
Hyper-threading
Disabled
Enabled
VT-d
Disabled
Enabled
Check to enable VT-d function on MCH.
Intel Virtualization Technology
Disabled
Enabled
Enable/Disable support for the Intel virtualization technology.
Intel(R) SpeedStep(TM)
Disabled
Enabled
Allows more than two frequency ranges to be supported.
Turbo Mode
Disabled
Enabled
Enable/Disable turbo mode.
Configurable TDP Boot Mode
TDP Nominal
TDP Down
Disabled
Configure TDP Mode as Nominal/Down/Disabled. Disabled option will
set MSR to Nominal and MMIO to Zero.
Express-SL/SLE
Enabled for Windows XP and Linux (OS optimized for HyperThreading Technology) and Disabled for other OS (OS not optimized
for Hyper-Threading Technology). When Disabled only one thread
per enabled core is enabled.
Page 57
Feature
Options
Config TDP Lock
Disabled
Enabled
Configurable TDP Mode Lock sets the Lock bits on
TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL.
Note: When CTDP Lock is enabled Custom ConfigTDP Count will be
forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.
CPU C state
Disabled
Enabled
Enable or disable CPU C states
C-State Auto Demotion
Disabled
C1
C3
C1 and C3
Configure C-State Auto Demotion
Package C State limit
Auto
C2
C3
C6
C7
Auto
Package C State limit
Intel TXT(LT) support
Disabled
Enabled
Enables or Disables Intel(R) TXT(LT) support.
CPU DTS
Disabled
Enabled
Enable/Disable CPU DTS.
ACPI 3.0 T-state
Disabled
Enabled
Enable/Disable ACPI 3.0 T-States.
Page 58
Description
Express-SL/SLE
7.3.2.
Memory
Feature
Options
Description
Memory RC Version
Info only
Display Memory Reference Code Version.
Memory Frequency
Info only
Display Memory Frequency.
Total Memory
Info only
Display Total Memory.
VDD
Info only
Display Memory Voltage.
DIMM#0/1
Info only
Display DIMM#0/1.
Memory Timings
Info only
Display Memory timings
XMP Profile 1
Info only
Display XMP Profile 1 support or not.
XMP Profile 2
Info only
Display XMP Profile 2 support or not.
I2C Write Protect Control
Active
Write Protect
I2C write protect control
SPD Write Protect
Enabled
Disabled
Enable:Writes to SMBus slave addresses A0h - AEh are disabled.
Maximum Memory Frequency
Auto
1067
1200
1333
1400
1600
1800
1867
2000
2133
2200
2400
2600
2800
2933
3000
3200
Maximun Memory Frequency Selections in MHz
Max TOLUD
Dynamic
Maximum Value of TOLUD. Dynamic assignment would adjust
TOLUD automatically based on largest MMIO length of installed
graphic controller.
Express-SL/SLE
Page 59
7.3.3.
Graphics
Feature
Options
Graphics Configuration
Info only
IGFX VBIOS Version
Info only
Display VBIOS Version.
IGfx Frequency
Info only
Display IGfx Frequency.
Graphics Turbo IMON Current
Number entry field
Graphics turbo IMON current values supported (14-31).
Primary Display
Auto
IGFX
PEG
PCIE
Select which of IGFX/PEG/PCI Graphics device should be Primary
Display Or select SG for Switchable Gfx.
Primary PEG
Auto
PEG1
PEG2
Select PEG0/PEG1/PEG2/PEG3 Graphics device should be Primary
PEG.
Primary PCIE
Auto
PCIE1
PCIE2
PCIE3
PCIE4
PCIE5
PCIE6
PCIE7
Select PCIE0/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7
Graphics device should be Primary PCIE.
Internal Graphics
Auto
Disabled
Enable
Keep IGD enabled based on the setup options.
Aperture Size
128MB
256MB
512MB
1024MB
2048MB
4096MB
Select the Aperture Size.
DVMT Pre-Allocated
XXM
Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used
by the Internal Graphics Device.
DVMT Total Gfx Mem
XXXM
Select DVMT5.0 Total Graphic Memory size used by the Internal
Graphics Device.
Gfx Low Power Mode
Enabled
Disabled
This option is applicable for SFF only.
EDP to LVDS Bridge Configuration
Info only
Data Format and Color Depth
VESA 24 bpp
JEIDA 24 bpp
JEIDA/VESA 18 bpp
Data format and color depth select
LVDS Output Mode
Single LVDS bus
Dual LVDS bus
Single/Dual mode select
Vsync Polarity
Active High
Active Low
Vsync Polarity select
Hsync Polarity
Active High
Hsync Polarity select
Page 60
Description
Express-SL/SLE
Feature
Options
Description
Active Low
LVDS/eDP Backlight Mode
BMC Mode
GTT Mode
Select LVDS Backlight control function.
GTT LVDS/eDP Backlight Control
0%
20%
40%
60%
80%
100%
Actual backlight value in percent of the maximum setting.
DDI function choose
Display Port
HDMI
Select DDI function choose to display port or HDMI.
Primary IGFX Boot Display
VBIOS Default
Select the Video Device which will be activated during POS.
Select Secondary Display
Disabled
Select Secondary Display Device.
LCD Panel Type
VBIOS Default
640X480
800X600
1024X768
1280X1024
1400X1050
1600X1200
1366X768
1680X1050
1920X1200
1440X900
1600X900
1024X768 LVDS2
1280X800
1920X1080
2048X1536
Select LCD panel used by Internal Graphics Device by selecting the
appropriate setup item.
Active LFP
No LVDS
eDP Port-A
Select the Active LFP Configuration.
Panel Scaling
Auto
Off
Force Scaling
Select the LCD panel scaling option used by the Internal Graphics
Device.
7.3.4.
SATA
Feature
Options
Description
SATA Controller(s)
Enabled
Disabled
Enable/Disable SATA Device.
SATA Mode Selection
AHCI
RAID
Determines how SATA controller(s) operate.
SATA Speed Selection
Default
Gen1
Gen2
Gen3
Indicates the maximum speed the SATA controller can support.
SATA Test Mode
Enabled
Disabled
Test Mode Enable/Disable (Loop Back)
Express-SL/SLE
Page 61
Feature
Options
Description
Aggressive LPM Support
Enabled
Disabled
Enable PCH to aggressively enter link power state.
SATA Port Configuration
Submenu
Software Feature Mask Configuration
Info only
RAID0
Enabled
Disabled
Enable/Disable RAID0 feature.
RAID1
Enabled
Disabled
Enable/Disable RAID1 feature.
RAID10
Enabled
Disabled
Enable/Disable RAID10 feature.
RAID5
Enabled
Disabled
Enable/Disable RAID5 feature.
Intel Rapid Recovery Technology
Enabled
Disabled
Enable/Disable Intel Rapid Recovery Technology.
OROM UI and BANNER
Enabled
Disabled
If enabled, then the OROM UI is shown. Otherwise, no OROM
banner or information will be displayed if all disks and RAID volumes
are Normal.
HDD Unlock
Enabled
Disabled
If enabled, indicates that the HDD password unlock in the OS is
enabled.
LED Locate
Enabled
Disabled
If enabled, indicates that the LED/SGPIO hardware is attached and
ping to locate feature is enabled on the OS.
IRRT Only on ESATA
Enabled
Disabled
If enabled, then only IRRT volumes can span internal and eSATA
drives. If disabled, then any RAID volume can span internal and
eSATA drives.
Smart Response Technology
Enabled
Disabled
Enable/Disable Smart Response Technology.
OROM UI Delay
Enabled
Disabled
If enabled, indicates the delay of the OROM UI Splash Screen in a
normal status.
RST Force Form
Enabled
Disabled
Enable/Disable Form for Intel Rapid Storage Technology.
7.3.4.1.
SATA > SATA Port Configuration
Feature
Options
SATA Port Configuration
Info only
Port X
Disabled
Enabled
Enable/Disable SATA Port.
Hot Plug
Disabled
Enabled
Designates this port as Hot Pluggable.
External SATA
Disabled
Enabled
External SATA Support.
SATA Device Type
Hard Disk Drive
Sold State Drive
Identify the SATA port is connected to Solid State Drive or Hard
Disk Drive.
Spin up Device
Disabled
Enabled
On an edge detect from 0 to 1, the PCH starts a COMRESET
initialization sequence to the device.
SATA Device Type
Hard Disk Drive
Solid State Drive
Identify the SATA port is connected to Solid State Drive or Hard
Disk Drive.
Page 62
Description
Express-SL/SLE
Feature
Options
Description
Topology
Unknown
ISATA
Direct Connect
Flex
M2
Identify the SATA Topology if it is Default, ISATA, Flex,
DirectConnect or M2.
Device Sleep
Disabled
Enabled
mSATA for RTD3
SATA DEVSLEP Idle Timeout Configuration
Disabled
Enabled
Enable/Disable SATA DTIO Configuration
7.3.5.
USB
Feature
Options
USB Configuration
Submenu
USB Module Version
Info only
USB Devices
Info only
X Drive, X Keyboards, X Mouse, X Hubs
Legacy USB Support
Enabled
Disabled
Auto
Enables legacy USB support.
Auto option disables legacy support if no USB devices are
connected.
Disable option will keep USB devices available only for EFI
applications and setup.
XHCI Hand-off
Enabled
Disabled
This is a workaround for OSes without XHCI hand-off support. The
XHCI ownership change should be claimed by the XHCI OS driver.
USB Mass Storage Driver Support
Enabled
Disabled
Enable/Disable USB Mass Storage Driver Support.
Port 60/64 Emulation
Enabled
Disabled
Enables I/O port 60h/64h emulation support. This should be enabled
for the complete USB keyboard legacy support for non-USB aware
OSes.
USB hardware delays and time-outs:
Info only
USB transfer time-out
1 sec
5 sec
10 sec
20 sec
The time-out value for Control, Bulk, and Interrupt transfers
Device reset time-out
10 sec
20 sec
30 sec
40 sec
USB mass storage device Start Unit command time-out.
Device power-up delay
Auto
Manual
Maximum time the device will take before it properly reports itself to
the Host Controller. 'Auto' uses default value: for a Root port it is 100
ms, for a Hub port the delay is taken from Hub descriptor.
Mass Storage Devices
Info only
List current USB max stroge device.
Express-SL/SLE
Description
Page 63
7.3.5.1.
USB > USB Configuration
Feature
Options
Description
USB Precondition
Disabled
Enabled
Precondition work on USB host controller and root ports for
faster enumeration.
XHCI Disable Compliance Mode
FALSE
TRUE
Options to disable Compliance Mode. Default is FALSE to not
disable Compliance Mode. Set TRUE to disable Compliance
Mode.
XDCI Support
Disabled
Enabled
Enable/Disable XDCI (USB OTG Device)
USB Port Disable Override
Disabled
Select Per-Pin
Selectively Enable/Disable the corresponding USB port from
reporting a Device Connection to the controller.
7.3.6.
Network
Feature
Options
Network Stack
Info only
Network Stack
Enabled
Disabled
Enable/Disable UEFI network stack.
PCH LAN Controller
Enabled
Disabled
Enable/Disable onboard NIC.
Wake on LAN
Enabled
Disabled
Enable/Disable integrated LAN to wake the system. (The Wake On
LAN cannot be disabled if ME is on at Sx state.
AMT Configuration
Info only
Intel AMT
Enabled
Disabled
Enable/Disable Intel (R) Active Management Technology BIOS
Extension.
BIOS Hotkey Pressed
Enabled
Disabled
Enable/Disable BIOS hotkey press.
MEBx Selection Screen
Enabled
Disabled
Enable/Disable MEBx selection screen.
Hide Un-Configure ME Confirmation
Enabled
Disabled
Hide Un-Configure ME without password Confirmation Prompt.
MEBx Debug Message Output
Enabled
Disabled
Enable MEBx debug message output.
Un-Configure ME
Enabled
Disabled
Un-Configure ME without password.
Amt Wait Timer
0
Set timer to wait before sending ASF_GET_BOOT_OPTIONS.
Disable ME
Enabled
Disabled
Set ME to Soft Temporary Disabled.
ASF
Enabled
Disabled
Enable/Disable Alert Specification Format.
Activate Remote Assistance Process
Enabled
Disabled
Trigger CIRA boot.
USB Configure
Enabled
Disabled
Enable/Disable USB Configure function.
PET Progress
Enabled
Disabled
User can Enable/Disable PET Events progress to recieve PET
events or not.
AMT CIRA Timeout
0
OEM defined timeout for MPS connection to be established. 0 - use
the default timeout value of 60 seconds. 255 - MEBX waits until the
connection succeeds.
Page 64
Description
Express-SL/SLE
Feature
Options
Description
Watchdog
Enabled
Disabled
Enable/Disable WatchDog Timer.
OS Timer
Set OS watchdog timer.
BIOS Timer
Set BIOS watchdog timer.
7.3.7.
PCI and PCIe
Feature
Options
PCI Common Settings
Info only
PCIE Ports 1-4 Configuration
4x1 Port
1x2 2x1 Port
2x2 Port
1x4 Port
Configures PCI-E Port 1-4 of PCH.
[4X1]: Port 1-4 (x1) and Port 8 (x1)
[1x2 2x1]: Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1)
[2x2]: Port 1-2 (x2) and Port 3-4 (x2)
[1x4]: Port 1 (x4), Ports 2-4 (disabled)
PCIE Ports 5-8 Configuration
4x1 Port
1x2 2x1 Port
Configures PCI-E Port 5-7 of PCH.
[4X1]:Port 5-8 (x1) and Port 8 (x1)
[1x2 2x1]: Port 5 (x2), Port 6 (disabled), Ports 7 and Port 8 (x1)
PCI Latency Timer
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Value to be programmed into PCI Latency Timer Register.
PCI-X Latency Timer
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Value to be programmed into PCI Latency Timer Register.
VGA Palette Snoop
Disabled
Enabled
Allow PCI cards that do not contain their own VGA color palette to
access the video core’s palette
PERR# Generation
Disabled
Enabled
Enables or Disables PCI Device to Generate PERR#.
SERR# Generation
Disabled
Enabled
Enables/Disables PCI Device to Generate SERR#.
PCI Express Configuration
Submenu
PEG Configuration
Submenu
Express-SL/SLE
Description
Page 65
7.3.7.1.
PCI and PCIe > PEG Configuration
Feature
Options
PEG Configuration
Info only
Description
PCI Express Clock Gating
Disabled
Enable
Enable/Disable PCI Express Clock Gating for each root port.
DMI Link ASPM Control
Disabled
Enable
ontrol of Active State Power Management on both NB side and
SB side of the DMI Link.
Port8xh Decode
Disabled
Port8xh Decode
Compliance Test Mode
Disabled
Compliance Test Mode
PCI Express Gen3 EQ Lanes
Submenu
PCI Express Root Port X
Submenu
PCI and PCIe > PCI Express Configuration > PCI Express Gen3 EQ Lanes
Feature
Options
Description
Override SW EQ settings
Disabled
Enable
Override SW EQ settings
PCI and PCIe > PCI Express Configuration > PCI Express Root Port X
Feature
Options
Description
PCI Express Root Port
Disabled
Enable
Control the PCI Express Root Port.
Unknown
x1
x4
Sata Express
M2
Identify the SATA Topology: Default, ISATA, Flex,
DirectConnect or M2.
ASPM Support
Disabled
L0s
L1
L0sL1
Auto
Set the ASPM Level.
Force L0s - Force all links to L0s State
Auto - BIOS auto configure;
Disabled - Disables ASPM
L1 Substates
Disabled
Enable
PCI Express L1 Substates settings.
URR
Disabled
Enable
Enable/Disable PCI Express Unsupported Request
Reporting.
FER
Disabled
Enable
Enable/Disable PCI Express Device Fatal Error Reporting.
NFER
Disabled
Enable
Enable/Disable PCI Express Device Non-Fatal Error
Reporting.
CER
Disabled
Enable
Enable/Disable PCI Express Device Correctable Error
Reporting.
CTO
Disabled
Enable
Enable/Disable PCI Express Completion Timer TO.
SEFE
Disabled
Enable
Enable/Disable Root PCI Express System Error on Fatal
Error.
Topology
Page 66
Express-SL/SLE
Feature
Options
Description
SENFE
Disabled
Enable
Enable/Disable Root PCI Express System Error on NonFatal Error.
SECE
Disabled
Enable
Enable/Disable Root PCI Express System Error on
Correctable Error.
PME SCI
Disabled
Enable
Enable/Disable PCI Express PME SCI.
Hot Plug
Disabled
Enable
Enable/Disable PCI Express Hot Plug.
Auto
Gen1
Gen2
Select PCI Express port speed.
Disabled
Enabled
Transmitter Half Swing Enable/Disable.
Detect Non-Compiance
Disabled
Enable
Detect Non-Compliance PCI Express Device. If enabled, it
will take more time at POST time.
Extra Bus Reserved
0
Extra Bus Reserved (0-7) for bridges behind this Root
Bridge.
Reseved Memory
10
Reserved Memory Range for this Root Bridge.
Prefetchable Memory
10
Prefetchable Memory Range for this Root Bridge.
Reserved I/O
4
Reserved I/O (4K/8K/12K/16K/.../48K) Range for this Root
Bridge.
PCIE LTR
Disabled
Enable
PCIE Latency Reporting Enable/Disable.
PCIE LTR Lock
Disabled
Enable
PCIE LTR Configuration Lock.
Snoop Latency Ocerrid
Disabled
Manual
Auto
Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerrid
Disabled
Manual
Auto
Non Snoop Latency Ocerride for PCH PCIE.
PCIe Speed
Transmitter Half Swing
7.3.7.2.
PCI and PCIe > PEG Configuration
Feature
Options
PEG Configuration
Info only
Description
PEG0
Not Present
Display PEG0 present or not.
Enable Root Port
Disabled
Enabled
Auto
Enable/Disable the Root Port.
Max Link Speed
Auto
Gen1
Gen2
Gen3
Configure 0:1:0 Max Speed
PEG0 Slot Power Limit Value
75
Sets the upper limit on power supplied by slot. Power limit (in
watts) is calculated by multiplying this value by the Slot Power
Limit Scale. Values 0-255
Express-SL/SLE
Page 67
Feature
Page 68
Options
Description
PEG0 Slot Power Limit Scale
1.0x
0.1x
0.01x
0.001x
Select the scale used for the Slot Power Limit Value.
PEG0 Physical Slot Number
1
Set the physical slot number attached to this Port. The number
has to be globally unique within the chassis. Values 0-8191
Detect Non-compliance Device
Disabled
Enable
Detect Non-Compliance PCI Express Device in PEG.
Program PCIe ASPM after OpROM
Disabled
Enabled
Enabled: PCIe ASPM will be programmed after OpROM.
Disabled: PCIe ASPM will be programmed before OpROM.
Program Static Phase1 Eq
Enabled
Disable
Program Phase1 Presets/CTLEp
Gen3 Root Port Preset Value for
each lane 0~15
7
Root Port preset value per lane for Gen3 Equalization
Gen3 Endpoint Preset value for
each Lane 0~15
7
Endpoint preset value per lane for Gen3 Equalization
Gen3 Endpoint Hint value for
each Lane 0~15
2
Endpoint Hint value per lane for Gen3 Equalization
PEG Gen3 RxCTLE Control 0~7
8
PEG Gen3 RxCTLE Control per Bundle
Always Attempt SW EQ
Disabled
Enabled
Always Attempt SW EQ, even it has been done once
Number of Presets to test
7, 3, 5
0–9
Auto
Choose between 7,3,5 and 0-9. Auto = current default for CPU
Allow PERST# GPIO Usage
Enabled
Disable
Enable/Disable GPIO-based resets to PEG endpoint(s) during
margin search, if needed
SW EQ Enable VOC
Jitter Only Test Mode
Jitter & VOC Test Mode
Auto
Select Jitter & VOC test mode (default) or Jitter only test mode.
Auto will current default (Enabled)
Jitter Dwell Time
3000
PEG Gen3 Preset Search dwell time [0..65535] in [usec]
Jitter Error Target
2
The margin search error target value [1..65535]
VOC Dwell Time
10000
The VOC margin search dwell time [0..65535] in [usec]
VOC Error Target
2
The VOC margin search error target value [1..65535]
Generate BDAT PEG Margin Data
Disabled
Enabled
Enable to generate BDAT PCIe margin tables
PCIe Rx CEM Test Mode
Disabled
Enabled
Enable/Disable PEG Rx CEM Loopback Mode
PCIe Spread Spectrum Clocking
Enabled
Disable
Allows disabling of Spread Spectrum Clocking for compliance
testing
Express-SL/SLE
7.3.8.
Super IO
Feature
Options
Super IO Chip
Info only
W83627DHG Super IO Configuration
Info only
Serial Port 1 Configuration
Serial Port
Description
Enabled
Disabled
Enable/Disable Serial Port (COM).
Device Settings
IO=3F8h; IRQ=4
Fixed configuration of serial port.
Change Settings
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Select an optimal setting for Super IO device.
Enabled
Disabled
Enable/Disable Serial Port (COM).
Device Settings
IO=2F8h; IRQ=4
Fixed configuration of serial port.
Change Settings
Auto
IO=2F8h; IRQ=3
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Select an optimal setting for Super IO device.
Device Mode
Standard Serial Port Mode
IrDA Active pulse 1.6 uS
IrDA Active pulse 3/16 bit time
ASKIR Mode
Serial Port 2 Configuration
Serial Port
N5104D Super IO Configuration
Serial Port 1 Configuration
Serial Port
Info only
Enabled
Disabled
Enable/Disable Serial Port (COM).
Device Settings
IO=240h; IRQ=10
Fixed configuration of serial port.
Change Settings
Auto
IO=240h; IRQ=10
IO=240h; IRQ=10,11,12
IO=248h; IRQ=10,11,12
IO=250h; IRQ=10,11,12
IO=258h; IRQ=10,11,12
Select an optimal setting for Super IO device.
Enabled
Disabled
Enable/Disable Serial Port (COM).
Serial Port 2 Configuration
Serial Port
Express-SL/SLE
Page 69
Feature
7.3.9.
Options
Description
Device Settings
IO=248h; IRQ=11
Fixed configuration of serial port.
Change Settings
Auto
IO=248h; IRQ=11
IO=240h; IRQ=10,11,12
IO=248h; IRQ=10,11,12
IO=250h; IRQ=10,11,12
IO=258h; IRQ=10,11,12
Select an optimal setting for Super IO device.
ACPI and Power Management
Feature
Options
Description
ACPI and Power Management
Info only
Enable ACPI Auto Configuration
Enabled
Disabled
Enables or Disables BIOS ACPI Auto Configuration.
Enable Hibernation
Enabled
Disabled
Enables or Disables System ability to Hibernate (OS/S4 Sleep
State). This option may be not effective with some OS.
ACPI Sleep State
S3 only
Select ACPI sleep state the system will enter when the SUSPEND
button is pressed.
Lock Legacy Resources
Enabled
Disabled
Enables or Disables Lock of Legacy Resources
ACPI Low Power S0 Idle
Enabled
Disabled
Enable or Disable ACPI Low Power S0 Idle Support.
Emulation AT/ATX
Emulation AT
ATX
Select Emulation AT or ATX function. If this option set to [Emulation
AT], BIOS will report no suspend functions to ACPI OS. In windows
XP, it will make OS show shutdown message during system
shutdown.
Feature
Options
Description
Sound
Info only
HD Audio
Disabled
Enabled
Auto
Control Detection of the HD-Audio device.
Disabled: HDA will be unconditionally disabled.
Enabled: HDA will be unconditionally enabled.
Auto: HDA will be enabled if present, disabled other.
Feature
Options
Description
Serial Port Console
Info only
COM1
Info only
7.3.10. Sound
7.3.11. Serial Port Console
Page 70
Console Redirection
Enabled
Disabled
Console Redirection Settings
Submenu
Console Redirection Enable or Disable.
Express-SL/SLE
Feature
Options
COM2
Info only
Console Redirection
Enabled
Disabled
Console Redirection Settings
Submenu
COM3
Description
Console Redirection Enable or Disable.
Info only
Console Redirection
Enabled
Disabled
Console Redirection Settings
Submenu
COM4
Console Redirection Enable or Disable.
Info only
Console Redirection
Enabled
Disabled
Console Redirection Settings
Submenu
7.3.11.1.
Console Redirection Enable or Disable.
Serial Port Console > Console Redirection Settings
Feature
Options
Console Redirection Settings
Info only
Terminal Type
VT100
VT100+
VT-UTF8
ANSI
Emulation: ANSI: Extended ASCII char set. VT100: ASCII char
set. VT100+: Extends VT100 to support color, function keys,
etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto
1 or more bytes.
Bits per second
9600
19200
38400
57600
115200
Selects serial port transmission speed.
Data Bits
7
8
Select Data Bits.
Parity
None
Even
Odd
Mark
Space
Select Parity.
Stop Bits
1
2
Select number of stop bits.
Flow Control
None
Hardware RTS/CTS
Select flow control.
VT-UTF8 Combo Key Support
Disabled
Enable
Enable VT-UTF8 Combination Key Support for ANSI/VT100
terminals.
Recorder Mode
Disabled
Enable
With this mode enabled only text will be sent. This is to capture
Terminal data.
Resolution 100x31
Disabled
Enable
Enables or disables extended terminal resolution
Legacy OS Redirection
80x24
80x25
On Legacy OS, the Number of Rows and Columns supported
redirection
Express-SL/SLE
Description
Page 71
Feature
Options
Description
Putty KeyPad
VT100
LINUX
XTERMR6
SCO
ESCN
VT400
Select FunctionKey and KeyPad on Putty.
Redirection After BIOS Post
Always Enabled
BootLoader
The Settings specify if BootLoader is selected than Legacy
console redirection is disabled before booting to Legacy OS.
Default value is Always Enable which means Legaacy console
Redirection is enabled for Legacy OS.
Feature
Options
Description
ICC Information
Info only
7.3.11.2.
ICC Configuration
Note1: The item is view only in standard BIOS default, the options can be opened by customer request if neccessary.
7.3.12. Thermal
Feature
Options
Thermal
Info only
Active Trip Point
Disabled
40 C
50 C
60 C
70 C
BMC Default
This value controls the temperature of the ACPI Active Trip Point the point in which the OS will turn the processor fan on Active Trip
Point Fan Speed.
Passive Trip Point
Disabled
80 C
90 C
This value controls the temperature of the ACPI Passive Trip Point the point in which the OS will begin throttling the processor.
Critical Trip Point
Disabled
85 C
95 C
This value controls the temperature of the ACPI Critical Trip Point the point in which the OS will shut the system off.
NOTE: 100C is the Plan Of Record (POR) for all Intel mobile
processors.
Watchdog ACPI Even Shutdown
Disabled
Enable
Enable/Disable Watchdog ACPI Even Shutdown.
Page 72
Description
Express-SL/SLE
7.3.13. Miscellaneous
Feature
Options
Trusted Computing
Submenu
NVME Configuration
Submenu
7.3.13.1.
Description
Miscellaneous > Trusted Computing
Feature
Options
Description
Security Device Support
Enabled
Disabled
Enables or Disables BIOS support for security device.
When disabled OS wil not show Security Device. TCG EFI
protocol and INT1A interface will not be available
TPM State
Enabled
Disabled
Enable/Disable Security Device. NOTE: Your Computer will
reboot during restart in order to change State of the Device.
Pending operation
None
TPM Clear
Schedule an Operation for the Security Device. NOTE: Your
Computer will reboot during restart in order to change State of
Security Device.
Device Start
TPM 1.2
TPM 2.0
Auto
TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will
restrict support to TPM 2.0 devices, Auto will support both with
the default set to TPM 2.0 devices if not found, TPM 1.2 devices
will be enumerated
7.3.13.2.
Miscellaneous > NVME Configuration
Feature
Options
NVME controller and Drive information
Info Only
Express-SL/SLE
Description
Page 73
7.4.
Boot
7.4.1.
Boot Configuration
Feature
Options
Boot Configuration
Info only
Setup Prompt Timeout
1
Enable/Disable the onboard SATA controllers.
Bootup NumLock State
On
Select SATA controller mode.
Quiet Boot
Disabled
Enabled
Enable/Disable the PATA port. In fact this enables or disables the
SATA channel on which the onboard SATA to PATA converter is
attached. When set to enabled the system boot will be delayed for
the time specified in PATA Port Detection Timeout if no PATA
device is connected.
Auto: Scan for PATA device and enable per default.
CSM Configuration
Submenu
Fast Boot
Disabled
Enabled
Boot Option Priorities
Info only
7.4.1.1.
Description
Define the maximum time to wait for drive detection on PATA port.
CSM Configuration
Feature
Options
Description
CSM Support
Enabled
Disable
This option controls if CSM will be launched.
CSM16 Module Version
Info only
GateA20 Active
Upon Request
Always
UPON REQUEST - GA20 can be disabled using BIOS services.
ALWAYS - do not allow disabling GA20; this option is useful when
any RT code is executed above 1MB.
Option ROM Messages
Force BIOS
Keep Current
Set display mode for Option ROM.
Boot Option filter
UEFI and Legacy
Legacy only
UEFI only
This option controls what devices system can to boot.
Option ROM execution
Info only
Network
Do not launch
Legacy only
UEFI only
Controls the execution of UEFI and Legacy PXE OpROM.
Storage
Do not launch
UEFI only
Legacy only
Controls the execution of UEFI and Legacy Storage OpROM.
Video
Do not launch
UEFI only
Legacy only
Controls the execution of UEFI and Legacy Video OpROM.
Other PCI devices
UEFI OpROM
Legacy OpROM
For PCI devices other than Network, Mass storage or Video defines
which OpROM to launch.
Page 74
Express-SL/SLE
7.5.
Security
7.5.1.
Password Description
Feature
Options
Administrator Password
Enter password
User Password
Enter password
HDD Security Configuration:
Info only
Px: xxxxxxxx
Info only
7.6.
Save & Exit
7.6.1.
Reset Options
Description
Feature
Options
Description
Save Changes and Reset
Save changes and reset the
system.
Save Changes and Reset
Discard Changes and Reset
Reset the system without
saving any changes.
Discard Changes and Reset
Options
Description
7.6.2.
Save Options
Feature
Save Changes
Save Changes done so far to any of the setup options.
Discard Changes
Discard Changes done so far to any of the setup options.
Restore Defaults
Restore/Load Default values for all the setup options.
Save as User Defaults
Save the changes done so far as User Defaults.
Restore User Defaults
Restore the User Defaults to all the setup options.
Express-SL/SLE
Page 75
8. BIOS Checkpoints, Beep Codes
This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are
inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.
Checkpoints and Beep Codes Definition
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self
Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the
preboot process.
Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been
initialized, and generated by the system board speaker.
Aptio Boot Flow
While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation
Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code &
checkpoint descriptions:
•
Security (SEC) – initial low-level initialization
•
Pre-EFI Initialization (PEI) – memory initialization1
•
Driver Execution Environment (DXE) – main hardware initialization2
•
Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network,
Shell, …)
Viewing BIOS Checkpoints
Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These
are PCI add-in cards that show the value of I/O port 80h on a LED display.
Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only
displays checkpoints that occur after the video card has been activated.
Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing
AMI Aptio BIOS checkpoints.
1Analogous
2Analogous
Page 76
to “bootblock” functionality of legacy BIOS
to “POST” functionality in legacy BIOS
Express-SL/SLE
8.1.
Status Code Ranges
Status Code
Range
Description
0x01 – 0x0F
SEC Status Codes & Errors
0x10 – 0x2F
PEI execution up to and including memory detection
0x30 – 0x4F
PEI execution after memory detection
0x50 – 0x5F
PEI errors
0x60 – 0xCF
DXE execution up to BDS
0xD0 – 0xDF
DXE errors
0xE0 – 0xE8
S3 Resume (PEI)
0xE9 – 0xEF
S3 Resume errors (PEI)
0xF0 – 0xF8
Recovery (PEI)
0xF9 – 0xFF
Recovery errors (PEI)
8.2.
Standard Status Codes
8.2.1.
SEC Status Codes
Status Code
Description
0x0
Not used
Progress Codes
0x1
Power on. Reset type detection (soft/hard).
0x2
AP initialization before microcode loading
0x3
North Bridge initialization before microcode loading
0x4
South Bridge initialization before microcode loading
0x5
OEM initialization before microcode loading
0x6
Microcode loading
0x7
AP initialization after microcode loading
0x8
North Bridge initialization after microcode loading
0x9
South Bridge initialization after microcode loading
0xA
OEM initialization after microcode loading
0xB
Cache initialization
SEC Error Codes
0xC – 0xD
Reserved for future AMI SEC error codes
0xE
Microcode not found
0xF
Microcode not loaded
Express-SL/SLE
Page 77
8.2.2.
SEC Beep Codes
None
8.2.3.
PEI Status Codes
Status Code
Description
Progress Codes
0x10
PEI Core is started
0x11
Pre-memory CPU initialization is started
0x12
Pre-memory CPU initialization (CPU module specific)
0x13
Pre-memory CPU initialization (CPU module specific)
0x14
Pre-memory CPU initialization (CPU module specific)
0x15
Pre-memory North Bridge initialization is started
0x16
Pre-Memory North Bridge initialization (North Bridge module specific)
0x17
Pre-Memory North Bridge initialization (North Bridge module specific)
0x18
Pre-Memory North Bridge initialization (North Bridge module specific)
0x19
Pre-memory South Bridge initialization is started
0x1A
Pre-memory South Bridge initialization (South Bridge module specific)
0x1B
Pre-memory South Bridge initialization (South Bridge module specific)
0x1C
Pre-memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2A
OEM pre-memory initialization codes
0x2B
Memory initialization. Serial Presence Detect (SPD) data reading
0x2C
Memory initialization. Memory presence detection
0x2D
Memory initialization. Programming memory timing information
0x2E
Memory initialization. Configuring memory
0x2F
Memory initialization (other).
0x30
Reserved for ASL (see ASL Status Codes section below)
0x31
Memory Installed
0x32
CPU post-memory initialization is started
0x33
CPU post-memory initialization. Cache initialization
0x34
CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35
CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36
CPU post-memory initialization. System Management Mode (SMM) initialization
0x37
Post-Memory North Bridge initialization is started
0x38
Post-Memory North Bridge initialization (North Bridge module specific)
0x39
Post-Memory North Bridge initialization (North Bridge module specific)
0x3A
Post-Memory North Bridge initialization (North Bridge module specific)
0x3B
Post-Memory South Bridge initialization is started
Page 78
Express-SL/SLE
Status Code
Description
0x3C
Post-Memory South Bridge initialization (South Bridge module specific)
0x3D
Post-Memory South Bridge initialization (South Bridge module specific)
0x3E
Post-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4E
OEM post memory initialization codes
0x4F
DXE IPL is started
PEI Error Codes
0x50
Memory initialization error. Invalid memory type or incompatible memory speed
0x51
Memory initialization error. SPD reading has failed
0x52
Memory initialization error. Invalid memory size or memory modules do not match.
0x53
Memory initialization error. No usable memory detected
0x54
Unspecified memory initialization error.
0x55
Memory not installed
0x56
Invalid CPU type or Speed
0x57
CPU mismatch
0x58
CPU self test failed or possible CPU cache error
0x59
CPU micro-code is not found or micro-code update is failed
0x5A
Internal CPU error
0x5B
reset PPI is not available
0x5C-0x5F
Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1
S3 Boot Script execution
0xE2
Video repost
0xE3
OS S3 wake vector call
0xE4-0xE7
Reserved for future AMI progress codes
0xE0
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
S3 Resume Error Codes
0xE8
S3 Resume Failed in PEI
0xE9
S3 Resume PPI not Found
0xEA
S3 Resume Boot Script Error
0xEB
S3 OS Wake Error
0xEC-0xEF
Reserved for future AMI error codes
Recovery Progress Codes
0xF0
Recovery condition triggered by firmware (Auto recovery)
0xF1
Recovery condition triggered by user (Forced recovery)
Express-SL/SLE
Page 79
Status Code
Description
0xF2
Recovery process started
0xF3
Recovery firmware image is found
0xF4
Recovery firmware image is loaded
0xF5-0xF7
Reserved for future AMI progress codes
Recovery Error Codes
0xF8
Recovery PPI is not available
0xF9
Recovery capsule is not found
0xFA
Invalid recovery capsule
0xFB – 0xFF
Reserved for future AMI error codes
8.2.4.
PEI Beep Codes
# of Beeps
Description
1
Memory not Installed
1
Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
2
Recovery started
3
DXEIPL was not found
3
DXE Core Firmware Volume was not found
7
Reset PPI is not available
4
Recovery failed
4
S3 Resume failed
8.2.5.
DXE Status Codes
Status Code
Description
0x60
DXE Core is started
0x61
NVRAM initialization
0x62
Installation of the South Bridge Runtime Services
0x63
CPU DXE initialization is started
0x64
CPU DXE initialization (CPU module specific)
0x65
CPU DXE initialization (CPU module specific)
0x66
CPU DXE initialization (CPU module specific)
0x67
CPU DXE initialization (CPU module specific)
0x68
PCI host bridge initialization
0x69
North Bridge DXE initialization is started
0x6A
North Bridge DXE SMM initialization is started
0x6B
North Bridge DXE initialization (North Bridge module specific)
Page 80
Express-SL/SLE
Status Code
Description
0x6C
North Bridge DXE initialization (North Bridge module specific)
0x6D
North Bridge DXE initialization (North Bridge module specific)
0x6E
North Bridge DXE initialization (North Bridge module specific)
0x6F
North Bridge DXE initialization (North Bridge module specific)
0x70
South Bridge DXE initialization is started
0x71
South Bridge DXE SMM initialization is started
0x72
South Bridge devices initialization
0x73
South Bridge DXE Initialization (South Bridge module specific)
0x74
South Bridge DXE Initialization (South Bridge module specific)
0x75
South Bridge DXE Initialization (South Bridge module specific)
0x76
South Bridge DXE Initialization (South Bridge module specific)
0x77
South Bridge DXE Initialization (South Bridge module specific)
0x78
ACPI module initialization
0x79
CSM initialization
0x7A – 0x7F
Reserved for future AMI DXE codes
0x80 – 0x8F
OEM DXE initialization codes
0x90
Boot Device Selection (BDS) phase is started
0x91
Driver connecting is started
0x92
PCI Bus initialization is started
0x93
PCI Bus Hot Plug Controller Initialization
0x94
PCI Bus Enumeration
0x95
PCI Bus Request Resources
0x96
PCI Bus Assign Resources
0x97
Console Output devices connect
0x98
Console input devices connect
0x99
Super IO Initialization
0x9A
USB initialization is started
0x9B
USB Reset
0x9C
USB Detect
0x9D
USB Enable
0x9E – 0x9F
Reserved for future AMI codes
0xA0
IDE initialization is started
0xA1
IDE Reset
0xA2
IDE Detect
0xA3
IDE Enable
0xA4
SCSI initialization is started
0xA5
SCSI Reset
Express-SL/SLE
Page 81
Status Code
Description
0xA6
SCSI Detect
0xA7
SCSI Enable
0xA8
Setup Verifying Password
0xA9
Start of Setup
0xAA
Reserved for ASL (see ASL Status Codes section below)
0xAB
Setup Input Wait
0xAC
Reserved for ASL (see ASL Status Codes section below)
0xAD
Ready To Boot event
0xAE
Legacy Boot event
0xAF
Exit Boot Services event
0xB0
Runtime Set Virtual Address MAP Begin
0xB1
Runtime Set Virtual Address MAP End
0xB2
Legacy Option ROM Initialization
0xB3
System Reset
0xB4
USB hot plug
0xB5
PCI bus hot plug
0xB6
Clean-up of NVRAM
0xB7
Configuration Reset (reset of NVRAM settings)
0xB8 – 0xBF
Reserved for future AMI codes
0xC0 – 0xCF
OEM BDS initialization codes
DXE Error Codes
0xD0
CPU initialization error
0xD1
North Bridge initialization error
0xD2
South Bridge initialization error
0xD3
Some of the Architectural Protocols are not available
0xD4
PCI resource allocation error. Out of Resources
0xD5
No Space for Legacy Option ROM
0xD6
No Console Output Devices are found
0xD7
No Console Input Devices are found
0xD8
Invalid password
0xD9
Error loading Boot Option (LoadImage returned error)
0xDA
Boot Option is failed (StartImage returned error)
0xDB
Flash update is failed
0xDC
Reset protocol is not available
Page 82
Express-SL/SLE
8.2.6.
DXE Beep Codes
# of Beeps
Description
4
Some of the Architectural Protocols are not available
5
No Console Output Devices are found
5
No Console Input Devices are found
1
Invalid password
6
Flash update is failed
7
Reset protocol is not available
8
Platform PCI resource requirements cannot be met
8.2.7.
ACPI/ASL Checkpoint
Status Code
Description
0x01
System is entering S1 sleep state
0x02
System is entering S2 sleep state
0x03
System is entering S3 sleep state
0x04
System is entering S4 sleep state
0x05
System is entering S5 sleep state
0x10
System is waking up from the S1 sleep state
0x20
System is waking up from the S2 sleep state
0x30
System is waking up from the S3 sleep state
0x40
System is waking up from the S4 sleep state
0xAC
System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAA
System has transitioned into ACPI mode. Interrupt controller is in APIC mode.
8.3.
OEM-Reserved Checkpoint Ranges
Status Code
Description
0x05
OEM SEC initialization before microcode loading
0x0A
OEM SEC initialization after microcode loading
0x1D – 0x2A
OEM pre-memory initialization codes
0x3F – 0x4E
OEM PEI post memory initialization codes
0x80 – 0x8F
OEM DXE initialization codes
0xC0 – 0xCF
OEM BDS initialization codes
Express-SL/SLE
Page 83
9. Mechanical Information
9.1.
Board-to-Board Connectors
To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When
5 mm receptacles are chosen, the carrier board should be free of components.
Tyco 3-1827253-6
Foxconn QT002206-2131-3H
•
220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
•
This connector can be used with 5 mm through-hole standoffs (SMT type).
Tyco 3-6318491-6
Foxconn QT002206-4141-3H
•
220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
•
This connector can be used with 8 mm through-hole standoffs (SMT type).
Common Specifications
•
Current capacity: 0.5A per pin
•
Rated voltage: 50 VAC
•
Insulation resistance: 100M or greater @ 500 VDC
•
Temperature rating: -40°C ~ 85°C
•
UL certification (ECBT2.E28476)
•
Copper alloy (contacts)
•
Housing: thermo-plastic molded compound (L.C.P.)
Page 84
Express-SL/SLE
9.2.
Thermal Solution
Note: For reference only. The actual COM Express module may differ from the illustrations below.
9.2.1.
Heat Spreaders
The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the
thermal solution that is built on top of the module is compatible with all COM Express modules.
9.2.2.
Heat Sinks
A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the
thermal requirements.
9.2.3.
Installation
Install a heat spreader or heat sink using the following instructions.
Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.
Step 2: Remove the protective membranes from the thermal pads.
Express-SL/SLE
Page 85
Page 86
Express-SL/SLE
Step 3: Assemble the heatsink onto the COM Express module.
Use the three M2.5, L=6mm screws provided to fasten the heatsink to the module.
Note: The Express-SL/SLE uses two screws to attach the heatsink to the COM Express module.
Step 4: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.
Then press down on the module until it is firmly seated on the carrier board.
Step 5: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.
Express-SL/SLE
Page 87
Step 6: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
Page 88
Express-SL/SLE
9.3.
Mounting Methods
There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of
5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on
the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the
thermal solution and the carrier board has through-hole standoffs.
Express-SL/SLE
Page 89
9.4.
Standoff Types
The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
5mm through-hole standoff (SMT type)
5mm threaded standoff (DIP type)
P/N: 33-72000-0050
P/N: 33-72016-0050
8mm through-hole standoff (SMT type)
8mm threaded standoff (DIP type)
P/N: 33-72000-0080
P/N: 33-72015-0050
Page 90
Express-SL/SLE
Safety Instructions
Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and
operating instructions for future use.
•
Please read these safety instructions carefully.
•
Please keep this User‘s Manual for later reference.
•
The equipment should be operated only from the type of power source indicated on the rating label. Make sure the voltage of the
power source when connect the equipment to the power outlet.
•
If your equipment has a voltage selector switch, make sure that the switch is in the proper position for your area. The voltage
selector switch is set at the factory to the correct voltage.
•
For pluggable equipment, that the socket-outlet shall be installed near the equipment and shall be easily accessible.
•
Place the power cord such a way that people can not step on it. Do not place anything over the power cord.
•
If the equipment is not use for long time, disconnect the equipment from mains to avoid being damaged by transient overvoltage.
•
All cautions and warnings on the equipment should be noted.
•
Please keep this equipment from humidity.
•
Do not use this equipment near water or a heat source.
•
Lay this equipment on a reliable surface when install. A drop or fall could cause injury.
•
Never pour any liquid into opening; this could cause fire or electrical shock.
•
Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure you provide adequate space
around the system for ventilation when you set up your work area. Never insert objects of any kind into the ventilation openings.
•
To avoid electrical shock, always unplug all power cables and modem cables from the wall outlets before removing covers.
•
Lithium Battery provided (real time clock battery)
“CAUTION – Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries according to the
instructions”
•
If one of the following situations arises, get the equipment checked by a service personnel:
ƒ
The power cord or plug is damaged.
ƒ
Liquid has penetrated into the equipment.
ƒ
The equipment has been exposed to moisture.
ƒ
The equipment has not work well or you can not get it work according to user‘s manual.
ƒ
The equipment has dropped and damaged.
ƒ
If the equipment has obvious sign of breakage.
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Getting Service
ADLINK Technology, Inc.
Address:
Tel:
Fax:
Email:
9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
+886-2-8226-5877
+886-2-8226-5717
service@adlinktech.com
Ampro ADLINK Technology, Inc.
Address:
Tel:
Toll Free:
Fax:
Email:
5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
+1-408-360-0200
+1-800-966-5200 (USA only)
+1-408-360-0222
info@adlinktech.com
ADLINK Technology (China) Co., Ltd.
Address:
Tel:
Fax:
Email:
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,Pudong New Area
Shanghai, 201203 China
+86-21-5132-8988
+86-21-5132-3588
market@adlinktech.com
ADLINK Technology Beijing
Address:
Tel:
Fax:
Email:
Rm. 801, Power Creative E, No. 1, B/D,
Beijing, 100085 China
+86-10-5885-8666
+86-10-5885-8625
market@adlinktech.com
Shang Di East Rd.
ADLINK Technology Shenzhen
Address:
Tel:
Fax:
Email:
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S.
Shenzhen, 518054 China
+86-755-2643-4858
+86-755-2664-6353
market@adlinktech.com
LiPPERT ADLINK Technology GmbH
Address:
Tel:
Fax:
Email:
Page 92
Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany
+49-621-43214-0
+49-621 43214-30
emea@adlinktech.com
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ADLINK Technology, Inc. (French Liaison Office)
Address:
6 allée de Londres, Immeuble Ceylan
91940 Les Ulis, France
Tel:
+33 (0) 1 60 12 35 66
Fax:
+33 (0) 1 60 12 35 66
Email:
france@adlinktech.com
ADLINK Technology Japan Corporation
Address:
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku
Tokyo 101-0045, Japan
Tel:
+81-3-4455-3722
Fax:
+81-3-5209-6013
Email:
japan@adlinktech.com
ADLINK Technology, Inc. (Korean Liaison Office)
Address:
802, Mointer B/D, 326 Seocho-daero, Seocho-Gu,
Seoul 137-881, Korea
Tel:
+82-2-2057-0565
Fax:
+82-2-2057-0563
Email:
korea@adlinktech.com
ADLINK Technology Singapore Pte. Ltd.
Address:
84 Genting Lane #07-02A, Cityneon Design Centre
Singapore 349584
Tel:
+65-6844-2261
Fax:
+65-6844-2263
Email:
singapore@adlinktech.com
ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)
Address:
#50-56, First Floor, Spearhead Towers
Margosa Main Road (between 16th/17th Cross), Malleswaram
Bangalore - 560 055, India
Tel:
+91-80-65605817, +91-80-42246107
Fax:
+91-80-23464606
Email:
india@adlinktech.com
ADLINK Technology, Inc. (Israeli Liaison Office)
Address:
27 Maskit St., Corex Building
PO Box 12777
Herzliya 4673300, Israel
Tel:
+972-54-632-5251
Fax:
+972-77-208-0230
Email:
israel@adlinktech.com
ADLINK Technology, Inc. (UK Liaison Office)
Tel:
+44 774 010 59 65
Email:
UK@adlinktech.com
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