ADT7473 dBCool® Remote Thermal Monitor and Fan Controller

dBCool® Remote Thermal
Monitor and Fan Controller
ADT7473
FEATURES
GENERAL DESCRIPTION
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Series resistance cancellation on the remote channel
Extended temperature measurement range, up to 191°C
Dynamic TMIN control mode optimizes system acoustics
intelligently
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium®4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully ROHS compliant
The ADT7473 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The
ADT7473 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. A unique dynamic TMIN control mode
enables the system thermals/acoustics to be intelligently
managed. The effectiveness of the system’s thermal solution can
be monitored using the THERM input. The ADT7473 also
provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
FUNCTIONAL BLOCK DIAGRAM
SCL SDA SMBALERT
ADT7473
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
TMIN
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
VCC
D1–
D2+
INTERRUPT
STATUS
REGISTERS
THERMAL
PROTECTION
VCC TO ADT7473
D1+
SRC
D2–
VCCP
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
PERFORMANCE
MONITORING
THERM
ADDRESS
POINTER
REGISTER
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
10-BIT
ADC
BAND GAP
REFERENCE
BAND GAP
TEMP. SENSOR
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
04686-001
PWM1
SERIAL BUS
INTERFACE
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADT7473
TABLE OF CONTENTS
Specifications..................................................................................... 3
THERM Timer ........................................................................... 22
Absolute Maximum Ratings............................................................ 5
Fan Drive Using PWM Control ............................................... 25
Thermal Characteristics .............................................................. 5
Fan Presence Detect................................................................... 30
ESD Caution.................................................................................. 5
Sleep States .................................................................................. 30
Pin Configuration and Function Descriptions............................. 6
XNOR Tree Test Mode .............................................................. 31
Typical Performance Characteristics ............................................. 7
Power-On Default ...................................................................... 31
Product Description......................................................................... 9
Programming the Automatic Fan Speed Control Loop ............ 32
Comparison Between ADT7467 and ADT7473 ...................... 9
Automatic Fan Control Overview............................................ 32
Recommended Implementation................................................. 9
Step 1: Hardware Configuration .............................................. 33
Serial Bus Interface..................................................................... 10
Step 2: Configuring the Mux .................................................... 35
Write Operations ........................................................................ 11
Step 3: TMIN Settings for Thermal Calibration Channels ...... 37
Read Operations ......................................................................... 12
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 38
SMBus Timeout .......................................................................... 12
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 38
Voltage Measurement Input...................................................... 12
Step 6: TRANGE for Temperature Channels................................ 39
Analog-to-Digital Converter .................................................... 12
Step 7: TTHERM for Temperature Channels ............................... 42
Input Circuitry............................................................................ 12
Step 8: THYST for Temperature Channels.................................. 43
Voltage Measurement Registers................................................ 12
Dynamic TMIN Control Mode ................................................... 45
VCCP Limit Registers ................................................................... 13
Step 9: Operating Points for Temperature Channels............. 47
Additional ADC Functions for Voltage Measurements ........ 13
Step 10: High and Low Limits for Temperature Channels ... 48
Temperature Measurement Method ........................................ 14
Step 11: Monitoring THERM ................................................... 50
Series Resistance Cancellation.................................................. 16
Factors Affecting Diode Accuracy ........................................... 16
Additional ADC Functions for Temperature Measurement 18
Limits, Status Registers, and Interrupts....................................... 19
Limit Values................................................................................. 19
Enhancing System Acoustics .................................................... 51
Step 12: Ramp Rate for Acoustic Enhancement..................... 53
Register Tables ................................................................................ 56
Outline Dimensions ....................................................................... 74
Ordering Guide .......................................................................... 74
Status Registers ........................................................................... 20
REVISION HISTORY
6/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 76
ADT7473
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise specified.
All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent most likely parametric
norm. Logic inputs accept input high voltages up to VMAX, even when device is operating down to VMIN. Timing specifications are tested at
logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. Serial management bus (SMBus) timing specifications are
guaranteed by design and are not production tested.
Table 1.
Parameter
POWER SUPPLY
Supply Voltage
Supply Current, ICC
TEMP-TO-DIGITAL CONVERTER
Local Sensor Accuracy
Min
Typ
Max
Unit
Test Conditions/Comments
3.0
3.3
1.5
3.6
3
V
mA
Interface inactive, ADC active
±0.5
±1.5
±2.5
°C
°C
°C
°C
°C
°C
μA
μA
μΑ
Resolution
Remote Diode Sensor Accuracy
0.25
±0.5
Resolution
Remote Sensor Source Current
0.25
6
36
96
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENTUATORS)
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Input Resistance
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±1.5
±1
90
0°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
First current
Second current
Third current
%
LSB
%/V
ms
ms
ms
ms
ms
kΩ
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging disabled
For VCCP channel
%
%
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ +120°C
RPM
RPM
RPM
RPM
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
0.1
8.0
0.4
20
mA
V
μA
IOUT = −8.0 mA
VOUT = VCC
0.1
0.4
1.0
V
μA
IOUT = −4.0 mA
VOUT = VCC
0.4
V
V
mV
±0.1
11
12
38
145
19
120
±6
±10
65,535
Full-Scale Count
Nominal Input RPM
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 TO PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
±1.5
±2.5
0°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
109
329
5,000
10,000
2.0
500
Rev. 0 | Page 3 of 76
8 bits
ADT7473
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Min
Typ
Max
Unit
Test Conditions/Comments
3.6
V
V
Maximum input voltage
2.0
Input Low Voltage, VIL
0.8
V
V
V p-p
−0.3
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
tLOW
0.5
0.75 × VCC
0.4
±1
±1
5
Minimum input voltage
V
V
μA
μA
pF
VIN = VCC
VIN = 0
See Figure 2
10
400
50
4.7
4.7
4.0
50
1,000
300
250
15
tR
kHz
ns
μs
μs
μs
ns
μs
ns
ms
35
tF
Can be optionally disabled
tHD; STA
SCL
tHIGH
tHD; DAT
tSU; STA
tSU; STO
tSU; DAT
SDA
tBUF
P
S
S
Figure 2. Serial Bus Timing Diagram
Rev. 0 | Page 4 of 76
P
04686-002
tHD; STA
ADT7473
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Positive Supply Voltage (VCC)
Voltage on Any Input or Output Pin
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
IR Reflow Peak Temperature
Lead Temperature (Soldering, 10 sec)
ESD Rating
Rating
3.6 V
−0.3 V to +3.6 V
±5 mA
±20 mA
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
260°C
16-lead QSOP package:
300°C
1,500 V
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 76
ADT7473
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL 1
16
SDA
GND 2
15
PWM1/XTO
VCC 3
14
VCCP
13
D1+
PWM2/SMBALERT 5
ADT7473
TOP VIEW
(Not to Scale) 12 D1–
TACH1 6
11
TACH2 7
10
D2+
D2–
PWM3 8
9
TACH4/GPIO/THERM/SMBALERT
04686-003
TACH3 4
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin
No.
1
2
3
4
5
Mnemonic
SCL
GND
VCC
TACH3
PWM2
6
7
8
SMBALERT
TACH1
TACH2
PWM3
9
TACH4
GPIO
THERM
SMBALERT
10
11
12
13
14
15
16
D2−
D2+
D1−
D1+
VCCP
PWM1
XTO
SDA
Description
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
Ground Pin for the ADT7473.
Power Supply. Powered by 3.3 V.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2 speed.
Can be configured as a high or low frequency drive.
Digital Output (Open Drain). Can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
General-Purpose Open Drain Digital I/O.
Can be configured as a bidirectional THERM pin, which can be used to time and monitor assertions on the THERM
input as well as to assert when an ADT7473 THERM overtemperature limit is exceeded. For example, the pin can be
connected to the PROCHOT output of an Intel Pentium 4 processor or to the output of a trip point temperature
sensor. Can be used as an output to signal overtemperature conditions.
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit
conditions.
Cathode Connection to Second Thermal Diode.
Anode Connection to Second Thermal Diode.
Cathode Connection to First Thermal Diode.
Anode Connection to First Thermal Diode.
Analog Input. Monitors processor core voltage (0 V − 3 V).
Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
Also functions as the output from the XNOR tree in XNOR test mode.
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 kΩ typical pull-up.
Rev. 0 | Page 6 of 76
ADT7473
TYPICAL PERFORMANCE CHARACTERISTICS
70
60
60
TEMPERATURE ERROR (°C)
TEMPERATURE ERROR (°C)
40
20
D+ TO GND
0
D+ TO VCC
–20
50
40
30
100mV
20
60mV
40mV
10
–40
–60
0
10
20
40
30
60
50
70
80
90
04686-008
04686-004
0
–10
0
100
100M
200M
300M
400M
500M
600M
NOISE FREQUENCY (Hz)
LEAKAGE RESISTANCE (MΩ)
Figure 4. Remote Temperature Error vs. PCB Resistance
Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency
0
1.20
1.18
1.16
1.14
–20
1.12
IDD (mA)
–30
1.10
1.08
1.06
–40
1.04
1.02
04686-006
–50
–60
0
2
4
6
8
10
12
14
16
18
20
04686-009
TEMPERATURE ERROR (°C)
–10
1.00
0.98
3.0
22
3.1
3.2
CAPACITANCE (nF)
Figure 5. Temperature Error vs. Capacitance Between D+ and D−
3.5
3.6
500M
600M
3.4
Figure 8. Normal IDD vs. Power Supply
15
30
25
10
100mV
TEMPERATURE ERROR (°C)
20
15
60mV
10
5
5
100mV
0
250mV
–5
–10
04686-007
0
40mV
–5
0
100M
200M
300M
400M
500M
04686-010
TEMPERATURE ERROR (°C)
3.3
VDD (V)
–15
0
600M
100M
200M
300M
400M
FREQUENCY (Hz)
NOISE FREQUENCY (Hz)
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
Rev. 0 | Page 7 of 76
Figure 9. Internal Temperature Error vs. Frequency
ADT7473
3.0
6
2.5
4
TEMPERATURE ERROR (°C)
2
0
–2
100mV
–4
–6
–8
1.5
1.0
0.5
0
–0.5
–12
0
100M
200M
300M
400M
500M
–1.5
–2.0
600M
–40
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
04686-012
–0.5
–1.0
–1.5
–20
0
20
40
60
–20
0
20
40
60
85
105
125
OIL BATH TEMPERATURE (°C)
FREQUENCY (Hz)
–40
04686-013
–10
TEMPERATURE ERROR (°C)
2.0
–1.0
04686-011
TEMPERATURE ERROR (°C)
250mV
85
105
125
OIL BATH TEMPERATURE (°C)
Figure 11. Internal Temperature Error vs. ADT7473 Temperature
Rev. 0 | Page 8 of 76
Figure 12. Remote Temperature Error vs. Temperature
ADT7473
PRODUCT DESCRIPTION
How to Set the Functionality of Pin 9
The ADT7473 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 16),
and an input line for the serial clock (Pin 1). All control and
programming functions for the ADT7473 are performed over
the serial bus. Additionally, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
Pin 9 on the ADT7473 has four possible functions: SMBALERT,
THERM, GPIO, and TACH4. The user chooses the required
functionality by setting Bit 0 and Bit 1 of Configuration
Register 4 at Address 0x7D.
Table 4. Pin 9 Settings
Bit 0
0
0
1
1
COMPARISON BETWEEN ADT7467 AND ADT7473
The ADT7473 can only be powered via a 3.3 V supply, and does
not support 5 V operation like the ADT7467.
Bit 1
0
1
0
1
Function
TACH4
THERM
SMBALERT
GPIO
RECOMMENDED IMPLEMENTATION
High frequency PWM drive can be independently selected for
each PWM channel on the ADT7473. This is not available on
the ADT7467.
Configuring the ADT7473, as shown in Figure 13, allows the
system designer to use the following features:
The range and resolution of the temperature offset register can
now be changed from a ±64°C range at 0.5°C resolution to a
±128°C range at 1°C resolution. This is not available on the
ADT7467.
•
Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
•
Three TACH fan speed measurement inputs.
THERM overtemperature events can be disabled/enabled
individually on each temperature channel. This is not available
on the ADT7467.
•
VCC measured internally through Pin 3.
•
CPU temperature measured using Remote 1 temperature
channel.
•
Ambient temperature measured through Remote 2
temperature channel.
•
Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.
Bit 7 of Configuration Register 1 is no longer supported because
the ADT7473 cannot be powered via a 5 V supply.
Bit 0 of Configuration Register 1 (0x40) remains writable after
the lock bit is set. This bit enables monitoring.
2-wire fan speed measurement is no longer supported on the
ADT7473.
ADT7473
FRONT
CHASSIS
FAN
CPU FAN
PWM1
TACH2
TACH1
REAR
CHASSIS
FAN
PWM3
D2+
TACH3
D2–
THERM
CPU
PROCHOT
D1+
SDA
D1–
SCL
SMBALERT
GND
Figure 13. ADT7473 Configuration
Rev. 0 | Page 9 of 76
ICH
04686-015
AMBIENT
TEMPERATURE
ADT7473
SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7473 is carried out
using the SMBus. The ADT7473 is connected to this bus as a
slave device, under the control of a master controller, which is
usually (but not necessarily) the ICH.
In the ADT7473, write operations contain either one or two
bytes, and read operations contain one byte. To write data to
one of the device data registers or read data from it, the address
pointer register must be set so the correct data register is
addressed, then data can be written into that register or read
from it. The first byte of a write operation always contains an
address that is stored in the address pointer register. If data is to
be written to the device, then the write operation contains a
second data byte that is written to the register selected by the
address pointer register.
The ADT7473 has a fixed 7-bit serial bus address of 0101110
or 0x2E. The read/write bit must be added to get the 8-bit
address (01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge bit from the slave device. Transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition when the clock is high might be interpreted as a stop
signal. The number of data bytes that can be transmitted over
the serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
This write operation is shown in Figure 14. The device address
is sent over the bus, and then R/W is set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the tenth clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse; this is known as No Acknowledge. The
master takes the data line low during the low period before the
tenth clock pulse, and then high during the tenth clock pulse to
assert a stop condition.
When reading data from a register, there are two possibilities:
•
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
1
If the ADT7473’s address pointer register value is unknown
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7473 as
before, but only the data byte containing the register
address is sent, because no data is written to the register.
This is shown in Figure 15.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte
read from the data register. This is shown in Figure 16.
•
9
If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, as shown in Figure 16.
9
1
SCL
0
1
0
1
1
1
0
D7
R/W
START BY
MASTER
D6
ACK. BY
ADT7473
FRAME 1
SERIAL BUS ADDRESS BYTE
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7473
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY STOP BY
ADT7473 MASTER
Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
Rev. 0 | Page 10 of 76
04686-016
SDA
ADT7473
1
9
9
1
SCL
0
1
START BY
MASTER
0
1
1
1
0
D7
R/W
D6
ACK. BY
ADT7473
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D5
D2
D3
D1
D0
ACK. BY
ADT7473
FRAME 2
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
04686-017
SDA
Figure 15. Writing to the Address Pointer Register Only
1
9
9
1
SCL
0
START BY
MASTER
1
0
1
1
1
0
R/W
D7
D6
ACK. BY
ADT7473
FRAME 1
SERIAL BUS ADDRESS BYTE
D4
D5
D2
D3
D1
D0
NO ACK. BY STOP BY
MASTER
MASTER
FRAME 2
DATA BYTE FROM ADT743
04686-018
SDA
Figure 16. Reading Data from a Previously Selected Register
In addition to supporting the send byte and receive byte
protocols, the ADT7473 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2 for more
information; this document is available from Intel.)
If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a
stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7473 are discussed below. The following abbreviations are
used in the diagrams:
S – START
P – STOP
R – READ
W – WRITE
A – ACKNOWLEDGE
A – NO ACKNOWLEDGE
The ADT7473 uses the following SMBus write protocols.
For the ADT7473, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address. This operation is illustrated in Figure 17.
1
2
4
5 6
REGISTER
ADDRESS
A P
3
SLAVE
S
W A
ADDRESS
04686-019
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is not
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
Figure 17. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master sends a data byte.
Send Byte
7.
The slave asserts ACK on SDA.
In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
8.
The master asserts a stop condition on SDA, and the
transaction ends.
6.
The master asserts a stop condition on SDA and the
transaction ends.
Rev. 0 | Page 11 of 76
1
2
3
SLAVE
S ADDRESS W A
4
5
6
7 8
REGISTER
ADDRESS
A
DATA
A P
Figure 18. Single Byte Write to a Register
04686-020
The byte write operation is illustrated in Figure 18.
ADT7473
READ OPERATIONS
SMBus TIMEOUT
The ADT7473 uses the following SMBus read protocols.
The ADT7473 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7473 assumes the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so it
can be disabled.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been previously set up.
In this operation, the master device receives a single byte from a
slave device, as follows:
Configuration Register 1 (Reg. 0x40)
1.
The master device asserts a start condition on SDA.
<6> TODIS = 0, SMBus timeout enabled (default).
2.
The master sends the 7-bit slave address followed by the
read bit (high).
<6> TODIS = 1, SMBus timeout disabled.
3.
The addressed slave device asserts ACK on SDA.
VOLTAGE MEASUREMENT INPUT
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
The ADT7473 has one external voltage measurement channel
and can also measure its own supply voltage, VCC. Pin 14 can
measure VCCP. The VCC supply voltage measurement is carried
out through the VCC pin (Pin 3). The VCCP input can be used to
monitor a chipset supply voltage in computer systems.
2
3
SLAVE
S ADDRESS R A
4
5 6
DATA
A P
Figure 19. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
events occur:
2.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accordance with normal SMBus arbitration.
5.
INPUT CIRCUITRY
The internal structure for the VCCP analog input is shown in
Figure 20. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order
low-pass filter that gives the input immunity to high frequency
noise.
17.5kΩ
52.5kΩ
SMBALERT is pulled low.
4.
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the
input has built-in attenuators to allow measurement of VCCP
without any external components. To allow for the tolerance of
the supply voltage, the ADC produces an output of 3/4 full-scale
(768 decimal or 300 hex) for the nominal input voltage and thus
has adequate headroom to deal with overvoltages.
VCCP
1.
3.
ANALOG-TO-DIGITAL CONVERTER
35pF
04686-022
1
04686-021
In the ADT7473, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is illustrated in Figure 19.
Figure 20. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Reg. 0x21 VCCP Reading = 0x00 default
Reg. 0x22 VCC Reading = 0x00 default
Once the ADT7473 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition is gone.
Rev. 0 | Page 12 of 76
ADT7473
VCCP LIMIT REGISTERS
Bypass Voltage Input Attenuator
Associated with the VCCP measurement channel is a high and
low limit register. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
can also generate SMBALERT interrupts.
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the VCCP input. This allows the
user to directly connect external sensors or to rescale the analog
voltage measurement inputs for other applications. The input
range of the ADC without the attenuators is 0 V to 2.25 V.
Reg. 0x46 VCCP Low Limit = 0x00 default
Single-Channel ADC Conversion
Reg. 0x47 VCCP High Limit = 0xFF default
Table 5 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 μs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
A number of other functions are available on the ADT7473 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. When
faster conversions are needed, setting Bit 4 of Configuration
Register 2 (Reg. 0x73) turns averaging off. This effectively gives
a reading 16 times faster (711 μs), but the reading may be
noisier.
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7473 into single-channel ADC conversion mode. In this
mode, the ADT7473 can be made to read a single voltage
channel only. If the internal ADT7473 clock is used, the selected
input is read every 711 μs. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 minimum high
byte register (0x55).
Bits <7:5> Reg. 0x55
001
010
101
110
111
Channel Selected
VCCP
VCC
Remote 1 temperature
Local temperature
Remote 2 temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<5> = 1, bypass input attenuators.
<6> = 1, single-channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> selects ADC channel for single-channel convert mode.
Rev. 0 | Page 13 of 76
ADT7473
Table 5. 10-Bit ADC Output Code vs. VIN
VCC (3.3 VIN) 1
<0.0042
0.0042 to 0.0085
0.0085 to 0.0128
0.0128 to 0.0171
0.0171 to 0.0214
0.0214 to 0.0257
0.0257 to 0.0300
0.0300 to 0.0343
0.0343 to 0.0386
VCCP
<0.00293
0.0293 to 0.0058
0.0058 to 0.0087
0.0087 to 0.0117
0.0117 to 0.0146
0.0146 to 0.0175
0.0175 to 0.0205
0.0205 to 0.0234
0.0234 to 0.0263
1.100 to 1.1042
0.7500 to 0.7529
2.200 to 2.2042
1.5000 to 1.5029
3.300 to 3.3042
2.2500 to 2.2529
4.3527 to 4.3570
4.3570 to 4.3613
4.3613 to 4.3656
4.3656 to 4.3699
4.3699 to 4.3742
4.3742 to 4.3785
4.3785 to 4.3828
4.3828 to 4.3871
4.3871 to 4.3914
4.3914 to 4.3957
>4.3957
2.9677 to 2.9707
2.9707 to 2.9736
2.9736 to 2.9765
2.9765 to 2.9794
2.9794 to 2.9824
2.9824 to 2.9853
2.9853 to 2.9882
2.9882 to 2.9912
2.9912 to 2.9941
2.9941 to 2.9970
>2.9970
1
ADC Output
Decimal
0
1
2
3
4
5
6
7
8
•
•
•
256 (1/4-scale)
•
•
•
512 (1/2-scale)
•
•
•
768 (3/4 scale)
•
•
•
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
Binary (10 Bits)
00000000 00
00000000 01
00000000 10
00000000 11
00000001 00
00000001 01
00000001 10
00000001 11
00000010 00
01000000 00
10000000 00
11000000 00
11111101 01
11111101 10
11111101 11
11111110 00
11111110 01
11111110 10
11111110 11
11111111 00
11111111 01
11111111 10
11111111 11
The VCC output codes listed assume that VCC is 3.3 V.
TEMPERATURE MEASUREMENT METHOD
A simple method of measuring temperature is to exploit the
negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor operated at constant
current. Unfortunately, this technique requires calibration to
null out the effect of the absolute value of VBE, which varies
from device to device.
The technique used in the ADT7473 is to measure the change
in VBE when the device is operated at three different currents.
Previous devices have used only two operating currents, but the
use of a third current allows automatic cancellation of resistances in series with the external temperature sensor.
Figure 21 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, but it could equally
be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D− input. C1
can optionally be added as a noise filter (recommended maximum value 1000 pF). However, a better option in noisy
environments is to add a filter, as described in the Noise
Filtering section.
Rev. 0 | Page 14 of 76
ADT7473
Local Temperature Measurement
Figure 21 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for
temperature monitoring on some microprocessors. It could also
be a discrete transistor such as a 2N3904/2N3906.
The ADT7473 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip 10-bit ADC.
The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative
temperatures can be measured, the temperature data is stored in
Offset 64 format or twos complement format, as shown in
Table 6 and Table 7. Theoretically, the temperature sensor and
ADC can measure temperatures from −63°C to +127°C (or
−63°C to +191°C in the extended temperature range) with a
resolution of 0.25°C. However, this exceeds the operating
temperature range of the device, so local temperature
measurements outside the ADT7473 operating temperature
range are not possible.
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input. Figure 23 and
Figure 24 show how to connect the ADT7473 to an NPN or
PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground, but
is biased above ground by an internal diode at the D– input.
Remote Temperature Measurement
The ADT7473 can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pins 10 and 11, or Pins 12 and 13.
To measure ∆VBE, the operating current through the sensor is
switched among three related currents. N1 × I and N2 × I are
different multiples of the current I, as shown in Figure 21. The
currents through the temperature diode are switched between
I and N1 × I, giving ∆VBE1, and then between I and N2 × I,
giving ∆VBE2. The temperature can then be calculated using the
two ∆VBE measurements. This method can also cancel the effect
of any series resistance on the temperature measurement.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device and individual
calibration is required to null this out, so the technique is
unsuitable for mass production. The technique used in the
ADT7473 is to measure the change in VBE when the device is
operated at three different currents. This is given by
The resulting ΔVBE waveforms are passed through a 65 kHz
low-pass filter to remove noise and then to a chopper-stabilized
amplifier. This amplifies and rectifies the waveform to produce
a dc voltage proportional to ΔVBE. The ADC digitizes this
voltage, and a temperature measurement is produced. To reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles.
ΔV BE = KT / q × 1n(N )
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
The results of remote temperature measurements are stored in
10-bit, twos complement format, as listed in Table 6. The extra
resolution for the temperature measurements is held in the
extended resolution register 2 (Reg. 0x77). This gives
temperature readings with a resolution of 0.25°C.
VDD
I
REMOTE
SENSING
TRANSISTOR D+
N2 × I
N1 × I
IBIAS
LPF
VOUT+
fC = 65kHz
VOUT–
TO ADC
04686-023
D–
Figure 21. Signal Conditioning for Remote Diode Temperature Sensors
Rev. 0 | Page 15 of 76
ADT7473
Noise Filtering
FACTORS AFFECTING DIODE ACCURACY
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
the D− pin to help combat the effects of noise. However, large
capacitances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1000 pF.
This capacitor reduces the noise, but does not eliminate it,
making use of the sensor difficult in a very noisy environment.
Remote Sensing Diode
The ADT7473 has a major advantage over other devices for
eliminating the effects of noise on the external sensor. Using the
series resistance cancellation feature, a filter can be constructed
between the external temperature sensor and the part. The effect
of any filter resistance seen in series with the remote sensor is
automatically canceled from the temperature result.
The construction of a filter allows the ADT7473 and the remote
temperature sensor to operate in noisy environments. Figure 22
shows a low-pass R-C filter with the following values:
The ADT7473 is designed to work with either substrate transistors built into processors or discrete transistors. Substrate
transistors are generally PNP types with the collector connected
to the substrate. Discrete types can be either PNP or NPN
transistors connected as a diode (base-shorted to the collector).
If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D−. If a PNP
transistor is used, the collector and base are connected to D−
and the emitter is connected to D+.
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•
R = 100 Ω, C = 1 nF
This filtering reduces both common-mode noise and
differential noise.
The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
ADT7473 is trimmed for an nf value of 1.008. Use the
following equation to calculate the error introduced at a
temperature T (°C), when using a transistor whose nf does
not equal 1.008. Refer to the data sheet for the related CPU
to obtain the nf values.
ΔT = (nf − 1.008)/1.008 × (273.15 K + T)
100Ω
D+
1nF
100Ω
D–
To factor this in, the user can write the ΔT value to the
offset register. The ADT7473 then automatically adds it to
or subtracts it from the temperature measurement.
04686-024
REMOTE
TEMPERATURE
SENSOR
Figure 22. Filter Between Remote Sensor and ADT7473
•
SERIES RESISTANCE CANCELLATION
Parasitic resistance to the ADT7473 D+ and D− inputs (seen in
series with the remote diode) is caused by a variety of factors
including PCB track resistance and track length. This series
resistance appears as a temperature offset in the remote sensor’s
temperature measurement. This error typically causes a 0.5°C
offset per Ω of parasitic resistance in series with the remote
diode.
The ADT7473 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result without the need for user characterization of this resistance. The ADT7473 is designed to automatically cancel,
typically, up to 3 kΩ of resistance. By using an advanced
temperature measurement method, this is transparent to the
user. This feature allows resistances to be added to the sensor
path to produce a filter, allowing the part to be used in noisy
environments. See the Noise Filtering section for details.
Some CPU manufacturers specify the high and low current
levels of the substrate transistors. The high current level of
the ADT7473, IHIGH, is 96 μA and the low level current,
ILOW, is 6 μA. If the ADT7473 current levels do not match
the current levels specified by the CPU manufacturer, it
might be necessary to remove an offset. The CPU’s data
sheet advises whether this offset needs to be removed and
how to calculate it. This offset can be programmed to the
offset register. It is important to note that, if more than one
offset must be considered, the algebraic sum of these
offsets must be programmed to the offset register.
If a discrete transistor is used with the ADT7473, the best
accuracy is obtained by choosing devices according to the
following criteria:
•
Base-emitter voltage greater than 0.25 V at 6 μA, at the
highest operating temperature.
•
Base-emitter voltage less than 0.95 V at 100 μA, at the
lowest operating temperature.
•
Base resistance less than 100 Ω.
•
Small variation in hFE (such as 50 to 150) that indicates
tight control of VBE characteristics.
Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23
packages, are suitable devices to use.
Rev. 0 | Page 16 of 76
ADT7473
Table 6. Twos Complement Temperature Data Format
1
Temperature
–128°C
–63°C
–50°C
–25°C
–10°C
0°C
10.25°C
25.5°C
50.75°C
75°C
100°C
125°C
127°C
1
Digital Output (10-Bit)
1000 0000 00 (diode fault)
1100 0001 00
1100 1110 00
1110 0111 00
1111 0110 00
0000 0000 00
0000 1010 01
0001 1001 10
0011 0010 11
0100 1011 00
0110 0100 00
0111 1101 00
0111 1111 00
Bold numbers denote 2 LSB of measurement in extended resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
Table 7. Extended Range, Temperature Data Format
Digital Output (10-Bit)1
0000 0000 00 (diode fault)
0000 0001 00
0011 1111 00
0100 0000 00
0100 0001 00
0100 1010 00
0101 1001 00
0111 0010 00
1000 1001 00
1010 0100 00
1011 1101 00
1111 1111 00
Temperature
–64°C
–63°C
–1°C
0°C
1°C
10°C
25°C
50°C
75°C
100°C
125°C
191°C
Bold numbers denote 2 LSB of measurement in extended resolution
Register 2 (Reg. 0x77) with 0.25°C resolution.
ADT7473
As CPUs run faster, it becomes more difficult to avoid high
frequency clocks when routing the D+/D– traces around a
system board. Even when recommended layout guidelines are
followed, some temperature errors may still be attributable to
noise coupled onto the D+/D– lines. Constant high frequency
noise usually attenuates or increases temperature measurements
by a linear, constant value.
The ADT7473 has temperature offset registers at addresses 0x70
and 0x72 for the Remote 1 and Remote 2 temperature channels.
By performing a one-time calibration of the system, the user
can determine the offset caused by system board noise and null
it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature
measurement. The LSBs add 0.5°C offset to the temperature
reading so the 8-bit register effectively allows temperature
offsets of up to ±64°C with a resolution of 0.5°C. This ensures
that the readings in the temperature measurement registers are
as accurate as possible.
Temperature Offset Registers
Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0°C default)
Reg. 0x71 Local Temperature Offset = 0x00 (0°C default)
Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0°C default)
ADT7460/ADT7473 Backwards-Compatible Mode
By setting Bit 1 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value
registers (0x25, 0x26, and 0x27) in twos complement in the
range −63°C to +127°C. (The ADT7473 still makes calculations
based on the Offset 64 extended range and clamps the results, if
necessary.) The temperature limits must be reprogrammed in
twos complement. If a twos complement temperature below
−63°C is entered, the temperature is clamped to −63°C. In this
mode, the diode fault condition remains −128°C = 1000 0000,
while in the extended temperature range (−64°C to +191°C),
the fault condition is represented by −64°C = 0000 0000.
D+
D–
04686-025
2N3904
NPN
Figure 23. Measuring Temperature Using an NPN Transistor
Temperature Measurement Registers
Reg. 0x25 Remote 1 Temperature
Reg. 0x26 Local Temperature
Reg. 0x27 Remote 2 Temperature
ADT7473
Reg. 0x77 Extended Resolution 2 = 0x00 default
D+
2N3906
PNP
D–
<7:6> TDM2, Remote 2 temperature LSBs.
04686-026
1
Nulling Out Temperature Errors
Figure 24. Measuring Temperature Using a PNP Transistor
<5:4> LTMP, Local temperature LSBs.
<3:2> TDM1, Remote 1 temperature LSBs.
Rev. 0 | Page 17 of 76
ADT7473
Temperature Measurement Limit Registers
Table 9. Conversion Time with Averaging Enabled
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Channel
Voltage Channels
Remote Temperature
Local Temperature
Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default
Single-Channel ADC Conversions
Measurement Time
11 ms
39 ms
12 ms
Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7473 into single-channel ADC conversion mode. In this
mode, the ADT7473 can be made to read a single temperature
channel only. The appropriate ADC channel is selected by
writing to Bits <7:5> of the TACH1 minimum high byte register
(0x55).
Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default
Table 10. Programming Single-Channel ADC Mode for
Temperatures
Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default
Reg. 0x50 Local Temperature Low Limit = 0x01 default
Reg. 0x51 Local Temperature High Limit = 0x7F default
Reading Temperature from the ADT7473
It is important to note that the temperature can be read from
the ADT7473 as an 8-bit value (with 1°C resolution) or as a
10-bit value (with 0.25°C resolution). If only 1°C resolution is
required, the temperature readings can be read back at any time
and in no particular order.
If the 10-bit measurement is required, a 2-register read for each
measurement is used. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read, and
vice versa.
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7473 to
offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it is necessary to take a very fast measurement. Setting Bit 4 of
Configuration Register 2 (Reg. 0x73) turns averaging off.
Channel
Voltage Channel
Remote Temperature 1
Remote Temperature 2
Local Temperature
Measurement Time
0.7 ms
7 ms
7 ms
1.3 ms
Channel Selected
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1, averaging off.
<6> = 1, single-channel convert mode.
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> selects ADC channel for single-channel convert mode.
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Reg. 0x6A to Reg. 0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all PWM
outputs run at 100% duty cycle or the maximum PWM duty
cycle (Reg. 0x38, Reg. 0x39, and Reg. 0x3A) if bit 3 of
Configuration Register 4, Reg. 0x7D is set. The fans remain
running at this speed until the temperature drops below
THERM minus hysteresis; this can be disabled by setting the
boost bit in Configuration Register 3, Bit 2, Reg. 0x78. The
hysteresis value for that THERM limit is the value programmed
into the hysteresis registers (Reg. 0x6D and Reg. 0x6E). The
default hysteresis value is 4°C.
THERM LIMIT
HYSTERESIS (°C)
TEMPERATURE
FANS
100%
Figure 25. THERM Limit Operation
Rev. 0 | Page 18 of 76
04686-027
Table 8. Conversion Time with Averaging Disabled
Bits <7:5> Reg. 0x55
101
110
111
ADT7473
LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
Fan Limit Registers
Associated with each measurement channel on the ADT7473
are high and low limits. These can form the basis of system
status monitoring; a status bit can be set for any out-of-limit
condition and is detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default
8-Bit Limits
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default
The following is a list of 8-bit limits on the ADT7473.
Reg. 0x59 TACH3 Minimum High Byte = 0xFF default
Voltage Limit Registers
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default
Reg. 0x46 VCCP Low Limit = 0x00 default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF default
Reg. 0x47 VCCP High Limit = 0xFF default
Out-of-Limit Comparisons
Reg. 0x55 TACH1 Minimum High Byte = 0xFF default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF default
Once all limits have been programmed, the ADT7473 can be
enabled for monitoring. The ADT7473 measures all voltage and
temperature measurements in round-robin format and sets the
appropriate status bit for out-of-limit conditions. TACH
measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured
value is being compared to a high or low limit.
Reg. 0x48 VCC Low Limit = 0x00 default
Reg. 0x49 VCC High Limit = 0xFF default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temperature Low Limit = 0x01 default
Reg. 0x4F Remote 1 Temperature High Limit = 0xFF default
High Limit: > Comparison Performed
Low Limit: ≤ Comparison Performed
Reg. 0x6A Remote 1 THERM Limit = 0xA4 default
Voltage and temperature channels use a window comparator for
error detecting and, therefore, have high and low limits. Fan
speed measurements use only a low limit. This fan limit is
needed only in manual fan control mode.
Reg. 0x50 Local Temperature Low Limit = 0x01 default
Reg. 0x51 Local Temperature High Limit = 0xFF default
Reg. 0x6B Local THERM Limit = 0xA4 default
Analog Monitoring Cycle Time
Reg. 0x52 Remote 2 Temperature Low Limit = 0x01 default
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). By
default, the ADT7473 powers up with this bit set. The ADC
measures each analog input in turn and, as each measurement is
completed, the result is automatically stored in the appropriate
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration
Register 1.
Reg. 0x53 Remote 2 Temperature High Limit = 0xFF default
Reg. 0x6C Remote 2 THERM Limit = 0xA4 default
THERM Limit Register
Reg. 0x7A THERM Limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Because fans running under speed or stalled are normally the
only conditions of interest, only high limits exist for fan TACHs.
Because the fan TACH period is actually being measured,
exceeding the limit indicates a slow or stalled fan.
As the ADC is normally left to free-run in this manner, the time
taken to monitor all the analog inputs is normally not of
interest, because the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it can easily be calculated. The total number of channels
measured is
•
•
•
•
Rev. 0 | Page 19 of 76
One dedicated supply voltage input (VCCP)
Supply voltage (VCC pin)
Local temperature
Two remote temperatures
ADT7473
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature monitoring
with averaging disabled is 19 ms. The ADT7473 is a derivative
of the ADT7467. As a result, the total conversion time in the
ADT7473 is the same as the total conversion time of the
ADT7467, even though the ADT7473 has fewer monitored
channels.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Status Register 1 (Reg. 0x41), 1 means an out-of-limit event has
been flagged in Status Register 2. This means the user needs
only to read Status Register 2 when this bit is set. Alternatively,
Pin 5 or Pin 9 can be configured as an SMBALERT output. This
automatically notifies the system supervisor of an out-of-limit
condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared. Status register bits are sticky. Whenever a status bit
is set, indicating an out-of-limit condition, it remains set even if
the event that caused it has gone away (until read). The only
way to clear the status bit is to read the status register after the
event has gone away. Interrupt status mask registers (Reg. 0x74,
0x75) allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is set
in the interrupt status registers.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1, Local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below the
minimum speed. Alternatively, indicates the THERM limit has
been exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below the
minimum speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below the
minimum speed.
Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has
been exceeded.
SMBALERT Interrupt Behavior
The ADT7473 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
HIGH LIMIT
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
STICKY
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
04686-028
The results of limit comparisons are stored in Status Register 1
and Status Register 2. The status register bit for each channel
reflects the status of the last measurement and limit comparison
on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is
out of limits, the corresponding status register bit is set to 1.
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below the
minimum speed.
STATUS REGISTERS
Status Register 1 (Reg. 0x41)
Status Register 2 (Reg. 0x42)
Figure 26. SMBALERT and Status Bit Behavior
Figure 26 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are
referred to as sticky because they remain set until read by
software. This ensures that an out-of-limit event cannot be
missed if software is polling the device periodically. Note that
the SMBALERT output remains low for the entire duration that
a reading is out of limit and until the status register has been
read. This has implications on how software handles the
interrupt.
Bit 2 (VCC) = 1, VCC high or low limit has been exceeded.
Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded.
Rev. 0 | Page 20 of 76
ADT7473
Handling SMBALERT Interrupts
Interrupt Mask Register 2 (Reg. 0x75)
To prevent the system from being tied up servicing interrupts, it
is recommend handling the SMBALERT interrupt as follows:
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, Reg. 0x75).
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 27.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
HIGH LIMIT
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
TEMPERATURE
Table 11. Configuring Pin 5 as SMBALERT Output
CLEARED ON READ
(TEMP BELOW LIMIT)
Register
Configuration Register 3 (Reg. 0x78)
STICKY
STATUS BIT
Assigning THERM Functionality to a Pin
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
04686-029
SMBALERT
Bit Setting
<0> ALERT = 1
Figure 27. How Masking the Interrupt Source Affects SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Register 1 is located at Address 0x74; Interrupt
Mask Register 2 is located at Address 0x75. These allow
individual interrupt sources to be masked out to prevent
SMBALERT interrupts. Masking an interrupt source prevents
only the SMBALERT output from being asserted; the
appropriate status bit is set normally.
Pin 9 on the ADT7473 has four possible functions: SMBus
ALERT, THERM, GPIO, and TACH4. The user chooses the
required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.
Bit 0
00
01
10
11
Bit 1
Function
TACH4
THERM
SMBus ALERT
GPIO
Once Pin 9 is configured as THERM, it must be enabled (Bit 1,
Configuration Register 3 at Address 0x78).
THERM as an Input
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
When THERM is configured as an input, the ADT7473 can
time assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge system
performance. See the THERM Timer section for more
information.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.
Bit 0 (VCCP) = 1, masks SMBALERT for VCCP channel.
Rev. 0 | Page 21 of 76
ADT7473
The user can also set up the ADT7473 so that, when the
THERM pin is driven low externally, the fans run at 100%. The
fans run at 100% for the duration of the time the THERM pin is
pulled low. This is done by setting the BOOST bit (Bit 2) in
Configuration Register 3 (Address 0x78) to 1. This works only if
the fan is already running, for example, in manual mode when
the current duty cycle is above 0x00, or in automatic mode
when the temperature is above TMIN. If the temperature is below
TMIN or if the duty cycle in manual mode is set to 0x00, then
pulling the THERM low externally has no effect. See Figure 28
for more information.
TMIN
When using the THERM timer, be aware of the following.
After a THERM timer read (Reg. 0x79):
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
If the THERM timer is read during a THERM assertion, then
the following happens:
1.
The contents of the timer are cleared.
2.
Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3.
The THERM timer increments from 0.
4.
If the THERM timer limit (Reg. 0x7A) = 0x00, the F4P bit
is set.
THERM
THERM
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS BELOW TMIN.
04686-030
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS ABOVE TMIN AND FANS
ARE ALREADY RUNNING.
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
≤ 22.76ms
THERM
Figure 28. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
THERM TIMER
The ADT7473 has an internal timer to measure THERM
assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The 8-bit THERM timer register (Reg. 0x79) is designed so that
Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time has exceeded 45.52 ms, Bit 1 of the
THERM timer is set and Bit 0 now becomes the LSB of the
timer with a resolution of 22.76 ms (see Figure 29).
THERM ASSERTED
≥ 45.52ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
04686-031
The timer is started on the assertion of the ADT7473’s THERM
input and stopped when THERM is deasserted. The timer
counts THERM times cumulatively; that is, the timer resumes
counting on the next THERM assertion. The THERM timer
continues to accumulate THERM assertion times until the
timer is read (it is cleared on read) or until it reaches full scale.
If the counter reaches full scale, it stops at that reading until
cleared.
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
Figure 29.Understanding the THERM Timer
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7473 can generate SMBALERTs when a programmable THERM timer limit is exceeded. This allows the system
designer to ignore brief, infrequent THERM assertions, while
capturing longer THERM timer events. Register 0x7A is the
THERM timer limit register. This 8-bit register allows a limit
from 0 sec (first THERM assertion) to 5.825 sec to be set before
an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
Rev. 0 | Page 22 of 76
ADT7473
If the THERM timer value exceeds the THERM timer limit
value, the F4P bit (Bit 5) of Status Register 2 is set and an
SMBALERT is generated. The F4P bit (Bit 5) of Mask Register 2
(Reg. 0x75) masks out SMBALERTs if this bit is set to 1;
however, the F4P bit of Interrupt Status Register 2 still is set if
the THERM timer limit is exceeded.
Figure 30 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (Reg. 0x7A) causes an SMBALERT
to be generated on the first THERM assertion. A THERM timer
limit value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
2.
Assuming the fans are running, setting Bit 2 (BOOST bit)
of Configuration Register 3 (Reg. 0x78) causes all fans to
run at 100% duty cycle whenever THERM is asserted. This
allows fail-safe system cooling. If this bit is 0, the fans run
at their current settings and are not affected by THERM
events. If the fans are not already running when THERM is
asserted, the fans do not run at full speed.
3.
Configure Pin 9 as a THERM timer input.
4.
Setting Bit 1 (THERM timer enable) of Configuration
Register 3 (Reg. 0x78) enables the THERM timer
monitoring functionality. This is disabled on Pin 9 by
default.
Setting Bits 0 and 1 (PIN9FUNC) of Configuration
Register 4 (Reg. 0x7D) enables THERM timer/output
functionality on Pin 9 (Bit 1 of Configuration Register 3,
THERM, must also be set). Pin 9 can also be used as
TACH4.
Select whether THERM timer events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks
out SMBALERTs when the THERM timer limit value is
exceeded. This bit should be cleared if SMBALERTs based
on THERM events are required.
Configuring the THERM Behavior
1.
Select the desired fan behavior for THERM timer events.
Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative
THERM assertion time limit is exceeded. A value of 0x00
causes an SMBALERT to be generated on the first THERM
assertion.
5.
Setting Bits 5, 6, and 7 of Configuration Register 5 (0x7C)
makes THERM bidirectional. This means that if the
appropriate temperature channel exceeds the THERM
temperature limit, the THERM output asserts. If the
ADT7473 is not pulling THERM low, but THERM is
pulled low by an external device (such as a CPU
overtemperature signal), the THERM timer also times
THERM assertions.
If Bits 5, 6, and 7 of Configuration Register 5 (0x7C) are 0,
THERM is set as a timer input only.
Rev. 0 | Page 23 of 76
Select a THERM monitoring time.
This value specifies how often OS or BIOS level software
checks the THERM timer. For example, BIOS could read
the THERM timer once an hour to determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and >5.825
sec in Hour 3, this can indicate that system performance is
degrading significantly because THERM is asserting more
frequently on an hourly basis.
Alternatively, OS- or BIOS-level software can timestamp
when the system is powered on. If an SMBALERT is
generated due to the THERM timer limit being exceeded,
another timestamp can be taken. The difference in time
can be calculated for a fixed THERM timer limit time. For
example, if it takes one week for a THERM timer limit of
2.914 sec to be exceeded and the next time it takes only one
hour, this is an indication of a serious degradation in
system performance.
ADT7473
THERM
TIMER LIMIT
(REG. 0x7A)
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
728.32ms
364.16ms THERM TIMER
(REG. 0x79)
182.08ms
91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
F4P BIT (BIT 5)
STATUS REGISTER 2
SMBALERT
LATCH
RESET
CLEARED
ON READ
1 = MASK
04686-032
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Figure 30. Functional Block Diagram of ADT7473’s THERM Monitoring Circuitry
Configuring the THERM Pin as Bidirectional
THERM LIMIT
0.25°C
In addition to monitoring THERM as an input, the ADT7473
can optionally drive THERM low as an output. When
PROCHOT is bidirectional, THERM can be used to throttle the
processor by asserting PROCHOT. The user can preprogram
system-critical thermal limits. If the temperature exceeds a
thermal limit by 0.25°C, THERM asserts low. If the temperature
is still above the thermal limit on the next monitoring cycle,
THERM stays low. THERM remains asserted low until the
temperature is equal to or below the thermal limit. Because the
temperature for that channel is measured only once for every
monitoring cycle after THERM asserts, it is guaranteed to
remain low for at least one monitoring cycle.
THERM LIMIT
The THERM pin can be configured to assert low, if the
Remote 1, local, or Remote 2 THERM temperature limits are
exceeded by 0.25°C. The THERM temperature limit registers
are at Registers 0x6A, 0x6B, and 0x6C, respectively. Setting
Bits 5, 6, and 7 of Configuration Register 5 (0x7C) makes
THERM bidirectional for the Remote 1, local, and Remote 2
temperature channels, respectively. Figure 31 shows how the
THERM pin asserts low as an output in the event of a critical
overtemperature.
TEMP
MONITORING
CYCLE
04686-033
THERM
Figure 31. Asserting THERM as an Output,
Based on Tripping THERM Limits
An alternative method of disabling THERM is to program the
THERM temperature limit to –64°C or less in Offset 64 mode,
or −128°C or less in twos complement mode; that is, for
THERM temperature limit values less than –63°C or –128°C,
respectively, THERM is disabled. THERM can also be disabled
by setting Bit 1 of Configuration Register 3 (0x78) to 0.
Rev. 0 | Page 24 of 76
ADT7473
FAN DRIVE USING PWM CONTROL
The ADT7473 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. For 4-wire fans, the PWM drive might need
only a pull-up resistor. In many cases, the 4-wire fan PWM
input has a built-in pull-up resistor.
Ensure that the base resistor is chosen so that the transistor is
saturated when the fan is powered on.
The ADT7473 PWM frequency can be set to a selection of low
frequencies or a single high PWM frequency. The low
frequency options are usually used for 3-wire fans, while the
high frequency option is usually used with 4-wire fans.
Figure 34 shows a typical drive circuit for 4-wire fans. As the
PWM input on 4-wire fans is usually internally pulled up to a
voltage greater than 3.6 V (the max voltage allowed on the
ADT7473 PWM output), the PWM output should be clamped
to 3.3 V using a Zener diode.
12V
10kΩ
TACH
10kΩ
ADT7473
12V
FAN
TACH
4.7kΩ
1N4148
3.3V
665Ω
Q1
MMBT2222
PWM
Figure 33. Driving a 3-Wire Fan Using an NPN Transistor
12V 12V
12V, 4-WIRE FAN
10kΩ
TACH
Figure 32 shows how to drive a 3-wire fan using PWM control.
12V
VCC
10kΩ
4.7kΩ
12V
12V
04686-035
For 3-wire fans, a single N-channel MOSFET is the only drive
device required. The specifications of the MOSFET depend on
the maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA; therefore, SOT devices
can be used where board space is a concern. In desktops, fans
can typically draw 250 mA to 300 mA each. If you drive several
fans in parallel from a single PWM output or drive larger server
fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should
have a gate voltage drive, VGS < 3.3 V, for direct interfacing to
the PWM_OUT pin. The MOSFET should also have a low on
resistance to ensure that there is not significant voltage drop
across the FET, which would reduce the voltage applied across
the fan and, therefore, the maximum operating speed of the fan.
Because 4-wire fans are powered continuously, the fan speed is
not switched on or off as with previous PWM driven/powered
fans. This enables it to perform better than 3-wire fans, especially for high frequency applications.
TACH
TACH
PWM
ADT7473
10kΩ
12V
FAN
PWM
1N4148
4.7kΩ
ADT7473
3.3V
3.3V
Figure 34. Driving a 4-Wire Fan
Q1
NDT3055L
04686-034
10kΩ
PWM
04686-036
TACH/AIN
10kΩ
Driving Two Fans from PWM3
Figure 32. Driving a 3-Wire Fan Using an N-Channel MOSFET
Figure 32 uses a 10 kΩ pull-up resistor for the TACH signal.
This assumes that the TACH signal is an open-collector from
the fan. In all cases, the TACH signal from the fan must be kept
below 3.6 V maximum to prevent damaging the ADT7473. If
uncertain as to whether the fan used has an open-collector or
totem pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section.
Figure 33 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher on resistance than MOSFETs. When
choosing a transistor, care should be taken to ensure that it
meets the fan’s current requirements.
The ADT7473 has four TACH inputs available for fan speed
measurement, but only three PWM drive outputs. If a fourth
fan is being used in the system, it should be driven from the
PWM3 output in parallel with the third fan. Figure 35 shows
how to drive two fans in parallel using low cost NPN
transistors. Figure 36 shows the equivalent circuit using a
MOSFET.
Because the MOSFET can handle up to 3.5 A, it is simply a
matter of connecting another fan directly in parallel with the
first. Care should be taken in designing drive circuits with
transistors and FETs to ensure the PWM pins are not required
to source current and that they sink less than the 8 mA
maximum current specified on the data sheet.
Rev. 0 | Page 25 of 76
ADT7473
Driving up to Three Fans from PWM3
Signal conditioning in the ADT7473 accommodates the slow
rise and fall times typical of fan tachometer outputs. The
maximum input signal range is 0 V to 3.6 V. In the event that
these inputs are supplied from fan outputs that exceed 0 V to
3.6 V, either resistive attenuation of the fan signal or diode
clamping must be included to keep inputs within an acceptable
range.
TACH measurements for fans are synchronized to particular
PWM channels, for example, TACH1 is synchronized to
PWM1. TACH3 and TACH4 are both synchronized to PWM3,
so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the
PWM3 output. This allows PWM3 to drive two or three fans. In
this case, the drive circuitry looks the same, as shown in
Figure 35 and Figure 36. The SYNC bit in Register 0x62 enables
this function.
Figure 37 to Figure 40 show circuits for most common fan
TACH outputs.
If the fan TACH output has a resistive pull-up to VCC, it can be
connected directly to the fan input, as shown in Figure 37.
Synchronization is not required in high frequency mode when
used with 4-wire fans.
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 3.6 V), the fan output can be clamped with a Zener
diode, as shown in Figure 38. The Zener diode voltage should
be chosen so that it is greater than VIH of the TACH input but
less than 3.6 V, allowing for the voltage tolerance of the Zener. A
value of between 3 V and 3.6 V is suitable.
<4> (SYNC) Enhance Acoustics Register 1 (Reg. 0x62)
SYNC = 1, synchronizes TACH2, TACH3, and TACH4 to
PWM3.
TACH Inputs
Pins 4, 6, 7, and 9 (when configured as TACH inputs) are opendrain TACH inputs intended for fan speed measurement.
12V
3.3V
3.3V
1N4148
ADT7473
TACH3
1kΩ
PWM3
3.3V
Q1
MMBT3904
2.2kΩ
10Ω
TACH4
3.3V
Q2
MMBT2222
04686-037
10Ω
Q3
MMBT2222
Figure 35. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
3.3V
10kΩ
TYPICAL
TACH4
3.3V
+V
+V
3.3V
ADT7473
TACH3
10kΩ
TYPICAL
TACH
3.3V
5V OR
12V FAN
3.3V
1N4148
TACH
5V OR
12V FAN
PWM3
Q1
NDT3055L
04686-038
10kΩ
TYPICAL
Figure 36. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Rev. 0 | Page 26 of 76
ADT7473
VCC
12V
PULL-UP
4.7kΩ
TYPICAL
FAN SPEED
COUNTER
TACH
ADT7473
04686-039
TACH
OUTPUT
Figure 37. Fan with TACH Pull-Up to VCC
VCC
TACH
ZD1*
<1kΩ
FAN SPEED
COUNTER
R1*
ADT7473
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC
Figure 38. Fan with TACH Pull-Up to Voltage > 3.6 V
(for example, 12 V) Clamped with Zener Diode
TACH
OUTPUT
ZD1
ZENER*
FAN SPEED
COUNTER
ADT7473
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC
04686-041
TACH
Figure 39. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Clamped with Zener and Resistor
Alternatively, a resistive attenuator can be used, as shown in
Figure 40. R1 and R2 should be chosen such that
2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 3.6 V
ADT7473
*SEE TEXT
The fan counter does not count the fan TACH output pulses
directly, because the fan speed could be less than 1,000 RPM
and it would take several seconds to accumulate a reasonably
large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the
input of a 16-bit counter for N periods of the fan TACH output
(Figure 41), so the accumulated count is actually proportional
to the fan tachometer period, and inversely proportional to the
fan speed.
N, the number of pulses counted, is determined by the settings
of the TACH pulses per revolution register (Register 0x7B).
This register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
CLOCK
The fan inputs have an input resistance of nominally 160 kΩ to
ground, which should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 are 120 kΩ and 47 kΩ,
respectively. This gives a high input voltage of 3.35 V.
R2*
FAN SPEED
COUNTER
Fan Speed Measurement
VCC
PULL-UP
4.7kΩ OR
TYPICAL
TACH
Figure 40. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,
Attenuated with R1/R2
If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a
totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 39.
12V
TACH
OUTPUT
04686-042
TACH
OUTPUT
PWM
TACH
1
2
3
4
Figure 41. Fan Speed Measurement
Rev. 0 | Page 27 of 76
04686-043
PULL-UP
4.7kΩ
TYPICAL
VCC
12V
04686-040
12V
ADT7473
Fan Speed Measurement Registers
Fan Speed Measurement Rate
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7473.
The fan TACH readings are normally updated once every
second.
Reg. 0x28 TACH1 Low Byte = 0x00 default
The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78),
when set, updates the fan TACH readings every 250 ms.
Reg. 0x29 TACH1 High Byte = 0x00 default
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, their associated dc bit in
Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source. For optimal results, the associated dc bit
should always be set when using 4-wire fans.
Reg. 0x2A TACH2 Low Byte = 0x00 default
Reg. 0x2B TACH2 High Byte = 0x00 default
Reg. 0x2C TACH3 Low Byte = 0x00 default
Reg. 0x2D TACH3 High Byte = 0x00 default
Calculating Fan Speed
Reg. 0x2E TACH4 Low Byte = 0x00 default
Reg. 0x2F TACH4 High Byte = 0x00 default
Assuming a fan with a two pulses per revolution (and two
pulses per revolution being measured), fan speed is calculated by
Reading Fan Speed from the ADT7473
Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading
The measurement of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read, preventing erroneous TACH readings.
The fan tachometer reading registers report back the number of
11.11 µs period clocks (90 kHz oscillator) gated to the fan speed
counter, from the rising edge of the first fan TACH pulse to the
rising edge of the third fan TACH pulse (assuming two pulses
per revolution are being counted). Because the device is
essentially measuring the fan TACH period, the higher the
count value, the slower the fan is actually running. A 16-bit fan
tachometer reading of 0xFFFF indicates either the fan has
stalled or is running very slowly (<100 RPM).
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of two
bytes.
Reg. 0x55 TACH1 Minimum High Byte = 0xFF default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default
Fan TACH Reading is the 16-bit fan tachometer reading.
Example
TACH1 High Byte (Reg. 0x29) = 0x17
TACH1 Low Byte (Reg. 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
RPM = (f × 60)/Fan 1 TACH Reading
RPM = (90000 × 60)/6143
High Limit: > Comparison Performed
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default
where:
Fan Speed = 879 RPM
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 TACH pulses
per revolution. Once the number of fan TACH pulses has been
determined, it can be programmed into the fan pulses per
revolution register (Reg. 0x7B) for each fan. Alternatively, this
register can be used to determine the number or pulses per
revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses per revolution
setting, the smoothest graph with the lowest ripple determines
the correct pulses per revolution value.
Reg. 0x57 TACH2 Minimum High Byte = 0xFF default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF default
Rev. 0 | Page 28 of 76
ADT7473
Fan Pulses per Revolution Register
Disabling Fan Startup Timeout
<1:0> Fan 1 default = 2 pulses per revolution.
Although fan startup makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up
times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1
(Reg. 0x40) disables the spin-up for two TACH pulses. Instead,
the fan spins up for the fixed time as selected in Reg. 0x5C to
Reg. 0x5E.
<3:2> Fan 2 default = 2 pulses per revolution.
<5:4> Fan 3 default = 2 pulses per revolution.
<7:6> Fan 4 default = 2 pulses per revolution.
00 = 1 pulse per revolution.
PWM Logic State
01 = 2 pulses per revolution.
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
10 = 3 pulses per revolution.
PWM1 Configuration (Reg. 0x5C)
11 = 4 pulses per revolution.
Fan Spin-Up
The ADT7473 has a unique fan spin-up function. It spins
the fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two TACH pulses are
detected, the PWM duty cycle goes to the expected running
value, for example, 33%. The advantage is that fans have
different spin-up characteristics and take different times to
overcome inertia. The ADT7473 runs the fans just fast enough
to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time.
Fan Startup Timeout
To prevent the generation of false interrupts as a fan spins up
(because it is below running speed), the ADT7473 includes a
fan startup timeout function. During this time, the ADT7473
looks for two TACH pulses. If two TACH pulses are not
detected, an interrupt is generated. Using Configuration
Register 4 (0x40) Bit 5 (FSPDIS), this functionality can be
changed (see the Disabling Fan Startup Timeout section).
<4> INV.
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
PWM2 Configuration (Reg. 0x5D)
<4> INV.
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
PWM3 Configuration (Reg. 0x5E)
<4> INV.
0 = Logic high for 100% PWM duty cycle.
1 = Logic low for 100% PWM duty cycle.
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Reg. 0x5F to Reg. 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively. In high frequency mode, the
PWM drive frequency is always 22.5 kHz.
High Frequency Mode PWM Drive
PWM1, 2, 3 Configuration (Reg. 0x5C, 0x5D, 0x5E)
Setting Bit 3 of Register 0x5F enables high frequency mode for
all fans.
<2:0> SPIN, startup timeout for PWM1 = 0x5C,
PWM2 = 0x5D and PWM3 = 0x5E.
PWM1 Frequency Registers (Reg. 0x5F to Reg. 0x61)
000 = No startup timeout
<2:0> FREQ
000 = 11.0 Hz
001 = 100 ms
001 = 14.7 Hz
010 = 250 ms default
010 = 22.1 Hz
011 = 400 ms
011 = 29.4 Hz
100 = 667 ms
100 = 35.3 Hz (default)
101 = 1 sec
101 = 44.1 Hz
110 = 2 sec
110 = 58.8 Hz
111 = 4 sec
111 = 88.2 Hz
Rev. 0 | Page 29 of 76
ADT7473
Fan Speed Control
The ADT7473 controls fan speed using automatic and manual
modes.
In automatic fan speed control mode, fan speed is automatically
varied with temperature and without CPU intervention, once
initial parameters are set up. The advantage of this is that, if the
system hangs, the user is guaranteed the system is protected
from overheating. The automatic fan speed control incorporates
a feature called dynamic TMIN calibration. This feature reduces
the design effort required to program the automatic fan speed
control loop. For more information and procedures on how to
program the automatic fan speed control loop and dynamic
TMIN calibration, see the Programming the Automatic Fan Speed
Control Loop section.
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.
FAN PRESENCE DETECT
This feature can be used to determine if a 4-wire fan is directly
connected to a PWM output. This feature does not work for
3-wire fans. To detect whether a 4-wire fan is connected directly
to a PWM output, the following must be performed in this order:
In manual fan speed control mode, the ADT7473 allows the
duty cycle of any PWM output to be manually adjusted. This
can be useful if the user wants to change fan speed in software
or adjust PWM duty cycle output for test purposes. Bits <7:5>
of Reg. 0x5C to Reg. 0x5E (PWM Configuration) control the
behavior of each PWM output.
PWM Configuration Registers (Reg. 0x5C to Reg. 0x5E)
<7:5> BHVR
111 = manual mode.
1.
Drive the appropriate PWM outputs to 100% duty
cycle.
2.
Set bit 0 of Configuration Register 2 (0x73).
3.
Wait 5 ms.
4.
Program the fans to run at a different speed if
necessary.
5.
Read the state of bits <3:1> of Configuration
Register 2 (0x73). The state of these bits reflects
whether a 4-wire fan is directly connected to the
PWM output.
Once under manual control, each PWM output can be manually updated by writing to Reg. 0x30 to Reg. 0x32 (PWMx
current duty cycle registers).
As the detection time only takes 5ms, programming the PWM
outputs to 100% and then back to its normal speed is not
noticeable in most cases.
Programming the PWM Current Duty Cycle Registers
Description of How Fan Presence Detect Works
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
Four-wire fans typically have an internal pull up to 4.75V ±10%,
which typically sources 5 mA. While the detection cycle is on,
an internal current sink is turned on, sinking current from the
fan’s internal pull-up. By driving some of the current from the
fan’s internal pull-up (~100μA) the logic buffer switches to a
defined logic state. If this state is high, a fan is present; if it is
low, no fan is present.
The value to be programmed into the PWMMIN register is given by
Value (decimal) = PWMMIN/0.39
Example 1: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWM Duty Cycle Registers
Reg. 0x30 PWM1 Duty Cycle = 0x00 (0% default)
Reg. 0x31 PWM2 Duty Cycle = 0x00 (0% default)
Reg. 0x32 PWM3 Duty Cycle = 0x00 (0% default)
The PWM input voltage should be clamped to 3.3 V. This
ensures the PWM output is not pulled to a voltage higher than
the max allowable voltage on that pin (3.6 V).
SLEEP STATES
The ADT7473 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states. If
using the dynamic TMIN mode, lowering the core voltage of the
processor changes the CPU temperature and the dynamics of
the system under dynamic TMIN control. Likewise, when
monitoring THERM, the THERM timer should be disabled
during these states.
Rev. 0 | Page 30 of 76
ADT7473
Dynamic TMIN Control Register 1 (Reg. 0X36) <1>
VCCPLO = 1
POWER-ON DEFAULT
When the ADT7473 is powered up, it polls the VCCP input.
When the VCCP voltage drops below the VCCP low limit, the
following occurs:
If VCCP stays below 0.75 V (the system CPU power rail is not
powered up), the ADT7473 assumes the functionality of the
default registers after the ADT7473 is addressed via any valid
SMBus transaction.
1.
Status Bit 1 (VCCP) in Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
4.
Dynamic TMIN control is disabled. This prevents TMIN from
being adjusted due to an S3 or S5 state.
5.
The ADT7473 is prevented from entering the shutdown
state.
Once the core voltage, VCCP, goes above the VCCP low limit,
everything is re-enabled, and the system resumes normal
operation.
XNOR TREE TEST MODE
If VCC goes high (the system processor power rail is powered
up), a fail-safe timer begins to count down. If the ADT7473 is
not addressed by any valid SMBus transactions before the failsafe timeout (4.6 sec) lapses, the ADT7473 drives the fans to full
speed. If the ADT7473 is addressed by a valid SMBus
transaction after this point, the fans stop, and the ADT7473
assumes its default settings and begins normal operation.
If VCCP goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7473 is addressed by a valid SMBus transaction before the
fail-safe timeout (4.6 sec) lapses, then the ADT7473 operates
normally, assuming the functionality of all the default registers.
See the flow chart in Figure 43.
The ADT7473 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Figure 42 shows the signals that are exercised in the XNOR tree
test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (Reg. 0x6F).
ADT7473 IS POWERED UP
Y
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
IS VCCP ABOVE 0.75V?
N
CHECK VCCP
Y
TACH1
TACH2
START FAIL-SAFE TIMER
TACH3
Y
TACH4
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
PWM2
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
Figure 42. XNOR Tree Test
N
RUNS THE FANS
TO FULL SPEED
Y
HAS THE ADT7473 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
Y
START UP THE
ADT7473 NORMALLY
SWITCH OFF FANS
Figure 43. Power-On Flow Chart
Rev. 0 | Page 31 of 76
04686-045
PWM1/XTO
04686-044
PWM3
FAIL-SAFE TIMER ELAPSES
AFTER THE FAIL-SAFE TIMEOUT
ADT7473
PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
To more efficiently understand the automatic fan speed control
loop, it is strongly recommended using the ADT7473
evaluation board and software while reading this section.
This section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step
guidance on effectively evaluating and selecting critical system
parameters. To optimize the system characteristics, the designer
needs to consider the system configuration, including the
number of fans, where they are located, and what temperatures
are being measured in the particular system.
The mechanical or thermal engineer who is tasked with the
system thermal characterization should also be involved at the
beginning of the process.
AUTOMATIC FAN CONTROL OVERVIEW
The ADT7473 can automatically control the speed of fans based
on the measured temperature. This is done independently of
CPU intervention once initial parameters are set up.
The ADT7473 has a local temperature sensor and two remote
temperature channels that can be connected to a CPU on-chip
thermal diode (available on Intel Pentium class and other
CPUs). These three temperature channels can be used as the
basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM).
Figure 44 gives a top-level overview of the automatic fan control
circuitry on the ADT7473. From a systems-level perspective, up
to three system temperatures can be monitored and used to
control three PWM outputs. The three PWM outputs can be
used to control up to four fans. The ADT7473 allows the speed
of four fans to be monitored. Each temperature channel has a
thermal calibration block, allowing the designer to individually
configure the thermal characteristics of each temperature
channel. For example, one can decide to run the CPU fan when
CPU temperature increases above 60°C, and a chassis fan when
the local temperature increases above 45°C. At this stage, the
designer has not assigned these thermal calibration settings to a
particular fan drive (PWM) channel. The right side of Figure 44
shows controls that are fan-specific. The designer has individual
control over parameters such as minimum PWM duty cycle, fan
speed failure thresholds, and even ramp control of the PWM
outputs. Automatic fan control, then, ultimately allows graceful
fan speed changes that are less perceptible to the system user.
PWM
MIN
100%
PWM
CONFIG
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
REMOTE 1
TEMP
TMIN
TRANGE
THERMAL CALIBRATION
TMIN
PWM
MIN
100%
TRANGE
THERMAL CALIBRATION
REMOTE 2
TEMP
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
LOCAL
TEMP
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
Figure 44. Automatic Fan Control Block Diagram
Rev. 0 | Page 32 of 76
TACH1
PWM
CONFIG
PWM
GENERATOR
PWM2
TACH2
PWM
CONFIG
PWM
GENERATOR
PWM3
TACH3
04686-046
THERMAL CALIBRATION
Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature.
Reducing fan speed can also decrease system current consumption. The automatic fan speed control mode is very flexible due
to the number of programmable parameters, including TMIN
and TRANGE. The TMIN and TRANGE values for a temperature
channel and, therefore, for a given fan, are critical because they
define the thermal characteristics of the system. The thermal
validation of the system is one of the most important steps in
the design process, so these values should be selected carefully.
ADT7473
STEP 1: HARDWARE CONFIGURATION
2.
During system design, the motherboard sensing and control
capabilities should be addressed early in the design stages.
Decisions about how these capabilities are used should involve
the system thermal/mechanical engineer. Consider the
following questions:
How many fans will be supported in the system, three or
four? This influences the choice of whether to use the
TACH4 pin or to reconfigure it for the THERM function.
3.
Is the CPU fan to be controlled using the ADT7473 or will
it run at full speed 100% of the time?
If run at 100%, this frees up a PWM output, but the system
is louder.
What ADT7473 functionality will be used?
•
PWM2 or SMBALERT?
•
TACH4 fan speed measurement or overtemperature
THERM function?
4.
This influences the assignment of the temperature
measurement channels to particular system thermal zones.
For example, locating the ADT7473 close to the VRM
controller circuitry allows the VRM temperature to be
monitored using the local temperature channel.
The ADT7473 offers multifunctional pins that can be
reconfigured to suit different system requirements and
physical layouts. These multifunction pins are software
programmable.
THERMAL CALIBRATION
Where will the ADT7473 be physically located in the
system?
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
REMOTE 2 =
CPU TEMP
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REAR CHASSIS
Figure 45. Hardware Configuration Example
Rev. 0 | Page 33 of 76
04686-047
1.
ADT7473
Recommended Implementation 1
Configuring the ADT7473, as in Figure 46, provides the system
designer with the following features:
•
CPU temperature measured using the Remote 1
temperature channel.
•
Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
•
Ambient temperature measured through the Remote 2
temperature channel.
•
Three TACH fan speed measurement inputs.
•
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
Bidirectional THERM pin allows the monitoring of
PROCHOT output from an Intel Pentium 4 processor, for
example, or can be used as an overtemperature THERM
output.
•
VRM temperature using local temperature sensor.
•
SMBALERT system interrupt output.
FRONT
CHASSIS
FAN
ADT7473
TACH2
PWM1
TACH1
CPU FAN
REAR
CHASSIS
FAN
PWM3
TACH3
D2+
D2–
THERM
PROCHOT
CPU
D1+
SDA
D1–
SCL
SMBALERT
GND
Figure 46. Recommended Implementation 1
Rev. 0 | Page 34 of 76
ICH
04686-048
AMBIENT
TEMPERATURE
ADT7473
STEP 2: CONFIGURING THE MUX
Automatic Fan Control Mux Options
After the system hardware configuration is determined, the fans
can be assigned to particular temperature channels. Not only
can fans be assigned to individual channels, but the behavior of
the fans is also configurable. For example, fans can be run
under automatic fan control, manually (under software
control), or at the fastest speed calculated by multiple
temperature channels. The mux is the bridge between
temperature measurement channels and the three PWM
outputs.
<7:5> (BHVR), Registers 0x5c, 0x5d, 0x5e.
Bits <7:5> (BHVR) of Registers 0x5C, 0x5D, and 0x5E (PWM
Configuration Registers) control the behavior of the fans
connected to the PWM1, PWM2, and PWM3 outputs. The
values selected for these bits determine how the mux connects a
temperature measurement channel to a PWM output.
The fastest speed calculated options pertain to controlling one
PWM output based on multiple temperature channels. The
thermal characteristics of the three temperature zones can be
set to drive a single fan. An example is the fan turning on when
Remote 1 temperature exceeds 60°C, or if the local temperature
exceeds 45°C.
000 = Remote 1 temperature controls PWMx
001 = Local temperature controls PWMx
010 = Remote 2 temperature controls PWMx
101 = Fastest speed calculated by local and Remote 2
temperature controls PWMx
110 = Fastest speed calculated by all three temperature
channels controls PWMx
Other Mux Options
<7:5> (BHVR), Registers 0x5c, 0x5d, 0x5e.
011 = PWMx runs full speed
100 = PWMx disabled (default)
111 = manual mode
PWMx is running under software control. In this mode,
PWM duty cycle registers (Registers 0x30 to 0x32) are
writable and control the PWM outputs.
MUX
PWM
MIN
100%
PWM
CONFIG
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 1 =
AMBIENT TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
REMOTE 2 =
CPU TEMP
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REAR CHASSIS
Figure 47. Assigning Temperature Channels to Fan Channels
Rev. 0 | Page 35 of 76
04686-049
THERMAL CALIBRATION
ADT7473
Mux Configuration Example
Example Mux Settings
This is an example of how to configure the mux in a system
using the ADT7473 to control three fans. The CPU fan sink is
controlled by PWM1, the front chassis fan is controlled by
PWM 2, and the rear chassis fan is controlled by PWM3. The
mux is configured for the following fan control behavior:
<7:5> (BHVR), PWM1 Configuration Register 0x5c.
•
101 = Fastest speed calculated by local and Remote 2
temperature controls PWM1
<7:5> (BHVR), PWM2 Configuration Register 0x5d.
000 = Remote 1 temperature controls PWM2
PWM1 (CPU fan sink) is controlled by the fastest speed
calculated by the local (VRM temperature) and Remote 2
(processor) temperature. In this case, the CPU fan sink is
also being used to cool the VRM.
<7:5> (BHVR), PWM3 Configuration Register 0x5e.
•
PWM2 (front chassis fan) is controlled by the Remote 1
temperature (ambient).
These settings configure the mux, as shown in Figure 48.
•
PWM3 (rear chassis fan) is controlled by the Remote 1
temperature (ambient).
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
MUX
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
PWM
MIN
0%
PWM
MIN
100%
TRANGE
PWM1
0%
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 48. Mux Configuration Example
Rev. 0 | Page 36 of 76
04686-050
THERMAL CALIBRATION
000 = Remote 1 temperature controls PWM3
ADT7473
STEP 3: TMIN SETTINGS FOR THERMAL
CALIBRATION CHANNELS
TMIN Registers
TMIN is the temperature at which the fans start to turn on under
automatic fan control. The speed at which the fan runs at TMIN is
programmed later. The TMIN values chosen are temperature
channel specific, for example, 25°C for ambient channel, 30°C
for VRM temperature, and 40°C for processor temperature.
Reg. 0x68, Local Temperature TMIN = 0x9A (90°C)
Reg. 0x67, Remote 1 Temperature TMIN = 0x9A (90°C)
TMIN is an 8-bit value, either twos complement or Offset 64, that
can be programmed in 1°C increments. A TMIN register is
associated with each temperature measurement channel:
Remote 1 local, and Remote 2 temperature. Once the TMIN value
is exceeded, the fan turns on and runs at the minimum PWM
duty cycle. The fan turns off once the temperature drops below
TMIN − THYST.
To overcome fan inertia, the fan is spun up until two valid
TACH rising edges are counted. See the Fan Startup Timeout
section for more details. In some cases, primarily for psychoacoustic reasons, it is desirable that the fan never switches off
below TMIN. Bits <7:5> of Enhanced Acoustics Register 1
(Reg. 0x62), when set, keep the fans running at the PWM
minimum duty cycle, if the temperature falls below TMIN.
Reg. 0x69, Remote 2 Temperature TMIN = 0x9A (90°C)
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN – THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN – THYST.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN – THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN – THYST.
PWM DUTYCYCLE
100%
0%
TMIN
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
PWM
MIN
0%
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 49. Understanding the TMIN Parameter
Rev. 0 | Page 37 of 76
04686-051
THERMAL CALIBRATION
ADT7473
STEP 4: PWMMIN FOR EACH PWM (FAN) OUTPUT
Programming the PWMMIN Registers
PWMMIN is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above TMIN.
Refer to Figure 50. For maximum system acoustic benefit,
PWMMIN should be set as low as possible. Depending on the fan
used, the PWMMIN setting is usually in the 20% to 33% duty
cycle range. This value can be found through fan validation.
The PWMMIN registers are 8-bit registers that allow the
minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
Value (decimal) = PWMMIN/0.39
Example 1: For a minimum PWM duty cycle of 50%,
100%
PWM DUTY CYCLE
The value to be programmed into the PWMMIN register is given by
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
Example 2: For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 54 (hex)
PWMMIN
0%
PWMMIN Registers
04686-052
TEMPERATURE
TMIN
Figure 50. PWMMIN Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan
characteristics can be set up differently. As a result, Fan 1 driven
by PWM1 can have a different PWMMIN value than that of Fan 2
connected to PWM2. Figure 51 illustrates this as PWM1MIN
(front fan) is turned on at a minimum duty cycle of 20%, while
PWM2MIN (rear fan) turns on at a minimum of 40% duty cycle.
However, both fans turn on at exactly the same temperature,
defined by TMIN.
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
% fanspeed = PWM duty cycle × 10
STEP 5: PWMMAX FOR PWM (FAN) OUTPUTS
100%
PWMMAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For
maximum system acoustic benefit, PWMMAX should be as low as
possible, but should be capable of maintaining the processor
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to 100%
for fail-safe cooling. Refer to Figure 52.
M2
PW
PW
PWM2MIN
M1
PWM1MIN
0%
TMIN
TEMPERATURE
Figure 51. Operating Two Different Fans
from a Single Temperature Channel
04686-053
PWM DUTY CYCLE
Reg. 0x64, PWM1 Minimum Duty Cycle = 0x80 (50% default)
Reg. 0x65, PWM2 Minimum Duty Cycle = 0x80 (50% default)
Reg. 0x66, PWM3 Minimum Duty Cycle = 0x80 (50% default)
There is a PWMMAX limit for each fan channel. The default value
of this register is 0xFF and thus has no effect unless it is
programmed.
Rev. 0 | Page 38 of 76
ADT7473
STEP 6: TRANGE FOR TEMPERATURE CHANNELS
TRANGE is the range of temperature over which automatic fan
control occurs once the programmed TMIN temperature is
exceeded. TRANGE is a temperature slope, not an arbitrary value,
that is, a TRANGE of 40°C holds true only for PWMMIN = 33%. If
PWMMIN is increased or decreased, the effective TRANGE changes.
Refer to Figure 53.
PWMMAX
PWMMIN
0%
TEMPERATURE
100%
PWM DUTY CYCLE
Figure 52. PWMMAX Determines Maximum PWM Duty Cycle
Below the THERM Temperature Limit
Programming the PWMMAX Registers
The PWMMAX registers are 8-bit registers that allow the
maximum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the maximum PWM
duty cycle to be set in steps of 0.39%.
0%
TMIN
TEMPERATURE
Figure 53. TRANGE Parameter Affects Cooling Slope
The value to be programmed into the PWMMAX register is
given by
The TRANGE or fan control slope is determined by the following
procedure:
Value (decimal) = PWMMAX/0.39
Example 1: For a maximum PWM duty cycle of 50%,
Value (decimal) – 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
1.
Determine the maximum operating temperature for that
channel (for example, 70°C).
2.
Determine experimentally the fan speed (PWM duty cycle
value) that does not exceed the temperature at the worstcase operating points (for example, 70°C is reached when
the fans are running at 50% PWM duty cycle).
3.
Determine the slope of the required control loop to meet
these requirements.
4.
Can graphically program and visualize this functionality
using the ADT7473 evaluation software. Ask your local
Analog Devices representative for details.
Example 2: For a minimum PWM duty cycle of 75%,
Value (decimal) = 75/0.39 = 85 (decimal)
Value = 192 (decimal) or C0 (hex)
PWMMAX Registers
Reg. 0x38, PWM1 Maximum Duty Cycle = 0xFF (100% default)
Reg. 0x39, PWM2 Maximum Duty Cycle = 0xFF (100% default)
Reg. 0x3A, PWM3 Maximum Duty Cycle = 0xFF
(100% default)
PWMMIN
04686-055
TMIN
04686-054
TRANGE
Figure 54 shows how adjusting PWMMIN affects TRANGE.
100%
PWM DUTY CYCLE
See the Note on Fan Speed and PWM Duty Cycle.
50%
33%
0%
30°C
40°C
TMIN
Figure 54. Adjusting PWMMIN Affects TRANGE
Rev. 0 | Page 39 of 76
04686-056
PWM DUTY CYCLE
100%
ADT7473
TRANGE is implemented as a slope, which means that as PWMMIN
is changed, TRANGE changes, but the actual slope remains the
same. The higher the PWMMIN value, the smaller the effective
TRANGE, that is, the fan reaches full speed (100%) at a lower
temperature. Figure 55 shows how increasing PWMMIN changes
the effective TRANGE.
Example 3: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 33% duty cycle = 85 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE /170
TMAX = 30°C + (100% − 33%) × 40°C/170
TMAX = 30°C + (255 − 85) × 40°C/170
TMAX = 70°C (effective TRANGE = 40°C)
Example 4: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 50% duty cycle = 128 (decimal).
PWM DUTY CYCLE
100%
TMAX = TMIN + (Max DC − Min DC) × TRANGE /170
TMAX = 30°C + (100% − 50%) × 40°C/170
TMAX = 30°C + (255 − 128) × 40°C/170
TMAX = 60°C (effective TRANGE = 30°C)
50%
33%
25%
Selecting a TRANGE Slope
10%
The TRANGE value can be selected for each temperature channel:
Remote 1, local, and Remote 2 temperature. Bits <7:4> (TRANGE)
of Registers 0x5F to 0x61 define the TRANGE value for each
temperature channel.
0%
45°C
54°C
TMIN
04686-057
30°C
40°C
Table 12. Selecting a TRANGE Value
Figure 55. Increasing PWMMIN Changes Effective TRANGE
For a given TRANGE value, the temperature at which the fan runs
at full speed for different PWMMIN values can be easily
calculated as follows:
TMAX = TMIN + (Max DC − Min DC) × TRANGE /170
where:
TMAX is the temperature at which the fan runs full speed.
TMIN is the temperature at which the fan turns on.
Max DC is the maximum duty cycle (100%) = 255 decimal.
Min DC is equal to PWMMIN.
TRANGE is the duty PWM duty cycle vs. temperature slope.
Example 1: Calculate T, given that TMIN = 30°C, TRANGE = 40°C,
and PWMMIN = 10% duty cycle = 26 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE /170
TMAX = 30°C + (100% − 10%) × 40°C/170
TMAX = 30°C + (255 − 26) × 40°C/170
TMAX = 84°C (effective TRANGE = 54°C)
Example 2: Calculate TMAX, given that TMIN = 30°C, TRANGE =
40°C, and PWMMIN = 25% duty cycle = 64 (decimal).
TMAX = TMIN + (Max DC − Min DC) × TRANGE /170
TMAX = 30°C + (100% − 25%) × 40°C/170
TMAX = 30°C + (255 − 64) × 40°C/170
TMAX = 75°C (effective TRANGE = 45°C)
Bits <7:4>1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
TRANGE (°C)
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
32 (default)
40
53.33
80
Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures local
TRANGE; Register 0x61 configures Remote 2 TRANGE.
Summary of TRANGE Function
When using the automatic fan control function, the
temperature at which the fan reaches full speed can be
calculated by
TMAX = TMIN + TRANGE
Equation 1 holds true only when PWMMIN is equal to 33%
PWM duty cycle.
Rev. 0 | Page 40 of 76
(1)
ADT7473
Increasing or decreasing PWMMIN changes the effective TRANGE,
although the fan control still follows the same PWM duty cycle
to temperature slope. The effective TRANGE for different PWMMIN
values can be calculated using Equation 2.
TMAX = TMIN + (Max DC − Min DC) × TRANGE/170
(2)
The graphs in Figure 56 assume the fan starts from 0% PWM
duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN,
needs to be factored in to see how the loop actually performs in
the system. Figure 57 shows how TRANGE is affected when the
PWMMIN value is set to 20%. It can be seen that the fan actually
runs at about 45% fan speed when the temperature exceeds TMIN.
where:
2°C
100
2.5°C
90
(Max DC − Min DC) × TRANGE/170 is the effective TRANGE value.
Figure 56 shows PWM duty cycle vs. temperature for each
TRANGE setting. The lower graph shows how each TRANGE setting
affects fan speed vs. temperature. As indicated by the graph, the
effect on fan speed is nonlinear.
90
8°C
10°C
50
13.3°C
16°C
40
20°C
30
2°C
20
2.5°C
10
0
0
26.6°C
32°C
40°C
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
6.67°C
8°C
100
2°C
10°C
50
13.3°C
16°C
40
FAN SPEED (% OF MAX)
26.6°C
32°C
40°C
10
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
100
3.33°C
80
20°C
30
2.5°C
90
80°C
2°C
4°C
5°C
70
6.67°C
8°C
60
10°C
50
13.3°C
16°C
40
20°C
30
26.6°C
32°C
20
2.5°C
90
80
4°C
0
0
5°C
70
6.67°C
10°C
50
16°C
20°C
30
32°C
40°C
10
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
The following example shows how the different TMIN and TRANGE
settings can be applied to three different thermal zones. In this
example, the following TRANGE values apply:
26.6°C
20
20
Example: Determining TRANGE for Each Temperature
Channel
13.3°C
40
53.3°C
Figure 57. TRANGE and % Fan Speed Slopes with PWMMIN = 20%
8°C
60
40°C
10
3.33°C
53.3°C
20
40
60
80
TEMPERATURE ABOVE TMIN
100
120
80°C
04686-059
60
04686-058
PWM DUTY CYCLE (%)
6.67°C
60
5°C
20
FAN SPEED (% OF MAX)
5°C
70
4°C
70
0
0
4°C
3.33°C
80
0
0
PWM DUTY CYCLE (%)
See the Note on Fan Speed and PWM Duty Cycle.
100
3.33°C
80
TRANGE = 80°C for ambient temperature
TRANGE = 53.3°C for CPU temperature
TRANGE = 40°C for VRM temperature
Figure 56. TRANGE vs. Actual Fan Speed Profile
This example uses the mux configuration, described in Step 2:
Configuring the Mux, with the ADT7473 connected as shown
in Figure 58. Both CPU temperature and VRM temperature
drive the CPU fan connected to PWM1. Ambient temperature
drives the front chassis fan and rear chassis fan connected to
PWM2 and PWM3. The front chassis fan is configured to
run at PWMMIN = 20%. The rear chassis fan is configured to
run at PWMMIN = 30%. The CPU fan is configured to run at
PWMMIN = 10%.
Rev. 0 | Page 41 of 76
ADT7473
Note on 4-Wire Fans
The control range for 4-wire fans is much wider than that of
3-wire fans. In many cases, 4-wire fans can start with a PWM
drive of as little as 20%.
100
90
programmed into the hysteresis registers (0x6D and 0x6E). The
default hysteresis value is 4°C.
The TTHERM limit should be considered the maximum worst-case
80
PWM DUTY CYCLE (%)
The fans remain running at 100% until the temperature drops
below TTHERM − hysteresis, where hysteresis is the number
operating temperature of the system. Because exceeding any
TTHERM limit runs all fans at 100%, it has very negative acoustic
70
60
effects. Ultimately, this limit should be set up as a fail-safe, and
one should ensure it is not exceeded under normal system
operating conditions.
50
40
30
Note that the TTHERM limits are nonmaskable and affect the fan
20
speed no matter how automatic fan control settings are
configured. This allows some flexibility, because a TRANGE value
can be selected based on its slope, while a hard limit (such as
70°C), can be programmed as TMAX (the temperature at which
the fan reaches full speed) by setting TTHERM to that limit (for
10
0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE TMIN
100
example, 70°C).
FAN SPEED (% MAX RPM)
90
80
THERM Registers
70
Reg. 0x6A, Remote 1 THERM limit = 0xA4 (100°C default)
60
Reg. 0x6B, Local THERM limit = 0xA4 (100°C default)
50
Reg. 0x6C, Remote 2 THERM limit = 0xA4 (100°C default)
40
30
Hysteresis Registers
20
Reg. 0x6D, Remote 1, Local Hysteresis Register
0
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE ABOVE TMIN
04686-060
10
Figure 58. TRANGE and % Fan Speed Slopes for VRM, Ambient, and
CPU Temperature Channels
<7:4>, Remote 1 temperature hysteresis (4°C default).
<3:0>, Local temperature hysteresis (4°C default).
Reg. 0x6E, Remote 2 Temperature Hysteresis Register
<7:4>, Remote 2 temperature hysteresis (4°C default).
STEP 7: TTHERM FOR TEMPERATURE CHANNELS
TTHERM is the absolute maximum temperature allowed on a
temperature channel. When operating above this temperature, a
component such as the CPU or VRM might be beyond its safe
operating limit. When the temperature measured exceeds
TTHERM, all fans are driven at 100% PWM duty cycle (full speed)
Because each hysteresis setting is four bits, hysteresis values are
programmable from 1°C to 15°C. It is not recommended that
hysteresis values ever be programmed to 0°C, because this
disables hysteresis. In effect, this would cause the fans to cycle
between normal speed and 100% speed, creating unsettling
acoustic noise.
to provide critical system cooling.
Rev. 0 | Page 42 of 76
ADT7473
TRANGE
PWM DUTY CYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACH1
PWM
CONFIG
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
0%
CPU FAN SINK
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
04686-061
TMIN
Figure 59. How TTHERM Relates to Automatic Fan Control
STEP 8: THYST FOR TEMPERATURE CHANNELS
Hysteresis Registers
THYST is the amount of extra cooling a fan provides after the
temperature measured has dropped back below TMIN before the
fan turns off. The premise for temperature hysteresis (THYST) is
that, without it, the fan would merely chatter or cycle on and off
regularly whenever temperature is hovering at about the TMIN
setting.
Reg. 0x6D, Remote 1, Local Hysteresis Register
The THYST value chosen determines the amount of time needed
for the system to cool down or heat up as the fan is turning on
and off. Values of hysteresis are programmable in the range 1°C
to 15°C. Larger values of THYST prevent the fans from chattering
on and off. The THYST default value is set at 4°C.
<7:4>, Remote 2 temperature hysteresis (4°C default).
The THYST setting applies not only to the temperature hysteresis
for fan on/off, but the same setting is used for the TTHERM
<7:4>, Remote 1 temperature hysteresis (4°C default).
<3:0>, Local temperature hysteresis (4°C default).
Reg. 0x6E, Remote 2 Temp Hysteresis Register
In some applications, it is required that fans not turn off below
TMIN, but remain running at PWMMIN. Bits <7:5> of Enhanced
Acoustics Register 1 (Reg. 0x62) allow the fans to be turned off
or to be kept spinning below TMIN. If the fans are always on, the
THYST value has no effect on the fan when the temperature drops
below TMIN.
hysteresis value, described in Step 6: TRANGE for Temperature
Channels. Therefore, programming Registers 0x6D and 0x6E
sets the hysteresis for both fan on/off and the THERM function.
Rev. 0 | Page 43 of 76
ADT7473
TRANGE
PWM DUTYCYCLE
100%
0%
TTHERM
THERMAL CALIBRATION
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACH1
PWM
CONFIG
PWM
GENERATOR
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
0%
CPU FAN SINK
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
04686-062
TMIN
Figure 60. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
Enhance Acoustics Register 1 (Reg. 0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle
below TMIN − THYST.
Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle
below TMIN − THYST.
Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when
temperature is below TMIN − THYST.
Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle
below TMIN − THYST.
Rev. 0 | Page 44 of 76
ADT7473
VENTS
DYNAMIC TMIN CONTROL MODE
I/O CARDS
GOOD CPU AIRFLOW
FAN
VENTS
CPU
POWER
SUPPLY
CPU
POOR CPU
AIRFLOW
DRIVE
BAYS
DRIVE
BAYS
04686-063
VENTS
POOR VENTING =
POOR AIR EXCHANGE
Figure 61. Chassis Airflow Issues
Worst-Case Altitude
A computer can be operated at different altitudes. The
altitude affects the relative air density, which alters the
effectiveness of the fan cooling solution. For example,
comparing 40°C air temperature at 10,000 ft. to 20°C air
temperature at sea level, relative air density is increased by
40%. This means that the fan can spin 40% slower and
make less noise at sea level than at 10,000 ft. while keeping
the system at the same temperature at both locations.
•
Worst-Case Processor Power Consumption
This data sheet maximum does not necessarily reflect the
true processor power consumption. Designing for worstcase CPU power consumption can result in a processor
becoming overcooled (generating excess system noise).
•
Worst-Case Peripheral Power Consumption
The tendency is to design to data sheet maximums for
peripheral components (again overcooling the system).
•
Worst-Case Assembly
Every system manufactured is unique because of
manufacturing variations. Heat sinks may be loose fitting
or slightly misaligned. Too much or too little thermal
grease might be used, or variations in application pressure
for thermal interface material could affect the efficiency of
the thermal solution. Accounting for manufacturing
variations in every system is difficult; therefore, the system
must be designed for the worst case.
Worst-Case Fan
Due to manufacturing tolerances, fan speeds in RPM are
normally quoted with a tolerance of ±20%. The designer
needs to assume that the fan RPM can be 20% below
tolerance. This translates to reduced system airflow and
elevated system temperature. Note that fans 20% out of
tolerance can negatively impact system acoustics because
they run faster and generate more noise.
Worst-Case Chassis Airflow
The same motherboard can be used in a number of
different chassis configurations. The design of the chassis
and the physical location of fans and components
determine the system thermal characteristics. Moreover,
for a given chassis, the addition of add-in cards, cables, or
other system configuration options can alter the system
airflow and reduce the effectiveness of the system cooling
solution. The cooling solution can also be inadvertently
altered by the end user. (For example, placing a computer
against a wall can block the air ducts and reduce system
airflow.)
TA
θSA
HEAT
SINK
THERMAL
INTERFACE
MATERIAL
INTEGRATED
HEAT
SPREADER
TS
θCA
θTIMS
TTIM
θCTIM
TC
θCS
θJA
θTIMC
PROCESSOR
θJTIM
SUBSTRATE
EPOXY
THERMAL INTERFACE MATERIAL
TTIM
TJ
04686-064
System design must always allow for worst-case conditions. In
PC design, the worst-case conditions include, but are not
limited to the following:
•
POWER
SUPPLY
GOOD VENTING =
GOOD AIR EXCHANGE
Designing for Worst-Case Conditions
•
FAN
I/O CARDS
In addition to the automatic fan speed control mode described
in the Automatic Fan Control Overview section, the ADT7473
has a mode that extends the basic automatic fan speed control
loop. Dynamic TMIN control allows the ADT7473 to intelligently
adapt the system’s cooling solution for best system performance
or lowest possible system acoustics, depending on user or
design requirements. Use of dynamic TMIN control alleviates the
need to design for worst-case conditions and significantly
reduces system design and validation time.
•
FAN
Figure 62. Thermal Model
Although a design usually accounts for worst-case conditions in
all these cases, the actual system is almost never operated at
worst-case conditions. The alternative to designing for the
worst case is to use the dynamic TMIN control function.
Rev. 0 | Page 45 of 76
ADT7473
TEMPERATURE
TLOW
TMIN OPERATING THIGH TTHERM TRANGE
POINT
04686-065
Dynamic TMIN control mode builds upon the basic automatic
fan control loop by adjusting the TMIN value based on system
performance and measured temperature. This is important
because instead of designing for the worst case, the system
thermals can be defined as operating zones. ADT7473 can selfadjust its fan control loop to maintain either an operating zone
temperature or a system target temperature. For example, one
can specify that the ambient temperature in a system should be
maintained at 50°C. If the temperature is below 50°C, the fans
might not need to run, or might run very slowly. If the
temperature is higher than 50°C, the fans need to throttle up.
Figure 63 shows an overview of the parameters that affect the
operation of the dynamic TMIN control loop.
PWM DUTY CYCLE
Dynamic TMIN Control Overview
Figure 63. Dynamic TMIN Control Loop
The challenge presented by any thermal design is finding the
right settings to suit the system’s fan control solution. This can
involve designing for the worst case, followed by weeks of
system thermal characterization, and finally fan acoustic
optimization (for psycho-acoustic reasons). Getting the most
benefit from the automatic fan control mode involves characterizing the system to find the best TMIN and TRANGE settings for the
control loop, and the best PWMMIN value for the quietest fan
speed setting. Using the ADT7473’s dynamic TMIN control
mode, however, shortens the characterization time and
alleviates tweaking the control loop settings because the device
can self-adjust during system operation.
Dynamic TMIN control mode is operated by specifying the
operating zone temperatures required for the system.
Associated with this control mode are three operating point
registers, one for each temperature channel. This allows the
system thermal solution to be broken down into distinct
thermal zones. For example, CPU operating temperature is
70°C, VRM operating temperature is 80°C, and ambient
operating temperature is 50°C. The ADT7473 dynamically
alters the control solution to maintain each zone temperature as
closely as possible to its target operating point.
Operating Point Registers
Reg. 0x33, Remote 1 Operating Point = 0xA4 (100°C default)
Table 13 provides a brief description of each parameter.
Table 13. TMIN Control Loop Parameters
Parameter
TLOW
THIGH
TMIN
Operating
Point
TTHERM
TRANGE
Description
If the temperature drops below the TLOW limit, an
error flag is set in a status register and an
SMBALERT interrupt can be generated.
If the temperature exceeds the THIGH limit, an
error flag is set in a status register and an
SMBALERT interrupt can be generated.
The temperature at which the fan turns on
under automatic fan speed control.
The target temperature for a particular
temperature zone. The ADT7473 attempts to
maintain system temperature at about the
operating point by adjusting the TMIN parameter
of the control loop.
If the temperature exceeds this critical limit, the
fans can be run at 100% for maximum cooling.
Programs the PWM duty cycle vs. temperature
control slope.
Dynamic TMIN Control Programming
Because the dynamic TMIN control mode is a basic extension of
the automatic fan control mode, program the automatic fan
control mode parameters first, as described in Step 1 to Step 8,
then proceed with dynamic TMIN control mode programming.
Reg. 0x34, Local Operating Point = 0xA4 (100°C default)
Reg. 0x35, Remote 2 Operating Point = 0xA4 (100°C default)
Rev. 0 | Page 46 of 76
ADT7473
Programming Operating Point Registers
STEP 9: OPERATING POINTS FOR TEMPERATURE
CHANNELS
The operating point for each temperature channel is the optimal
temperature for that thermal zone. The hotter each zone is
allowed to be, the quieter the system, because the fans are not
required to run as fast. The ADT7473 increases or decreases fan
speeds as necessary to maintain the operating point temperature, allowing for system-to-system variation and removing the
need for worst-case design. If a sensible operating point value is
chosen, any TMIN value can be selected in the system characterization. If the TMIN value is too low, the fans run sooner than
required, and the temperature is below the operating point. In
response, the ADT7473 increases TMIN to keep the fans off
longer and to allow the temperature zone to get closer to the
operating point. Likewise, too high a TMIN value causes the
operating point to be exceeded, and in turn, the ADT7473
reduces TMIN to turn the fans on sooner to cool the system.
Operating Point Registers
Reg. 0x33, Remote 1 Operating Point = 0xA4 (100°C default)
Reg. 0x34, Local Operating Point = 0xA4 (100°C default)
Reg. 0x35, Remote 2 Operating Point = 0xA4 (100°C default)
OPERATING
POINT
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
PWM
MIN
0%
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
100%
TRANGE
PWM
GENERATOR
PWM1
0%
MUX
TMIN
PWM
CONFIG
PWM
MIN
100%
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
TACHOMETER 3
AND 4
MEASUREMENT
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
Figure 64. Operating Point Value Dynamically Adjusts Automatic Fan Control Settings
Rev. 0 | Page 47 of 76
04686-066
THERMAL CALIBRATION
There are three operating point registers, one for each
temperature channel. These 8-bit registers allow the operating
point temperatures to be programmed with 1°C resolution.
ADT7473
Short Cycle and Long Cycle
STEP 10: HIGH AND LOW LIMITS FOR
TEMPERATURE CHANNELS
The low limit defines the temperature at which the TMIN value
starts to be increased, if temperature falls below this value. This
has the net effect of reducing the fan speed, allowing the system
to get hotter. An interrupt can be generated when the temperature drops below the low limit.
The high limit defines the temperature at which the TMIN value
starts to be reduced, if temperature increases above this value.
This has the net effect of increasing fan speed to cool down the
system. An interrupt can be generated when the temperature
rises above the high limit.
Programming High and Low Limits
There are six limit registers; a high limit and low limit are
associated with each temperature channel. These 8-bit registers
allow the high and low limit temperatures to be programmed
with 1°C resolution.
Temperature Limit Registers
Reg. 0x4E, Remote 1 Temperature Low Limit = 0x01
Reg. 0x4F, Remote 1 Temperature High Limit = 0x7F
Reg. 0x50, Local Temperature Low Limit = 0x01
The ADT7473 implements two loops: a short cycle and a long
cycle. The short cycle takes place every n monitoring cycles.
The long cycle takes place every 2n monitoring cycles. The
value of n is programmable for each temperature channel. The
bits are located at the following register locations:
Remote 1 = CYR1 = Bits <2:0> of Calibration Control
Register 2 (Address = 0x37).
Local = CYL = Bits <5:3> of Calibration Control Register 2
(Address = 0x37).
Remote 2 = CYR2 = Bits <7:6> of Calibration Control Register
2 and Bit 0 of Calibration Control Register 1 (Address = 0x36).
Table 14. Cycle Bit Assignments
Code
000
001
010
011
100
101
110
111
Short Cycle
8 cycles
16 cycles
32 cycles
64 cycles
128 cycles
256 cycles
512 cycles
1024 cycles
(1 sec)
(2 sec)
(4 sec)
(8 sec)
(16 sec)
(32 sec)
(64 sec)
(128 sec)
Long Cycle
16 cycles
32 cycles
64 cycles
128 cycles
256 cycles
512 cycles
1024 cycles
2048 cycles
(2 sec)
(4 sec)
(8 sec)
(16 sec)
(32 sec)
(64 sec)
(128 sec)
(256 sec)
The basic premise is as follows:
Care should be taken when choosing the cycle time. A long
cycle time means that TMIN is updated less often. If your system
has very fast temperature transients, the dynamic TMIN control
loop will always be lagging. If a cycle time is chosen that is too
fast, the full benefit of changing TMIN might not be realized and
needs to change again on the next cycle; in effect, it is overshooting. It is necessary to carry out some calibration to
identify the most suitable response time.
1.
Figure 65 shows the steps taken during the short cycle.
Reg. 0x51, Local Temperature High Limit = 0x7F
Reg. 0x52, Remote 2 Temperature Low Limit = 0x01
Reg. 0x53, Remote 2 Temperature High Limit = 0x7F
How Dynamic TMIN Control Works
3.
As the temperature in that zone (Remote 1 temperature)
rises toward and exceeds the operating point temperature,
TMIN is reduced, and the fan speed increases.
As the temperature drops below the operating point
temperature, TMIN is increased, and the fan speed is
reduced.
WAIT n
MONITORING
CYCLES
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
OPERATING
POINT
TEMPERATURE
OP1
PREVIOUS
TEMPERATURE
MEASUREMENT
T1 (n – 1)
IS T1(n) >
(OP1 – HYS)
NO
DO NOTHING
YES
IS T1(n) – T1(n – 1)
≤ 0.25°C
DO NOTHING
(SYSTEM IS
COOLING OF
FOR CONSTANT)
YES
NO
IS T1(n) – T1(n – 1) = 0.5 – 0.75°C
IS T1(n) – T1(n – 1) = 1.0 – 1.75°C
However, the loop operation is not as simple as described in
these steps. A number of conditions govern the situations in
which TMIN can increase or decrease.
IS T1(n) – T1(n – 1) > 2.0°C
DECREASE TMIN BY 1°C
DECREASE TMIN BY 2°C
DECREASE TMIN BY 4°C
Figure 65. Short Cycle Steps
Rev. 0 | Page 48 of 76
04686-067
2.
Set the target temperature for the temperature zone, which
could be, for example, the Remote 1 thermal diode. This
value is programmed to the Remote 1 operating
temperature register.
ADT7473
Figure 66 shows the steps taken during the long cycle.
Once the temperature exceeds the operating temperature minus
the hysteresis (OP − Hyst), TMIN starts to decrease. This occurs
during the short cycle (see Figure 65). The rate at which TMIN
decreases depends on the programmed value of n. It also
depends on how much the temperature has increased between
this monitoring cycle and the last monitoring cycle, that is, if
the temperature has increased by 1°C, then TMIN is reduced by
2°C. Decreasing TMIN has the effect of increasing the fan speed,
thus providing more cooling to the system.
WAIT 2n
MONITORING
CYCLES
IS T1(n) > OP1
OPERATING
POINT
TEMPERATURE
OP1
YES
DECREASE TMIN
BY 1°C
NO
IS T1(n) < LOW TEMP LIMIT
AND
TMIN < HIGH TEMP LIMIT YES
AND
TMIN < OP1
AND
T1(n) > TMIN
NO
INCREASE
TMIN BY 1°C
DO NOT
CHANGE
04686-068
CURRENT
TEMPERATURE
MEASUREMENT
T1(n)
Figure 66. Long Cycle Steps
The following examples illustrate some of the circumstances
that might cause TMIN to increase, decrease, or stay the same.
Example: Normal Operation—No TMIN Adjustment
1.
2.
If measured temperature never exceeds the programmed
operating point minus the hysteresis temperature, then
TMIN is not adjusted, that is, it remains at its current setting.
If measured temperature never drops below the low
temperature limit, then TMIN is not adjusted.
THERM LIMIT
Once the temperature exceeds the operating temperature, the
long cycle causes TMIN to be reduced by 1°C every long cycle
while the temperature remains above the operating temperature. This takes place in addition to the decrease in TMIN that
would occur due to the short cycle. In Figure 68, because the
temperature is increasing at a rate ≤0.25°C per short cycle, no
reduction in TMIN takes place during the short cycle.
Once the temperature falls below the operating temperature,
TMIN stays the same. Even when the temperature starts to
increase slowly, TMIN stays the same because the temperature
increases at a rate ≤0.25°C per cycle.
Example: Increase TMIN Cycle
HIGH TEMP
LIMIT
OPERATING
POINT
If the temperature is slowly increasing only in the range
(OP − Hyst), that is, ≤0.25°C per short monitoring cycle, then
TMIN does not decrease. This allows small changes in
temperature in the desired operating zone without changing
TMIN. The long cycle makes no change to TMIN in the temperature range (OP − Hyst) because the temperature has not
exceeded the operating temperature.
When the temperature drops below the low temperature limit,
TMIN can increase in the long cycle. Increasing TMIN has the
effect of running the fan slower and, therefore, quieter. The long
cycle diagram in Figure 66 shows the conditions that need to be
true for TMIN to increase. A quick summary of those conditions
and the reasons they need to be true follows:
HYSTERESIS
LOW TEMP
LIMIT
TMIN
04686-069
ACTUAL
TEMP
TMIN can increase if
1.
The measured temperature falls below the low temperature
limit. This means the user must choose the low limit
carefully. It should not be so low that the temperature
never falls below it because TMIN would never increase, and
the fans would run faster than necessary.
2.
TMIN is below the high temperature limit. TMIN is never
allowed to increase above the high temperature limit. As a
result, the high limit should be sensibly chosen because it
determines how high TMIN can go.
3.
TMIN is below the operating point temperature. TMIN should
never be allowed to increase above the operating point
temperature because the fans would not switch on until the
temperature rose above the operating point.
4.
The temperature is above TMIN. The dynamic TMIN control
is turned off below TMIN.
Figure 67. Temperature Between Operating Point
and Low Temperature Limit
Because neither the operating point minus the hysteresis
temperature nor the low temperature limit has been exceeded,
the TMIN value is not adjusted, and the fan runs at a speed
determined by the fixed TMIN and TRANGE values defined in the
automatic fan speed control mode.
Example: Operating Point Exceeded—TMIN Reduced
When the measured temperature is below the operating point
temperature minus the hysteresis, TMIN remains the same.
Rev. 0 | Page 49 of 76
ADT7473
THERM
LIMIT
HIGH TEMP
LIMIT
OPERATING
POINT
HYSTERESIS
ACTUAL
TEMP
NO CHANGE IN TMIN HERE
DUE TO ANY CYCLE BECAUSE
T1(n) – T1 (n – 1) 0.25°C
AND T1(n) < OP = > TMIN
STAYS THE SAME
TMIN
LOW TEMP
LIMIT
DECREASE HERE DUE TO
LONG CYCLE ONLY
T1(n) – T1 (n – 1) 0.25°C
AND T1(n) > OP = > TMIN
DECREASES BY 1°C
EVERY LONG CYCLE
04686-070
DECREASE HERE DUE TO
SHORT CYCLE ONLY
T1(n) – T1 (n – 1) = 0.5°C
OR 0.75°C = > TMIN
DECREASES BY 1°C
EVERY SHORT CYCLE
Figure 68. Effect of Exceeding Operating Point Minus Hysteresis Temperature
Figure 69 shows how TMIN increases when the current temperature is above TMIN and below the low temperature limit, and
TMIN is below the high temperature limit and below the
operating point. Once the temperature rises above the low
temperature limit, TMIN stays the same.
THERM
LIMIT
If the temperature is below TMIN, the fan is switched off or
is running at minimum speed and dynamic TMIN control is
disabled.
3.
THERM
LIMIT
OPERATING
POINT
HYSTERESIS
HIGH TEMP
LIMIT
HYSTERESIS
HIGH TEMP
LIMIT
ACTUAL
TEMP
TMIN
TMIN
STEP 11: MONITORING THERM
Example: Preventing TMIN from Reaching Full Scale
Because TMIN is dynamically adjusted, it is undesirable for TMIN
to reach full scale (127°C) because the fan would never switch
on. As a result, TMIN is allowed to vary only within a specified
range:
The lowest possible value for TMIN is –127°C (twos
complement mode) or −64°C (Offset 64 mode).
2.
TMIN cannot exceed the high temperature limit.
TMIN PREVENTED
FROM INCREASING
Figure 70. TMIN Adjustments Limited by the High Temperature Limit
Figure 69. Increasing TMIN for Quieter Operation
1.
ACTUAL
TEMP
04686-072
LOW TEMP
LIMIT
LOW TEMP
LIMIT
04686-071
OPERATING
POINT
Using the operating point limit ensures that the dynamic TMIN
control mode is operating in the best possible acoustic position
while ensuring that the temperature never exceeds the maximum operating temperature. Using the operating point limit
allows TMIN to be independent of system-level issues because of
its self-corrective nature. In PC design, the operating point for
the chassis is usually the worst-case internal chassis
temperature.
The optimal operating point for the processor is determined by
monitoring the thermal monitor in the Intel Pentium 4 processor. To do this, the PROCHOT output of the Pentium 4 is
connected to the THERM input of the ADT7473.
Rev. 0 | Page 50 of 76
ADT7473
The operating point for the processor can be determined by
allowing the current temperature to be copied to the operating
point register when the PROCHOT output pulls the THERM
input low on the ADT7473. This gives the maximum
temperature at which the Pentium 4 can run before clock
modulation occurs.
Enabling the THERM Trip Point as the Operating Point
Bits <4:2> of dynamic TMIN Control Register 1 (Reg. 0x36)
enable/disable THERM monitoring to program the operating
point.
Dynamic TMIN Control Register 1 (0x36)
<2> PHTR2 = 1, copies the Remote 2 current temperature to
the Remote 2 operating point register, if THERM is asserted.
The operating point contains the temperature at which THERM
is asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTR2 = 0, ignores any THERM assertions. The Remote 2
operating point register reflects its programmed value.
<3> PHTL = 1, copies the local current temperature to the local
temperature operating point register if THERM is asserted. The
operating point contains the temperature at which THERM is
asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTL = 0, ignores any THERM assertions. The local
temperature operating point register reflects its programmed
value.
<4> PHTR1 = 1, copies the Remote 1 current temperature to
the Remote 1 operating point register if THERM is asserted.
The operating point contains the temperature at which THERM
is asserted. This allows the system to run as quietly as possible
without affecting system performance.
PHTR1 = 0, ignores any THERM assertions. The Remote 1
operating point register reflects its programmed value.
Enabling Dynamic TMIN Control Mode
Bits <7:5> of dynamic TMIN control Register 1 (Reg. 0x36)
enable/disable dynamic TMIN control on the temperature
channels.
Dynamic TMIN Control Register 1 (0x36)
<5> R2T = 1, enables dynamic TMIN control on the Remote 2
temperature channel. The chosen TMIN value is dynamically
adjusted based on the current temperature, operating point, and
high and low limits for this zone.
R2T = 0, disables dynamic TMIN control. The TMIN value chosen
is not adjusted and the channel behaves as described in the
Automatic Fan Control Overview section.
<6> LT = 1, enables dynamic TMIN control on the local
temperature channel. The chosen TMIN value is dynamically
adjusted based on the current temperature, operating point, and
high and low limits for this zone.
LT = 0, disables dynamic TMIN control. The TMIN value chosen is
not adjusted and the channel behaves as described in the
Automatic Fan Control Overview section.
<7> R1T = 1, enables dynamic TMIN control on the Remote 1
temperature channel. The chosen TMIN value is dynamically
adjusted based on the current temperature, operating point, and
high and low limits for this zone.
R1T = 0, disables dynamic TMIN control. The TMIN value chosen
is not adjusted, and the channel behaves as described in the
Automatic Fan Control Overview section.
ENHANCING SYSTEM ACOUSTICS
Automatic fan speed control mode reacts instantaneously to
changes in temperature; that is, the PWM duty cycle responds
immediately to temperature change. Any impulses in
temperature can cause an impulse in fan noise. For psychoacoustic reasons, the ADT7473 can prevent the PWM output
from reacting instantaneously to temperature changes.
Enhanced acoustic mode controls the maximum change in
PWM duty cycle at a given time. The objective is to prevent the
fan from cycling up and down, annoying the user.
Acoustic Enhancement Mode Overview
Figure 71 gives a top-level overview of the automatic fan control
circuitry on the ADT7473 and shows where acoustic enhancement fits in. Acoustic enhancement is intended as a postdesign
tweak made by a system or mechanical engineer evaluating best
settings for the system. Having determined the optimal settings
for the thermal solution, the engineer can adjust the system
acoustics. The goal is to implement a system that is acoustically
pleasing without causing user annoyance due to fan cycling. It is
important to realize that although a system might pass an
acoustic noise requirement specification (for example, 36 dB), if
the fan is annoying, it fails the consumer test.
Rev. 0 | Page 51 of 76
ADT7473
ACOUSTIC
ENHANCEMENT
PWM
CONFIG
PWM
MIN
100%
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TMIN
REMOTE 2 =
CPU TEMP
TRANGE
THERMAL CALIBRATION
PWM
MIN
100%
LOCAL =
VRM TEMP
TRANGE
THERMAL CALIBRATION
TMIN
TACHOMETER 1
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
0%
PWM
MIN
100%
TRANGE
PWM1
0%
MUX
TMIN
PWM
GENERATOR
TACHOMETER 2
MEASUREMENT
RAMP
CONTROL
(ACOUSTIC
ENHANCEMENT)
TACHOMETER 3
AND 4
MEASUREMENT
0%
TACH1
PWM
CONFIG
PWM
GENERATOR
CPU FAN SINK
PWM2
TACH2
PWM
CONFIG
FRONT CHASSIS
PWM
GENERATOR
PWM3
TACH3
REMOTE 1 =
AMBIENT TEMP
REAR CHASSIS
04686-073
THERMAL CALIBRATION
Figure 71. Acoustic Enhancement Smoothes Fan Speed Variations Under Automatic Fan Speed Control
Approaches to System Acoustic Enhancement
There are two different approaches to implementing system
acoustic enhancement: temperature-centric and fan-centric.
The temperature-centric approach involves smoothing transient
temperatures as they are measured by a temperature source (for
example, Remote 1 temperature). The temperature values used
to calculate the PWM duty cycle values are smoothed, reducing
fan speed variation. However, this approach causes an inherent
delay in updating fan speed and causes the thermal characteristics of the system to change. It also causes the system fans to
stay on longer than necessary because the fan’s reaction is
merely delayed. The user has no control over noise from
different fans driven by the same temperature source. Consider,
for example, a system in which control of a CPU cooler fan (on
PWM1) and a chassis fan (on PWM2) use Remote 1 temperature. Because the Remote 1 temperature is smoothed, both fans
are updated at exactly the same rate. If the chassis fan is much
louder than the CPU fan, there is no way to improve its
acoustics without changing the thermal solution of the CPU
cooling fan.
The fan-centric approach to system acoustic enhancement
controls the PWM duty cycle, driving the fan at a fixed rate (for
example, 6%). Each time the PWM duty cycle is updated, it is
incremented by a fixed 6%. As a result, the fan ramps smoothly
to its newly calculated speed. If the temperature starts to drop,
the PWM duty cycle immediately decreases by 6% at every
update. Therefore, the fan ramps smoothly up or down without
inherent system delay. Consider, for example, controlling the
same CPU cooler fan (on PWM1) and chassis fan (on PWM2)
using Remote 1 temperature. The TMIN and TRANGE settings have
already been defined in automatic fan speed control mode, that
is, thermal characterization of the control loop has been
optimized. Now the chassis fan is noisier than the CPU cooling
fan. Using the fan-centric approach, PWM2 can be placed into
acoustic enhancement mode independently of PWM1. The
acoustics of the chassis fan can, therefore, be adjusted without
affecting the acoustic behavior of the CPU cooling fan, even
though both fans are controlled by Remote 1 temperature. The
fan-centric approach is how acoustic enhancement works on
the ADT7473.
Enabling Acoustic Enhancement for Each PWM Output
Enhance Acoustics Register 1 (Reg. 0x62)
<3> = 1, enables acoustic enhancement on PWM1 output.
Enhance Acoustics Register 2 (Reg. 0x63)
<7> = 1, enables acoustic enhancement on PWM2 output.
<3> = 1, enables acoustic enhancement on PWM3 output.
Effect of Ramp Rate on Enhanced Acoustics Mode
The PWM signal driving the fan has a period, T, given by the
PWM drive frequency, f, because T = 1/f. For a given PWM
period, T, the PWM period is subdivided into 255 equal time
slots. One time slot corresponds to the smallest possible
increment in the PWM duty cycle. A PWM signal of 33% duty
cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3
× 255 time slots. Therefore, a 33% PWM duty cycle corresponds
to a signal that is high for 85 time slots and low for 170 time slots.
Rev. 0 | Page 52 of 76
ADT7473
85
TIME SLOTS
STEP 12: RAMP RATE FOR ACOUSTIC
ENHANCEMENT
170
TIME SLOTS
04686-074
PWM_OUT
33% DUTY
CYCLE
PWM OUTPUT
(ONE PERIOD)
= 255 TIME SLOTS
Figure 72. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable
from the values 1, 2, 3, 5, 8, 12, 24, and 48. The ramp rates are
discrete time slots. For example, if the ramp rate is 8, then eight
time slots are added to the PWM high duty cycle each time the
PWM duty cycle needs to be increased. If the PWM duty cycle
value needs to be decreased, it is decreased by eight time slots.
Figure 73 shows how the enhanced acoustics mode algorithm
operates.
The optimal ramp rate for acoustic enhancement can be found
through system characterization after the thermal optimization
has been finished. The effect of each ramp rate should be
logged, if possible, to determine the best setting for a given
solution.
Enhanced Acoustics Register 1 (Reg. 0x62)
<2:0> ACOU, selects the ramp rate for PWM1.
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots = 3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
Enhance Acoustics Register 2 (Reg. 0x63)
IS NEW PWM
VALUE >
PREVIOUS
VALUE?
NO
<2:0> ACOU3, selects the ramp rate for PWM3.
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots = 3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
INCREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
04686-075
YES
Figure 73. Enhanced Acoustics Algorithm
The enhanced acoustics mode algorithm calculates a new PWM
duty cycle based on the temperature measured. If the new
PWM duty cycle value is greater than the previous PWM value,
then the previous PWM duty cycle value is incremented by
either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the
settings of the enhance acoustics registers. If the new PWM
duty cycle value is less than the previous PWM value, the
previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24,
or 48 time slots. Each time the PWM duty cycle is incremented
or decremented, its value is stored as the previous PWM duty
cycle for the next comparison. A ramp rate of 1 corresponds to
one time slot, which is 1/255 of the PWM period. In enhanced
acoustics mode, incrementing or decrementing by 1 changes the
PWM output by 1/255 × 100%.
<6:4> ACOU2, selects the ramp rate for PWM2.
000 = 1 time slot = 35 sec
001 = 2 time slots = 17.6 sec
010 = 3 time slots = 11.8 sec
011 = 5 time slots = 7 sec
100 = 8 time slots = 4.4 sec
101 = 12 time slots = 3 sec
110 = 24 time slots = 1.6 sec
111 = 48 time slots = 0.8 sec
Another way to view the ramp rates is to measure the time it
takes for the PWM output to ramp up from 0% to 100% duty
cycle for an instantaneous change in temperature. This can be
tested by putting the ADT7473 into manual mode and changing
the PWM output from 0% to 100% PWM duty cycle. The PWM
output takes 35 sec to reach 100% when a ramp rate of 1 time
slot is selected.
Rev. 0 | Page 53 of 76
ADT7473
Figure 74 shows remote temperature plotted against PWM duty
cycle for enhanced acoustics mode. The ramp rate is set to 48,
which corresponds to the fastest ramp rate. Assume that a new
temperature reading is available every 115 ms. With these
settings, it takes approximately 0.76 sec to go from 33% duty
cycle to 100% duty cycle (full speed). Even though the
temperature increases very rapidly, the fan ramps up to full
speed gradually.
140
Figure 76 shows the PWM output response for a ramp rate of 2.
In this instance, the fan took about 17.6 sec to reach full
running speed.
140
120
RTEMP (°C)
120
100
100
80
120
80
100
60
RTEMP (°C)
60
PWM DUTY CYCLE (%)
120
40
100
40
80
80
20
20
60
0
0
PWM CYCLE (%)
TIME (s)
40
40
0
17.6
04686-078
60
Figure 76. Enhanced Acoustics Mode with Ramp Rate = 2
0
0
0
0.76
TIME (s)
04686-076
20
20
Figure 74. Enhanced Acoustics Mode with Ramp Rate = 48
Figure 75 shows how changing the ramp rate from 48 to 8
affects the control loop. The overall response of the fan is
slower. Because the ramp rate is reduced, it takes longer for the
fan to achieve full running speed. In this case, it takes
approximately 4.4 sec for the fan to reach full speed.
120
Figure 77 shows how the control loop reacts to temperature
with the slowest ramp rate. The ramp rate is set to 1, while all
other control parameters remain the same. With the slowest
ramp rate selected, it takes 35 sec for the fan to reach full speed.
140
120
RTEMP (°C)
120
100
100
80
80
60
140
RTEMP (°C)
60
PWM DUTY CYCLE (%)
120
100
40
40
100
20
PWM DUTY CYCLE (%)
20
80
0
60
0
60
TIME (s)
35
0
04686-079
80
Figure 77. Enhanced Acoustics Mode with Ramp Rate = 1
40
40
20
TIME (s)
4.4
0
04686-077
0
0
20
As Figure 74 to Figure 77 show, the rate at which the fan reacts
to temperature change is dependent on the ramp rate selected in
the enhanced acoustics registers. The higher the ramp rate, the
faster the fan reaches the newly calculated fan speed.
Figure 75. Enhanced Acoustics Mode with Ramp Rate = 8
Rev. 0 | Page 54 of 76
ADT7473
Figure 78 shows the behavior of the PWM output as temperature varies. As the temperature increases, the fan speed ramps
up. Small drops in temperature do not affect the ramp-up
function because the newly calculated fan speed is still higher
than the previous PWM value. Enhanced acoustics mode allows
the PWM output to be made less sensitive to temperature
variations. This is dependent on the ramp rate selected and
programmed into the enhanced acoustics registers.
The following sections list the ramp-up times when the SLOW
bit is set for each PWM output.
Enhanced Acoustics Register 1 (Reg. 0x62)
<2:0> ACOU, selects the ramp rate for PWM1.
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
90
80
PWM DUTY CYCLE (%)
70
60
50
Enhance Acoustics Register 2 (Reg. 0x63)
RTEMP (°C)
40
<2:0> ACOU3, selects the ramp rate for PWM3.
30
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
04686-080
20
10
0
Figure 78. How Fan Reacts to Temperature Variation
in Enhanced Acoustics Mode
Slower Ramp Rates
The ADT7473 can be programmed for much longer ramp times
by slowing the ramp rates. Each ramp rate can be slowed by a
factor of 4.
<6:4> ACOU2, selects the ramp rate for PWM2.
PWM1 Configuration Register (Reg. 0x5C)
<3> SLOW, 1 slows the ramp rate for PWM1 by 4.
PWM2 Configuration Register (Reg. 0x5D)
<3> SLOW, 1 slows the ramp rate for PWM2 by 4.
PWM3 Configuration Register (Reg. 0x5E)
<3> SLOW, 1 slows the ramp rate for PWM3 by 4.
Rev. 0 | Page 55 of 76
000 = 140 sec
001 = 70.4 sec
010 = 47.2 sec
011 = 28 sec
100 = 17.6 sec
101 = 12 sec
110 = 6.4 sec
111 = 3.2 sec
ADT7473
REGISTER TABLES
Table 15. ADT7473 Registers
Address
0x21
0x22
0x25
R/W
R
R
R
0x26
R
0x27
R
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
R
R
R
R
R
R
R
R
R/W
0x31
R/W
0x32
R/W
0x33
R/W
0x34
R/W
0x35
R/W
0x36
R/W
0x37
R/W
0x38
R/W
0x39
R/W
0x3A
R/W
0x3D
R
0x3E
R
0x3F
0x40
R
R/W
0x41
R
0x42
R
0x46
0x47
0x48
0x49
0x4E
R/W
R/W
R/W
R/W
R/W
0x4F
R/W
Description
VCCP Reading
VCC Reading
Remote 1
Temperature
Local
Temperature
Remote 2
Temperature
TACH 1 Low Byte
TACH 1 High Byte
TACH 2 Low Byte
TACH 2 High Byte
TACH 3 Low Byte
TACH 3 High Byte
TACH 4 Low Byte
TACH 4 High Byte
PWM1 Current
Duty Cycle
PWM2 Current
Duty Cycle
PWM3 Current
Duty Cycle
Remote 1
Operating Point
Local Temp
Operating Point
Remote 2
Operating Point
Dynamic TMIN
Control Reg. 1
Dynamic TMIN
Control Reg. 2
Max PWM 1 Duty
Cycle
Max PWM 2 Duty
Cycle
Max PWM 3 Duty
Cycle
Device ID
Register
Company ID
Number
Revision Number
Configuration
Register 1
Interrupt Status
Register 1
Interrupt Status
Register 2
VCCP Low Limit
VCCP High Limit
VCC Low Limit
VCC High Limit
Remote 1 Temp
Low Limit
Remote 1 Temp
High Limit
Bit 7
9
9
9
Bit 6
8
8
8
Bit 5
7
7
7
Bit 4
6
6
6
Bit 3
5
5
5
Bit 2
4
4
4
Bit 1
3
3
3
Bit 0
2
2
2
Default
0x00
0x00
0x01
9
8
7
6
5
4
3
2
0x01
9
8
7
6
5
4
3
2
0x01
7
15
7
15
7
15
7
15
7
6
14
6
14
6
14
6
14
6
5
13
5
13
5
13
5
13
5
4
12
4
12
4
12
4
12
4
3
11
3
11
3
11
3
11
3
2
10
2
10
2
10
2
10
2
1
9
1
9
1
9
1
9
1
0
8
0
8
0
8
0
8
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0x00
7
6
5
4
3
2
1
0
0xA4
Yes
7
6
5
4
3
2
1
0
0xA4
Yes
7
6
5
4
3
2
1
0
0xA4
Yes
R2T
LT
R1T
PHTR2
PHTL
PHTR1
VCCPLO
CYR2
0x00
Yes
CYR2
CYR2
CYL
CYL
CYL
CYR1
CYR1
CYR1
0x00
Yes
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0x73
7
6
5
4
3
2
1
0
0x41
VER
RES
VER
TODIS
VER
FSPDIS
VER
Vx1
STP
FSPD
STP
RDY
STP
LOCK
STP
STRT
0x68
0x01
OOL
R2T
LT
R1T
RES
VCC
VCCP
RES
0x00
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
RES
0x00
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
0x00
0xFF
0x00
0xFF
0x01
7
6
5
4
3
2
1
0
0xFF
Rev. 0 | Page 56 of 76
Lockable?
Yes
ADT7473
Address
0x50
R/W
R/W
0x51
R/W
0x52
R/W
0x53
R/W
0x54
R/W
0x55
R/W
0x56
R/W
0x57
R/W
0x58
R/W
0x59
R/W
0x5A
R/W
0x5B
R/W
0x5C
R/W
0x5D
R/W
0x5E
R/W
0x5F
R/W
0x60
R/W
0x61
R/W
0x62
R/W
0x63
R/W
0x64
R/W
0x65
R/W
0x66
R/W
0x67
R/W
0x68
0x69
R/W
R/W
0x6A
R/W
0x6B
R/W
Description
Local Temp Low
Limit
Local Temp High
Limit
Remote 2 Temp
Low Limit
Remote 2 Temp
High Limit
TACH1 Minimum
Low Byte
TACH1 Minimum
High Byte
TACH2 Minimum
Low Byte
TACH2 Minimum
High Byte
TACH3 Minimum
Low Byte
TACH3 Minimum
High Byte
TACH4 Minimum
Low Byte
TACH4 Minimum
High Byte
PWM1
Configuration
Register
PWM2
Configuration
Register
PWM3
Configuration
Register
Remote 1
TRANGE/PWM 1
Frequency
Local TRANGE/PWM
2 Frequency
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0x01
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0x01
7
6
5
4
3
2
1
0
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
7
6
5
4
3
2
1
0
0xFF
15
14
13
12
11
10
9
8
0xFF
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x82
Yes
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x82
Yes
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x82
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
Fan 1
FREQ
FREQ
FREQ
0xCC
Yes
RANGE
RANGE
RANGE
RANGE
HF/LF
Fan 2
FREQ
FREQ
FREQ
0xCC
Yes
Remote 2
TRANGE/PWM 3
Frequency
Enhance
Acoustics Reg. 1
Enhance
Acoustics Reg. 2
PWM1 Min Duty
Cycle
PWM2 Min Duty
Cycle
PWM3 Min Duty
Cycle
Remote 1 Temp
TMIN
Local Temp TMIN
Remote 2 Temp
TMIN
Remote 1 THERM
Temp Limit
Local THERM
Temp Limit
RANGE
RANGE
RANGE
RANGE
HF/LF
Fan 3
FREQ
FREQ
FREQ
0xCC
Yes
MIN3
MIN2
MIN1
SYNC
EN1
ACOU
ACOU
ACOU
0x00
Yes
EN2
ACOU2
ACOU2
ACOU2
EN3
ACOU3
ACOU3
0x00
Yes
7
6
5
4
3
2
ACOU
3
1
0
0x80
Yes
7
6
5
4
3
2
1
0
0x80
Yes
7
6
5
4
3
2
1
0
0x80
Yes
7
6
5
4
3
2
1
0
0x9A
Yes
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0x9A
0x9A
Yes
Yes
7
6
5
4
3
2
1
0
0xA4
Yes
7
6
5
4
3
2
1
0
0xA4
Yes
Rev. 0 | Page 57 of 76
Lockable?
ADT7473
Address
0x6C
R/W
R/W
0x6D
R/W
0x6E
R/W
0x6F
R/W
0x70
R/W
0x71
R/W
0x72
R/W
0x73
R/W
0x74
R/W
0x75
R/W
0x76
R/W
0x77
R/W
0x78
R/W
0x79
R
0x7A
R/W
0x7B
R/W
0x7C
R/W
0x7D
R/W
0x7E
0x7F
R
R
Description
Remote 2 THERM
Temp Limit
Remote 1 and
Local Temp/TMIN
Hysteresis
Remote 2
Temp/TMIN
Hysteresis
XNOR Tree Test
Enable
Remote 1
Temperature
Offset
Local
Temperature
Offset
Remote 2
Temperature
Offset
Configuration
Register 2
Interrupt Mask 1
Register
Interrupt Mask 2
Register
Extended
Resolution 1
Extended
Resolution 2
Configuration
Register 3
THERM Timer
Status Register
THERM Timer
Limit Register
TACH Pulses per
Revolution
Configuration
Register 5
Configuration
Register 4
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
Default
0xA4
Lockable?
Yes
HYSR1
HYSR1
HYSR1
HYSR1
HYSL
HYSL
HYSL
HYSL
0x44
Yes
HYSR2
HYSR2
HYSR2
HYRS
RES
RES
RES
RES
0x40
Yes
RES
RES
RES
RES
RES
RES
RES
XEN
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
7
6
5
4
3
2
1
0
0x00
Yes
SHDN
CONV
ATTN
AVG
FAN3
Detect
FAN2
Detect
FAN1
Detect
Fan
Presence
DT
0x00
Yes
OOL
R2T
LT
RIT
RES
VCC
VCCP
RES
0x00
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
RES
0x00
RES
RES
VCC
VCC
VCCP
VCCP
RES
RES
0x00
TDM2
TDM2
LTMP
LTMP
TDM1
TDM1
RES
RES
0x00
DC4
DC3
DC2
DC1
FAST
BOOST
THERM
0x00
TMR
TMR
TMR
TMR
TMR
TMR
TMR
ALERT
Enable
ASRT/TMR
O
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
0x00
FAN4
FAN4
FAN3
FAN3
FAN2
FAN2
FAN1
FAN1
0X55
R2
THERM
Local
THERM
R1
THERM
RES
GPIOP
GPIOD
Temp
Offset
TWOS
COMPL
0x00
Yes
RES
BpAtt
VCCP
RES
RES
Max/Full
on
THERM
THERM
Disable
Pin 9
Func
Pin 9 Func
0x00
Yes
0x00
0x00
Yes
Yes
Test Register 1
Test Register 2
Do not write to these registers
Do not write to these registers
Yes
0x00
Table 16. Voltage Reading Registers (Power-On Default = 0x00) 1
Register Address
0x21
0x22
R/W
Read-only
Read-only
Description
Reflects the voltage measurement at the VCCP input on Pin 14 (8 MSBs of reading). 2
Reflects the voltage measurement at the VCC input on Pin 3 (8 MSBs of reading). 3
1
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are
frozen.
2
If VCCPLo (Bit 1 of the Dynamic TMIN Control Register 1, 0x36) is set, VCCP can control the sleep state of the ADT7473.
3
VCC (Pin 3) is the supply voltage for the ADT7473.
Rev. 0 | Page 58 of 76
ADT7473
Table 17. Temperature Reading Registers (Power-On Default = 0x01) 1, 2
Register Address
0x25
0x26
0x27
R/W
Read-only
Read-only
Read-only
Description
Remote 1 temperature reading 3, 4 (8 MSB of reading).
Local temperature reading (8 MSB of reading).
Remote 2 temperature reading (8 MSB of reading).
1
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
3
In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
4
In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
2
Table 18. Fan Tachometer Reading Registers (Power-On Default = 0x00) 1
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
1
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
TACH1 low byte.
TACH1 high byte.
TACH2 low byte.
TACH2 high byte.
TACH3 low byte.
TACH3 high byte.
TACH4 low byte.
TACH4 high byte.
These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately
measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until
read. At power-on, these registers contain 0x0000 until the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring
while the fans are spinning up. A count of 0xFFFF indicates a fan is one of the following:
•
Stalled or blocked (object jamming the fan).
•
Failed (internal circuitry destroyed).
•
Not populated. (The ADT7473 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.)
•
Alternate function, for example, TACH4 reconfigured as THERM pin.
Table 19. Current PWM Duty Cycle Registers (Power-On Default = 0x00) 1
Register Address
0x30
0x31
0x32
1
R/W
Read/write
Read/write
Read/write
Description
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7473 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 20. Operating Point Registers (Power-On Default = 0xA4) 1, 2, 3
Register Address
0x33
0x34
0x35
1
2
3
R/W3
Read/write
Read/write
Read/write
Description
Remote 1 operating point register (default = 100°C).
Local temperature operating point register (default = 100°C).
Remote 2 operating point register (default = 100°C).
These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled.
The fans being controlled are adjusted to maintain temperature about an operating point.
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. 0 | Page 59 of 76
ADT7473
Table 21. Register 0x36—Dynamic TMIN Control Register 1 (Power-On Default = 0x00) 1
Bit
<0>
Name
CYR2
R/W
Read/write
<1>
VCCPLO
Read/write
<2>
PHTR1
Read/write
<3>
PHTL
Read/write
<4>
PHTR2
Read/write
<5>
R1T
Read/write
<6>
LT
Read/write
<7>
R2T
Read/write
1
Description
MSB of 3-Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic TMIN Control Register 2
(Reg. 0x37). These three bits define the delay time between making subsequent TMIN adjustments in the
control loop, in terms of the number of monitoring cycles. The system has associated thermal time constants
that need to be found to optimize the response of fans and the control loop.
VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP
low limit value (Reg. 0x46), the following occurs:
• Status Bit 1 in Status Register 1 is set.
• SMBALERT is generated, if enabled.
• PROCHOT monitoring is disabled.
• Dynamic TMIN control is disabled.
• The device is prevented from entering shutdown.
• Everything is re-enabled once VCCP increases above the VCCP low limit.
PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM is
asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to
run as quietly as possible without affecting system performance.
PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point register reflects its
programmed value.
PHTL = 1 copies the local channel’s current temperature to the local operating point register if THERM is
asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to
run as quietly as possible without affecting system performance.
PHTL = 0 ignores any THERM assertions on the THERM pin. The local temperature operating point register
reflects its programmed value.
PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM is
asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to
run as quietly as possible without affecting system performance.
PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point register reflects its
programmed value.
R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is
dynamically adjusted based on the current temperature, operating point, and high and low limits for this
zone.
R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as
described in the Fan Speed Control section.
LT=1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically
adjusted based on the current temperature, operating point, and high and low limits for this zone.
LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as
described in the Fan Speed Control section.
R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is
dynamically adjusted based on the current temperature, operating point, and high and low limits for this
zone.
R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as
described in the Fan Speed Control section.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 0 | Page 60 of 76
ADT7473
Table 22. Register 0x37—Dynamic TMIN Control Register 2 (Power-On Default = 0x00) 1
Bit
<2:0>
<5:3>
<7:6>
Name
CYR1
R/W
Read/write
CYL
Bits
000
001
010
011
100
101
110
111
Read/write
CYR2
Bits
000
001
010
011
100
101
110
111
Read/write
Bits
000
001
010
011
100
101
110
111
1
Description
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent TMIN
adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles. The
system has associated thermal time constants that need to be found to optimize the response of fans and
the control loop.
Decrease Cycle
Increase Cycle
8 cycles (1 sec)
16 cycles (2 sec)
16 cycles (2 sec)
32 cycles (4 sec)
32 cycles (4 sec)
64 cycles (8 sec)
64 cycles (8 sec)
128 cycles (16 sec)
128 cycles (16 sec)
256 cycles (32 sec)
256 cycles (32 sec)
512 cycles (64 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
3-Bit Local Temperature Cycle Value. These three bits define the delay time between making subsequent
TMIN adjustments in the control loop for the local temperature channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the response of
fans and the control loop.
Decrease Cycle
Increase Cycle
8 cycles (1 sec)
16 cycles (2 sec)
16 cycles (2 sec)
32 cycles (4 sec)
32 cycles (4 sec)
64 cycles (8 sec)
64 cycles (8 sec)
128 cycles (16 sec)
128 cycles (16 sec)
256 cycles (32 sec)
256 cycles (32 sec)
512 cycles (64 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic TMIN Control Register 1
(Reg. 0x36). These three bits define the delay time between making subsequent TMIN adjustments in the
control loop for the Remote 2 channel, in terms of number of monitoring cycles. The system has associated
thermal time constants that need to be found to optimize the response of fans and the control loop.
Decrease Cycle
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 23. Maximum PWM Duty Cycle (Power-On Default = 0xFF) 1, 2, 3
Register Address
0x38
0x39
0x3A
R/W2
Read/write
Read/write
Read/Write
Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1
These registers set the maximum PWM duty cycle of the PWM output.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
3
If Bit 3 of Configuration Register 4 (0x7D) is set, then on a THERM overtemperature event, fans go to their maximum programmed PWM value as programmed here.
If Bit 3 of Configuration Register 4 (0x7D) is 0, then on a THERM overtemperature event, fans go to 100% PWM.
2
Rev. 0 | Page 61 of 76
ADT7473
Table 24. Register 0x40—Configuration Register 1 (Power-On Default = 0x01)
Bit
<0>
Name
STRT 1
R/W
Read/write
<1>
LOCK
Write once
<2>
RDY
Read-only
<3>
<4>
FSPD
VxI
Read/write
Read/write
<5>
FSPDIS
Read/write
<6>
TODIS
Read/write
<7>
RES
1
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
This bit will not be locked when Bit 1 (LOCK bit) has been written.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become readonly and cannot be modified until the ADT7473 is powered down and powered up again. This prevents
rogue programs, such as viruses, from modifying critical system limit settings. (Lockable.)
This bit is set to 1 by the ADT7473 to indicate only that the device is fully powered up and ready to begin
system monitoring.
When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit is not locked at any time.
BIOS should set this bit to a 1 when the ADT7473 is configured to measure current from an ADI ADOPT® VRM
controller and to measure the CPU’s core voltage. This bit allows monitoring software to display CPU watts
usage. (Lockable.)
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan spinup timeout selected.
When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7473 to be used with
SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
Reserved.
Bit 0 (STRT) of 0x40, Configuration Register 1 remains writable after lock bit is set.
Table 25. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
<1>
Name
VCCP
R/W
Read-only
<2>
VCC
Read-only
<4>
RIT
Read-only
<5>
LT
Read-only
<6>
R2T
Read-only
<7>
OOL
Read-only
Description
VCCP = 1 indicates the VCCP high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
VCC = 1 indicates the VCC high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
RIT = 1 indicates the Remote 1 low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
LT = 1 indicates the local low or high temperature has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
R2T = 1 indicates the Remote 2 low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
OOL = 1 indicates an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all
status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage,
temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which saves the need to
read Status Register 2 every interrupt or polling cycle.
Table 26. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
<1>
Name
OVT
R/W
Read-only
<2>
FAN1
Read-only
<3>
FAN2
Read-only
<4>
FAN3
Read-only
<5>
F4P
Read-only
Read/write
Read-only
<6>
<7>
D1
D2
Read-only
Read-only
Description
OVT = 1 indicates one of the THERM overtemperature limits is exceeded. This bit is cleared on a read of the
status register when the temperature drops below THERM –THYST.
FAN1 = 1 indicates Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the
PWM1 output is off.
FAN2 = 1 indicates Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the
PWM2 output is off.
FAN3 = 1 indicates Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the
PWM3 output is off.
F4P = 1 indicates Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3
output is off.
When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO.
If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM
assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Rev. 0 | Page 62 of 76
ADT7473
Table 27. Voltage Limit Registers 1
Register Address
0x46
0x47
0x48
0x49
1
2
R/W
Read/write
Read/write
Read/write
Read/write
Description 2
VCCP low limit.
VCCP high limit.
VCC low limit.
VCC high limit.
Power-On Default
0x00
0xFF
0x00
0xFF
Setting the Configuration Register 1 lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 28. Temperature Limit Registers 1
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
1
2
R/W
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description 2
Remote 1 temperature low limit.
Remote 1 temperature high limit.
Local temperature low limit.
Local temperature high limit.
Remote 2 temperature low limit.
Remote 2 temperature high limit.
Power-On Default
0x01
0xFF
0x01
0xFF
0x01
0xFF
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 29. Fan Tachometer Limit Registers 1
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
1
R/W
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description
TACH1 minimum low byte.
TACH1 minimum high byte/single-channel ADC channel select.
TACH2 minimum low byte.
TACH2 minimum high byte.
TACH3 minimum low byte.
TACH3 minimum high byte.
TACH4 minimum low byte.
TACH4 minimum high byte.
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Exceeding any of the TACH limit registers by 1 indicates the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to
indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 30. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF)
Bits
<4:0>
Name
Reserved
R/W
Read-only
<7:5>
SCADC
Read/write
Description
These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode).
Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are used to
select the only channel from which the ADC makes measurements. Otherwise, these bits represent
Bits <7:5> of the TACH1 minimum high byte.
Rev. 0 | Page 63 of 76
ADT7473
Table 31. PWM Configuration Registers
Register Address
0x5C
0x5D
0x5E
Bit
<2:0>
Name
SPIN
R/W 1
Read/write
Read/write
Read/write
R/W
Read/write
<3>
<4>
SLOW
INV
Read/write
Read/write
<7:5>
BHVR
Read/write
1
Description
Power-On Default
PWM1 configuration.
0x82
PWM2 configuration.
0x82
PWM3 configuration.
0x82
Description
These bits control the startup timeout for PWMx. The PWM output stays high until two
valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during
the fan TACH measurement directly after the fan startup timeout period, then the TACH
measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH
minimum high and low bytes contain 0xFFFF or 0x0000, then the status register 2 bit is
not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty
cycle corresponds to a logic low output.
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = fastest speed calculated by all three temperature channel controls PWMx.
111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become writable.
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. 0 | Page 64 of 76
ADT7473
Table 32. TEMP TRANGE/PWM Frequency Registers
Register Address
0x5F
0x60
0x61
Bit
Name
<2:0>
FREQ
R/W 1
Read/write
Read/write
Read/write
R/W
Read/write
Register Address
R/W1
<3>
HF/LF
Read/write
<7:4>
RANGE
Read/write
1
Description
Power-On Default
Remote 1 TRANGE/PWM1 frequency.
0xCC
Local temperature TRANGE/PWM2 frequency.
0xCC
Remote 2 TRANGE/PWM3 frequency.
0xCC
Description
These bits control the PWMx frequency.
000 = 11.0 Hz.
001 = 14.7 Hz.
010 = 22.1 Hz.
011 = 29.4 Hz.
Description
100 = 35.3 Hz (default).
101 = 44.1 Hz.
110 = 58.8 Hz.
111 = 88.2 Hz.
HF/LF =1, enables high frequency PWM output for 4 wire fans. Once enabled, 3-wire
fan specific settings have no effect (that is, pulse stretching).
0x5F, HF/LF = 1 enables high frequency mode for Fan 1.
0x60, HF/LF = 1 enables high frequency mode for Fan 2.
0x61, HF/LF = 1 enables high frequency mode for Fan 3.
These bits determine the PWM duty cycle vs. the temperature slope for automatic fan
control.
0000 = 2°C.
0001 = 2.5°C.
0010 = 3.33°C.
0011 = 4°C.
0100 = 5°C.
0101 = 6.67°C.
0110 = 8°C.
0111 = 10°C.
1000 = 13.33°C.
1001 = 16°C.
1010 = 20°C.
1011 = 26.67°C.
1100 = 32°C (default).
1101 = 40°C.
1110 = 53.33°C.
1111 = 80°C
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
Rev. 0 | Page 65 of 76
ADT7473
Table 33. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00)
Bit
<2:0>
Name
ACOU
R/W 1
Read/write
<3>
<4>
EN1
SYNC
Read/write
Read/write
<5>
MIN
Read/write
<6>
MIN
Read/write
<7>
MIN3
Read/writ
1
Description
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to
its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature
enhances the acoustics of the fan being driven by the PWM1 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 4
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to
three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.
When the ADT7473 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or
at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM1 minimum duty cycle below TMIN – hysteresis.
When the ADT7473 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty
cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis
value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM 2 minimum duty cycle below TMIN – hysteresis.
When the ADT7473 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty
cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis
value.
0 = 0% duty cycle below TMIN – hysteresis.
1 = PWM3 minimum duty cycle below TMIN – hysteresis.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 66 of 76
ADT7473
Table 34. Register 0x63—Enhanced Acoustics Register 2 (Power-On Default = 0x00)
Bit
<2:0>
Name
ACOU
R/W 1
Read/write
<3>
<6:4>
EN3
ACOU2
Read/write
Read/write
<7>
EN2
Read/write
1
Description
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to
its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect
enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to
its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect
enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 35. PWM Minimum Duty Cycle Registers
Register Address
0x64
0x65
0x66
Bit
Name
<7:0>
PWM duty cycle
1
R/W 1
Read/write
Read/write
Read/write
R/W1
Read/write
Description
PWM1 minimum duty cycle.
PWM2 minimum duty cycle.
PWM3 minimum duty cycle.
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% duty cycle (fan off).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (fan full speed).
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
These registers become read-only when the ADT7473 is in automatic fan control mode.
Table 36. TMIN Registers 1
Register Address
0x67
0x68
0x69
R/W 2
Read/write
Read/write
Read/write
Description
Remote 1 temperature TMIN
Local temperature TMIN
Remote 2 temperature TMIN
1
Power-On Default
0x9A (90°C)
0x9A (90°C)
0x9A (90°C)
These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases
with temperature according to TRANGE.
2
These registers become read-only when the Configuration Register 1 lock bit is set. Any further attempts to write to these registers have no effect.
Rev. 0 | Page 67 of 76
ADT7473
Table 37. THERM Limit Registers 1
R/W 2
Read/write
Read/write
Read/write
Register Address
0x6A
0x6B
0x6C
Description
Remote 1 THERM limit.
Local THERM limit.
Remote 2 THERM limit.
Power-On Default
0xA4 (100°C)
0xA4 (100°C)
0xA4 (100°C)
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below THERM Limit – Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25°C can cause the THERM pin to assert low as an output.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
1
Table 38. Temperature/TMIN Hysteresis Registers 1
Register Address
0x6D
<3:0>
R/W 2
Read/write
HYSL
<7:4>
HYSR1
0x6E
<7:4>
Read/write
HYSR2
Description
Remote 1 and local temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of
hysteresis can be applied to the local temperature
AFC and dynamic TMIN control loops.
Remote 1 temperature hysteresis. 0°C to 15°C of
hysteresis can be applied to the Remote 1
temperature AFC and dynamic TMIN control loops.
Remote 2 temperature hysteresis.
Local temperature hysteresis. 0°C to 15°C of
hysteresis can be applied to the local temperature
AFC and dynamic TMIN control loops.
Power-On Default
0x44
0x40
1
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN
value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature channel.
The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the THERM
limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be
programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.
2
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers have no effect.
Table 39. XNOR Tree Test Enable
Register
Address
0x6F
<0>
R/W 1
Read/write
XEN
<7:1>
Reserved
1
Description
XNOR tree test enable register.
If the XEN bit is set to 1, the device enters the XNOR
tree test mode. Clearing the bit removes the device
from the XNOR tree test mode.
Unused. Do not write to these bits.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 40. Remote 1 Temperature Offset
Register Address
0x70
<7:0>
1
R/W 1
Read/write
Read/write
Description
Remote 1 temperature offset.
Allows a twos complement offset value to be automatically added to or
subtracted from the Remote 1 temperature reading. This is to compensate for
any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 41. Local Temperature Offset
Register Address
0x71
<7:0>
1
R/W 1
Read/write
Read/write
Description
Local temperature offset.
Allows a twos complement offset value to be automatically added to or
subtracted from the local temperature reading. LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 68 of 76
ADT7473
Table 42. Remote 2 Temperature Offset
R/W 1
Read/write
Read/write
Register Address
0x72
<7:0>
1
Description
Remote 2 temperature offset.
Allows a twos complement offset value to be automatically added to or
subtracted from the Remote 2 temperature reading. This is to compensate for
any inherent system offsets such as PCB trace resistance. LSB value = 0.5°C.
Power-On Default
0x00
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 43. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)
Bit
0
Name
FanPresenceDT
R/W 1
Read/write
1
2
3
4
Fan1 Detect
Fan2 Detect
Fan3 Detect
AVG
Read
Read
Read
Read/write
5
ATTN
Read/write
6
CONV
Read/write
7
SHDN
Read/write
1
Description
When FanPresenceDT=1, the state of bits <3:1> of 0x73 reflects the presence of a
4-wire fan on the appropriate TACH channel.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM 1 input.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM 2 input.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM 3 input.
AVG = 1, averaging on the temperature and voltage measurements is turned off.
This allows measurements on each channel to be made much faster.
ATTN = 1, the ADT7473 removes the attenuators from the VCCP input. The VCCP
input can be used for other functions such as connecting up external sensors.
CONV = 1, the ADT7473 is put into a single-channel ADC conversion mode. In this
mode, the ADT7473 can be made to read continuously from one input only, for
example, Remote 1 temperature. The appropriate ADC channel is selected by
writing to bits <7:5> of TACH1 minimum high byte register (0x55).
Bits <7:5> Reg. 0x55
000
Reserved.
001
VCCP.
010
VCC (3.3 V).
011
Reserved.
100
Reserved.
101
Remote 1 temperature.
110
Local temperature.
111
Remote 2 temperature.
SHDN = 1, ADT7473 goes into shutdown mode. All PWM outputs assert low (or
high depending on the state of the INV bit) to switch off all fans. The PWM current
duty cycle registers read 0x00 to indicate the fans are not being driven.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 44. Register 0x74—Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit
1
2
4
5
6
7
Name
VCCP
VCC
RIT
LT
R2T
OOL
R/W
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description
VCCP = 1, masks SMBALERT for out-of-limit conditions on the VCCP channel.
VCC = 1, masks SMBALERT for out-of-limit conditions on the VCC channel.
RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 1, masks SMBALERT for any out-of-limit condition in Status Register 2.
Rev. 0 | Page 69 of 76
ADT7473
Table 45. Register 0x75—Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit
1
2
3
4
5
Name
OVT
FAN1
FAN2
FAN3
F4P
R/W
Read only
Read/write
Read/write
Read/write
Read/writ
6
7
D1
D2
Read/write
Read/write
Description
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input, this
bit masks SMBALERT for a THERM timer event.
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 46. Register 0x76—Extended Resolution Register 1 1
Bit
<3:2>
<5:4>
1
Name
VCCP
VCC
R/W
Read-only
Read-only
Description
VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.
VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 47. Register 0x77—Extended Resolution Register 2 1
Bit
<3:2>
<5:4>
<7:6>
1
Name
TDM1
LTMP
TDM2
R/W
Read-only
Read-only
Read-only
Description
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 48. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit
<0>
Name
ALERT
R/W 1
Read/write
<1>
THERM
Read/write
<2>
BOOST
Read/write
<3>
FAST
Read/write
<4>
DC1
Read/write
<5>
DC2
Read/write
<6>
DC3
Read/write
<7>
DC4
Read/write
1
Description
ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-oflimit error conditions.
THERM Enable = 1 enables THERM functionality on Pin 9. Also determined by Bits 0 and 1 (PIN9FUNC) of
Configuration Register 4. Direction is controlled by bits 5, 6 and 7 of Configuration Register 5 (0x7C).
When THERM is asserted, if the fans are running and the boost bit is set, the fans run at full speed. THERM
can also be programmed so that a timer monitors the duration THERM has been asserted.
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement rate
from once per second to once every 250 ms (4 ×).
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc.
Setting this bit prevents pulse stretching, because it is not required for DC-driven motors.
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc.
Setting this bit prevents pulse stretching, because it is not required for DC-driven motors.
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven by dc.
Setting this bit prevents pulse stretching, because it is not required for DC-driven motors.
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven by dc.
Setting this bit prevents pulse stretching, because it is not required for DC-driven motors.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 70 of 76
ADT7473
Table 49. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit
<7:1>
Name
TMR
R/W
Read-only
<0>
ASRT/
TMR0
Read-only
Description
Times the duration THERM input is asserted. These seven bits read 0 until the THERM assertion time
exceeds 45.52 ms.
This bit is set high on the assertion of the THERM input, and is cleared on read. If the THERM assertion time
exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion
times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms.
Table 50. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit
<7:0>
Name
LIMT
R/W
Read/write
Description
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register
2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion
of the THERM input.
Table 51. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit
<1:0>
Name
FAN1
R/W
Read/write
<3:2>
FAN2
Read/write
<5:4>
FAN3
Read/write
<7:6>
FAN4
Read/write
Description
Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 =
11 = 4
Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan
pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (default)
10 = 3
11 = 4
Rev. 0 | Page 71 of 76
ADT7473
Table 52. Register 0x7C—Configuration Register 5 (Power-On Default = 0x00)
Bit
<0>
Name
2sC
<1>
TempOffset
<2>
GPIOD
<3>
GPIOP
<4>
<5>
RES
R1 THERM
R/W 1
Read/write
Read/write
Description
2sC = 1, sets the temperature range to twos complement temperature range.
2sC = 0, changes the temperature range to Offset 64. When this bit is changed, the ADT7473
interprets all relevant temperature register values as defined by this bit.
TempOffset = 0 Sets offset range to ±64°C at 0.5°C resolution.
TempOffset = 1 Sets offset range to ±128°C at 1°C resolution.
GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an
output (1).
GPIO polarity. When the GPIO function is enabled and is programmed as an output, this bit
determines whether the GPIO is active low (0) or high (1).
Reserved
R1 THERM = 1, THERM temperature limit functionality enabled for Remote 1 temperature channel;
that is, THERM is bidirectional. R1 THERM = 0, THERM is a timer input only.
THERM can also be disabled on any channel by
•
<6>
<7>
1
Local
THERM
R2 THERM
Read/write
Read/write
Writing −64˚C to the appropriate THERM temperature limit in Offset 64 mode.
•
Writing −128˚C to the appropriate THERM temperature limit in twos complement mode.
Local THERM = 1, THERM temperature limit functionality enabled for the local temperature channel;
that is, THERM is bidirectional. Local THERM = 0, THERM is a timer input only.
THERM can also be disabled on any channel by
•
Writing −64˚C to the appropriate THERM temperature limit in Offset 64 mode.
•
Writing −128˚C to the appropriate THERM temperature limit in two complement mode.
R2 THERM = 1, THERM temperature limit functionality enabled for Remote 2 temperature channel;
that is, THERM is bidirectional. R2 THERM = 0, THERM is a timer input only.
THERM can also be disabled on any channel by
•
Writing −64°C to the appropriate THERM temperature limit in Offset 64 mode.
•
Writing −128°C to the appropriate THERM temperature limit in twos complement mode.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 53. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)
Bit
<1:0>
Name
Pin9FUNC
R/W 1
Read/write
<2>
THERM
Disable
Max/Full
on THERM
Read/write
<3>
<4:5>
<6>
RES
BpAttVCCP
<7>
RES
1
Read/write
Read/write
Description
These bits set the functionality of Pin 9:
00 = TACH4 (default)
01 = THERM
10 = SMBALERT
11 = GPIO
THERM Disable = 1, disables THERM over temperature feature.
Max/Full on THERM = 0; when THERM temperature limit is exceeded, fans go to full speed.
Max/Full on THERM = 1; when THERM temperature limit is exceeded, fans go to max programmed fan
speed.
Max/Full on THERM = 1; when THERM limit is exceeded, fans go to max speed as defined in registers
0x38, 0x39, 0x3A.
Unused.
Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to
2.2965 V (0xFF).
Unused.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Rev. 0 | Page 72 of 76
ADT7473
Table 54. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit
<7:0>
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Table 55. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit
<7:0>
Name
Reserved
R/W
Read-only
Description
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not
be written to under normal operation.
Rev. 0 | Page 73 of 76
ADT7473
OUTLINE DIMENSIONS
0.193
BSC
9
16
0.154
BSC
1
0.236
BSC
8
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
0.050
0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 79. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7473ARQZ 1
ADT7473ARQZ-REEL1
ADT7473ARQZ-REEL71
EVAL-ADT7473EB
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 74 of 76
Package Option
RQ-16
RQ-16
RQ-16
ADT7473
NOTES
Rev. 0 | Page 75 of 76
ADT7473
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04686–0–6/05(0)
Rev. 0 | Page 76 of 76
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