MCP4911-E/P Datasheet

MCP4901/4911/4921
8/10/12-Bit Voltage Output Digital-to-Analog Converter
with SPI Interface
Features
Description
•
•
•
•
•
•
The MCP4901/4911/4921 devices are single channel
8-bit, 10-bit and 12-bit buffered voltage output
Digital-to-Analog Converters (DACs), respectively. The
devices operate from a single 2.7V to 5.5V supply with
an SPI compatible Serial Peripheral Interface. The user
can configure the full-scale range of the device to be
VREF or 2*VREF by setting the gain selection option bit
(gain of 1 of 2).
Applications
•
•
•
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Set Point or Offset Trimming
Precision Selectable Voltage Reference
Motor Control Feedback Loop
Digitally-Controlled Multiplier/Divider
Calibration of Optical Communication Devices
Related Products
P/N
DAC
Resolution
No. of
Channels
MCP4801
8
1
MCP4811
10
1
MCP4821
12
1
Voltage
Reference
(VREF)
Internal
(2.048V)
The user can shut down the device by setting the Configuration Register bit. In Shutdown mode, most of the
internal circuits are turned off for power savings, and
the output amplifier is configured to present a known
high resistance output load (500 ktypical.
The devices include double-buffered registers,
allowing synchronous updates of the DAC output using
the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable powerup.
The devices utilize a resistive string architecture, with
its inherent advantages of low Differential Non-Linearity (DNL) error and fast settling time. These devices are
specified over the extended temperature range
(+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4901/4911/4921 devices are available in the
PDIP, SOIC, MSOP and DFN packages.
Package Types
MCP4802
8
2
MCP4812
10
2
MCP4822
12
2
VDD 1
MCP4901
8
1
CS 2
MCP4911
10
1
MCP4921
12
1
MCP4902
8
2
MCP4912
10
2
MCP4922
12
2
8-Pin PDIP, SOIC, MSOP
External
Note: The products listed here have similar AC/DC
performances.
 2010 Microchip Technology Inc.
SCK 3
SDI 4
MCP49x1
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•
•
•
•
•
MCP4901: 8-Bit Voltage Output DAC
MCP4911: 10-Bit Voltage Output DAC
MCP4921: 12-Bit Voltage Output DAC
Rail-to-Rail Output
SPI Interface with 20 MHz Clock Support
Simultaneous Latching of the DAC Output
with LDAC Pin
Fast Settling Time of 4.5 µs
Selectable Unity or 2x Gain Output
External Voltage Reference Input
External Multiplier Mode
2.7V to 5.5V Single-Supply Operation
Extended Temperature Range: -40°C to +125°C
DFN-8 (2x3)*
8 VOUT
VDD 1
8 VOUT
7 VSS
6 VREF
CS 2
SCK 3
EP 7 VSS
9 6 VREF
5 LDAC
SDI 4
5 LDAC
MCP4901: 8-bit single DAC
MCP4911: 10-bit single DAC
MCP4921: 12-bit single DAC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS22248A-page 1
MCP4901/4911/4921
Block Diagram
LDAC
CS
SDI
SCK
Interface Logic
Power-on
Reset
Input
Register
VDD
VSS
DAC
Register
VREF
String
DAC
Buffer
Gain
Logic
Output
Op Amp
Output
Logic
VOUT
DS22248A-page 2
 2010 Microchip Technology Inc.
MCP4901/4911/4921
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ............................................................................................................. 6.5V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
All inputs and outputs w.r.t ................VSS –0.3V to VDD+0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ...............................................±50 mA
Current at Output Pins ...............................................±25 mA
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins  4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ) . .........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Operating Voltage
VDD
2.7
—
5.5
Supply Current
IDD
—
175
350
µA
125
250
µA
VDD = 5V
VDD = 3V
VREF input is unbuffered, all digital
inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 0x000h
—
—
3.3
6
µA
—
2.0
—
V
8
—
—
Bits
Power Requirements
Software Shutdown Current ISHDN_SW
Power-On-Reset Threshold
VPOR
Power-on Reset circuit remains on
DC Accuracy
MCP4901
Resolution
n
INL Error
INL
-1
±0.125
1
LSb
DNL
DNL
-0.5
±0.1
+0.5
LSb
n
10
—
—
Bits
Note 1
MCP4911
Resolution
INL Error
INL
-3.5
±0.5
3.5
LSb
DNL
DNL
-0.5
±0.1
+0.5
LSb
n
12
—
—
Bits
Note 1
MCP4921
Resolution
Note 1:
2:
INL Error
INL
-12
±2
12
LSb
DNL
DNL
-0.75
±0.2
+0.75
LSb
Note 1
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
 2010 Microchip Technology Inc.
DS22248A-page 3
MCP4901/4911/4921
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C.
Parameters
Offset Error
Offset Error Temperature
Coefficient
Sym
Min
Typ
Max
Units
Conditions
VOS
—
±0.02
1
% of
FSR
VOS/°C
—
0.16
—
ppm/°C
-45°C to 25°C
+25°C to 85°C
Code = 0x000h
—
-0.44
—
ppm/°C
gE
—
-0.10
1
% of
FSR
G/°C
—
-3
—
ppm/°C
Input Range – Buffered
Mode
VREF
0.040
—
VDD –
0.040
V
Input Range – Unbuffered
Mode
VREF
0
—
VDD
V
Input Impedance
RVREF
—
165
—
k
Input Capacitance –
Unbuffered Mode
CVREF
—
7
—
pF
Multiplier Mode
-3 dB Bandwidth
fVREF
—
450
—
kHz
VREF = 2.5V ±0.2Vp-p,
Unbuffered, G = 1
fVREF
—
400
—
kHz
VREF = 2.5V ±0.2 Vp-p,
Unbuffered, G = 2
THDVREF
—
-73
—
dB
VREF = 2.5V ±0.2Vp-p,
Frequency = 1 kHz
VOUT
—
0.01 to
VDD –
0.04
—
V
Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Gain Error
Gain Error Temperature
Coefficient
Code = 0xFFFh, not including
offset error
Input Amplifier (VREF Input)
Multiplier Mode –
Total Harmonic Distortion
Note 2
Code = 2048
VREF = 0.2 Vp-p, f = 100 Hz and
1 kHz
Unbuffered Mode
Output Amplifier
Output Swing
Phase Margin
m
—
66
—
Degrees
Slew Rate
SR
—
0.55
—
V/µs
ISC
—
15
24
mA
tsettling
—
4.5
—
µs
DAC-to-DAC Crosstalk
—
10
—
nV-s
Major Code Transition
Glitch
—
45
—
nV-s
Digital Feedthrough
—
10
—
nV-s
Analog Crosstalk
—
10
—
nV-s
Short Circuit Current
Settling Time
Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
Note 1:
2:
1 LSB change around major carry
(0111...1111 to 1000...0000)
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
DS22248A-page 4
 2010 Microchip Technology Inc.
MCP4901/4911/4921
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Voltage
VDD
2.7
—
5.5
Input Current
IDD
—
200
—
µA
VREF input is unbuffered, all digital inputs are grounded, all analog
outputs (VOUT) are unloaded.
Code = 0x000h
—
5
—
µA
—
1.85
—
V
8
—
—
Bits
Power Requirements
Software Shutdown Current ISHDN_SW
Power-on Reset Threshold
VPOR
DC Accuracy
MCP4901
Resolution
n
INL Error
INL
±0.25
LSb
DNL
DNL
±0.2
LSb
Note 1
MCP4911
Resolution
n
10
—
—
Bits
INL Error
INL
±1
LSb
DNL
DNL
±0.2
LSb
Note 1
MCP4921
Resolution
n
12
—
—
Bits
INL Error
INL
±4
LSb
DNL
DNL
±0.25
LSb
Note 1
VOS
—
±0.02
—
% of FSR
VOS/°C
—
-5
—
ppm/°C
gE
—
-0.10
—
% of FSR
G/°C
—
-3
—
ppm/°C
Input Range – Buffered
Mode
VREF
—
0.040 to
VDD0.040
—
V
Input Range – Unbuffered
Mode
VREF
0
—
VDD
V
Input Impedance
RVREF
—
174
—
k
Input Capacitance –
Unbuffered Mode
CVREF
—
7
—
pF
Multiplying Mode
-3 dB Bandwidth
fVREF
—
450
—
kHz
VREF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 1x
fVREF
—
400
—
kHz
VREF = 2.5V ±0.1 Vp-p,
Unbuffered, G = 2x
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
Code = 0x000h
+25°C to +125°C
Code = 0xFFFh, not including
offset error
Input Amplifier (VREF Input)
Note 1:
2:
Note 1
Code = 2048,
VREF = 0.2 Vp-p, f = 100 Hz and
1 kHz
Unbuffered Mode
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
 2010 Microchip Technology Inc.
DS22248A-page 5
MCP4901/4911/4921
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain
(G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters
Sym
Min
Typ
Max
Units
THDVREF
—
—
—
dB
VREF = 2.5V ±0.1Vp-p,
Frequency = 1 kHz
Output Swing
VOUT
—
0.01 to
VDD –
0.04
—
V
Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD – 40 mV)
Phase Margin
m
—
66
—
Degrees
Slew Rate
SR
—
0.55
—
V/µs
ISC
—
17
—
mA
tsettling
—
4.5
—
µs
Within 1/2 LSB of final value from
1/4 to 3/4 full-scale range
Major Code Transition
Glitch
—
45
—
nV-s
1 LSB change around major carry
(0111...1111 to 1000...0000)
Digital Feedthrough
—
10
—
nV-s
Multiplying Mode - Total
Harmonic Distortion
Conditions
Output Amplifier
Short Circuit Current
Settling Time
Dynamic Performance (Note 2)
Note 1:
2:
Guaranteed monotonic by design over all codes.
This parameter is ensured by design, and not 100% tested.
DS22248A-page 6
 2010 Microchip Technology Inc.
MCP4901/4911/4921
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Parameters
Sym
Min
Typ
Max
Units
Schmitt Trigger High Level
Input Voltage (All digital input
pins)
VIH
0.7 VDD
—
—
V
Schmitt Trigger Low Level Input
Voltage (All digital input pins)
VIL
—
—
0.2 VDD
V
VHYS
—
0.05 VDD
—
Input Leakage Current
ILEAKAGE
-1
—
1
A
LDAC = CS = SDI =
SCK = VREF = VDD or VSS
Digital Pin Capacitance
(All inputs/outputs)
CIN,
COUT
—
10
—
pF
VDD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency
FCLK
—
—
20
MHz
Clock High Time
tHI
15
—
—
ns
Note 1
Clock Low Time
tLO
15
—
—
ns
Note 1
tCSSR
40
—
—
ns
Applies only when CS falls with
CLK high (Note 1)
tSU
15
—
—
ns
Note 1
Data Input Hold Time
tHD
10
—
—
ns
Note 1
SCK Rise to CS Rise Hold
Time
tCHS
15
—
—
ns
Note 1
CS High Time
tCSH
15
—
—
ns
Note 1
tLD
100
—
—
ns
Note 1
tLS
40
—
—
ns
Note 1
tIDLE
40
—
—
ns
Note 1
Hysteresis of Schmitt Trigger
Inputs
CS Fall to First Rising CLK
Edge
Data Input Setup Time
LDAC Pulse Width
LDAC Setup Time
SCK Idle Time before CS Fall
Note 1:
Conditions
TA = +25°C (Note 1)
This parameter is ensured by design and not 100% tested.
tCSH
CS
tIDLE
tCSSR
Mode 1,1
tHI
tLO
tCHS
SCK Mode 0,0
tSU
tHD
SI
MSB in
LSB in
LDAC
tLS
FIGURE 1-1:
tLD
SPI Input Timing Data.
 2010 Microchip Technology Inc.
DS22248A-page 7
MCP4901/4911/4921
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-DFN (2 x 3)
JA
—
68
—
°C/W
Thermal Resistance, 8L-PDIP
JA
—
90
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
150
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
211
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1:
The MCP4901/4911/4921 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of
150°C.
DS22248A-page 8
 2010 Microchip Technology Inc.
MCP4901/4911/4921
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
0.0766
0.3
Absolute DNL (LSB)
DNL (LSB)
0.2
0.1
0
-0.1
-0.2
0.0764
0.0762
0.076
0.0758
0.0756
0.0754
0.0752
0.075
-0.3
0
1024
2048
3072
-40
4096
FIGURE 2-1:
DNL vs. Code (MCP4921).
20
40
60
80
100 120
0.35
Absolute DNL (LSB)
0.1
DNL (LSB)
0
FIGURE 2-4:
Absolute DNL vs.
Temperature (MCP4921).
0.2
0
-0.1
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.2
0
1024
2048
3072
Code (Decimal)
1
4096
125C
85C
INL (LSB)
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
2048
Code (Decimal)
3072
1
2
4096
3
4
5.5
FIGURE 2-3:
DNL vs. Code and VREF,
Gain=1 (MCP4921).
 2010 Microchip Technology Inc.
4
5
FIGURE 2-5:
Absolute DNL vs. Voltage
Reference (MCP4921).
0.3
1024
3
Voltage Reference (V)
0.4
0
2
25C
FIGURE 2-2:
DNL vs. Code and
Temperature (MCP4921).
DNL (LSB)
-20
Ambient Temperature (ºC)
Code (Decimal)
5
4
3
2
1
0
-1
-2
-3
-4
-5
Ambient Temperature
125C
0
1024
85
2048
3072
Code (Decimal)
25
4096
FIGURE 2-6:
INL vs. Code and
Temperature (MCP4921).
DS22248A-page 9
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2
2
0
INL (LSB)
Absolute INL (LSB)
2.5
1.5
1
-2
-4
0.5
0
-6
-40
-20
0
20
40
60
80
100
120
0
1024
Ambient Temperature (ºC)
3072
4096
Code (Decimal)
FIGURE 2-7:
Absolute INL vs.
Temperature (MCP4921).
FIGURE 2-10:
Note:
3
INL vs. Code (MCP4921).
Single device graph (Figure 2-10) for
illustration of 64 code effect.
0.2
Temp = - 40oC to +125oC
2.5
0.1
2
DNL (LSB)
Absolute INL (LSB)
2048
1.5
1
0
-0.1
0.5
0
1
2
3
4
-0.2
5
0
Voltage Reference (V)
FIGURE 2-8:
(MCP4921).
Absolute INL vs. VREF
3
1
2
3
384
512 640
Code
768
896 1024
1.5
4
5.5
0.5
1
0
INL (LSB)
INL (LSB)
256
FIGURE 2-11:
DNL vs. Code and
Temperature (MCP4911).
VREF
2
128
-1
-2
o
85 C
-0.5
-1.5
o
-3
1024
FIGURE 2-9:
(MCP4921).
DS22248A-page 10
2048
3072
Code (Decimal)
4096
INL vs. Code and VREF
- 40 C
o
125 C
-4
0
25 C
o
-2.5
-3.5
0
128
256
384
512 640
Code
768
896 1024
FIGURE 2-12:
INL vs. Code and
Temperature (MCP4911).
 2010 Microchip Technology Inc.
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.06
18
Temp = -40oC to +125oC
16
14
Occurrence
0.02
0
-0.02
12
10
8
6
4
2
-0.04
0
32
64
96
128 160 192 224 256
Code
167
165
163
161
159
157
155
153
151
IDD (μA)
FIGURE 2-16:
2.7V).
FIGURE 2-13:
DNL vs. Code and
Temperature (MCP4901).
149
147
143
0
-0.06
145
DNL (LSB)
0.04
IDD Histogram (VDD =
9
0.5
8
o
o
-40 C to +85 C
7
Occurrence
INL (LSB)
0.25
0
6
5
4
3
2
-0.25
o
1
125 C
0
151 156 161 166 171 176 181 186 191 196 201
-0.5
0
32
64
96
128 160
Code
192
224
IDD (μA)
256
FIGURE 2-17:
5.0V).
FIGURE 2-14:
INL vs. Code and
Temperature (MCP4901).
210
IDD Histogram (VDD =
5.5V
5.0V
IDD (µA)
190
4.0V
3.0V
2.7V
170
VDD
150
130
110
-40
-20
FIGURE 2-15:
VDD.
0
20 40 60 80 100 120
Ambient Temperature (°C)
IDD vs. Temperature and
 2010 Microchip Technology Inc.
DS22248A-page 11
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
6
VDD
4
ISHDN_SW (μA)
5
5.0V
4
4.0V
3
3.0V
2.7V
2
VDD
1
VIN Hi Threshold (V)
5.5V
5.0V
3
2.5
4.0V
2
3.0V
2.7V
1.5
1
0
-40
-20
-40
0
20
40
60
80 100 120
Ambient Temperature (ºC)
-20
0
20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-21:
VIN High Threshold vs.
Temperature and VDD.
FIGURE 2-18:
Shutdown Current vs.
Temperature and VDD.
0.12
0.08
VDD
0.06
0.04
5.5V
0.02
0
5.0V
4.0V
3.0V
2.7V
-0.02
-40
-20
0
20
40
60
80
Offset Error vs.Temperature
-0.08
VDD
1.5
5.5V
1.4
5.0V
1.3
1.2
4.0V
1.1
1
3.0V
2.7V
0.9
0.8
-40
100 120
Ambient Temperature (ºC)
FIGURE 2-19:
and VDD.
VIN Low Threshold (V)
1.6
0.1
Offset Error (%)
5.5V
3.5
-20
0
20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-22:
VIN Low Threshold vs.
Temperature and VDD.
VDD
Gain Error (%)
5.5V
-0.1
5.0V
-0.12
4.0V
3.0V
2.7V
-0.14
-0.16
-40
-20
0
20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-20:
and VDD.
DS22248A-page 12
Gain Error vs. Temperature
 2010 Microchip Technology Inc.
MCP4901/4911/4921
VDD
5.5V
5.0V
4.0V
3.0V
2.7V
0.0045
VOUT_LOW Limit (Y-AVSS)(V)
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.004
5.5V
0.0035
0.003
5.0V
0.0025
4.0V
3.0V
2.7V
0.002
-40 -20
0
20 40 60 80 100 120
Ambient Temperature (ºC)
0
20
40
60
80 100 120
Ambient Temperature (ºC)
FIGURE 2-26:
VOUT Low Limit vs.
Temperature and VDD.
FIGURE 2-23:
Input Hysteresis vs.
Temperature and VDD.
18
175
VREF_UNBUFFERED Impedance
(kOhm)
5.5V 2.7V
VDD
170
165
160
VDD
17
5.5V
5.0V
4.0V
3.0V
2.7V
16
15
14
13
12
11
10
155
-40 -20
-40
0
20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-24:
VREF Input Impedance vs.
Temperature and VDD.
0.045
5.0
0.035
VREF=4.0
4.0V
0.03
0.025
3.0V
2.7V
0.02
VDD
0.015
0.01
0
20 40 60 80 100 120
Ambient Temperature (ºC)
6.0
5.5V
5.0V
0.04
-20
FIGURE 2-27:
IOUT High Short vs.
Temperature and VDD.
VOUT (V)
VOUT_HI Limit (VDD-Y)(V)
VDD
0.0015
-40 -20
IOUT_HI_SHORTED (mA)
VIN_SPI Hysteresis (V)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
4.0
Output Shorted to VDD
3.0
2.0
1.0
Output Shorted to VSS
0.005
0.0
0
-40 -20
0
20 40 60 80 100 120
Ambient Temperature (ºC)
FIGURE 2-25:
VOUT High Limit vs.
Temperature and VDD.
 2010 Microchip Technology Inc.
0
2
FIGURE 2-28:
4
6
8
10
IOUT (mA)
12
14
16
IOUT vs. VOUT. Gain = 1.
DS22248A-page 13
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
VOUT
VOUT
SCK
LDAC
LDAC
Time (1 µs/div)
FIGURE 2-29:
VOUT Rise Time
Time (1 µs/div)
FIGURE 2-32:
VOUT Rise Time
VOUT
VOUT
SCK
SCK
LDAC
LDAC
Time (1 µs/div)
VOUT Fall Time.
FIGURE 2-33:
Shutdown.
VOUT
SCK
LDAC
Time (1 µs/div)
FIGURE 2-31:
DS22248A-page 14
VOUT Rise Time Exit
Ripple Rejection (dB)
FIGURE 2-30:
Time (1 µs/div)
VOUT Rise Time
Frequency (Hz)
FIGURE 2-34:
PSRR vs. Frequency.
 2010 Microchip Technology Inc.
MCP4901/4911/4921
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.50V, Gain = 2, RL = 5 k, CL = 100 pF.
0
Attenuation (dB)
-2
-4
-6
-8
-10
-12
100
FIGURE 2-35:
Frequency (kHz)
160
416
672
928
1184
1440
1696
1952
2208
2464
2720
2976
3232
3488
3744
1,000
Multiplier Mode Bandwidth.
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
-45
qVREF – qVOUT
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
D=
0
-90
-135
-180
100
FIGURE 2-37:
Frequency (kHz)
160
416
672
928
1184
1440
1696
1952
2208
2464
2720
2976
3232
3488
3744
1,000
Phase Shift.
Bandwidth (kHz)
Figure 2-35 calculation:
Attenuation (dB) = 20 log (VOUT/VREF) – 20 log (G(D/4096))
600
580
560
540
520
500
480
460
440
420
400
G=1
G=2
44
37
88
34
32
32
76
29
20
27
64
24
08
22
52
19
96
16
40
14
84
11
8
92
2
67
6
41
0
16
Worst Case Codes (decimal)
FIGURE 2-36:
Codes.
-3 db Bandwidth vs. Worst
 2010 Microchip Technology Inc.
DS22248A-page 15
MCP4901/4911/4921
NOTES:
DS22248A-page 16
 2010 Microchip Technology Inc.
MCP4901/4911/4921
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
PDIP, MSOP, SOIC
DFN
Symbol
1
1
VDD
2
2
CS
Chip Select Input
3
3
SCK
Serial Clock Input
4
4
SDI
Serial Data Input
5
5
LDAC
DAC Output Synchronization Input. This pin is used to transfer
the input register (DAC settings) to the output register (VOUT)
6
6
VREF
Voltage Reference Input
7
7
VSS
Ground reference point for all circuitry on the device
8
8
VOUT
—
9
EP
3.1
Description
Supply Voltage Input (2.7V to 5.5V)
DAC Analog Output
Exposed Thermal Pad. This pad must be connected to VSS in
application
Supply Voltage Pins (VDD, VSS)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for good DAC performance. It
is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional
10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise
present in application boards.
VSS is the analog ground pin and the current return path
of the device. The user must connect the VSS pin to a
ground plane through a low-impedance connection. If
an analog ground path is available in the application
Printed Circuit Board (PCB), it is highly recommended
that the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.2
Chip Select (CS)
CS is the chip select input, which requires an active-low
signal to enable serial clock and data functions.
3.3
Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input.
3.4
Serial Data Input (SDI)
3.5
Latch DAC Input (LDAC)
The LDAC (latch DAC synchronization input) pin is
used to transfer the input latch register to the DAC register (output latches, VOUT). When this pin is low, VOUT
is updated with input register content. This pin can be
tied to low (VSS) if the VOUT update is desired at the
rising edge of the CS pin. This pin can be driven by an
external control device such as an MCU I/O pin.
3.6
Analog Output (VOUT)
VOUT is the DAC analog output pin. The DAC output
has an output amplifier. The full-scale range of the DAC
output is from VSS to G*VREF, where G is the gain
selection option (1x or 2x). The DAC analog output
cannot go higher than the supply voltage (VDD).
3.7
Voltage Reference Input (VREF)
VREF is the voltage reference input for the device. The
reference on this pin is utilized to set the reference
voltage on the string DAC. The input voltage can range
from VSS to VDD. This pin can be tied to VDD.
3.8
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin. They must
be connected to the same potential on the PCB.
SDI is the SPI compatible serial data input.
 2010 Microchip Technology Inc.
DS22248A-page 17
MCP4901/4911/4921
NOTES:
DS22248A-page 18
 2010 Microchip Technology Inc.
MCP4901/4911/4921
4.0
GENERAL OVERVIEW
The MCP4901, MCP4911 and MCP4921 are single
channel voltage output 8-bit, 10-bit and 12-bit DAC
devices, respectively. These devices include a VREF
input buffer, a rail-to-rail output amplifier, shutdown and
reset management circuitry. The devices use an SPI
serial communication interface and operate with a
single-supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1:
VOUT = ------------------------------ G
n
2
Where:
VREF
Dn
G
n
ANALOG OUTPUT
VOLTAGE (VOUT)
 VREF  Dn 
=
=
=
=
=
=
=
=
=
EXternal voltage reference
DAC input code
Gain Selection
2 for <GA> bit = 0
1 for <GA> bit = 1
DAC Resolution
8 for MCP4901
10 for MCP4911
12 for MCP4912
TABLE 4-1:
LSb OF EACH DEVICE
Gain
Selection
Device
LSb Size
1x
VREF/256
2x
(2*VREF)/256
MCP4911
1x
VREF/1024
(n = 10)
2x
(2*VREF)/1024
MCP4921
1x
VREF/4096
(n = 12)
2x
(2*VREF)/4096
where VREF is the external voltage reference.
MCP4901
(n = 8)
4.1
4.1.1
DC Accuracy
INL ACCURACY
Integral Non-Linearity (INL) error is the maximum
deviation between an actual code transition point and
its corresponding ideal transition point, after offset and
gain errors have been removed. The two endpoints
(from 0x000 and 0xFFF) method is used for the calculation. Figure 4-1 shows the details.
A positive INL error represents transition(s) later than
ideal. A negative INL error represents transition(s) earlier than ideal.
INL < 0
111
The ideal output range of each device is:
110
• MCP4901 (n = 8)
101
(a) 0V to 255/256*VREF when gain setting = 1x.
(b) 0V to 255/256*2*VREF when gain setting = 2x.
• MCP4911 (n = 10)
Actual
Transfer
Function
Digital
Input
Code
100
011
Ideal Transfer
Function
(a) 0V to 1023/1024*VREF when gain setting = 1x.
010
(b) 0V to 1023/1024*2*VREF when gain setting = 2x.
• MCP4921 (n = 12)
001
(a) 0V to 4095/4096*VREF when gain setting = 1x.
000
(b) 0V to 4095/4096*2*VREF when gain setting = 2x.
Note:
See the output swing voltage specification
in Section 1.0 “Electrical Characteristics”.
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
calculation of each device.
 2010 Microchip Technology Inc.
INL < 0
DAC Output
FIGURE 4-1:
4.1.2
Example for INL Error.
DNL ACCURACY
A Differential Non-Linearity (DNL) error is the measure
of variations in code widths from the ideal code width.
A DNL error of zero indicates that every code is exactly
1 LSB wide.
DS22248A-page 19
MCP4901/4911/4921
4.2.2
111
110
Actual
Transfer
Function
101
100
Ideal Transfer
Function
011
010
Wide Code, > 1 LSb
4.2.3
000
Narrow Code, < 1 LSb
DAC Output
FIGURE 4-2:
Example for DNL Accuracy.
OFFSET ERROR
An offset error is the deviation from zero voltage output
when the digital input code is zero.
4.1.4
GAIN ERROR
A gain error is the deviation from the ideal output,
VREF– 1 LSB, excluding the effects of offset error.
4.2
4.2.1
Circuit Descriptions
OUTPUT AMPLIFIER
The DAC’s output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load driving capability, the
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong output allows VOUT to
be used as a programmable voltage reference in a
system.
Selecting a gain of 2 reduces the bandwidth of the
amplifier in Multiplying mode. Refer to Section 1.0
“Electrical Characteristics” for the Multiplying mode
bandwidth for given load conditions.
POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (VDD) during device operation.
The circuit also ensures that the device powers up with
high output impedance (<SHDN> = 0, typically
500 k. The devices will continue to have a highimpedance output until a valid write command is
received, and the LDAC pin meets the input low threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the device will be held
in its Reset state. It will remain in that state until
VDD > VPOR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
5V
Supply Voltages
001
4.1.3
The input buffer amplifier for the MCP4901/4911/4921
devices provides low offset voltage and low noise. A
Configuration bit for each DAC allows the VREF input to
bypass the VREF input buffer amplifier, achieving
Buffered or Unbuffered mode. Buffered mode provides
a very high input impedance, with only minor limitations
on the input range and frequency response. Unbuffered mode provides a wide input range (0V to VDD),
with a typical input impedance of 165 k with 7 pF.
Unbuffered mode (<BUF> = 0) is the default
configuration.
VPOR
VDD - VPOR
Transient Duration
Time
10
Transient Duration (µs)
Digital
Input
Code
VOLTAGE REFERENCE AMPLIFIER
Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default value is a gain of 2x
(<GA> = 0).
DS22248A-page 20
FIGURE 4-3:
=
6
4
Transients
above
the
2
Transients
0
4.2.1.1
TA
8
1
below
the
2
3
4
VDD – VPOR (V)
5
Typical Transient Response.
 2010 Microchip Technology Inc.
MCP4901/4911/4921
4.2.4
SHUTDOWN MODE
The user can shut down the device by using a software
command. During Shutdown mode, most of the internal
circuits, including the output amplifier, are turned off for
power savings. The serial interface remains active,
thus allowing a write command to bring the device out
of Shutdown mode. There will be no analog output at
the VOUT pin, and the VOUT pin is internally switched to
a known resistive load (500 k typical. Figure 4-4
shows the analog output stage during Shutdown mode.
The device will remain in Shutdown mode until it
receives a write command with <SHDN> bit = 1 and the
bit is latched into the device. When the device is
changed from Shutdown to Active mode, the output
settling time takes less than 10 µs, but more than the
standard active mode settling time (4.5 µs).
 2010 Microchip Technology Inc.
VOUT
OP
Amp
Power-Down
Control Circuit
Resistive
Load
500 k
Resistive String DAC
FIGURE 4-4:
Mode.
Output Stage for Shutdown
DS22248A-page 21
MCP4901/4911/4921
NOTES:
DS22248A-page 22
 2010 Microchip Technology Inc.
MCP4901/4911/4921
5.0
SERIAL INTERFACE
5.1
Overview
The MCP4901/4911/4921 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4901/4911/4921. The
CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 through Register 5-3 detail the input register that is used to configure and load the DAC register
for each device. Figure 5-1 through Figure 5-3 show
the write command for each device.
Refer to Figure 1-1 and the SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
 2010 Microchip Technology Inc.
5.2
Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the DAC’s input register.
The MCP4901/4911/4921 utilizes a double-buffered
latch structure to allow the analog output to be
synchronized with the LDAC pin, if desired.
By bringing the LDAC pin down to a low state, the content stored in the DAC’s input register is transferred into
the DAC’s output register (VOUT), and VOUT is updated.
All writes to the MCP4901/4911/4921 devices are
16-bit words. Any clocks past the 16th clock will be
ignored. The Most Significant 4 bits are Configuration
bits. The remaining 12 bits are data bits. No data can
be transferred into the device with CS high. This
transfer will only occur if 16 clocks have been
transferred into the device. If the rising edge of CS
occurs prior to that, shifting of data into the input
register will be aborted.
DS22248A-page 23
MCP4901/4911/4921
REGISTER 5-1:
WRITE COMMAND REGISTER FOR MCP4921 (12-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
BUF
GA
SHDN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
bit 15
bit 0
REGISTER 5-2:
WRITE COMMAND REGISTER FOR MCP4911 (10-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
BUF
GA
SHDN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
W-x
x
bit 15
bit 0
REGISTER 5-3:
WRITE COMMAND REGISTER FOR MCP4901 (8-BIT DAC)
W-x
W-x
W-x
W-0
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
0
BUF
GA
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
W-x
bit 15
x
bit 0
Where:
bit 15
0 = Write to DAC register
1 = Ignore this command
bit 14
BUF: VREF Input Buffer Control bit
1 = Buffered
0 = Unbuffered
bit 13
GA: Output Gain Selection bit
1 = 1x (VOUT = VREF * D/4096)
0 = 2x (VOUT = 2 * VREF * D/4096)
bit 12
SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is available. 
0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500 ktypical)
bit 11-0
D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS22248A-page 24
x = bit is unknown
 2010 Microchip Technology Inc.
MCP4901/4911/4921
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
SDI
0
12 data bits
BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1:
Write Command for MCP4921 (12-bit DAC).
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
SDI
0
12 data bits
BUF GA SHDN D9
D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
LDAC
VOUT
FIGURE 5-2:
Write Command for MCP4911 (10-bit DAC). Note: X are don’t care bits.
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
(Mode 1,1)
13 14 15
SCK
(Mode 0,0)
config bits
SDI
0
BUF GA SHDN D7
12 data bits
D6 D5 D4 D3 D2 D1 D0
X
X
X
X
LDAC
VOUT
FIGURE 5-3:
Write Command for MCP4901(8-bit DAC). Note: X are don’t care bits.
 2010 Microchip Technology Inc.
DS22248A-page 25
MCP4901/4911/4921
NOTES:
DS22248A-page 26
 2010 Microchip Technology Inc.
MCP4901/4911/4921
TYPICAL APPLICATIONS
VDD
C1
VDD
VREF
Applications generally suited for the devices are:
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Digitally-Controlled Multiplier/Divider
Portable Instrumentation (Battery Powered)
Motor Control Feedback Loop
6.1
Digital Interface
The MCP4901/4911/4921 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup
and output values from the digital source. The serial
protocol can be interfaced to SPI or Microwire peripherals that are common on many microcontrollers,
including Microchip’s PIC® MCUs and dsPIC® DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC pin synchronizes the analog output
(VOUT) with the pin event. By bringing the LDAC pin
down “low”, the DAC input code and settings in the
input register are latched into the output register, and
the analog output is updated. Figure 6-1 shows an
example of the pin connections. Note that the LDAC pin
can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16-clock transmission has been received and CS pin
has been raised.
6.2
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply's traces from various
events such as digital switching or as a result of
changes on the DAC's output. The bypass capacitor
helps to minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy. In
this example, two bypass capacitors are used in
parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum).
These capacitors should be placed as close to the
device power pin (VDD) as possible (within 4 mm).
VOUT
C1
VDD
C2
CS1
SDI
VREF
VOUT
SDI
C2
C1
AVSS
SDO
SCK
LDAC
PIC® Microcontroller
C1 = 10 µF
C2 = 0.1 µF
MCP49X1
The MCP4901/4911/4921 family devices are general
purpose DACs intended to be used in applications
where precision with low-power and moderate
bandwidth is required.
MCP49X1
6.0
CS0
VSS
AVSS
FIGURE 6-1:
Diagram.
6.3
Typical Connection
Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the input and output signal
integrity, potentially reducing the device’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, and
isolated outputs with proper decoupling, is critical for
best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
 2010 Microchip Technology Inc.
DS22248A-page 27
MCP4901/4911/4921
6.4
6.4.1.1
Single-Supply Operation
The MCP4901/4911/4921 devices are rail-to-rail voltage output DAC devices designed to operate with a
VDD range of 2.7V to 5.5V. Its output amplifier is robust
enough to drive small signal loads directly. Therefore, it
does not require an external output buffer for most
applications.
6.4.1
DC SET POINT OR CALIBRATION
A common application for DAC devices is
digitally-controlled set points and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP4921 and MCP4922 provide
4096 output steps. If the external voltage reference
(VREF) is 4.096V, the LSb size is 1 mV. If a smaller
output step size is desired, a lower external voltage
reference is needed.
Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve a 0.8V range is to either
reduce VREF to 0.82V or use a voltage divider on the
DAC’s output.
Using a VREF is an option if the VREF is available with
the desired output voltage range. However,
occasionally, when using a low-voltage VREF, the noise
floor causes an SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when the desired output voltage is not available. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
(a) Single Output DAC:
MCP4901
MCP4911
MCP4921
VDD
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
VCC+
RSENSE
VDD
VREF
VO
DAC
VOUT
Comparator
R1
VTRIP
R2
0.1 uF
VCC–
SPI
3-wire
Dn
V OUT = V REF  G  -----N
2
 R2 
Vtrip = V OUT  --------------------
 R1 + R2
EXAMPLE 6-1:
DS22248A-page 28
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION.
 2010 Microchip Technology Inc.
MCP4901/4911/4921
6.4.1.2
Building a “Window” DAC
If the threshold is not near VREF or VSS, then creating
a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a
pull-up and pull-down resistor. Example 6-2 and
Example 6-4 illustrate this concept.
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
(a) Single Output DAC:
MCP4901
MCP4911
MCP4921
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
VREF
VCC+
VCC+
Rsense
VDD
DAC
VOUT
R3
R1
Comparator
Vtrip
0.1 µF
R2
VCC-
SPI
3
VCC-
Dn
V OUT = VREF  G  -----N
2
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
Thevenin
Equivalent
R 2 R3
R 23 = -----------------R2 + R 3
R1
VOUT
 V CC+ R2  +  VCC- R3 
V 23 = ---------------------------------------------------R 2 + R3
V OUT R23 + V 23 R1
V trip = ------------------------------------------R 2 + R23
EXAMPLE 6-2:
VO
R23
V23
SINGLE-SUPPLY “WINDOW” DAC.
 2010 Microchip Technology Inc.
DS22248A-page 29
MCP4901/4911/4921
6.5
Bipolar Operation
Bipolar operation is achievable using the MCP4901/
4911/4921 family devices by using an external
operational amplifier (op amp). This configuration is
desirable due to the wide variety and availability of op
amps. This allows a general purpose DAC, with its cost
and availability advantages, to meet almost any
desired output voltage range, power and noise
performance.
Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VREF instead of VSS
if a higher offset is desired. Note that a pull-up to VREF
could be used, instead of R4, if a higher offset is
desired.
VREF
(a) Single Output DAC:
MCP4901
MCP4911
MCP4921
VREF
VDD
VOUT
(b) Dual Output DAC:
R3
DAC
MCP4902
MCP4912
MCP4922
VCC+
R1
VO
VIN+
VCC–
R4
0.1 µF
SPI
3
Dn
VOUT = V REF  G  -----N
2
VIN+
V OUT R4
= ------------------R3 + R 4
R2
R
VO = V IN+  1 + -----2- – VDD  ------
R1
R1
EXAMPLE 6-3:
6.5.1
G = Gain selection (1x or 2x)
Dn = Digital value of DAC (0 – 255) for MCP4901/MCP4902
= Digital value of DAC (0 – 1023) for MCP4911/MCP4912
= Digital value of DAC (0 – 4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE.
DESIGN EXAMPLE: DESIGN A BIPOLAR
DAC USING EXAMPLE 6-3 WITH 12-BIT
MCP4912 OR MCP4922
An output step magnitude of 1 mV with an output range
of ±2.05V is desired for a particular application.
The following steps show the details:
1. Calculate the range: +2.05V – (-2.05V) = 4.1V.
2. Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
3. The amplifier gain (R2/R1), multiplied by VREF,
must be equal to the desired minimum output to
achieve bipolar operation. Since any gain can
be realized by choosing resistor values
(R1 + R2), the VREF source needs to be determined first. If a VREF of 4.1V is used, solve for
the gain by setting the DAC to 0, knowing that
the output needs to be -2.05V. The equation can
be simplified to:
– R2
– 2.05
– 2.05
--------- = ------------- = ------------R1
V REF
4.1
4.
Next, solve for R3 and R4 by setting the DAC to
4096, knowing that the output needs to be
+2.05V.
R4
2.05V + 0.5V REF
2
----------------------- = ----------------------------------------- = --1.5VREF
 R3 + R 4 
3
If R4 = 20 k, then R3 = 10 k
R2
1
------ = --R1
2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5
DS22248A-page 30
 2010 Microchip Technology Inc.
MCP4901/4911/4921
6.6
Selectable Gain and Offset Bipolar
Voltage Output Using DAC
Devices
This circuit is typically used in Multiplier mode and is
ideal for linearizing a sensor whose slope and offset
varies. Refer to Section 6.9 “Using Multiplier Mode”
for more information on Multiplier mode.
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustrates how
to use the DAC devices to achieve this in a bipolar or
single-supply application.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
R2
VREFA VDD
VOUTA
VCC+
R1
DACA
DACA (Gain Adjust)
VDD
VREFB
VOUTB
VCC+
VO
R5
R3
DACB
DACB (Offset Adjust)
SPI
R4
3
0.1uF
VCC–
VCC–
DA
VOUTA =  V REFA G A  -----N
2
DB
V OUTB =  VREFB G B  -----N
2
GX = Gain selection (1x or 2x)
N = DAC Bit Resolution
DA, DB = Digital value of DAC (0-255) for MCP4901/MCP4902
VOUTB R 4 + VCC- R3
V IN+ = ----------------------------------------------R3 + R4
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4912/MCP4922
R2
R
V O = V IN+  1 + -----2- – V OUTA  ------

 R 1
R 
1
Offset Adjust Gain Adjust
Bipolar “Window” DAC using R4 and R5
Thevenin
Equivalent
V CC+ R4 + V CC- R 5
V45 = ------------------------------------------R4 + R5
VOUTB R 45 + V45 R 3
V IN+ = ---------------------------------------------R3 + R 45
R4 R5
R 45 = -----------------R4 + R5
R2
R
V O = VIN+  1 + -----2- – V OUTA  ------
R1
R1
Offset Adjust Gain Adjust
EXAMPLE 6-4:
BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET.
 2010 Microchip Technology Inc.
DS22248A-page 31
MCP4901/4911/4921
6.7
Designing a Double-Precision
DAC
1.
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution by
using 12-bit DACs. This design is simply a voltage
divider with a buffered output.
As an example, if a similar application to the one
developed in Section 6.5.1 “Design Example:
Design a bipolar dac using example 6-3 with 12-bit
MCP4912 or MCP4922” required a resolution of 1 µV
instead of 1 mV and a range of 0V to 4.1V, then 12-bit
resolution would not be adequate.
2.
3.
4.
VDD
VREF
DACA
VDD
DACB
Calculate the resolution needed:
4.1V/1 µV = 4.1x 106. Since 222 = 4.2 x 106,
22-bit resolution is desired. Since DNL = ±0.75
LSB, this design can be done with the MCP4921
or MCP4922.
Since the DACB‘s VOUTB has a resolution of
1 mV, its output only needs to be “pulled” 1/1000
to meet the 1 µV target. Dividing VOUTA by 1000
would allow the application to compensate for
DACB’s DNL error.
If R2 is 100, then R1 needs to be 100 k.
The resulting transfer function is not perfectly
linear, as shown in the equation of Example 6-5.
VCC+
VOUTA
VO
DACA (Fine Adjust)
R1
R1 >> R2
VOUTB
R2
0.1 µF
VCC–
DACB (Course Adjust)
SPI
3
DA
V OUTA = VREFA GA ------12
2
G = Gain selection (1x or 2x)
D = Digital value of DAC (0-4096)
VOUTA R 2 + VOUTB R 1
V O = ----------------------------------------------------R 1 + R2
DB
V OUTB = VREFB GB ------12
2
EXAMPLE 6-5:
DS22248A-page 32
SIMPLE, DOUBLE PRECISION DAC WITH MCP4921 OR MCP4922.
 2010 Microchip Technology Inc.
MCP4901/4911/4921
6.8
Building Programmable Current
Source
When working with very small sensor voltages, plan on
eliminating the amplifier’s offset error by storing the
DAC's setting under known sensor conditions.
Example 6-6 shows an example for building a
programmable current source using a voltage follower.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller Rsense
is, the less power is dissipated across it. However, this
also reduces the resolution that the current can be
controlled with. The voltage divider, or “window”, DAC
configuration would allow the range to be reduced, thus
increasing the resolution around the range of interest.
VDD or VREF
(a) Single Output DAC:
VREF
VDD
IL
VOUT
DAC
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
Load
VCC+
MCP4901
MCP4911
MCP4921
Ib
SPI
3-wire
VCC–
RSENSE
I
Ib = ----L

VOUT

IL = ---------------  -----------R sense  + 1
where Common-Emitter Current Gain
Dn
VOUT = V REF  G  -----N
2
EXAMPLE 6-6:
G = Gain select (1x or 2x)
Dn = Digital value of DAC (0-255) for MCP4901/MCP4902
= Digital value of DAC (0-1023) for MCP4911/MCP4912
= Digital value of DAC (0-4095) for MCP4921/MCP4922
N = DAC Bit Resolution
DIGITALLY-CONTROLLED CURRENT SOURCE.
 2010 Microchip Technology Inc.
DS22248A-page 33
MCP4901/4911/4921
6.9
Using Multiplier Mode
If the gain selection bit is configured for 1x mode
(<GA> = 1), the resulting input signal will be attenuated
by D/2n. With the 12-bit DAC (MCP4921 or MCP4922),
if the gain is configured for 2x mode (<GA> = 0), codes
less than 2048 attenuate the signal, while codes
greater than 2048 gain the signal.
The MCP4901/4911/4921 and MCP4902/MCP4912/
MCP4922 family devices use external reference, and
these devices are ideally suited for use as a multiplier/
divider in a signal chain. Common applications are: (a)
precision programmable gain/attenuator amplifiers and
(b) motor control feedback loops. The wide input range
(0V – VDD) is in Unbuffered mode, and near rail-to-rail
range in Buffered mode. Its bandwidth (> 400 kHz),
selectable 1x/2x gain and low power consumption give
maximum flexibility to meet the application’s needs.
A DAC provides significantly more gain/attenuation
resolution when compared to typical programmable
gain amplifiers. Adding an op amp to buffer the output,
as illustrated in Examples 6-2 through 6-6, extends the
output range and power to meet the precise needs of
the application.
To configure the device for multiplier applications,
connect the input signal to VREF and serially configure
the DAC’s input buffer, gain and output value. The
DAC’s output can utilize any of the examples from 6-1
to 6-6, depending on the application requirements.
Example 6-7 is an illustration of how the DAC can
operate in a motor control feedback loop.
VRPM_SET
VRPM
(a) Single Output DAC:
MCP4901
MCP4911
MCP4921
(b) Dual Output DAC:
MCP4902
MCP4912
MCP4922
VDD
DAC
VREF
ZFB
VOUT
VCC+
+
–
VCC–
SPI
3
Rsense
Dn
V OUT = V REF  G  -----N
2
EXAMPLE 6-7:
DS22248A-page 34
MULTIPLIER MODE USING VREF INPUT.
 2010 Microchip Technology Inc.
MCP4901/4911/4921
7.0
DEVELOPMENT SUPPORT
7.1
Evaluation & Demonstration
Boards
The Mixed Signal PICtail™ Board supports the
MCP4901/4911/4921 family of devices. Please refer to
www.microchip.com for further information on this
product’s capabilities and availability.
 2010 Microchip Technology Inc.
DS22248A-page 35
MCP4901/4911/4921
NOTES:
DS22248A-page 36
 2010 Microchip Technology Inc.
MCP4901/4911/4921
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
8-Lead DFN (2x3)
Example:
AHS
010
25
XXX
YWW
NN
Example:
8-Lead MSOP
XXXXXX
4901E
YWWNNN
010256
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
MCP4901
E/P e3 256
1010
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
Example:
MCP4901E
SN e3 1010
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
 2010 Microchip Technology Inc.
DS22248A-page 37
MCP4901/4911/4921
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 2010 Microchip Technology Inc.
MCP4901/4911/4921
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
DS22248A-page 41
MCP4901/4911/4921
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 2010 Microchip Technology Inc.
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 2010 Microchip Technology Inc.
DS22248A-page 43
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DS22248A-page 44
 2010 Microchip Technology Inc.
MCP4901/4911/4921
APPENDIX A:
REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
 2010 Microchip Technology Inc.
DS22248A-page 45
MCP4901/4911/4921
NOTES:
DS22248A-page 46
 2010 Microchip Technology Inc.
MCP4901/4911/4921
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device
MCP4901: 8-Bit Voltage Output DAC
MCP4901T: 8-Bit Voltage Output DAC
(Tape and Reel)
MCP4911: 10-Bit Voltage Output DAC
MCP4911T: 10-Bit Voltage Output DAC
(Tape and Reel)
MCP4921: 12-Bit Voltage Output DAC
MCP4921T: 12-Bit Voltage Output DAC
(Tape and Reel)
c)
d)
e)
f)
Temperature Range
E
= -40C to +125C
Package
MC
=
MS
SN
=
=
P
=
(Extended)
8-Lead Plastic Dual Flat, No Lead Package 2x3x0.9 mm Body (DFN)
8-Lead Plastic Micro Small Outline (MSOP)
8-Lead Plastic Small Outline - Narrow, 150 mil
(SOIC)
8-Lead Plastic Dual In-Line (PDIP)
g)
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 2010 Microchip Technology Inc.
MCP4901-E/P:
Extended temperature,
PDIP package.
MCP4901-E/SN: Extended temperature,
SOIC package.
MCP4901T-E/SN: Extended temperature,
SOIC package
Tape and Reel.
MCP4901-E/MS: Extended temperature,
MSOP package.
MCP4901T-E/MS: Extended temperature,
MSOP package
Tape and Reel.
MCP4901-E/MC: Extended temperature,
DFN package.
MCP4901T-E/MC:Extended temperature,
DFN package
Tape and Reel.
Extended temperature,
PDIP package.
MCP4911-E/SN: Extended temperature,
SOIC package.
MCP4911T-E/SN: Extended temperature,
SOIC package
Tape and Reel.
MCP4911-E/MS: Extended temperature,
MSOP package.
MCP4911T-E/MS: Extended temperature,
MSOP package
Tape and Reel.
MCP4911-E/MC: Extended temperature,
DFN package.
MCP4911T-E/MC: Extended temperature,
DFN package
Tape and Reel.
MCP4911-E/P:
Extended temperature,
PDIP package.
MCP4921-E/SL:
Extended temperature,
SOIC package.
MCP4921T-E/SL: Extended temperature,
SOIC package
Tape and Reel.
MCP4921-E/MS: Extended temperature,
MSOP package.
MCP4921T-E/MS: Extended temperature,
MSOP package
Tape and Reel.
MCP4921-E/MC: Extended temperature,
DFN package.
MCP4921T-E/MC:Extended temperature,
DFN package
Tape and Reel.
MCP4921-E/P:
DS22248A-page 47
MCP4901/4911/4921
NOTES:
DS22248A-page 48
 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010 Microchip Technology Inc.
DS22248A-page 49
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
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Tel: 678-957-9614
Fax: 678-957-1455
Boston
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Tel: 774-760-0087
Fax: 774-760-0088
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
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Detroit
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Tel: 248-538-2250
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Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS22248A-page 50
 2010 Microchip Technology Inc.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
MCP4901-E/MC MCP4901-E/MS MCP4901-E/P MCP4901-E/SN MCP4901T-E/MC MCP4901T-E/MS MCP4901TE/SN MCP4911-E/MC MCP4911-E/MS MCP4911-E/P MCP4911-E/SN MCP4911T-E/MC MCP4911T-E/MS
MCP4911T-E/SN MCP4921-E/MC
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