Optimized SiT15xx Drive Settings for 32 kHz Crystal Inputs of Low

July 2016
Optimized SiT15xx Drive Settings for
32 kHz Crystal Inputs of Low Power MCUs
Table of Contents
1
2
3
Introduction ............................................................................................................................................ 2
MCU 32 kHz Oscillator Operating Modes .............................................................................................. 2
SiT15xx Output Drive Levels ................................................................................................................. 4
3.1
NanoDrive Reduced Swing Mode ................................................................................................. 4
3.2
Full-Swing LVCMOS Drive ............................................................................................................ 5
4 Energy Micro EFM32 ............................................................................................................................. 5
5 STMicroelectronics STM32 .................................................................................................................... 6
6 Renesas Electronics RL78G13 .............................................................................................................. 6
7 Texas Instruments MSP430F2x ............................................................................................................ 7
8 NXP LPC11xx ........................................................................................................................................ 7
9 Freescale Kinetis L4x/L5x ...................................................................................................................... 8
10
Microchip PIC18 ................................................................................................................................ 8
11
Appendix A: Programming the EnergyMicro EFM32 LFXO .............................................................. 9
11.1 EFM32 Clock Management Unit ................................................................................................... 9
11.2 Configuring the LFXO ................................................................................................................. 12
12
Appendix B: Programming the STMicroelectronics STM32 LSE Oscillator .................................... 13
12.1 Low-speed External Clock Oscillator .......................................................................................... 13
12.2 External Clock Source (LSE bypass) .......................................................................................... 14
12.3 Clock Security System on LSE ................................................................................................... 14
12.4 Clock-out Capability .................................................................................................................... 14
12.5 Configuring LSE .......................................................................................................................... 16
13
Appendix C: Programming the Renesas Electronics RL78G13 XT1 Oscillator .............................. 17
13.1 XT1 Oscillator .............................................................................................................................. 17
13.2 Configuration XT1 ....................................................................................................................... 17
14
Appendix D: Programming the Texas Instruments MSP430 low frequency oscillator.................... 19
14.1 The MSP430 LFXT Oscillator ..................................................................................................... 19
14.2 Clock-out Capability .................................................................................................................... 21
14.3 Low-power Modes ....................................................................................................................... 21
15
Appendix E: Programming the NXP LPC1100 RTC Oscillator ....................................................... 22
15.1 Configuring the RTC Oscillator ................................................................................................... 22
15.2 Clock Output Capability............................................................................................................... 22
16
Appendix F: Programming the Freescale Kinetis L4x and L5x System Oscillator .......................... 30
16.1 Programming Model .................................................................................................................... 30
16.2 Clock Output Capability............................................................................................................... 35
17
Appendix G: Programming the PIC18 MCU Secondary Oscillator ................................................. 36
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
1 Introduction
Embedded microcontroller (MCU) based systems have historically relied on a low frequency
32.768 kHz quartz resonator driven oscillator for time keeping and failure recovery functions.
TempFlat™ MEMS SiT153x oscillators and SiT155x temperature compensated oscillators
(TCXOs) are a new generation of smaller footprint 32.768 kHz devices that offer a cost
effective, more reliable, improved frequency stability alternative to quartz-based 32.768 kHz
oscillators.
This application note gives an overview of on-chip 32 kHz oscillator modes used in low power
MCUs and the different drive settings supported by the SiT15xx families. The SiT15xx devices
feature NanoDrive™, a factory programmable output voltage swing to optimize power and
connectivity to existing oscillator sustaining circuits. This document lists valid combinations of
SiT15xx output drive VOH/VOL settings and the associated part number for specific MCUs.
1.
2.
3.
4.
Energy Micro EFM32
Renesas Electronics RL78G13
STMicroelectronics STM32
Texas Instruments MSP430F2x
5. NXP LPC11xx
6. Freescale Kinetis L4x/L5x
7. Microchip PIC18
The programming details specific to each MCU are listed in individual Appendices at the end of
this application note.
2 MCU 32 kHz Oscillator Operating Modes
Most energy efficient MCUs implement on-chip 32.768 kHz oscillators as a variant of a Pierce
oscillator with either fixed or adjustable inverting gain stage as show in Figure 1.
Variable Gain
Inverting Amplifier
Level
Translator
Rs
To downstream
receiver
Rf
Crystal IN
(XIN)
Crystal OUT
(XOUT)
C1
C2
Figure 1: Typical 32.768 kHz oscillator block diagram shown with a crystal resonator.
This low frequency oscillator can be configured to operate in three distinct modes as shown in
Figure 2.
1. Mode-1: Resonator only mode: drives a 32.768 kHz quartz resonator
2. Mode-2: Accept a sine wave input ≥200 mVpp on XIN pin
3. Mode-3: Digital logic level clock input after bypassing or shutting off the on-chip
oscillator. For oscillator inputs compatible to 1.8V logic levels, a smaller swing
NanoDrive supported by the SiT15xx can be leveraged to save additional power.
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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MCU
MCU
(A)
32.768 kHz
Oscillator
(Enabled)
32.768 kHz
Oscillator
(Enabled)
XOUT
XOUT
XIN
250-800 mV
XIN
VDD
4
1
3
CLK OUT
2
C2
*
C1
GND
C2
*C1
SiT153x
(Mode-1) Oscillator ON and driven by SiT153x NanoDrive output. C1
and C2 are optional and can be removed for additional power savings
(Mode-1) Oscillator ON and driven by external quartz resonator
MCU
MCU
(B)
32.768 kHz
Oscillator
(Enabled)
32.768 kHz
Oscillator
(Enabled)
XOUT
XIN
XOUT
XIN
VDD
250 mV
4
SiT153x
1
3
CLK OUT
2
GND
250 mV
(Mode-2) Oscillator ON and driven by external sine wave signal
(Mode-2) Oscillator ON and driven by SiT153x NanoDrive output
MCU
MCU
(C)
32.768 kHz
Oscillator
(Disabled)
32.768 kHz
Oscillator
(Disabled)
1.2-3.3V
XOUT
XOUT
XIN
SiT153x
XIN
VDD
OR
4
1
3
2
GND
1.2-3.3V
(Mode-3) Oscillator OFF/Bypassed and driven
by external logic level square wave signal
800 mV
(Mode-3) Oscillator OFF/Bypassed and driven by SiT153x
CMOS drive or NanoDrive for 1.8V logic level inputs
* - C1 and C2 are optional and can be de-populated for additional power savings.
Figure 2: Operational modes of an MCU on-chip 32 kHz oscillator.
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SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
3 SiT15xx Output Drive Levels
The SiT15xx devices support two distinct output drive modes.
1. NanoDrive™ reduced swing, factory programmable
2. Rail-to-rail full-swing LVCMOS
3.1 NanoDrive Reduced Swing Mode
In NanoDrive mode, the SiT15xx output driver achieves various voltage swings and commonmode bias voltages similar to drive levels sustained by various implementations of a 32 kHz
quartz crystal driven Pierce oscillator.
DC coupled VOH/VOL drive levels shown below are supported for 32 kHz oscillator circuits
sensitive to DC bias and swing levels. The correct part number designator is shown inside each
VOH/VOL combinationError! Reference source not found.. For example SiT153xAI-H4-D2632.768 will provide typical drive levels: VOH = 1.2V and VOL = 0.6V. The applicable oscillator
operating modes for this setting is Mode-1 as illustrated in Figure 2.
Table 1: Matrix of Permitted NanoDrive Levels
NanoDrive
D26
D14
D74
AA3
VOH (V)
1.2
1.1
0.7
N/A
VOL (V)
0.6
0.4
0.4
N/A
Swing (mV)
600 ±50
700 ±50
300 ±50
300 ±50
Comments
1.8V logic Compatible
1.8V logic Compatible
XTAL Compatible
XTAL Compatible
Figure 3 shows a typical waveform output of a SiT153x oscillator when programmed in
NanoDrive mode: swing voltage, Vswing = 0.7 V, VOH = 1.1V, VOL = 0.4V into a 15 pF load.
The corresponding part number for a 2012 package is SiT1533AI-H4-D14-32.768.
VOH = 1.1V
Vsw= 0.7V
VOL = 0.4V
Figure 3: SiT153xAI-H4-D14-32.768 output waveform in to a 15 pF load.
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SiT-AN10037 Rev 1.5
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3.2 Full-Swing LVCMOS Drive
The SiT153x/SiT1552 families can be programmed to generate a full-swing, LVCMOS output.
Figure 4 shows the waveform of SiT153xAI-H4-DCC-32.768, 1.8V VDD into a 15 pF load.
Figure 4: LVCMOS waveform of SiT153xAI-H4-DCC-32.768 at 1.8V VDD in to 15 pf load.
4 Energy Micro EFM32
The EFM32 family of microcontrollers is based on the ARM Cortex-M0, M3 or M4 processor
core targeted for low power operation. The EFM32 incorporates a low frequency crystal driven
oscillator (LFXO) for clocking on-chip peripherals (including RTC) and potentially the CPU core.
The LFXO can operate from a 32.768 kHz quartz crystal connected across the LFXTAL_N and
LFXTAL_P pins or an external clock source on the LFXTAL_P pin.
By default the low frequency crystal oscillator (LFXO) is disabled. Table 2 lists the optimal
settings of SiT15xx devices for each of the three operating modes of the LFXO oscillator.
Table 2: SiT15xx Configuration for the Three EFM32 LFXO Oscillator Modes
LFXTAL_N, P
connections
SiT15xx Output
Drive Settings
Mode-1: LFXO
Enabled
Mode-2: LFXO
Enabled with Sine
Wave Input
Mode-3: LFXO Disabled
SiT15xx pin 3 
LFXTAL_N pin
LFXTAL_P pin = NC
SiT15xx pin 3 
LFXTAL_N pin
LFXTAL_P pin = NC
SiT15xx pin 3  LFXTAL_P pin
LFXTAL_N pin = NC
NanoDrive: AA3
LVCMOS: DCC for MCU VDD ≥ 1.8V
NanoDrive: D26 for MCU VDD = 1.8V
(“D26” recommended for lowest power)
NanoDrive: AA3
Appendix A provides details on how to enable, disable and program various operating modes of
the EFM32 LFXO oscillator.
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5 STMicroelectronics STM32
The STM32L152RBT6 is an ARM-based Cortex-M3 MCU. The internal RTC has a separate
accurate low frequency (LSE) oscillator. The LSE oscillator has the advantage of providing a low
power but highly accurate clock source for the real-time clock (RTC), peripheral clock/calendar or
other timing functions. The oscillator incorporates OSC32_IN and OSC32_OUT pins for crystal
connection. As an option, an external clock source can be routed directly to the OSC32_IN pin
after bypassing the on-chip oscillator by settings the MCU registers. By default the LSE oscillator
is switched off. Unlike the EFM32, the LSE oscillator supports two operating modes. Table 3 lists
the optimal settings of SiT15xx for each of the two operating modes of the LSE oscillator.
Table 3: SiT15xx Configuration for the Two STM-32 LSE Oscillator Modes
Mode-1: LSE
Enabled
Mode-2: LSE
Enabled with Sine
Wave Input
Mode-3: LSE Disabled
OSC32_IN, OUT
connections
SiT15xx pin-3 
OSC32_IN pin
OSC_OUT pin = NC
Not Supported
SiT15xx pin 3  OSC32_IN pin
OSC_OUT pin = NC
SiT15xx Output
Drive Settings
NanoDrive: D14
Not Applicable
LVCMOS: DCC for MCU VDD ≥1.8V
NanoDrive: D26 for MCU VDD = 1.8V
(“D26” recommended for lowest power)
Appendix B provides details on how to enable, disable and program various operating modes of
the STM32 LSE oscillator.
6 Renesas Electronics RL78G13
The R5F100LE is a 16-bit MCU based on the RL78 core. The MCU includes a low frequency
crystal oscillator (XT1) that can be used for clocking peripherals (including RTC) and the core if
necessary. The XT1 clock oscillator has two pins for a crystal connection XT1 and XT2. The
oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control
register (CSC). An external CMOS level clock can also be supplied to the EXCLKS/XT2 pin.
Table 4 lists the optimal settings of SiT15xx for each of the three operating modes of the XT1
oscillator.
Table 4: SiT15xx Configuration for the Three XT1 Oscillator Modes
Mode-1: LFXO
Enabled
Mode-2: LFXO Enabled
with Sine Wave Input
Mode-3: LFXO Disabled
XT1, XT2
Connection
SiT15xx pin 3 
XT1 pin
XT2 pin = NC
Not Supported
SiT15xx pin 3  XT2 pin
XT1 pin = NC
SiT15xx Output
Drive Settings
Contact Factory
Not Applicable
LVCMOS: DCC for MCU VDD ≥ 1.8V
NanoDrive: D26 for MCU VDD = 1.8V
(“D26” recommended for lowest power)
Appendix C provides details on how to enable, disable and program various operating modes of
the RL78G13 XT1 oscillator.
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7 Texas Instruments MSP430F2x
MSP430 microcontrollers from Texas Instruments are based on a 16-bit RISC CPU. The
architecture, combined with five different low-power modes is optimized to achieve extended
battery life in portable applications. MSP430 MCUs include the basic clock module that supports
low system cost and ultralow power consumption. The basic clock module includes low/high
frequency oscillator that can be used with low-frequency watch crystals, resonators or external
clock sources of 32768 Hz. The MCU has two XIN and XOUT pins for a crystal connection.
Table 5 lists the optimal settings of SiT153x for each of the three operating modes of the XT1
oscillator.
Table 5: SiT15xx Configuration for the Two LFXT Oscillator Modes
Mode-1: LFXT Enabled
Mode-3: LFXT Disabled
XIN, XOUT
connection
SiT15xx pin 3  XIN pin
XOUT pin = NC
SiT15xx pin 3  XIN pin
XOUT pin = NC
SiT15xx Output Drive Settings
Not Applicable
LVCMOS: DCC
Appendix D provides details on how to enable, disable and program various operating modes of
the MSP430 low frequency oscillator.
8 NXP LPC11xx
The LPC1100 MCUs are Cortex-M0 based MCUs running at speeds up to 50 MHz. The CortexM0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of
embedded applications. The MCU has several low power modes that enable to reach low power
consumption with high performance in portable applications: Sleep Mode, Deep Sleep Mode,
Power-Down Mode, and Deep Power-Down Mode.
The MCU incorporates the low power RTC oscillator providing 32768 Hz clock. Two pins
RTCXIN and RTCXOUT are used for a connection of a 32768 Hz crystal. The RTC oscillator is
always working despite the low power mode. The internal RTC oscillator cannot be bypassed.
Table 6 lists the optimal settings of SiT153x for applicable operating mode of the XT1 oscillator.
Table 6: SiT15xx Configuration for the RTC Oscillator Mode
Mode-1: RTC Oscillator Enabled
RTCXIN, XOUT connection
SiT15xx pin 3  RTCXIN pin
RTCXOUT pin = NC
SiT15xx Output Drive Settings
NanoDrive: D14
Appendix E provides details on how to enable, disable and program various operating modes of
the LPC1100 RTC oscillator.
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9 Freescale Kinetis L4x/L5x
The Kinetis L series MCUs are based on ARM Cortex-M0+ processors. These processors
feature low-power consumption in conjunction with high performance. The clock distribution
system of the MCU includes Multipurpose Clock Generator (MCS), Crystal Oscillator (XOSC)
and Real Time Clock (RTC) modules. A quartz crystal can be connected to the EXTAL32 and
XTAL32 pins. If the XOSC is bypassed an external clock may be supplied to the EXTAL32 pin.
The XOSC incorporates tunable on-chip load capacitors, that are controlled by an user
firmware. They exclude connecting external load capacitors to a crystal. Two oscillator modes of
operation are available: high-gain and low-power configurations. The high gain configuration
requires high voltage levels. Table below lists the optimal settings of the SiT153x for two
operating modes of the XOSC oscillator.
Table 7: SiT15xx Configuration for the XOSC Oscillator Modes
Mode-1: XOSC Enabled
Mode-3: XOSC Bypassed
XTAL32, EXTAL32 connection
SiT15xx pin 3  EXTAL32 pin
XTAL32 pin = NC
SiT15xx pin 3  EXTAL32 pin
XTAL32 pin = NC
SiT15xx Output Drive Settings
Contact Factory
LVCMOS: DCC
Appendix F provides details on how to enable, disable and program various operating modes of
the KL04/05 oscillator.
10 Microchip PIC18
The PIC18 MCUs are low-power 8-bit devices that allow flexible clock customization and simple
register access that enables designers to achieve low average power consumption in powersaving applications. The PIC18 devices include two oscillators. One is high-speed oscillator that
operates in the MHz frequency range. The second oscillator operates in low-power low
frequency using Timer1 and continues to operate while the core and other peripherals are in
power-saving mode.
The secondary oscillator includes two T1OSI and T1OSO pins for connecting an external clock
source. The table below shows two possible modes when using SiT153x devices as a clock
source. To achieve the lowest power consumption SiTime recommends using the bypass mode
(Mode-3). This eliminates additional current consumed by the on-chip secondary oscillator
circuit.
Table 8: SiT15xx Configuration for the Secondary Oscillator Modes
Mode-1: Secondary Oscillator
Enabled
Mode-3: Secondary
Oscillator Bypassed
T1OSI, T1OSO connection
SiT15xx pin 3  T1OSI pin
T1OSO pin = NC
SiT15xx pin 3  T1OSO pin
T1OSI pin = NC
SiT15xx Output Drive Settings
NanoDrive: D14
LVCMOS: DCC
Appendix G provides details on how to enable, disable and program various operating modes of
Secondary Oscillator.
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11 Appendix A: Programming the EnergyMicro EFM32 LFXO
11.1 EFM32 Clock Management Unit
All on-chip oscillators are controlled by a Clock Management Unit (CMU). The CMU provides
the capability to configure and turn on/off the clock on an individual basis to all peripheral
modules. It is possible to connect an external clock source to LFXTAL_N pin of the LFXO.
By configuring the LFXOMODE field in CMU_CTRL[12:11], the LFXO can be bypassed.
Table 9: CMU_CTRL - CMU Control Register
1
0
RW
HFXOMODE
0x0
3
2
RW
HFXOBOOST
0x3
5
4
RW
HFXOBUFCUR
0x1
7
6
RW
HFXOGLITCHDETEN
0
9
8
RW
HFXOTMEOUT
0x3
11
10
RW
LFXOMODE
0x0
13
12
RW
LFXOBOOST
1
15
14
17
16
RW
LFXOBUFCUR
0
19
18
RW
LFXOTMEOUT
0x3
21
20
0x0
RW
RW
Name
CLKOUTSEL0
Access
CLKOUTSEL1
0
Reset
23
22
25
24
27
26
29
28
0x02C
Bit Position
31
30
Offset
Table 10: The LFXOMODE Field
Value
Mode
Description
0
XTAL
1
BUFEXTCLK
2
DIGEXTCLK
32.768 kHz crystal oscillator
An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus
wave (32.768 kHz)
Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.
To bypass the on-chip oscillator write '0x2' to the LFXOMODE[12:11] field.
The oscillator setting takes effect when 1 is written to LFXOEN in CMU_OSCENCMD.
The oscillator setting is reset to default when 1 is written to LFXODIS in CMU_OSCENCMD.
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Table 11: CMU_OSCENCMD - Oscillator Enable/Disable Command Register
1
0
1
1
W1
W1
HFRCODIS
HFRCOEN
3
2
0
0
W1
W1
5
4
0
0
W1
W1
7
6
0
0
W1
W1
Name
LFRCODIS
LFRCOEN
AUXHFRCO
DIS
AUXHFRCO
EN
HFXODIS
HFXOEN
9
8
0
0
Access
W1
W1
Reset
LFXODIS
LFXOEN
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
0x02C
Bit Position
31
30
Offset
Table 12: OSCENCMD - The [31:3] Field Descriptions
Bit
31:10
Name
Reset
Access
Description
To ensure compatibility with future devices,
always write bits to 0.
Reserved
9
LFXODIS
Disables the LFXO. LFXOEN has higher priority if written
simultaneously.
0
W1
LFXO Disable
8
LFXOEN
Enables the LFXO.
0
W1
LFXO Enable
7
LFRCODIS
Disables the LFRCO. LFRCOEN has higher priority if
written simultaneously.
0
W1
LFRCO Disable
6
LFRCOEN
Enables the LFRCO.
0
W1
LFRCO Enable
5
AUXHFRCODIS
Disables the AUXHFRCO. AUXHFRCOEN has higher
priority if written simultaneously. Warning: Do not disable
this clock during a flash erase/write operation.
0
W1
AUXHFRCO
Disable
4
AUXHFRCOEN
Enables the AUXHFRCO.
0
W1
AUXHFRCO
Enable
3
HFXODIS
Disables the HFXO. HFXOEN has higher priority if written
simultaneously. Do not disable the HFRXO if this
oscillator is selected as the source for HFCLK.
0
W1
HFXO Disable
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Table 13: CMU_STATUS - Status Register
3
2
R 0
R 0
R 1
R 1
HFRCORDY
HFRCOENS
0
5
4
R 0
R 0
1
7
6
R 0
R 0
LFRCORDY
LFRCOENS
AUXHFRCO
RDY
AUXHFRCO
ENS
HFXORDY
HFXOENS
9
8
R 0
R 0
LFXORDY
LFXOENS
11
10
R 0
R 0
HFXOSEL
HFRCOSEL
13
12
R 0
R 0
LFXOSEL
LFRCOSEL
15
14
Name
R 0
Reset
Access
CALBSY
17
16
19
18
21
20
23
22
25
24
27
26
29
28
0x02C
Bit Position
31
30
Offset
Table 14: CMU_STATUS - The [14:8] Field Descriptions
Bit
31:15
14
13
12
11
10
9
8
Name
Reset
Reserved
To ensure compatibility with future devices, always write
bits to 0.
CALBSY
Calibration is on-going
LFXOSEL
LFXO is selected as HFCLK clock source
LFRCOSEL
LFRCO is selected as HFCLK clock source
HFXOSEL
HFXO is selected as HFCLK clock source
HFRCOSEL
HFRCO is selected as HFCLK clock source
LFXORDY
LFXO is enabled and start-up time has
exceeded
LFXOENS
LFXO is enabled
The Smart Timing Choice™
Access
Description
0
R
Calibration Busy
0
R
LFXO Selected
0
R
LFRCO Selected
0
R
HFXO Selected
1
R
HFRCO Selected
0
R
LFXO Ready
0
R
LFXO Enable
Status
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11.2 Configuring the LFXO
Below is a code snippet of LFXO configuration from IAR Embedded Workbench IDE:
1. Enable the LFXO oscillator by setting the LFXOEN bit in the CMU_OSCENCMD[8].
2. Wait until the LFXORDY bit in the CMU_STATUS[9] is set. Applicable only for the XTAL
mode, otherwise skip this step.
______________________________________________________________________________
CMU->CTRL &= ~(0x3 << 11);
CMU->CTRL
|= 0x00000000;
//CMU->CTRL |= 0x00000800;
//CMU->CTRL |= 0x00001000;
// (XTAL)32768 Hz crystal oscillator
// (BUFEXTCLK)AC coupled
// (DIGEXTCLK)an external clock source
// Lock CMU_CTRL
CMU->OSCENCMD = (0x1UL << 8);
/* Wait for clock to stabilize if requested
!!!Applicable only for crystal oscillator configuration!!! */
if (wait)
{
while (!(CMU->STATUS & (0x1 << 9)));
}
______________________________________________________________________________
The LFXO is able to operate from external clock sources with small signal amplitude (100mV
and above). This mode (AC mode - BUFEXTCLK) can be set by configuring the LFXMODE field
in the CMU_CTRL[12:11] register (see Table 9).
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12 Appendix B: Programming the STMicroelectronics STM32
LSE Oscillator
12.1 Low-speed External Clock Oscillator
The low-speed external (LSE) crystal oscillator can be switched on/off by setting/clearing the
LSEON bit in the RCC_CSR[8] register.
Table 15: Control/Status Register (RCC_CSR)
31
LPWR
RSTF
rw
30
WWDG
RSTF
rw
29
IWDG
RSTF
rw
28
SFT
RSTF
rw
23
RTC
RST
rw
22
RTC
EN
rw
21
20
15
14
13
Reserved
7
6
27
POR
RSTF
rw
19
26
PIN
RSTF
rw
18
25
24
OBLRSF
RMVF
rw
rw
17
Reserved
rw
12
LSECS
SD
r
5
11
LSECS
SON
rw
4
10
LSE
BYP
rw
3
2
Reserved
16
RTCSEL
[1:0]
rw
9
8
LSERDY
LSEON
r
rw
1
LSI
RDY
r
0
LSION
rw
The LSERDY flag in the RCC_CSR[9] register indicates whether the LSE crystal is stable or
not. At startup the LSE crystal output clock signal is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC_CIR[8] (Table 16).
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Table 16: Clock Interrupt Register (RCC_CIR)
31
30
29
28
27
26
25
24
Reserved
23
CSSC
W
15
Res
7
CSSF
r
22
LSECS
SC
w
21
MSI
RDYC
w
20
PLL
RDYC
w
19
HSE
RDYC
w
18
HSI
RDYC
w
17
LSE
RDYC
w
16
LSI
RDYC
w
14
LSECS
SIE
rw
13
MSI
RDYIE
rw
12
PLL
RDYIE
rw
11
HSE
RDYIE
rw
10
HSI
RDYIE
rw
9
LSE
RDYIE
rw
8
LSI
RDYIE
rw
6
LSE
RDYF
r
5
MSI
RDYF
r
4
PLL
RDYF
r
3
HSE
RDYF
r
2
HSI
RDYF
r
1
LSE
RDYF
r
0
LSI
RDYF
r
12.2 External Clock Source (LSE bypass)
It is possible to connect an external clock source to OSC32_IN pin of the LSE oscillator. This
feature is selected by setting the LSEBYP and LSEON bits in the RCC_CSR (Table 15). The
external clock signal (square, sine or triangle) with ~50% duty cycle has to drive the OSC32_IN
pin while the OSC32_OUT pin should be left unconnected (Hi-Z).
12.3 Clock Security System on LSE
The clock security system on the LSE oscillator can be activated by software writing the
LSECSSON in the RCC_CSR register (Table 15). This bit can be disabled only by a hardware
reset or RTC software reset, or after a failure detection on the LSE oscillator. LSECSSON must
be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY
and LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL. The
CSS on LSE is working in all modes: Run, Sleep, Stop and Standby.
If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to
the RTC but no hardware action is made to the registers. In Standby mode a wakeup is
generated. In other modes an interrupt can be sent to wake up. The software MUST then
disable the LSECSSON bit, stop the defective 32 kHz oscillator (disabling LSEON), and can
change the RTC clock source (no clock or LSI or HSE, with RTCSEL), or take any required
action to secure the application.
12.4 Clock-out Capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the external
MCO pin (PA8) using a configurable prescaler (1, 2, 4, 8, or 16). The configuration registers of
the corresponding GPIO port must be programmed in alternate function mode.
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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One of seven clock signals can be selected as the MCO clock:
 System clock (SYSCLK)
 Internal RC 16MHz (HSI) oscillator
 Internal 65 kHz to 4.2 MHz (MSI) oscillator
 External 1 to 24 MHz (HSE) oscillator
 PLL
 Internal low-power oscillator (LSI)
 Low-power 32.768 kHz external oscillator (LSE)
The selection is controlled by the MCOSEL[2:0] bits of the RCC_CFGR register (Table 17).
Table 17: Configuration Register (RCC_CFGR)
31
30
29
28
27
MCOPRE[2:0]
Res.
Res.
rw
rw
rw
15
14
13
12
11
PPRE2[2:0]
Reserved
rw
rw
rw
26
rw
24
MCOSEL[2:0]
rw
rw
9
8
PPRE1[2:0]
rw
rw
23
22
PLLDIV[1:0]
18
17
21
20
19
PLLMUL[3:0]
25
rw
10
Res.
rw
rw
rw
15
14
13
Reserved
7
rw
rw
rw
12
11
PPRE2[2:0]
rw
rw
rw
10
9
rw
rw
rw
3
2
SWS[1:0]
rw
rw
1
0
SW[1:0]
rw
6
5
HPRE1[3:0]
rw
rw
rw
16
PLL
SRC
rw
4
rw
8
PPRE1[2:0]
rw
Note: If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
Standby low power modes, and can be used as wake-up source. However, when the HSE clock
is used as RTC clock source, the RTC cannot be used in Stop and Standby low power modes.
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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12.5 Configuring LSE
1) Reset LSEON[8] and LSEBYP[10] bits in RCC_CSR before configuring the LSE.
IAR Embedded Workbench IDE example:
// #define RCC_LSE_OFF
((uint8_t)0x00)
/* Reset LSEON and LSEBYP bits before configuring the LSE --------*/
*(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
2) Set the new LSE configuration. Set LSEBYP[10] bit if you need the bypass mode and set the
LSEON bit. It can be performed simultaneously.
IAR Embedded Workbench IDE example:
// #define RCC_LSE_Bypass
// #define RCC_LSE_ON
((uint8_t)0x05)
((uint8_t)0x01)
/* Set the new LSE configuration ----------------------------------*/
*(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_ON;
// or *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_Bypass;
3) Wait until the LSERDY[9] bit in RCC_CSR is ready. This is applicable when using an external
crystal.
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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13 Appendix C: Programming the Renesas Electronics
RL78G13 XT1 Oscillator
13.1 XT1 Oscillator
The XT1 oscillator is a circuit with low gain in order to achieve low-power consumption. There
are AMPHS1[2], AMPHS0[1] fields in the CMC register (Table 20) that enables to choose
optimal gain for a crystal.
Table 18: Oscillation Mode Fields
AMPHS1
AMPHS0
XT1 oscillator oscillation mode selection
0
0
Low power consumption oscillation (default)
0
1
Normal oscillation
1
0
Ultra-low power consumption oscillation
1
1
Setting prohibited
13.2 Configuration XT1
1) Set the XTSTOP bit in CSC[6] to disable the XT1 oscillator.
2) Change the oscillation mode (AMPHS1, AMPHS0) if required.
3) Set the oscillator mode by setting/clearing EXCLKS, OSCSELS fields in the CMC
register (Table 20).
4) Clear the XTSTOP bit in CSC[6] (Table 19Error! Reference source not found.) to enable
the XT1 oscillator.
Table 19: CSC Register
Symbol
CSC
<7>
MSTOP
<6>
XTSTOP
5
0
MSTOP
0
1
X1 oscillation mode
X1 oscillator operating
X1 oscillator stopped
4
0
HIOSTOP
0
1
2
0
1
0
High-speed system clock operation control
External clock input mode
External clock from EXCLK pin is valid
External clock from EXCLK pin is invalid
XTSTOP
0
1
3
0
XT1 oscillation mode
XT1 oscillator operating
XT1 oscillator stopped
Subsystem clock operation control
External clock input mode
External clock from EXCLKS pin is valid
External clock from EXCLKS pin is
invalid
<0>
HIOSTOP
Input port mode
Input port
Input port
High-speed on-chip oscillator clock operation control
High-speed on-chip oscillator operating
High-speed on-chip oscillator stopped
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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Table 20: CMC Register
Symbol
CMC
7
EXCLK
6
OSCSEL
EXCLK
OSCSEL
0
0
1
1
0
1
0
1
EXCLKS
OSCSELS
0
0
1
1
0
1
0
1
AMPHS1
0
0
1
1
AMPHS0
0
1
0
1
AMPH
0
1
5
EXCLKS
4
OSCSELS
High-speed system clock pin
operation mode
Input port mode
X1 oscillation mode
Input port mode
External clock input mode
Subsystem clock pin
operation mode
3
0
2
AMPHS1
X1/P121 pin
1
AMPHS0
0
AMPH
X2/EXCLK/P122 pin
Input port
Crystal/ceramic resonator connection
Input port
Input port
External clock input
XT1/P123 pin
XT2/EXCLKS/P124 pin
Input port
Crystal resonator connection
Input port
Input port
External clock input
XT1 oscillator oscillation mode selection
Low power consumption oscillation (default)
Normal oscillation
Ultra-low power consumption oscillation
Setting prohibited
Control of X1 clock oscillation frequency
1 MHz ≤ fx ≤ 10 MHz
10 MHz ≤ fx ≤ 20 MHz
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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14 Appendix D: Programming the Texas Instruments MSP430
low frequency oscillator
14.1 The MSP430 LFXT Oscillator
The LFXT1 oscillator supports ultra-low current consumption using a 32768 Hz watch crystal in
LF mode (XTS = 0) or a high frequency crystal in HF mode. A watch crystal connects with the
XIN and XOUT pins without any other external components. The software-selectable XCAPx
bits configure the internally provided load capacitance for the LFXT1 crystal in LF mode. This
capacitance can be selected as 1 pF, 6 pF, 10 pF, or 12.5 pF typical. Additional external
capacitors can be added if necessary. The LFXT1 oscillator is not implemented in the
MSP430G22x0 device family.
The LFXT1 oscillator also supports high-speed crystals or resonators when in HF mode (XTS =
1, XCAPx = 00). The high-speed crystal or resonator connects to XIN and XOUT and requires
external capacitors on both terminals. When LFXT1 is in HF mode, the LFXT1Sx bits select the
range of operation. LFXT1 may be used with an external clock signal on the XIN pin in either LF
or HF mode when LFXT1Sx = 11, OSCOFF = 0, and XCAPx = 00. When used with an external
signal, the external frequency must meet the data sheet parameters for the chosen mode. When
the input frequency is below the specified lower limit, the LFXT1OF bit may be set preventing
the CPU from being clocked with LFXT1CLK.
Steps to configure the LFXT1 oscillator:
1) Set the mode in XTS and the divider value in DIVAx.
2) Choose mode by changing the LFXT1Sx bits in BCSCTL3.
3) Enable internal capacitors if needed. It is controlled by XCAPx in BCSCTL3.
4) Turn on the oscillator by clearing XT2OFF in BCSCTL1.
Table 21: BCSCTL1, Basic Clock System Control Register 1
Bit
Name
State
7
XT2OFF
rw-(1)
6
XTS
rw-(0)
XT2OFF
Bit 7
XTS
Bit 6
DIVAx
Bits 5-4
RSELx
Bits 3-0
The Smart Timing Choice™
5
4
DIVAx
rw-(0)
rw-(0)
3
rw-0
2
1
RSELx
rw-1
rw-1
0
rw-1
XT2 off. This bit turns off the XT2 oscillator
0 XT2 is on
1 XT2 if off
LFXT1 mode select
0 Low-frequency mode
1 High-frequency mode
Divider for ACLK
00 /1
01 /2
10 /4
11 /8
Range select. Sixteen different frequency ranges are
available. The lowest frequency range is selected by setting
RSELx = 0. RSEL3 is ignored when DCOR = 1
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SiT-AN10037 Rev 1.5
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Table 22: BCSCTL3, Basic Clock System Control Register 3
Bit
Name
State
7
6
XT2Sx
rw-0
rw-0
XT2Sx
Bits 7-6
LFXT1Sx
Bits 5-4
XCAPx
Bits 3-2
XT2OF
Bit 1
LFXT1OF
Bit 0
5
4
LFXT1Sx
rw-0
rw-0
3
2
XCAPx
rw-0
rw-1
1
XT2OF
r0
0
LFXT1OF
r-(1)
XT2 range select. These bits select the frequency range for XT2.
00
0.4- to 1-MHz crystal or resonator
01
1- to 3-MHz crystal or resonator
10
3- to 16-MHz crystal or resonator
11
Digital external 0.4- to 16-MHz clock source
Low-frequency clock select and LFXT1 range select. These bits select
between LFXT1 and VLO when XTS = 0, and select the frequency range
for LFXT1 when XTS = 1.
When XTS = 0:
When XTS = 1:
32768-Hz crystal on
0.4- to 1-MHz crystal
00
00
LFXT1
Reserved
1- to 3-MHz crystal
01
01
VLOCLK
3- to 16-MHz crystal
10
10
External clock source
0.4- to 16-MHz clock
11
11
source
Oscillator capacitor selection. These bits select the effective capacitance
seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFXT1Sx = 11
XCAPx should be 00.
~1 pF
00
~6 pF
01
~10 pF
10
~12.5 pF
11
XT2 oscillator fault
No fault condition present
0
Fault condition present
1
LFXT1 oscillator fault
No fault condition present
0
Fault condition present
1
Below is the configuration code of a base clock module example from IAR Embedded
Workbench IDE:
BCSCTL3 = 0x00;
BCSCTL1 = 0x00;
The Smart Timing Choice™
// 32768-Hz crystal, 1pF internal capacitor
// XT2 oscillator is on, Low-frequency mode
20
SiT-AN10037 Rev 1.5
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14.2 Clock-out Capability
The microcontroller can be easily configured to clock external on-board peripherals from one of
its pins. For this you need configure the PxSEL and PxSEL2 function registers that are used to
select the pin function. A pin has to be configured as an output by setting needed in PxDIR.
Below is code from IAR Embedded Workbench that configures it:
P2SEL = P2SEL | 0x01;
P2DIR = P2DIR | 0x01;
// Select ACLK function for pin
// Set direction of P2.0 to output
Table 23: PxSEL and PxSEL2
PxSEL2
PxSEL
0
0
I/O function is selected
Pin Function
0
1
Primary peripheral module function is selected
1
0
Reserved. See device-specific data sheet
1
1
Secondary peripheral module function is selected
14.3 Low-power Modes
The MSP430 devices have several low-power modes. Every LPMx low-power mode allows
developers to create an application with balanced power consumption. The low-power modes
are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register. The
advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the
status register is that the present operating mode is saved onto the stack during an interrupt
service routine.
The ACLK clock is working in LPM0-LPM3 modes. The LPM4 mode disables CPU and all
clocks.
Table 24: Status Register
15
14
13 12 11
Reserved
10
9
8
V
7
SCG1
6
SCG0
5
OSCOFF
4
CPUOFF
3
GIE
2
N
1
Z
0
C
Table 25: Low Power Modes and ACLK Clock
SCG1
SCG0
OSCOFF
CPUOFF
Mode
ACLK
0
0
0
0
Active
Enabled
0
0
0
1
LPM0
Enabled
0
1
0
1
LPM1
Enabled
1
0
0
1
LPM2
Enabled
1
1
0
1
LPM3
Enabled
1
1
1
1
LPM4
Disabled
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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15 Appendix E: Programming the NXP LPC1100 RTC
Oscillator
15.1 Configuring the RTC Oscillator
The system clock block generates all clocks for the chip. The system block incorporates the low
frequency RTC 32k oscillator. It provides a clock for the RTC block that resides in a separate
always-on voltage domain with battery back-up. The RTC oscillator is also located in the
always-on voltage domain. These circuits are always working independently of low-power
modes. The RTC oscillator is easily controlled by RTCOSCCTRL.
Table 26: RTC Oscillator 32 kHz Output Control RTCOSCCTRL
Bit
Symbol
Value
Description
Reset Value
Enable the RTC 32 kHz output.
0
31:1
RTCOSCEN
0
Disabled. 32 kHz output disabled.
1
Enabled. 32 kHz output enabled.
-
1
Reserved
-
There is no possibility to bypass the RTC oscillator. The external clock should be applied to the
RTCXIN pin.
15.2 Clock Output Capability
The LPC1100 devices feature a clock output function that routes the IRS oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin. You can configure the
MCU to get 32768 Hz clock from an I/O pin for on-board peripherals. To distribute 32k clock to
the CLKOUT pin you need set the RTC clock for the main clock domain. There are several
steps to do this:
Below is the code example from LPCXpresso IDE that configures the clock-out feature for
LPC11U68:
// 1) Enable a clock for the GPIO clock domain
LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << 6);
// 2) Set PLL input as a clock source of the main clock domain
LPC_SYSCTL->MAINCLKSEL = 0x1;
// 3) Configure the PIO0_1 as the CLKOUT pin
pIOCON->PIO0[1] = 0x1;
// 4) Set the main clock as a clock source for CLKOUT
LPC_SYSCTL->CLKOUTSEL = (uint32_t) 0x3;
// 5) Set divider to /1 for CLKOUT
LPC_SYSCTL->CLKOUTDIV = 1;
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
// 6) Set the RTC oscillator clock source as the clock source for the PLL
LPC_SYSCTL->SYSPLLCLKSEL = 0x3;
// 7) updated clock source for PLL
LPC_SYSCTL->SYSPLLCLKUEN = 0;
LPC_SYSCTL->SYSPLLCLKUEN = 1;
// update clock source for the main clock domain
LPC_SYSCTL->MAINCLKUEN = 0;
LPC_SYSCTL->MAINCLKUEN = 1;
// update clock source for CLKOUT
LPC_SYSCTL->CLKOUTUEN = 0;
LPC_SYSCTL->CLKOUTUEN = 0x1;
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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Table 27: System Clock Control SYSAHBCLKCTRL
Bit
0
Symbol
Value
SYS
0
1
1
ROM
0
1
2
RAM0
0
1
3
FLASHREG
0
1
4
FLASHARRAY
0
1
5
I2C0
0
1
6
GPIO
0
1
7
CT16B0
0
1
CT16B1
0
1
9
CT32B0
0
1
10
CT32B1
0
1
8
The Smart Timing Choice™
Description
Reset Value
This bit is read-only and always reads as 1. It
configures the always-on clock for the AHB, APB
bridges the Cortex-M0 core clocks, SYSCON, reset
control, SRAM0, and the PMU.
Writes to this bit are ignored.
Disable
Enable
Enables clock for ROM.
Disable
Enable
Enables clock for Main SRAM0.
Disable
Enable
Enables clock for flash register interface.
Disable
Enable
Enables clock for flash access.
Disable
Enable
Enables clock for I2C.
Disable
Enable
Enables clock for GPIO port registers.
Disable
Enable
Enables clock for 16-bit counter/timer 0.
Disable
Enable
Enables clock for 16-bit counter/timer 1.
Disable
Enable
Enables clock for 32-bit counter/timer 0.
Disable
Enable
Enables clock for 32-bit counter/timer 1.
Disable
Enable
24
1
1
1
1
1
0
1
0
0
0
0
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
Bit
Symbol
Value
11
SSP0
0
1
12
USART0
0
1
13
ADC
0
1
14
USB
0
1
15
WWDT
0
1
16
IOCON
0
1
17
-
18
SSP1
0
1
19
PINT
0
1
20
USART1
0
1
21
USART2
0
1
22
USART3_4
0
1
23
GROUP0INT
0
1
The Smart Timing Choice™
Description
Reset Value
Enables clock for SSP0.
Disable
Enable
Enables clock for USART0.
Disable
Enable
Enables clock for ADC.
Disable
Enable
Enables clock to the USB register interface.
Disable
Enable
Enables clock for WWDT.
Disable
Enable
Enables clock for I/O configuration block.
Disable
Enable
Reserved
Enables clock for SSP1.
Disable
Enable
Enables clock to GPIO Pin interrupt register
interface.
Disable
Enable
Enables clock to USART1 register interface.
Disable
Enable
Enables clock to USART2 register interface.
Disable
Enable
Enables clock to USART3 and USART4 register
interfaces.
Disable
Enable
Enables clock to GPIO GROUP0 interrupt register
interface.
Disable
Enable
25
1
0
0
1
0
0
0
0
0
0
0
0
0
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
Bit
Symbol
Value
24
GROUP1INT
0
1
25
I2C1
0
1
26
RAM1
27
USBSRAM
28
CRC
0
1
29
DMA
0
1
30
RTC
0
1
31
SCT0_1
0
1
0
1
0
1
Description
Enables clock to GPIO GROUP1 interrupt register
interface.
Disable
Enable
Enables clock for I2C1.
Disable
Enable
Enables clock for SRAM1 located at 0x2000 0000
to 0x2000 0800.
Disable
Enable
Enables USB SRAM/SRAM2 block located at
0x2000 4000 to 0x2000 4800.
Disable
Enable
Enables clock for CRC.
Disable
Enable
Enables clock for DMA.
Disable
Enable
Enables clock for RTC register interface.
Disable
Enable
Enables clock for SCT0 and SCT1.
Reset Value
0
0
0
1
0
0
0
0
Disable
Enable
Table 28: Main Clock Source Select MAINCLKSEL
Bit
Symbol
Value
Description
Reset Value
Clock source for main clock
1:0
31:2
SEL
-
The Smart Timing Choice™
0x0
IRC Oscillator
0x1
PLL input
0x2
Watchdog oscillator
0x3
PLL output
0
Reserved
-
26
SiT-AN10037 Rev 1.5
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Table 29: Digital Pin Control Register IOCON (PIO0_1)
Bit
Symbol
Value
0x0
0x1
0x2
0x3
0x4..0x7
2:0
FUNC
4:3
MODE
5
HYS
0
1
6
INV
9:7
-
0
1
-
10
OD
12:11
S_MODE
15:13
CLKDIV
31:16
-
0x0
0x1
0x2
0x3
0
1
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
The Smart Timing Choice™
Description
Selects pin function.
PIO0_1
CLKOUT
CT32B0_MAT2
USB_FTOGGLE
Selects function mode (on-chip pull-up/pull-down
resistor control).
Inactive (no pull-down/pull-up resistor enabled).
Pull-down resistor enabled.
Pull-up resistor enabled.
Repeater mode.
Hysteresis.
Disable
Enable
Invert input
Input not inverted (HIGH on pin reads as 1)
Input inverted (HIGH on pin reads as 0)
Reserved
Open-drain mode
Disable
Enable. Open-drain mode enabled
Digital filter sample mode.
Bypass input filter.
1 clock cycle.
2 clock cycles.
3 clock cycles.
Select peripheral clock divider for input filter sampling
clock IOCONCLKDIV. Value 0x7 is reserved.
IOCONCLKDIV0. Use IOCON clock divider 0.
IOCONCLKDIV1. Use IOCON clock divider 1.
IOCONCLKDIV2. Use IOCON clock divider 2.
IOCONCLKDIV3. Use IOCON clock divider 3.
IOCONCLKDIV4. Use IOCON clock divider 4.
IOCONCLKDIV5. Use IOCON clock divider 5.
IOCONCLKDIV6. Use IOCON clock divider 6.
Reserved
27
Reset Value
0
0x2
0
0
0
0
0
0
0
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
Table 30: CLKOUT Clock Source Select CLKOUTSEL
Bit
Symbol
1:0
SEL
31:2
-
Value
0x0
0x1
0x2
0x3
Description
Reset Value
CLKOUT clock source
IRC oscillator
Crystal oscillator (SYSOSC)
Watchdog oscillator
Main clock
Reserved
0
0
Table 31: CLKOUT Clock Divider CLKOUTDIV
Bit
Symbol
7:0
DIV
31:8
-
Value
0
1
to 255
Description
Reset Value
CLKOUT clock divider values
Disable CLKOUT clock divider.
Divide by 1.
Divide by 255.
Reserved
0
0
Table 32: System PLL Clock Source Select SYSPLLCLKSEL
Bit
Symbol
Value
0x0
0x1
0x2
1:0
SEL
0x3
31:2
-
Description
Reset Value
System PLL clock source
IRC
System oscillator. Crystal Oscillator.
Reserved
32 kHz clock. Select this option when the
32 kHz clock is the clock source for the
main clock and select the pll input in the
MAINCLKSEL register. Do not use the 32
kHz clock with the PLL.
Reserved
0
0
Table 33: System PLL Clock Source Update Enable Register SYSPLLCLKUEN
Bit
Symbol
0
ENA
31:1
-
The Smart Timing Choice™
Value
0
1
-
Description
Enable system PLL clock source update
No change
Update clock source
Reserved
28
Reset Value
1
-
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
Table 34: Main Clock Source Update Enable Register MAINCLKUEN
Bit
Symbol
0
ENA
31:1
-
Value
0
1
-
Description
Reset Value
Enable main clock source update
No change
Update clock source
Reserved
1
-
Table 35: CLKOUT Clock Source Update Enable Register CLKOUTUEN
Bit
Symbol
Value
0
ENA
31:1
-
0
1
-
The Smart Timing Choice™
Description
Reset Value
Enable CLKOUT clock source update
No change
Update clock source
Reserved
29
1
-
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
16 Appendix F: Programming the Freescale Kinetis L4x and
L5x System Oscillator
16.1 Programming Model
The MCU incorporates two modules managing a clock distribution. The selection and
multiplexing of system clock sources is controlled and programmed via the multipurpose clock
generator (MCG) module. The setting of clock dividers and module clock gating for the system
are programmed via the system integration module (SIM). The system oscillator, MCG and SIM
registers control the multiplexers, dividers and clock gates.
NOTE. After OSC is enabled and starts generating clocks, the configurations such as low
power and frequency range must not be changed.
The oscillator module has built-in load capacitors for a connected crystal. OSC0_CR controls
low power modes operation and the load capacitors. If ERCLKEN and EREFSTEN in
OSC0_CR are set, the OSC is in operation when the MCU enters Stop modes.
Table 36: OSC Control Register (OSCx_CR)
Bit
Symbol
Value
7
ERCLKEN
0
1
6
Reserved
External Reference Enable. Enables external reference clock (OSCERCLK).
External reference clock is inactive.
External reference clock is enabled.
This read-only field is reserved and always has the value 0.
EREFSTEN
External Reference Stop Enable. Controls whether or not the external reference
clock (OSCERCLK) remains enabled when MCU enters Stop mode.
External reference clock is disabled in Stop mode.
5
0
1
4
Reserved
3
SC2P
0
1
2
SC4P
0
1
1
SC8P
0
1
0
SC16P
0
1
Description
External reference clock stays enabled in Stop mode if ERCLKEN is set before
entering Stop mode.
This read-only field is reserved and always has the value 0.
Oscillator 2 pF Capacitor Load Configure. Configures the oscillator load.
Disable the selection.
Add 2 pF capacitor to the oscillator load.
Oscillator 4 pF Capacitor Load Configure. Configures the oscillator load.
Disable the selection.
Add 4 pF capacitor to the oscillator load.
Oscillator 8 pF Capacitor Load Configure. Configures the oscillator load.
Disable the selection.
Add 8 pF capacitor to the oscillator load.
Oscillator 16 pF Capacitor Load Configure. Configures the oscillator load.
Disable the selection.
Add 16 pF capacitor to the oscillator load.
The system oscillator supports 32 kHz oscillators as well as crystals with higher frequency (3 to
32 MHz). Three clocks are output from OSC module:
 OSCCLK for MCU system
 OSCERCLK for on-chip peripherals
 OSC32KCLK
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RANGE0 bits in MGC_C2[5:4] define frequency range for the crystal oscillator. You have to
clear RANGE0 bits to select the oscillator frequency range for 32 kHz operation.
The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096
cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes
XTL_CLK onto OSC_CLK_OUT. This counting time-out is used to guarantee output clock
stability.
Table 37: MCG Control 2 Register (MCG_C2)
Bit
7
Symbol
Value
LOCRE0
0
1
6
5-4
3
Reserved
RANGE0
HGO0
2
EREFS0
1
LP
0
IRCS
00
11
1x
0
1
Description
Loss of Clock Reset Enable. Determines whether an interrupt or a reset request
is made following a loss of OSC0 external reference clock. The LOCRE0 only
has an affect when CME0 is set.
Interrupt request is generated on a loss of OSC0 external reference clock.
Generate a reset request on a loss of OSC0 external reference clock.
This read-only field is reserved and always has the value 0.
Frequency Range Select. Selects the frequency range for the crystal oscillator
or external clock source. See the Oscillator (OSC) chapter for more details and
the device data sheet for the frequency ranges used.
Encoding 0 — Low frequency range selected for the crystal oscillator.
Encoding 1 — High frequency range selected for the crystal oscillator.
Encoding 2 — Very high frequency range selected for the crystal oscillator.
High Gain Oscillator Select. Controls the crystal oscillator mode of operation.
See the Oscillator (OSC) chapter for more details.
Configure crystal oscillator for low-power operation.
Configure crystal oscillator for high-gain operation.
0
1
External Reference Select. Selects the source for the external reference clock.
See the Oscillator (OSC) chapter for more details.
External reference clock requested.
Oscillator requested.
Low Power Select. Controls whether the FLL is disabled in BLPI and BLPE
modes. In FBE mode, setting this bit to 1 will transition the MCG into BLPE
mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode.
In any other MCG mode, LP bit has no affect.
FLL is not disabled in bypass modes.
FLL is disabled in bypass modes (lower power)
0
1
Internal Reference Clock Select. Selects between the fast or slow internal
reference clock source.
Slow internal reference clock selected.
Fast internal reference clock selected.
0
1
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Table 38: MCG Status Register (MCG_S)
Bit
7-5
4
Symbol
Reserved
CLKST
1
OSCINIT0
Description
0
1
Reserved. This field is reserved. This read-only field is reserved and always
has the value 0.
Interrupt request is generated on a loss of OSC0 external reference clock.
Generate a reset request on a loss of OSC0 external reference clock.
0
1
Internal Reference Status This bit indicates the current source for the FLL
reference clock. The IREFST bit does not update immediately after a write to
the IREFS bit due to internal synchronization between clock domains.
Source of FLL reference clock is the external reference clock.
Source of FLL reference clock is the internal reference clock.
00
01
10
11
Clock Mode Status. These bits indicate the current clock mode. The CLKST
bits do not update immediately after a write to the CLKS bits due to internal
synchronization between clock domains.
Encoding 0 — Output of the FLL is selected (reset default).
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Reserved.
IREFST
3-2
0
Value
OSC Initialization. This bit, which resets to 0, is set to 1 after the initialization
cycles of the crystal oscillator clock have completed. After being set, the bit is
cleared to 0 if the OSC is subsequently disabled. See the OSC module's
detailed description for more information.
IRCST
0
1
The Smart Timing Choice™
Internal Reference Clock Status. The IRCST bit indicates the current source
for the internal reference clock select clock (IRCSCLK). The IRCST bit does
not update immediately after a write to the IRCS bit due to internal
synchronization between clock domains. The IRCST bit will only be updated if
the internal reference clock is enabled, either by the MCG being in a mode that
uses the IRC or by setting the C1[IRCLKEN] bit.
Source of internal reference clock is the slow clock (32 kHz IRC).
Source of internal reference clock is the fast clock (4 MHz IRC).
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SiT-AN10037 Rev 1.5
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Table 39: System Options Register 2 (SIM_SOPT2)
Bit
31-28
Symbol
UART0SRC
25-24
TPMSRC
23-8
Reserved
CLKOUTSEL
4
RTCCLKOUTSEL
3-0
Reserved
The Smart Timing Choice™
Description
This field is reserved. This read-only field is reserved and always has the
value 0.
Reserved
27-26
7-5
Value
00
01
10
11
00
01
10
11
000
001
010
011
100
101
110
111
0
1
UART0 clock source select. Selects the clock source for the UART0
transmit and receive clock.
Clock disabled
MCGFLLCLK clock
OSCERCLK clock
MCGIRCLK clock
TPM clock source select. Selects the clock source for the TPM counter
clock
Clock disabled
MCGFLLCLK clock
OSCERCLK clock
MCGIRCLK clock
This field is reserved. This read-only field is reserved and always has the
value 0.
CLKOUT select. Selects the clock to output on the CLKOUT pin.
Reserved.
Reserved.
Bus clock.
LPO clock (1 kHz)
MCGIRCLK
Reserved.
OSCERCLK
Reserved.
RTC clock out select. Selects either the RTC 1 Hz clock or the OSC
clock to be output on the RTC_CLKOUT pin.
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
OSCERCLK clock is output on the RTC_CLKOUT pin.
This field is reserved. This read-only field is reserved and always has the
value 0.
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Table 40: MCG Control 4 Register (MCG_C4)
Bit
Symbol
Value
Description
DCO Maximum Frequency with 32.768 kHz Reference. The DMX32 bit
controls whether the DCO frequency range is narrowed to its maximum
frequency with a 32.768 kHz reference. The following table identifies
settings for the DCO frequency range.
7
NOTE: The system clocks derived from this source should not exceed their
specified maximums.
DMX3
FLL
DRST_DRS
2
Reference Range
Factor
DCO Range
0
640
31.25–39.0625 kHz
20–25 MHz
00
1
732
32.768 kHz
24 MHz
0
1280
31.25–39.0625 kHz
40–50 MHz
01
1
1464
32.768 kHz
48 MHz
0
1920
31.25–39.0625 kHz
60–75 MHz
10
1
2197
32.768 kHz
72 MHz
DMX32
2560
31.25–39.0625 kHz
80–100 MHz
2929
32.768 kHz
96 MHz
DCO has a default range of 25%.
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
DCO Range Select. The DRS bits select the frequency range for the FLL
output, DCOOUT. When the LP bit is set, writes to the DRS bits are
ignored. The DRST read field indicates the current frequency range for
DCOOUT. The DRST field does not update immediately after a write to the
DRS field due to internal synchronization between clock domains. See the
DCO Frequency Range table for more details.
Encoding 0 — Low range (reset default).
Encoding 1 — Mid range.
Encoding 2 — Mid-high range.
Encoding 3 — High range.
11
0
1
6-5
4-1
0
DRST_DR
S
00
01
10
11
0
1
FCTRIM
Fast Internal Reference Clock Trim Setting FCTRIM controls the fast
internal reference clock frequency by controlling the fast internal reference
clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts
twice as much as bit 0. Increasing the binary value increases the period,
and decreasing the value decreases the period. If an FCTRIM[3:0] value
stored in nonvolatile memory is to be used, it is your responsibility to copy
that value from the nonvolatile memory location to this register.
SCFTRIM
Slow Internal Reference Clock Fine Trim. SCFTRIM controls the smallest
adjustment of the slow internal reference clock frequency. Setting
SCFTRIM increases the period and clearing SCFTRIM decreases the
period by the smallest amount Possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your
responsibility to copy that value from the nonvolatile memory location to
this bit.
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Below is the code example from CodeWarrior Development Studio showing configuration to be
run with SiT1533AI-H4 in Mode-1.
// 1) Enable external reference clock (OSCERCLK) and disable all the
//
built-in load capacitors
OSC0_CR = 0xA0;
// 2) Configure MCG_C2. Set low frequency range for the crystal
//
oscillator, low power mode and select external reference
MCG_C2 &= ~(0x3C);
// 3) Select external reference
MCG_C2 |= 0x04;
// 4) Wait for oscillator initialization has completed
while((MCG_S & 0x2) != 0x2);
16.2 Clock Output Capability
The MCU has the RTC_CLKOUT pin that can be driven either with RTC 1 Hz or with the
OSCERCLK on-chip clock source. Control for this option is through SIM_SOPT2[4] bit.
SIM_SOPT2[7:5] bits control the clock source.
Below is the code example configuring the RTC_CLKOUT pin to be driven by a clock source:
// 1) Configure PTC13 pin as output
PORTB_PCR13 = (PORT_PCR_MUX(0x3));
// 2) Select clock source
SIM_SOPT2 |= (uint32_t) 0xD0;
The Smart Timing Choice™
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17 Appendix G: Programming the PIC18 MCU Secondary
Oscillator
The secondary oscillator is part of Timer1 and can be configured by customizing Timer1
registers. Timer1 can operate in three modes:
 Timer
 Synchronous Counter
 Asynchronous Counter
Timer1 requires clocking for operation. There are three clock sources:
 Internal Clock (system clock routed from high-speed oscillator or from internal RC oscillator)
 Secondary Oscillator (with a 32 kHz crystal connected)
 External Clock (from T1OSO pin)
When configuring the secondary oscillator, the user must provide a software time delay to
ensure proper start-up. When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. This means the values of TRISC are ignored and the pins are read as ‘0’.
PIC18 MCUs are simple devices to program. All Timer1 configurations can be accomplished in
one register. Timer1 is controlled by T1CON (Timer1 Control Register). It also contains the
Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or
clearing control bit TMR1ON (T1CON<0>).
Table 41: Timer1 Control Register (T1CON)
R/W-0
RD16
Bit7
R-0
T1RUN
Bit6
R/W-0
T1CKPS1
Bit5
Bit 7
RD16:
1
0
T1RUN:
1
0
T1CKPS<1:0>
11
10
01
00
T1OSCEN:
1
0
T1SYNC:
16-Bit Read/Write Mode Enable bit
Enables register read/write of Timer1 in one 16-bit operation
Enables register read/write of Timer1 in two 8-bit operations
Timer1 System Clock Status bit
Device clock is derived from Timer1 oscillator
Device clock is derived from another source
Timer1 Input Clock Prescale Select bits
1:8 Prescale value
1:4 Prescale value
1:2 Prescale value
1:1 Prescale value
Timer1 Oscillator Enable bit
Timer1 oscillator is enabled
Timer1 oscillator is shut off.
Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1
Do not synchronize external clock input
Synchronize external clock input
Timer1 uses the internal clock when TMR1CS = 0 and this bit is ignored.
Timer1 Clock Source Select bit
External clock from RC0/T1OSO/T13CKI pin (on the rising edge)
Internal clock (FOSC/4)
Timer1 On bit
Enables Timer1
Stops Timer1
Bit 6
Bit 5-4
Bit 3
Bit 2
1
0
Bit 1
Bit 0
TMR1CS:
1
0
TMR1ON:
1
0
The Smart Timing Choice™
R/W-0
T1CKPS0
Bit4
R/W-0
T1OSCEN
Bit3
36
R/W-0
T1SYNC
Bit2
R/W-0
TMR1CS
Bit1
R/W-0
TMR1ON
Bit0
SiT-AN10037 Rev 1.5
SiT15xx Optimized Drive Settings
Below are two code snippets for configuring the oscillator to operate in Mode-1 and Mode-3:
// Configure Secondary Oscillator in Mode-1
// enable Timer1 Oscillator
T1CON = 0x08;
// enabling Timer1 and switching to Secondary Oscillator clock
T1CON |= 0xC3;
// Configure Secondary Oscillator in Mode-3 (Bypass Mode)
// enabling Timer1 and switching to Secondary Oscillator clock
T1CON = 0xC3;
The Smart Timing Choice™
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SiT-AN10037 Rev 1.5
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Revision History
1.0
Version
Release Date
1/15/2014
Original document.
Change Summary
1.1
6/20/2014
Document was re-structured.
1.2
12/4/2014
Added Support for Freescale Kinetis
1.4
2/25/2015
Added support for Microchip PIC16
1.5
7/19/2016
Reduced the number of NanoDrive levels supported. Updated NanoDrive
settings across all MCU sections accordingly.
SiTime Corporation
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USA
Phone: 408-328-4400
http://www.sitime.com
© SiTime Corporation, 2008-2016. The information contained herein is subject to change at any time without notice. SiTime
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The Smart Timing Choice™
38
SiT-AN10037 Rev 1.5
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