MAX97003 High-Efficiency, Low-Noise Audio

19-6044; Rev 0; 9/11
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
General Description
Features
The MAX97003 audio subsystem combines a mono
speaker amplifier with a stereo headphone amplifier. The
headphone and speaker amplifiers have independent
volume and on/off controls. The four inputs are configurable as two differential or four single-ended inputs.
S2.7V to 5.5V Speaker Supply Voltage
S1.8V Headphone Supply Voltage
S1.0W Speaker Output (VPVDD = 4.2V, ZSPK = 8I +
68µH, 1% THD+N)
To minimize output noise, both the headphone and
speaker outputs utilize a downward expander/noise gate
to attenuate noise when no desired input signal is present.
S32mW/Channel Headphone Output (RHP = 32I)
The speaker output incorporates an adjustable dynamic
range compressor (DRC) and distortion limiter to protect
the speaker and maximize loudness. This allows high
gain for low-level signals without compromising the quality of large signals.
SEfficient Class H Headphone Amplifier
All controls are performed using the two-wire I2C inter-
SIntegrated Expander/Noise Gate for Low Output
Noise
SActive Emissions Limiting for Enhanced EMI
Reduction
SGround-Referenced Headphone Outputs
SHeadphone Ground Sense
S2 Stereo Single-Ended/Mono Differential Inputs
face. The IC operates in the extended -40NC to +85NC
temperature range, and is available in the 2.0mm x
2.4mm, 20-bump WLP package (0.4mm pitch).
SIntegrated DRC (Speaker Outputs)
SIntegrated Distortion Limiter (Speaker Outputs)
Applications
SExtensive Click-and-Pop Reduction Circuitry
STDMA Noise Free
Cell Phones
S2.0mm x 2.4mm, 20-Bump WLP Package (0.4mm
Pitch)
Portable Media Players
Ordering Information appears at end of data sheet.
Simplified Block Diagram
1.8V
I2C
BATTERY
POWER SUPPLY
STEREO/
MONO
INPUT
CONTROL
DRC AND
EXPANDER
VOLUME
CLASS D
AMPLIFIER
LIMITER
EXPANDER
STEREO/
MONO
INPUT
VOLUME
CLASS H
AMPLIFIER
CHARGE
PUMP
MAX97003
HEADPHONE
GROUND
SENSE
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX97003.related.
����������������������������������������������������������������� Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bump Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Dynamic Range Compressor (DRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Speaker Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ground Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Volume-Change Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Volume Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Enhanced Volume Smoothing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Volume Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Volume Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
TABLE OF CONTENTS (continued)
Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Expander (Noise Gate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Speaker Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Output Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Advanced Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
����������������������������������������������������������������� Maxim Integrated Products 3
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
LIST OF FIGURES
Figure 1. Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Stereo Single-Ended and Differential Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. EMI with 12in of Speaker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Low-Signal to High-Signal Transition, No Clipping, DRC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Low-Signal to High-Signal Transition, Increased Gain, DRC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Low-Signal to High-Signal Transition, Increased Gain, DRC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. DRC Gain Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Expander Gain Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. High-Signal to Low-Signal Transition, Expander Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. High-Signal to Low-Signal Transition, Expander Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. High-Signal to Low-Signal Transition, Speaker Expander with Speaker Low-Power Mode . . . . . . . . . . . . . 26
Figure 12. Limiter Gain Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Traditional Amplifier Output vs. MAX97003 DirectDrive Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. I2C Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. START, STOP, and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. Writing 1 Byte of Data to the IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19. Writing n-Bytes of Data to the IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. Reading One Byte of Data from the IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21. Reading n-Bytes of Data from the IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22. Optional Class D Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. WLP Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
����������������������������������������������������������������� Maxim Integrated Products 4
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
LIST OF TABLES
Table 1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2. Volume Readback Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3. Input Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4. Mixer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5. Headphone Volume Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. Dynamic Range Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. Expander Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. Distortion Limiter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Speaker Low-Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Output Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Advanced Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 12. Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
����������������������������������������������������������������� Maxim Integrated Products 5
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Functional Diagram/Typical Application Circuit
1.6V TO 2.0V
10µF
2.7V TO 5.5V
0.1µF
1µF
VDD
PVDD
C3
1µF
C1
PGAINA
-3dB TO +12dB
INA1 D4
BIAS
HPLVOL:
-63dB TO 0dB
INADIFF
1µF
INA2 D5
A5 HPL
0dB TO 6dB
HPLEN
HPLMIX
PGAINA
-3dB TO +12dB
HPVSS
EXPANDER
+
B4 HPSNS
HPVDD
MIX
A4 HPR
0dB TO 6dB
1µF
PGAINB
-3dB TO +12dB
INB1 C4
HPRVOL:
-63dB TO 0dB
HPRMIX
INBDIFF
PGAINB
-3dB TO +12dB
INB2 C5
HPREN
HPVSS
PVDD
SPKVOL:
-63dB TO 0dB
D1 SPKP
+12dB TO 24dB
MIX
1µF
D2 SPKN
SPKEN
SPKMIX
PGND
DRC AND
EXPANDER
+
THD LIMITER
THDCLP
VDD
VDD
SDA C2
SCL B2
B5 BIAS
HPVDD
MIX
1µF
10µF
MAX97003
CONTROL
CHARGE PUMP
B1
GND
D3
PGND
A2
A1
B3
A3
C1P
C1N
CPVDD
CPVSS
1µF
1µF
1µF
����������������������������������������������������������������� Maxim Integrated Products 6
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to GND.)
VDD, CPVDD.........................................................-0.3V to +2.2V
BIAS........................................................... -0.3V to (VDD + 0.3V)
PVDD.....................................................................-0.3V to +6.0V
PGND....................................................................-0.1V to +0.1V
CPVSS.................................................................. -2.2V to +0.3V
C1N.................................... (VCPVSS - 0.3V) to (VCPVDD + 0.3V)
C1P...................................................... -0.3V to (VCPVDD + 0.3V)
HPL, HPR........................... (VCPVSS - 0.3V) to (VCPVDD + 0.3V)
INA1, INA2, INB1, INB2........................................-0.3V to +6.0V
SDA, SCL..............................................................-0.3V to +6.0V
SPKP, SPKN...........................................-0.3V to (VPVDD + 0.3V)
HPSNS...................................................................-0.3V to +0.3V
Continuous Current In/Out of PVDD, PGND, SPK_........ Q800mA
Continuous Current In/Out of HPR, HPL, VDD............... Q140mA
Continuous Input Current (all other pins)......................... Q20mA
Duration of SPK_ Short Circuit to GND or PVDD.......Continuous
Duration of Short Circuit Between SPKP and SPKN.... Continuous
Duration of HP_ Short Circuit to GND or VDD............Continuous
Continuous Power Dissipation (TA = +70NC)
WLP Multilayer Board
(derate 21.7mW/NC above +70NC).................................1.74W
Junction Temperature......................................................+150NC
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -65NC to +150NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Speaker Amplifier Supply
Voltage Range
Headphone Amplifier Supply
Voltage Range
SYMBOL
CONDITIONS
TYP
MAX
UNITS
PVDD
Guaranteed by PSRR test
2.7
5.5
V
VDD
Guaranteed by PSRR test
1.6
2
V
IVDD
1.21
1.6
IPVDD
1.07
1.3
IVDD
2.46
2.95
IPVDD
1.34
1.6
IVDD
0.1
0.15
IPVDD
2.25
2.6
IVDD
1.35
1.65
IPVDD
2.6
2.95
1.21
1.6
2.74
3.2
HP mode, TA = +25NC, stereo
SE input on INA routed to HP
output, HP expander disabled
HP mode, TA = +25NC, stereo
SE input on INA routed to HP
output, HP expander enabled
Quiescent Current
MIN
IDD
SPK mode, TA = +25NC mono
differential input on INA routed
to SPK output; SPK expander,
DRC, and limiter all disabled
SPK mode, TA = +25NC mono
differential input on INA routed
to SPK output; SPK expander,
DRC, and limiter all enabled
SPK + HP mode, TA = +25NC
IVDD
stereo SE input on INA routed
to HP and SPK output; SPK and
HP expanders, DRC, and limiter
IPVDD
all disabled
mA
����������������������������������������������������������������� Maxim Integrated Products 7
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Shutdown Current
SYMBOL
ISHDN
Turn On-Time
MIN
TYP
MAX
IVDD, TA = +25NC
CONDITIONS
0.08
2.5
IPVDD, TA = +25NC
0.05
1
SLEW = 0
17
SLEW = 1
10
-3dB to +9dB
15
20.4
28.5
+10.5dB to +12dB
5.2
6.96
9.5
-3.2
-2.98
-2.79
tON
Time from power-on
to full operation
RIN
TA = +25NC
UNITS
FA
ms
PREAMPLIFIERS
Input Resistance
PGAIN_ = 0x0
PGAIN_ = 0x1
-1.49
PGAIN_ = 0x2 Gain
Maximum Input Signal Swing
Common-Mode Rejection Ratio
Input DC Voltage
CMRR
Bias Voltage
VBIAS
kI
-0.22
-0.02
PGAIN_ = 0x3 1.57
PGAIN_ = 0x4 3.04
PGAIN_ = 0x5 4.52
PGAIN_ = 0x6 6.06
PGAIN_ = 0x7 7.51
PGAIN_ = 0x8 9.01
PGAIN_ = 0x9 10.59
+0.21
dB
PGAIN_ = 0xA 11.82
12
12.36
Preamp = 0dB
2.4
VP-P
63
dB
IN__ inputs
1.2
1.23
1.275
V
1.2
1.23
1.275
V
TA = +25NC (volume at mute,
SPKGAIN = 00)
Q0.5
Q2.5 TA = +25NC (volume at 0dB,
SPKGAIN = 00)
Q1.0
-72
f = 1kHz (differential input mode), 0dB
SPEAKER AMPLIFIER
Output Offset Voltage
Click-and-Pop Level
VOS
KCP
Peak voltage,
TA = +25NC,
A-weighted,
32 samples per
second, volume at
0dB, SPKGAIN = 00
(Note 2)
Into shutdown
mV
dBV
Out of shutdown
-65
����������������������������������������������������������������� Maxim Integrated Products 8
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
65
90.4
f = 217Hz,
VRIPPLE = 200mVP-P
80
f = 1kHz,
VRIPPLE = 200mVP-P
78
f = 10kHz,
VRIPPLE = 200mVP-P
72
ZSPK = 8I + 68FH,
VPVDD = 4.2V
1007
ZSPK = 8I + 68FH,
VPVDD = 3.6V
735
ZSPK = 4I + 33FH,
VPVDD = 5.0V
2585
VPVDD = 2.7V to
5.5V
Power-Supply Rejection Ratio
(Note 2)
Output Power (Note 3)
Total Harmonic Distortion Plus
Noise
Output Noise
PSRR
POUT
THD+N
TA = +25NC
THD+N = 1%
f = 1kHz, POUT = 700mW, TA = +25NC,
ZSPK = 8I + 68FH
dB
0.048
Noise gate disabled
40
Noise gate enabled
25
Noise gate disabled
93
Noise gate enabled
98
298.9
kHz
Q10
kHz
SNR
A-weighted,
POUT = 700mW
Output Frequency
fOSC
Spread spectrum
SPKGAIN = 00
Gain
0.06
0.029
Signal-to-Noise Ratio
Spread-Spectrum Bandwidth
mW
%
f = 1kHz, POUT = 350mW, TA = +25NC,
ZSPK = 8I + 68FH
A-weighted
UNITS
SPKGAIN = 01
FVRMS
dB
11.69
15.4
15.65
SPKGAIN = 10
19.64
SPKGAIN = 11
23.7
15.92
dB
Current Limit
2
A
Efficiency
h
92
%
Volume Control
POUT = 1W, f = 1kHz, ZSPK = 8I + 68FH
SPKVOL = 0x00
-63.35
-62.87
-62.36
SPKVOL = 0x3F
-0.044
0
0.13
Volume Control Step Size
1
dB
Mute Attenuation
f = 1kHz
118
dB
dB
����������������������������������������������������������������� Maxim Integrated Products 9
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
80
83.3
86
665
500
UNITS
CHARGE PUMP
Charge-Pump Frequency
Positive Output Voltage
VCPVDD
Negative Output Voltage
VCPVSS
Output Voltage Threshold
VTH
Mode Transition Timeouts
VHPL = VHPR = 0V
VHPL = VHPR = 0.2V
kHz
VHPL = VHPR = 0.5V
VOUT > VTH
VDD
VOUT < VTH
VDD/2
VOUT > VTH
VOUT < VTH
-VDD
-VDD/2
QVDD
x 0.216
QVDD
x 0.25
QVDD
x 0.278
V
Time it takes for the charge pump to
transition from invert to split mode
30
ms
Time it takes for the charge pump to
transition from split to invert mode
20
Fs
Q0.15
Q0.5 mV
-73
Output voltage at which the charge pump
switches modes, VOUT rising or falling
V
V
HEADPHONE AMPLIFIERS
Output Offset Voltage
Click-and-Pop Level
Power-Supply Rejection Ratio
(Note 2)
VOS
TA = +25NC
KCP
Peak voltage,
TA = +25NC,
A-weighted,
32 samples per
second, volume at
0dB (Note 2)
PSRR
TA = +25NC
Into shutdown
dBV
Out of shutdown
-73
VDD = 1.6V to 2.0V
65
99.9
f = 217Hz,
VRIPPLE = 200mVP-P
93
f = 1kHz,
VRIPPLE = 200mVP-P
88
f = 20kHz,
VRIPPLE = 200mVP-P
65
dB
���������������������������������������������������������������� Maxim Integrated Products 10
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Output Power
SYMBOL
POUT
Channel-to-Channel Gain
Tracking
Total Harmonic Distortion Plus
Noise
Output Noise
THD+N
Signal-to-Noise Ratio
Capacitive Drive
SNR
CL
Crosstalk
CONDITIONS
THD+N = 1%,
PGAINA = -1.5dB,
HPGAIN = +2dB
THD+N = 0.1%,
PGAINA = -1.5dB,
HPGAIN = +2dB
MIN
TYP
MAX
RHP = 16I
42
RHP = 32I
32
RHP = 32I
27
0.25
1.5 0.005
0.006
Noise gate disabled
10
Noise gate enabled
5.9
Noise gate disabled
94.2
Noise gate enabled
96.4
1000
-78
HPL to HPR, volume at 0dB, HPLMIX =
0x1, HPRMIX = 0x2, IN_DIFF = 0
RHP = 32I, POUT = 10mW, f = 1kHz
RHP = 16I, POUT = 10mW, f = 1kHz
A-weighted
A-weighted,
POUT = 10mW
HPL to HPR, HPR
to HPL, RHP = 32I,
POUT = 10mW
f = 20Hz to 10kHz
Volume Control
%
%
FVRMS
dB
pF
-83
-0.53
-0.25
HPGAIN = 01
1.72
HPGAIN = 10
3.72
HPGAIN = 11
5.85
+0.09
dB
HP_VOL = 0x00
-63.74
-63.3
-62.9
HP_VOL = 0x3F
-0.50
-0.27
+0.09
1
dB
100
dB
Volume Control Step Size
Mute Attenuation
mW
dB
f = 1kHz
HPGAIN = 00
Gain
UNITS
f = 1kHz
dB
SPEAKER DRC
Release Time
Attack Time
Compression Ratio
DRCRLS = 000
800
DRCRLS = 101
25
DRCATK = 000
0.5
DRCATK = 111
50
DRCEN = 001
1.34:1
DRCEN = 101
J:1
ms/
step
ms
ratio
���������������������������������������������������������������� Maxim Integrated Products 11
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured single-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
Compression Threshold
CONDITIONS
MIN
TYP
MAX
DRCTH = 0x01
0.839
DRCTH = 0x1F
0.199
EXP_ATK = 000
500
EXP_ATK = 101
25 EXP_ATK = 110
15
Low-signal to high-signal transition
0.2
EXP_TH = 0x1
32
EXP_TH = 0xF
1
THDCLP = 0x1
<1
THDCLP = 0xF
24
UNITS
VRMS
SPEAKER AND HEADPHONE EXPANDER
High signal to low
signal transition
Attack Time
Release Time
Expander Threshold
ms/
step
ms/
step
mVP
SPEAKER DISTORTION LIMITER
Distortion Threshold
Attack Time
Release Time
%
0.5
THDRLS = 000
0.076
THDRLS = 111
6.2
ms
s
DIGITAL I/O CHARACTERISTICS
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA and SCL)
Input Voltage High
ViH
Input Voltage Low
VIL
Input Hysteresis
0.7 x
VDD
V
0.4 x
VDD
V
VHYS
200
mV
Input Capacitance
CIN
10
pF
Input Leakage Current
IIN
TA = +25NC
Q1.0
FA
Input Leakage Current
IIN
VDD = 0V, TA = +25NC
Q1.0
FA
0.4
V
DIGITAL OUTPUTS (SDA Open Drain)
Output Low Voltage SDA
VOL
ISINK = 3mA
���������������������������������������������������������������� Maxim Integrated Products 12
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
I2C TIMING CHARACTERISTICS
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
Serial-Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
Hold Time (Repeated) START
Condition
tHD,STA
0.6
Fs
SCL Pulse-Width Low
tLOW
1.3
Fs
SCL Pulse-Width High
tHIGH
0.6
Fs
Setup Time for a Repeated
START Condition
tSU,STA
0.6
Fs
Data Hold Time
tHD,DAT
0
Data Setup Time
tSU,DAT
100
ns
ns
900
ns
SDA and SCL Receiving Rise
Time
tR
(Note 4)
20 +
0.1CB
SDA and SCL Receiving Fall
Time
tF
(Note 4)
20 +
0.1CB
300
ns
SDA Transmitting Fall Time
tF
(Note 4)
20 +
0.1CB
250
ns
0.6
Setup Time for STOP Condition
tSU,STO
Bus Capacitance
CB
Pulse Width of Suppressed Spike
tSP
Note
Note
Note
Note
0
Fs
400
pF
50
ns
1: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
2: Amplifier inputs are AC-coupled to GND.
3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load.
4:CB is in pF.
���������������������������������������������������������������� Maxim Integrated Products 13
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
GENERAL
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
IPVDD SPK MODE
EXPANDER, DRC,
AND LIMITER DISABLED
IPVDD
0.09
SHUTDOWN CURRENT (µA)
SUPPLY CURRENT (mA)
2.5
0.10
MAX97003 toc01
3.0
2.0
1.5
1.0
MAX97003 toc02
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.5
0.01
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SPEAKER AMPLIFIER
1
POUT = 800mW
0.01
1
POUT = 1.5W
0.1
0.01
0.001
1k
FREQUENCY (Hz)
10
1
0.1
SSM
0.01
POUT = 200mW
100
VPVDD = 4.2V
ZSPK = 8I + 68µH
POUT = 600mW
POUT = 500mW
0.001
10
100
10k
100k
MAX97003 toc05
VPVDD = 4.2V
ZSPK = 4I + 33µH
10
THD+N RATIO (%)
THD+N RATIO (%)
10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
THD+N RATIO (%)
VPVDD = 4.2V
ZSPK = 8I + 68µH
0.1
100
MAX97003 toc03
100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX97003 toc04
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
FFM
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 14
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
SPEAKER AMPLIFIER
0.1
f = 1kHz
0.01
f = 6kHz
0.1
f = 1kHz
0.01
f = 100kHz
0.001
1.0
1.5
2.0
f = 100kHz
0.001
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
VPVDD = 3.6V
ZSPK = 8I + 68µH
f = 6kHz
0.1
f = 1kHz
0.01
f = 100kHz
0.001
1.0
1.5
2.0
OUTPUT POWER (W)
2.5
3.0
1
f = 6kHz
0.1
f = 1kHz
0.01
f = 100kHz
0.001
0.5
VPVDD = 3.6V
ZSPK = 4I + 33µH
10
THD+N RATIO (%)
THD+N RATIO (%)
10
1
100
MAX97003 toc10
100
1.6
MAX97003 toc11
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
f = 1kHz
0
f = 1kHz
OUTPUT POWER (W)
f = 6kHz
0.01
0.1
OUTPUT POWER (W)
10
0.1
f = 6kHz
OUTPUT POWER (W)
VPVDD = 4.2V
ZSPK = 4I + 33µH
1
2.5
MAX97003 toc09
100
0.5
1
0.01
f = 100kHz
0.001
0
THD+N RATIO (%)
1
VPVDD = 4.2V
ZSPK = 8I + 68µH
10
THD+N RATIO (%)
f = 6kHz
VPVDD = 5V
ZSPK = 4I + 33µH
10
THD+N RATIO (%)
THD+N RATIO (%)
10
100
MAX97003 toc07
VPVDD = 5V
ZSPK = 8I + 68µH
1
100
MAX97003 toc06
100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX97003 toc08
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
f = 100kHz
0.001
0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
1.0
1.2
0
0.5
1.0
1.5
2.0
OUTPUT POWER (W)
���������������������������������������������������������������� Maxim Integrated Products 15
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
SPEAKER AMPLIFIER
60
50
40
60
50
40
30
20
20
VPVDD = 4.2V
fIN = 1kHz
0
0
0.5
1.0
1.5
2.0
ZSPK = 8I + 68µH
fIN = 1kHz
2.0
1.5
10% THD+N
1.0
1% THD+N
0.5
VPVDD = 3.6V
fIN = 1kHz
10
0
2.5
MAX97003 toc14
ZSPK = 4I + 33µH
70
30
10
0
0.5
1.0
1.5
0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT POWER (mW)
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
OUTPUT POWER vs. SUPPLY VOLTAGE
OUTPUT POWER vs. LOAD RESISTANCE
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY
10% THD+N
2.0
1.5
1% THD+N
1.0
3.0
THD+N = 10%
2.0
1.5
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
MAX97003 toc17
100
60
40
THD+N = 1%
VPVDD = 4.2V
VRIPPLE = 200mVP-P
ZSPK = 8I + 68µH
INPUTS AC-COUPLED TO GND
20
0.5
0
5.5
80
2.5
1.0
0.5
120
PSRR (dB)
3.0
2.5
3.5
OUTPUT POWER (W)
3.5
VPVDD = 4.2V
ZSPK = LOAD + 68µH
fIN = 1kHz
MAX97003 toc16
ZSPK = 4I + 33µH
fIN = 1kHz
4.0
4.0
MAX97003 toc15
4.5
OUTPUT POWER (W)
80
2.5
OUTPUT POWER (W)
ZSPK = 4I + 33µH
70
ZSPK = 8I + 68µH
90
EFFICIENCY (%)
EFFICIENCY (%)
80
100
MAX97003 toc12
90
OUTPUT POWER vs. SUPPLY VOLTAGE
EFFICIENCY vs. OUTPUT POWER
ZSPK = 8I + 68µH
MAX97003 toc13
EFFICIENCY vs. OUTPUT POWER
100
0
0
1
10
100
LOAD RESISTANCE (I)
1k
10
100
1k
10k
100k
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 16
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
SPEAKER AMPLIFIER
60
40
20
0
3.0
3.5
4.0
4.5
-80
-80
-100
-120
-120
-140
0
5k
10k
15k
20k
5k
0
10k
15k
FREQUENCY (Hz)
FREQUENCY (Hz)
WIDEBAND OUTPUT SPECTRUM
WIDEBAND OUTPUT SPECTRUM
SPEAKER VOLUME GAIN
vs. SPKVOL CODE
-60
-80
-100
-20
-40
-60
-80
-100
-120
10
FREQUENCY (MHz)
100
0
-10
-20
-30
-40
-50
-60
-70
-120
1
20k
MAX97003 toc23
RBW = 100Hz
SSM
SPEAKER VOLUME GAIN (dB)
-40
0
MAX97003 toc22
RBW = 100Hz
FFM
0.1
-60
-100
-140
5.5
MAX97003 toc21
OUTPUT AMPLITUDE (dBV)
-60
-40
SUPPLY VOLTAGE (V)
0
-20
5.0
OUTPUT AMPLITUDE (dBV)
2.5
-40
FFM
fIN = 1kHz
-20
AMPLITUDE (dBV)
AMPLITUDE (dBV)
PSRR (dB)
80
SSM
fIN = 1kHz
-20
INBAND OUTPUT SPECTRUM
0
MAX97003 toc19
VRIPPLE = 200mVP-P
fIN = 1kHz
INPUTS AC-COUPLED TO GND
100
INBAND OUTPUT SPECTRUM
0
MAX97003 toc18
120
MAX97003 toc20
POWER-SUPPLY REJECTION
RATIO vs. SUPPLY VOLTAGE
0.1
1
10
FREQUENCY (MHz)
100
0
10
20
30
40
50
60
70
SPKVOL CODE (NUMERIC)
���������������������������������������������������������������� Maxim Integrated Products 17
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
SPEAKER AMPLIFIER
SHUTDOWN RESPONSE
TURN-ON RESPONSE
MAX97003 toc24
MAX97003 toc25
SCL
2V/div
VS2EN = 0
SLEW = 0
ZCD = 0
SCL
2V/div
VS2EN = 0
SLEW = 0
ZCD = 0
SPEAKER
OUTPUT
200mA /div
SPEAKER
OUTPUT
200mA /div
2ms/div
4ms/div
HEADPHONE AMPLIFIER
0.1
POUT = 5mW
0.01
10
100
1
0.1
1k
FREQUENCY (Hz)
10k
10
1
0.1
f = 6kHz
f = 1kHz
0.01
POUT = 25mW
0.001
100k
RHP = 32I
POUT = 10mW
0.01
POUT = 20mW
0.001
100
THD+N RATIO (%)
THD+N RATIO (%)
THD+N RATIO (%)
1
VPVDD = 4.2V
VDD = 1.8V
RHP = 16I
10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX97003 toc27
VPVDD = 4.2V
VDD = 1.8V
RHP = 32I
10
100
MAX97003 toc26
100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX97003 toc28
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
10
100
1k
FREQUENCY (Hz)
10k
100k
f = 100Hz
0.001
0
0.010
0.020
0.030
0.040
0.050
0.005
0.015
0.025
0.035
0.045
OUTPUT POWER (W)
���������������������������������������������������������������� Maxim Integrated Products 18
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
HEADPHONE AMPLIFIER
POWER DISSIPATION
vs. OUTPUT POWER
f = 6kHz
f = 1kHz
0.01
0
0.01
0.02
RLOAD = 32I
50
40
30
0.04
0.05
0.06
0.07
20
40
60
80
100
120
OUTPUT POWER vs. LOAD RESISTANCE
AND CHARGE-PUMP CAPACITANCE
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
40
CCHARGE_PUMP
= 1µF
30
CCHARGE_PUMP
= 0.47µF
10
60
VPVDD = 4.2V
VDD = 1.8V
VRIPPLE = 200mVP-P on VDD
INPUTS AC-COUPLED TO GND
RLOAD = 32I
20
0
10
100
1k
LOAD RESISTANCE (I)
10k
10k
0
fIN = 1kHz
RLOAD = 32I
-20
-40
-60
-80
-100
-120
-140
0
1
1k
INBAND OUTPUT SPECTRUM
80
40
20
100
LOAD RESISTANCE (I)
MAX97003 toc33
100
10
1
AMPLITUDE (dBV)
50
120
PSRR (dB)
fIN = 1kHz
THD+N = 1%
CCHARGE_PUMP = CC1N-C1P
CCPVDD = CCPVSS
THD+N = 1%
30
140 160
OUTPUT POWER (mW)
CCHARGE_PUMP = 2.2µF
40
0
0
OUTPUT POWER (W)
60
THD+N = 10%
50
10
0
0.03
60
20
fIN = 1kHz
POUT = PHPL + PHPR
10
70
OUTPUT POWER (mW)
60
20
f = 100Hz
0.001
70
MAX97003 toc34
0.1
RLOAD = 16I
80
fIN = 1kHz
70
OUTPUT POWER (mW)
1
90
MAX97003 toc32
THD+N RATIO (%)
10
80
MAX97003 toc30
RHP = 16I
OUTPUT POWER vs. LOAD RESISTANCE
100
POWER DISSIPATION (mW)
MAX97003 toc29
100
MAX97003 toc31
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
-160
10
100
1k
FREQUENCY (Hz)
10k
100k
0
2k
4k 6k 8k 10k 12k 14k 16k 18k 20k
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 19
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Typical Operating Characteristics (continued)
(VDD = 1.8V, VPVDD = 4.2V, VGND = VPGND = 0V. Headphone path: PGAIN_ = -1.5dB, HP_VOL = 0dB, HPGAIN = +2dB, input signal
configured singled-ended. Speaker path: PGAIN_ = 0dB, SPKVOL = 0dB, SPKGAIN = +12dB, input signal configured differential.
Speaker loads (ZSPK) connected between SPKP and SPKN. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and
SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P‑C1N = CCPVDD = CCPVSS = CBIAS = 1FF.)
HEADPHONE AMPLIFIER
-20
CROSSTALK (dB)
-60
-80
-100
80
-40
-60
HPR TO HPL
-80
PGAIN = 0dB
PGAIN = -3dB
60
PGAIN = 6dB
50
40
PGAIN = 12dB
30
HPL TO HPR
-100
20
10
0
-120
-160
0
2k
4k 6k 8k 10k 12k 14k 16k 18k 20k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
HEADPHONE VOLUME GAIN
vs. HP_VOL CODE
SHUTDOWN RESPONSE
100k
MAX97003 toc38
-10
10
100
1k
10k
100k
FREQUENCY (Hz)
MAX97003 toc39
0
HEADPHONE VOLUME GAIN (dB)
RLOAD = 32I
90
70
-120
-140
100
MAX97003 toc36
RLOAD = 32I
CMRR (dB)
fIN = 1kHz
RLOAD = 16I
-40
AMPLITUDE (dBV)
0
MAX97003 toc35
0
-20
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
CROSSTALK vs. FREQUENCY
MAX97003 toc37
INBAND OUTPUT SPECTRUM
TURN-ON RESPONSE
MAX97003 toc40
SCL
2V/div
SCL
2V/div
VS2EN = 0
SLEW = 0
ZCD = 0
-20
-30
-40
HP_
500mV/div
-50
HP_
500mV/div
VS2EN = 0
SLEW = 0
ZCD = 0
-60
-70
0
10
20
30
40
50
60
70
4ms/div
4ms/div
HP_VOL CODE (NUMERIC)
���������������������������������������������������������������� Maxim Integrated Products 20
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX97003
1
2
3
4
5
A
C1N
C1P
CPVSS
HPR
HPL
B
GND
SCL
CPVDD
HPSNS
BIAS
C
PVDD
SDA
VDD
INB1
INB2
D
SPKP
SPKN
PGND
INA1
INA2
+
WLP
Bump Description
BUMP
NAME
FUNCTION
A1
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and C1N.
A2
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N.
A3
CPVSS
A4
HPR
Headphone Amplifier Right Output
A5
HPL
Headphone Amplifier Left Output
B1
GND
Analog Ground
B2
SCL
Serial Clock Input. Connect a pullup resistor from SCL to the I2C bus supply.
B3
CPVDD
Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to PGND.
B4
HPSNS
Headphone Ground Sense. Connect to the headset jack’s ground terminal.
Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to PGND.
B5
BIAS
Common-Mode Bias. Bypass to GND with a 1FF capacitor.
C1
PVDD
Speaker Amplifier Power Supply. Bypass with a 0.1FF and a 10FF capacitor to PGND.
C2
SDA
Serial-Data Input/Output. Connect a pullup resistor from SDA to the I2C bus supply.
C3
VDD
Headphone Amplifier Supply. Bypass with a 0.1FF and a 10FF capacitor to GND.
C4
INB1
Input B1. Left or negative input.
C5
INB2
Input B2. Right or positive input.
D1
SPKP
Positive Speaker Output
D2
SPKN
Negative Speaker Output
D3
PGND
Speaker Amplifier Ground and Charge-Pump Ground
D4
INA1
Input A1. Left or negative input.
D5
INA2
Input A2. Right or positive input.
���������������������������������������������������������������� Maxim Integrated Products 21
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Detailed Description
The MAX97003 audio subsystem combines a mono
speaker amplifier with a stereo headphone amplifier. The
high-efficiency 1W class D speaker amplifier operates
directly from a lithium-ion battery and consumes no more
than 0.05FA when in shutdown mode. The headphone
amplifier utilizes a dual-mode charge pump and a Class
H output stage to maximize efficiency while outputting a
ground-referenced signal that does not require output
coupling capacitors. The headphone and speaker amplifiers have independent volume and on/off control. The
four inputs are configurable as two differential inputs or
four single-ended inputs. All control is performed using
the two-wire I2C interface.
The speaker amplifier incorporates a distortion limiter to
automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals.
The speaker amplifier also features an adjustable DRC
that provides programmable compression or limiting
of the audio signal. Both the headphone and speaker
amplifiers feature a downward expander/noise gate to
attenuate noise when no input signal is present. The
headphone amplifier features a ground-sense pin to
eliminate ground loop noise when the headphone jack
is in use.
Signal Path
The signal path consists of flexible inputs, signal mixing,
volume control, and output amplifiers (Figure 1). The
inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature
programmable gain settings using internal resistors.
Following preamplification, the input signals are mixed,
volume adjusted, and routed to the headphone and
speaker amplifiers based on the desired configuration.
Class D Speaker Amplifier
The Class D speaker amplifier utilizes active emissionslimiting and spread-spectrum modulation to minimize the
EMI radiated by the amplifier.
HPL
INA2
INA1
INPUT A
-3dB TO +12dB
-63dB TO 0dB
0dB TO +6dB
MIXER
AND
MUX
INB2
INB1
HPR
-63dB TO 0dB
0dB TO +6dB
SPKP
INPUT B
-3dB TO +12dB
SPKN
-63dB TO 0dB
+12dB TO +24dB
Figure 1. Signal Path
���������������������������������������������������������������� Maxim Integrated Products 22
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
STEREO SINGLE-ENDED
IN_2 (R)
R
TO MIXER
IN_1 (L)
L
DIFFERENTIAL
IN_2 (+)
IN_1 (-)
TO MIXER
Figure 2. Stereo Single-Ended and Differential Input Configurations
EMISSION LEVEL (dBµV/m)
90
70
50
30
10
-10
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters or shielding to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim’s
patented active emissions limiting edge-rate control
circuitry and spread-spectrum modulation reduces EMI
emissions, while maintaining up to 93% efficiency.
Maxim’s spread-spectrum modulation mode flattens
wideband spectral components, while proprietary techniques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction or
efficiency. The IC’s spread-spectrum modulator randomly varies the switching frequency by Q10kHz around the
center frequency (300kHz). Above 10MHz, the wideband
spectrum looks like noise for EMI purposes. See Figure 3.
Figure 3. EMI with 12in of Speaker Cable
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Dynamic Range Compressor (DRC)
The speaker amplifier features a dynamic range compressor (DRC) that attenuates high-amplitude signals and
allows for a higher gain setting to be selected without
clipping the output signal. This increases the perceived
loudness of the audio signal and maintains a stable output
amplitude despite changes in input amplitude. Figure 4,
Figure 5, and Figure 6 demonstrate the benefits of using
the DRC. Each of these figures uses the same input signal.
Figure 4. Low-Signal to High-Signal Transition, No Clipping,
DRC Disabled
To operate the DRC, select a threshold level, compression ratio, attack time constant, and release time through
registers 0x0A and 0x0B. When enabled, RMS signal
levels that cross above the selected DRC threshold level
are attenuated based on the selected compression ratio
(Figure 7). Attenuation is achieved by automatically modifying the speaker volume to a lower gain setting. The
user-selected gain setting is automatically restored when
the RMS signal level falls below the DRC threshold. The
attack time constant determines the time constant used
when the DRC engages. The release time determines the
time-per-step used when the DRC disengages.
OUTPUT
(VRMS)
0.85
1:1 1.5:1
2:1
Figure 5. Low-Signal to High-Signal Transition, Increased Gain,
DRC Disabled
4:1
∞:1
THRESHOLD
0.199 TO 0.839
Figure 6. Low-Signal to High-Signal Transition, Increased Gain,
DRC Enabled
0.85
INPUT
(VRMS)
Figure 7. DRC Gain Curve
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
OUTPUT
(mVP)
1200
1:1
2:1
4:1
∞:1
INPUT
(mVP)
Expander
The IC’s speaker and headphone amplifier signal paths
include and expander. The expander reduces the noise
floor when there is no desired input signal by attenuating peak signals that are below the selected expander
threshold (Figure 8). Attenuation is achieved by automatically modifying the speaker or headphone volume to a
lower gain setting. Expansion ratio and attack time settings are configured by registers 0x0C for the headphone
path and 0x0D for the speaker path. The expansion ratio
determines the input:output relationship used when the
input signal is below the selected threshold. The expansion attack time determines the time-per-step used when
the expander engages. Figure 9 and Figure 10 show
the benefits of the expander by comparing the output
with the expander disabled against the output with the
expander enabled.
Figure 8. Expander Gain Curve
The expander acts as a noise gate when the expansion
ratio is set to an input:output relationship of infinity:1. In
this case, all signals below the selected threshold are
muted.
Figure 9. High-Signal to Low-Signal Transition, Expander
Disabled
Figure 10. High-Signal to Low-Signal Transition, Expander
Enabled
THRESHOLD
1 TO 32
1200
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Speaker Low-Power Mode
The IC’s speaker path expander includes a low-power
mode that increases power efficiency when there is no
desired input signal. Set the programmable threshold
in register 0x0F to determine when low-power mode is
activated. When low-power mode is enabled, the Class
D switching output is active only if the speaker volume
setting selected by the expander is above the selected
low-power mode threshold. For example, if the speaker
low-power mode threshold is set to -30dB and the input
SPKP
Distortion Limiter
The speaker amplifier integrates a limiter to provide
speaker protection and ensures high-quality audio. When
enabled, the limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the
gain if the distortion exceeds the predefined threshold.
Attenuation is achieved by automatically modifying the
speaker volume as appropriate. The limiter automatically
tracks the battery voltage to reduce the gain as the battery voltage drops.
Figure 12 shows the typical output vs. input curves with
and without the distortion limiter. The dotted line shows
the maximum gain for a given distortion limit without
the distortion limiter. The solid line shows how, with the
distortion limiter enabled, the gain can be increased
without exceeding the set distortion limit. When the
limiter is enabled, selecting a high gain level results in
peak signals being attenuated while low signals are left
unchanged. This increases the perceived loudness without the harshness of a clipped waveform.
SPKN
Figure 11. High-Signal to Low-Signal Transition, Speaker
Expander with Speaker Low-Power Mode
To operate the distortion limiter, select a distortion threshold and release time constant through the 0x0E register.
ZCD must be set to 0 in register 0x11 for the distortion
limiter to operate properly.
DISTORTION
(% THD+N)
DISTORTION
THRESHOLD
LEVEL
< 1 TO 24
signal is such that the speaker expander attenuates
the output volume setting to at least -30dB, the Class D
amplifier is turned off (Figure 11). Low-power mode is
only available when the speaker expander is enabled.
Headphone Amplifier
DirectDrive
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and
headphone amplifier.
LIMITER
ENABLED AND
GAIN INCREASED
LIMITER
DISABLED
INPUT
Figure 12. Limiter Gain Curve
Maxim’s patented DirectDriveM architecture uses a
charge pump to create an internal negative supply voltage. This allows the headphone outputs of the IC to be
biased at GND while operating from a single supply
(Figure 13). Without a DC component, there is no need
for the large DC-blocking capacitors. Instead of two large
(220FF, typ) capacitors, the IC's charge pump requires
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
���������������������������������������������������������������� Maxim Integrated Products 26
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
two small ceramic capacitors, conserving board space,
reducing cost, and improving the frequency response
of the headphone amplifier. See the Output Power vs.
Charge-Pump Capacitance and Load Resistance graph
in the Typical Operating Characteristics section for
details of the possible capacitor sizes. There is a low DC
voltage on the amplifier outputs due to amplifier offset.
However, the offset of the IC is typically Q0.15mV, which,
when combined with a 32I load, results in less than 5FA
of DC current flow to the headphones.
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the
audio signal. Previous attempts at eliminating the
VDD
VOUT
VDD/2
GND
CONVENTIONAL DRIVER-BIASING SCHEME
+VDD
VOUT
VDD/2
-VDD
DirectDrive BIASING SCHEME
Figure 13. Traditional Amplifier Output vs. MAX97003
DirectDrive Output
output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the
headphone amplifiers. This method raises a few issues:
• The sleeve is typically grounded to the chassis. Using
the midrail biasing approach, the sleeve must be
isolated from system ground, complicating product
design.
• During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the amplifier
must be able to withstand the full energy from an ESD
strike.
• When using the headphone jack as a line out to other
equipment, the bias voltage on the sleeve can conflict with the ground potential from other equipment,
resulting in possible damage to the amplifiers.
Charge Pump
The IC’s dual-mode charge pump generates both the
positive and negative power supply for the headphone
amplifier. To maximize efficiency, both the charge
pump’s switching frequency and output voltage change
based on signal level.
When the input signal level is less than 10% of VDD,
the switching frequency is reduced to a low rate. This
minimizes switching-losses in the charge pump. When
the input signal exceeds 10% of VDD, the switching frequency increases to support the load current.
For input signals below 25% of VDD, the charge pump
generates Q(VDD/2) to minimize the voltage drop across
the amplifier’s power stage and thus improves efficiency.
Input signals that exceed 25% of VDD cause the charge
pump to output QVDD. The higher output voltage allows
for full output power from the headphone amplifier.
To prevent audible glitches when transitioning from the
Q(VDD/2) output mode to the QVDD output mode, the
charge pump transitions very quickly. This quick change
draws significant current from VDD for the duration of the
transition. The bypass capacitor on VDD supplies the
required current and prevent droop on VDD.
The charge pump’s dynamic switching mode can be
turned off through the I2C interface. The charge pump
can then be forced to output either Q(VDD/2) or QVDD
regardless of input signal level.
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Class H Operation
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the IC, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V)
are available from the charge pump. Figure 14 shows the
operation of the output voltage dependent power supply.
Ground Sense
The headphone amplifier features output ground sensing
that is used to reduce ground loop noise when the headphone output jack is connected to a different ground than
the amplifier ground. An example of this is when the headphone jack is used as a lineout and connected to an external power amplifier. In addition, the ground sense reduces
noise that can be caused by voltage drops between the
amplifier ground and the headphone jack ground pin during normal headphone use. HPSNS must be connected to
the ground pin on the headphone jack.
Volume-Change Features
The IC includes several features that enhance performance during volume changes. Zero-crossing detection, volume slewing, and enhanced volume smoothing
are used to improve click-and-pop performance during
volume changes. Volume readback is used to report the
actual volume setting after the DRC, expander, or distortion limiter applies an automatic volume change.
Zero-Crossing Detection
The IC features zero-crossing detection to reduce clicks
and pops during volume changes. When zero-crossing
detection is enabled, all volume changes are delayed
until a zero-crossing has been detected. If no zero-crossing is detected within 100ms, then the zero-crossing
detector times out and volume changes are executed.
1.8V
0.9V
VTH
HPVDD
32ms
OUTPUT
VOLTAGE
VTH
-0.9V
HPVSS
-1.8V
32ms
Disabling zero-crossing detection allows volume changes to occur immediately.
Volume Slewing
The IC offers volume slewing for all volume changes
to further reduce clicks and pops. When enabled, the
IC ramps through intermediate volume settings when a
change to the volume is made. If zero-crossing detection
is disabled, slewing occurs at a rate of 0.2ms per step.
If zero-crossing detection is enabled, slew time depends
on the input signal. If the duration between zero-crossings is less than 0.2ms, the slew time is limited at 0.2ms
per volume change. If the duration between zero-crossings is longer than 0.2ms, volume changes occur at each
zero-crossing. Volume slewing also provides a soft-start
at power-on and soft-stop at power-off.
Enhanced Volume Smoothing
Enhanced volume smoothing can be used when the volume slewing feature is enabled. When enhanced volume
smoothing is enabled and a volume change occurs, the
IC waits for each step in the ramp to be applied before
executing the next step. When zero-crossing detection
is enabled, enhanced volume smoothing prevents large
steps in the output volume when no zero-crossings are
detected.
Volume Readback
The IC features three volume readback registers that
report the actual volume settings of the speaker, left
headphone, and right headphone volume registers. The
DRC, expander, and distortion limiter are capable of
automatically adjusting these volume registers according
to their respective settings.
I2C Slave Address
The IC’s audio subsystem uses a slave address of 0x9A
or 1001101 R/W. The address is defined as the 7 most
significant bits (MSBs) followed by the read/write bit. Set
the read/write bit to 1 to configure the audio subsystem to
read mode. Set the read/write bit to 0 to configure the IC
to write mode. The address is the first byte of information
sent to the IC after the START condition.
Registers Map
19 internal registers program the audio subsystem.
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Register 0xFF indicates the
device revision. Write zeros to all unused bits in the
register table when updating the register, unless otherwise noted.
Figure 14. Class H Operation
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Table 1. Register Map
REGISTER
B7
B6
0
0
0
B5
B4
B3
B2
B1
B0
ADDRESS
DEFAULT
R/W
HPLVOLRB
0x00
—
R
0
HPRVOLRB
0x01
—
R
0
0
SPKVOLRB
0x02
—
R
Input A Configuration
0
0
0
INADIFF
PGAINA
0x03
0x00
R/W
Input B Configuration
0
0
0
INBDIFF
PGAINB
0x04
0x00
R/W
HPRMIX
0x05
0x00
R/W
0
0
0
0
SPKMIX
0x06
0x00
R/W
HPLM
0
HPLVOL
0x07
0x00
R/W
HPRM
0
HPRVOL
0x08
0x00
R/W
STATUS
Left Headphone Volume
Readback
Right Headphone
Volume Readback
Speaker Volume
Readback
Headphone Mixer
HPLMIX
Speaker Mixer
Left Headphone Volume
Right Headphone
Volume
Speaker Volume
SPKM
Dynamic Range Control
Dynamic Range Control
0
SPKVOL
DRCEN
0
DRCATK
0
0x00
R/W
0x0A
0x00
R/W
0x0B
0x00
R/W
Headphone Expander
EXPHEN
EXPHATK
EXPHTH
0x0C
0x00
R/W
Speaker Expander
EXPSEN
EXPSATK
EXPSTH
0x0D
0x00
R/W
THDRLS
0x0E
0x00
R/W
0x0F
0x00
R/W
0x10
0x00
R/W
Distortion Limiter
0
0x09
DRCRLS
DRCTH
THDCLP
Speaker Low-Power
0
SLPEN
0
0
0
0
0
Advanced Configuration
VS2EN
SLEW
ZCD
0
FFM
0
CPSEL
FIXED
0x11
0x00
R/W
Power Management
SHDN
0
0
0
0
SPKEN
HPLEN
HPREN
0x12
0x00
R/W
0xFF
0x40
R
Mode
Output Gain
SLPTH
HPGAIN
SPKGAIN
REVISION ID
Rev ID
REV
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Volume Readback
The Volume Readback registers report the actual volume setting of each output volume control when the DRC, expander, or distortion limiter is active.
Table 2. Volume Readback Registers
REGISTER
BIT
NAME
DESCRIPTION
Output Volume
5
4
0x00/0x01/
0x02
3
2
1
0
HPLVOLRB/
HPRVOLRB/
SPKVOLRB
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
0x00
-63
0x10
-47
0x20
-31
0x30
-15
0x01
-62
0x11
-46
0x21
-30
0x31
-14
0x02
-61
0x12
-45
0x22
-29
0x32
-13
0x03
-60
0x13
-44
0x23
-28
0x33
-12
0x04
-59
0x14
-43
0x24
-27
0x34
-11
0x05
-58
0x15
-42
0x25
-26
0x35
-10
0x06
-57
0x16
-41
0x26
-25
0x36
-9
0x07
-56
0x17
-40
0x27
-24
0x37
-8
0x08
-55
0x18
-39
0x28
-23
0x38
-7
0x09
-54
0x19
-38
0x29
-22
0x39
-6
0x0A
-53
0x1A
-37
0x2A
-21
0x3A
-5
0x0B
-52
0x1B
-36
0x2B
-20
0x3B
-4
0x0C
-51
0x1C
-35
0x2C
-19
0x3C
-3
0x0D
-50
0x1D
-34
0x2D
-18
0x3D
-2
0x0E
-49
0x1E
-33
0x2E
-17
0x3E
-1
0x0F
-48
0x1F
-32
0x2F
-16
0x3F
0
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Input Configuration
The input configuration registers allow the selection of single-ended or differential modes as well as preamp gain settings for INA and INB.
Table 3. Input Configuration Registers
REGISTER
BIT
NAME
4
INADIFF/
INBDIFF
DESCRIPTION
Input A/B Differential Mode. Configures the input as either a mono differential signal
(IN_ = IN_2 - IN_1) or as a stereo signal (IN_1 = left, IN_2 = right).
0 = Stereo single-ended
1 = Differential
Input A/B Preamp Gain. Set the input gain to maximize output signal level for a given
input signal range to improve the SNR of the system.
3
0x03/0x04
VALUE
2
1
0
PGAINA/
PGAINB
LEVEL (dB)
VALUE
LEVEL (dB)
0x0
-3
0x6
+6
0x1
-1.5
0x7
+7.5
0x2
-0
0x8
+9
0x3
+1.5
0x9
+10.5
0x4
+3
0xA–0xF
+12
0x5
+4.5
—
—
���������������������������������������������������������������� Maxim Integrated Products 31
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Mixers
The IC features independent mixers for the left headphone, right headphone, and speaker paths. Each output can
select any combination of any inputs. This allows for mixing two audio signals together and routing independent signals
to the headphone and speaker amplifiers. If one of the inputs is not selected by either mixer, it is automatically powered
down to reduce current consumption.
Table 4. Mixer Registers
REGISTER
BIT
NAME
7
6
HPLMIX
5
4
0x05
HPRMIX
1
0
3
1
0
No input
INA1 (Disabled when INADIFF = 1)
INA2 (Select when INADIFF = 1)
INB1 (Disabled when INBDIFF = 1)
INB2 (Select when INBDIFF = 1)
0000
xxx1
xx1x
x1xx
1xxx
No input
INA1 (Disabled when INADIFF = 1)
INA2 (Select when INADIFF = 1)
INB1 (Disabled when INBDIFF = 1)
INB2 (Select when INBDIFF = 1)
Speaker Mixer. Selects which of the four inputs is routed to the speaker output.
2
0x06
0000
xxx1
xx1x
x1xx
1xxx
Right Headphone Mixer. Selects which of the four inputs is routed to the right
headphone output.
3
2
DESCRIPTION
Left Headphone Mixer. Selects which of the four inputs is routed to the left headphone
output.
SPKMIX
0000
xxx1
xx1x
x1xx
1xxx
No input
INA1 (Disabled when INADIFF = 1)
INA2 (Select when INADIFF = 1)
INB1 (Disabled when INBDIFF = 1)
INB2 (Select when INBDIFF = 1)
���������������������������������������������������������������� Maxim Integrated Products 32
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Volume Control
The speaker, left headphone, and right headphone have independent volume control registers that allow a gain to be
selected from -63dB to 0dB.
Table 5. Headphone Volume Control Registers
REGISTER
BIT
NAME
7
HPLM/
HPRM/
SPKM
DESCRIPTION
Output Mute
0 = Unmuted
1 = Muted
Output Volume
5
4
0x07/0x08/
0x09
3
2
1
0
HPLVOL/
HPRVOL/
SPKVOL
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
0x00
-63
0x10
-47
0x20
-31
0x30
-15
0x01
-62
0x11
-46
0x21
-30
0x31
-14
0x02
-61
0x12
-45
0x22
-29
0x32
-13
0x03
-60
0x13
-44
0x23
-28
0x33
-12
0x04
-59
0x14
-43
0x24
-27
0x34
-11
0x05
-58
0x15
-42
0x25
-26
0x35
-10
0x06
-57
0x16
-41
0x26
-25
0x36
-9
0x07
-56
0x17
-40
0x27
-24
0x37
-8
0x08
-55
0x18
-39
0x28
-23
0x38
-7
0x09
-54
0x19
-38
0x29
-22
0x39
-6
0x0A
-53
0x1A
-37
0x2A
-21
0x3A
-5
0x0B
-52
0x1B
-36
0x2B
-20
0x3B
-4
0x0C
-51
0x1C
-35
0x2C
-19
0x3C
-3
0x0D
-50
0x1D
-34
0x2D
-18
0x3D
-2
0x0E
-49
0x1E
-33
0x2E
-17
0x3E
-1
0x0F
-48
0x1F
-32
0x2F
-16
0x3F
0
���������������������������������������������������������������� Maxim Integrated Products 33
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Dynamic Range Control
The DRC attenuates high-level signals without affecting low-level signals. Attenuation is achieved by automatically
modifying the speaker volume as appropriate. When the DRC is enabled, the overall volume can be increased without
clipping the high-level signals. To operate the DRC, select a compression threshold, compression ratio, attack time
constant, and release time.
Table 6. Dynamic Range Control Registers
REGISTER
BIT
NAME
DRCEN
DRC Enable and Compression Ratio
000 = 1:1 (disabled)
001 = 1.34:1
010 = 2:1
011 = 4:1
100 – 111 = J:1
DRCATK
DRC Attack Time Constant. Defines the time constant used during attack.
00 = 500Fs
01 = 1ms
10 = 10ms
11 = 50ms
DRCRLS
0
DRC Release Time. Defines the release rate per step.
000 = 800ms
001 = 400ms
010 = 150ms
011 = 75ms
100 = 50ms
101–111 = 25ms
4
Compression Threshold Level. Specifies the minimum input signal level for which
compression is applied.
7
6
5
4
0x0A
3
2
1
3
0x0B
DESCRIPTION
2
1
0
DRCTH
VALUE
LEVEL (VRMS)
VALUE
LEVEL (VRMS)
0x00
Reserved
0x10
0.354
0x01
0.839
0x11
0.334
0x02
0.792
0x12
0.315
0x03
0.748
0x13
0.298
0x04
0.706
0x14
0.281
0x05
0.667
0x15
0.265
0x06
0.629
0x16
0.251
0x07
0.594
0x17
0.237
0x08
0.561
0x18
0.223
0x09
0.529
0x19
0.211
0x0A
0.500
0x1A–0x1F
0.199
0x0B
0.472
0x0C
0.445
0x0D
0.421
0x0E
0.397
0x0F
0.375
���������������������������������������������������������������� Maxim Integrated Products 34
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Expander (Noise Gate)
The expander/noise gate eliminates noise when no desired signal is present by attenuating peak signals that are below
the selected threshold. Attenuation is achieved by automatically modifying the headphone or speaker volume as appropriate. To operate the headphone or speaker expander, select an expansion threshold, expansion ratio, and attack time
in the appropriate headphone or speaker expander registers.
Table 7. Expander Registers
REGISTER
BIT
NAME
7
EXPHEN/
EXPSEN
6
0x0C/0x0D
EXPHATK/
EXPSATK
3
0
VALUE
ATTACK TIME (ms/step)
000
001
010
011
100
101
110–111
500
350
250
100
50
25
15
Headphone/Speaker Noise Gate Threshold. The expander attenuates or mutes the
output below this threshold. Thresholds are based on the PGA input signal level.
2
1
Headphone/Speaker Expansion Ratio
00 = 1:1 (disabled)
01 = 2:1
10 = 4:1
11 = J:1 (noise gate)
Headphone/Speaker Expander Attack Time. Decreases volume after the signal
drops below the selected expander threshold.
5
4
DESCRIPTION
EXPHTH/
EXPSTH
VALUE
THRESHOLD (mVP)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Reserved
32
20
10
8
4
2
1
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Distortion Limiter
The distortion limiter monitors the audio signal at the output of the Class D speaker amplifier and decreases the gain if
the distortion exceeds the selected threshold. Attenuation is achieved by automatically modifying the speaker volume
as appropriate. To operate the distortion limiter, select a distortion limit (% THD+N) and a release time constant.
Table 8. Distortion Limiter Register
REGISTER
BIT
NAME
Distortion Limit. Measured in % THD+N. ZCD must be set to 0 for the distortion
limiter to function.
7
6
THDCLP
5
0x0E
4
2
1
0
DESCRIPTION
THDRLS
VALUE
DISTORTION LIMIT (%)
VALUE
DISTORTION LIMIT (%)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Limiter disabled
<1
1
2
4
6
8
10
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
12
14
16
18
20
21
22
24
Limiter Release Time Constant. Time constant used while increasing the gain after
distortion is no longer detected at the output.
000 = 6.2s
001 = 3.1s
010 = 1.6s
011 = 815ms
100 = 419ms
101 = 223ms
110 = 116ms
111 = 76ms
���������������������������������������������������������������� Maxim Integrated Products 36
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Speaker Low-Power Mode
The speaker expander includes a low-power mode that increases power efficiency when a desired audio signal is not
present. When this feature is enabled, the Class D switching output is active only if the speaker volume setting selected
by the expander is above the selected low-power mode threshold. Low-power mode is only available when the speaker
expander is enabled.
Table 9. Speaker Low-Power Mode Register
REGISTER
BIT
7
NAME
SLPEN
4
3
0x0F
1
0
Speaker Low-Power Mode. Only functions if EXPSEN ≠ 0.
0 = Class D output is active continuously.
1 = Class D output is active if the speaker volume setting selected by the expander is
above SLPTH.
Speaker Low-Power Mode Volume Threshold. Threshold used to determine if speaker
amplifier should be enabled or disabled. If the volume selected by the expander is less
than this threshold, the speaker amplifier is disabled.
5
2
DESCRIPTION
SLPTH
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
VALUE
GAIN
(dB)
0x00
-63
0x10
-47
0x20
-31
0x30
-15
0x01
-62
0x11
-46
0x21
-30
0x31
-14
0x02
-61
0x12
-45
0x22
-29
0x32
-13
0x03
-60
0x13
-44
0x23
-28
0x33
-12
0x04
-59
0x14
-43
0x24
-27
0x34
-11
0x05
-58
0x15
-42
0x25
-26
0x35
-10
0x06
-57
0x16
-41
0x26
-25
0x36
-9
0x07
-56
0x17
-40
0x27
-24
0x37
-8
0x08
-55
0x18
-39
0x28
-23
0x38
-7
0x09
-54
0x19
-38
0x29
-22
0x39
-6
0x0A
-53
0x1A
-37
0x2A
-21
0x3A
-5
0x0B
-52
0x1B
-36
0x2B
-20
0x3B
-4
0x0C
-51
0x1C
-35
0x2C
-19
0x3C
-3
0x0D
-50
0x1D
-34
0x2D
-18
0x3D
-2
0x0E
-49
0x1E
-33
0x2E
-17
0x3E
-1
0x0F
-48
0x1F
-32
0x2F
-16
0x3F
0
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Output Gain
The output stage of the headphone and speaker amplifiers can be configured to provide additional gain. The headphone amplifier allows a range of 0dB to +6dB. The speaker amplifier allows range of +12dB to +24dB.
Table 10. Output Gain Register
REGISTER
BIT
NAME
DESCRIPTION
HPGAIN
Headphone Output Gain
00 = 0dB
01 = +2dB
10 = +4dB
11 = +6dB
SPKGAIN
Speaker Output Gain
00 = +12dB
01 = +16dB
10 = +20dB
11 = +24dB
3
2
0x10
1
0
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Advanced Configuration
The IC includes several advanced configurations related to automatic volume changes initiated by the DRC, expander,
and distortion limiter. In addition, settings for the Class D speaker modulation scheme and headphone charge pump
are configured in register 0x11.
Table 11. Advanced Configuration Register
REGISTER
BIT
7
6
0x11
NAME
DESCRIPTION
VS2EN
Enhanced Volume Smoothing. During volume slewing, the controller waits for each step
in the ramp to be applied before executing the next step. When zero-crossing detection
is enabled, this prevents large steps in the output volume when no zero-crossings are
detected.
0 = Disabled
1 = Enabled
SLEW
Volume Slewing. Determines whether volume slewing is used on all volume control
changes to reduce clicks and pops. When enabled, volume changes cause the IC to
ramp through intermediate volume settings whenever a change to the volume is made. If
ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew time depends on
the input signal frequency. This bit also activates soft-start at power-on and soft-stop at
power-off.
0 = Enabled
1 = Disabled
5
ZCD
Zero-Crossing Detection. Determines whether zero-crossing detection is used on all
volume control changes to reduce clicks and pops. Disabling zero-crossing detection
allows volume changes to occur immediately. Zero-crossing detection times out at
100ms.
0 = Enabled
1 = Disabled
3
FFM
Fixed Class D Frequency Enable
0 = Spread-spectrum modulation
1 = Fixed-frequency modulation
1
0
CPSEL
Charge-Pump Output Select. Works with FIXED to set QVDD or QVDD/2 outputs on
CPVDD and CPVSS. Ignored when FIXED = 0.
0 = QVDD on CPVDD/CPVSS
1 = QVDD/2 on CPVDD/CPVSS
FIXED
Class H Mode. When enabled, this bit forces the charge pump to generate static power
rails for CPVDD and CPVSS, instead of dynamically adjusting them based on output
signal level.
0 = Class H mode
1 = Fixed supply mode
���������������������������������������������������������������� Maxim Integrated Products 39
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Power Management
The power management register allows the speaker, left headphone, and right headphone signal paths to be enabled.
It also enables the IC device.
Table 12. Power Management Register
REGISTER
BIT
NAME
DESCRIPTION
7
SHDN
Software Shutdown
0 = Device disabled
1 = Device enabled
2
SPKEN
Speaker Amplifier Enable
0 = Disabled
1 = Enabled
1
HPLEN
Left Headphone Amplifier Enable
0 = Disabled
1 = Enabled
0
HPREN
Right Headphone Amplifier Enable
0 = Disabled
1 = Enabled
0x12
I2C Serial Interface
The IC features an I2C/SMBus-compatible, two-wire serial interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to
400kHz. Figure 1 shows the two-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC
by transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START (S) or REPEATED
START (Sr) condition, a not acknowledge, and a STOP
SDA
tSU,STA
tSU,DAT
tLOW
tBUF
tHD,STA
tHD,DAT
tSP
tSU,STO
tHIGH
SCL
tHD,STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 15. I2C Serial Interface Timing Diagram
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
(P) condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500I, is required on SDA. SCL operates only as an
input. A pullup resistor, typically greater than 500I, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the IC from
high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals. See the START and STOP Conditions
section.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 16). A START condition
from the master signals the beginning of a transmission
to the IC. The master terminates transmission, and frees
S
Sr
P
SCL
SDA
Figure 16. START, STOP, and REPEATED START Conditions
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 1001101. Setting
the read/write bit to 1 (slave address = 0x9B) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x9A) configures the IC for write mode. The
address is the first byte of information sent to the IC after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked ninth bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 17). The IC pulls down SDA during the entire master-generated ninth clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the ninth
clock cycle to acknowledge receipt of data when the IC
is in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue. A
not-acknowledge is sent when the master reads the final
byte of data from the IC, followed by a STOP condition.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
the bus, by issuing a STOP condition. The bus remains
active if a REPEATED START condition is generated
instead of a STOP condition.
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 17. Acknowledge
���������������������������������������������������������������� Maxim Integrated Products 41
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Write Data Format
A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one
byte of data to configure the internal register address
pointer, one or more bytes of data, and a STOP condition. Figure 18 illustrates the proper frame format for
writing one byte of data to the IC. Figure 19 illustrates
the frame format for writing n-bytes of data to the IC.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated ninth SCL pulse.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer tells
the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address
pointer data.
The third byte sent to the IC contains the data that are
written to the chosen register. An acknowledge pulse
from the IC signals receipt of the data byte. The address
pointer autoincrements to the next register address after
each received data byte. This autoincrement feature
allows a master to write to sequential registers within one
continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses
greater than 0x12 are reserved. Do not write to these
addresses.
ACKNOWLEDGE FROM SLAVE
B7
ACKNOWLEDGE FROM SLAVE
SLAVE ADDRESS
S
0
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM SLAVE
A
REGISTER ADDRESS
A
A
DATA BYTE
R/W
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 18. Writing 1 Byte of Data to the IC
ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
ACKNOWLEDGE FROM SLAVE
0
A
REGISTER ADDRESS
R/W
A
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE 1
A
1 BYTE
DATA BYTE n
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 19. Writing n-Bytes of Data to the IC
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
The address pointer can be preset to a specific register
before a read command is issued. The master presets the address pointer by first sending the IC’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting the
first byte.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its
slave address by pulling SDA low during the ninth SCL
clock pulse. A START command followed by a read command resets the address pointer to register 0x00.
The first byte transmitted from the IC is the contents of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continuous
frame. A STOP condition can be issued after any number
of read data bytes. If a STOP condition is issued followed
by another read operation, the first data byte to be read
are from register 0x00.
ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condition. Figure 20 illustrates the frame format for reading
one byte from the IC. Figure 21 illustrates the frame
format for reading multiple bytes from the IC.
ACKNOWLEDGE FROM SLAVE
A
0
REGISTER ADDRESS
R/W
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM SLAVE
Sr
A
SLAVE ADDRESS
REPEATED START
1
A
R/W
DATA BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 20. Reading One Byte of Data from the IC
ACKNOWLEDGE FROM SALVE
ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
R/W
ACKNOWLEDGE FROM SLAVE
A
REPEATED START
Sr
SLAVE ADDRESS
1
R/W
A
DATA BYTE
A
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 21. Reading n-Bytes of Data from the IC
���������������������������������������������������������������� Maxim Integrated Products 43
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Applications Information
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filters add cost, increase the solution size of the
amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large
differential output swings (2 x VPVDD peak-to-peak) and
causes large ripple currents. Any parasitic resistance in
the filter components results in a loss of power, lowering
the efficiency.
The IC does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear
to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less
costly, more efficient solution.
Because the frequency of the IC output is well beyond
the bandwidth of most speakers, voice coil movement
due to the square-wave frequency is very small. Although
this movement is small, a speaker not designed to handle
the additional power can be damaged. For optimum
results, use a speaker with a series inductance > 10FH.
Typical 8I speakers exhibit series inductances in the
20FH to 100FH range.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers.
The IC is designed specifically to reject RF signals. PCB
layout, however, has a large impact on the susceptibility
of the end product.
In RF applications, improvements to both layout and
component selection decreases the IC’s susceptibility to
RF noise and prevent RF signals from being demodulated
into audible noise. Trace lengths should be kept below
1/4 of the wavelength of the RF frequency of interest.
Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the IC. The
wavelength (l) in meters is given by: l = c/f where c = 3
x 108 m/s, and f = the RF frequency of interest.
Route audio signals on middle layers of the PCB to allow
ground planes above and below to shield them from RF
interference. Ideally, the top and bottom layers of the
PCB should primarily be ground planes to create effective shielding.
Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors as it
exhibits the frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies.
These capacitors when placed at the input pins can
effectively shunt the RF noise at the inputs of the IC. For
these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane.
Avoid using microvias to connect to the ground plane
whenever possible as these vias do not conduct well at
RF frequencies.
Startup/Shutdown Sequencing
To ensure proper device initialization and minimal clickand-pop, program the IC’s control registers in the correct
order. Table 13 lists the correct startup sequence for the
device. To shutdown the IC, simply set SHDN = 0.
Table 13. Startup Sequence
SEQUENCE
DESCRIPTION
REGISTERS
1
Ensure SHDN = 0
0x12
2
Configure inputs
0x03, 0x04
3
Configure mixers
0x05, 0x06
4
Configure volume
0x07, 0x08, 0x09
5
Configure output gain
0x10
6
Enable amplifiers
0x12
7
Configure expander and DRC
0x0A–0x0F
10
Set SHDN = 1
0x12
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Component Selection
Optional Ferrite Bead Filter
For applications in which speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 22). Use a ferrite bead with low DC resistance, high frequency (> 600MHz) impedance between
100I and 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
Input Capacitor
An input capacitor, CIN, in conjunction with the input
impedance of the IC line inputs forms a highpass filter
that removes the DC bias from an incoming analog
signal. The AC-coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level.
Assuming zero source impedance, the -3dB point of the
highpass filter is given by:
f-3dB =
1
2πRINCIN
RIN is defined in the Electrical Characteristics table
under the Input Resistance section. Choose CIN so that
f-3dB is well below the lowest frequency of interest. For
best audio quality, use capacitors whose dielectrics have
low-voltage coefficients, such as tantalum or aluminum
electrolytic. Capacitors with high-voltage coefficients,
such as ceramics, can result in increased distortion at
low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mI for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
SPKP
MAX97000
CLASS D
SPKN
Figure 22. Optional Class D Ferrite Bead Filter
Charge-Pump Flying Capacitor
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the charge
pump. A value that is too small degrades the device’s
ability to provide sufficient current drive, which leads to a
loss of output voltage. Increasing the value of the flying
capacitor reduces the charge-pump output resistance to
an extent. Above 1FF, the on-resistance of the internal
switches and the ESR of external charge-pump capacitors dominate.
Charge-Pump Holding Capacitor
The holding capacitor (bypassing CPVSS) value and ESR
directly affect the ripple at CPVSS. Increasing the capacitor’s value reduces output ripple. Likewise, decreasing
the ESR reduces both ripple and output resistance.
Lower capacitance values can be used in systems with
low maximum output power levels. See the Output Power
vs. Load Resistance graph in the Typical Operating
Characteristics section for more information.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use a large continuous ground plane on
a dedicated layer of the PCB to minimize loop areas.
Connect GND and PGND directly to the ground plane
using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk
between channels, and prevents digital noise from coupling into the analog signals.
Place the capacitor between C1P and C1N as close as
possible to the IC to minimize trace length from C1P
to C1N. Inductance and resistance added to C1P and
C1N reduce the output power of the headphone amplifier. Bypass CPVDD and CPVSS with capacitors located
close to the pins with a short trace length to PGND. Close
decoupling of CPVDD and CPVSS minimizes supply
ripple and maximizes output power from the headphone
amplifier.
Bypass PVDD to PGND with as little trace length as possible. Connect SPKP and SPKN to the speaker using
the shortest and widest traces possible. Reducing trace
length minimizes radiated EMI. Route SPKP/SPKN as a
differential pair on the PCB to minimize the loop area
and thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate
them as close as possible to the IC to ensure maximum
effectiveness. Minimize the trace length from any ground
tied passive components to PGND to further minimize
radiated EMI.
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
An evaluation kit (EV kit) is available to provide an example layout for the IC. The EV kit allows quick setup of the
IC and includes easy-to-use software allowing all internal
registers to be controlled.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and its Applications on Maxim’s
website. Figure 23 shows the dimensions of the WLP
balls used on the IC.
Ordering Information
0.24mm
PART
TEMP RANGE
PIN-PACKAGE
MAX97003EWP+
-40NC to +85NC
20 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
0.21mm
Figure 23. WLP Ball Dimensions
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MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
20 WLP
W201A2+1
21-0544
Refer to Application Note 1891
E
PIN 1
INDICATOR
COMMON DIMENSIONS
MARKING
1
A3
A
A1
AAAA
D
A2
0.05 S
0.64
0.05
A1
0.19
0.03
0.45 REF
A2
A
0.025 BASIC
A3
0.27
b
S
See Note 7
SIDE VIEW
TOP VIEW
A
E1
SE
0.03
D1
1.20 BASIC
E1
1.60 BASIC
e
0.40 BASIC
SD
0.20
BASIC
SE
0.00
BASIC
e
B
E
D
C
B
SD
PKG. CODE
D1
A
1
2
3
4
5
b
0.05 M
S
AB
MIN
D
MAX
MIN
MAX
DEPOPULATED
BUMPS
W201A2+1
2.33
2.36
1.92
1.95
NONE
W201B2+1
2.16
2.19
1.60
1.63
NONE
W201C2+1
2.01
2.04
1.61
1.64
NONE
W201D2+1
2.08
2.11
1.71
1.74
NONE
A
BOTTOM VIEW
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
-DRAWING NOT TO SCALE-
TITLE
APPROVAL
PACKAGE OUTLINE
20 BUMPS, WLP PKG. 0.4mm PITCH
DOCUMENT CONTROL NO.
21-0544
REV.
B
1
1
���������������������������������������������������������������� Maxim Integrated Products 47
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011
Maxim Integrated Products 48
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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