OMAP-L132 C6000 DSP+ARM Processor (Rev. C)

OMAP-L132
DSP+ARM Processor
Technical Reference Manual
Literature Number: SPRUH78A
December 2011
2
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Contents
......................................................................................................................................
Overview ..........................................................................................................................
1.1
Introduction .................................................................................................................
1.2
Block Diagram .............................................................................................................
1.3
DSP Subsystem ...........................................................................................................
1.4
ARM Subsystem ...........................................................................................................
1.5
DMA Subsystem ...........................................................................................................
ARM Subsystem ................................................................................................................
2.1
Introduction .................................................................................................................
2.2
Operating States/Modes ..................................................................................................
2.3
Processor Status Registers ..............................................................................................
2.4
Exceptions and Exception Vectors ......................................................................................
2.5
The 16-BIS/32-BIS Concept .............................................................................................
2.6
16-BIS/32-BIS Advantages ...............................................................................................
2.7
Co-Processor 15 (CP15) .................................................................................................
2.7.1 Addresses in an ARM926EJ-S System ........................................................................
2.7.2 Memory Management Unit (MMU) .............................................................................
2.7.3 Caches and Write Buffer ........................................................................................
DSP Subsystem ................................................................................................................
3.1
Introduction .................................................................................................................
3.2
TMS320C674x Megamodule .............................................................................................
3.2.1 Internal Memory Controllers .....................................................................................
3.2.2 Internal Peripherals ...............................................................................................
3.3
Memory Map ...............................................................................................................
3.3.1 DSP Internal Memory ............................................................................................
3.3.2 External Memory ..................................................................................................
3.4
Advanced Event Triggering (AET) ......................................................................................
System Interconnect ..........................................................................................................
4.1
Introduction .................................................................................................................
4.2
System Interconnect Block Diagram ....................................................................................
System Memory ................................................................................................................
5.1
Introduction .................................................................................................................
5.2
ARM Memories ............................................................................................................
5.3
DSP Memories .............................................................................................................
5.4
Shared RAM Memory .....................................................................................................
5.5
External Memories ........................................................................................................
5.6
Internal Peripherals ........................................................................................................
5.7
Peripherals .................................................................................................................
Memory Protection Unit (MPU) ............................................................................................
6.1
Introduction .................................................................................................................
6.1.1 Purpose of the MPU .............................................................................................
6.1.2 Features ...........................................................................................................
6.1.3 Block Diagram ....................................................................................................
6.1.4 MPU Default Configuration ......................................................................................
Preface
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6.2
6.3
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Device Clocking
7.1
7.2
7.3
8
............................................................................................................... 119
Overview ..................................................................................................................
Frequency Flexibility .....................................................................................................
Peripheral Clocking ......................................................................................................
7.3.1 USB Clocking ....................................................................................................
7.3.2 DDR2/mDDR Memory Controller Clocking ..................................................................
7.3.3 EMIFA Clocking .................................................................................................
7.3.4 EMAC Clocking ..................................................................................................
7.3.5 McASP Clocking ................................................................................................
7.3.6 I/O Domains .....................................................................................................
Phase-Locked Loop Controller (PLLC)
8.1
8.2
8.3
4
Architecture ................................................................................................................. 99
6.2.1 Privilege Levels ................................................................................................... 99
6.2.2 Memory Protection Ranges .................................................................................... 100
6.2.3 Permission Structures .......................................................................................... 100
6.2.4 Protection Check ................................................................................................ 101
6.2.5 DSP L1/L2 Cache Controller Accesses ...................................................................... 102
6.2.6 MPU Register Protection ....................................................................................... 102
6.2.7 Invalid Accesses and Exceptions ............................................................................. 102
6.2.8 Reset Considerations ........................................................................................... 102
6.2.9 Interrupt Support ................................................................................................ 103
6.2.10 Emulation Considerations ..................................................................................... 103
MPU Registers ........................................................................................................... 104
6.3.1 Revision Identification Register (REVID) .................................................................... 106
6.3.2 Configuration Register (CONFIG) ............................................................................ 106
6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................ 107
6.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ......................................................... 108
6.3.5 Interrupt Enable Set Register (IENSET) ..................................................................... 109
6.3.6 Interrupt Enable Clear Register (IENCLR) ................................................................... 109
6.3.7 Fixed Range Start Address Register (FXD_MPSAR) ...................................................... 110
6.3.8 Fixed Range End Address Register (FXD_MPEAR) ....................................................... 110
6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .............................. 111
6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR) .................................. 112
6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) ................................... 113
6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ............ 114
6.3.13 Fault Address Register (FLTADDRR) ....................................................................... 115
6.3.14 Fault Status Register (FLTSTAT) ............................................................................ 116
6.3.15 Fault Clear Register (FLTCLR) .............................................................................. 117
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Introduction ...............................................................................................................
PLL Controllers ...........................................................................................................
8.2.1 Device Clock Generation .......................................................................................
8.2.2 Steps for Programming the PLLs .............................................................................
PLLC Registers ...........................................................................................................
8.3.1 PLLC0 Revision Identification Register (REVID) ...........................................................
8.3.2 PLLC1 Revision Identification Register (REVID) ...........................................................
8.3.3 Reset Type Status Register (RSTYPE) ......................................................................
8.3.4 PLLC0 Reset Control Register (RSCTRL) ...................................................................
8.3.5 PLLC0 Control Register (PLLCTL) ...........................................................................
8.3.6 PLLC1 Control Register (PLLCTL) ...........................................................................
8.3.7 PLLC0 OBSCLK Select Register (OCSEL) ..................................................................
8.3.8 PLLC1 OBSCLK Select Register (OCSEL) ..................................................................
8.3.9 PLL Multiplier Control Register (PLLM) ......................................................................
8.3.10 PLLC0 Pre-Divider Control Register (PREDIV) ............................................................
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8.3.11
8.3.12
8.3.13
8.3.14
8.3.15
8.3.16
8.3.17
8.3.18
8.3.19
8.3.20
8.3.21
8.3.22
8.3.23
8.3.24
8.3.25
8.3.26
8.3.27
8.3.28
8.3.29
8.3.30
8.3.31
8.3.32
8.3.33
8.3.34
8.3.35
8.3.36
8.3.37
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PLLC0 Divider 1 Register (PLLDIV1) .......................................................................
PLLC1 Divider 1 Register (PLLDIV1) .......................................................................
PLLC0 Divider 2 Register (PLLDIV2) .......................................................................
PLLC1 Divider 2 Register (PLLDIV2) .......................................................................
PLLC0 Divider 3 Register (PLLDIV3) .......................................................................
PLLC1 Divider 3 Register (PLLDIV3) .......................................................................
PLLC0 Divider 4 Register (PLLDIV4) .......................................................................
PLLC0 Divider 5 Register (PLLDIV5) .......................................................................
PLLC0 Divider 6 Register (PLLDIV6) .......................................................................
PLLC0 Divider 7 Register (PLLDIV7) .......................................................................
PLLC0 Oscillator Divider 1 Register (OSCDIV) ............................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV) ............................................................
PLL Post-Divider Control Register (POSTDIV) ............................................................
PLL Controller Command Register (PLLCMD) ............................................................
PLL Controller Status Register (PLLSTAT) ................................................................
PLLC0 Clock Align Control Register (ALNCTL) ...........................................................
PLLC1 Clock Align Control Register (ALNCTL) ...........................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ............................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ............................................
PLLC0 Clock Enable Control Register (CKEN) ............................................................
PLLC1 Clock Enable Control Register (CKEN) ............................................................
PLLC0 Clock Status Register (CKSTAT) ...................................................................
PLLC1 Clock Status Register (CKSTAT) ...................................................................
PLLC0 SYSCLK Status Register (SYSTAT) ...............................................................
PLLC1 SYSCLK Status Register (SYSTAT) ...............................................................
Emulation Performance Counter 0 Register (EMUCNT0) ................................................
Emulation Performance Counter 1 Register (EMUCNT1) ................................................
Power and Sleep Controller (PSC)
9.1
9.2
9.3
9.4
9.5
9.6
..................................................................................... 163
Introduction ...............................................................................................................
Power Domain and Module Topology .................................................................................
9.2.1 Power Domain States ..........................................................................................
9.2.2 Module States ...................................................................................................
Executing State Transitions ............................................................................................
9.3.1 Power Domain State Transitions ..............................................................................
9.3.2 Module State Transitions .......................................................................................
IcePick Emulation Support in the PSC ................................................................................
PSC Interrupts ............................................................................................................
9.5.1 Interrupt Events .................................................................................................
9.5.2 Interrupt Registers ..............................................................................................
9.5.3 Interrupt Handling ...............................................................................................
PSC Registers ............................................................................................................
9.6.1 Revision Identification Register (REVID) ....................................................................
9.6.2 Interrupt Evaluation Register (INTEVAL) ....................................................................
9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ..................................
9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ..................................
9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ......................................
9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ......................................
9.6.7 Power Error Pending Register (PERRPR) ...................................................................
9.6.8 Power Error Clear Register (PERRCR) ......................................................................
9.6.9 Power Domain Transition Command Register (PTCMD) ..................................................
9.6.10 Power Domain Transition Status Register (PTSTAT) .....................................................
9.6.11 Power Domain 0 Status Register (PDSTAT0) .............................................................
9.6.12 Power Domain 1 Status Register (PDSTAT1) .............................................................
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9.6.13
9.6.14
9.6.15
9.6.16
9.6.17
9.6.18
9.6.19
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Power Domain 0 Control Register (PDCTL0) ..............................................................
Power Domain 1 Control Register (PDCTL1) ..............................................................
Power Domain 0 Configuration Register (PDCFG0) ......................................................
Power Domain 1 Configuration Register (PDCFG1) ......................................................
Module Status n Register (MDSTATn) ......................................................................
PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................
PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................
Power Management
.......................................................................................................... 189
Introduction ...............................................................................................................
Power Consumption Overview .........................................................................................
PSC and PLLC Overview ...............................................................................................
Features ...................................................................................................................
Clock Management ......................................................................................................
10.5.1 Module Clock ON/OFF ........................................................................................
10.5.2 Module Clock Frequency Scaling ............................................................................
10.5.3 PLL Bypass and Power Down ...............................................................................
10.6 ARM Sleep Mode Management ........................................................................................
10.6.1 ARM Wait-For-Interrupt Sleep Mode ........................................................................
10.6.2 ARM Clock OFF ................................................................................................
10.6.3 ARM Subsystem Clock ON ...................................................................................
10.7 DSP Sleep Mode Management ........................................................................................
10.7.1 DSP Sleep Modes .............................................................................................
10.7.2 C674x DSP CPU Sleep Mode ...............................................................................
10.7.3 C674x Megamodule Sleep Mode ............................................................................
10.7.4 C674x Megamodule Clock ON/OFF .........................................................................
10.8 RTC-Only Mode ..........................................................................................................
10.9 Dynamic Voltage and Frequency Scaling (DVFS) ...................................................................
10.9.1 Frequency Scaling Considerations ..........................................................................
10.9.2 Voltage Scaling Considerations ..............................................................................
10.10 Deep Sleep Mode .......................................................................................................
10.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ...........................
10.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up .................................
10.10.3 Deep Sleep Sequence .......................................................................................
10.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking .....................................
10.11 Additional Peripheral Power Management Considerations ........................................................
10.11.1 USB PHY Power Down Control ............................................................................
10.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode ..............................
10.11.3 LVCMOS I/O Buffer Receiver Disable .....................................................................
10.11.4 Pull-Up/Pull-Down Disable ..................................................................................
10.1
10.2
10.3
10.4
10.5
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System Configuration (SYSCFG) Module
11.1
11.2
11.3
11.4
11.5
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Introduction ...............................................................................................................
Privilege Mode Protection ...............................................................................................
Master Priority Control ...................................................................................................
ARM-DSP Communication Interrupts .................................................................................
SYSCFG Registers ......................................................................................................
11.5.1 Revision Identification Register (REVID) ...................................................................
11.5.2 Device Identification Register 0 (DEVIDR0) ................................................................
11.5.3 Boot Configuration Register (BOOTCFG) ..................................................................
11.5.4 Kick Registers (KICK0R-KICK1R) ...........................................................................
11.5.5 Host 0 Configuration Register (HOST0CFG) ...............................................................
11.5.6 Host 1 Configuration Register (HOST1CFG) ...............................................................
11.5.7 Interrupt Registers .............................................................................................
11.5.8 Fault Registers .................................................................................................
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11.5.9
11.5.10
11.5.11
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
11.5.17
11.5.18
11.5.19
11.5.20
11.5.21
11.5.22
11.5.23
11.5.24
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Master Priority Registers (MSTPRI0-MSTPRI2) ...........................................................
Pin Multiplexing Control Registers (PINMUX0-PINMUX19) ............................................
Suspend Source Register (SUSPSRC) ...................................................................
Chip Signal Register (CHIPSIG) ...........................................................................
Chip Signal Clear Register (CHIPSIG_CLR) .............................................................
Chip Configuration 0 Register (CFGCHIP0) ..............................................................
Chip Configuration 1 Register (CFGCHIP1) ..............................................................
Chip Configuration 2 Register (CFGCHIP2) ..............................................................
Chip Configuration 3 Register (CFGCHIP3) ..............................................................
Chip Configuration 4 Register (CFGCHIP4) ..............................................................
VTP I/O Control Register (VTPIO_CTL) ...................................................................
DDR Slew Register (DDR_SLEW) .........................................................................
Deep Sleep Register (DEEPSLEEP) ......................................................................
Pullup/Pulldown Enable Register (PUPD_ENA) .........................................................
Pullup/Pulldown Select Register (PUPD_SEL) ...........................................................
RXACTIVE Control Register (RXACTIVE) ................................................................
ARM Interrupt Controller (AINTC)
12.1
12.2
12.3
12.4
....................................................................................... 285
Introduction ...............................................................................................................
Interrupt Mapping ........................................................................................................
AINTC Methodology .....................................................................................................
12.3.1 Interrupt Processing ...........................................................................................
12.3.2 Interrupt Enabling ..............................................................................................
12.3.3 Interrupt Status Checking .....................................................................................
12.3.4 Interrupt Channel Mapping ...................................................................................
12.3.5 Host Interrupt Mapping Interrupts ............................................................................
12.3.6 Interrupt Prioritization ..........................................................................................
12.3.7 Interrupt Nesting ...............................................................................................
12.3.8 Interrupt Vectorization .........................................................................................
12.3.9 Interrupt Status Clearing ......................................................................................
12.3.10 Interrupt Disabling ............................................................................................
AINTC Registers .........................................................................................................
12.4.1 Revision Identification Register (REVID) ...................................................................
12.4.2 Control Register (CR) .........................................................................................
12.4.3 Global Enable Register (GER) ...............................................................................
12.4.4 Global Nesting Level Register (GNLR) .....................................................................
12.4.5 System Interrupt Status Indexed Set Register (SISR) ....................................................
12.4.6 System Interrupt Status Indexed Clear Register (SICR) ..................................................
12.4.7 System Interrupt Enable Indexed Set Register (EISR) ...................................................
12.4.8 System Interrupt Enable Indexed Clear Register (EICR) .................................................
12.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) ....................................................
12.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) ................................................
12.4.11 Vector Base Register (VBR) ................................................................................
12.4.12 Vector Size Register (VSR) .................................................................................
12.4.13 Vector Null Register (VNR) .................................................................................
12.4.14 Global Prioritized Index Register (GPIR) ..................................................................
12.4.15 Global Prioritized Vector Register (GPVR) ................................................................
12.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) ..................................................
12.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) ..................................................
12.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3) ..................................................
12.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4) ..................................................
12.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1) ...........................................
12.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2) ...........................................
12.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3) ...........................................
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12.4.23
12.4.24
12.4.25
12.4.26
12.4.27
12.4.28
12.4.29
12.4.30
12.4.31
12.4.32
12.4.33
12.4.34
12.4.35
12.4.36
12.4.37
12.4.38
12.4.39
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Boot Considerations
13.1
13.2
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System Interrupt Status Enabled/Clear Register 4 (SECR4) ...........................................
System Interrupt Enable Set Register 1 (ESR1) .........................................................
System Interrupt Enable Set Register 2 (ESR2) .........................................................
System Interrupt Enable Set Register 3 (ESR3) .........................................................
System Interrupt Enable Set Register 4 (ESR4) .........................................................
System Interrupt Enable Clear Register 1 (ECR1) .......................................................
System Interrupt Enable Clear Register 2 (ECR2) .......................................................
System Interrupt Enable Clear Register 3 (ECR3) .......................................................
System Interrupt Enable Clear Register 4 (ECR4) .......................................................
Channel Map Registers (CMR0-CMR25) .................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) .....................................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) .....................................................
Host Interrupt Nesting Level Register 1 (HINLR1) .......................................................
Host Interrupt Nesting Level Register 2 (HINLR2) .......................................................
Host Interrupt Enable Register (HIER) ....................................................................
Host Interrupt Prioritized Vector Register 1 (HIPVR1) ...................................................
Host Interrupt Prioritized Vector Register 2 (HIPVR2) ...................................................
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Introduction ............................................................................................................... 316
DSP Wake Up ............................................................................................................ 317
............................................................. 319
DDR2/mDDR Memory Controller ........................................................................................ 321
15.1 Introduction ............................................................................................................... 322
15.1.1 Purpose of the Peripheral ..................................................................................... 322
15.1.2 Features ......................................................................................................... 322
15.1.3 Functional Block Diagram ..................................................................................... 323
15.1.4 Supported Use Case Statement ............................................................................. 323
15.1.5 Industry Standard(s) Compliance Statement ............................................................... 323
15.2 Architecture ............................................................................................................... 324
15.2.1 Clock Control ................................................................................................... 324
15.2.2 Signal Descriptions ............................................................................................ 325
15.2.3 Protocol Description(s) ........................................................................................ 326
15.2.4 Memory Width and Byte Alignment .......................................................................... 334
15.2.5 Address Mapping .............................................................................................. 335
15.2.6 DDR2/mDDR Memory Controller Interface ................................................................. 340
15.2.7 Refresh Scheduling ............................................................................................ 343
15.2.8 Self-Refresh Mode ............................................................................................. 343
15.2.9 Partial Array Self Refresh for Mobile DDR ................................................................. 344
15.2.10 Power-Down Mode ........................................................................................... 344
15.2.11 Reset Considerations ........................................................................................ 345
15.2.12 VTP IO Buffer Calibration ................................................................................... 346
15.2.13 Auto-Initialization Sequence ................................................................................ 346
15.2.14 Interrupt Support .............................................................................................. 349
15.2.15 DMA Event Support .......................................................................................... 349
15.2.16 Power Management .......................................................................................... 350
15.2.17 Emulation Considerations ................................................................................... 351
15.3 Supported Use Cases ................................................................................................... 352
15.3.1 Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory ........................... 352
15.3.2 Configuring Memory-Mapped Registers to Meet DDR2 Specification .................................. 353
15.4 Registers .................................................................................................................. 357
15.4.1 Revision ID Register (REVID) ................................................................................ 357
15.4.2 SDRAM Status Register (SDRSTAT) ....................................................................... 358
15.4.3 SDRAM Configuration Register (SDCR) .................................................................... 359
Programmable Real-Time Unit Subsystem (PRUSS)
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15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.4.9
15.4.10
15.4.11
15.4.12
15.4.13
15.4.14
15.4.15
15.4.16
15.4.17
15.4.18
15.4.19
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Enhanced Capture (eCAP) Module
16.1
16.2
16.3
16.4
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SDRAM Refresh Control Register (SDRCR) ...............................................................
SDRAM Timing Register 1 (SDTIMR1) .....................................................................
SDRAM Timing Register 2 (SDTIMR2) .....................................................................
SDRAM Configuration Register 2 (SDCR2) ................................................................
Peripheral Bus Burst Priority Register (PBBPR) ...........................................................
Performance Counter 1 Register (PC1) .....................................................................
Performance Counter 2 Register (PC2) ...................................................................
Performance Counter Configuration Register (PCC) ....................................................
Performance Counter Master Region Select Register (PCMRS) ......................................
Performance Counter Time Register (PCT) ..............................................................
DDR PHY Reset Control Register (DRPYRCR) ..........................................................
Interrupt Raw Register (IRR) ................................................................................
Interrupt Masked Register (IMR) ...........................................................................
Interrupt Mask Set Register (IMSR) ........................................................................
Interrupt Mask Clear Register (IMCR) .....................................................................
DDR PHY Control Register (DRPYC1R) ..................................................................
..................................................................................... 377
Introduction ...............................................................................................................
16.1.1 Purpose of the Peripheral .....................................................................................
16.1.2 Features .........................................................................................................
Architecture ...............................................................................................................
16.2.1 Capture and APWM Operating Mode .......................................................................
16.2.2 Capture Mode Description ....................................................................................
Applications ...............................................................................................................
16.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example .........................................
16.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ...........................
16.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example .......................................
16.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example .........................
16.3.5 Application of the APWM Mode .............................................................................
Registers ..................................................................................................................
16.4.1 Time-Stamp Counter Register (TSCTR) ....................................................................
16.4.2 Counter Phase Control Register (CTRPHS) ...............................................................
16.4.3 Capture 1 Register (CAP1) ...................................................................................
16.4.4 Capture 2 Register (CAP2) ...................................................................................
16.4.5 Capture 3 Register (CAP3) ...................................................................................
16.4.6 Capture 4 Register (CAP4) ...................................................................................
16.4.7 ECAP Control Register 1 (ECCTL1) ........................................................................
16.4.8 ECAP Control Register 2 (ECCTL2) ........................................................................
16.4.9 ECAP Interrupt Enable Register (ECEINT) .................................................................
16.4.10 ECAP Interrupt Flag Register (ECFLG) ...................................................................
16.4.11 ECAP Interrupt Clear Register (ECCLR) ..................................................................
16.4.12 ECAP Interrupt Forcing Register (ECFRC) ...............................................................
16.4.13 Revision ID Register (REVID) ..............................................................................
Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
17.1
17.2
378
378
378
379
380
381
388
389
391
393
395
397
404
404
405
405
406
406
407
407
409
410
412
413
414
415
.............................................. 417
Introduction ...............................................................................................................
17.1.1 Introduction .....................................................................................................
17.1.2 Submodule Overview ..........................................................................................
17.1.3 Register Mapping ..............................................................................................
Architecture ...............................................................................................................
17.2.1 Overview ........................................................................................................
17.2.2 Proper Interrupt Initialization Procedure ....................................................................
17.2.3 Time-Base (TB) Submodule ..................................................................................
17.2.4 Counter-Compare (CC) Submodule .........................................................................
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17.3
17.4
18
Enhanced Direct Memory Access (EDMA3) Controller
18.1
18.2
18.3
10
17.2.5 Action-Qualifier (AQ) Submodule ............................................................................
17.2.6 Dead-Band Generator (DB) Submodule ....................................................................
17.2.7 PWM-Chopper (PC) Submodule .............................................................................
17.2.8 Trip-Zone (TZ) Submodule ...................................................................................
17.2.9 Event-Trigger (ET) Submodule ...............................................................................
17.2.10 High-Resolution PWM (HRPWM) Submodule ............................................................
Applications to Power Topologies .....................................................................................
17.3.1 Overview of Multiple Modules ................................................................................
17.3.2 Key Configuration Capabilities ...............................................................................
17.3.3 Controlling Multiple Buck Converters With Independent Frequencies ..................................
17.3.4 Controlling Multiple Buck Converters With Same Frequencies ..........................................
17.3.5 Controlling Multiple Half H-Bridge (HHB) Converters .....................................................
17.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................
17.3.7 Practical Applications Using Phase Control Between PWM Modules ..................................
17.3.8 Controlling a 3-Phase Interleaved DC/DC Converter .....................................................
17.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter .....................................
Registers ..................................................................................................................
17.4.1 Time-Base Submodule Registers ............................................................................
17.4.2 Counter-Compare Submodule Registers ...................................................................
17.4.3 Action-Qualifier Submodule Registers ......................................................................
17.4.4 Dead-Band Generator Submodule Registers ..............................................................
17.4.5 PWM-Chopper Submodule Register ........................................................................
17.4.6 Trip-Zone Submodule Registers .............................................................................
17.4.7 Event-Trigger Submodule Registers ........................................................................
17.4.8 High-Resolution PWM Submodule Registers ..............................................................
441
459
463
467
471
475
482
482
483
484
487
490
493
497
498
503
506
506
510
513
517
520
521
525
528
.......................................................... 531
Introduction ...............................................................................................................
18.1.1 Overview ........................................................................................................
18.1.2 Features .........................................................................................................
18.1.3 Functional Block Diagram .....................................................................................
18.1.4 Terminology Used in This Document ........................................................................
Architecture ...............................................................................................................
18.2.1 Functional Overview ...........................................................................................
18.2.2 Types of EDMA3 Transfers ...................................................................................
18.2.3 Parameter RAM (PaRAM) ....................................................................................
18.2.4 Initiating a DMA Transfer .....................................................................................
18.2.5 Completion of a DMA Transfer ...............................................................................
18.2.6 Event, Channel, and PaRAM Mapping ......................................................................
18.2.7 EDMA3 Channel Controller Regions ........................................................................
18.2.8 Chaining EDMA3 Channels ..................................................................................
18.2.9 EDMA3 Interrupts ..............................................................................................
18.2.10 Event Queue(s) ...............................................................................................
18.2.11 EDMA3 Transfer Controller (EDMA3TC) ..................................................................
18.2.12 Event Dataflow ................................................................................................
18.2.13 EDMA3 Prioritization .........................................................................................
18.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................
18.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................
18.2.16 Reset Considerations ........................................................................................
18.2.17 Power Management ..........................................................................................
18.2.18 Emulation Considerations ...................................................................................
Transfer Examples .......................................................................................................
18.3.1 Block Move Example ..........................................................................................
18.3.2 Subframe Extraction Example ................................................................................
Contents
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18.4
18.5
18.6
19
EMAC/MDIO Module
19.1
19.2
19.3
20
18.3.3 Data Sorting Example .........................................................................................
18.3.4 Peripheral Servicing Example ................................................................................
Registers ..................................................................................................................
18.4.1 Parameter RAM (PaRAM) Entries ...........................................................................
18.4.2 EDMA3 Channel Controller (EDMA3CC) Registers .......................................................
18.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers .......................................................
Tips ........................................................................................................................
18.5.1 Debug Checklist ................................................................................................
18.5.2 Miscellaneous Programming/Debug Tips ...................................................................
Setting Up a Transfer ....................................................................................................
......................................................................................................... 667
Introduction ...............................................................................................................
19.1.1 Purpose of the Peripheral .....................................................................................
19.1.2 Features .........................................................................................................
19.1.3 Functional Block Diagram .....................................................................................
19.1.4 Industry Standard(s) Compliance Statement ...............................................................
19.1.5 Terminology .....................................................................................................
Architecture ...............................................................................................................
19.2.1 Clock Control ...................................................................................................
19.2.2 Memory Map ....................................................................................................
19.2.3 Signal Descriptions ............................................................................................
19.2.4 Ethernet Protocol Overview ..................................................................................
19.2.5 Programming Interface ........................................................................................
19.2.6 EMAC Control Module ........................................................................................
19.2.7 MDIO Module ...................................................................................................
19.2.8 EMAC Module ..................................................................................................
19.2.9 MAC Interface ..................................................................................................
19.2.10 Packet Receive Operation ..................................................................................
19.2.11 Packet Transmit Operation ..................................................................................
19.2.12 Receive and Transmit Latency .............................................................................
19.2.13 Transfer Node Priority .......................................................................................
19.2.14 Reset Considerations ........................................................................................
19.2.15 Initialization ....................................................................................................
19.2.16 Interrupt Support ..............................................................................................
19.2.17 Power Management ..........................................................................................
19.2.18 Emulation Considerations ...................................................................................
Registers ..................................................................................................................
19.3.1 EMAC Control Module Registers ............................................................................
19.3.2 MDIO Registers ................................................................................................
19.3.3 EMAC Module Registers ......................................................................................
External Memory Interface A (EMIFA)
20.1
20.2
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668
668
669
670
670
671
671
672
672
675
676
687
688
693
695
699
704
705
705
706
707
709
713
713
714
714
728
741
................................................................................. 791
Introduction ...............................................................................................................
20.1.1 Purpose of the Peripheral .....................................................................................
20.1.2 Features .........................................................................................................
20.1.3 Functional Block Diagram .....................................................................................
Architecture ...............................................................................................................
20.2.1 Clock Control ...................................................................................................
20.2.2 EMIFA Requests ...............................................................................................
20.2.3 Pin Descriptions ................................................................................................
20.2.4 SDRAM Controller and Interface .............................................................................
20.2.5 Asynchronous Controller and Interface .....................................................................
20.2.6 Data Bus Parking ..............................................................................................
20.2.7 Reset and Initialization Considerations .....................................................................
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20.3
20.4
21
General-Purpose Input/Output (GPIO)
21.1
21.2
12
20.2.8 Interrupt Support ...............................................................................................
20.2.9 EDMA Event Support ..........................................................................................
20.2.10 Pin Multiplexing ...............................................................................................
20.2.11 Memory Map ..................................................................................................
20.2.12 Priority and Arbitration .......................................................................................
20.2.13 System Considerations ......................................................................................
20.2.14 Power Management ..........................................................................................
20.2.15 Emulation Considerations ...................................................................................
Example Configuration ..................................................................................................
20.3.1 Hardware Interface ............................................................................................
20.3.2 Software Configuration ........................................................................................
Registers ..................................................................................................................
20.4.1 Module ID Register (MIDR) ...................................................................................
20.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) ..............................................
20.4.3 SDRAM Configuration Register (SDCR) ....................................................................
20.4.4 SDRAM Refresh Control Register (SDRCR) ...............................................................
20.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) ..........................................
20.4.6 SDRAM Timing Register (SDTIMR) .........................................................................
20.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................
20.4.8 EMIFA Interrupt Raw Register (INTRAW) ..................................................................
20.4.9 EMIFA Interrupt Masked Register (INTMSK) ..............................................................
20.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET) ......................................................
20.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ...................................................
20.4.12 NAND Flash Control Register (NANDFCR) ...............................................................
20.4.13 NAND Flash Status Register (NANDFSR) ................................................................
20.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) .........................................
20.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ......................................
20.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ..................................................
20.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ..................................................
20.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ..................................................
20.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ..................................................
20.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) ................................
20.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) ................................
20.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ....................................
20.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ....................................
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Introduction ...............................................................................................................
21.1.1 Purpose of the Peripheral .....................................................................................
21.1.2 Features .........................................................................................................
21.1.3 Functional Block Diagram .....................................................................................
21.1.4 Industry Standard(s) Compliance Statement ...............................................................
Architecture ...............................................................................................................
21.2.1 Clock Control ...................................................................................................
21.2.2 Signal Descriptions ............................................................................................
21.2.3 Pin Multiplexing ................................................................................................
21.2.4 Endianness Considerations ..................................................................................
21.2.5 GPIO Register Structure ......................................................................................
21.2.6 Using a GPIO Signal as an Output ..........................................................................
21.2.7 Using a GPIO Signal as an Input ............................................................................
21.2.8 Reset Considerations ..........................................................................................
21.2.9 Initialization .....................................................................................................
21.2.10 Interrupt Support ..............................................................................................
21.2.11 EDMA Event Support ........................................................................................
Contents
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21.3
22
21.2.12 Power Management ..........................................................................................
21.2.13 Emulation Considerations ...................................................................................
Registers ..................................................................................................................
21.3.1 Revision ID Register (REVID) ................................................................................
21.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) .....................................................
21.3.3 GPIO Direction Registers (DIRn) ............................................................................
21.3.4 GPIO Output Data Registers (OUT_DATAn) ...............................................................
21.3.5 GPIO Set Data Registers (SET_DATAn) ...................................................................
21.3.6 GPIO Clear Data Registers (CLR_DATAn) ................................................................
21.3.7 GPIO Input Data Registers (IN_DATAn) ....................................................................
21.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) ..........................................
21.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) .......................................
21.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................
21.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) .....................................
21.3.12 GPIO Interrupt Status Registers (INTSTATn) ............................................................
Inter-Integrated Circuit (I2C) Module
22.1
22.2
22.3
................................................................................... 911
Introduction ...............................................................................................................
22.1.1 Purpose of the Peripheral .....................................................................................
22.1.2 Features .........................................................................................................
22.1.3 Functional Block Diagram .....................................................................................
22.1.4 Industry Standard(s) Compliance Statement ...............................................................
Architecture ...............................................................................................................
22.2.1 Bus Structure ...................................................................................................
22.2.2 Clock Generation ..............................................................................................
22.2.3 Clock Synchronization .........................................................................................
22.2.4 Signal Descriptions ............................................................................................
22.2.5 START and STOP Conditions ................................................................................
22.2.6 Serial Data Formats ...........................................................................................
22.2.7 Operating Modes ...............................................................................................
22.2.8 NACK Bit Generation ..........................................................................................
22.2.9 Arbitration .......................................................................................................
22.2.10 Reset Considerations ........................................................................................
22.2.11 Initialization ....................................................................................................
22.2.12 Interrupt Support ..............................................................................................
22.2.13 DMA Events Generated by the I2C Peripheral ...........................................................
22.2.14 Power Management ..........................................................................................
22.2.15 Emulation Considerations ...................................................................................
Registers ..................................................................................................................
22.3.1 I2C Own Address Register (ICOAR) ........................................................................
22.3.2 I2C Interrupt Mask Register (ICIMR) ........................................................................
22.3.3 I2C Interrupt Status Register (ICSTR) ......................................................................
22.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) ......................................................
22.3.5 I2C Data Count Register (ICCNT) ...........................................................................
22.3.6 I2C Data Receive Register (ICDRR) ........................................................................
22.3.7 I2C Slave Address Register (ICSAR) .......................................................................
22.3.8 I2C Data Transmit Register (ICDXR) ........................................................................
22.3.9 I2C Mode Register (ICMDR) .................................................................................
22.3.10 I2C Interrupt Vector Register (ICIVR) ......................................................................
22.3.11 I2C Extended Mode Register (ICEMDR) ..................................................................
22.3.12 I2C Prescaler Register (ICPSC) ............................................................................
22.3.13 I2C Revision Identification Register (REVID1) ...........................................................
22.3.14 I2C Revision Identification Register (REVID2) ...........................................................
22.3.15 I2C DMA Control Register (ICDMAC) .....................................................................
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22.3.16
22.3.17
22.3.18
22.3.19
22.3.20
22.3.21
23
Function Register (ICPFUNC) ....................................................................
Direction Register (ICPDIR) .......................................................................
Data In Register (ICPDIN) .........................................................................
Data Out Register (ICPDOUT) ....................................................................
Data Set Register (ICPDSET) ....................................................................
Data Clear Register (ICPDCLR) ..................................................................
Multichannel Audio Serial Port (McASP)
23.1
23.2
23.3
14
I2C Pin
I2C Pin
I2C Pin
I2C Pin
I2C Pin
I2C Pin
946
947
948
949
950
951
............................................................................. 953
Introduction ............................................................................................................... 954
23.1.1 Purpose of the Peripheral ..................................................................................... 954
23.1.2 Features ......................................................................................................... 954
23.1.3 Protocols Supported ........................................................................................... 955
23.1.4 Functional Block Diagram ..................................................................................... 956
23.1.5 Industry Standard Compliance Statement .................................................................. 959
23.1.6 Definition of Terms ............................................................................................. 964
Architecture ............................................................................................................... 967
23.2.1 Overview ........................................................................................................ 967
23.2.2 Clock and Frame Sync Generators .......................................................................... 967
23.2.3 General Architecture ........................................................................................... 971
23.2.4 Operation ........................................................................................................ 977
23.2.5 Reset Considerations ........................................................................................ 1007
23.2.6 EDMA Event Support ........................................................................................ 1007
23.2.7 Power Management .......................................................................................... 1007
Registers ................................................................................................................. 1008
23.3.1 Register Bit Restrictions ..................................................................................... 1011
23.3.2 Revision Identification Register (REV) ..................................................................... 1012
23.3.3 Pin Function Register (PFUNC) ............................................................................ 1012
23.3.4 Pin Direction Register (PDIR) ............................................................................... 1014
23.3.5 Pin Data Output Register (PDOUT) ........................................................................ 1016
23.3.6 Pin Data Input Register (PDIN) ............................................................................. 1018
23.3.7 Pin Data Set Register (PDSET) ............................................................................ 1020
23.3.8 Pin Data Clear Register (PDCLR) .......................................................................... 1022
23.3.9 Global Control Register (GBLCTL) ......................................................................... 1024
23.3.10 Audio Mute Control Register (AMUTE) .................................................................. 1026
23.3.11 Digital Loopback Control Register (DLBCTL) ........................................................... 1028
23.3.12 Digital Mode Control Register (DITCTL) ................................................................. 1029
23.3.13 Receiver Global Control Register (RGBLCTL) .......................................................... 1030
23.3.14 Receive Format Unit Bit Mask Register (RMASK) ..................................................... 1031
23.3.15 Receive Bit Stream Format Register (RFMT) ........................................................... 1032
23.3.16 Receive Frame Sync Control Register (AFSRCTL) .................................................... 1034
23.3.17 Receive Clock Control Register (ACLKRCTL) .......................................................... 1035
23.3.18 Receive High-Frequency Clock Control Register (AHCLKRCTL) .................................... 1036
23.3.19 Receive TDM Time Slot Register (RTDM) .............................................................. 1037
23.3.20 Receiver Interrupt Control Register (RINTCTL) ......................................................... 1038
23.3.21 Receiver Status Register (RSTAT) ....................................................................... 1039
23.3.22 Current Receive TDM Time Slot Registers (RSLOT) .................................................. 1040
23.3.23 Receive Clock Check Control Register (RCLKCHK) ................................................... 1041
23.3.24 Receiver DMA Event Control Register (REVTCTL) .................................................... 1042
23.3.25 Transmitter Global Control Register (XGBLCTL) ....................................................... 1043
23.3.26 Transmit Format Unit Bit Mask Register (XMASK) ..................................................... 1044
23.3.27 Transmit Bit Stream Format Register (XFMT) .......................................................... 1045
23.3.28 Transmit Frame Sync Control Register (AFSXCTL) ................................................... 1047
23.3.29 Transmit Clock Control Register (ACLKXCTL) ......................................................... 1048
23.3.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................... 1049
Contents
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23.3.31
23.3.32
23.3.33
23.3.34
23.3.35
23.3.36
23.3.37
23.3.38
23.3.39
23.3.40
23.3.41
23.3.42
23.3.43
23.3.44
23.3.45
23.3.46
23.3.47
23.3.48
24
Transmit TDM Time Slot Register (XTDM) ..............................................................
Transmitter Interrupt Control Register (XINTCTL) ......................................................
Transmitter Status Register (XSTAT) ....................................................................
Current Transmit TDM Time Slot Register (XSLOT) ...................................................
Transmit Clock Check Control Register (XCLKCHK) ..................................................
Transmitter DMA Event Control Register (XEVTCTL) .................................................
Serializer Control Registers (SRCTLn) ..................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .........................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) .......................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ....................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ..................................
Transmit Buffer Registers (XBUFn) ......................................................................
Receive Buffer Registers (RBUFn) .......................................................................
AFIFO Revision Identification Register (AFIFOREV) ..................................................
Write FIFO Control Register (WFIFOCTL) ..............................................................
Write FIFO Status Register (WFIFOSTS) ...............................................................
Read FIFO Control Register (RFIFOCTL) ...............................................................
Read FIFO Status Register (RFIFOSTS) ................................................................
Multichannel Buffered Serial Port (McBSP)
24.1
24.2
24.3
....................................................................... 1065
Introduction ..............................................................................................................
24.1.1 Purpose of the Peripheral ...................................................................................
24.1.2 Features .......................................................................................................
24.1.3 Functional Block Diagram ...................................................................................
24.1.4 Industry Standard Compliance Statement ................................................................
Architecture ..............................................................................................................
24.2.1 Clock Control ..................................................................................................
24.2.2 Signal Descriptions ...........................................................................................
24.2.3 Pin Multiplexing ...............................................................................................
24.2.4 Endianness Considerations .................................................................................
24.2.5 Clock, Frames, and Data ....................................................................................
24.2.6 McBSP Buffer FIFO (BFIFO) ...............................................................................
24.2.7 McBSP Standard Operation ................................................................................
24.2.8 μ-Law/A-Law Companding Hardware Operation .........................................................
24.2.9 Multichannel Selection Modes ..............................................................................
24.2.10 SPI Operation Using the Clock Stop Mode ..............................................................
24.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET ........................................
24.2.12 McBSP Initialization Procedure ...........................................................................
24.2.13 Interrupt Support ............................................................................................
24.2.14 EDMA Event Support .......................................................................................
24.2.15 Power Management ........................................................................................
24.2.16 Emulation Considerations ..................................................................................
Registers .................................................................................................................
24.3.1 Data Receive Register (DRR) ..............................................................................
24.3.2 Data Transmit Register (DXR) ..............................................................................
24.3.3 Serial Port Control Register (SPCR) .......................................................................
24.3.4 Receive Control Register (RCR) ...........................................................................
24.3.5 Transmit Control Register (XCR) ...........................................................................
24.3.6 Sample Rate Generator Register (SRGR) ................................................................
24.3.7 Multichannel Control Register (MCR) ......................................................................
24.3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ..................................
24.3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) .................................
24.3.10 Pin Control Register (PCR) ................................................................................
24.3.11 BFIFO Revision Identification Register (BFIFOREV) ..................................................
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1051
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24.3.12
24.3.13
24.3.14
24.3.15
25
1135
1136
1137
1138
................................................ 1139
Introduction .............................................................................................................. 1140
25.1.1 Purpose of the Peripheral ................................................................................... 1140
25.1.2 Features ....................................................................................................... 1140
25.1.3 Functional Block Diagram ................................................................................... 1140
25.1.4 Supported Use Case Statement ............................................................................ 1140
25.1.5 Industry Standard(s) Compliance Statement ............................................................. 1141
Architecture .............................................................................................................. 1141
25.2.1 Clock Control .................................................................................................. 1142
25.2.2 Signal Descriptions ........................................................................................... 1143
25.2.3 Protocol Descriptions ........................................................................................ 1143
25.2.4 Data Flow in the Input/Output FIFO ........................................................................ 1145
25.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) .......................................... 1147
25.2.6 FIFO Operation During Card Read Operation ............................................................ 1148
25.2.7 FIFO Operation During Card Write Operation ............................................................ 1150
25.2.8 Reset Considerations ........................................................................................ 1150
25.2.9 Initialization .................................................................................................... 1152
25.2.10 Interrupt Support ............................................................................................ 1155
25.2.11 DMA Event Support ........................................................................................ 1156
25.2.12 Power Management ........................................................................................ 1156
25.2.13 Emulation Considerations .................................................................................. 1156
Procedures for Common Operations ................................................................................ 1157
25.3.1 Card Identification Operation ............................................................................... 1157
25.3.2 MMC/SD Mode Single-Block Write Operation Using CPU .............................................. 1160
25.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ....................................... 1162
25.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ......................................... 1162
25.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ........................................... 1164
25.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU ............................................ 1164
25.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA .......................................... 1166
25.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................ 1166
25.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA .......................................... 1168
25.3.10 SDIO Card Function ........................................................................................ 1168
Registers ................................................................................................................. 1169
25.4.1 MMC Control Register (MMCCTL) ......................................................................... 1170
25.4.2 MMC Memory Clock Control Register (MMCCLK) ....................................................... 1171
25.4.3 MMC Status Register 0 (MMCST0) ........................................................................ 1172
25.4.4 MMC Status Register 1 (MMCST1) ........................................................................ 1174
25.4.5 MMC Interrupt Mask Register (MMCIM) .................................................................. 1175
25.4.6 MMC Response Time-Out Register (MMCTOR) ......................................................... 1177
25.4.7 MMC Data Read Time-Out Register (MMCTOD) ........................................................ 1178
25.4.8 MMC Block Length Register (MMCBLEN) ................................................................ 1179
25.4.9 MMC Number of Blocks Register (MMCNBLK) .......................................................... 1180
25.4.10 MMC Number of Blocks Counter Register (MMCNBLC) .............................................. 1180
25.4.11 MMC Data Receive Register (MMCDRR) ............................................................... 1181
25.4.12 MMC Data Transmit Register (MMCDXR) ............................................................... 1181
25.4.13 MMC Command Register (MMCCMD) ................................................................... 1182
25.4.14 MMC Argument Register (MMCARGHL) ................................................................ 1184
25.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) .................................................. 1185
25.4.16 MMC Data Response Register (MMCDRSP) ........................................................... 1187
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.1
25.2
25.3
25.4
16
Write FIFO Control Register (WFIFOCTL) ..............................................................
Write FIFO Status Register (WFIFOSTS) ...............................................................
Read FIFO Control Register (RFIFOCTL) ...............................................................
Read FIFO Status Register (RFIFOSTS) ................................................................
Contents
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25.4.17
25.4.18
25.4.19
25.4.20
25.4.21
25.4.22
26
Real-Time Clock (RTC)
26.1
26.2
26.3
27
MMC Command Index Register (MMCCIDX) ...........................................................
SDIO Control Register (SDIOCTL) .......................................................................
SDIO Status Register 0 (SDIOST0) ......................................................................
SDIO Interrupt Enable Register (SDIOIEN) .............................................................
SDIO Interrupt Status Register (SDIOIST) ..............................................................
MMC FIFO Control Register (MMCFIFOCTL) ..........................................................
.................................................................................................... 1193
Introduction ..............................................................................................................
26.1.1 Purpose of the Peripheral ...................................................................................
26.1.2 Features .......................................................................................................
26.1.3 Block Diagram ................................................................................................
Architecture ..............................................................................................................
26.2.1 Clock Source ..................................................................................................
26.2.2 Signal Descriptions ...........................................................................................
26.2.3 Isolated Power Supply .......................................................................................
26.2.4 Operation ......................................................................................................
26.2.5 Interrupt Requests ............................................................................................
26.2.6 Register Protection Against Spurious Writes .............................................................
26.2.7 General-Purpose Scratch Registers .......................................................................
26.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) ..............................
26.2.9 Emulation Modes of the Real-Time Clock .................................................................
26.2.10 Reset Considerations .......................................................................................
Registers .................................................................................................................
26.3.1 Second Register (SECOND) ................................................................................
26.3.2 Minute Register (MINUTE) ..................................................................................
26.3.3 Hour Register (HOUR) .......................................................................................
26.3.4 Day of the Month Register (DAY) ..........................................................................
26.3.5 Month Register (MONTH) ...................................................................................
26.3.6 Year Register (YEAR) .......................................................................................
26.3.7 Day of the Week Register (DOTW) ........................................................................
26.3.8 Alarm Second Register (ALARMSECOND) ...............................................................
26.3.9 Alarm Minute Register (ALARMMINUTE) .................................................................
26.3.10 Alarm Hour Register (ALARMHOUR) ....................................................................
26.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................
26.3.12 Alarm Month Register (ALARMMONTH) ................................................................
26.3.13 Alarm Year Register (ALARMYEAR) .....................................................................
26.3.14 Control Register (CTRL) ...................................................................................
26.3.15 Status Register (STATUS) .................................................................................
26.3.16 Interrupt Register (INTERRUPT) .........................................................................
26.3.17 Compensation (LSB) Register (COMPLSB) .............................................................
26.3.18 Compensation (MSB) Register (COMPMSB) ...........................................................
26.3.19 Oscillator Register (OSC) ..................................................................................
26.3.20 Scratch Registers (SCRATCH0-SCRATCH2) ..........................................................
26.3.21 Kick Registers (KICK0R, KICK1R) .......................................................................
Serial Peripheral Interface (SPI)
27.1
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27.1.1 Purpose of the Peripheral ...................................................................................
27.1.2 Features .......................................................................................................
27.1.3 Functional Block Diagram ...................................................................................
27.1.4 Industry Standard(s) Compliance Statement .............................................................
Architecture ..............................................................................................................
27.2.1 Clock ...........................................................................................................
27.2.2 Signal Descriptions ...........................................................................................
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27.3
28
64-Bit Timer Plus
28.1
28.2
18
27.2.3 Operation Modes .............................................................................................
27.2.4 Programmable Registers ....................................................................................
27.2.5 Master Mode Settings ........................................................................................
27.2.6 Slave Mode Settings .........................................................................................
27.2.7 SPI Operation: 3-Pin Mode .................................................................................
27.2.8 SPI Operation: 4-Pin with Chip Select Mode .............................................................
27.2.9 SPI Operation: 4-Pin with Enable Mode ...................................................................
27.2.10 SPI Operation: 5-Pin Mode ................................................................................
27.2.11 Data Formats ................................................................................................
27.2.12 Interrupt Support ............................................................................................
27.2.13 DMA Events Support .......................................................................................
27.2.14 Robustness Features .......................................................................................
27.2.15 Reset Considerations .......................................................................................
27.2.16 Power Management ........................................................................................
27.2.17 General-Purpose I/O Pin ...................................................................................
27.2.18 Emulation Considerations ..................................................................................
27.2.19 Initialization ..................................................................................................
27.2.20 Timing Diagrams ............................................................................................
Registers .................................................................................................................
27.3.1 SPI Global Control Register 0 (SPIGCR0) ................................................................
27.3.2 SPI Global Control Register 1 (SPIGCR1) ................................................................
27.3.3 SPI Interrupt Register (SPIINT0) ...........................................................................
27.3.4 SPI Interrupt Level Register (SPILVL) .....................................................................
27.3.5 SPI Flag Register (SPIFLG) ................................................................................
27.3.6 SPI Pin Control Register 0 (SPIPC0) ......................................................................
27.3.7 SPI Pin Control Register 1 (SPIPC1) ......................................................................
27.3.8 SPI Pin Control Register 2 (SPIPC2) ......................................................................
27.3.9 SPI Pin Control Register 3 (SPIPC3) ......................................................................
27.3.10 SPI Pin Control Register 4 (SPIPC4) ....................................................................
27.3.11 SPI Pin Control Register 5 (SPIPC5) ....................................................................
27.3.12 SPI Transmit Data Register 0 (SPIDAT0) ...............................................................
27.3.13 SPI Transmit Data Register 1 (SPIDAT1) ...............................................................
27.3.14 SPI Receive Buffer Register (SPIBUF) ..................................................................
27.3.15 SPI Emulation Register (SPIEMU) .......................................................................
27.3.16 SPI Delay Register (SPIDELAY) ..........................................................................
27.3.17 SPI Default Chip Select Register (SPIDEF) .............................................................
27.3.18 SPI Data Format Registers (SPIFMTn) ..................................................................
27.3.19 SPI Interrupt Vector Register 1 (INTVEC1) .............................................................
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28.1.1 Purpose of the Peripheral ...................................................................................
28.1.2 Features .......................................................................................................
28.1.3 Block Diagram ................................................................................................
28.1.4 Industry Standard Compatibility Statement ...............................................................
Architecture ..............................................................................................................
28.2.1 Architecture – General-Purpose Timer Mode .............................................................
28.2.2 Architecture – Watchdog Timer Mode .....................................................................
28.2.3 Reset Considerations ........................................................................................
28.2.4 Interrupt Support ..............................................................................................
28.2.5 DMA Event Support ..........................................................................................
28.2.6 TM64P_OUT Event Support ................................................................................
28.2.7 External Timer Pin GPIO Mode ............................................................................
28.2.8 Interrupt/DMA Event Generation Control and Status ....................................................
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28.3
29
Universal Asynchronous Receiver/Transmitter (UART)
29.1
29.2
29.3
30
28.2.9 Power Management ..........................................................................................
28.2.10 Emulation Considerations ..................................................................................
Registers .................................................................................................................
28.3.1 Revision ID Register (REVID) ..............................................................................
28.3.2 Emulation Management Register (EMUMGT) ............................................................
28.3.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ...........................................
28.3.4 GPIO Data and Direction Register (GPDATGPDIR) .....................................................
28.3.5 Timer Counter Registers (TIM12 and TIM34) ............................................................
28.3.6 Timer Period Registers (PRD12 and PRD34) ............................................................
28.3.7 Timer Control Register (TCR) ..............................................................................
28.3.8 Timer Global Control Register (TGCR) ....................................................................
28.3.9 Watchdog Timer Control Register (WDTCR) .............................................................
28.3.10 Timer Reload Register 12 (REL12) .......................................................................
28.3.11 Timer Reload Register 34 (REL34) .......................................................................
28.3.12 Timer Capture Register 12 (CAP12) .....................................................................
28.3.13 Timer Capture Register 34 (CAP34) .....................................................................
28.3.14 Timer Interrupt Control and Status Register (INTCTLSTAT) ..........................................
28.3.15 Timer Compare Registers (CMP0-CMP7) ...............................................................
....................................................... 1307
Introduction ..............................................................................................................
29.1.1 Purpose of the Peripheral ...................................................................................
29.1.2 Features .......................................................................................................
29.1.3 Functional Block Diagram ...................................................................................
29.1.4 Industry Standard(s) Compliance Statement .............................................................
Peripheral Architecture ................................................................................................
29.2.1 Clock Generation and Control ..............................................................................
29.2.2 Signal Descriptions ...........................................................................................
29.2.3 Pin Multiplexing ...............................................................................................
29.2.4 Protocol Description ..........................................................................................
29.2.5 Operation ......................................................................................................
29.2.6 Reset Considerations ........................................................................................
29.2.7 Initialization ....................................................................................................
29.2.8 Interrupt Support ..............................................................................................
29.2.9 DMA Event Support ..........................................................................................
29.2.10 Power Management ........................................................................................
29.2.11 Emulation Considerations ..................................................................................
29.2.12 Exception Processing ......................................................................................
Registers .................................................................................................................
29.3.1 Receiver Buffer Register (RBR) ............................................................................
29.3.2 Transmitter Holding Register (THR) .......................................................................
29.3.3 Interrupt Enable Register (IER) .............................................................................
29.3.4 Interrupt Identification Register (IIR) .......................................................................
29.3.5 FIFO Control Register (FCR) ...............................................................................
29.3.6 Line Control Register (LCR) ................................................................................
29.3.7 Modem Control Register (MCR) ............................................................................
29.3.8 Line Status Register (LSR) ..................................................................................
29.3.9 Modem Status Register (MSR) .............................................................................
29.3.10 Scratch Pad Register (SCR) ..............................................................................
29.3.11 Divisor Latches (DLL and DLH) ...........................................................................
29.3.12 Revision Identification Registers (REVID1 and REVID2) ..............................................
29.3.13 Power and Emulation Management Register (PWREMU_MGMT) ...................................
29.3.14 Mode Definition Register (MDR) ..........................................................................
Universal Serial Bus 2.0 (USB) Controller
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30.1
30.2
30.3
30.4
20
Introduction ..............................................................................................................
30.1.1 Purpose of the Peripheral ...................................................................................
30.1.2 Features .......................................................................................................
30.1.3 Functional Block Diagram ...................................................................................
30.1.4 Industry Standard(s) Compliance Statement .............................................................
Architecture ..............................................................................................................
30.2.1 Clock Control ..................................................................................................
30.2.2 Signal Descriptions ...........................................................................................
30.2.3 Indexed and Non-Indexed Registers .......................................................................
30.2.4 USB PHY Initialization .......................................................................................
30.2.5 VBUS Voltage Sourcing Control ............................................................................
30.2.6 Dynamic FIFO Sizing ........................................................................................
30.2.7 USB Controller Host and Peripheral Modes Operation ..................................................
30.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ...........................
30.2.9 Test Modes ....................................................................................................
30.2.10 Reset Considerations .......................................................................................
30.2.11 Interrupt Support ............................................................................................
30.2.12 DMA Event Support ........................................................................................
30.2.13 Power Management ........................................................................................
Use Cases ...............................................................................................................
30.3.1 User Case 1: Example of How to Initialize the USB Controller ........................................
30.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode ................
30.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode .......................
30.3.4 User Case 4: Example of How to Program the USB DMA Controller .................................
Registers .................................................................................................................
30.4.1 Revision Identification Register (REVID) ..................................................................
30.4.2 Control Register (CTRLR) ...................................................................................
30.4.3 Status Register (STATR) ....................................................................................
30.4.4 Emulation Register (EMUR) ................................................................................
30.4.5 Mode Register (MODE) ......................................................................................
30.4.6 Auto Request Register (AUTOREQ) .......................................................................
30.4.7 SRP Fix Time Register (SRPFIXTIME) ...................................................................
30.4.8 Teardown Register (TEARDOWN) .........................................................................
30.4.9 USB Interrupt Source Register (INTSRCR) ...............................................................
30.4.10 USB Interrupt Source Set Register (INTSETR) .........................................................
30.4.11 USB Interrupt Source Clear Register (INTCLRR) ......................................................
30.4.12 USB Interrupt Mask Register (INTMSKR) ...............................................................
30.4.13 USB Interrupt Mask Set Register (INTMSKSETR) .....................................................
30.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) ..................................................
30.4.15 USB Interrupt Source Masked Register (INTMASKEDR) .............................................
30.4.16 USB End of Interrupt Register (EOIR) ...................................................................
30.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) .................................................
30.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) .................................................
30.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) .................................................
30.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................................................
30.4.21 Function Address Register (FADDR) .....................................................................
30.4.22 Power Management Register (POWER) .................................................................
30.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................
30.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ............................................
30.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ......................................................
30.4.26 Interrupt Enable Register for INTRRX (INTRRXE) .....................................................
30.4.27 Interrupt Register for Common USB Interrupts (INTRUSB) ...........................................
30.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) .................................................
Contents
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30.4.29 Frame Number Register (FRAME) .......................................................................
30.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) .................
30.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE) ..........................................
30.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ..........................
30.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) .........................
30.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...............................
30.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .........................
30.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................
30.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ..........................
30.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .........................
30.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ...............................
30.4.40 Count 0 Register (COUNT0) ..............................................................................
30.4.41 Receive Count Register (RXCOUNT) ....................................................................
30.4.42 Type Register (Host mode only) (HOST_TYPE0) ......................................................
30.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) .........................................
30.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ..........................................
30.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................
30.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) .........................................
30.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................
30.4.48 Configuration Data Register (CONFIGDATA) ...........................................................
30.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ........................................
30.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ........................................
30.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ........................................
30.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ........................................
30.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ........................................
30.4.54 Device Control Register (DEVCTL) .......................................................................
30.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ) ..............................................................
30.4.56 Receive Endpoint FIFO Size (RXFIFOSZ) ..............................................................
30.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR) .....................................................
30.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) .....................................................
30.4.59 Hardware Version Register (HWVERS) .................................................................
30.4.60 Transmit Function Address (TXFUNCADDR) ...........................................................
30.4.61 Transmit Hub Address (TXHUBADDR) ..................................................................
30.4.62 Transmit Hub Port (TXHUBPORT) .......................................................................
30.4.63 Receive Function Address (RXFUNCADDR) ...........................................................
30.4.64 Receive Hub Address (RXHUBADDR) ..................................................................
30.4.65 Receive Hub Port (RXHUBPORT) ........................................................................
30.4.66 CDMA Revision Identification Register (DMAREVID) ..................................................
30.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ...............................
30.4.68 CDMA Emulation Control Register (DMAEMU) .........................................................
30.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) ..............
30.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) ..............
30.4.71 CDMA Receive Channel n Host Packet Configuration Registers A
(RXHPCRA[0]-RXHPCRA[3]) ................................................................................
30.4.72 CDMA Receive Channel n Host Packet Configuration Registers B
(RXHPCRB[0]-RXHPCRB[3]) ................................................................................
30.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ...........................................
30.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) ..................................
30.4.75 Queue Manager Revision Identification Register (QMGRREVID) ....................................
30.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................
30.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ..................
30.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ..................
30.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ..................
30.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ..................
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Contents
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30.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ..................
30.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ..............................
30.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ..................
30.4.84 Queue Manager Queue Pending Register 0 (PEND0) ................................................
30.4.85 Queue Manager Queue Pending Register 1 (PEND1) ................................................
30.4.86 Queue Manager Memory Region R Base Address Registers
(QMEMRBASE[0]-QMEMRBASE[15]) ......................................................................
30.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
30.4.88 Queue Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) .............................
30.4.89 Queue Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ...........................
30.4.90 Queue Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ...........................
30.4.91 Queue Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ..........................
A
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List of Figures
.................................................................
1-1.
OMAP-L132 Applications Processor Block Diagram
3-1.
TMS320C674x Megamodule Block Diagram .......................................................................... 82
4-1.
System Interconnect Block Diagram .................................................................................... 91
6-1.
MPU Block Diagram....................................................................................................... 98
6-2.
Permission Fields ........................................................................................................ 100
6-3.
Revision ID Register (REVID) .......................................................................................... 106
6-4.
Configuration Register (CONFIG)
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
.....................................................................................
Interrupt Raw Status/Set Register (IRAWSTAT).....................................................................
Interrupt Enable Status/Clear Register (IENSTAT) ..................................................................
Interrupt Enable Set Register (IENSET) ..............................................................................
Interrupt Enable Clear Register (IENCLR) ............................................................................
Fixed Range Start Address Register (FXD_MPSAR) ...............................................................
Fixed Range End Address Register (FXD_MPEAR) ................................................................
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .......................................
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) .....................................
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) .....................................
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) ......................................
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ......................................
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) ........................
Fault Address Register (FLTADDRR) .................................................................................
Fault Status Register (FLTSTAT) ......................................................................................
Fault Clear Register (FLTCLR).........................................................................................
Overall Clocking Diagram ...............................................................................................
USB Clocking Diagram ..................................................................................................
DDR2/mDDR Memory Controller Clocking Diagram ................................................................
EMIFA Clocking Diagram ...............................................................................................
EMAC Clocking Diagram................................................................................................
McASP Clocking Diagram ..............................................................................................
PLLC Structure ...........................................................................................................
PLLC0 Revision Identification Register (REVID) ....................................................................
PLLC1 Revision Identification Register (REVID) ....................................................................
Reset Type Status Register (RSTYPE) ...............................................................................
Reset Control Register (RSCTRL) .....................................................................................
PLLC0 Control Register (PLLCTL) ....................................................................................
PLLC1 Control Register (PLLCTL) ....................................................................................
PLLC0 OBSCLK Select Register (OCSEL)...........................................................................
PLLC1 OBSCLK Select Register (OCSEL)...........................................................................
PLL Multiplier Control Register (PLLM) ...............................................................................
PLLC0 Pre-Divider Control Register (PREDIV) ......................................................................
PLLC0 Divider 1 Register (PLLDIV1) .................................................................................
PLLC1 Divider 1 Register (PLLDIV1) .................................................................................
PLLC0 Divider 2 Register (PLLDIV2) .................................................................................
PLLC1 Divider 2 Register (PLLDIV2) .................................................................................
PLLC0 Divider 3 Register (PLLDIV3) .................................................................................
PLLC1 Divider 3 Register (PLLDIV3) .................................................................................
PLLC0 Divider 4 Register (PLLDIV4) .................................................................................
PLLC0 Divider 5 Register (PLLDIV5) .................................................................................
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8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
10-1.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
24
.................................................................................
PLLC0 Divider 7 Register (PLLDIV7) .................................................................................
PLLC0 Oscillator Divider 1 Register (OSCDIV) ......................................................................
PLLC1 Oscillator Divider 1 Register (OSCDIV) ......................................................................
PLL Post-Divider Control Register (POSTDIV) ......................................................................
PLL Controller Command Register (PLLCMD).......................................................................
PLL Controller Status Register (PLLSTAT)...........................................................................
PLLC0 Clock Align Control Register (ALNCTL)......................................................................
PLLC1 Clock Align Control Register (ALNCTL)......................................................................
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ......................................................
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ......................................................
PLLC0 Clock Enable Control Register (CKEN) ......................................................................
PLLC1 Clock Enable Control Register (CKEN) ......................................................................
PLLC0 Clock Status Register (CKSTAT) .............................................................................
PLLC1 Clock Status Register (CKSTAT) .............................................................................
PLLC0 SYSCLK Status Register (SYSTAT) .........................................................................
PLLC1 SYSCLK Status Register (SYSTAT) .........................................................................
Emulation Performance Counter 0 Register (EMUCNT0) ..........................................................
Emulation Performance Counter 1 Register (EMUCNT1) ..........................................................
Revision Identification Register (REVID) .............................................................................
Interrupt Evaluation Register (INTEVAL) .............................................................................
PSC0 Module Error Pending Register 0 (MERRPR0) ..............................................................
PSC1 Module Error Pending Register 0 (MERRPR0) ..............................................................
PSC0 Module Error Clear Register 0 (MERRCR0)..................................................................
PSC1 Module Error Clear Register 0 (MERRCR0)..................................................................
Power Error Pending Register (PERRPR) ............................................................................
Power Error Clear Register (PERRCR) ...............................................................................
Power Domain Transition Command Register (PTCMD) ...........................................................
Power Domain Transition Status Register (PTSTAT) ...............................................................
Power Domain 0 Status Register (PDSTAT0) .......................................................................
Power Domain 1 Status Register (PDSTAT1) .......................................................................
Power Domain 0 Control Register (PDCTL0) ........................................................................
Power Domain 1 Control Register (PDCTL1) ........................................................................
Power Domain 0 Configuration Register (PDCFG0) ................................................................
Power Domain 1 Configuration Register (PDCFG1) ................................................................
Module Status n Register (MDSTATn) ................................................................................
PSC0 Module Control n Register (MDCTLn) .........................................................................
PSC1 Module Control n Register (MDCTLn) .........................................................................
Deep Sleep Mode Sequence ...........................................................................................
Revision Identification Register (REVID) .............................................................................
Device Identification Register 0 (DEVIDR0) ..........................................................................
Boot Configuration Register (BOOTCFG) ............................................................................
Kick 0 Register (KICK0R) ...............................................................................................
Kick 1 Register (KICK1R) ...............................................................................................
Host 0 Configuration Register (HOST0CFG) .........................................................................
Host 1 Configuration Register (HOST1CFG) .........................................................................
Interrupt Raw Status/Set Register (IRAWSTAT).....................................................................
Interrupt Enable Status/Clear Register (IENSTAT) ..................................................................
Interrupt Enable Register (IENSET) ...................................................................................
PLLC0 Divider 6 Register (PLLDIV6)
List of Figures
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11-11. Interrupt Enable Clear Register (IENCLR) ............................................................................ 219
11-12. End of Interrupt Register (EOI) ......................................................................................... 220
11-13. Fault Address Register (FLTADDRR) ................................................................................. 220
11-14. Fault Status Register (FLTSTAT) ...................................................................................... 221
11-15. Master Priority 0 Register (MSTPRI0)................................................................................. 222
11-16. Master Priority 1 Register (MSTPRI1)................................................................................. 223
11-17. Master Priority 2 Register (MSTPRI2)................................................................................. 224
11-18. Pin Multiplexing Control 0 Register (PINMUX0) ..................................................................... 225
11-19. Pin Multiplexing Control 1 Register (PINMUX1) ..................................................................... 227
11-20. Pin Multiplexing Control 2 Register (PINMUX2) ..................................................................... 229
11-21. Pin Multiplexing Control 3 Register (PINMUX3) ..................................................................... 231
11-22. Pin Multiplexing Control 4 Register (PINMUX4) ..................................................................... 233
11-23. Pin Multiplexing Control 5 Register (PINMUX5) ..................................................................... 235
11-24. Pin Multiplexing Control 6 Register (PINMUX6) ..................................................................... 237
11-25. Pin Multiplexing Control 7 Register (PINMUX7) ..................................................................... 239
11-26. Pin Multiplexing Control 8 Register (PINMUX8) ..................................................................... 241
11-27. Pin Multiplexing Control 9 Register (PINMUX9) ..................................................................... 243
11-28. Pin Multiplexing Control 10 Register (PINMUX10) .................................................................. 245
11-29. Pin Multiplexing Control 11 Register (PINMUX11) .................................................................. 247
11-30. Pin Multiplexing Control 12 Register (PINMUX12) .................................................................. 249
11-31. Pin Multiplexing Control 13 Register (PINMUX13) .................................................................. 251
11-32. Pin Multiplexing Control 14 Register (PINMUX14) .................................................................. 253
11-33. Pin Multiplexing Control 15 Register (PINMUX15) .................................................................. 255
11-34. Pin Multiplexing Control 16 Register (PINMUX16) .................................................................. 257
11-35. Pin Multiplexing Control 17 Register (PINMUX17) .................................................................. 259
11-36. Pin Multiplexing Control 18 Register (PINMUX18) .................................................................. 261
11-37. Pin Multiplexing Control 19 Register (PINMUX19) .................................................................. 263
11-38. Suspend Source Register (SUSPSRC) ............................................................................... 265
11-39. Chip Signal Register (CHIPSIG) ....................................................................................... 267
11-40. Chip Signal Clear Register (CHIPSIG_CLR) ......................................................................... 268
11-41. Chip Configuration 0 Register (CFGCHIP0) .......................................................................... 269
11-42. Chip Configuration 1 Register (CFGCHIP1) .......................................................................... 270
11-43. Chip Configuration 2 Register (CFGCHIP2) .......................................................................... 273
11-44. Chip Configuration 3 Register (CFGCHIP3) .......................................................................... 275
11-45. Chip Configuration 4 Register (CFGCHIP4) .......................................................................... 276
11-46. VTP I/O Control Register (VTPIO_CTL) .............................................................................. 277
11-47. DDR Slew Register (DDR_SLEW)..................................................................................... 279
11-48. Deep Sleep Register (DEEPSLEEP) .................................................................................. 280
11-49. Pullup/Pulldown Enable Register (PUPD_ENA) ..................................................................... 281
11-50. Pullup/Pulldown Select Register (PUPD_SEL)
......................................................................
281
11-51. RXACTIVE Control Register (RXACTIVE)............................................................................ 283
...............................................................................................
12-1.
AINTC Interrupt Mapping
12-2.
Flow of System Interrupts to Host ..................................................................................... 289
12-3.
Revision Identification Register (REVID)
12-4.
12-5.
12-6.
12-7.
12-8.
.............................................................................
Control Register (CR) ...................................................................................................
Global Enable Register (GER) .........................................................................................
Global Nesting Level Register (GNLR) ...............................................................................
System Interrupt Status Indexed Set Register (SISR) ..............................................................
System Interrupt Status Indexed Clear Register (SICR)............................................................
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12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
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15-15.
15-16.
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.............................................................
System Interrupt Enable Indexed Clear Register (EICR) ...........................................................
Host Interrupt Enable Indexed Set Register (HEISR) ...............................................................
Host Interrupt Enable Indexed Clear Register (HIEICR)............................................................
Vector Base Register (VBR) ............................................................................................
Vector Size Register (VSR) .............................................................................................
Vector Null Register (VNR) .............................................................................................
Global Prioritized Index Register (GPIR) .............................................................................
Global Prioritized Vector Register (GPVR) ...........................................................................
System Interrupt Status Raw/Set Register 1 (SRSR1) .............................................................
System Interrupt Status Raw/Set Register 2 (SRSR2) .............................................................
System Interrupt Status Raw/Set Register 3 (SRSR3) .............................................................
System Interrupt Status Raw/Set Register 4 (SRSR4) .............................................................
System Interrupt Status Enabled/Clear Register 1 (SECR1) ......................................................
System Interrupt Status Enabled/Clear Register 2 (SECR2) ......................................................
System Interrupt Status Enabled/Clear Register 3 (SECR3) ......................................................
System Interrupt Status Enabled/Clear Register 4 (SECR4) ......................................................
System Interrupt Enable Set Register 1 (ESR1) .....................................................................
System Interrupt Enable Set Register 2 (ESR2) .....................................................................
System Interrupt Enable Set Register 3 (ESR3) .....................................................................
System Interrupt Enable Set Register 4 (ESR4) .....................................................................
System Interrupt Enable Clear Register 1 (ECR1) ..................................................................
System Interrupt Enable Clear Register 2 (ECR2) ..................................................................
System Interrupt Enable Clear Register 3 (ECR3) ..................................................................
System Interrupt Enable Clear Register 4 (ECR4) ..................................................................
Channel Map Registers (CMRn) .......................................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) ................................................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) ................................................................
Host Interrupt Nesting Level Register 1 (HINLR1) ..................................................................
Host Interrupt Nesting Level Register 2 (HINLR2) ..................................................................
Host Interrupt Enable Register (HIER) ................................................................................
Host Interrupt Prioritized Vector Register 1 (HIPVR1) ..............................................................
Host Interrupt Prioritized Vector Register 2 (HIPVR2) ..............................................................
Data Paths to DDR2/mDDR Memory Controller .....................................................................
DDR2/mDDR Memory Controller Clock Block Diagram ............................................................
DDR2/mDDR Memory Controller Signals.............................................................................
Refresh Command .......................................................................................................
DCAB Command .........................................................................................................
DEAC Command .........................................................................................................
ACTV Command .........................................................................................................
DDR2/mDDR READ Command ........................................................................................
DDR2/mDDR WRT Command .........................................................................................
DDR2/mDDR MRS and EMRS Command ...........................................................................
Byte Alignment ...........................................................................................................
Logical Address-to-DDR2/mDDR SDRAM Address Map ...........................................................
DDR2/mDDR SDRAM Column, Row, and Bank Access ...........................................................
Address Mapping Diagram (IBANKPOS = 1) ........................................................................
SDRAM Column, Row, Bank Access (IBANKPOS = 1) ............................................................
DDR2/mDDR Memory Controller FIFO Block Diagram .............................................................
System Interrupt Enable Indexed Set Register (EISR)
List of Figures
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15-17. DDR2/mDDR Memory Controller Reset Block Diagram ............................................................ 345
15-18. DDR2/mDDR Memory Controller Power Sleep Controller Diagram............................................... 350
15-19. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory ........................................ 352
15-20. Revision ID Register (REVID) .......................................................................................... 357
................................................................................
.............................................................................
SDRAM Refresh Control Register (SDRCR) ........................................................................
SDRAM Timing Register 1 (SDTIMR1) ...............................................................................
SDRAM Timing Register 2 (SDTIMR2) ...............................................................................
SDRAM Configuration Register 2 (SDCR2) .........................................................................
Peripheral Bus Burst Priority Register (PBBPR) .....................................................................
Performance Counter 1 Register (PC1) ...............................................................................
Performance Counter 2 Register (PC2) ...............................................................................
Performance Counter Configuration Register (PCC) ................................................................
Performance Counter Master Region Select Register (PCMRS) ..................................................
Performance Counter Time Register (PCT) ..........................................................................
DDR PHY Reset Control Register (DRPYRCR) .....................................................................
Interrupt Raw Register (IRR) ...........................................................................................
Interrupt Masked Register (IMR) .......................................................................................
Interrupt Mask Set Register (IMSR) ...................................................................................
Interrupt Mask Clear Register (IMCR).................................................................................
DDR PHY Control Register 1 (DRPYC1R) ...........................................................................
Multiple eCAP Modules .................................................................................................
Capture and APWM Modes of Operation .............................................................................
Capture Function Diagram ..............................................................................................
Event Prescale Control ..................................................................................................
Prescale Function Waveforms .........................................................................................
Continuous/One-shot Block Diagram..................................................................................
Counter and Synchronization Block Diagram ........................................................................
Interrupts in eCAP Module ..............................................................................................
PWM Waveform Details Of APWM Mode Operation ................................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ...............................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect .................................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect ............................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ..............................
PWM Waveform Details of APWM Mode Operation ................................................................
Multichannel PWM Example Using 4 eCAP Modules ...............................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules .......................................
Time-Stamp Counter Register (TSCTR) ..............................................................................
Counter Phase Control Register (CTRPHS) .........................................................................
Capture 1 Register (CAP1) ............................................................................................
Capture 2 Register (CAP2) .............................................................................................
Capture 3 Register (CAP3) .............................................................................................
Capture 4 Register (CAP4) .............................................................................................
ECAP Control Register 1 (ECCTL1) ..................................................................................
ECAP Control Register 2 (ECCTL2) ..................................................................................
ECAP Interrupt Enable Register (ECEINT) ...........................................................................
ECAP Interrupt Flag Register (ECFLG) ...............................................................................
ECAP Interrupt Clear Register (ECCLR) .............................................................................
15-21. SDRAM Status Register (SDRSTAT)
358
15-22. SDRAM Configuration Register (SDCR)
359
15-23.
362
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
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16-28. ECAP Interrupt Forcing Register (ECFRC) ........................................................................... 414
16-29. Revision ID Register (REVID) .......................................................................................... 415
17-1.
Multiple ePWM Modules ................................................................................................ 419
17-2.
Submodules and Signal Connections for an ePWM Module ....................................................... 420
17-3.
ePWM Submodules and Critical Internal Signal Interconnects .................................................... 421
17-4.
Time-Base Submodule Block Diagram................................................................................ 426
17-5.
Time-Base Submodule Signals and Registers ....................................................................... 428
17-6.
Time-Base Frequency and Period ..................................................................................... 430
17-7.
Time-Base Counter Synchronization Scheme 1 ..................................................................... 431
17-8.
Time-Base Up-Count Mode Waveforms .............................................................................. 433
17-9.
Time-Base Down-Count Mode Waveforms ........................................................................... 434
17-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event .... 434
17-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ........ 435
.........................................................................................
Counter-Compare Submodule Signals and Registers ..............................................................
Counter-Compare Event Waveforms in Up-Count Mode ...........................................................
Counter-Compare Events in Down-Count Mode.....................................................................
17-12. Counter-Compare Submodule
436
17-13.
436
17-14.
17-15.
439
439
17-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event .................................................................................................. 440
17-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ...................................................................................................................... 440
17-18. Action-Qualifier Submodule............................................................................................. 441
17-19. Action-Qualifier Submodule Inputs and Outputs ..................................................................... 442
17-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs .......................................... 443
17-21. Up-Down-Count Mode Symmetrical Waveform ...................................................................... 446
17-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High.................................................................................................. 447
17-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low .................................................................................................. 449
17-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............ 451
17-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 453
17-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary........................................................................................... 455
17-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low......................................................................................................................... 457
....................................................................................
Configuration Options for the Dead-Band Generator Submodule .................................................
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ..................................................
PWM-Chopper Submodule .............................................................................................
PWM-Chopper Submodule Signals and Registers ..................................................................
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ...............................
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses.......
17-28. Dead-Band Generator Submodule
459
17-29.
460
17-30.
17-31.
17-32.
17-33.
17-34.
462
463
464
465
465
17-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 466
17-36. Trip-Zone Submodule ................................................................................................... 467
17-37. Trip-Zone Submodule Mode Control Logic ........................................................................... 470
17-38. Trip-Zone Submodule Interrupt Logic ................................................................................. 470
17-39. Event-Trigger Submodule ............................................................................................... 471
17-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
..............................................
472
17-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ....................................... 472
28
List of Figures
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17-42. Event-Trigger Interrupt Generator ..................................................................................... 474
17-43. HRPWM System Interface .............................................................................................. 475
17-44. Resolution Calculations for Conventionally Generated PWM ...................................................... 476
17-45. Operating Logic Using MEP ............................................................................................ 477
17-46. Required PWM Waveform for a Requested Duty = 40.5% ......................................................... 479
17-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ............................... 481
17-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ............................... 481
17-49. Simplified ePWM Module ............................................................................................... 482
.....................................
Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ...................................................
Buck Waveforms for (Note: Only three bucks shown here) ........................................................
Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) ............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1)) ...........................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ..........................................................
Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ).........................................................
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ..............................
3-Phase Inverter Waveforms for (Only One Inverter Shown) ......................................................
Configuring Two PWM Modules for Phase Control .................................................................
Timing Waveforms Associated With Phase Control Between 2 Modules ........................................
Control of a 3-Phase Interleaved DC/DC Converter ................................................................
3-Phase Interleaved DC/DC Converter Waveforms for ............................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ...................................................................
ZVS Full-H Bridge Waveforms .........................................................................................
Time-Base Control Register (TBCTL) .................................................................................
Time-Base Status Register (TBSTS) ..................................................................................
Time-Base Phase Register (TBPHS)..................................................................................
Time-Base Counter Register (TBCNT)................................................................................
Time-Base Period Register (TBPRD) .................................................................................
Counter-Compare Control Register (CMPCTL) ......................................................................
Counter-Compare A Register (CMPA) ...............................................................................
Counter-Compare B Register (CMPB) ................................................................................
Action-Qualifier Output A Control Register (AQCTLA) ..............................................................
Action-Qualifier Output B Control Register (AQCTLB) ..............................................................
Action-Qualifier Software Force Register (AQSFRC) ...............................................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) ...............................................
Dead-Band Generator Control Register (DBCTL) ...................................................................
Dead-Band Generator Rising Edge Delay Register (DBRED) .....................................................
Dead-Band Generator Falling Edge Delay Register (DBFED) .....................................................
PWM-Chopper Control Register (PCCTL) ............................................................................
Trip-Zone Select Register (TZSEL) ....................................................................................
Trip-Zone Control Register (TZCTL) ..................................................................................
Trip-Zone Enable Interrupt Register (TZEINT) .......................................................................
Trip-Zone Flag Register (TZFLG) ......................................................................................
Trip-Zone Clear Register (TZCLR) ....................................................................................
Trip-Zone Force Register (TZFRC) ....................................................................................
Event-Trigger Selection Register (ETSEL) ...........................................................................
Event-Trigger Prescale Register (ETPS) .............................................................................
Event-Trigger Flag Register (ETFLG) .................................................................................
Event-Trigger Clear Register (ETCLR)................................................................................
17-50. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
483
17-51.
484
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
17-80.
17-81.
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
17-88.
17-89.
17-90.
SPRUH78A – December 2011
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List of Figures
Copyright © 2011, Texas Instruments Incorporated
485
487
488
490
491
493
494
497
498
499
500
503
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506
508
509
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17-91. Event-Trigger Force Register (ETFRC) ............................................................................... 528
17-92. Time-Base Phase High-Resolution Register (TBPHSHR) .......................................................... 529
17-93. Counter-Compare A High-Resolution Register (CMPAHR) ........................................................ 529
17-94. HRPWM Configuration Register (HRCNFG) ......................................................................... 530
18-1.
EDMA3 Controller Block Diagram ..................................................................................... 535
18-2.
EDMA3 Channel Controller (EDMA3CC) Block Diagram ........................................................... 538
18-3.
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ........................................................... 539
18-4.
Definition of ACNT, BCNT, and CCNT
18-5.
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................... 541
18-6.
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)
18-7.
PaRAM Set ............................................................................................................... 543
18-8.
Linked Transfer Example
18-9.
Link-to-Self Transfer Example .......................................................................................... 552
...............................................................................
..................................................
...............................................................................................
540
542
551
18-10. QDMA Channel to PaRAM Mapping .................................................................................. 559
18-11. Shadow Region Registers .............................................................................................. 561
566
18-13.
569
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
30
........................................................................................................
Error Interrupt Operation ................................................................................................
EDMA3 Prioritization.....................................................................................................
Block Move Example ....................................................................................................
Block Move Example PaRAM Configuration .........................................................................
Subframe Extraction Example ..........................................................................................
Subframe Extraction Example PaRAM Configuration ...............................................................
Data Sorting Example ...................................................................................................
Data Sorting Example PaRAM Configuration ........................................................................
Servicing Incoming McBSP Data Example ...........................................................................
Servicing Incoming McBSP Data Example PaRAM .................................................................
Servicing Peripheral Burst Example ...................................................................................
Servicing Peripheral Burst Example PaRAM .........................................................................
Servicing Continuous McBSP Data Example ........................................................................
Servicing Continuous McBSP Data Example PaRAM ..............................................................
Servicing Continuous McBSP Data Example Reload PaRAM .....................................................
Ping-Pong Buffering for McBSP Data Example .....................................................................
Ping-Pong Buffering for McBSP Example PaRAM ..................................................................
Ping-Pong Buffering for McBSP Example Pong PaRAM ...........................................................
Ping-Pong Buffering for McBSP Example Ping PaRAM ............................................................
Intermediate Transfer Completion Chaining Example ..............................................................
Single Large Block Transfer Example .................................................................................
Smaller Packet Data Transfers Example .............................................................................
Channel Options Parameter (OPT) ....................................................................................
Channel Source Address Parameter (SRC) ..........................................................................
A Count/B Count Parameter (A_B_CNT) .............................................................................
Channel Destination Address Parameter (DST) .....................................................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ..............................................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) ......................................................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ..............................................
C Count Parameter (CCNT) ............................................................................................
Revision ID Register (REVID) ..........................................................................................
EDMA3CC Configuration Register (CCCFG) ........................................................................
QDMA Channel n Mapping Register (QCHMAPn) ..................................................................
18-12. Interrupt Diagram
List of Figures
Copyright © 2011, Texas Instruments Incorporated
576
580
581
582
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583
584
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600
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601
602
603
603
607
607
609
SPRUH78A – December 2011
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18-46. DMA Channel Queue Number Register n (DMAQNUMn) .......................................................... 610
18-47. QDMA Channel Queue Number Register (QDMAQNUM)
.........................................................
611
18-48. Event Missed Register (EMR) .......................................................................................... 612
18-49. Event Missed Clear Register (EMCR)................................................................................. 613
18-50. QDMA Event Missed Register (QEMR) ............................................................................... 614
18-51. QDMA Event Missed Clear Register (QEMCR)...................................................................... 615
18-52. EDMA3CC Error Register (CCERR)
..................................................................................
616
18-53. EDMA3CC Error Clear Register (CCERRCLR) ...................................................................... 617
18-54. Error Evaluate Register (EEVAL) ...................................................................................... 618
18-55. DMA Region Access Enable Register for Region m (DRAEm) .................................................... 619
............................................................
Event Queue Entry Registers (QxEy) .................................................................................
Queue n Status Register (QSTATn) ...................................................................................
Queue Watermark Threshold A Register (QWMTHRA) ............................................................
EDMA3CC Status Register (CCSTAT)................................................................................
Event Register (ER) .....................................................................................................
Event Clear Register (ECR) ............................................................................................
Event Set Register (ESR) ...............................................................................................
Chained Event Register (CER).........................................................................................
Event Enable Register (EER) ..........................................................................................
Event Enable Clear Register (EECR) .................................................................................
Event Enable Set Register (EESR) ....................................................................................
Secondary Event Register (SER) ......................................................................................
Secondary Event Clear Register (SECR) .............................................................................
Interrupt Enable Register (IER) ........................................................................................
Interrupt Enable Clear Register (IECR) ...............................................................................
Interrupt Enable Set Register (IESR)..................................................................................
Interrupt Pending Register (IPR) .......................................................................................
Interrupt Clear Register (ICR) ..........................................................................................
Interrupt Evaluate Register (IEVAL) ...................................................................................
QDMA Event Register (QER) ..........................................................................................
QDMA Event Enable Register (QEER) ...............................................................................
QDMA Event Enable Clear Register (QEECR) ......................................................................
QDMA Event Enable Set Register (QEESR) .........................................................................
QDMA Secondary Event Register (QSER) ...........................................................................
QDMA Secondary Event Clear Register (QSECR) ..................................................................
Revision ID Register (REVID) ..........................................................................................
EDMA3TC Configuration Register (TCCFG) .........................................................................
EDMA3TC Channel Status Register (TCSTAT) .....................................................................
Error Status Register (ERRSTAT) .....................................................................................
Error Enable Register (ERREN) .......................................................................................
Error Clear Register (ERRCLR) ........................................................................................
Error Details Register (ERRDET) ......................................................................................
Error Interrupt Command Register (ERRCMD) ......................................................................
Read Command Rate Register (RDRATE) ...........................................................................
Source Active Options Register (SAOPT) ............................................................................
Source Active Source Address Register (SASRC) ..................................................................
Source Active Count Register (SACNT) ..............................................................................
Source Active Destination Address Register (SADST) .............................................................
18-56. QDMA Region Access Enable for Region m (QRAEm)
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
18-69.
18-70.
18-71.
18-72.
18-73.
18-74.
18-75.
18-76.
18-77.
18-78.
18-79.
18-80.
18-81.
18-82.
18-83.
18-84.
18-85.
18-86.
18-87.
18-88.
18-89.
18-90.
18-91.
18-92.
18-93.
18-94.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Figures
Copyright © 2011, Texas Instruments Incorporated
620
621
622
623
624
626
627
628
629
630
631
631
632
632
633
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18-95. Source Active B-Index Register (SABIDX) ........................................................................... 655
18-96. Source Active Memory Protection Proxy Register (SAMPPRXY) ................................................. 656
18-97. Source Active Count Reload Register (SACNTRLD)
...............................................................
657
18-98. Source Active Source Address B-Reference Register (SASRCBREF) ........................................... 657
18-99. Source Active Destination Address B-Reference Register (SADSTBREF) ...................................... 658
.....................................................
18-101. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) .................................
18-102. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) ............................
18-103. Destination FIFO Options Register n (DFOPTn) ...................................................................
18-104. Destination FIFO Source Address Register n (DFSRCn) .........................................................
18-105. Destination FIFO Count Register n (DFCNTn) .....................................................................
18-106. Destination FIFO Destination Address Register n (DFDSTn) ....................................................
18-107. Destination FIFO B-Index Register n (DFBIDXn) ..................................................................
18-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ........................................
19-1. EMAC and MDIO Block Diagram ......................................................................................
19-2. Ethernet Configuration—MII Connections ............................................................................
19-3. Ethernet Configuration—RMII Connections ..........................................................................
19-4. Ethernet Frame Format .................................................................................................
19-5. Basic Descriptor Format ................................................................................................
19-6. Typical Descriptor Linked List ..........................................................................................
19-7. Transmit Buffer Descriptor Format.....................................................................................
19-8. Receive Buffer Descriptor Format .....................................................................................
19-9. EMAC Control Module Block Diagram ................................................................................
19-10. MDIO Module Block Diagram ..........................................................................................
19-11. EMAC Module Block Diagram ..........................................................................................
19-12. EMAC Control Module Revision ID Register (REVID) ..............................................................
19-13. EMAC Control Module Software Reset Register (SOFTRESET)..................................................
19-14. EMAC Control Module Interrupt Control Register (INTCONTROL) ...............................................
18-100. Destination FIFO Set Count Reload Register (DFCNTRLD)
658
659
659
660
661
661
662
662
663
669
672
674
675
676
677
680
683
687
689
693
715
716
717
19-15. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 718
19-16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ..................... 719
19-17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ..................... 720
19-18. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ........... 721
19-19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) .................................................................................................. 722
19-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) ................... 723
19-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT)
..................
724
19-22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)......... 725
19-23. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ....... 726
19-24. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ....... 727
19-25. MDIO Revision ID Register (REVID) .................................................................................. 728
19-26. MDIO Control Register (CONTROL) .................................................................................. 729
730
19-28.
730
19-29.
19-30.
19-31.
19-32.
19-33.
32
.........................................................................
PHY Link Status Register (LINK) ......................................................................................
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) .....................................
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ....................................
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ...........................
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) .........................
19-27. PHY Acknowledge Status Register (ALIVE)
List of Figures
Copyright © 2011, Texas Instruments Incorporated
731
732
733
734
735
SPRUH78A – December 2011
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19-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................... 736
19-35. MDIO User Access Register 0 (USERACCESS0)................................................................... 737
19-36. MDIO User PHY Select Register 0 (USERPHYSEL0) .............................................................. 738
19-37. MDIO User Access Register 1 (USERACCESS1)................................................................... 739
19-38. MDIO User PHY Select Register 1 (USERPHYSEL1) .............................................................. 740
19-39. Transmit Revision ID Register (TXREVID) ........................................................................... 744
19-40. Transmit Control Register (TXCONTROL)
...........................................................................
744
19-41. Transmit Teardown Register (TXTEARDOWN)...................................................................... 745
19-42. Receive Revision ID Register (RXREVID) ............................................................................ 746
19-43. Receive Control Register (RXCONTROL) ............................................................................ 746
19-44. Receive Teardown Register (RXTEARDOWN) ...................................................................... 747
19-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .............................................. 748
19-46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ............................................ 749
19-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) .......................................................... 750
19-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .................................................... 751
19-49. MAC Input Vector Register (MACINVECTOR) ....................................................................... 752
19-50. MAC End Of Interrupt Vector Register (MACEOIVECTOR)
.......................................................
753
19-51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) .............................................. 754
19-52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)............................................. 755
19-53. Receive Interrupt Mask Set Register (RXINTMASKSET) .......................................................... 756
19-54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .................................................... 757
19-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 758
19-56. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .............................................. 758
19-57. MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................ 759
19-58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 759
19-59. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ..................... 760
19-60. Receive Unicast Enable Set Register (RXUNICASTSET).......................................................... 763
19-61. Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 764
19-62. Receive Maximum Length Register (RXMAXLEN) .................................................................. 765
19-63. Receive Buffer Offset Register (RXBUFFEROFFSET) ............................................................. 765
19-64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ............................. 766
19-65. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .................................... 766
19-66. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
...........................................
767
19-67. MAC Control Register (MACCONTROL) ............................................................................. 768
19-68. MAC Status Register (MACSTATUS) ................................................................................. 770
19-69. Emulation Control Register (EMCONTROL) ......................................................................... 772
19-70. FIFO Control Register (FIFOCONTROL) ............................................................................. 772
19-71. MAC Configuration Register (MACCONFIG) ......................................................................... 773
19-72. Soft Reset Register (SOFTRESET) ................................................................................... 773
19-73. MAC Source Address Low Bytes Register (MACSRCADDRLO) .................................................. 774
19-74. MAC Source Address High Bytes Register (MACSRCADDRHI) .................................................. 774
19-75. MAC Hash Address Register 1 (MACHASH1) ....................................................................... 775
19-76. MAC Hash Address Register 2 (MACHASH2) ....................................................................... 775
19-77. Back Off Random Number Generator Test Register (BOFFTEST) ............................................... 776
19-78. Transmit Pacing Algorithm Test Register (TPACETEST) .......................................................... 776
19-79. Receive Pause Timer Register (RXPAUSE) ......................................................................... 777
19-80. Transmit Pause Timer Register (TXPAUSE) ......................................................................... 777
19-81. MAC Address Low Bytes Register (MACADDRLO) ................................................................. 778
19-82. MAC Address High Bytes Register (MACADDRHI) ................................................................. 779
SPRUH78A – December 2011
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List of Figures
Copyright © 2011, Texas Instruments Incorporated
33
www.ti.com
779
19-84.
780
19-85.
19-86.
19-87.
19-88.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
34
....................................................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) .........................................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ..........................................
Transmit Channel n Completion Pointer Register (TXnCP) ........................................................
Receive Channel n Completion Pointer Register (RXnCP) ........................................................
Statistics Register ........................................................................................................
EMIFA Functional Block Diagram......................................................................................
Timing Waveform of SDRAM PRE Command .......................................................................
EMIFA to 2M × 16 × 4 bank SDRAM Interface ......................................................................
EMIFA to 512K × 16 × 2 bank SDRAM Interface ....................................................................
Timing Waveform for Basic SDRAM Read Operation ..............................................................
Timing Waveform for Basic SDRAM Write Operation...............................................................
EMIFA Asynchronous Interface ........................................................................................
EMIFA to 8-bit/16-bit Memory Interface ...............................................................................
Common Asynchronous Interface .....................................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode .............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode .....................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .....................................
EMIFA to NAND Flash Interface .......................................................................................
ECC Value for 8-Bit NAND Flash ......................................................................................
EMIFA Reset Block Diagram ...........................................................................................
EMIFA PSC Block Diagram ............................................................................................
Example Configuration Interface .......................................................................................
SDRAM Timing Register (SDTIMR) ...................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ...........................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
SDRAM Configuration Register (SDCR) ..............................................................................
Timing Waveform of an ASRAM Read ...............................................................................
Timing Waveform of an ASRAM Write ...............................................................................
Timing Waveform of an ASRAM Read with PCB Delays ...........................................................
Timing Waveform of an ASRAM Write with PCB Delays ...........................................................
Timing Waveform of a NAND Flash Read ...........................................................................
Timing Waveform of a NAND Flash Command Write ..............................................................
Timing Waveform of a NAND Flash Address Write ................................................................
Timing Waveform of a NAND Flash Data Write .....................................................................
Module ID Register (MIDR) .............................................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) ......................................................
SDRAM Configuration Register (SDCR) ..............................................................................
SDRAM Refresh Control Register (SDRCR) .........................................................................
Asynchronous n Configuration Register (CEnCFG) .................................................................
SDRAM Timing Register (SDTIMR) ...................................................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) ...........................................................
EMIFA Interrupt Raw Register (INTRAW) ............................................................................
EMIFA Interrupt Mask Register (INTMSK) ...........................................................................
EMIFA Interrupt Mask Set Register (INTMSKSET) .................................................................
EMIFA Interrupt Mask Clear Register (INTMSKCLR) ...............................................................
NAND Flash Control Register (NANDFCR) ..........................................................................
NAND Flash Status Register (NANDFSR) ...........................................................................
19-83. MAC Index Register (MACINDEX)
List of Figures
Copyright © 2011, Texas Instruments Incorporated
780
781
781
782
792
796
797
797
804
805
807
808
808
812
814
816
818
820
822
825
830
833
834
835
835
836
838
839
841
842
847
849
849
850
855
855
857
859
860
861
862
863
864
865
866
867
869
SPRUH78A – December 2011
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20-44. NAND Flash n ECC Register (NANDFnECC) ........................................................................ 870
20-45. NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD).................................................. 871
20-46. NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ............................................................. 872
20-47. NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ............................................................. 872
20-48. NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ............................................................. 873
20-49. NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) ............................................................. 873
20-50. NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) ............................................ 874
20-51. NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) ............................................ 874
20-52. NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ............................................... 875
20-53. NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ............................................... 875
21-1.
GPIO Block Diagram .................................................................................................... 879
21-2.
Revision ID Register (REVID) .......................................................................................... 888
21-3.
GPIO Interrupt Per-Bank Enable Register (BINTEN) ............................................................... 889
21-4.
GPIO Banks 0 and 1 Direction Register (DIR01) .................................................................... 890
21-5.
GPIO Banks 2 and 3 Direction Register (DIR23) .................................................................... 890
21-6.
GPIO Banks 4 and 5 Direction Register (DIR45) .................................................................... 890
21-7.
GPIO Banks 6 and 7 Direction Register (DIR67) .................................................................... 890
21-8.
GPIO Bank 8 Direction Register (DIR8)
21-9.
GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) ...................................................... 892
..............................................................................
891
21-10. GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) ...................................................... 892
21-11. GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) ...................................................... 892
21-12. GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) ...................................................... 892
21-13. GPIO Bank 8 Output Data Register (OUT_DATA8) ................................................................. 893
21-14. GPIO Banks 0 and 1 Set Data Register (SET_DATA01) ........................................................... 894
21-15. GPIO Banks 2 and 3 Set Data Register (SET_DATA23) ........................................................... 894
21-16. GPIO Banks 4 and 5 Set Data Register (SET_DATA45) ........................................................... 894
21-17. GPIO Banks 6 and 7 Set Data Register (SET_DATA67) ........................................................... 894
21-18. GPIO Bank 8 Set Data Register (SET_DATA8) ..................................................................... 895
21-19. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) ........................................................ 896
21-20. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) ........................................................ 896
21-21. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) ........................................................ 896
21-22. GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) ........................................................ 896
21-23. GPIO Bank 8 Clear Data Register (CLR_DATA8) ................................................................... 897
21-24. GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ........................................................... 898
21-25. GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ........................................................... 898
21-26. GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ........................................................... 898
21-27. GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ........................................................... 898
21-28. GPIO Bank 8 Input Data Register (IN_DATA8) ...................................................................... 899
............................................
GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............................................
GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................
GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ............................................
GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) .......................................................
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ..........................................
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) ..........................................
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ..........................................
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ..........................................
GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ....................................................
GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) ............................................
21-29. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01)
900
21-30.
900
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Figures
Copyright © 2011, Texas Instruments Incorporated
900
900
901
902
902
902
902
903
904
35
www.ti.com
21-40. GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ............................................ 904
21-41. GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ............................................ 904
21-42. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................................ 904
......................................................
GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) .........................................
GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) .........................................
GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) .........................................
GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .........................................
GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ....................................................
GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) .....................................................
GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) .....................................................
GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) .....................................................
GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) .....................................................
GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................................................................
I2C Peripheral Block Diagram ..........................................................................................
Multiple I2C Modules Connected ......................................................................................
Clocking Diagram for the I2C Peripheral .............................................................................
Synchronization of Two I2C Clock Generators During Arbitration.................................................
Bit Transfer on the I2C-Bus.............................................................................................
I2C Peripheral START and STOP Conditions .......................................................................
I2C Peripheral Data Transfer ...........................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) ...........................................
21-43. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8)
905
21-44.
906
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
906
906
906
907
908
908
908
908
909
913
914
915
916
917
917
918
918
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR) ........................................................................................................ 919
22-10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR) ............................................................. 919
22-11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR) ... 919
22-12. Arbitration Procedure Between Two Master-Transmitters .......................................................... 922
22-13. I2C Own Address Register (ICOAR) .................................................................................. 927
22-14. I2C Interrupt Mask Register (ICIMR) .................................................................................. 928
22-15. I2C Interrupt Status Register (ICSTR)
................................................................................
929
22-16. I2C Clock Low-Time Divider Register (ICCLKL) ..................................................................... 932
22-17. I2C Clock High-Time Divider Register (ICCLKH) .................................................................... 932
22-18. I2C Data Count Register (ICCNT) ..................................................................................... 933
22-19. I2C Data Receive Register (ICDRR) .................................................................................. 934
22-20. I2C Slave Address Register (ICSAR) ................................................................................. 935
22-21. I2C Data Transmit Register (ICDXR) .................................................................................. 936
22-22. I2C Mode Register (ICMDR)
...........................................................................................
937
22-23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ................................... 940
22-24. I2C Interrupt Vector Register (ICIVR) ................................................................................. 941
942
22-26. I2C Prescaler Register (ICPSC)
943
22-27.
944
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
36
.............................................................................
.......................................................................................
I2C Revision Identification Register 1 (REVID1) .....................................................................
I2C Revision Identification Register 2 (REVID2) .....................................................................
I2C DMA Control Register (ICDMAC) .................................................................................
I2C Pin Function Register (ICPFUNC) ................................................................................
I2C Pin Direction Register (ICPDIR) ..................................................................................
I2C Pin Data In Register (ICPDIN) ....................................................................................
I2C Pin Data Out Register (ICPDOUT) ...............................................................................
I2C Pin Data Set Register (ICPDSET) ................................................................................
22-25. I2C Extended Mode Register (ICEMDR)
List of Figures
Copyright © 2011, Texas Instruments Incorporated
944
945
946
947
948
949
950
SPRUH78A – December 2011
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............................................................................. 951
McASP Block Diagram .................................................................................................. 956
McASP to Parallel 2-Channel DACs .................................................................................. 957
McASP to 6-Channel DAC and 2-Channel DAC..................................................................... 957
McASP to Digital Amplifier .............................................................................................. 958
McASP as Digital Audio Encoder ..................................................................................... 958
TDM Format–6 Channel TDM Example .............................................................................. 959
TDM Format Bit Delays from Frame Sync ............................................................................ 960
Inter-IC Sound (I2S) Format ............................................................................................ 960
Biphase-Mark Code (BMC) ............................................................................................. 961
S/PDIF Subframe Format ............................................................................................... 962
S/PDIF Frame Format ................................................................................................... 963
Definition of Bit, Word, and Slot ........................................................................................ 964
Bit Order and Word Alignment Within a Slot Examples............................................................. 965
Definition of Frame and Frame Sync Width .......................................................................... 966
Transmit Clock Generator Block Diagram ............................................................................ 968
Receive Clock Generator Block Diagram ............................................................................. 969
Frame Sync Generator Block Diagram ............................................................................... 970
Individual Serializer and Connections Within McASP ............................................................... 971
Receive Format Unit ..................................................................................................... 972
Transmit Format Unit .................................................................................................... 973
McASP I/O Pin Control Block Diagram ............................................................................... 975
McASP I/O Pin to Control Register Mapping ......................................................................... 976
Burst Frame Sync Mode ................................................................................................ 981
Transmit DMA Event (AXEVT) Generation in TDM Time Slots .................................................... 984
DSP Service Time Upon Transmit DMA Event (AXEVT) ........................................................... 989
DSP Service Time Upon Receive DMA Event (AREVT) ........................................................... 990
DMA Events in an Audio Example–Two Events ..................................................................... 992
McASP Audio FIFO (AFIFO) Block Diagram ......................................................................... 993
Data Flow Through Transmit Format Unit ............................................................................ 996
Data Flow Through Receive Format Unit ............................................................................. 998
Audio Mute (AMUTE) Block Diagram ................................................................................ 1000
Transmit Clock Failure Detection Circuit Block Diagram .......................................................... 1004
Receive Clock Failure Detection Circuit Block Diagram........................................................... 1005
Serializers in Loopback Mode ........................................................................................ 1006
Revision Identification Register (REV) ............................................................................... 1012
Pin Function Register (PFUNC) ...................................................................................... 1012
Pin Direction Register (PDIR) ......................................................................................... 1014
Pin Data Output Register (PDOUT) .................................................................................. 1016
Pin Data Input Register (PDIN) ....................................................................................... 1018
Pin Data Set Register (PDSET) ...................................................................................... 1020
Pin Data Clear Register (PDCLR) .................................................................................... 1022
Global Control Register (GBLCTL) ................................................................................... 1024
Audio Mute Control Register (AMUTE) .............................................................................. 1026
Digital Loopback Control Register (DLBCTL) ....................................................................... 1028
Digital Mode Control Register (DITCTL) ............................................................................ 1029
Receiver Global Control Register (RGBLCTL) ..................................................................... 1030
Receive Format Unit Bit Mask Register (RMASK) ................................................................. 1031
Receive Bit Stream Format Register (RFMT) ...................................................................... 1032
22-35. I2C Pin Data Clear Register (ICPDCLR)
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
23-45.
23-46.
23-47.
23-48.
SPRUH78A – December 2011
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Copyright © 2011, Texas Instruments Incorporated
37
www.ti.com
23-49. Receive Frame Sync Control Register (AFSRCTL)................................................................ 1034
23-50. Receive Clock Control Register (ACLKRCTL) ...................................................................... 1035
23-51. Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................ 1036
23-52. Receive TDM Time Slot Register (RTDM) .......................................................................... 1037
23-53. Receiver Interrupt Control Register (RINTCTL) .................................................................... 1038
23-54. Receiver Status Register (RSTAT)................................................................................... 1039
23-55. Current Receive TDM Time Slot Registers (RSLOT) .............................................................. 1040
23-56. Receive Clock Check Control Register (RCLKCHK)
..............................................................
1041
23-57. Receiver DMA Event Control Register (REVTCTL)................................................................ 1042
1043
23-59. Transmit Format Unit Bit Mask Register (XMASK)
1044
23-60.
23-61.
23-62.
23-63.
23-64.
23-65.
23-66.
23-67.
23-68.
23-69.
23-70.
23-71.
23-72.
23-73.
23-74.
23-75.
23-76.
23-77.
23-78.
23-79.
23-80.
23-81.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
38
..................................................................
................................................................
Transmit Bit Stream Format Register (XFMT) ......................................................................
Transmit Frame Sync Control Register (AFSXCTL) ...............................................................
Transmit Clock Control Register (ACLKXCTL) .....................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ...............................................
Transmit TDM Time Slot Register (XTDM) .........................................................................
Transmitter Interrupt Control Register (XINTCTL) .................................................................
Transmitter Status Register (XSTAT) ................................................................................
Current Transmit TDM Time Slot Register (XSLOT) ..............................................................
Transmit Clock Check Control Register (XCLKCHK) ..............................................................
Transmitter DMA Event Control Register (XEVTCTL) .............................................................
Serializer Control Registers (SRCTLn) ..............................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .....................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ...................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ..............................................
Transmit Buffer Registers (XBUFn) ..................................................................................
Receive Buffer Registers (RBUFn)...................................................................................
AFIFO Revision Identification Register (AFIFOREV) ..............................................................
Write FIFO Control Register (WFIFOCTL) ..........................................................................
Write FIFO Status Register (WFIFOSTS) ...........................................................................
Read FIFO Control Register (RFIFOCTL) ..........................................................................
Read FIFO Status Register (RFIFOSTS) ...........................................................................
McBSP Block Diagram.................................................................................................
Clock and Frame Generation .........................................................................................
Transmit Data Clocking ................................................................................................
Receive Data Clocking.................................................................................................
Sample Rate Generator Block Diagram .............................................................................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ..........................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ..........................
Digital Loopback Mode ................................................................................................
Programmable Frame Period and Width ............................................................................
Dual-Phase Frame Example ..........................................................................................
Single-Phase Frame of Four 8-Bit Elements .......................................................................
Single-Phase Frame of One 32-Bit Element ........................................................................
Data Delay...............................................................................................................
2-Bit Data Delay Used to Discard Framing Bit .....................................................................
McBSP Standard Operation...........................................................................................
Receive Operation......................................................................................................
23-58. Transmitter Global Control Register (XGBLCTL)
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1045
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1057
1058
1058
1059
1059
1060
1061
1062
1063
1064
1067
1069
1070
1070
1071
1074
1074
1075
1077
1079
1080
1081
1081
1082
1083
1084
SPRUH78A – December 2011
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24-17. Transmit Operation ..................................................................................................... 1084
24-18. Maximum Frame Frequency for Transmit and Receive ........................................................... 1085
..........................................................
..........................................................
Maximum Frame Frequency Operation With 8-Bit Data ..........................................................
Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................................
Serial Port Receive Overrun ..........................................................................................
Serial Port Receive Overrun Avoided ................................................................................
Decision Tree Response to Receive Frame Synchronization Pulse.............................................
Unexpected Receive Frame Synchronization Pulse ...............................................................
Transmit With Data Overwrite ........................................................................................
Transmit Empty .........................................................................................................
Transmit Empty Avoided ..............................................................................................
Decision Tree Response to Transmit Frame Synchronization Pulse ............................................
Unexpected Transmit Frame Synchronization Pulse ..............................................................
McBSP Buffer FIFO (BFIFO) Block Diagram .......................................................................
Companding Flow ......................................................................................................
Companding Data Formats ...........................................................................................
Transmit Data Companding Format in DXR ........................................................................
Companding of Internal Data .........................................................................................
DX Timing for Multichannel Operation ...............................................................................
Alternating Between the Channels of Partition A and the Channels of Partition B ............................
Reassigning Channel Blocks Throughout a McBSP Data Transfer .............................................
McBSP Data Transfer in the 8-Partition Mode .....................................................................
Activity on McBSP Pins for the Possible Values of XMCM .......................................................
Data Receive Register (DRR) ........................................................................................
Data Transmit Register (DXR) ........................................................................................
Serial Port Control Register (SPCR) .................................................................................
Receive Control Register (RCR) .....................................................................................
Transmit Control Register (XCR) .....................................................................................
Sample Rate Generator Register (SRGR) ..........................................................................
Multichannel Control Registers (MCR) ..............................................................................
Enhanced Receive Channel Enable Register n (RCEREn) ......................................................
Enhanced Transmit Channel Enable Register n (XCEREn) ......................................................
Pin Control Register (PCR) ...........................................................................................
BFIFO Revision Identification Register (BFIFOREV) ..............................................................
Write FIFO Control Register (WFIFOCTL) ..........................................................................
Write FIFO Status Register (WFIFOSTS) ...........................................................................
Read FIFO Control Register (RFIFOCTL) ..........................................................................
Read FIFO Status Register (RFIFOSTS) ...........................................................................
MMC/SD Card Controller Block Diagram ...........................................................................
MMC/SD Controller Interface Diagram ..............................................................................
MMC Configuration and SD Configuration Diagram ...............................................................
MMC/SD Controller Clocking Diagram ..............................................................................
MMC/SD Mode Write Sequence Timing Diagram .................................................................
MMC/SD Mode Read Sequence Timing Diagram .................................................................
FIFO Operation Diagram ..............................................................................................
Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA .....................................
FIFO Operation During Card Read Diagram .......................................................................
24-19. Unexpected Frame Synchronization With (R/X)FIG = 0
1086
24-20. Unexpected Frame Synchronization With (R/X)FIG = 1
1087
24-21.
1087
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
24-52.
24-53.
24-54.
24-55.
24-56.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1088
1089
1089
1090
1091
1091
1092
1092
1094
1094
1095
1097
1097
1097
1098
1100
1102
1102
1103
1106
1116
1116
1117
1119
1121
1123
1124
1128
1130
1132
1134
1135
1136
1137
1138
1140
1141
1142
1143
1144
1145
1146
1147
1149
39
www.ti.com
25-10. FIFO Operation During Card Write Diagram ........................................................................ 1151
25-11. MMC Card Identification Procedure .................................................................................. 1158
25-12. SD Card Identification Procedure
....................................................................................
1159
25-13. MMC/SD Mode Single-Block Write Operation ...................................................................... 1161
25-14. MMC/SD Mode Single-Block Read Operation ...................................................................... 1163
25-15. MMC/SD Multiple-Block Write Operation ............................................................................ 1165
25-16. MMC/SD Mode Multiple-Block Read Operation .................................................................... 1167
25-17. MMC Control Register (MMCCTL) ................................................................................... 1170
25-18. MMC Memory Clock Control Register (MMCCLK) ................................................................. 1171
25-19. MMC Status Register 0 (MMCST0) .................................................................................. 1172
25-20. MMC Status Register 1 (MMCST1) .................................................................................. 1174
25-21. MMC Interrupt Mask Register (MMCIM)............................................................................. 1175
25-22. MMC Response Time-Out Register (MMCTOR) ................................................................... 1177
25-23. MMC Data Read Time-Out Register (MMCTOD) .................................................................. 1178
25-24. MMC Block Length Register (MMCBLEN) .......................................................................... 1179
1180
25-26.
1180
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
40
....................................................................
MMC Number of Blocks Counter Register (MMCNBLC) ..........................................................
MMC Data Receive Register (MMCDRR) ...........................................................................
MMC Data Transmit Register (MMCDXR) ..........................................................................
MMC Command Register (MMCCMD) ..............................................................................
Command Format ......................................................................................................
MMC Argument Register (MMCARGHL) ............................................................................
MMC Response Register 0 and 1 (MMCRSP01) ..................................................................
MMC Response Register 2 and 3 (MMCRSP23) ..................................................................
MMC Response Register 4 and 5 (MMCRSP45) ..................................................................
MMC Response Register 6 and 7 (MMCRSP67) ..................................................................
MMC Data Response Register (MMCDRSP) .......................................................................
MMC Command Index Register (MMCCIDX).......................................................................
SDIO Control Register (SDIOCTL) ...................................................................................
SDIO Status Register 0 (SDIOST0)..................................................................................
SDIO Interrupt Enable Register (SDIOIEN) .........................................................................
SDIO Interrupt Status Register (SDIOIST) ..........................................................................
MMC FIFO Control Register (MMCFIFOCTL) ......................................................................
Real-Time Clock Block Diagram......................................................................................
32-kHz Oscillator Counter Compensation ...........................................................................
Kick State Machine .....................................................................................................
Second Register (SECOND) ..........................................................................................
Minute Register (MINUTE) ............................................................................................
Hour Register (HOUR) .................................................................................................
Days Register (DAY) ...................................................................................................
Month Register (MONTH) .............................................................................................
Year Register (YEAR) .................................................................................................
Day of the Week Register (DOTW) ..................................................................................
Alarm Second Register (ALARMSECOND) .........................................................................
Alarm Minute Register (ALARMMINUTE) ...........................................................................
Alarm Hour Register (ALARMHOUR)................................................................................
Alarm Day Register (ALARMDAY) ...................................................................................
Alarm Month Register (ALARMMONTH) ............................................................................
Alarm Year Register (ALARMYEAR) ................................................................................
25-25. MMC Number of Blocks Register (MMCNBLK)
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1181
1181
1182
1183
1184
1185
1185
1185
1185
1187
1187
1188
1189
1190
1190
1191
1194
1198
1199
1202
1202
1203
1204
1204
1205
1205
1206
1206
1207
1208
1209
1209
SPRUH78A – December 2011
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www.ti.com
26-17. Control Register (CTRL) ............................................................................................... 1210
26-18. Status Register (STATUS) ............................................................................................ 1211
26-19. Interrupt Register (INTERRUPT) ..................................................................................... 1212
26-20. Compensation (LSB) Register (COMPLSB) ........................................................................ 1213
26-21. Compensation (MSB) Register (COMPMSB) ....................................................................... 1214
.............................................................................................
Scratch Registers (SCRATCHn) .....................................................................................
Kick Registers (KICKnR) ..............................................................................................
SPI Block Diagram .....................................................................................................
SPI 3-Pin Option ........................................................................................................
SPI 4-Pin Option with SPIx_SCS[n] .................................................................................
SPI 4-Pin Option with SPIx_ENA ....................................................................................
SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ..............................................................
Format for Transmitting 12-Bit Word .................................................................................
Format for 10-Bit Received Word ....................................................................................
Clock Mode with POLARITY = 0 and PHASE = 0 .................................................................
Clock Mode with POLARITY = 0 and PHASE = 1 .................................................................
Clock Mode with POLARITY = 1 and PHASE = 0 .................................................................
Clock Mode with POLARITY = 1 and PHASE = 1 .................................................................
Five Bits per Character (5-Pin Option)...............................................................................
SPI 3-Pin Master Mode with WDELAY ..............................................................................
SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY, WDELAY, and C2TDELAY .............................
SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY ...................................
SPI 5-Pin Mode Demonstrating T2CDELAY, T2EDELAY, and WDELAY ......................................
SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ....................................................
SPI Global Control Register 0 (SPIGCR0) ..........................................................................
SPI Global Control Register 1 (SPIGCR1) ..........................................................................
SPI Interrupt Register (SPIINT0) .....................................................................................
SPI Interrupt Level Register (SPILVL) ...............................................................................
SPI Flag Register (SPIFLG) ..........................................................................................
SPI Pin Control Register 0 (SPIPC0) ................................................................................
SPI Pin Control Register 1 (SPIPC1) ................................................................................
SPI Pin Control Register 2 (SPIPC2) ................................................................................
SPI Pin Control Register 3 (SPIPC3) ................................................................................
SPI Pin Control Register 4 (SPIPC4) ................................................................................
SPI Pin Control Register 5 (SPIPC5) ................................................................................
SPI Data Register 0 (SPIDAT0) ......................................................................................
SPI Data Register 1 (SPIDAT1) ......................................................................................
SPI Buffer Register (SPIBUF) ........................................................................................
SPI Emulation Register (SPIEMU) ...................................................................................
SPI Delay Register (SPIDELAY) .....................................................................................
Example: tC2TDELAY = 8 SPI Module Clock Cycles ...................................................................
Example: tT2CDELAY = 4 SPI Module Clock Cycles ...................................................................
Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ..........................................................
Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout ..........................................................
SPI Default Chip Select Register (SPIDEF) ........................................................................
SPI Data Format Register (SPIFMTn) ...............................................................................
SPI Interrupt Vector Register 1 (INTVEC1) .........................................................................
Timer Block Diagram ...................................................................................................
26-22. Oscillator Register (OSC)
26-23.
26-24.
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
27-28.
27-29.
27-30.
27-31.
27-32.
27-33.
27-34.
27-35.
27-36.
27-37.
27-38.
27-39.
27-40.
28-1.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1215
1216
1216
1219
1225
1227
1229
1231
1232
1232
1233
1234
1234
1234
1235
1240
1241
1242
1244
1245
1246
1247
1249
1251
1252
1254
1255
1256
1257
1258
1259
1260
1261
1262
1264
1265
1266
1267
1267
1267
1268
1269
1271
1275
41
www.ti.com
28-2.
Timer Clock Source Block Diagram .................................................................................. 1276
28-3.
64-Bit Timer Mode Block Diagram ................................................................................... 1277
28-4.
Dual 32-Bit Timers Chained Mode Block Diagram ................................................................. 1280
28-5.
Dual 32-Bit Timers Chained Mode Example ........................................................................ 1280
28-6.
Dual 32-Bit Timers Unchained Mode Block Diagram .............................................................. 1282
28-7.
Dual 32-Bit Timers Unchained Mode Example ..................................................................... 1283
28-8.
32-Bit Timer Counter Overflow Example ............................................................................ 1286
28-9.
Watchdog Timer Mode Block Diagram .............................................................................. 1288
.........................................................................
Timer Operation in Pulse Mode (CPn = 0) ..........................................................................
Timer Operation in Clock Mode (CPn = 1) ..........................................................................
Revision ID Register (REVID) ........................................................................................
Emulation Management Register (EMUMGT) ......................................................................
GPIO Interrupt Control and Enable Register (GPINTGPEN) .....................................................
GPIO Data and Direction Register (GPDATGPDIR) ...............................................................
Timer Counter Register 12 (TIM12) ..................................................................................
Timer Counter Register 34 (TIM34) ..................................................................................
Timer Period Register 12 (PRD12) ..................................................................................
Timer Period Register 34 (PRD34) ..................................................................................
Timer Control Register (TCR).........................................................................................
Timer Global Control Register (TGCR) ..............................................................................
Watchdog Timer Control Register (WDTCR) .......................................................................
Timer Reload Register 12 (REL12) ..................................................................................
Timer Reload Register 34 (REL34) ..................................................................................
Timer Capture Register 12 (CAP12) .................................................................................
Timer Capture Register 34 (CAP34) .................................................................................
Timer Interrupt Control and Status Register (INTCTLSTAT) .....................................................
Timer Compare Register (CMPn) ....................................................................................
UART Block Diagram ..................................................................................................
UART Clock Generation Diagram ....................................................................................
Relationships Between Data Bit, BCLK, and UART Input Clock .................................................
UART Protocol Formats ...............................................................................................
UART Interface Using Autoflow Diagram ...........................................................................
Autoflow Functional Timing Waveforms for UARTn_RTS ........................................................
Autoflow Functional Timing Waveforms for UARTn_CTS ........................................................
UART Interrupt Request Enable Paths ..............................................................................
Receiver Buffer Register (RBR) ......................................................................................
Transmitter Holding Register (THR) .................................................................................
Interrupt Enable Register (IER) .......................................................................................
Interrupt Identification Register (IIR) .................................................................................
FIFO Control Register (FCR) .........................................................................................
Line Control Register (LCR) ..........................................................................................
Modem Control Register (MCR) ......................................................................................
Line Status Register (LSR) ............................................................................................
Modem Status Register (MSR) .......................................................................................
Scratch Pad Register (SCR) ..........................................................................................
Divisor LSB Latch (DLL) ...............................................................................................
Divisor MSB Latch (DLH) ..............................................................................................
Revision Identification Register 1 (REVID1) ........................................................................
28-10. Watchdog Timer Operation State Diagram
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
28-26.
28-27.
28-28.
28-29.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
42
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1288
1290
1290
1293
1293
1294
1295
1296
1296
1297
1297
1298
1300
1301
1302
1302
1303
1303
1304
1305
1309
1310
1311
1313
1316
1317
1317
1319
1322
1323
1324
1325
1327
1328
1330
1331
1334
1335
1336
1336
1337
SPRUH78A – December 2011
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29-22. Revision Identification Register 2 (REVID2) ........................................................................ 1337
29-23. Power and Emulation Management Register (PWREMU_MGMT) .............................................. 1338
29-24. Mode Definition Register (MDR)...................................................................................... 1339
30-1.
Functional Block Diagram ............................................................................................. 1342
30-2.
USB Clocking Diagram ................................................................................................ 1343
30-3.
Interrupt Service Routine Flow Chart ................................................................................ 1347
30-4.
CPU Actions at Transfer Phases ..................................................................................... 1352
30-5.
Sequence of Transfer .................................................................................................. 1352
30-6.
Service Endpoint 0 Flow Chart ....................................................................................... 1354
30-7.
IDLE Mode Flow Chart
30-8.
TX Mode Flow Chart ................................................................................................... 1356
30-9.
RX Mode Flow Chart ................................................................................................... 1357
................................................................................................
1355
30-10. Setup Phase of a Control Transaction Flow Chart ................................................................. 1367
............................................................................................
OUT Data Phase Flow Chart .........................................................................................
Completion of SETUP or OUT Data Phase Flow Chart ...........................................................
Completion of IN Data Phase Flow Chart ...........................................................................
USB Controller Block Diagram .......................................................................................
Host Packet Descriptor Layout .......................................................................................
Host Buffer Descriptor Layout ........................................................................................
Teardown Descriptor Layout ..........................................................................................
Relationship Between Memory Regions and Linking RAM .......................................................
High-Level Transmit and Receive Data Transfer Example .......................................................
Transmit Descriptors and Queue Status Configuration ...........................................................
Transmit USB Data Flow Example (Initialization) ..................................................................
Transmit USB Data Flow Example (Completion)...................................................................
Receive Descriptors and Queue Status Configuration ............................................................
Receive USB Data Flow Example (Initialization) ...................................................................
Receive USB Data Flow Example (Completion) ...................................................................
Revision Identification Register (REVID) ............................................................................
Control Register (CTRLR) .............................................................................................
Status Register (STATR) ..............................................................................................
Emulation Register (EMUR)...........................................................................................
Mode Register (MODE) ................................................................................................
Auto Request Register (AUTOREQ) .................................................................................
SRP Fix Time Register (SRPFIXTIME)..............................................................................
Teardown Register (TEARDOWN) ...................................................................................
USB Interrupt Source Register (INTSRCR) .........................................................................
USB Interrupt Source Set Register (INTSETR) ....................................................................
USB Interrupt Source Clear Register (INTCLRR) ..................................................................
USB Interrupt Mask Register (INTMSKR) ...........................................................................
USB Interrupt Mask Set Register (INTMSKSETR) .................................................................
USB Interrupt Mask Clear Register (INTMSKCLRR) ..............................................................
USB Interrupt Source Masked Register (INTMASKEDR) .........................................................
USB End of Interrupt Register (EOIR) ...............................................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) .............................................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) .............................................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) .............................................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) .............................................................
30-11. IN Data Phase Flow Chart
1369
30-12.
1371
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
30-34.
30-35.
30-36.
30-37.
30-38.
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1373
1375
1382
1385
1388
1390
1393
1399
1400
1401
1402
1403
1403
1404
1428
1428
1429
1429
1430
1432
1433
1433
1434
1435
1436
1437
1438
1439
1440
1441
1441
1442
1442
1443
43
www.ti.com
30-47. Function Address Register (FADDR) ................................................................................ 1443
30-48. Power Management Register (POWER) ............................................................................ 1444
30-49. Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ........................................... 1445
.......................................................
Interrupt Enable Register for INTRTX (INTRTXE) .................................................................
Interrupt Enable Register for INTRRX (INTRRXE) .................................................................
Interrupt Register for Common USB Interrupts (INTRUSB) ......................................................
Interrupt Enable Register for INTRUSB (INTRUSBE) .............................................................
Frame Number Register (FRAME) ...................................................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................
Register to Enable the USB 2.0 Test Modes (TESTMODE) ......................................................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) .....................................
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) .....................................
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ...........................................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR).....................................
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ..........................................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ......................................
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .....................................
Control Status Register for Host Receive Endpoint (HOST_RXCSR)...........................................
Count 0 Register (COUNT0) ..........................................................................................
Receive Count Register (RXCOUNT) ...............................................................................
Type Register (Host mode only) (HOST_TYPE0) .................................................................
Transmit Type Register (Host mode only) (HOST_TXTYPE) ....................................................
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .....................................................
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ...........................................
Receive Type Register (Host mode only) (HOST_RXTYPE) .....................................................
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ............................................
Configuration Data Register (CONFIGDATA) ......................................................................
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ....................................................
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ....................................................
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ....................................................
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ....................................................
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ....................................................
Device Control Register (DEVCTL) ..................................................................................
Transmit Endpoint FIFO Size (TXFIFOSZ) .........................................................................
Receive Endpoint FIFO Size (RXFIFOSZ) ..........................................................................
Transmit Endpoint FIFO Address (TXFIFOADDR).................................................................
Receive Endpoint FIFO Address (RXFIFOADDR) .................................................................
Hardware Version Register (HWVERS) .............................................................................
Transmit Function Address (TXFUNCADDR) ......................................................................
Transmit Hub Address (TXHUBADDR) ..............................................................................
Transmit Hub Port (TXHUBPORT) ...................................................................................
Receive Function Address (RXFUNCADDR) .......................................................................
Receive Hub Address (RXHUBADDR) ..............................................................................
Receive Hub Port (RXHUBPORT) ...................................................................................
CDMA Revision Identification Register (DMAREVID) .............................................................
CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)...........................................
CDMA Emulation Control Register (DMAEMU) ....................................................................
CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) .......................................
30-50. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
30-66.
30-67.
30-68.
30-69.
30-70.
30-71.
30-72.
30-73.
30-74.
30-75.
30-76.
30-77.
30-78.
30-79.
30-80.
30-81.
30-82.
30-83.
30-84.
30-85.
30-86.
30-87.
30-88.
30-89.
30-90.
30-91.
30-92.
30-93.
30-94.
30-95.
44
List of Figures
Copyright © 2011, Texas Instruments Incorporated
1446
1447
1447
1448
1449
1449
1450
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1459
1460
1460
1461
1461
1462
1463
1464
1465
1465
1466
1466
1467
1467
1468
1468
1469
1469
1470
1471
1471
1471
1472
1472
1472
1473
1473
1474
1474
SPRUH78A – December 2011
Submit Documentation Feedback
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30-96. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ....................................... 1475
30-97. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ................................... 1476
30-98. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) ................................... 1477
30-99. CDMA Scheduler Control Register (DMA_SCHED_CTRL) ....................................................... 1478
30-100. CDMA Scheduler Table Word n Registers (WORD[n]) .......................................................... 1478
30-101. Queue Manager Revision Identification Register (QMGRREVID) .............................................. 1480
30-102. Queue Manager Queue Diversion Register (DIVERSION) ...................................................... 1480
30-103. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ............................ 1481
30-104. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ............................ 1482
30-105. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ............................ 1483
30-106. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ............................ 1484
30-107. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ............................ 1484
30-108. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ......................................... 1485
30-109. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ............................ 1485
30-110. Queue Manager Queue Pending Register 0 (PEND0) ........................................................... 1486
30-111. Queue Manager Queue Pending Register 1 (PEND1) ........................................................... 1486
30-112. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) ........................... 1487
30-113. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ................................... 1488
30-114. Queue Manager Queue N Control Register D (CTRLD[N]) ..................................................... 1489
30-115. Queue Manager Queue N Status Register A (QSTATA[N])..................................................... 1490
30-116. Queue Manager Queue N Status Register B (QSTATB[N])..................................................... 1490
30-117. Queue Manager Queue N Status Register C (QSTATC[N]) .................................................... 1491
SPRUH78A – December 2011
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List of Figures
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45
www.ti.com
List of Tables
2-1.
Exception Vector Table for ARM ........................................................................................ 76
2-2.
.............................................................................. 78
DSP Interrupt Map ........................................................................................................ 83
OMAP-L132 Applications Processor System Interconnect Matrix .................................................. 90
MPU Memory Regions .................................................................................................... 99
MPU Default Configuration ............................................................................................... 99
Device Master Settings .................................................................................................. 100
Request Type Access Controls ........................................................................................ 101
MPU_BOOTCFG_ERR Interrupt Sources ............................................................................ 103
Memory Protection Unit 1 (MPU1) Registers......................................................................... 104
Memory Protection Unit 2 (MPU2) Registers......................................................................... 104
Revision ID Register (REVID) Field Descriptions .................................................................... 106
Configuration Register (CONFIG) Field Descriptions ............................................................... 106
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions .............................................. 107
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ........................................... 108
Interrupt Enable Set Register (IENSET) Field Descriptions ........................................................ 109
Interrupt Enable Clear Register (IENCLR) Field Descriptions ..................................................... 109
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ................. 111
MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ............... 112
MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ............... 112
MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions ................ 113
MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions ................ 113
Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions .. 114
Fault Address Register (FLTADDRR) Field Descriptions ........................................................... 115
Fault Status Register (FLTSTAT) Field Descriptions................................................................ 116
Fault Clear Register (FLTCLR) Field Descriptions .................................................................. 117
Device Clock Inputs ..................................................................................................... 120
System Clock Domains ................................................................................................. 120
Example PLL Frequencies ............................................................................................. 123
USB Clock Multiplexing Options ....................................................................................... 123
EMAC Reference Clock Frequencies ................................................................................. 127
Peripherals ................................................................................................................ 128
System PLLC Output Clocks ........................................................................................... 132
PLL Controller 0 (PLLC0) Registers ................................................................................... 135
PLL Controller 1 (PLLC1) Registers ................................................................................... 136
PLLC0 Revision Identification Register (REVID) Field Descriptions .............................................. 136
PLLC1 Revision Identification Register (REVID) Field Descriptions .............................................. 137
Reset Type Status Register (RSTYPE) Field Descriptions......................................................... 137
Reset Control Register (RSCTRL) Field Descriptions .............................................................. 138
PLLC0 Control Register (PLLCTL) Field Descriptions .............................................................. 139
PLLC1 Control Register (PLLCTL) Field Descriptions .............................................................. 140
PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions .................................................... 141
PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions .................................................... 142
PLL Multiplier Control Register (PLLM) Field Descriptions ......................................................... 143
PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................ 143
PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions ........................................................... 144
PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ........................................................... 144
3-1.
4-1.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
46
Different Address Types in ARM System
List of Tables
Copyright © 2011, Texas Instruments Incorporated
SPRUH78A – December 2011
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8-16.
PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions ........................................................... 145
8-17.
PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ........................................................... 145
8-18.
PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ........................................................... 146
8-19.
PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ........................................................... 146
8-20.
PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ........................................................... 147
8-21.
PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ........................................................... 147
8-22.
PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ........................................................... 148
8-23.
PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ........................................................... 148
8-24.
PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................ 149
8-25.
PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................ 149
8-26.
PLL Post-Divider Control Register (POSTDIV) Field Descriptions ................................................ 150
8-27.
PLL Controller Command Register (PLLCMD) Field Descriptions ................................................ 150
8-28.
PLL Controller Status Register (PLLSTAT) Field Descriptions .................................................... 151
8-29.
PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ............................................... 152
8-30.
PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ............................................... 153
8-31.
PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ................................ 154
8-32.
PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ................................ 155
8-33.
PLLC0 Clock Enable Control Register (CKEN) Field Descriptions ................................................ 156
8-34.
PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ................................................ 156
8-35.
PLLC0 Clock Status Register (CKSTAT) Field Descriptions ....................................................... 157
8-36.
PLLC1 Clock Status Register (CKSTAT) Field Descriptions ....................................................... 158
8-37.
PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ................................................... 159
8-38.
PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ................................................... 160
8-39.
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions .................................... 161
8-40.
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions .................................... 161
9-1.
PSC0 Default Module Configuration................................................................................... 165
9-2.
PSC1 Default Module Configuration................................................................................... 165
9-3.
Module States ............................................................................................................ 168
9-4.
IcePick Emulation Commands
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
.........................................................................................
PSC Interrupt Events ....................................................................................................
Power and Sleep Controller 0 (PSC0) Registers ....................................................................
Power and Sleep Controller 1 (PSC1) Registers ....................................................................
Revision Identification Register (REVID) Field Descriptions .......................................................
Interrupt Evaluation Register (INTEVAL) Field Descriptions .......................................................
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions ........................................
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ...........................................
Power Error Pending Register (PERRPR) Field Descriptions .....................................................
Power Error Clear Register (PERRCR) Field Descriptions .........................................................
Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................
Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................
Power Domain 0 Status Register (PDSTAT0) Field Descriptions .................................................
Power Domain 1 Status Register (PDSTAT1) Field Descriptions .................................................
Power Domain 0 Control Register (PDCTL0) Field Descriptions ..................................................
Power Domain 1 Control Register (PDCTL1) Field Descriptions ..................................................
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions ..........................................
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ..........................................
Module Status n Register (MDSTATn) Field Descriptions .........................................................
PSC0 Module Control n Register (MDCTLn) Field Descriptions ..................................................
PSC1 Module Control n Register (MDCTLn) Field Descriptions ..................................................
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List of Tables
Copyright © 2011, Texas Instruments Incorporated
170
170
173
173
174
174
175
176
177
177
178
179
180
181
182
183
184
185
186
187
188
47
www.ti.com
10-1.
Power Management Features .......................................................................................... 191
11-1.
Master IDs
11-2.
Default Master Priority ................................................................................................... 210
11-3.
System Configuration Module 0 (SYSCFG0) Registers ............................................................ 211
11-4.
System Configuration Module 1 (SYSCFG1) Registers ............................................................ 212
11-5.
Revision Identification Register (REVID) Field Descriptions ....................................................... 212
11-6.
Device Identification Register 0 (DEVIDR0) Field Descriptions
11-7.
Boot Configuration Register (BOOTCFG) Field Descriptions ...................................................... 213
11-8.
Kick 0 Register (KICK0R) Field Descriptions......................................................................... 214
11-9.
Kick 1 Register (KICK1R) Field Descriptions......................................................................... 214
................................................................................................................
...................................................
209
213
11-10. Host 0 Configuration Register (HOST0CFG) Field Descriptions .................................................. 215
11-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions .................................................. 216
11-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions .............................................. 217
218
11-14.
219
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
11-46.
11-47.
11-48.
48
...........................................
Interrupt Enable Register (IENSET) Field Descriptions .............................................................
Interrupt Enable Clear Register (IENCLR) Field Descriptions .....................................................
End of Interrupt Register (EOI) Field Descriptions ..................................................................
Fault Address Register (FLTADDRR) Field Descriptions ...........................................................
Fault Status Register (FLTSTAT) Field Descriptions................................................................
Master Priority 0 Register (MSTPRI0) Field Descriptions ..........................................................
Master Priority 1 Register (MSTPRI1) Field Descriptions ..........................................................
Master Priority 2 Register (MSTPRI2) Field Descriptions ..........................................................
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ...............................................
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ...............................................
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ...............................................
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ...............................................
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ...............................................
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ...............................................
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ...............................................
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ...............................................
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ...............................................
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ...............................................
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions ............................................
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions ............................................
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions ............................................
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions ............................................
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions ............................................
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions ............................................
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions ............................................
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions ............................................
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions ............................................
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions ............................................
Suspend Source Register (SUSPSRC) Field Descriptions .........................................................
Chip Signal Register (CHIPSIG) Field Descriptions .................................................................
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ...................................................
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ...................................................
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ...................................................
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ...................................................
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ...................................................
11-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
219
220
220
221
222
223
224
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
263
265
267
268
269
271
273
275
SPRUH78A – December 2011
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...................................................
VTP I/O Control Register (VTPIO_CTL) Field Descriptions ........................................................
DDR Slew Register (DDR_SLEW) Field Descriptions ..............................................................
Deep Sleep Register (DEEPSLEEP) Field Descriptions ...........................................................
Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions ...............................................
Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ................................................
Pullup/Pulldown Select Register (PUPD_SEL) Default Values ....................................................
RXACTIVE Control Register (RXACTIVE) Field Descriptions .....................................................
AINTC System Interrupt Assignments ................................................................................
ARM Interrupt Controller (AINTC) Registers .........................................................................
Revision Identification Register (REVID) Field Descriptions .......................................................
Control Register (CR) Field Descriptions .............................................................................
Global Enable Register (GER) Field Descriptions ...................................................................
Global Nesting Level Register (GNLR) Field Descriptions .........................................................
System Interrupt Status Indexed Set Register (SISR) Field Descriptions ........................................
System Interrupt Status Indexed Clear Register (SICR) Field Descriptions .....................................
System Interrupt Enable Indexed Set Register (EISR) Field Descriptions .......................................
System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions.....................................
Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions.........................................
Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions .....................................
Vector Base Register (VBR) Field Descriptions .....................................................................
Vector Size Register (VSR) Field Descriptions ......................................................................
Vector Null Register (VNR) Field Descriptions .......................................................................
Global Prioritized Index Register (GPIR) Field Descriptions .......................................................
Global Prioritized Vector Register (GPVR) Field Descriptions .....................................................
System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions .......................................
System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions .......................................
System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions .......................................
System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions .......................................
System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions ................................
System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions ................................
System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions ................................
System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions ................................
System Interrupt Enable Set Register 1 (ESR1) Field Descriptions ..............................................
System Interrupt Enable Set Register 2 (ESR2) Field Descriptions ..............................................
System Interrupt Enable Set Register 3 (ESR3) Field Descriptions ..............................................
System Interrupt Enable Set Register 4 (ESR4) Field Descriptions ..............................................
System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions ............................................
System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions ............................................
System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions ............................................
System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions ............................................
Channel Map Registers (CMRn) Field Descriptions .................................................................
Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions ..........................................
Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions ..........................................
Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ............................................
Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions ............................................
Host Interrupt Enable Register (HIER) Field Descriptions ..........................................................
Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ........................................
Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions ........................................
11-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
11-50.
11-51.
11-52.
11-53.
11-54.
11-55.
11-56.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
SPRUH78A – December 2011
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List of Tables
Copyright © 2011, Texas Instruments Incorporated
276
277
279
280
281
281
282
283
287
293
294
295
296
296
297
297
298
298
299
299
300
300
301
301
302
302
303
303
304
304
305
305
306
306
307
307
308
308
309
309
310
310
311
311
312
312
313
314
314
49
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15-1.
DDR2/mDDR Memory Controller Signal Descriptions .............................................................. 326
15-2.
DDR2/mDDR SDRAM Commands .................................................................................... 326
15-3.
Truth Table for DDR2/mDDR SDRAM Commands
15-4.
Addressable Memory Ranges .......................................................................................... 334
15-5.
Configuration Register Fields for Address Mapping ................................................................. 335
15-6.
Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM ..................................... 336
15-7.
Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) .................................................. 338
15-8.
DDR2/mDDR Memory Controller FIFO Description ................................................................. 340
15-9.
Refresh Urgency Levels................................................................................................. 343
.................................................................
15-10. Configuration Bit Field for Partial Array Self-refresh
................................................................
327
344
15-11. Reset Sources ............................................................................................................ 345
15-12. DDR2 SDRAM Configuration by MRS Command ................................................................... 347
15-13. DDR2 SDRAM Configuration by EMRS(1) Command .............................................................. 347
15-14. Mobile DDR SDRAM Configuration by MRS Command ............................................................ 347
15-15. Mobile DDR SDRAM Configuration by EMRS(1) Command ....................................................... 348
15-16. SDCR Configuration ..................................................................................................... 353
15-17. DDR2 Memory Refresh Specification
................................................................................
354
15-18. SDRCR Configuration ................................................................................................... 354
15-19. SDTIMR1 Configuration ................................................................................................. 355
15-20. SDTIMR2 Configuration ................................................................................................. 355
15-21. DRPYC1R Configuration ................................................................................................ 356
15-22. DDR2/mDDR Memory Controller Registers .......................................................................... 357
15-23. Revision ID Register (REVID) Field Descriptions .................................................................... 357
15-24. SDRAM Status Register (SDRSTAT) Field Descriptions ........................................................... 358
15-25. SDRAM Configuration Register (SDCR) Field Descriptions
.......................................................
359
15-26. SDRAM Refresh Control Register (SDRCR) Field Descriptions ................................................... 362
15-27. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ......................................................... 363
15-28. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ......................................................... 364
15-29. SDRAM Configuration Register 2 (SDCR2) Field Descriptions .................................................... 365
15-30. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
..............................................
366
15-31. Performance Counter 1 Register (PC1) Field Descriptions ........................................................ 367
15-32. Performance Counter 2 Register (PC2) Field Descriptions ........................................................ 367
15-33. Performance Counter Configuration Register (PCC) Field Descriptions ......................................... 368
15-34. Performance Counter Filter Configuration ............................................................................ 369
15-35. Performance Counter Master Region Select Register (PCMRS) Field Descriptions
...........................
370
15-36. Performance Counter Time Register (PCT) Field Description ..................................................... 371
15-37. DDR PHY Reset Control Register (DRPYRCR) ..................................................................... 371
15-38. Interrupt Raw Register (IRR) Field Descriptions ..................................................................... 372
................................................................
Interrupt Mask Set Register (IMSR) Field Descriptions .............................................................
Interrupt Mask Clear Register (IMCR) Field Descriptions ..........................................................
DDR PHY Control Register 1 (DRPYC1R) Field Descriptions .....................................................
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger ..........................................
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ............................
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ..............................................
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers ..............................
ECAP Initialization for APWM Mode ..................................................................................
ECAP1 Initialization for Multichannel PWM Generation with Synchronization ...................................
ECAP2 Initialization for Multichannel PWM Generation with Synchronization ...................................
15-39. Interrupt Masked Register (IMR) Field Descriptions
15-40.
15-41.
15-42.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
50
List of Tables
Copyright © 2011, Texas Instruments Incorporated
372
373
374
375
390
392
394
396
398
400
400
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16-8.
ECAP3 Initialization for Multichannel PWM Generation with Synchronization ................................... 400
16-9.
ECAP4 Initialization for Multichannel PWM Generation with Synchronization ................................... 400
16-10. ECAP1 Initialization for Multichannel PWM Generation with Phase Control ..................................... 403
16-11. ECAP2 Initialization for Multichannel PWM Generation with Phase Control ..................................... 403
16-12. ECAP3 Initialization for Multichannel PWM Generation with Phase Control ..................................... 403
16-13. Control and Status Register Set ....................................................................................... 404
16-14. Time-Stamp Counter Register (TSCTR) Field Descriptions ........................................................ 404
16-15. Counter Phase Control Register (CTRPHS) Field Descriptions ................................................... 405
16-16. Capture 1 Register (CAP1) Field Descriptions ....................................................................... 405
16-17. Capture 2 Register (CAP2) Field Descriptions ....................................................................... 406
16-18. Capture 3 Register (CAP3) Field Descriptions ....................................................................... 406
16-19. Capture 4 Register (CAP4) Field Descriptions ....................................................................... 407
16-20. ECAP Control Register 1 (ECCTL1) Field Descriptions ............................................................ 407
16-21. ECAP Control Register 2 (ECCTL2) Field Descriptions ............................................................ 409
....................................................
........................................................
ECAP Interrupt Clear Register (ECCLR) Field Descriptions ......................................................
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions ....................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
ePWM Module Control and Status Registers Grouped by Submodule ...........................................
Submodule Configuration Parameters ................................................................................
Time-Base Submodule Registers ......................................................................................
Key Time-Base Signals .................................................................................................
Counter-Compare Submodule Registers ............................................................................
Counter-Compare Submodule Key Signals ..........................................................................
Action-Qualifier Submodule Registers ................................................................................
Action-Qualifier Submodule Possible Input Events ..................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode ..........................................................
Action-Qualifier Event Priority for Up-Count Mode ..................................................................
Action-Qualifier Event Priority for Down-Count Mode ...............................................................
Behavior if CMPA/CMPB is Greater than the Period................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
EPWMx Initialization for ................................................................................................
EPWMx Run Time Changes for .......................................................................................
Dead-Band Generator Submodule Registers ........................................................................
Classical Dead-Band Operating Modes ..............................................................................
PWM-Chopper Submodule Registers .................................................................................
Trip-Zone Submodule Registers .......................................................................................
Possible Actions On a Trip Event ......................................................................................
Event-Trigger Submodule Registers ..................................................................................
16-22. ECAP Interrupt Enable Register (ECEINT) Field Descriptions
411
16-23. ECAP Interrupt Flag Register (ECFLG) Field Descriptions
412
16-24.
16-25.
16-26.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
SPRUH78A – December 2011
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List of Tables
Copyright © 2011, Texas Instruments Incorporated
413
414
415
422
423
428
429
437
437
441
442
444
444
444
445
448
448
450
450
452
452
454
454
456
456
458
458
459
461
463
468
469
471
51
www.ti.com
17-31. Resolution for PWM and HRPWM ..................................................................................... 476
17-32. HRPWM Submodule Registers ........................................................................................ 477
17-33. Relationship Between MEP Steps, PWM Frequency and Resolution
............................................
478
17-34. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ....................................................... 479
486
17-36. EPWM2 Initialization for
486
17-37.
486
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
52
................................................................................................
................................................................................................
EPWM3 Initialization for ................................................................................................
EPWM1 Initialization for ................................................................................................
EPWM2 Initialization for ................................................................................................
EPWM1 Initialization for ................................................................................................
EPWM2 Initialization for ................................................................................................
EPWM1 Initialization for ................................................................................................
EPWM2 Initialization for ................................................................................................
EPWM3 Initialization for ................................................................................................
EPWM1 Initialization for ................................................................................................
EPWM2 Initialization for ................................................................................................
EPWM3 Initialization for ................................................................................................
EPWM1 Initialization for ................................................................................................
EPWM2 Initialization for ................................................................................................
Submodule Registers ....................................................................................................
Time-Base Submodule Registers ......................................................................................
Time-Base Control Register (TBCTL) Field Descriptions ...........................................................
Time-Base Status Register (TBSTS) Field Descriptions ...........................................................
Time-Base Phase Register (TBPHS) Field Descriptions ...........................................................
Time-Base Counter Register (TBCNT) Field Descriptions .........................................................
Time-Base Period Register (TBPRD) Field Descriptions ...........................................................
Counter-Compare Submodule Registers .............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions ...............................................
Counter-Compare A Register (CMPA) Field Descriptions ..........................................................
Counter-Compare B Register (CMPB) Field Descriptions ..........................................................
Action-Qualifier Submodule Registers ................................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .......................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .......................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions .........................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions ........................
Dead-Band Generator Submodule Registers ........................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions .............................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions...............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ..............................
PWM-Chopper Control Register (PCCTL) Bit Descriptions ........................................................
Trip-Zone Submodule Registers .......................................................................................
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ..............................................
Trip-Zone Control Register (TZCTL) Field Descriptions ............................................................
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ................................................
Trip-Zone Flag Register (TZFLG) Field Descriptions ...............................................................
Trip-Zone Clear Register (TZCLR) Field Descriptions .............................................................
Trip-Zone Force Register (TZFRC) Field Descriptions .............................................................
Event-Trigger Submodule Registers ..................................................................................
Event-Trigger Selection Register (ETSEL) Field Descriptions ....................................................
17-35. EPWM1 Initialization for
List of Tables
Copyright © 2011, Texas Instruments Incorporated
489
489
492
492
495
495
496
501
501
502
505
505
506
506
507
508
509
509
510
510
511
512
513
513
514
515
516
517
517
518
519
519
520
521
521
522
522
523
524
524
525
525
SPRUH78A – December 2011
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......................................................
Event-Trigger Flag Register (ETFLG) Field Descriptions ...........................................................
Event-Trigger Clear Register (ETCLR) Field Descriptions .........................................................
Event-Trigger Force Register (ETFRC) Field Descriptions ........................................................
High-Resolution PWM Submodule Registers ........................................................................
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ...................................
Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ..................................
HRPWM Configuration Register (HRCNFG) Field Descriptions ...................................................
EDMA3 Channel Parameter Description ..............................................................................
Dummy and Null Transfer Request ....................................................................................
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ....................................
Expected Number of Transfers for Non-Null Transfer ..............................................................
EDMA3 DMA Channel to PaRAM Mapping ..........................................................................
Shadow Region Registers ..............................................................................................
Chain Event Triggers ....................................................................................................
EDMA3 Transfer Completion Interrupts ...............................................................................
EDMA3 Error Interrupts .................................................................................................
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping.................................................
Number of Interrupts .....................................................................................................
EDMA3 Transfer Controller Configurations ...........................................................................
Read/Write Command Optimization Rules ...........................................................................
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries ....................................
Channel Options Parameters (OPT) Field Descriptions ............................................................
Channel Source Address Parameter (SRC) Field Descriptions ...................................................
A Count/B Count Parameter (A_B_CNT) Field Descriptions .......................................................
Channel Destination Address Parameter (DST) Field Descriptions ...............................................
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions ........................
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ...............................
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions .......................
C Count Parameter (CCNT) Field Descriptions ......................................................................
EDMA3 Channel Controller (EDMA3CC) Registers .................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3CC Configuration Register (CCCFG) Field Descriptions ..................................................
QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions ............................................
DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ...................................
Bits in DMAQNUMn .....................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ...................................
Event Missed Register (EMR) Field Descriptions ...................................................................
Event Missed Clear Register (EMCR) Field Descriptions ..........................................................
QDMA Event Missed Register (QEMR) Field Descriptions ........................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ...............................................
EDMA3CC Error Register (CCERR) Field Descriptions ............................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ...............................................
Error Evaluate Register (EEVAL) Field Descriptions ................................................................
DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions..............................
QDMA Region Access Enable for Region m (QRAEm) Field Descriptions ......................................
Event Queue Entry Registers (QxEy) Field Descriptions ...........................................................
Queue n Status Register (QSTATn) Field Descriptions ............................................................
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ......................................
17-80. Event-Trigger Prescale Register (ETPS) Field Descriptions
526
17-81.
527
17-82.
17-83.
17-84.
17-85.
17-86.
17-87.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
SPRUH78A – December 2011
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List of Tables
Copyright © 2011, Texas Instruments Incorporated
527
528
528
529
529
530
544
547
548
556
558
560
563
563
564
564
565
572
578
597
598
600
600
601
601
602
603
603
604
607
608
609
610
610
611
612
613
614
615
616
617
618
619
620
621
622
623
53
www.ti.com
18-42. EDMA3CC Status Register (CCSTAT) Field Descriptions ......................................................... 624
18-43. Event Register (ER) Field Descriptions ............................................................................... 626
18-44. Event Clear Register (ECR) Field Descriptions ...................................................................... 627
628
18-46.
629
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
18-69.
18-70.
18-71.
18-72.
18-73.
18-74.
18-75.
18-76.
18-77.
18-78.
18-79.
18-80.
18-81.
18-82.
18-83.
18-84.
18-85.
18-86.
18-87.
18-88.
18-89.
18-90.
54
........................................................................
Chained Event Register (CER) Field Descriptions ..................................................................
Event Enable Register (EER) Field Descriptions ....................................................................
Event Enable Clear Register (EECR) Field Descriptions ...........................................................
Event Enable Set Register (EESR) Field Descriptions .............................................................
Secondary Event Register (SER) Field Descriptions................................................................
Secondary Event Clear Register (SECR) Field Descriptions ......................................................
Interrupt Enable Register (IER) Field Descriptions ..................................................................
Interrupt Enable Clear Register (IECR) Field Descriptions .........................................................
Interrupt Enable Set Register (IESR) Field Descriptions ...........................................................
Interrupt Pending Register (IPR) Field Descriptions ................................................................
Interrupt Clear Register (ICR) Field Descriptions ....................................................................
Interrupt Evaluate Register (IEVAL) Field Descriptions .............................................................
QDMA Event Register (QER) Field Descriptions ....................................................................
QDMA Event Enable Register (QEER) Field Descriptions .........................................................
QDMA Event Enable Clear Register (QEECR) Field Descriptions ................................................
QDMA Event Enable Set Register (QEESR) Field Descriptions ..................................................
QDMA Secondary Event Register (QSER) Field Descriptions.....................................................
QDMA Secondary Event Clear Register (QSECR) Field Descriptions ...........................................
EDMA3 Transfer Controller (EDMA3TC) Registers .................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
EDMA3TC Configuration Register (TCCFG) Field Descriptions ...................................................
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ...............................................
Error Status Register (ERRSTAT) Field Descriptions ...............................................................
Error Enable Register (ERREN) Field Descriptions .................................................................
Error Clear Register (ERRCLR) Field Descriptions .................................................................
Error Details Register (ERRDET) Field Descriptions................................................................
Error Interrupt Command Register (ERRCMD) Field Descriptions ................................................
Read Command Rate Register (RDRATE) Field Descriptions ....................................................
Source Active Options Register (SAOPT) Field Descriptions ......................................................
Source Active Source Address Register (SASRC) Field Descriptions ............................................
Source Active Count Register (SACNT) Field Descriptions ........................................................
Source Active Destination Address Register (SADST) Field Descriptions .......................................
Source Active B-Index Register (SABIDX) Field Descriptions .....................................................
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ...........................
Source Active Count Reload Register (SACNTRLD) Field Descriptions .........................................
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ....................
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ................
Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions ................................
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ............
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions .......
Destination FIFO Options Register n (DFOPTn) Field Descriptions ..............................................
Destination FIFO Source Address Register n (DFSRCn) Field Descriptions ....................................
Destination FIFO Count Register n (DFCNTn) Field Descriptions ................................................
Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions ...............................
Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions .............................................
18-45. Event Set Register (ESR) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
630
631
631
632
632
633
634
634
635
636
637
638
639
640
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
654
655
655
656
657
657
658
658
659
659
660
661
661
662
662
SPRUH78A – December 2011
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18-91. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions ................... 663
18-92. Debug List................................................................................................................. 664
19-1.
EMAC and MDIO Signals for MII Interface ........................................................................... 673
19-2.
EMAC and MDIO Signals for RMII Interface ......................................................................... 674
19-3.
Ethernet Frame Description
675
19-4.
Basic Descriptor Description
677
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
............................................................................................
...........................................................................................
Receive Frame Treatment Summary ..................................................................................
Middle of Frame Overrun Treatment ..................................................................................
Emulation Control ........................................................................................................
EMAC Control Module Registers ......................................................................................
EMAC Control Module Revision ID Register (REVID) Field Descriptions ........................................
EMAC Control Module Software Reset Register (SOFTRESET)..................................................
EMAC Control Module Interrupt Control Register (INTCONTROL) ...............................................
702
703
713
714
715
716
717
19-12. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ...................................................................................................... 718
19-13. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ..................... 719
19-14. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ..................... 720
19-15. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ........... 721
19-16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT) .................................................................................................. 722
19-17. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) ................... 723
19-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT)
..................
724
19-19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT)......... 725
19-20. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ....... 726
19-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ....... 727
19-22. Management Data Input/Output (MDIO) Registers .................................................................. 728
19-23. MDIO Revision ID Register (REVID) Field Descriptions ............................................................ 728
19-24. MDIO Control Register (CONTROL) Field Descriptions ............................................................ 729
19-25. PHY Acknowledge Status Register (ALIVE) Field Descriptions ................................................... 730
19-26. PHY Link Status Register (LINK) Field Descriptions ................................................................ 730
19-27. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ............... 731
19-28. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions.............. 732
19-29. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ...... 733
19-30. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
....
734
19-31. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ... 735
19-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions ............................................................................................................... 736
19-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................ 737
19-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions........................................ 738
19-35. MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................ 739
19-36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions........................................ 740
19-37. Ethernet Media Access Controller (EMAC) Registers
..............................................................
741
19-38. Transmit Revision ID Register (TXREVID) Field Descriptions ..................................................... 744
19-39. Transmit Control Register (TXCONTROL) Field Descriptions ..................................................... 744
19-40. Transmit Teardown Register (TXTEARDOWN) Field Descriptions ............................................... 745
19-41. Receive Revision ID Register (RXREVID) Field Descriptions ..................................................... 746
19-42. Receive Control Register (RXCONTROL) Field Descriptions...................................................... 746
19-43. Receive Teardown Register (RXTEARDOWN) Field Descriptions ................................................ 747
19-44. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
.......................
748
19-45. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ...................... 749
SPRUH78A – December 2011
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Copyright © 2011, Texas Instruments Incorporated
55
www.ti.com
19-46. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions.................................... 750
.............................
................................................
MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................................
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ........................
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ......................
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ....................................
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ..............................
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .........................
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ........................
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions .....................................
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ...............................
19-47. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
751
19-48. MAC Input Vector Register (MACINVECTOR) Field Descriptions
752
19-49.
753
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
754
755
756
757
758
758
759
759
19-58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions ............................................................................................................... 760
19-59. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ................................... 763
19-60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 764
19-61. Receive Maximum Length Register (RXMAXLEN) Field Descriptions............................................ 765
19-62. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ....................................... 765
19-63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
......
766
19-64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions .............. 766
19-65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ..................... 767
19-66. MAC Control Register (MACCONTROL) Field Descriptions ....................................................... 768
19-67. MAC Status Register (MACSTATUS) Field Descriptions ........................................................... 770
19-68. Emulation Control Register (EMCONTROL) Field Descriptions ................................................... 772
19-69. FIFO Control Register (FIFOCONTROL) Field Descriptions ....................................................... 772
773
19-71.
773
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
19-82.
19-83.
19-84.
19-85.
19-86.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
56
..................................................
Soft Reset Register (SOFTRESET) Field Descriptions .............................................................
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ...........................
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ............................
MAC Hash Address Register 1 (MACHASH1) Field Descriptions.................................................
MAC Hash Address Register 2 (MACHASH2) Field Descriptions.................................................
Back Off Test Register (BOFFTEST) Field Descriptions ...........................................................
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ....................................
Receive Pause Timer Register (RXPAUSE) Field Descriptions ...................................................
Transmit Pause Timer Register (TXPAUSE) Field Descriptions ..................................................
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ..........................................
MAC Address High Bytes Register (MACADDRHI) Field Descriptions ...........................................
MAC Index Register (MACINDEX) Field Descriptions ..............................................................
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ...................
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ...................
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions..................................
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ..................................
EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories .......................................
EMIFA Pins Specific to SDRAM .......................................................................................
EMIFA Pins Specific to Asynchronous Memory .....................................................................
EMIFA SDRAM Commands ............................................................................................
Truth Table for SDRAM Commands ..................................................................................
16-bit EMIFA Address Pin Connections ..............................................................................
Description of the SDRAM Configuration Register (SDCR) ........................................................
19-70. MAC Configuration Register (MACCONFIG) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
774
774
775
775
776
776
777
777
778
779
779
780
780
781
781
793
794
794
795
795
797
798
SPRUH78A – December 2011
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20-8.
Description of the SDRAM Refresh Control Register (SDRCR) ................................................... 798
20-9.
Description of the SDRAM Timing Register (SDTIMR) ............................................................. 799
20-10. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR)...................................... 799
20-11. SDRAM LOAD MODE REGISTER Command ....................................................................... 800
20-12. Refresh Urgency Levels................................................................................................. 801
20-13. Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM ................................................. 806
20-14. Normal Mode vs. Select Strobe Mode
................................................................................
807
20-15. Description of the Asynchronous m Configuration Register (CEnCFG) .......................................... 809
.................................
Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ...........................................
Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) .........................................
Asynchronous Read Operation in Normal Mode ....................................................................
Asynchronous Write Operation in Normal Mode .....................................................................
Asynchronous Read Operation in Select Strobe Mode .............................................................
Asynchronous Write Operation in Select Strobe Mode .............................................................
Description of the NAND Flash Control Register (NANDFCR) ....................................................
Reset Sources ............................................................................................................
Interrupt Monitor and Control Bit Fields ...............................................................................
SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface ...............................................
SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface .................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ................................................
RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ................................................
SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ..........................................
EMIFA Input Timing Requirements ....................................................................................
ASRAM Output Timing Characteristics ...............................................................................
ASRAM Input Timing Requirement for a Read ......................................................................
ASRAM Input Timing Requirements for a Write ....................................................................
ASRAM Timing Requirements With PCB Delays ....................................................................
EMIFA Timing Requirements for TC5516100FT-12 Example .....................................................
ASRAM Timing Requirements for TC5516100FT-12 Example ....................................................
Measured PCB Delays for TC5516100FT-12 Example .............................................................
Configuring CE3CFG for TC5516100FT-12 Example...............................................................
Recommended Margins .................................................................................................
EMIFA Read Timing Requirements ...................................................................................
NAND Flash Read Timing Requirements .............................................................................
NAND Flash Write Timing Requirements ............................................................................
EMIFA Timing Requirements for HY27UA081G1M Example ......................................................
NAND Flash Timing Requirements for HY27UA081G1M Example ...............................................
Configuring CE2CFG for HY27UA081G1M Example ...............................................................
Configuring NANDFCR for HY27UA081G1M Example .............................................................
External Memory Interface (EMIFA) Registers .......................................................................
Module ID Register (MIDR) Field Descriptions ......................................................................
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ................................
SDRAM Configuration Register (SDCR) Field Descriptions .......................................................
SDRAM Refresh Control Register (SDRCR) Field Descriptions ...................................................
Asynchronous n Configuration Register (CEnCFG) Field Descriptions ..........................................
SDRAM Timing Register (SDTIMR) Field Descriptions .............................................................
SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions .....................................
EMIFA Interrupt Raw Register (INTRAW) Field Descriptions ......................................................
20-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC)
810
20-17.
811
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Tables
Copyright © 2011, Texas Instruments Incorporated
811
811
813
815
817
819
825
827
832
834
835
835
836
837
837
837
838
840
843
843
843
845
845
846
846
848
851
851
853
853
854
855
856
857
859
860
861
862
863
57
www.ti.com
20-57. EMIFA Interrupt Mask Register (INTMSK) Field Descriptions ..................................................... 864
20-58. EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ........................................... 865
20-59. EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions
........................................
866
20-60. NAND Flash Control Register (NANDFCR) Field Descriptions .................................................... 867
20-61. NAND Flash Status Register (NANDFSR) Field Descriptions ..................................................... 869
870
20-63.
871
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
58
.................................................
NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions ...........................
NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions .......................................
NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions .......................................
NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions .......................................
NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions .......................................
NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions .....................
NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions .....................
NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions .........................
NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions .........................
GPIO Register Bits and Banks Associated With GPIO Signals....................................................
GPIO Registers...........................................................................................................
Revision ID Register (REVID) Field Descriptions ....................................................................
GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions .........................................
GPIO Direction Register (DIRn) Field Descriptions .................................................................
GPIO Output Data Register (OUT_DATAn) Field Descriptions ....................................................
GPIO Set Data Register (SET_DATAn) Field Descriptions ........................................................
GPIO Clear Data Register (CLR_DATAn) Field Descriptions ......................................................
GPIO Input Data Register (IN_DATAn) Field Descriptions .........................................................
GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions .....................
GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions.............................
GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions ....................
GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions ............................
GPIO Interrupt Status Register (INTSTATn) Field Descriptions ...................................................
Operating Modes of the I2C Peripheral ...............................................................................
Ways to Generate a NACK Bit .........................................................................................
Descriptions of the I2C Interrupt Events ..............................................................................
Inter-Integrated Circuit (I2C) Registers................................................................................
I2C Own Address Register (ICOAR) Field Descriptions ............................................................
I2C Interrupt Mask Register (ICIMR) Field Descriptions ............................................................
I2C Interrupt Status Register (ICSTR) Field Descriptions ..........................................................
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ...............................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ..............................................
I2C Data Count Register (ICCNT) Field Descriptions ...............................................................
I2C Data Receive Register (ICDRR) Field Descriptions ............................................................
I2C Slave Address Register (ICSAR) Field Descriptions ...........................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ...........................................................
I2C Mode Register (ICMDR) Field Descriptions .....................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ..................................
How the MST and FDF Bits Affect the Role of TRX Bit ............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions ...........................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions .......................................................
I2C Prescaler Register (ICPSC) Field Descriptions .................................................................
I2C Revision Identification Register 1 (REVID1) Field Descriptions ..............................................
20-62. NAND Flash n ECC Register (NANDFnECC) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
872
872
873
873
874
874
875
875
880
887
888
889
891
893
895
897
899
901
903
905
907
909
920
921
925
926
927
928
929
932
932
933
934
935
936
937
939
939
941
942
943
944
SPRUH78A – December 2011
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.............................................. 944
I2C DMA Control Register (ICDMAC) Field Descriptions........................................................... 945
I2C Pin Function Register (ICPFUNC) Field Descriptions .......................................................... 946
I2C Pin Direction Register (ICPDIR) Field Descriptions ............................................................ 947
I2C Pin Data In Register (ICPDIN) Field Descriptions .............................................................. 948
I2C Pin Data Out Register (ICPDOUT) Field Descriptions ......................................................... 949
I2C Pin Data Set Register (ICPDSET) Field Descriptions .......................................................... 950
I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ....................................................... 951
Biphase-Mark Encoder .................................................................................................. 961
Preamble Codes ......................................................................................................... 962
Channel Status and User Data for Each DIT Block ................................................................ 988
Transmit Bitstream Data Alignment ................................................................................... 995
Receive Bitstream Data Alignment .................................................................................... 997
EDMA Events - McASP ................................................................................................ 1007
McASP Registers Accessed Through Peripheral Configuration Port ............................................ 1008
McASP Registers Accessed Through DMA Port ................................................................... 1010
McASP AFIFO Registers Accessed Through Peripheral Configuration Port ................................... 1010
Bits With Restrictions on When They May be Changed .......................................................... 1011
Revision Identification Register (REV) Field Descriptions ........................................................ 1012
Pin Function Register (PFUNC) Field Descriptions ................................................................ 1013
Pin Direction Register (PDIR) Field Descriptions .................................................................. 1015
Pin Data Output Register (PDOUT) Field Descriptions ........................................................... 1017
Pin Data Input Register (PDIN) Field Descriptions................................................................. 1019
Pin Data Set Register (PDSET) Field Descriptions ................................................................ 1021
Pin Data Clear Register (PDCLR) Field Descriptions ............................................................. 1023
Global Control Register (GBLCTL) Field Descriptions ............................................................ 1024
Audio Mute Control Register (AMUTE) Field Descriptions........................................................ 1026
Digital Loopback Control Register (DLBCTL) Field Descriptions ................................................ 1028
Digital Mode Control Register (DITCTL) Field Descriptions ...................................................... 1029
Receiver Global Control Register (RGBLCTL) Field Descriptions ............................................... 1030
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions ........................................... 1031
Receive Bit Stream Format Register (RFMT) Field Descriptions ................................................ 1032
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ......................................... 1034
Receive Clock Control Register (ACLKRCTL) Field Descriptions ............................................... 1035
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ......................... 1036
Receive TDM Time Slot Register (RTDM) Field Descriptions .................................................... 1037
Receiver Interrupt Control Register (RINTCTL) Field Descriptions .............................................. 1038
Receiver Status Register (RSTAT) Field Descriptions ............................................................ 1039
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions ....................................... 1040
Receive Clock Check Control Register (RCLKCHK) Field Descriptions ........................................ 1041
Receiver DMA Event Control Register (REVTCTL) Field Descriptions ......................................... 1042
Transmitter Global Control Register (XGBLCTL) Field Descriptions ............................................ 1043
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions .......................................... 1044
Transmit Bit Stream Format Register (XFMT) Field Descriptions................................................ 1045
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions ......................................... 1047
Transmit Clock Control Register (ACLKXCTL) Field Descriptions ............................................... 1048
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions ......................... 1049
Transmit TDM Time Slot Register (XTDM) Field Descriptions ................................................... 1050
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ........................................... 1051
22-21. I2C Revision Identification Register 2 (REVID2) Field Descriptions
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
SPRUH78A – December 2011
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List of Tables
Copyright © 2011, Texas Instruments Incorporated
59
www.ti.com
1052
23-43.
1053
23-44.
23-45.
23-46.
23-47.
23-48.
23-49.
23-50.
23-51.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
60
.........................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ........................................
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions .......................................
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions ......................................
Serializer Control Registers (SRCTLn) Field Descriptions ........................................................
AFIFO Revision Identification Register (AFIFOREV) Field Descriptions ........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions.....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .....................................................
McBSP Interface Signals ..............................................................................................
Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits .............
Receive Clock Selection ...............................................................................................
Transmit Clock Selection ..............................................................................................
Receive Frame Synchronization Selection ..........................................................................
Transmit Frame Synchronization Selection .........................................................................
RCR/XCR Fields Controlling Elements per Frame and Bits per Element.......................................
Receive/Transmit Frame Length Configuration ....................................................................
Receive/Transmit Element Length Configuration ..................................................................
Effect of RJUST Bit Values With 12-Bit Example Data ABCh ....................................................
Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh ................................................
Justification of Expanded Data in DRR ..............................................................................
Receive Channel Assignment and Control When Two Receive Partitions are Used .........................
Transmit Channel Assignment and Control When Two Transmit Partitions are Used ........................
Receive Channel Assignment and Control When Eight Receive Partitions are Used ........................
Transmit Channel Assignment and Control When Eight Transmit Partitions are Used .......................
Selecting a Transmit Multichannel Selection Mode With the XMCM Bits .......................................
Reset State of McBSP Pins ...........................................................................................
Receiver Clock and Frame Configurations ..........................................................................
Transmitter Clock and Frame Configurations .......................................................................
McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR ...............................
McBSP Registers .......................................................................................................
Data Receive Register (DRR) Field Descriptions ..................................................................
Data Transmit Register (DXR) Field Descriptions .................................................................
Serial Port Control Register (SPCR) Field Descriptions...........................................................
Receive Control Register (RCR) Field Descriptions ..............................................................
Transmit Control Register (XCR) Field Descriptions ..............................................................
Sample Rate Generator Register (SRGR) Field Descriptions ....................................................
Multichannel Control Register (MCR) Field Descriptions .........................................................
Enhanced Receive Channel Enable Register n (RCEREn) Field Descriptions ................................
Use of the Receive Channel Enable Registers .....................................................................
Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions................................
Use of the Transmit Channel Enable Registers ....................................................................
Pin Control Register (PCR) Field Descriptions .....................................................................
BFIFO Revision Identification Register (BFIFOREV) Field Descriptions ........................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions.....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .....................................................
23-42. Transmitter Status Register (XSTAT) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
1054
1055
1056
1060
1061
1062
1063
1064
1068
1072
1075
1076
1077
1078
1079
1079
1080
1082
1082
1098
1101
1101
1103
1103
1104
1107
1108
1108
1114
1115
1116
1116
1117
1119
1121
1123
1124
1128
1129
1130
1131
1132
1134
1135
1136
1137
1138
SPRUH78A – December 2011
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www.ti.com
25-1.
MMC/SD Controller Pins Used in Each Mode ...................................................................... 1143
25-2.
MMC/SD Mode Write Sequence
25-3.
MMC/SD Mode Read Sequence ..................................................................................... 1145
25-4.
Description of MMC/SD Interrupt Requests ......................................................................... 1155
25-5.
Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers .......................................... 1169
25-6.
MMC Control Register (MMCCTL) Field Descriptions ............................................................. 1170
25-7.
MMC Memory Clock Control Register (MMCCLK) Field Descriptions
25-8.
MMC Status Register 0 (MMCST0) Field Descriptions ............................................................ 1172
25-9.
MMC Status Register 1 (MMCST1) Field Descriptions ............................................................ 1174
.....................................................................................
..........................................
1144
1171
25-10. MMC Interrupt Mask Register (MMCIM) Field Descriptions ...................................................... 1175
25-11. MMC Response Time-Out Register (MMCTOR) Field Descriptions ............................................. 1177
25-12. MMC Data Read Time-Out Register (MMCTOD) Field Descriptions ............................................ 1178
25-13. MMC Block Length Register (MMCBLEN) Field Descriptions .................................................... 1179
25-14. MMC Number of Blocks Register (MMCNBLK) Field Descriptions .............................................. 1180
...................................
....................................................
MMC Data Transmit Register (MMCDXR) Field Descriptions ....................................................
MMC Command Register (MMCCMD) Field Descriptions ........................................................
Command Format ......................................................................................................
MMC Argument Register (MMCARGHL) Field Descriptions......................................................
R1, R3, R4, R5, or R6 Response (48 Bits) .........................................................................
R2 Response (136 Bits) ...............................................................................................
MMC Data Response Register (MMCDRSP) Field Descriptions ................................................
MMC Command Index Register (MMCCIDX) Field Descriptions ................................................
SDIO Control Register (SDIOCTL) Field Descriptions ............................................................
SDIO Status Register 0 (SDIOST0) Field Descriptions ...........................................................
SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions ..................................................
SDIO Interrupt Status Register (SDIOIST) Field Descriptions ...................................................
MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions ................................................
Real-Time Clock Signals ..............................................................................................
Real-Time Clock (RTC) Registers ....................................................................................
Second Register (SECOND) Field Descriptions....................................................................
Minute Register (MINUTE) Field Descriptions ......................................................................
Hour Register (HOUR) Field Descriptions ..........................................................................
Day Register (DAY) Field Descriptions ..............................................................................
Month Register (MONTH) Field Descriptions .......................................................................
Year Register (YEAR) Field Descriptions ...........................................................................
Day of the Week Register (DOTW) Field Descriptions ............................................................
Alarm Second Register (ALARMSECOND) Field Descriptions ..................................................
Alarm Minute Register (ALARMMINUTE) Field Descriptions .....................................................
Alarm Hour Register (ALARMHOUR) Field Descriptions .........................................................
Alarm Day Register (ALARMDAY) Field Descriptions .............................................................
Alarm Month Register (ALARMMONTH) Field Descriptions ......................................................
Alarm Years Register (ALARMYEARS) Field Descriptions .......................................................
Control Register (CTRL) Field Descriptions ........................................................................
Status Register (STATUS) Field Descriptions ......................................................................
Interrupt Register (INTERRUPT) Field Descriptions ...............................................................
Compensations Register (COMPLSB) Field Descriptions ........................................................
Compensations Register (COMPMSB) Field Descriptions........................................................
25-15. MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions
1180
25-16. MMC Data Receive Register (MMCDRR) Field Descriptions
1181
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Tables
Copyright © 2011, Texas Instruments Incorporated
1181
1182
1183
1184
1186
1186
1187
1187
1188
1189
1190
1190
1191
1195
1201
1202
1202
1203
1204
1204
1205
1205
1206
1206
1207
1208
1209
1209
1210
1211
1212
1213
1214
61
www.ti.com
26-21. Oscillator Register (OSC) Field Descriptions ....................................................................... 1215
26-22. Scratch Registers (SCRATCHn) Field Descriptions ............................................................... 1216
26-23. Kick Registers (KICKnR) Field Descriptions ........................................................................ 1216
27-1.
SPI Pins.................................................................................................................. 1220
27-2.
SPI Registers
27-3.
SPI Register Settings Defining Master Modes...................................................................... 1222
27-4.
Allowed SPI Register Settings in Master Modes ................................................................... 1222
27-5.
SPI Register Settings Defining Slave Modes ....................................................................... 1224
27-6.
Allowed SPI Register Settings in Slave Modes..................................................................... 1224
27-7.
Clocking Modes ......................................................................................................... 1233
27-8.
SPI Registers
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
27-25.
27-26.
27-27.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
62
...........................................................................................................
...........................................................................................................
SPI Global Control Register 0 (SPIGCR0) Field Descriptions....................................................
SPI Global Control Register 1 (SPIGCR1) Field Descriptions....................................................
SPI Interrupt Register (SPIINT0) Field Descriptions ...............................................................
SPI Interrupt Level Register (SPILVL) Field Descriptions.........................................................
SPI Flag Register (SPIFLG) Field Descriptions ....................................................................
SPI Pin Control Register 0 (SPIPC0) Field Descriptions ..........................................................
SPI Pin Control Register 1 (SPIPC1) Field Descriptions ..........................................................
SPI Pin Control Register 2 (SPIPC2) Field Descriptions ..........................................................
SPI Pin Control Register 3 (SPIPC3) Field Descriptions ..........................................................
SPI Pin Control Register 4 (SPIPC4) Field Descriptions ..........................................................
SPI Pin Control Register 5 (SPIPC5) Field Descriptions ..........................................................
SPI Data Register 0 (SPIDAT0) Field Descriptions ................................................................
SPI Data Register 1 (SPIDAT1) Field Descriptions ................................................................
SPI Buffer Register (SPIBUF) Field Descriptions ..................................................................
SPI Emulation Register (SPIEMU) Field Descriptions .............................................................
SPI Delay Register (SPIDELAY) Field Descriptions ...............................................................
SPI Default Chip Select Register (SPIDEF) Field Descriptions ..................................................
SPI Data Format Register (SPIFMTn) Field Descriptions.........................................................
SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ...................................................
Timer Clock Source Selection ........................................................................................
64-Bit Timer Configurations ...........................................................................................
32-Bit Timer Chained Mode Configurations .........................................................................
32-Bit Timer Unchained Mode Configurations ......................................................................
Counter and Period Registers Used in GP Timer Modes .........................................................
TSTAT Parameters in Pulse and Clock Modes ....................................................................
Timer Emulation Modes Selection ...................................................................................
Timer Registers .........................................................................................................
Revision ID Register (REVID) Field Descriptions ..................................................................
Emulation Management Register (EMUMGT) Field Descriptions ................................................
GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ...............................
GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions ........................................
Timer Counter Register 12 (TIM12) Field Descriptions ...........................................................
Timer Counter Register 34 (TIM34) Field Descriptions ...........................................................
Timer Period Register (PRD12) Field Descriptions ................................................................
Timer Period Register (PRD34) Field Descriptions ................................................................
Timer Control Register (TCR) Field Descriptions ..................................................................
Timer Global Control Register (TGCR) Field Descriptions........................................................
Watchdog Timer Control Register (WDTCR) Field Descriptions .................................................
List of Tables
Copyright © 2011, Texas Instruments Incorporated
1221
1246
1246
1247
1249
1251
1252
1254
1255
1256
1257
1258
1259
1260
1261
1262
1264
1265
1268
1269
1271
1276
1278
1281
1284
1286
1290
1292
1292
1293
1293
1294
1295
1296
1296
1297
1297
1298
1300
1301
SPRUH78A – December 2011
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www.ti.com
28-20. Timer Reload Register 12 (REL12) Field Descriptions ............................................................ 1302
28-21. Timer Reload Register 34 (REL34) Field Descriptions ............................................................ 1302
28-22. Timer Capture Register 12 (CAP12) Field Descriptions........................................................... 1303
28-23. Timer Capture Register 34 (CAP34) Field Descriptions........................................................... 1303
28-24. Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ............................... 1304
28-25. Timer Compare Register (CMPn) Field Descriptions .............................................................. 1305
.......................
.......................
UART Signal Descriptions .............................................................................................
Character Time for Word Lengths ....................................................................................
UART Interrupt Requests Descriptions ..............................................................................
UART Registers ........................................................................................................
Receiver Buffer Register (RBR) Field Descriptions ................................................................
Transmitter Holding Register (THR) Field Descriptions ...........................................................
Interrupt Enable Register (IER) Field Descriptions ................................................................
Interrupt Identification Register (IIR) Field Descriptions ...........................................................
Interrupt Identification and Interrupt Clearing Information .........................................................
FIFO Control Register (FCR) Field Descriptions ...................................................................
Line Control Register (LCR) Field Descriptions ....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR ............................................................
Number of STOP Bits Generated ....................................................................................
Modem Control Register (MCR) Field Descriptions................................................................
Line Status Register (LSR) Field Descriptions .....................................................................
Modem Status Register (MSR) Field Descriptions .................................................................
Scratch Pad Register (MSR) Field Descriptions ...................................................................
Divisor LSB Latch (DLL) Field Descriptions.........................................................................
Divisor MSB Latch (DLH) Field Descriptions .......................................................................
Revision Identification Register 1 (REVID1) Field Descriptions ..................................................
Revision Identification Register 2 (REVID2) Field Descriptions ..................................................
Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ........................
Mode Definition Register (MDR) Field Descriptions ...............................................................
USB Clock Multiplexing Options ......................................................................................
PHY PLL Clock Frequencies Supported ............................................................................
USB Terminal Functions ...............................................................................................
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions..............................................
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ..........................................
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ....................................
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions .................................
Host Packet Descriptor Word 0 (HPD Word 0) .....................................................................
Host Packet Descriptor Word 1 (HPD Word 1) .....................................................................
Host Packet Descriptor Word 2 (HPD Word 2) .....................................................................
Host Packet Descriptor Word 3 (HPD Word 3) .....................................................................
Host Packet Descriptor Word 4 (HPD Word 4) .....................................................................
Host Packet Descriptor Word 5 (HPD Word 5) .....................................................................
Host Packet Descriptor Word 6 (HPD Word 6) .....................................................................
Host Packet Descriptor Word 7 (HPD Word 7) .....................................................................
Host Buffer Descriptor Word 0 (HBD Word 0) ......................................................................
Host Buffer Descriptor Word 1 (HBD Word 1) ......................................................................
Host Buffer Descriptor Word 2 (HBD Word 2) ......................................................................
29-1.
Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode
1311
29-2.
Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode
1311
29-3.
29-4.
29-5.
29-6.
29-7.
29-8.
29-9.
29-10.
29-11.
29-12.
29-13.
29-14.
29-15.
29-16.
29-17.
29-18.
29-19.
29-20.
29-21.
29-22.
29-23.
29-24.
29-25.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
SPRUH78A – December 2011
Submit Documentation Feedback
List of Tables
Copyright © 2011, Texas Instruments Incorporated
1312
1315
1319
1321
1322
1323
1324
1325
1326
1327
1328
1329
1329
1330
1331
1334
1335
1336
1336
1337
1337
1338
1339
1343
1344
1344
1359
1360
1362
1364
1385
1385
1386
1386
1386
1386
1387
1387
1388
1388
1388
63
www.ti.com
30-19. Host Buffer Descriptor Word 3 (HBD Word 3) ...................................................................... 1388
30-20. Host Buffer Descriptor Word 4 (HBD Word 4) ...................................................................... 1389
30-21. Host Buffer Descriptor Word 5 (HBD Word 5) ...................................................................... 1389
30-22. Host Buffer Descriptor Word 6 (HBD Word 6) ...................................................................... 1389
30-23. Host Buffer Descriptor Word 7 (HBD Word 7) ...................................................................... 1389
30-24. Teardown Descriptor Word 0 ......................................................................................... 1390
30-25. Teardown Descriptor Words 1-7...................................................................................... 1390
30-26. Allocation of Queues ................................................................................................... 1391
30-27. Interrupts Generated by the USB Controller ........................................................................ 1405
30-28. USB Interrupt Conditions .............................................................................................. 1405
30-29. USB Interrupts .......................................................................................................... 1408
30-30. Universal Serial Bus OTG (USB0) Registers ....................................................................... 1421
30-31. Revision Identification Register (REVID) Field Descriptions ...................................................... 1428
30-32. Control Register (CTRLR) Field Descriptions....................................................................... 1428
30-33. Status Register (STATR) Field Descriptions ........................................................................ 1429
30-34. Emulation Register (EMUR) Field Descriptions .................................................................... 1429
1430
30-36. Auto Request Register (AUTOREQ) Field Descriptions
1432
30-37.
1433
30-38.
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
30-66.
30-67.
64
.........................................................................
..........................................................
SRP Fix Time Register (SRPFIXTIME) Field Descriptions .......................................................
Teardown Register (TEARDOWN) Field Descriptions ............................................................
USB Interrupt Source Register (INTSRCR) Field Descriptions ..................................................
USB Interrupt Source Set Register (INTSETR) Field Descriptions ..............................................
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ...........................................
USB Interrupt Mask Register (INTMSKR) Field Descriptions ....................................................
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ..........................................
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions ........................................
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ..................................
USB End of Interrupt Register (EOIR) Field Descriptions.........................................................
Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions ......................................
Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions ......................................
Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions ......................................
Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions ......................................
Function Address Register (FADDR) Field Descriptions ..........................................................
Power Management Register (POWER) Field Descriptions ......................................................
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions ..............
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions .................................
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ...........................................
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ..........................................
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions ................................
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions .......................................
Frame Number Register (FRAME) Field Descriptions.............................................................
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions .......
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions ...............................
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ...............
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions ...............
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions ....................
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ..............
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ....................
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ...............
30-35. Mode Register (MODE) Field Descriptions
List of Tables
Copyright © 2011, Texas Instruments Incorporated
1433
1434
1435
1436
1437
1438
1439
1440
1441
1441
1442
1442
1443
1443
1444
1445
1446
1447
1447
1448
1449
1449
1450
1450
1451
1452
1453
1454
1455
1456
SPRUH78A – December 2011
Submit Documentation Feedback
www.ti.com
30-68. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions ............... 1457
30-69. Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions .................... 1458
30-70. Count 0 Register (COUNT0) Field Descriptions .................................................................... 1459
30-71. Receive Count Register (RXCOUNT) Field Descriptions ......................................................... 1459
30-72. Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ........................................... 1460
30-73. Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions .............................. 1460
30-74. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ............................... 1461
30-75. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ..................... 1461
..............................
30-77. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions .....................
30-78. Configuration Data Register (CONFIGDATA) Field Descriptions ................................................
30-79. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions..............................
30-80. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions..............................
30-81. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions..............................
30-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions..............................
30-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions..............................
30-84. Device Control Register (DEVCTL) Field Descriptions ............................................................
30-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions ...................................................
30-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions ...................................................
30-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ..........................................
30-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions ...........................................
30-89. Hardware Version Register (HWVERS) Field Descriptions .......................................................
30-90. Transmit Function Address (TXFUNCADDR) Field Descriptions ................................................
30-91. Transmit Hub Address (TXHUBADDR) Field Descriptions .......................................................
30-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................
30-93. Receive Function Address (RXFUNCADDR) Field Descriptions.................................................
30-94. Receive Hub Address (RXHUBADDR) Field Descriptions ........................................................
30-95. Receive Hub Port (RXHUBPORT) Field Descriptions .............................................................
30-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions .......................................
30-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ....................
30-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions ..............................................
30-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions.................
30-100. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ................
30-101. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ...........
30-102. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ...........
30-103. CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ...............................
30-104. CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions ....................................
30-105. Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions........................
30-106. Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ...............................
30-107. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions ......
30-108. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions ......
30-109. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions ......
30-110. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions ......
30-111. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions......
30-112. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ..................
30-113. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions......
30-114. Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions ....................................
30-115. Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions ....................................
30-116. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .....
30-76. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions
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1462
1463
1464
1465
1465
1466
1466
1467
1467
1468
1468
1469
1469
1470
1471
1471
1471
1472
1472
1472
1473
1473
1474
1474
1475
1476
1477
1478
1478
1480
1480
1481
1482
1483
1484
1484
1485
1485
1486
1486
1487
65
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30-117. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ............. 1488
30-118. Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ............................... 1489
30-119. Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions .............................. 1490
30-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions .............................. 1490
30-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions .............................. 1491
A-1.
66
Document Revision History ........................................................................................... 1493
List of Tables
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Preface
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Read This First
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components:
• ARM subsystem and associated memories
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
Code Composer Studio is a trademark of Texas Instruments.
ARM926EJ-S, Jazelle are trademarks of ARM Limited.
SPI is a trademark of Motorola, Inc..
SD is a trademark of SanDisk Corporation.
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Chapter 1
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Overview
Topic
1.1
1.2
1.3
1.4
1.5
...........................................................................................................................
Introduction ......................................................................................................
Block Diagram ..................................................................................................
DSP Subsystem ................................................................................................
ARM Subsystem ................................................................................................
DMA Subsystem ................................................................................................
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70
70
70
71
69
Introduction
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Introduction
The OMAP-L132 Applications Processor contains two primary CPU cores: an ARM RISC CPU for
general-purpose processing and systems control; and a powerful DSP to efficiently handle communication
and audio processing tasks. The OMAP-L132 Applications Processor consists of the following primary
components:
• ARM subsystem and associated memories
• DSP subsystem and associated memories
• A set of I/O peripherals
• A powerful DMA subsystem and SDRAM EMIF interface
1.2
Block Diagram
A block diagram for the OMAP-L132 Applications Processor is shown in Figure 1-1.
1.3
DSP Subsystem
The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of
internal memory (L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components.
1.4
ARM Subsystem
The ARM926EJ-S™ 32-bit RISC CPU in the ARM subsystem (ARMSS) acts as the overall system
controller. The ARM CPU performs general system control tasks, such as system initialization,
configuration, power management, user interface, and user command implementation. The ARM
Subsystem chapter describes the ARMSS components and system control functions that the ARM core
performs.
Figure 1-1. OMAP-L132 Applications Processor Block Diagram
ARM Subsystem
DSP Subsystem
ARM926EJ-S CPU
With MMU
C674x™
DSP CPU
4KB ETB
AET
JTAG Interface
System Control
Input
Clock(s)
PLL/Clock
Generator
w/OSC
GeneralPurpose
Timer (x4)
16KB
16KB
I-Cache D-Cache
Power/Sleep
Controller
RTC/
32-kHz
OSC
Pin
Multiplexing
32KB
L1 Pgm
32KB
L1 RAM
8KB RAM
(Vector Table)
256KB L2 RAM
64KB ROM
BOOT ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
(x2)
McASP
w/FIFO
Serial Interfaces
McBSP
(x2)
I2C
(x2)
Connectivity
Control Timers
ePWM
(x2)
eCAP
(x3)
UART
(x3)
SPI
(x2)
USB2.0
OTG Ctlr
PHY
EMAC
10/100
(MII/RMII)
MDIO
Shared
Memory
Customizable
Interface
128KB
RAM
PRU
Subsystem
External Memory Interfaces
MMC/SD
(8b)
(x2)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/mDDR
Memory
Controller
Note: Not all peripherals are available at the same time due to multiplexing.
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1.5
DMA Subsystem
The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more
information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter.
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Chapter 2
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ARM Subsystem
Topic
2.1
2.2
2.3
2.4
2.5
2.6
2.7
...........................................................................................................................
Introduction ......................................................................................................
Operating States/Modes .....................................................................................
Processor Status Registers ................................................................................
Exceptions and Exception Vectors ......................................................................
The 16-BIS/32-BIS Concept .................................................................................
16-BIS/32-BIS Advantages ..................................................................................
Co-Processor 15 (CP15) .....................................................................................
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75
76
77
77
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Introduction
2.1
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Introduction
This chapter describes the ARM subsystem and its associated memories. The ARM subsystem consists of
the following components:
• ARM926EJ-S™ 32-bit RISC CPU
• 16-KB Instruction cache
• 16-KB Data cache
• Memory Management Unit (MMU)
• Co-Processor 15 (CP15) to control MMU, cache, etc.
• Jazelle™ Java Accelerator
• ARM Internal Memory
– 8 KB RAM
– 64 KB built-in ROM
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32-bit ARM/16-bit THUMB instruction sets
– Fixed little-endian memory format
– Enhanced DSP instructions
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The
ARM926EJ-S processor targets multi-tasking applications where full memory management, high
performance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets, enabling
you to trade off between high performance and high code density. This includes features for efficient
execution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreter
without associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard architecture and provides
a complete high performance subsystem, including the following:
• An ARM926EJ-S integer core
• A Memory Management Unit (MMU)
• Separate instruction and data Advanced Microcontroller Bus Architecture (AHBA) Advanced High
Performance Bus (AHB) bus interfaces
NOTE: There is no TCM memory and interface on this device.
The ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM926EJ-S core includes NEON signal processing extensions to enhance 16-bit fixed-point
performance using a single-cycle 32 × 16 multiply-accumulate (MAC) unit. The ARM core also has 8 KB
RAM (typically used for vector table) and 64 KB ROM (for boot images) associated with it. The RAM/ROM
locations are not accessible by the DSP or any other master peripherals. Furthermore, the ARM has DMA
and CFG bus master ports via the AHB interface.
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Operating States/Modes
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2.2
Operating States/Modes
The ARM can operate in two states: ARM (32-bit) mode and THUMB (16-bit) mode. You can switch the
ARM926EJ-S processor between ARM mode and THUMB mode using the BX instruction.
The ARM can operate in the following modes:
• User mode (USR): Non-privileged mode, usually for the execution of most application programs.
• Fast interrupt mode (FIQ): Fast interrupt processing
• Interrupt mode (IRQ): Normal interrupt processing
• Supervisor mode (SVC): Protected mode of execution for operating systems
• Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort
• System mode (SYS): Privileged mode of execution for operating systems
• Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode.
You can only enter privileged modes (system or supervisor) from other privileged modes.
To enter supervisor mode from user mode, generate a software interrupt (SWI). An IRQ interrupt causes
the processor to enter the IRQ mode. An FIQ interrupt causes the processor to enter the FIQ mode.
Different stacks must be set up for different modes. The stack pointer (SP) automatically changes to the
SP of the mode that was entered.
2.3
Processor Status Registers
The processor status register (PSR) controls the enabling and disabling of interrupts and setting the mode
of operation of the processor. The 8 least-significant bits PSR[7:0] are the control bits of the processor.
PSR[27:8] are reserved bits and PSR[31:28] are status registers. The details of the control bits are:
• Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)
• Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)
• Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1) or ARM mode (T = 0)
• Bits 4:0 Mode: Controls the mode of operation of the processor
– PSR [4:0] = 10000 : User mode
– PSR [4:0] = 10001 : FIQ mode
– PSR [4:0] = 10010 : IRQ mode
– PSR [4:0] = 10011 : Supervisor mode
– PSR [4:0] = 10111 : Abort mode
– PSR [4:0] = 11011 : Undefined mode
– PSR [4:0] = 11111 : System mode
Status bits show the result of the most recent ALU operation. The details of status bits are:
• Bit 31 - N bit: Negative or less than
• Bit 30 - Z bit: Zero
• Bit 29 - C bit: Carry or borrow
• Bit 28 - V bit: Overflow or underflow
NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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Exceptions and Exception Vectors
2.4
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Exceptions and Exception Vectors
Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that
occur in an ARM system are given below:
• Reset exception: processor reset
• FIQ interrupt: fast interrupt
• IRQ interrupt: normal interrupt
• Abort exception: abort indicates that the current memory access could not be completed. The abort
could be a pre-fetch abort or a data abort.
• SWI interrupt: use software interrupt to enter supervisor mode.
• Undefined exception: occurs when the processor executes an undefined instruction
The exceptions in the order of highest priority to lowest priority are: reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction, and SWI. SWI and undefined instruction have the same priority. The ARM is
configured with the VINITHI signal set high (VINITHI = 1), such that the vector table is located at address
FFFF 0000h. This address maps to the beginning of the ARM local RAM (8 KB).
NOTE: The VINITHI signal is configurable by way of the register setting in CP15. However, it is not
recommended to set VINITHI = 0, as the device has no physical memory in the 0000 0000h
address region.
The default vector table is shown in Table 2-1.
Table 2-1. Exception Vector Table for ARM
76
Vector Offset Address
Exception
Mode on entry
I Bit State on Entry
F Bit State on Entry
0h
Reset
Supervisor
Set
Set
4h
Undefined instruction
Undefined
Set
Unchanged
8h
Software interrupt
Supervisor
Set
Unchanged
Ch
Pre-fetch abort
Abort
Set
Unchanged
10h
Data abort
Abort
Set
Unchanged
14h
Reserved
—
—
—
18h
IRQ
IRQ
Set
Unchanged
1Ch
FIQ
FIQ
Set
Set
ARM Subsystem
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The 16-BIS/32-BIS Concept
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2.5
The 16-BIS/32-BIS Concept
The key idea behind 16-BIS is that of a super-reduced instruction set. Essentially, the ARM926EJ
processor has two instruction sets:
• ARM mode or 32-BIS: the standard 32-bit instruction set
• THUMB mode or 16-BIS: a 16-bit instruction set
The 16-bit instruction length (16-BIS) allows the 16-BIS to approach twice the density of standard 32-BIS
code while retaining most of the 32-BIS’s performance advantage over a traditional 16-bit processor using
16-bit registers. This is possible because 16-BIS code operates on the same 32-bit register set as 32-BIS
code. 16-bit code can provide up to 65% of the code size of the 32-bit code and 160% of the performance
of an equivalent 32-BIS processor connected to a 16-bit memory system.
2.6
16-BIS/32-BIS Advantages
16-bit instructions operate with the standard 32-bit register configuration, allowing excellent
inter-operability between 32-BIS and 16-BIS states. Each 16-bit instruction has a corresponding 32-bit
instruction with the same effect on the processor model. The major advantage of a 32-bit architecture over
a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a
large address space efficiently. When processing 32-bit data, a 16-bit architecture takes at least two
instructions to perform the same task as a single 32-bit instruction. However, not all of the code in a
program processes 32-bit data (for example, code that performs character string handling), and some
instructions (like branches) do not process any data at all. If a 16-bit architecture only has 16-bit
instructions, and a 32-bit architecture only has 32-bit instructions, then the 16-bit architecture has better
code density overall, and has better than one half of the performance of the 32-bit architecture. Clearly,
32-bit performance comes at the cost of code density. The 16-bit instruction breaks this constraint by
implementing a 16-bit instruction length on a 32-bit architecture, making the processing of 32-bit data
efficient with compact instruction coding. This provides far better performance than a 16-bit architecture,
with better code density than a 32-bit architecture. The 16-BIS also has a major advantage over other
32-bit architectures with 16-bit instructions. The advantage is the ability to switch back to full 32-bit code
and execute at full speed. Thus, critical loops for applications such as fast interrupts and DSP algorithms
can be coded using the full 32-BIS and linked with 16-BIS code. The overhead of switching from 16-bit
code to 32-bit code is folded into sub-routine entry time. Various portions of a system can be optimized for
speed or for code density by switching between 16-BIS and 32-BIS execution, as appropriate.
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Co-Processor 15 (CP15)
2.7
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Co-Processor 15 (CP15)
The system control coprocessor (CP15) is used to configure and control instruction and data caches,
Tightly-Coupled Memories (TCMs), Memory Management Units (MMUs), and many system functions. The
CP15 registers are only accessible with MRC and MCR instructions by the ARM in a privileged mode like
supervisor mode or system mode.
2.7.1 Addresses in an ARM926EJ-S System
Three different types of addresses exist in an ARM926EJ-S system. They are listed in Table 2-2.
Table 2-2. Different Address Types in ARM System
Domain
ARM9EJ-S
Caches and MMU
TCM and AMBA Bus
Address type
Virtual Address (VA)
Modified Virtual Address (MVA)
Physical Address (PA)
An example of the address manipulation that occurs when the ARM9EJ-S core requests an instruction is
shown in Example 2-1
Example 2-1. Address Manipulation
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated to the MVA. The Instruction Cache (Icache) and Memory Management Unit (MMU) detect
the MVA.
If the protection check carried out by the MMU on the MVA does not abort and the MVA tag is in the Icache,
the instruction data is returned to the ARM9EJ-S core.
If the protection check carried out by the MMU on the MVA does not abort, and the MVA tag is not in the
cache, then the MMU translates the MVA to produce the PA.
NOTE: See the Programmers Model of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
2.7.2 Memory Management Unit (MMU)
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as
SymbianOS, WindowsCE, and Linux. A single set of two level page tables stored in main memory controls
the address translation, permission checks, and memory region attributes for both data and instruction
accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information
held in the page tables.
The MMU features are as follows:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access protection scheme.
• Mapping sizes are 1 MB (sections), 64 KB (large pages), 4 KB (small pages) and 1 KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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2.7.3 Caches and Write Buffer
The ARM926EJ-S processor includes:
• An Instruction cache (Icache)
• A Data cache (Dcache)
• A write buffer
The size of the data cache is 16 KB, instruction cache is 16 KB, and write buffer is 17 bytes.
The caches have the following features:
• Virtual index, virtual tag, addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32 bytes per line), and two
dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
• Perform critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown and controlling cache pollution.
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the
TAGRAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations to provide efficient invalidation of the following:
– The entire Dcache or Icache
– Regions of the Dcache or Icache
– The entire Dcache
– Regions of virtual memory
• They also provide operations for efficient cleaning and invalidation of the following:
– The entire Dcache
– Regions of the Dcache
– Regions of virtual memory
The write buffer is used for all writes to a non-cachable bufferable region, write-through region, and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines.
The main write buffer has a 16-word data buffer and a four-address buffer.
The Dcache write-back has eight data word entries and a single address entry.
The MCR drain write buffer enables both write buffers to be drained under software control.
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be
put into a low power state until an interrupt occurs.
NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM),
downloadable from http://infocenter.arm.com/help/index.jsp for more detailed information.
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Chapter 3
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DSP Subsystem
Topic
3.1
3.2
3.3
3.4
...........................................................................................................................
Introduction ......................................................................................................
TMS320C674x Megamodule ................................................................................
Memory Map .....................................................................................................
Advanced Event Triggering (AET) .......................................................................
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Introduction
3.1
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Introduction
The DSP subsystem (Figure 3-1) includes TI’s standard TMS320C674x megamodule and several blocks
of internal memory (L1P, L1D, and L2). This chapter provides an overview of the DSP subsystem and the
following considerations associated with it:
• Memory mapping
• Interrupts
• Power management
For more information on the TMS320C674x megamodule, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5), the TMS320C674x DSP CPU and Instruction Set Reference Guide
(SPRUFE8), and the TMS320C674x DSP Cache User’s Guide (SPRUG82).
Figure 3-1. TMS320C674x Megamodule Block Diagram
32K bytes
L1P RAM/
cache
256K bytes
L2 RAM
256
256
1M bytes
L2 ROM
256
256
Cache control
Memory protect
Bandwidth Mgmt
Cache control
Memory protect
Bandwidth Mgmt
L1P
256
256
256
256
Instruction fetch
Power down
Interrupt
Controller
C674x
Fixed/floating point CPU
Register
file A
Register
file B
64
64
Bandwidth Mgmt
Memory protect
Cache control
8x32
82
IDMA
256
Port
EMC
L1D
MDMA Port
64
32K bytes
L1D RAM/
cache
L2
64
32
Configuration
peripherals
bus
SDMA Port
64
64
High performance
switch fabric
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3.2
TMS320C674x Megamodule
The C674x megamodule (Figure 3-1) consists of the following components:
• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
For more information about each of these controllers, see the TMS320C674x DSP Megamodule
Reference Guide (SPRUFK5).
3.2.1 Internal Memory Controllers
The C674x megamodule implements a two-level internal cache-based memory architecture with external
memory support. Level 1 memory (L1) is split into separate program memory (L1P memory) and data
memory (L1D memory). L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also
be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory
locations. The internal direct memory access controller (IDMA) manages DMA among the L1P, L1D, and
L2 memories.
3.2.2 Internal Peripherals
The C674x megamodule includes the following internal peripherals:
• DSP interrupt controller (INTC)
• DSP power-down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA) controller
This section briefly describes the INTC, PDC, BWM, and IDMA controller. For more information on these
internal peripherals, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
3.2.2.1
Interrupt Controller (INTC)
The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The INTC
maps DSP device events to 12 CPU interrupts. All DSP device events are listed in Table 3-1. The INTC is
fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
The interrupt events listed in Table 3-1 are for the DSP interrupt controller (INTC) only. For the ARM
interrupt controller (AINTC) event mappings, see the ARM Interrupt Controller (AINTC) chapter.
Table 3-1. DSP Interrupt Map
Event
Interrupt Name
Source
0
EVT0
C674x Interrupt Control 0
1
EVT1
C674x Interrupt Control 1
2
EVT2
C674x Interrupt Control 2
3
EVT3
C674x Interrupt Control 3
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Table 3-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
4
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
5
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
6
PRU_EVTOUT0
PRUSS Interrupt
7
EHRPWM0
HiResTimer/PWM0 Interrupt
8
EDMA3_0_CC0_INT1
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
15
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
16
MMCSD0_INT1
MMCSD0 SDIO Interrupt
17
PRU_EVTOUT1
PRUSS Interrupt
18
EHRPWM1
HiResTimer/PWM1 Interrupt
19
USB0_INT
USB0 (USB2.0) Interrupt
—
Reserved
22
PRU_EVTOUT2
PRUSS Interrupt
23
EHRPWM1TZ
HiResTimer/PWM1 Trip Zone Interrupt
24
—
Reserved
25
T64P2_TINTALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
26
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
27
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
28
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
29
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
30
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
31
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
32
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
33
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
34
—
Reserved
35
PRU_EVTOUT3
PRUSS Interrupt
36
IIC0_INT
I2C0 Interrupt
37
SPI0_INT
SPI0 Interrupt
38
UART0_INT
UART0 Interrupt
39
PRU_EVTOUT5
PRUSS Interrupt
40
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
IIC1_INT
I2C1 Interrupt
43
SPI1_INT
SPI1 Interrupt
44
PRU_EVTOUT6
PRUSS Interrupt
45
ECAP0
ECAP0 Interrupt
46
UART_INT1
UART1 Interrupt
47
ECAP1
ECAP1 Interrupt
48
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
PRU_EVTOUT7
PRUSS Interrupt
51
ECAP2
ECAP2 Interrupt
20-21
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Table 3-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
52
GPIO_B3INT
GPIO Bank 3 Interrupt
53
MMCSD1_INT1
MMCSD1 SDIO Interrupt
54
GPIO_B4INT
GPIO Bank 4 Interrupt
55
EMIFA_INT
EMIFA Interrupt
56
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrrupt
57
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrrupt
58
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrrupt
59
GPIO_B5INT
GPIO Bank 5 Interrupt
60
DDR2_MEMERR
DDR2 Memory Error Interrupt
61
MCASP0_INT
McASP0 Combined RX/TX Interrupt
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
RTC Combined Interrupt
64
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
65
GPIO_B0INT
GPIO Bank 0 Interrupt
66
PRU_EVTOUT4
PRUSS Interrupt
67
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
68
MMCSD1_INT0
MMCSD1 MMC/SD Interrupt
69
UART2_INT
UART2 Interrupt
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
GPIO Bank 7 Interrupt
73
—
Reserved
74
PROTERR
SYSCFG Protection Shared Interrupt
75
GPIO_B8INT
GPIO Bank 8 Interrupt
—
Reserved
78
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
79
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
80
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
81
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
82
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
83
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
84
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
85
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
86
T64P3_TINTALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
87
MCBSP0_RINT
McBSP0 Receive Interrupt
88
MCBSP0_XINT
McBSP0 Transmit Interrupt
89
MCBSP1_RINT
McBSP1 Receive Interrupt
90
MCBSP1_XINT
McBSP1 Transmit Interrupt
91
EDMA3_1_CC0_INT1
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
92
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrrupt
93
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrrupt
—
Reserved
96
INTERR
C674x-Interrupt Control
97
EMC_IDMAERR
C674x-EMC
—
Reserved
PMC_ED
C674x-PMC
—
Reserved
76-77
94-95
98-112
113
114-115
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Table 3-1. DSP Interrupt Map (continued)
Event
Interrupt Name
Source
116
UMC_ED1
C674x-UMC
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
3.2.2.1.1 Interrupt Controller Registers
For more information on the DSP interrupt controller (INTC) registers, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
3.2.2.1.2 NMI Interrupt
In addition to the interrupts listed in Table 3-1, the DSP also supports a special interrupt that behaves
more like an exception, non-maskable interrupt (NMI). The NMI interrupt is controlled by two registers in
the System Configuration Module, the chip signal register (CHIPSIG) and the chip signal clear register
(CHIPSIG_CLR).
The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. The NMI interrupt is cleared
by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. For more information on CHIPSIG and
CHIPSIG_CLR, see the System Configuration (SYSCFG) Module chapter.
3.2.2.2
Power-Down Controller (PDC)
The C674x megamodule includes a power-down controller (PDC). The PDC can power-down all of the
following components of the C674x megamodule and internal memories of the DSP subsystem:
• C674x CPU
• Level 1 program memory controller (PMC)
• Level 1 data memory controller (DMC)
• Level 2 unified memory controller (UMC)
• Extended memory controller (EMC)
• Internal direct memory access (IDMA) controller
• L1P memory
• L1D memory
• L2 memory
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This device supports the static power-down feature from the C674x megamodule. The TMS320C674x
DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail.
• Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and
all internal memories immediately upon command from software.
Static power-down (clock gating) affects all components of the C674x megamodule and all internal
memories. Software can initiate static power-down by way of a register bit in the power-down controller
command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
3.2.2.3
Bandwidth Manager (BWM)
The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the
requesters for resources, which include the following:
• EDMA3-initiated DMA transfers (and resulting coherency operations)
• DSP subsystem IDMA-initiated transfers (and resulting coherency operations)
• Programmable cache coherency operations
– Block based coherency operations
– Global coherency operations
• CPU direct-initiated transfers
– Data access (load/store)
– Program access
The resources include the following:
• L1P memory
• L1D memory
• L2 memory
• Resources outside of the C674x megamodule: external memory, on-chip peripherals, registers
Since any given requestor could potentially block a resource for extended periods of time, the bandwidth
manager is implemented to assure fairness for all requesters.
The bandwidth manager implements a weighted-priority-driven bandwidth allocation. Each requestor
(EDMA3, DSP subsystem IDMA, CPU, etc.) is assigned a priority level on a per-transfer basis. The
programmable priority level has a single meaning throughout the system. There are a total of nine priority
levels, where priority zero is the highest priority and priority eight is the lowest priority. When requests for
a single resource contend, access is granted to the highest-priority requestor. When the contention occurs
for multiple successive cycles, a contention counter assures that the lower-priority requestor gets access
to the resource every 1 out of n arbitration cycles, where n is programmable. A priority level of -1
represents a transfer whose priority has been increased due to expiration of the contention counter or a
transfer that is fixed as the highest-priority transfer to a given resource.
3.2.2.4
Internal DMA (IDMA) Controller
The IDMA controller performs fast block transfers between any two memory locations local to the C674x
megamodule. Local memory locations are defined as those in Level 1 program (L1P), Level 1 data (L1D),
and Level 2 (L2) memories, or in the external peripheral configuration (CFG) port. The IDMA cannot
transfer data to or from the internal DSP memory-mapped register space. The IDMA is fully described in
the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
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Memory Map
3.3
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Memory Map
Refer to your device-specific data manual for the addresses of the memory-map registers.
3.3.1 DSP Internal Memory
See the System Memory chapter for a description of the DSP internal memory.
3.3.2 External Memory
See the System Interconnect chapter and the System Memory chapter for a description of the additional
memory and peripherals that the DSP has access to.
3.4
Advanced Event Triggering (AET)
The C674x megamodule supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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System Interconnect
Topic
4.1
4.2
...........................................................................................................................
Page
Introduction ...................................................................................................... 90
System Interconnect Block Diagram .................................................................... 91
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Introduction
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Introduction
The DSP, the ARM, the Programmable Real-Time Unit (PRU) subsystem, the EDMA3 transfer controllers,
and the device peripherals are interconnected through a switch fabric architecture (see Section 4.2). The
switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. The SCRs
establish low-latency connectivity between master peripherals and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through the SCRs, the DSP can send data to the EMIF without affecting a
data transfer between a device peripheral and internal shared memory. Bridges are mainly used to
perform bus-width conversion as well as bus operating frequency conversion.
The DSP, the ARM, the PRU subsystem, the EDMA3 transfer controllers, and the various device
peripherals can be classified into two categories: master peripherals and slave peripherals.
Master peripherals are typically capable of initiating read and write transfers in the system and do not rely
on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include
the DSP, the ARM, the EDMA3 transfer controllers, EMAC, PRU subsystem, and USB DMAs. Not all
master peripherals may connect to all slave peripherals. The supported connections are designated by an
X in Table 4-1.
Table 4-1. OMAP-L132 Applications Processor System Interconnect Matrix
Masters
Master
Default
Priority
ARM
RAM
DSP
SDMA
EMIFA
DDR2/mD
DR
128K
RAM
EDMA3_0_
TC0/TC1
EDMA3_1_
TC0
Peripheral
Group (1)
EDMA3_0_CC0
0
EDMA3_1_CC0
0
EDMA3_0_TC0
0
X
X
X
X
X
X
X
EDMA3_0_TC1
0
X
X
X
X
X
X
X
PRU0
0
X
X
X
X
X
X
X
PRU1
0
X
X
X
X
X
X
X
ARM I
2
X
X
X
X
X
X
ARM D
2
X
X
X
X
X
X
X
X
X
DSP CFG
2
X
X
X
DSP MDMA
2
EDMA3_1_TC0
4
X
X
X
EMAC
4
USB2.0
4
(1)
90
Slaves
ARM
ROM,
AINTC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Peripheral group: SYSCFG, EMAC, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, GPIO, I2C0, I2C1, McASP0, McBSP0,
McBSP1, MDIO, MMC/SD0, MMC/SD1, PLLC0, PLLC1, PRU RAM0, PRU RAM1, PRU Config, PSC0, PSC1, RTC, SPI0, SPI1,
TIMER64P0, TIMER64P1, TIMER64P2, TIMER64P3, EDMA3_0_CC0, EDMA3_1_CC0, UART0, UART1, UART2, USB0
(USB2.0).
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4.2
System Interconnect Block Diagram
Figure 4-1 shows a system interconnect block diagram.
Figure 4-1. System Interconnect Block Diagram
USB0 VBUSP
DSP SDMA (L1D/L2)
USB0 CDMA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
SCR F1
EMAC
SCR F0
BR F0
BR F6
SCR F4
128 KB
Shared RAM
MPU1
BR F1
SCR F3
MPU2
DDR2/mDDR
DSP MDMA
EDMA3_0_TC0
EDMA3_0_TC1
rd
EDMA3_0_CC1
wr
SCR1
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
rd
EDMA3_0_CC1
wr
EDMA3_1_CC0
EDMA3_1_TC0
PSC0
rd
SCR5
wr
SCR F5
USB0 Cfg
PLLC0
MMC/SD1
SYSCFG0
BR5
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 2 Clock Domain
SYSCFG1
Clock Domain: SYSCLK6 [CPU/1 Synchronous]
ARM-I
BR3
BR1
SCR0
ARM-D
EMAC
Timer64P0
BR4
SCR6
BR2
EMAC MDIO
Timer64P1
PLLC1
I2C0
SCR F6
RTC
BR0
BR6
GPIO
PSC1
I2C1
BR8
Async 1 Clock Domain
AINTC
BR7
BR F3
EMIFA
Clock Domain: SYSCLK4 [CPU/4 Synchronous]
Async 3 [PLL1] Clock Domain
PRU CFG
DSP CFG
McBSP0
ARM ROM
PRU0
McBSP1
ARM RAM
PRU1
BR F4
SCR F7
UART1
UART2
SCR2
MMC/SD0
SCR4
McASP0
SPI0
UART0
Legend:
32-bit BUS
64-bit BUS
eHRPWM0
EDMA3_0_TC0
IP Module
Synchronous Bridge
Asynchronous Bridge
SCR
eHRPWM1
EDMA3_0_TC1
Timer64P2
BR F5
SCR F8
Timer64P3
eCAP0
eCAP1
Paths with dashed lines cross the subchip boundary
eCAP2
SPI1
EDMA3_0_CC0
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System Memory
Topic
5.1
5.2
5.3
5.4
5.5
5.6
5.7
...........................................................................................................................
Introduction ......................................................................................................
ARM Memories ..................................................................................................
DSP Memories ..................................................................................................
Shared RAM Memory .........................................................................................
External Memories .............................................................................................
Internal Peripherals ...........................................................................................
Peripherals .......................................................................................................
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94
94
94
94
95
95
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This device has multiple on-chip/off-chip memories and several external device interfaces associated with
its two CPUs and various subsystems. To help simplify software development, a unified memory-map is
used wherever possible to maintain a consistent view of device resources across all masters.
For details on the memory addresses, actual memory supported and accessibility by various bus masters,
see the detailed memory-map information in the device-specific data manual.
5.2
ARM Memories
The configuration for the ARM internal memory is:
• 8 KB ARM local RAM
• 64 KB ARM local ROM
• 16 KB Instruction Cache and 16 KB Data cache
The ARM RAM/ROM are only accessible by ARM.
5.3
DSP Memories
The DSP internal memories are accessible by the ARM and other master peripherals (as dictated by the
connectivity matrix) via the system interconnect through the DSP SDMA port.
The DSP internal memory consists of L1P, L1D, and L2. The DSP internal memory configuration is:
• L1P memory includes 32 KB of RAM. The DSP program memory controller (PMC) allows you to
configure part or all of the L1P RAM as normal program RAM or as cache. You can configure cache
sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB
cache.
• L1D memory includes 32 KB of RAM. The DSP data memory controller (DMC) allows you to configure
part of the L1D RAM as normal data RAM or as cache. You can configure cache sizes of 0 KB, 4 KB,
8 KB, 16 KB, or 32 KB of the 32 KB of RAM. The default configuration is 32 KB cache.
• L2 memory includes 256 KB of RAM. The DSP unified memory controller (UMC) allows you to
configure part or all of the L2 RAM as normal RAM or as cache. You can configure cache sizes of 0
KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, or 256 KB of the 256 KB of RAM. The default
configuration is 256 KB normal RAM.
• L2 memory also includes 1024 KB of ROM.
5.4
Shared RAM Memory
This device also offers an on-chip 128-KB shared single-port RAM, apart from the ARM and the DSP
internal memories. This shared RAM is accessible by both the ARM and the DSP, and is also accessible
by several master peripherals. Writes to this RAM by all masters is atomic.
5.5
External Memories
This device has two external memory interfaces that provide multiple external memory options accessible
by the CPU and master peripherals:
• EMIF:
– 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM,
NAND Flash, and NOR Flash (up to 4 devices)
– 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices)
– 16-bit SDRAM with 128-MB address space
• DDR2/mDDR memory controller:
– 16-bit DDR2 with up to 512-MB memory address space
– 16-bit mDDR with up to 256-MB memory address space
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5.6
Internal Peripherals
The following peripherals are internal to the DSP subsystem and are only accessible to the DSP:
• DSP interrupt controller (INTC)
• DSP power down controller (PDC)
• Bandwidth manager (BWM)
• Internal DMA (IDMA)
For more information on the internal peripherals, see the TMS320C674x DSP Megamodule Reference
Guide (SPRUFK5).
The peripheral only accessible by the ARM is the ARM interrupt controller (AINTC). For more information
on the AINTC, see the ARM Interrupt Controller (AINTC) chapter.
5.7
Peripherals
The ARM and the DSP have access to all peripherals. This also includes system modules like the PLL
controller (PLLC), the power and sleep controller (PSC), and the system configuration module (SYSCFG).
See the device-specific data manual for the complete list of peripherals supported on your device.
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Chapter 6
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Memory Protection Unit (MPU)
Topic
6.1
6.2
6.3
...........................................................................................................................
Page
Introduction ...................................................................................................... 98
Architecture ...................................................................................................... 99
MPU Registers ................................................................................................ 104
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This device supports two memory protection units (MPU1 and MPU2). MPU1 supports the 128KB RAM
and MPU2 supports the DDR2/mDDR SDRAM.
6.1.1 Purpose of the MPU
The memory protection unit (MPU) is provided to manage access to memory. The MPU allows you to
define multiple ranges and limit access to system masters based on their privilege ID. The MPU can
record a detected fault, or invalid access, and notify the system through an interrupt.
6.1.2 Features
The MPU supports the following features:
• Supports multiple programmable address ranges
• Supports 0 or 1 fixed range
• Supports read, write, and execute access privileges
• Supports privilege ID associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• Supports L1/L2 cache accesses
• Supports protection of its own registers
6.1.3 Block Diagram
Figure 6-1 shows a block diagram of the MPU. An access to a protected memory must pass through the
MPU. During an access, the MPU checks the memory address on the input data bus against fixed and
programmable ranges. If allowed, the transfer is passed unmodified to the output data bus. If the transfer
fails the protection check then the MPU does not pass the transfer to the output bus but rather services
the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor
as well as generating an interrupt about the fault. The MPU generates two interrupts: an address error
interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).
Figure 6-1. MPU Block Diagram
MPU
Input
Data
Bus
Protection
Checks
Output
Data
Bus
MPU_ADDR_ERR_INT
MMRs
MPU_PROT_ERR_INT
MPU Register Bus
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6.1.4 MPU Default Configuration
Two MPUs are supported on the device, one for the 128KB RAM and one for the DDR2/mDDR SDRAM.
Table 6-1 shows the memory regions protected by each MPU. Table 6-2 shows the configuration of each
MPU.
Table 6-1. MPU Memory Regions
Memory Region
Unit
Memory Protection
Start Address
MPU1
128KB RAM
8000 0000h
End Address
8001 FFFFh
MPU2
DDR2/mDDR SDRAM
C000 0000h
DFFF FFFFh
Table 6-2. MPU Default Configuration
Setting
MPU1
MPU2
Assume allowed
Assume allowed
Number of allowed IDs supported
12
12
Number of fixed ranges supported
1
0
Number of programmable ranges supported
6
12
1 KB granularity
64 KB granularity
Default permission
Compare width
6.2
Architecture
6.2.1 Privilege Levels
The privilege level of a memory access determines what level of permissions the originator of the memory
access might have. Two privilege levels are supported: supervisor and user.
Supervisor level is generally granted access to peripheral registers and the memory protection
configuration. User level is generally confined to the memory spaces that the OS specifically designates
for its use.
ARM and DSP CPU instruction and data accesses have a privilege level associated with them. The
privilege level is inherited from the code running on the CPU. See the TMS320C674x DSP CPU and
Instruction Set Reference Guide (SPRUFE8) for more details on privilege levels of the DSP and ARM
CPU.
Table 6-3 shows the privilege ID of the CPU and every mastering peripheral. Table 6-3 also shows the
privilege level (supervisor vs. user) and access type (instruction read vs. data/DMA read or write) of each
master on the device. In some cases, a particular setting depends on software being executed at the time
of the access or the configuration of the master peripheral.
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Table 6-3. Device Master Settings
Master
Privilege ID
Privilege Level
Access Type
EDMA3_0_CC0
Inherited
Inherited
DMA
EDMA3_0_TC0 and EDMA3_0_TC1
Inherited
Inherited
DMA
EDMA3_1_CC0
Inherited
Inherited
DMA
EDMA3_1_TC0
Inherited
Inherited
DMA
ARM (instruction access)
0
Software dependant
Instruction
ARM (data access)
0
Software dependant
Data
DSP
1
Software dependant
Software dependant
PRU0/PRU1
2
Supervisor
DMA
EMAC
4
Supervisor
Data/DMA
USB2.0
6
Supervisor
DMA
6.2.2 Memory Protection Ranges
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory. One of the programmable
address ranges could be used to detect accesses to this unpopulated memory.
The MPU divides its assigned memory into address ranges. Each MPU can support one fixed address
range and multiple programmable address ranges. The fixed address range is configured to an exact
address. The programmable address range allows software to program the start and end addresses.
Each address range has the following set of registers:
• Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending
address of the address range.
• Memory protection page attribute register (MPPA): Use to program the permission settings of the
address range.
It is allowed to configure ranges such that they overlap each other. In this case, all the overlapped ranges
must allow the access, otherwise the access is not allowed. The final permissions given to the access are
the lowest of each type of permission from any hit range.
Addresses not covered by a range are either allowed or disallowed based on the configuration of the
MPU. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the
ASSUME_ALLOWED bit in the configuration register (CONFIG).
6.2.3 Permission Structures
The MPU defines a per-range permission structure with three permission fields in a 32-bit permission
entry. Figure 6-2 shows the structure of a permission entry.
Figure 6-2. Permission Fields
31
22
21
20
19
AID11
AID10
AID9
5
4
3
Reserved
15
14
13
12
11
10
100
AID4
AID3
AID2
9
8
6
Reserved
AID1
AID0
17
16
AID8
AID7
AID6
2
1
0
UW
UX
Allowed IDs
Allowed IDs
AID5
18
AIX
Access Types
SR
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SW
SX
UR
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6.2.3.1
Requestor-ID Based Access Controls
Each master on the device has an N-bit code associated with it that identifies it for privilege purposes.
This privilege ID accompanies all memory accesses made on behalf of that master. That is, when a
master triggers a memory access command, the privilege ID will be carried alongside the command.
Each memory protection range has an allowed ID (AID) field associated with it that indicates which
requestors may access the given address range. The MPU maps the privilege IDs of all the possible
requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA).
• AID0 through AID11 are used to specify the allowed privilege IDs.
• An additional allowed ID bit, AIDX, captures access made by all privilege IDs not covered by AID0
through AID11.
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies
access to the corresponding requestor.
6.2.3.2
Request-Type Based Permissions
The memory protection model defines three fundamental functional access types: read, write, and
execute. Read and write refer to data accesses -- accesses originating via the load/store units on the CPU
or via a master peripheral. Execute refers to accesses associated with an instruction fetch.
The memory protection model allows controlling read, write, and execute permissions independently for
both user and supervisor mode. This results in six permission bits, listed in Table 6-4. For each bit, a 1
permits the access type and a 0 denies access. For example, UX = 1 means that User Mode may execute
from the given page. The memory protection unit allows you to specify all six of these bits separately; 64
different encodings are permitted altogether, although programs might not use all of them.
Table 6-4. Request Type Access Controls
Bit
Field
Description
5
SR
Supervisor may read
4
SW
Supervisor may write
3
SX
Supervisor may execute
2
UR
User may read
1
UW
User may write
0
UX
User may execute
6.2.4 Protection Check
During a memory access, the MPU checks if the address range of the input transfer overlaps one of the
address ranges. When the input transfer address is within a range the transfer parameters are checked
against the address range permissions.
The MPU first checks the transfers privilege ID against the AID settings. If the AID bit is 0, then the range
will not be checked; if the AID bit is 1, then the transfer parameters are checked against the memory
protection page attribute register (MPPA) values to detect an allowed access.
For non-debug accesses, the read, write, and execute permissions are also checked. There is a set of
permissions for supervisor mode and a set for user mode. For supervisor mode accesses, the SR, SW,
and SX bits are checked. For user mode accesses, the UR, UW, and UX bits are checked.
If the transfer address range does not match any address range then the transfer is either allowed or
disallowed based on the configuration of the MPU. The MPU can be configured for assumed allowed or
assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register
(CONFIG).
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In the case that a transfer spans multiple address ranges, all the overlapped ranges must allow the
access, otherwise the access is not allowed. The final permissions given to the access are the lowest of
each type of permission from any hit range. Therefore, if a transfer matches 2 ranges, one that is RW and
one that is RX, then the final permission is just R.
The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see
Section 6.2.5 for more details.
6.2.5 DSP L1/L2 Cache Controller Accesses
A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory
protection to be enforced by the DSP level. This is because a subsequent memory access that hits in the
cache does not pass through the MPU. Instead the memory access is serviced directly by the L1/L2
memory controllers.
During a cache memory read, the permission settings stored in the memory protection page attribute
registers (MPPA) are passed to the L1/L2 memory controllers along with the read data. The permissions
settings returned by the MPU are taken from MPPA that covers the address range of the original
request—only the SR, SW, SX, UR, UW, and UX bits are passed. If the request address is covered by
multiple address ranges, then the returned value is the logical-AND of all MPPA permissions. If the
transfer address range is not covered by an address range then the transfer is either allowed or
disallowed based on the configuration of the MPU.
6.2.6 MPU Register Protection
Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page
attribute registers (MPPA) is also protected. All non-debug writes must be by a supervisor entity. A
protection fault can occur from a register write with invalid permissions and this triggers an interrupt just
like a memory access.
Faults are not recorded (nor interrupts generated) for debug accesses.
6.2.7 Invalid Accesses and Exceptions
When a transfer fails the protection check, the MPU does not pass the transfer to the output bus. The
MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.
The behavior of the MPU depends on whether the access was a read or a write:
• For a read: The MPU returns 0s, a permission value is 0 (no access allowed), a protection error status.
• For a write: The MPU receives all the write data and returns a protection error status.
The MPU captures system faults due to addressing or protection violations in its registers. The MPU can
store the fault information for only one fault, so the first detected fault is recorded into the fault registers
and an interrupt is generated. Software must use the fault clear register (FLTCLR) to clear the fault status
so that another fault can be recorded. The MPU will not record another fault nor generate another interrupt
until the existing fault has been cleared. Also, additional faults will be ignored. Faults are not recorded (no
interrupts generated) for debug accesses.
6.2.8 Reset Considerations
After reset, the memory protection page attribute registers (MPPA) default to 0. This disables all protection
features.
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6.2.9 Interrupt Support
6.2.9.1
Interrupt Events and Requests
The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection
interrupt (MPU_PROT_ERR_INT). The MPU_ADDR_ERR_INT is generated when there is an addressing
violation due to an access to a non-existent location in the MPU register space. The
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined
ranges or to the MPU registers.
The transfer parameters that caused the violation are saved in the MPU registers.
6.2.9.2
Interrupt Multiplexing
The interrupts from both MPUs are combined with the boot configuration module into a single interrupt
called MPU_BOOTCFG_ERR. The combined interrupt is routed to the ARM and DSP interrupt controllers.
Table 6-5 shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR.
Table 6-5. MPU_BOOTCFG_ERR Interrupt Sources
Interrupt
Source
MPU1_ADDR_ERR_INT
MPU1 address error interrupt
MPU1_PROT_ERR_INT
MPU1 protection interrupt
MPU2_ADDR_ERR_INT
MPU2 address error interrupt
MPU2_PROT_ERR_INT
MPU2 protection interrupt
BOOTCFG_ADDR_ERR
Boot configuration address error
BOOTCFG_PROT_ERR
Boot configuration protection error
6.2.10 Emulation Considerations
Memory and MPU registers are not protected against emulation accesses.
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MPU Registers
There are two MPUs on the device. Each MPU contains a set of memory-mapped registers.
Table 6-7 lists the memory-mapped registers for the MPU2.
Table 6-6. Memory Protection Unit 1 (MPU1) Registers
Address
Acronym
Register Description
01E1 4000h
REVID
Revision identification register
Section 6.3.1
Section
01E1 4004h
CONFIG
Configuration register
Section 6.3.2
01E1 4010h
IRAWSTAT
Interrupt raw status/set register
Section 6.3.3
01E1 4014h
IENSTAT
Interrupt enable status/clear register
Section 6.3.4
01E1 4018h
IENSET
Interrupt enable set register
Section 6.3.5
01E1 401Ch
IENCLR
Interrupt enable clear register
01E1 4200h
PROG1_MPSAR
Programmable range 1 start address register
Section 6.3.10.1
01E1 4204h
PROG1_MPEAR
Programmable range 1 end address register
Section 6.3.11.1
01E1 4208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 4210h
PROG2_MPSAR
Programmable range 2 start address register
Section 6.3.10.1
01E1 4214h
PROG2_MPEAR
Programmable range 2 end address register
Section 6.3.11.1
01E1 4218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 4220h
PROG3_MPSAR
Programmable range 3 start address register
Section 6.3.10.1
01E1 4224h
PROG3_MPEAR
Programmable range 3 end address register
Section 6.3.11.1
01E1 4228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 4230h
PROG4_MPSAR
Programmable range 4 start address register
Section 6.3.10.1
01E1 4234h
PROG4_MPEAR
Programmable range 4 end address register
Section 6.3.11.1
01E1 4238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 4240h
PROG5_MPSAR
Programmable range 5 start address register
Section 6.3.10.1
01E1 4244h
PROG5_MPEAR
Programmable range 5 end address register
Section 6.3.11.1
01E1 4248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 4250h
PROG6_MPSAR
Programmable range 6 start address register
Section 6.3.10.1
01E1 4254h
PROG6_MPEAR
Programmable range 6 end address register
Section 6.3.11.1
01E1 4258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
Section 6.3.12
01E1 4300h
FLTADDRR
Fault address register
Section 6.3.13
01E1 4304h
FLTSTAT
Fault status register
Section 6.3.14
01E1 4308h
FLTCLR
Fault clear register
Section 6.3.15
Section 6.3.6
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Table 6-7. Memory Protection Unit 2 (MPU2) Registers
Address
Acronym
Register Description
01E1 5000h
REVID
Revision identification register
Section 6.3.1
01E1 5004h
CONFIG
Configuration register
Section 6.3.2
01E1 5010h
IRAWSTAT
Interrupt raw status/set register
Section 6.3.3
01E1 5014h
IENSTAT
Interrupt enable status/clear register
Section 6.3.4
01E1 5018h
IENSET
Interrupt enable set register
Section 6.3.5
01E1 501Ch
IENCLR
Interrupt enable clear register
Section 6.3.6
01E1 5100h
FXD_MPSAR
Fixed range start address register
Section 6.3.7
01E1 5104h
FXD_MPEAR
Fixed range end address register
Section 6.3.8
01E1 5108h
FXD_MPPA
Fixed range memory protection page attributes register
01E1 5200h
PROG1_MPSAR
Programmable range 1 start address register
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Section
Section 6.3.9
Section 6.3.10.2
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Table 6-7. Memory Protection Unit 2 (MPU2) Registers (continued)
Address
Acronym
Register Description
01E1 5204h
PROG1_MPEAR
Programmable range 1 end address register
01E1 5208h
PROG1_MPPA
Programmable range 1 memory protection page attributes register
01E1 5210h
PROG2_MPSAR
Programmable range 2 start address register
Section 6.3.10.2
01E1 5214h
PROG2_MPEAR
Programmable range 2 end address register
Section 6.3.11.2
01E1 5218h
PROG2_MPPA
Programmable range 2 memory protection page attributes register
01E1 5220h
PROG3_MPSAR
Programmable range 3 start address register
Section 6.3.10.2
01E1 5224h
PROG3_MPEAR
Programmable range 3 end address register
Section 6.3.11.2
01E1 5228h
PROG3_MPPA
Programmable range 3 memory protection page attributes register
01E1 5230h
PROG4_MPSAR
Programmable range 4 start address register
Section 6.3.10.2
01E1 5234h
PROG4_MPEAR
Programmable range 4 end address register
Section 6.3.11.2
01E1 5238h
PROG4_MPPA
Programmable range 4 memory protection page attributes register
01E1 5240h
PROG5_MPSAR
Programmable range 5 start address register
Section 6.3.10.2
01E1 5244h
PROG5_MPEAR
Programmable range 5 end address register
Section 6.3.11.2
01E1 5248h
PROG5_MPPA
Programmable range 5 memory protection page attributes register
01E1 5250h
PROG6_MPSAR
Programmable range 6 start address register
Section 6.3.10.2
01E1 5254h
PROG6_MPEAR
Programmable range 6 end address register
Section 6.3.11.2
01E1 5258h
PROG6_MPPA
Programmable range 6 memory protection page attributes register
01E1 5260h
PROG7_MPSAR
Programmable range 7 start address register
Section 6.3.10.2
01E1 5274h
PROG7_MPEAR
Programmable range 7 end address register
Section 6.3.11.2
01E1 5268h
PROG7_MPPA
Programmable range 7 memory protection page attributes register
01E1 5270h
PROG8_MPSAR
Programmable range 8 start address register
Section 6.3.10.2
01E1 5274h
PROG8_MPEAR
Programmable range 8 end address register
Section 6.3.11.2
01E1 5278h
PROG8_MPPA
Programmable range 8 memory protection page attributes register
01E1 5280h
PROG9_MPSAR
Programmable range 9 start address register
Section 6.3.10.2
01E1 5284h
PROG9_MPEAR
Programmable range 9 end address register
Section 6.3.11.2
01E1 5288h
PROG9_MPPA
Programmable range 9 memory protection page attributes register
01E1 5290h
PROG10_MPSAR
Programmable range 10 start address register
Section 6.3.10.2
01E1 5294h
PROG10_MPEAR
Programmable range 10 end address register
Section 6.3.11.2
01E1 5298h
PROG10_MPPA
Programmable range 10 memory protection page attributes register
01E1 52A0h
PROG11_MPSAR
Programmable range 11 start address register
Section 6.3.10.2
01E1 52A4h
PROG11_MPEAR
Programmable range 11 end address register
Section 6.3.11.2
01E1 52A8h
PROG11_MPPA
Programmable range 11 memory protection page attributes register
01E1 52B0h
PROG12_MPSAR
Programmable range 12 start address register
Section 6.3.10.2
01E1 52B4h
PROG12_MPEAR
Programmable range 12 end address register
Section 6.3.11.2
01E1 52B8h
PROG12_MPPA
Programmable range 12 memory protection page attributes register
Section 6.3.12
01E1 5300h
FLTADDRR
Fault address register
Section 6.3.13
01E1 5304h
FLTSTAT
Fault status register
Section 6.3.14
01E1 5308h
FLTCLR
Fault clear register
Section 6.3.15
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Section 6.3.11.2
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
Section 6.3.12
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6.3.1 Revision Identification Register (REVID)
The revision ID register (REVID) contains the MPU revision. The REVID is shown in Figure 6-3 and
described in Table 6-8.
Figure 6-3. Revision ID Register (REVID)
31
0
REV
R-4E81 0101h
LEGEND: R = Read only; -n = value after reset
Table 6-8. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E81 0101h
Description
Revision ID of the MPU.
6.3.2 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown
in Figure 6-4 and described in Table 6-9.
NOTE: Although the NUM_AIDS bit defaults to 12 (Ch), not all AIDs may be supported on your
device. Unsupported AIDs should be cleared to 0 in the memory page protection attributes
registers (MPPA). See for a list of AIDs supported on your device.
Figure 6-4. Configuration Register (CONFIG)
31
24
15
23
20
19
16
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-0 (1) or 6h (2)
R-0 (1) or 1 (2)
R-6h (1) or Ch (2)
12
11
1
0
NUM_AIDS
Reserved
ASSUME_ALLOWED
R-Ch
R-0
R-1
LEGEND: R = Read only; -n = value after reset
(1)
For MPU1.
For MPU2.
(2)
Table 6-9. Configuration Register (CONFIG) Field Descriptions
Field
Value
Description
31-24
Bit
ADDR_WIDTH
0-FFh
Address alignment (2n KByte alignment) for range checking.
23-20
NUM_FIXED
0-Fh
Number of fixed address ranges.
19-16
NUM_PROG
0-Fh
Number of programmable address ranges.
15-12
NUM_AIDS
0-Fh
Number of supported AIDs.
11-1
Reserved
0
106
0
ASSUME_ALLOWED
Reserved
Assume allowed. When an address is not covered by any MPU protection range, this bit
determines whether the transfer is assumed to be allowed or not allowed.
0
Assume is disallowed.
1
Assume is allowed.
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6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 6-5 and described in Table 6-10.
Figure 6-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR
Reserved
Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
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Description
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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6.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 6-6 and described in
Table 6-11.
Figure 6-6. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
2
R-0
1
0
ADDRERR
PROTERR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
108
Field
Reserved
Value
0
ADDRERR
Description
Reserved
Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0
Interrupt is not set.
1
Interrupt is set.
PROTERR
Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0
Interrupt is not set.
1
Interrupt is set.
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6.3.5 Interrupt Enable Set Register (IENSET)
Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Software can
write to IENSET to enable an interrupt. Writes of 0 have no effect. The IENSET is shown in Figure 6-7 and
described in Table 6-12.
Figure 6-7. Interrupt Enable Set Register (IENSET)
31
16
Reserved
R-0
15
2
1
0
ADDRERR_EN
PROTERR_EN
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-12. Interrupt Enable Set Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved
Address violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
PROTERR_EN
Protection violation error enable.
0
Writing 0 has no effect.
1
Interrupt is enabled.
6.3.6 Interrupt Enable Clear Register (IENCLR)
Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Software can
write to IENCLR to clear/disable an interrupt. Writes of 0 have no effect. The IENCLR is shown in
Figure 6-8 and described in Table 6-13.
Figure 6-8. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
R-0
1
0
ADDRERR_CLR PROTERR_CLR
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_CLR
Reserved
Address violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
PROTERR_CLR
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Description
Protection violation error disable.
0
Writing 0 has no effect.
1
Interrupt is cleared/disabled.
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6.3.7 Fixed Range Start Address Register (FXD_MPSAR)
The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range. The
fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPSAR and the fixed range end
address register (FXD_MPEAR), which instead read as 0. The FXD_MPSAR is shown in Figure 6-9.
Figure 6-9. Fixed Range Start Address Register (FXD_MPSAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
6.3.8 Fixed Range End Address Register (FXD_MPEAR)
The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range. The fixed
address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h–
B000 7FFFh). However, these addresses are not indicated in FXD_MPEAR and the fixed range start
address register (FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 6-10.
Figure 6-10. Fixed Range End Address Register (FXD_MPEAR)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
110
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6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the
fixed region. This register is writeable by a supervisor entity only. The FXD_MPPA is shown in Figure 6-11
and described in Table 6-14.
Figure 6-11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-14. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Controls access from ID = n.
0
Access is denied.
1
Access is granted.
Controls access from ID > 11.
AIDX
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR)
NOTE: In some cases the amount of physical memory in actual use may be less than the maximum
amount of memory supported by the device. For example, the device may support a total of
512 Mbytes of SDRAM memory, but your design may only populate 128 Mbytes. In such
cases, the unpopulated memory range must be protected in order to prevent
unintended/disallowed aliased access to protected memory, especially memory. One of the
programmable address ranges could be used to detect accesses to this unpopulated
memory.
The programmable range n start address register (PROGn_MPSAR) holds the start address for the range
n. The PROGn_MPSAR is writeable by a supervisor entity only.
The start address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KBbyte; the page size for MPU2 is 64 KBytes. The size of the page determines
the width of the address field in PROGn_MPSAR and the programmable range n end address register
(PROGn_MPEAR). For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
6.3.10.1 MPU1 Programmable Range n Start Address Register (PROG1_MPSAR-PROG6_MPSAR)
The PROGn_MPSAR for MPU1 is shown in Figure 6-12 and described in Table 6-15.
Figure 6-12. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
Reserved
R/W-20 0000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-15. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
START_ADDR
Reserved
20 0000h–
20 007Fh
0
Description
Start address for range N .
Reserved
6.3.10.2 MPU2 Programmable Range n Start Address Register (PROG1_MPSAR-PROG12_MPSAR)
The PROGn_MPSAR for MPU2 is shown in Figure 6-13 and described in Table 6-16.
Figure 6-13. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
31
16 15
0
START_ADDR
Reserved
R/W-C000h
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-16. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)
Field Descriptions
Bit
Field
31-16
START_ADDR
15-0
Reserved
112
Value
C000h–DFFFh
0
Description
Start address for range N.
Reserved
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6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR)
The programmable range n end address register (PROGn_MPEAR) holds the end address for the range
n. This register is writeable by a supervisor entity only.
The end address must be aligned on a page boundary. The size of the page depends on the MPU: the
page size for MPU1 is 1 KByte; the page size for MPU2 is 64 KBytes. The size of the page determines the
width of the address field in the programmable range n start address register (PROGn_MPSAR) and
PROGn_MPEAR. For example, to protect a 64-KB page starting at byte address 8001 0000h, write
8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.
6.3.11.1 MPU1 Programmable Range n End Address Register (PROG1_MPEAR-PROG6_MPEAR)
The PROGn_MPEAR for MPU1 is shown in Figure 6-14 and described in Table 6-17.
Figure 6-14. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
Reserved
R/W-20 007Fh
R-3FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-17. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
31-10
9-0
Field
Value
END_ADDR
20 0000h–
20 007Fh
Reserved
3FFh
Description
End address for range N.
Reserved
6.3.11.2 MPU2 Programmable Range n End Address Register (PROG1_MPEAR-PROG12_MPEAR)
The PROGn_MPEAR for MPU2 is shown in Figure 6-15 and described in Table 6-18.
Figure 6-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
31
16 15
0
END_ADDR
Reserved
R/W-DFFFh
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-18. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)
Field Descriptions
Bit
Field
31-16
END_ADDR
15-0
Reserved
Value
C000h–DFFFh
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Description
Start address for range N.
Reserved
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6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA)
The programmable range n memory protection page attributes register (PROGn_MPPA) holds the
permissions for the region n. This register is writeable only by a supervisor entity. The PROGn_MPPA is
shown in Figure 6-16 and described in Table 6-19.
Figure 6-16. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
31
26
25
22
21
20
19
18
17
16
Reserved
Reserved
AID11
AID10
AID9
AID8
AID7
AID6
R-0
R-Fh
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Rsvd
Rsvd
Rsvd
SR
SW
SX
UR
UW
UX
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-19. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA)
Field Descriptions
Bit
Field
Value
Description
31-26
Reserved
0
Reserved
25-22
Reserved
Fh
Reserved
21-10
AIDn
9
Access is denied.
1
Access is granted.
Controls access from ID > 11.
AIDX
0
Access is denied.
1
Access is granted.
8
Reserved
0
Reserved
7
Reserved
1
Reserved. This bit must be written as 1.
6
Reserved
1
Reserved. This bit must be written as 1.
5
SR
4
3
2
1
0
114
Controls access from ID = n.
0
Supervisor Read permission.
0
Access is denied.
1
Access is allowed.
SW
Supervisor Write permission.
0
Access is denied.
1
Access is allowed.
SX
Supervisor Execute permission.
0
Access is denied.
1
Access is allowed.
UR
User Read permission.
0
Access is denied.
1
Access is allowed.
UW
User Write permission.
0
Access is denied.
1
Access is allowed.
UX
User Execute permission.
0
Access is denied.
1
Access is allowed.
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6.3.13 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) holds the address of the first protection fault transfer. The
FLTADDRR is shown in Figure 6-17 and described in Table 6-20.
Figure 6-17. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-20. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
Field
FLTADDR
Value
0-FFFF FFFFh
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Description
Memory address of fault.
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6.3.14 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. The
FLTSTAT is shown in Figure 6-18 and described in Table 6-21.
Figure 6-18. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
Reserved
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 6-21. Fault Status Register (FLTSTAT) Field Descriptions
Bit
Field
31-24
Reserved
23-16
MSTID
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
Value
0
0-FFh
0
0-Fh
0
0-3Fh
Reserved
Master ID of fault transfer.
Reserved
Privilege ID of fault transfer.
Reserved
Fault type. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear
register (FLTCLR).
0
No fault.
1h
User execute fault.
2h
User write fault.
3h
Reserved
4h
User read fault.
5h-7h
8h
9h-Fh
Reserved
Supervisor execute fault.
Reserved
10h
Supervisor write fault.
11h
Reserved
12h
Relaxed cache write back fault.
13h-1Fh
20h
21h-3Eh
3Fh
116
Description
Reserved
Supervisor read fault.
Reserved
Relaxed cache line fill fault.
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6.3.15 Fault Clear Register (FLTCLR)
The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured
in the fault status register (FLTSTAT) as well as produce an interrupt. Only the TYPE bit field in FLTSTAT
is cleared when a 1 is written to the CLEAR bit. The FLTCLR is shown in Figure 6-19 and described in
Table 6-22.
Figure 6-19. Fault Clear Register (FLTCLR)
31
16
Reserved
R-0
15
1
0
Reserved
CLEAR
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 6-22. Fault Clear Register (FLTCLR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
CLEAR
Description
Reserved
Command to clear the current fault. Writing 0 has no effect.
0
No effect.
1
Clear the current fault.
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Chapter 7
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Device Clocking
Topic
7.1
7.2
7.3
...........................................................................................................................
Page
Overview ........................................................................................................ 120
Frequency Flexibility ........................................................................................ 122
Peripheral Clocking ......................................................................................... 123
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Overview
7.1
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Overview
This device requires two primary reference clocks:
• One reference clock is required for the phase-locked loop controllers (PLLCs)
• One reference clock is required for the real-time clock (RTC) module.
These reference clocks may be sourced from either the on-board oscillator via an externally supplied
crystal or by a direct external oscillator input. For detailed specifications on clock frequency and voltage
requirements, see the electrical specifications in your device-specific data manual.
In addition to the reference clocks required for the PLLCs and RTC module, some peripherals, such as the
USB, may also require an input reference clock to be supplied. All possible input clocks are described in
Table 7-1. The CPU and the majority of the device peripherals operate at fixed ratios of the primary
system/ARM clock frequency, as listed in Table 7-2. However, there are two system clock domains that do
not require a fixed ratio to the ARM, these are PLL0_SYSCLK3 and PLL0_SYSCLK7. Figure 7-1 shows
the clocking architecture.
Table 7-1. Device Clock Inputs
Peripheral
Input Clock Signal Name
Oscillator/PLL
OSCIN
RTC
RTC_XI
JTAG
TCK
EMAC RMII
RMII_MHZ_50_CLK
EMAC MII
MII_TXCLK, MII_RXCLK
I2Cs
I2Cn_SCL
Timers
TM64Pn_IN12
SPIs
SPIn_CLK
McASP0
ACLKR, AHCLKR, ACLKX, AHCLKX
Table 7-2. System Clock Domains
120
CPU/Device Peripherals
System Clock Domain
Fixed Ratio to
CPU ARM Clock
Required?
Default Ratio to
CPU ARM
Clock
DSP
PLL0_SYSCLK1
Yes
1:1
ARM RAM/ROM, DSP ports, Shared RAM, UART0,
EDMA, SPI0, MMC/SDs, DDR2/mDDR (bus ports),
USB2.0, PRU subsystem
PLL0_SYSCLK2
Yes
1:2
EMIFA
PLL0_SYSCLK3
No
1:3
System configuration (SYSCFG), GPIO, PLLCs, PSCs, PLL0_SYSCLK4
I2C1, EMAC/MDIO, ARM INTC
Yes
1:4
ARM
PLL0_SYSCLK6
Yes
1:1
EMAC RMII clock
PLL0_SYSCLK7
No
1:6
I2C0, Timer64P0/P1, RTC, USB2.0 PHY, McASP0
serial clock
PLL0_AUXCLK
Not Applicable
Not Applicable
DDR2/mDDR PHY
PLL1_SYSCLK1
Not Applicable
Not Applicable
PLL0 input reference clock
(not configured by default)
PLL1_SYSCLK3
Not Applicable
Not Applicable
ECAPs, UART1/2, Timer64P2/3, eHRPWMs, McBSPs,
McASP0, SPI1
ASYNC3
Not Applicable
Not Applicable
Device Clocking
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Figure 7-1. Overall Clocking Diagram
PLL0 Multiplier Out
Div 4.5
1
EMIFA (C)
0+
SYSCLK3 (/3)
SYSCLK6 (/1)
ARM
SYSCLK1 (/1)
DSP
CFGCHIP3[EMA_CLKSRC]
Shared RAM
ARM RAM/ROM
ARM INTC
SYSCLK4 (/4)
EDMA
System CFG
PLL0
Controller
SPI0
PSCs
MMC/SDs
I2C1
CLKSRC
USB2.0 (A)
EMAC/MDIO (D)
UART0
GPIO
EXTCLKSRC
DDR2/mDDR (B)
PRU
I2C0
AUXCLK
PLL
Ref CLK
Timers0/1
Timers2/3
RTC
UART1/2
SYSCLK2 (/2)
0+
SYSCLK2 (/2)
1
PLL1
Controller
CFGCHIP3[ASYNC3_CLKSRC]
SYSCLK3 (/3)
+ Default Mux Selection
McBSPs
eHRPWMs
eCAPs
SPI1
CLKSRC
A
McASP0 (E)
See Section 7.3.1 for USB clocking.
B
See Section 7.3.2 for DDR2/mDDR clocking.
C
See Section 7.3.3 for EMIFA clocking.
D
See Section 7.3.4 for EMAC clocking.
E
See Section 7.3.5 for McASP clocking.
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Frequency Flexibility
7.2
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Frequency Flexibility
There are two PLLs on the device with similar architecture and behavior. Each PLL has two clocking
modes:
• PLL Bypass
• PLL Active
When the PLL is in Bypass mode, the reference clock supplied on OSCIN serves as the clock source from
which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. This means that when the PLL is in
Bypass mode, the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that
creates each of the system clocks. For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to
use PLL1_SYSCLK3 as the Bypass mode reference clock.
When the PLL operates in Active mode, the PLL is enabled and the PLL multiplier setting is used to
multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. It is this
multiplied frequency that all system clocks are derived from in PLL Active mode.
The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the
system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). Each
SYSCLKn has a PLLDIVn block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter
for more details on the PLL.
The combination of the PLL multiplier, POSTDIV, and PLLDIV blocks provides flexibility in the frequencies
that the system clock domains support. This flexibility does have limitations, as follows:
• OSCIN input frequency is limited to a supported range.
• The output of the PLL Multiplier must be within the range specified in the device-specific data manual.
• The output of each PLLDIV block must be less than or equal to the maximum device frequency
specified in the device-specific data manual.
NOTE: The above limitations are provided here as an example and are used to illustrate the
recommended configuration of the PLL controller. These limitations may vary based on core
voltage and between devices. See the device-specific data manual for more details.
Table 7-3 shows examples of possible PLL multiplier settings, along with the available PLL post-divider
modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL
post-divider control register (POSTDIV). Additional post-divider modes are supported and are documented
in the Phase-Locked Loop Controller (PLLC) chapter.
NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases.
To decrease PLL power consumption, the lowest PLL multiplier (PLLM) setting should be
chosen that achieves the desired frequency. For example, if 200 MHz is the desired CPU
operating frequency and the OSCIN frequency is 25 MHz; lower power consumption is
achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2
instead of a PLLM setting of ×24 and a POSTDIV setting of /3, even though both of these
modes would result in a CPU frequency of 200 MHz.
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Table 7-3. Example PLL Frequencies
7.3
OSCIN Frequency
PLL Multiplier
Multiplier Frequency
Div3
Div4
20
30
600 MHz
200
150
24
25
600 MHz
200
150
25
24
600 MHz
200
150
30
20
600 MHz
200
150
20
25
500 MHz
167
125
24
20
480 MHz
160
120
25
18
450 MHz
150
112.5
30
14
420 MHz
140
105
25
16
400 MHz
133
100
Peripheral Clocking
7.3.1 USB Clocking
Figure 7-2 shows the clock connections for the USB2.0 module. Note that there is no built-in oscillator.
The USB2.0 subsystem requires a reference clock for its internal PLL. This reference clock can be
sourced from either the USB_REFCLKIN pin or from the AUXCLK of the system PLL. The reference clock
input to the USB2.0 subsystem is selected by programming the USB0PHYCLKMUX bit in the chip
configuration 2 register (CFGCHIP2) of the System Configuration Module. The USB_REFCLKIN source
should be selected when it is not possible (such as when specific audio rates are required) to operate the
device at one of the allowed input frequencies to the USB2.0 subsystem. The USB2.0 subsystem
peripheral bus clock is sourced from PLL0_SYSCLK2. Table 7-4 determines the source origination as well
as the source input frequency to the USB 2.0 PHY. Once the clock source origination (internal/external)
and its frequency is determined, the firmware should program the PHY PLL with the correct input
frequency via CFGCHIP2.USB0REF_FREQ.
Figure 7-2. USB Clocking Diagram
USB_
AUXCLK REFCLKIN
CFGCHIP2[USB0PHYCLKMUX]
1
0
USB 2.0
Subsystem
(USB0)
Table 7-4. USB Clock Multiplexing Options
CFGCHIP2.
USB0PHYCLKMUX
bit
USB2.0
Clock
Source
0
USB_REFCLKIN
USB_REFCLKIN must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
1
PLL0_AUXCLK
PLL0_AUXCLK must be 12, 24, 48, 19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be configured to accept any of these input
clock frequencies.
Additional Conditions
Device Clocking 123
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7.3.2 DDR2/mDDR Memory Controller Clocking
The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see
Figure 7-3):
• VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO, write FIFO, and read FIFO of
the DDR2/mDDR memory controller. From this, VCLK drives the interface to the peripheral bus.
• 2X_CLK is sourced from PLL1_SYSCLK1.
2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the
application as a free running clock that could be used by an FPGA or for some other purpose, then
2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. This
allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while
still providing a clock on the DDR_CLK and DDR_CLK.
NOTE: DDR_CLK and DDR_CLK are output clock signals.
Figure 7-3. DDR2/mDDR Memory Controller Clocking Diagram
On Chip
PLL0_SYSCLK2/2
DDR2/mDDR
Memory
Controller
LPSC #6
DDR_CLK
DDR_CLK
VCLK
PLL1_SYSCLK1
2X_CLK
124
DDR
PHY
MCLK
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7.3.3 EMIFA Clocking
EMIFA requires a single input clock source. The EMIFA clock can be sourced from either PLL0_SYSCLK3
or DIV4P5 (see Figure 7-4). The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the
System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock
source for EMIFA.
Figure 7-4. EMIFA Clocking Diagram
LPSC
PLL Controller
SYSCLK3
0
DIV4P5 CLK
1
EMIFA
CFGCHIP3[EMA_CLKSRC]
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7.3.4 EMAC Clocking
The EMAC module sources its peripheral bus interface reference clock from PLL0_SYSCLK4 that is at a
fixed ratio of the CPU clock. The external clock requirement for EMAC varies with the interface used.
When the MII interface is active, the MII_TXCLK and MII_RXCLK signals must be provided from an
external source. When the RMII interface is active, the RMII 50 MHz reference clock is sourced either
from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 (as shown in Figure 7-5).
The PINMUX15_3_0 bits in the pin multiplexing control 15 register (PINMUX15) of the System
Configuration Module control this clock selection:
• PINMUX15_3_0 = 0: enables sourcing of the 50 MHz reference clock from an external source on the
RMII_MHZ_50_CLK pin.
• PINMUX15_3_0 = 8h: enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7. Also,
PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.
Table 7-5 shows example PLL register settings and the resulting PLL0_SYSCLK7 frequencies based on
the OSCIN reference clock frequency of 25 MHz.
Figure 7-5. EMAC Clocking Diagram
On Chip
PLL Controller 0
LPSC
EMAC
SYSCLK4
SYSCLK7
50 MHz Reference Clock
PINMUX15[3:0]
1000 0000
3-State
0000 1000
RMII_MHZ_50_CLK
Signal
NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of
50 MHz +/-50 ppm.
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Table 7-5. EMAC Reference Clock Frequencies
OSCIN
Frequency
PLL Multiplier
Register Setting
Multiplier
Frequency
Post Divider
Mode (1)
POSTDIV
Output
Frequency
PLLDIV7
Register
Setting
PLL0_SYSCLK7
25
24
600 MHz
Div3
200 MHz
3
50 MHz
Div4
150 MHz
2
50 MHz
Div3
150 MHz
2
50 MHz
Div4
112.5 MHz
25
(1)
(2)
18
450 MHz
Not Applicable (2)
See Section 7.2 for explanation of POSTDIV divider modes.
Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7.
7.3.5 McASP Clocking
As shown in Figure 7-6, the McASP peripheral requires multiple clock sources. Internally, the module
clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC
bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module.
The transmit and receive clocks are sourced internally or externally by configuring the McASP clock
control registers ACLKRCTL, AHCLKRCTL, ACLKXCTL, and AHCLKXCTL. If an external clock is driven
into a high-frequency master clock (AHCLKX or AHCLKR), the McASP module allows for a mixed clock
mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the
high-frequency master clock through a programmable divider.
When the internal clock source option is selected, the transmit and receive clocks are derived from the
PLL0_AUXCLK clock through programmable dividers.
Figure 7-6. McASP Clocking Diagram
On Chip
CFGCHIP3[ASYNC3_CLKSRC]
PLL0_SYSCLK2
0
PLL1_SYSCLK2
1
LPSC
Module
Clock
McASP0
PLL0_AUXCLK
TX/RX
Reference
Clock
Clock
Generator
Frame Sync
Generator
ACLKX
AHCLKX
AFSX
AFSR
ACLKR
AHCLKR
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7.3.6 I/O Domains
The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In
many cases, there are frequency requirements for a peripheral pin interface that are set by an outside
standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock
generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to
the CPU frequency by definition.
The peripherals can be divided into the following groups, depending upon their clock requirements, as
shown in Table 7-6.
Table 7-6. Peripherals
Source of Peripheral Clock
RTC
—
Peripheral Group
Peripheral Group Definition
RTC
Operates off of a dedicated 32 kHz
crystal oscillator.
Fixed-Frequency Peripherals
As the name suggests,
Timer64P0/P1
fixed-frequency peripherals have a
I2C0
fixed-frequency. They are fed the
AUXCLK directly from the oscillator
input.
—
Synchronous peripherals have their MMC/SDs
frequencies derived from the ARM
UART0
clock frequency. The peripheral
GPIO
system clock frequency changes
accordingly, if the PLL0 frequency
changes. Most synchronous
peripherals have internal dividers
so they can generate their required
clock frequencies.
PLL0_SYSCLK2
Asynchronous peripherals are not
required to operate at a fixed ratio
of the ARM clock.
eCAPs
ASYNC3
eHRPWMs
ASYNC3
UART1/2
ASYNC3
Timer64P2/P3
ASYNC3
EMIFA
DIV_4P5 or PLL0_SYSCLK3
DDR2/mDDR
PLL1_SYSCLK1 or
PLL1 Direct Output
McASP0
ASYNC3 or
Peripheral Serial Clock
McBSPs
ASYNC3 or
Peripheral Serial Clock
SPI0
PLL0_SYSCLK2 or
Peripheral Serial Clock
SPI1
ASYNC3 or
Peripheral Serial Clock
I2C1
PLL0_SYSCLK4 or
Peripheral Serial Clock
EMAC
PLL0_SYSCLK4 or
RMII_MHZ_50_CLK
USB2.0
USB_REFCLKIN or AUXCLK
Synchronous Peripherals
Asynchronous Peripherals
Synchronous/Asynchronous
Peripherals
128
Peripherals
Contained
within Group
Synchronous/asynchronous
peripherals can be run with either
internally generated synchronous
clocks, or externally generated
asynchronous clocks.
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PLL0_SYSCLK2
PLL0_SYSCLK4
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Chapter 8
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Phase-Locked Loop Controller (PLLC)
Topic
8.1
8.2
8.3
...........................................................................................................................
Page
Introduction .................................................................................................... 130
PLL Controllers ............................................................................................... 130
PLLC Registers ............................................................................................... 135
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Introduction
8.1
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Introduction
This device has two phase-locked loop (PLL) controllers, PLLC0 and PLLC1. These PLL controllers
provide clock signals to most of the components of the device through various clock dividers.
Both PLL0 and PLL1 provide the following:
• Glitch-free transitions when clock settings are changed
• Domain clock alignment
• Clock gating
• PLL power-down
The clock outputs generated by the PLL controllers are:
• Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3]
• Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source
Dividers that can be used for the PLL controllers are:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: D1, …, Dn
Various other control signals supported are:
• PLL multiplier: PLLM
• Software-programmable PLL bypass: PLLEN
8.2
PLL Controllers
PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode
configuration.
PLL0 provides the primary system clock to the device. PLL0 operations are software programmable
through the PLL controller 0 (PLLC0) registers.
PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate
clocks that are asynchronous to the PLL0 clocks. PLL1 operations are software programmable through the
PLL controller 1 (PLLC1) registers.
Figure 8-1 shows the PLLC0 and PLLC1 architecture.
The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM).
The PLLM defaults to a multiplier value of 13h at power-up, which results in a PLL multiplier of 20×. The
PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider
control register (POSTDIV). The POSTDIV has a default value of /2, but may be modified through
software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default
PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source.
At power-up, PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through
the PLLPWRDN bit in their respective PLL control register (PLLCTL). Before each PLL completes the
power-up and frequency-lock sequence, the system operates in bypass mode by default and the system
clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator)
selected by the CLKMODE bit in PLLCTL. After the power-up and frequency-lock sequences are
complete, software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).
The PLL controller registers are listed in Section 8.3.
130
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Figure 8-1. PLLC Structure
PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
PLLCTL[CLKMODE]
1
PLLCTL[PLLEN]
0
OSCIN
0
Square
Wave
1
Crystal
0
PREDIV
POSTDIV
PLL
1
PLLM
DEEPSLEEP
Enable
PLLDIV1 (/1)
SYSCLK1
PLLDIV2 (/2)
SYSCLK2
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV6 (/1)
SYSCLK6
PLLDIV7 (/6)
SYSCLK7
PLLDIV3 (/3)
SYSCLK3
EMIFA
Internal
Clock
Source
0
1
DIV4.5
CFGCHIP3[EMA_CLKSRC]
AUXCLK
PLLC0 OBSCLK
(CLKOUT Pin)
DIV4.5
OSCDIV
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
0
POSTDIV
PLL
1
PLLM
SYSCLK1
SYSCLK2
SYSCLK3
PLL Controller 1
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV1 (/1)
SYSCLK1
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
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8.2.1 Device Clock Generation
The PLL controllers (PLLC0 and PLLC1) manage the clock ratios, alignment, and gating for the device
system clocks. Various PLL mode attributes such as pre-division, multiplier, and post-division are software
programmable through the PLL controller registers. Additionally, the reset controller in PLLC0 manages
reset propagation through the device, clock alignment, and test points.
The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the
SYSCLK dividers can handle. The POSTDIV stage should be programmed to keep the input to the
SYSCLK dividers within operating limits. See the device datasheet for the maximum operating
frequencies.
PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. These
reference clocks are summarized in Table 8-1. Some output clock dividers require fixed values so that
clock ratios between various device components are maintained regardless of PLL or bypass frequency.
Table 8-1. System PLLC Output Clocks
Output Clock
Used by
Default Ratio
(relative to PLLn_SYSCLK1)
Fixed Clock
Ratio
PLLC0 (1)
PLL0_SYSCLK1
DSP
/1
Yes
PLL0_SYSCLK2
ARM RAM/ROM, DSP ports, Shared RAM,
UART0, EDMA, SPI0, MMC/SDs,
DDR2/mDDR (bus ports), USB2.0, PRU
/2
Yes
PLL0_SYSCLK3 (2)
EMIFA
/3
No
PLL0_SYSCLK4
System configuration (SYSCFG), GPIO,
PLLCs, PSCs, I2C1, EMAC/MDIO, ARM
INTC
/4
Yes
PLL0_SYSCLK5
Not used
/3
No
PLL0_SYSCLK6
ARM
/1
Yes
PLL0_SYSCLK7
EMAC RMII clock
PLL0_AUXCLK
I2C0, Timer64P0/P1, RTC, USB2.0 PHY,
McASP0 serial clock
PLL0_OBSCLK
Observation clock (OBSCLK) source
PLL1_SYSCLK1
/6
No
PLL bypass clock
No
Pin configurable
No
DDR2/mDDR PHY
/1 or disabled
No
PLL1_SYSCLK2 (3)
ECAPs, UART1/2, Timer64P2/3, eHRPWMs,
McBSPs, McASP0, SPI1 (all these modules
use PLL0_SYSCLK2 by default)
/2 or disabled
No
PLL1_SYSCLK3 (4)
PLL0 input reference clock
(not configured by default)
/3 or disabled
No
PLLC1
(1)
(2)
(3)
(4)
132
The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6, PLL0_SYSCLK2, and PLL0_SYSCLK4 can be changed for
power savings, but the device must maintain the 1:2:4 clock ratios between the clock domains.
PLLC0 supports an additional post-divider value of /4.5 that can be used for EMIFA clock generation. When this /4.5 value is
used, the resulting clock will not have a 50% duty cycle. Instead, the duty cycle will be 44.4%. The EMIFA uses PLL0_SYSCLK3
by default, but can be configured to use a /4.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the
EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG)
module.
The ASYNC3 modules use PLL0_SYSCLK2 by default, but all these modules can be configured as a group to use
PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system
configuration (SYSCFG) module.
The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit
in the PLLC0 PLL control register (PLLCTL). The PLL1 input clock source will also be OSCIN.
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8.2.2 Steps for Programming the PLLs
Note that there is a lock mechanism implemented to protect the PLL controller registers. See
Section 8.2.2.1 for information on unlocking the PLL controller registers.
Refer to the appropriate subsection on how to program the PLL clocks:
• If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in Section 8.2.2.2.
• If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 8.2.2.3 to change the PLL multiplier.
• If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated,
follow the sequence in Section 8.2.2.4.
Note that the PLLs are powered down after a Power-on Reset (POR). The PLLs are not powered down
after a Warm Reset (RESET), but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the
PLLDIVx registers are reset to default values.
8.2.2.1
Locking/Unlocking PLL Register Access
A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller
registers. This provides protection from stopping modules when the module clocks are disabled. For
example, the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally
disabled.
The PLL lock bits are located within the system configuration (SYSCFG) module:
• When set, the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0.
• When set, the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1.
NOTE: The functionality of the protection scheme has been disabled on this device. All SYSCFG
module registers remain unlocked by default.
CPU reads to the KICK0R and KICK1R registers return successfully. Data returned by a
read should be disregarded by the software application.
CPU writes to the KICK0R and KICK1R registers return successfully but have no influence
on the accessibility of the SYSCFG module registers.
Because the SYSCFG module has its own lock mechanism, the SYSCFG module must be unlocked first
by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared. Like the KICK
registers, the PLL lock bits can only be modified while in a privileged mode. See the System Configuration
(SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers.
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in
CFGCHIP3 default to unlocked after reset, so the following procedure is only required if the
PLLs have been locked (set to 1).
To modify the PLL controller registers, use the following sequence:
1. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
2. Configure the desired PLL controller register values.
3. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3,
as required.
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8.2.2.2
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Initializing PLL Mode from PLL Power Down
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), perform the following procedure to
initialize the PLL:
1. Program the CLKMODE bit in PLLC0 PLLCTL.
2. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
3. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
4. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode).
5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
8. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
8.2.2.3
Changing PLL Multiplier
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), perform the following
procedure to change the PLL multiplier:
1. Switch the PLL to bypass mode:
(a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect).
(b) For PLL0 only, select the clock source by programming the EXTCLKSRC bit in PLLCTL.
(c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).
(d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
2. Clear the PLLRST bit in PLLCTL to 0 (resets PLL).
3. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed.
4. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
(a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in
progress).
(b) Program the RATIO field in PLLDIVn.
(c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).
6. Wait for the PLL to lock. See the device-specific data manual for PLL lock time.
7. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode).
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8.2.2.4
Changing SYSCLK Dividers
If the PLL is already operating at the desired multiplier mode, perform the following procedure to change
the SYSCLK divider values:
1. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).
2. Program the RATIO field in PLLDIVn.
3. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
8.3
PLLC Registers
Table 8-2 lists the memory-mapped registers for the PLLC0 and Table 8-3 lists the memory-mapped
registers for the PLLC1.
Table 8-2. PLL Controller 0 (PLLC0) Registers
Address
Acronym
Register Description
01C1 1000h
REVID
PLLC0 Revision Identification Register
Section 8.3.1
Section
01C1 10E4h
RSTYPE
PLLC0 Reset Type Status Register
Section 8.3.3
01C1 10E8h
RSCTRL
PLLC0 Reset Control Register
Section 8.3.4
01C1 1100h
PLLCTL
PLLC0 Control Register
Section 8.3.5
01C1 1104h
OCSEL
PLLC0 OBSCLK Select Register
Section 8.3.7
01C1 1110h
PLLM
PLLC0 PLL Multiplier Control Register
Section 8.3.9
01C1 1114h
PREDIV
PLLC0 Pre-Divider Control Register
Section 8.3.10
01C1 1118h
PLLDIV1
PLLC0 Divider 1 Register
Section 8.3.11
01C1 111Ch
PLLDIV2
PLLC0 Divider 2 Register
Section 8.3.13
01C1 1120h
PLLDIV3
PLLC0 Divider 3 Register
Section 8.3.15
01C1 1124h
OSCDIV
PLLC0 Oscillator Divider 1 Register
Section 8.3.21
01C1 1128h
POSTDIV
PLLC0 PLL Post-Divider Control Register
Section 8.3.23
01C1 1138h
PLLCMD
PLLC0 PLL Controller Command Register
Section 8.3.24
01C1 113Ch
PLLSTAT
PLLC0 PLL Controller Status Register
Section 8.3.25
01C1 1140h
ALNCTL
PLLC0 Clock Align Control Register
Section 8.3.26
01C1 1144h
DCHANGE
PLLC0 PLLDIV Ratio Change Status Register
Section 8.3.28
01C1 1148h
CKEN
PLLC0 Clock Enable Control Register
Section 8.3.30
01C1 114Ch
CKSTAT
PLLC0 Clock Status Register
Section 8.3.32
01C1 1150h
SYSTAT
PLLC0 SYSCLK Status Register
Section 8.3.34
01C1 1160h
PLLDIV4
PLLC0 Divider 4 Register
Section 8.3.17
01C1 1164h
PLLDIV5
PLLC0 Divider 5 Register
Section 8.3.18
01C1 1168h
PLLDIV6
PLLC0 Divider 6 Register
Section 8.3.19
01C1 116Ch
PLLDIV7
PLLC0 Divider 7 Register
Section 8.3.20
01C1 11F0h
EMUCNT0
PLLC0 Emulation Performance Counter 0 Register
Section 8.3.36
01C1 11F4h
EMUCNT1
PLLC0 Emulation Performance Counter 1 Register
Section 8.3.37
Phase-Locked Loop Controller (PLLC) 135
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Table 8-3. PLL Controller 1 (PLLC1) Registers
Address
Acronym
Register Description
Section
01E1 A000h
REVID
PLLC1 Revision Identification Register
Section 8.3.2
01E1 A100h
PLLCTL
PLLC1 Control Register
Section 8.3.6
01E1 A104h
OCSEL
PLLC1 OBSCLK Select Register
Section 8.3.8
01E1 A110h
PLLM
PLLC1 PLL Multiplier Control Register
Section 8.3.9
01E1 A118h
PLLDIV1
PLLC1 Divider 1 Register
Section 8.3.12
01E1 A11Ch
PLLDIV2
PLLC1 Divider 2 Register
Section 8.3.14
01E1 A120h
PLLDIV3
PLLC1 Divider 3 Register
Section 8.3.16
01E1 A124h
OSCDIV
PLLC1 Oscillator Divider 1 Register
Section 8.3.22
01E1 A128h
POSTDIV
PLLC1 PLL Post-Divider Control Register
Section 8.3.23
01E1 A138h
PLLCMD
PLLC1 PLL Controller Command Register
Section 8.3.24
01E1 A13Ch
PLLSTAT
PLLC1 PLL Controller Status Register
Section 8.3.25
01E1 A140h
ALNCTL
PLLC1 Clock Align Control Register
Section 8.3.27
01E1 A144h
DCHANGE
PLLC1 PLLDIV Ratio Change Status Register
Section 8.3.29
01E1 A148h
CKEN
PLLC1 Clock Enable Control Register
Section 8.3.31
01E1 A14Ch
CKSTAT
PLLC1 Clock Status Register
Section 8.3.33
01E1 A150h
SYSTAT
PLLC1 SYSCLK Status Register
Section 8.3.35
01E1 A1F0h
EMUCNT0
PLLC1 Emulation Performance Counter 0 Register
Section 8.3.36
01E1 A1F4h
EMUCNT1
PLLC1 Emulation Performance Counter 1 Register
Section 8.3.37
8.3.1 PLLC0 Revision Identification Register (REVID)
The PLLC0 revision identification register (REVID) is shown in Figure 8-2 and described in Table 8-4.
Figure 8-2. PLLC0 Revision Identification Register (REVID)
31
0
REV
R-4481 3C00h
LEGEND: R = Read only; -n = value after reset
Table 8-4. PLLC0 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 3C00h
136
Description
Peripheral revision ID for PLLC0.
Phase-Locked Loop Controller (PLLC)
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8.3.2 PLLC1 Revision Identification Register (REVID)
The PLLC1 revision identification register (REVID) is shown in Figure 8-3 and described in Table 8-5.
Figure 8-3. PLLC1 Revision Identification Register (REVID)
31
0
REV
R-4481 4400h
LEGEND: R = Read only; -n = value after reset
Table 8-5. PLLC1 Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4481 4400h
Description
Peripheral revision ID for PLLC1.
8.3.3 Reset Type Status Register (RSTYPE)
The reset type status register (RSTYPE) latches the cause of the last reset. If multiple reset sources are
asserted simultaneously, RSTYPE records the reset source that deasserts last. If multiple reset sources
are asserted and deasserted simultaneously, RSTYPE latches the highest priority reset source. RSTYPE
is shown in Figure 8-4 and described in Table 8-6.
Figure 8-4. Reset Type Status Register (RSTYPE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
PLLSWRST
XWRST
POR
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-6. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
PLLSWRST
Description
Reserved
PLL software reset.
0
PLL soft reset was not the last reset to occur.
1
PLL soft was the last reset to occur.
XWRST
External warm reset.
0
External warm reset was not the last reset to occur.
1
External warm reset was the last reset to occur.
POR
Power on reset.
0
Power On Reset (POR) was not the last reset to occur.
1
Power On Reset (POR) was the last reset to occur.
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8.3.4 PLLC0 Reset Control Register (RSCTRL)
The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Before writing
to the SWRST bit, the register must be unlocked by writing the key value of 5A69h to the KEY bit field.
The KEY bit field reads back as Ch when the register is unlocked; any other key value is invalid and
indicates that the register is locked. Any write to the register following a successful unlock relocks the
register. RSCTRL is shown in Figure 8-5 and described in Table 8-7.
Figure 8-5. Reset Control Register (RSCTRL)
31
17
16
Reserved
SWRST
R-0
R/W-1
15
0
KEY
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-7. Reset Control Register (RSCTRL) Field Descriptions
Bit
31-17
16
15-0
Field
Reserved
Value
0
SWRST
KEY
Reserved
PLL software reset. Register must be unlocked before writing to this bit. Writes are possible only
when qualified with a valid key.
0
In software reset
1
Not in software reset
0-FFFFh
RSCTRL unlock key. Key used to enable writes to RSCTRL.
3h
Register is locked when read value is 3h.
Ch
Register is unlocked when read value is Ch.
5A69h
138
Description
RSCTRL unlock key
Phase-Locked Loop Controller (PLLC)
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8.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in Figure 8-6 and described in Table 8-8.
Figure 8-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
7
6
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
31-10
9
8
Field
Value
Reserved
0
EXTCLKSRC
Description
Reserved
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
7-6
2
Reserved
1
PLLPWRDN
0
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
0
Reserved
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
PLLEN
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PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
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8.3.6 PLLC1 Control Register (PLLCTL)
The PLLC1 control register (PLLCTL) is shown in Figure 8-7 and described in Table 8-9.
Figure 8-7. PLLC1 Control Register (PLLCTL)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
6
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-9. PLLC1 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
2
Reserved
1
PLLPWRDN
0
140
PLL1 reset.
0
PLL1 reset is asserted.
1
PLL1 reset is not asserted.
0
Reserved
PLL1 power-down.
0
PLL1 is operating.
1
PLL1 is powered-down.
PLLEN
PLL1 mode enables.
0
PLL1 is in bypass mode.
1
PLL1 mode is enabled, not bypassed.
Phase-Locked Loop Controller (PLLC)
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8.3.7 PLLC0 OBSCLK Select Register (OCSEL)
The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 8-8 and described in Table 8-10.
Figure 8-8. PLLC0 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-10. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC0 OBSCLK source. Output on CLKOUT pin.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL0_SYSCLK1
18h
PLL0_SYSCLK2
19h
PLL0_SYSCLK3
1Ah
PLL0_SYSCLK4
1Bh
PLL0_SYSCLK5
1Ch
PLL0_SYSCLK6
1Dh
PLL0_SYSCLK7
1Eh
PLLC1 OBSCLK
1Fh
Disabled
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8.3.8 PLLC1 OBSCLK Select Register (OCSEL)
The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it
may be used for test and debug purposes (in addition to its normal function of being a direct input clock
divider). The OCSEL is shown in Figure 8-9 and described in Table 8-11.
Figure 8-9. PLLC1 OBSCLK Select Register (OCSEL)
31
16
Reserved
R-0
15
5
4
0
Reserved
OCSRC
R-0
R/W-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions
Bit
Field
31-5
Reserved
4-0
OCSRC
Value
0
Description
Reserved
0-1Fh
PLLC1 OBSCLK source.
0-13h
Reserved
14h
OSCIN
15h-16h Reserved
17h
PLL1_SYSCLK1
18h
PLL1_SYSCLK2
19h
PLL1_SYSCLK3
1A-1Fh Reserved
142
Phase-Locked Loop Controller (PLLC)
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8.3.9 PLL Multiplier Control Register (PLLM)
The PLL multiplier control register (PLLM) is shown in Figure 8-10 and described in Table 8-12.
Figure 8-10. PLL Multiplier Control Register (PLLM)
31
16
Reserved
R-0
15
5
4
0
Reserved
PLLM
R-0
R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
Field
31-5
Reserved
4-0
PLLM
Value
0
0-1Fh
Description
Reserved
PLL multiplier select. Multiplier Value = PLLM + 1. The valid range of multiplier values for a given
OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. See the
device-specific data manual for PLL VCO frequency specification limits.
8.3.10 PLLC0 Pre-Divider Control Register (PREDIV)
The PLLC0 pre-divider control register (PREDIV) is shown in Figure 8-11 and described in Table 8-13.
Figure 8-11. PLLC0 Pre-Divider Control Register (PREDIV)
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-13. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
31-14
Reserved
15
PREDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
PLLC0 pre-divider enable.
0
PLLC0 pre-divider is disabled. Clock output from the PREDIV stage is disabled.
1
PLLC0 pre-divider is enabled.
0
Reserved
0-1Fh
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Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1).
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8.3.11 PLLC0 Divider 1 Register (PLLDIV1)
The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. PLLDIV1 is shown in
Figure 8-12 and described in Table 8-14.
Figure 8-12. PLLC0 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
8.3.12 PLLC1 Divider 1 Register (PLLDIV1)
The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. PLLDIV1 is shown in
Figure 8-13 and described in Table 8-15.
Figure 8-13. PLLC1 Divider 1 Register (PLLDIV1)
31
16
Reserved
R-0
15
14
5
4
0
D1EN
Reserved
RATIO
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-15. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D1EN
14-5
Reserved
4-0
RATIO
144
Value
Description
Reserved
Divider 1 enable.
0
Divider 1 is disabled.
1
Divider 1 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
Phase-Locked Loop Controller (PLLC)
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8.3.13 PLLC0 Divider 2 Register (PLLDIV2)
The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2. PLLDIV2 is shown in
Figure 8-14 and described in Table 8-16.
Figure 8-14. PLLC0 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-16. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
8.3.14 PLLC1 Divider 2 Register (PLLDIV2)
The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. PLLDIV2 is shown in
Figure 8-15 and described in Table 8-17.
Figure 8-15. PLLC1 Divider 2 Register (PLLDIV2)
31
16
Reserved
R-0
15
14
5
4
0
D2EN
Reserved
RATIO
R/W-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-17. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D2EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 2 enable.
0
Divider 2 is disabled.
1
Divider 2 is enabled.
0
Reserved
0-1Fh
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Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2).
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8.3.15 PLLC0 Divider 3 Register (PLLDIV3)
The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. PLLDIV3 is shown in
Figure 8-16 and described in Table 8-18.
Figure 8-16. PLLC0 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-18. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D3EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
8.3.16 PLLC1 Divider 3 Register (PLLDIV3)
The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. PLLDIV3 is shown in
Figure 8-17 and described in Table 8-19.
Figure 8-17. PLLC1 Divider 3 Register (PLLDIV3)
31
16
Reserved
R-0
15
14
5
4
0
D3EN
Reserved
RATIO
R/W-0
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-19. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D3EN
14-5
Reserved
4-0
RATIO
146
Value
Description
Reserved
Divider 3 enable.
0
Divider 3 is disabled.
1
Divider 3 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 2h (PLL divide by 3).
Phase-Locked Loop Controller (PLLC)
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8.3.17 PLLC0 Divider 4 Register (PLLDIV4)
The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. PLLDIV4 is shown
inFigure 8-18 and described in Table 8-20.
Figure 8-18. PLLC0 Divider 4 Register (PLLDIV4)
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
RATIO
R/W-1
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-20. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D4EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 4 enable.
0
Divider 4 is disabled.
1
Divider 4 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4).
8.3.18 PLLC0 Divider 5 Register (PLLDIV5)
The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. PLLDIV5 is shown in
Figure 8-19 and described in Table 8-21.
Figure 8-19. PLLC0 Divider 5 Register (PLLDIV5)
31
16
Reserved
R-0
15
14
5
4
0
D5EN
Reserved
RATIO
R/W-1
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-21. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D5EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 5 enable.
0
Divider 5 is disabled.
1
Divider 5 is enabled.
0
Reserved
0-1Fh
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Divider ratio. Divider Value = RATIO + 1. RATIO defaults 2 (PLL divide by 3).
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8.3.19 PLLC0 Divider 6 Register (PLLDIV6)
The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. PLLDIV6 is shown in
Figure 8-20 and described in Table 8-22.
Figure 8-20. PLLC0 Divider 6 Register (PLLDIV6)
31
16
Reserved
R-0
15
14
5
4
0
D6EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-22. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
D6EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Divider 6 enable.
0
Divider 6 is disabled.
1
Divider 6 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1).
8.3.20 PLLC0 Divider 7 Register (PLLDIV7)
The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV7 is shown in
Figure 8-21 and described in Table 8-23.
Figure 8-21. PLLC0 Divider 7 Register (PLLDIV7)
31
16
Reserved
R-0
15
14
5
4
0
D7EN
Reserved
RATIO
R/W-1
R-0
R/W-5h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-23. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions
Bit
31-16
15
Field
Reserved
0
D7EN
14-5
Reserved
4-0
RATIO
148
Value
Description
Reserved
Divider 7 enable.
0
Divider 7 is disabled.
1
Divider 7 is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6).
Phase-Locked Loop Controller (PLLC)
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8.3.21 PLLC0 Oscillator Divider 1 Register (OSCDIV)
The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK, dividing down
the clock selected as the PLLC0 OBSCLK source. The PLLC0 OBSCLK is connected to the CLKOUT pin.
The OSCDIV is shown in Figure 8-22 and described in Table 8-24.
Figure 8-22. PLLC0 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-24. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC0 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC0 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
8.3.22 PLLC1 Oscillator Divider 1 Register (OSCDIV)
The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK, dividing down
the clock selected as the PLLC1 OBSCLK source. The PLLC1 OBSCLK signal may be selected as the
output on the CLKOUT pin. The OSCDIV is shown in Figure 8-23 and described in Table 8-25.
Figure 8-23. PLLC1 Oscillator Divider 1 Register (OSCDIV)
31
16
Reserved
R-0
15
14
5
4
0
OD1EN
Reserved
RATIO
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-25. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit
31-16
15
Field
Reserved
Value
0
OD1EN
14-5
Reserved
4-0
RATIO
Description
Reserved
Oscillator divider 1 enable.
0
Oscillator divider 1 is disabled.
1
Oscillator divider 1 is enabled. For PLLC1 OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in
the PLLC1 clock enable control register (CKEN) must be set to 1.
0
Reserved
0-1Fh
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8.3.23 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 8-24 and described in Table 8-26.
Figure 8-24. PLL Post-Divider Control Register (POSTDIV)
31
16
Reserved
R-0
15
14
5
4
0
POSTDEN
Reserved
RATIO
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-26. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit
Field
31-16
Reserved
15
POSTDEN
14-5
Reserved
4-0
RATIO
Value
0
Description
Reserved
Post-divider enable.
0
Post-divider is disabled.
1
Post-divider is enabled.
0
Reserved
0-1Fh
Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
8.3.24 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) contains the command bit for phase alignment. A write of
1 initiates the command; a write of 0 clears the bit, but has no effect. PLLCMD is shown in Figure 8-25
and described in Table 8-27.
Figure 8-25. PLL Controller Command Register (PLLCMD)
31
16
Reserved
R-0
15
1
0
Reserved
GOSET
R-0
R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 8-27. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31-1
0
150
Field
Reserved
Value
0
GOSET
Description
Reserved
GO bit for phase alignment.
0
Clear bit (no effect)
1
Phase alignment
Phase-Locked Loop Controller (PLLC)
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8.3.25 PLL Controller Status Register (PLLSTAT)
The PLL controller status register (PLLSTAT) is shown in Figure 8-26 and described in Table 8-28.
Figure 8-26. PLL Controller Status Register (PLLSTAT)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
STABLE
Reserved
GOSTAT
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-28. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
STABLE
1
Reserved
0
GOSTAT
Value
0
Description
Reserved
OSC counter done, oscillator assumed to be stable. By the time the device comes out of reset, this bit
should become 1.
0
No
1
Yes
0
Reserved
Status of GO operation. If 1, indicates GO operation is in progress.
0
GO operation is not in progress.
1
GO operation is in progress.
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8.3.26 PLLC0 Clock Align Control Register (ALNCTL)
The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 8-27 and described in Table 8-29.
Figure 8-27. PLLC0 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
ALN7
ALN6
ALN5
ALN4
ALN3
ALN2
ALN1
R-3h
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-29. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
152
Field
Reserved
Value
3h
ALN7
Description
Reserved
PLL0_SYSCLK7 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN6
PLL0_SYSCLK6 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN5
PLL0_SYSCLK5 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN4
PLL0_SYSCLK4 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN3
PLL0_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL0_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL0_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
Phase-Locked Loop Controller (PLLC)
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8.3.27 PLLC1 Clock Align Control Register (ALNCTL)
The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for
proper device operation. ALNCTL is shown in Figure 8-28 and described in Table 8-30.
Figure 8-28. PLLC1 Clock Align Control Register (ALNCTL)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
ALN3
ALN2
ALN1
R-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-30. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
ALN3
Description
Reserved
PLL1_SYSCLK3 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN2
PLL1_SYSCLK2 needs to be aligned to others selected in this register.
0
No
1
Yes
ALN1
PLL1_SYSCLK1 needs to be aligned to others selected in this register.
0
No
1
Yes
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8.3.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 8-29 and described in Table 8-31.
Figure 8-29. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
6
5
4
3
2
1
0
Reserved
7
SYS7
SYS6
SYS5
SYS4
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-31. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-7
6
5
4
3
2
1
0
154
Field
Reserved
Value
0
SYS7
Description
Reserved
PLL0_SYSCLK7 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS6
PLL0_SYSCLK6 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS5
PLL0_SYSCLK5 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS4
PLL0_SYSCLK4 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS3
PLL0_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL0_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL0_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
Phase-Locked Loop Controller (PLLC)
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8.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio
has been modified. DCHANGE is shown in Figure 8-30 and described in Table 8-32.
Figure 8-30. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE)
31
16
Reserved
R-0
15
2
1
0
Reserved
3
SYS3
SYS2
SYS1
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-32. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-3
2
1
0
Field
Reserved
Value
0
SYS3
Description
Reserved
PLL1_SYSCLK3 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS2
PLL1_SYSCLK2 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
SYS1
PLL1_SYSCLK1 divide ratio is modified.
0
Ratio is not modified.
1
Ratio is modified.
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8.3.30 PLLC0 Clock Enable Control Register (CKEN)
The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. CKEN
is shown in Figure 8-31 and described in Table 8-33.
Figure 8-31. PLLC0 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-33. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK enable. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 OBSCLK is disabled.
1
PLLC0 OBSCLK is enabled. For PLLC0 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1.
AUXEN
AUXCLK enable. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT).
0
PLLC0 AUXCLK is disabled.
1
PLLC0 AUXCLK is enabled.
8.3.31 PLLC1 Clock Enable Control Register (CKEN)
The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. CKEN is shown in
Figure 8-32 and described in Table 8-34.
Figure 8-32. PLLC1 Clock Enable Control Register (CKEN)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-34. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions
Bit
31-2
1
0
156
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK enable. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT).
0
PLLC1 OBSCLK is disabled.
1
PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle, both the OBSEN bit and the OD1EN bit in
the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1.
0
Reserved
Phase-Locked Loop Controller (PLLC)
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8.3.32 PLLC0 Clock Status Register (CKSTAT)
The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. The
PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 8-33 and described in Table 8-35.
Figure 8-33. PLLC0 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
AUXEN
R-0
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Table 8-35. PLLC0 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
OBSEN
Description
Reserved
OBSCLK on status. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC0 clock enable control register (CKEN).
0
PLLC0 OBSCLK is off.
1
PLLC0 OBSCLK is on.
AUXEN
AUXCLK on status. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control
register (CKEN).
0
PLLC0 AUXCLK is off.
1
PLLC0 AUXCLK is on.
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8.3.33 PLLC1 Clock Status Register (CKSTAT)
The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. The
PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). CKSTAT is shown in
Figure 8-34 and described in Table 8-36.
Figure 8-34. PLLC1 Clock Status Register (CKSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
OBSEN
Reserved
R-2h
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-36. PLLC1 Clock Status Register (CKSTAT) Field Descriptions
Bit
31-2
1
0
158
Field
Reserved
Value
0
OBSEN
Reserved
Description
Reserved
OBSCLK on status. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV)
by the OBSEN bit in the PLLC1 clock enable control register (CKEN).
0
PLLC1 OBSCLK is off.
1
PLLC1 OBSCLK is on.
0
Reserved
Phase-Locked Loop Controller (PLLC)
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8.3.34 PLLC0 SYSCLK Status Register (SYSTAT)
The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC0 PLLDIVn.
SYSTAT is shown in Figure 8-35 and described in Table 8-37.
Figure 8-35. PLLC0 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-1
7
6
5
4
3
2
1
0
Reserved
SYS7ON
SYS6ON
SYS5ON
SYS4ON
SYS3ON
SYS2ON
SYS1ON
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-37. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-7
Reserved
6
SYS7ON
5
4
3
2
1
0
Value
3h
Description
Reserved
PLL0_SYSCLK7 on status.
0
Off
1
On
SYS6ON
PLL0_SYSCLK6 on status.
0
Off
1
On
SYS5ON
PLL0_SYSCLK5 on status.
0
Off
1
On
SYS4ON
PLL0_SYSCLK4 on status.
0
Off
1
On
SYS3ON
PLL0_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL0_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL0_SYSCLK1 on status.
0
Off
1
On
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8.3.35 PLLC1 SYSCLK Status Register (SYSTAT)
The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. The actual
default is determined by the actual clock on/off status, which depends on the DnEN bit in PLLC1 PLLDIVn.
SYSTAT is shown in Figure 8-36 and described in Table 8-38.
Figure 8-36. PLLC1 SYSCLK Status Register (SYSTAT)
31
8
Reserved
R-0
7
2
1
0
Reserved
3
SYS3ON
SYS2ON
SYS1ON
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-38. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
31-3
Reserved
2
SYS3ON
1
0
160
Value
0
Description
Reserved
PLL1_SYSCLK3 on status.
0
Off
1
On
SYS2ON
PLL1_SYSCLK2 on status.
0
Off
1
On
SYS1ON
PLL1_SYSCLK1 on status.
0
Off
1
On
Phase-Locked Loop Controller (PLLC)
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8.3.36 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 8-37 and described in
Table 8-39. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 8-37. Emulation Performance Counter 0 Register (EMUCNT0)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-39. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit
31-0
Field
Value
COUNT
0-FFFF FFFFh
Description
Counter value for lower 64-bits.
8.3.37 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 8-38 and described in
Table 8-40. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 8-38. Emulation Performance Counter 1 Register (EMUCNT1)
31
0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 8-40. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit
31-0
Field
COUNT
Value
0-FFFF FFFFh
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Description
Counter value for upper 64-bits.
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Chapter 9
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Power and Sleep Controller (PSC)
Topic
...........................................................................................................................
9.1
9.2
9.3
9.4
9.5
9.6
Introduction ....................................................................................................
Power Domain and Module Topology .................................................................
Executing State Transitions ..............................................................................
IcePick Emulation Support in the PSC ................................................................
PSC Interrupts .................................................................................................
PSC Registers .................................................................................................
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164
164
169
170
170
173
163
Introduction
9.1
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Introduction
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupts, a state machine for each
peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and
provides clock and reset control. Many of the operations of the PSC are transparent to user (software),
such as power on and reset control. However, the PSC module(s) also provide you with interface to
control several important power, clock and reset operations. The module level power, clock and reset
operations managed and controlled by the PSC are the focus of this chapter.
The PSC includes the following features:
• Manages chip power-on/off
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Manages on-chip RAM sleep modes (for DSP memories and L3 RAM)
• Supports IcePick emulation features: power, clock and reset
9.2
Power Domain and Module Topology
This device includes two PSC modules. Each PSC module consists of:
• an Always On power domain
• an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in
the DSP subsystem and the L3 RAM, respectively
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 9-1 and Table 9-2 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 9.2.2.
Even though there are 2 PSC modules with 2 power domains each on the device, both PSC modules and
all the power domains are powered by the CVDD pins of the device. All power domains are on when the
chip is powered on. There is no provision to remove power externally for the non Always On domains, that
is, the pseudo/internal power domains.
There are a few modules/peripherals on the device that do not have an LPSC assigned to them. These
modules do not have their module reset/clocks controlled by the PSC module. The decision to assign an
LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will
result in significant power savings. This typically depends on the size and the frequency of operation of the
module.
NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC,
Timer64P0/P1, and I2C0); from a power savings stand point, clock-gating these peripherals
does not result in significant power savings.
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Table 9-1. PSC0 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_0 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3_0 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3_0 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD0
AlwaysON (PD0)
SwRstDisable
—
6
ARM Interrupt Controller
AlwaysON (PD0)
Enable
—
7
ARM RAM/ROM
AlwaysON (PD0)
Enable
Yes
8
Not Used
—
—
—
9
UART0
AlwaysON (PD0)
SwRstDisable
—
10
SCR0 (BR0, BR1, BR2, BR8)
AlwaysON (PD0)
Enable
Yes
11
SCR1 (BR4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (BR3, BR5, BR6)
AlwaysON (PD0)
Enable
Yes
13
PRU
AlwaysON (PD0)
SwRstDisable
—
14
ARM
AlwaysON (PD0)
SwRstDisable
—
15
DSP
PD_DSP (PD1)
Enable
—
Table 9-2. PSC1 Default Module Configuration
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
0
EDMA3_1 Channel Controller 0
AlwaysON (PD0)
SwRstDisable
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
Not Used
—
—
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
Not Used
—
—
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
DDR2/mDDR
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 (+ McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8-9
Not Used
—
—
—
10
SPI1
AlwaysON (PD0)
SwRstDisable
—
11
I2C1
AlwaysON (PD0)
SwRstDisable
—
12
UART1
AlwaysON (PD0)
SwRstDisable
—
13
UART2
AlwaysON (PD0)
SwRstDisable
—
14
McBSP0 (+ McBSP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
15
McBSP1 (+ McBSP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
16
Not Used
—
—
—
17
eHRPWM0/1
AlwaysON (PD0)
SwRstDisable
—
18
MMC/SD1
AlwaysON (PD0)
SwRstDisable
—
19
Not Used
—
—
—
20
eCAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EDMA3_1 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR F0
AlwaysON (PD0)
Enable
Yes
25
SCR F1
AlwaysON (PD0)
Enable
Yes
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Table 9-2. PSC1 Default Module Configuration (continued)
LPSC
Number
Module Name
Power Domain
Default Module
State
Auto Sleep/
Wake Only
26
SCR F2
AlwaysON (PD0)
Enable
Yes
27
SCR F6
AlwaysON (PD0)
Enable
Yes
28
SCR F7
AlwaysON (PD0)
Enable
Yes
29
SCR F8
AlwaysON (PD0)
Enable
Yes
30-31
Not Used
—
—
—
9.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In this device, for both PSC0 and PSC1, the Always ON domain (or PD0 power domain), is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state (See details on
PDCTL register).
Additionally, for both PSC0 and PSC1, the PD1 power domains, the internal/pseudo power domain can
either be in the ON state or OFF state. Furthermore, for these power domains the transition from ON to
OFF state is further qualified by the PSC0/1.PDCTL1.PDMODE settings. The PDCTL1.PDMODE settings
determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128KB Shared RAM
NOTE: Currently programming the PD1 power domain state to OFF is not supported. You should
leave both the PDCTL1.NEXT and PDCTL1.PDMODE values at default/power on reset
values.
Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of
the device. There is no capability to individually remove voltage/power from the DSP or
Shared RAM power domains
.
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9.2.2 Module States
The PSC defines several possible states for a module. This various states are essentially a combination of
the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The various
module states are defined in Table 9-3.
The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in
Auto Sleep mode, it will transition back to the clock disabled state (automatically sleep) after servicing the
internal read/write access request where as in Auto Wake mode, on receiving the first internal read/write
access request, the module will permanently transition from the clock disabled to clock enabled state
(automatically wake).
When the module state is programmed to Disable, SwRstDisable, Auto Sleep or Auto Wake modes,
where in the module clocks are off/disabled, an external event or I/O request cannot enable the clocks.
For the module to appropriately respond to such external request, it would need to be reconfigured to the
Enable state.
9.2.2.1
Auto Sleep/Wake Only Configurations and Limitation
NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes. If the
module clocks need to gated/disabled for power savings, you should program the module
state to Disable. For Auto Sleep/Auto Wake Only modules, disabling the clock is not
supported and they should be kept in their default “Enable” state.
Table 9-1 and Table 9-2 each have a column to indicate whether or not the LPSC configuration for a
module is Auto Sleep/Wake Only. Modules that have a “Yes” marked for the Auto Sleep/Wake Only
column can be programmed in software to be in Enable, Auto Sleep and Auto Wake states only; that is, if
the software tries to program these modules to Disable, SyncReset, or SwRstDisable state the power
sleep controller ignores these transition requests and transitions the module state to Enable.
9.2.2.2
Local Reset
In addition to module reset, the following modules can be reset using a special local reset that is also a
part of the PSC module control for resets.
• DSP: When the DSP local reset is asserted the DSP internal memories (L1P, L1D and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of DSP subsystem, as the DSP
module reset would. Local Reset is useful in cases where the DSP is in enable or disable state; since
when module is in SyncReset or SwRstDisable state the module reset is asserted, and the module
reset takes precedence over the local reset.
• ARM: When the ARM local reset is asserted the entire ARM processor is reset , including cache etc.
This does not include the ARM RAM/ROM or ARM interrupt controller module as these exist outside
the ARM core. The local reset for ARM additionally ensures that any outstanding requests are
completed before ARM is reset, therefore for scenarios where it is needed to just reset the ARM locally
but not change the state of clocks, user can use ARM local reset feature.
The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the
module that supports local reset):
1. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset.
2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset.
If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted.
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Table 9-3. Module States
168
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has
its clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has
its module clock off. This state is typically used for disabling a module
clock to save power. This device is designed in full static CMOS, so when
you stop a module clock, it retains the module’s state. When the clock is
restarted, the module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it
has its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it
has its clock disabled. After initial power-on, several modules come up in
the SwRstDisable state. Generally, software is not expected to initiate this
state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it
can “automatically” transition to “Enable” state whenever there is an
internal read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re
de-asserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data. See Section 9.2.2.1 for
additional considerations, constraints, limitations around this mode.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted
and its module clock disabled, similar to the Disable state. However this is
a special state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from
then on (with module reset re de-asserted and module clock on), without
any software intervention. The transition from sleep to enabled state has
some cycle latency associated with it. It is not envisioned to use this mode
when peripherals are fully operational and moving data. See
Section 9.2.2.1 for additional considerations, constraints, limitations around
this mode.
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9.3
Executing State Transitions
This section describes how to execute the state transitions modules.
9.3.1 Power Domain State Transitions
This device consists of two types of domain (in each PSC controller):
• Always On domain(s)
• pseudo/RAM power domain(s)
The Always On power domains are always in the ON state when the chip is powered on. You are not
allowed to change the power domain state to OFF.
The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with
these domains (L1/L2 for PD_DSP in PSC0 and Shared RAM for PD_SHRAM in PSC1) so that these
RAMs can run in lower power sleep modes via the power sleep controller.
NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported;
therefore, these domains and the RAM should be left in their default power on state.
As mentioned in Section 9.2, the pseudo/RAM power domains are powered down internally,
and in this context powering down does not imply removing the core voltage from pins
externally.
9.3.2 Module State Transitions
This section describes the procedure for transitioning the module state (clock and reset control). Note that
some peripherals have special programming requirements and additional recommended steps you must
take before you can invoke the PSC module state transition. See the individual peripheral user guides for
more details. For example, the external memory controller requires that you first place the SDRAM
memory in self-refresh mode before you invoke the PSC module state transitions, if you want to maintain
the memory contents.
The following procedure is directly applicable for all modules that are controlled via the PSC (shown in
Table 9-1 and Table 9-2), except for the core(s). To transition the DSP or ARM module state, there are
additional system considerations and constraints that you should be aware of. These system
considerations and the procedure for transitioning the DSP or ARM module state are described in details
in the Power Management chapter.
NOTE: In the following procedure, x is 0 for modules in PD0 (Power Domain 0 or Always On
domain) and x is 1 for modules in PD1 (Power Domain 1). See Table 9-1 and Table 9-2 for
power domain associations.
The procedure for module state transitions is:
1. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
2. Set the NEXT bit in MDCTLn to SwRstDisable (0), SyncReset (1), Disable (2h), Enable (3h), Auto
Sleep (4h) or Auto Wake (5h).
NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step. Transitions do not
actually take place until you set the GO[x] bit in PTCMD in a later step.
3. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s).
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only
after the GOSTAT[x] bit in PTSTAT is cleared to 0.
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IcePick Emulation Support in the PSC
The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the
state of power domains and modules. This IcePick support only applies to the following modules:
• DSP [MDCTL15]
• ARM [MDCTL14]
In particular, Table 9-4 shows IcePick emulation commands recognized by the PSC.
Table 9-4. IcePick Emulation Commands
Power On and
Enable Features
Power On and Enable Descriptions
Reset Features
Reset Descriptions
Inhibit Sleep
Allows emulation to prevent software from
transitioning the module out of the enable state.
Assert Reset
Allows emulation to assert the
module’s local reset.
Force Power
Allows emulation to force the power domain into
an on state. Not applicable as AlwaysOn power
domain is always on.
Wait Reset
Allows emulation to keep local
reset asserted for an extended
period of time after software
initiates local reset de-assert.
Force Active
Allows emulation to force the module into the
enable state.
Block Reset
Allows emulation to block
software initiated local and
module resets.
NOTE: When emulation tools remove the above commands, the PSC immediately executes a state
transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in
MDCTLn, as set by software.
9.5
PSC Interrupts
The PSC has an interrupt that is tied to the core interrupt controller. This interrupt is named PSCINT in the
interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.
9.5.1 Interrupt Events
The PSC interrupt is generated when any of the following events occur:
• Power Domain Emulation Event (applies to pseudo/RAM power domain only)
• Module State Emulation event
• Module Local Reset Emulation event
These interrupt events are summarized in Table 9-5 and described in more detail in this section.
Table 9-5. PSC Interrupt Events
Interrupt Enable Bits
Control Register
Enable Bit
Interrupt Condition
PDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the power domain state
MDCTLn
EMUIHBIE
Interrupt occurs when the emulation alters the module state
MDCTLn
EMURSTIE
Interrupt occurs when the emulation tries to alter the module’s local reset
The PSC interrupt events only apply when IcePick emulation alters the state of the module from the
user-programmed state in the NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to
the modules listed in Section 9.4; therefore, the PSC interrupt conditions only apply to those modules
listed.
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9.5.1.1
Power Domain Emulation Events
A power domain emulation event occurs when emulation alters the state of a power domain (does not
apply to the Always On domain). Status is reflected in the EMUIHB bit in PDSTATn. In particular, a power
domain emulation event occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
on state
• When force power is asserted by emulation and power domain is not already in the on state
• When force active is asserted by emulation and power domain is not already in the on state
NOTE:
9.5.1.2
Putting the pseudo/RAM power domain associated with the DSP (PD_DSP) to the off state
currently is not supported.
Module State Emulation Events
A module state emulation event occurs when emulation alters the state of a module. Status is reflected in
the EMUIHB bit in the module status register (MDSTATn). In particular, a module state emulation event
occurs under the following conditions:
• When inhibit sleep is asserted by emulation and software attempts to transition the module out of the
enable state
• When force active is asserted by emulation and module is not already in the enable state
9.5.1.3
Local Reset Emulation Events
A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected
in the EMURST bit in the module status register (MDSTATn). In particular, a module local reset emulation
event occurs under the following conditions:
• When assert reset is asserted by emulation although software de-asserted the local reset
• When wait reset is asserted by emulation
• When block reset is asserted by emulation and software attempts to change the state of local reset
9.5.2 Interrupt Registers
The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0), the EMUIHBIE and the
EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support, as specified in
Section 9.4).
NOTE:
To interrupt the CPU, the power sleep controller interrupt (PSC0_ALLINT and
PSC1_ALLINT) must also be enabled appropriately in the ARM interrupt controller. For
details on the ARM interrupt controller, see the ARM Interrupt Controller (AINTC) chapter.
The PSC interrupt status bits are:
• For DSP:
– The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).
– The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain
associated with DSP memories.
• For ARM:
– The M[14] bit in the module error pending register 0 (MERRPR0) in PSC0 module.
– The EMUIHB and the EMURST bits in the module status register for ARM (MDSTAT14).
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The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or
power domain has generated an emulation interrupt and then software can read the corresponding status
bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine
which event caused the interrupt.
The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module
error clear register (MERRCR0), or the bit corresponding to the power domain number in the power error
clear register (PERRCR) in PSC0 module.
The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register. When set, this bit forces the
PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set)
when the ALLEV bit in the INTEVAL is set to 1, the PSC interrupt is re-asserted to the interrupt controller.
Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do
not miss any PSC interrupts.
See Section 9.6 for a description of the PSC registers.
9.5.3 Interrupt Handling
Handle the PSC interrupts as described in the following procedure:
First, enable the interrupt:
1. Set the EMUIHBIE bit in PDCTLn, the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the
interrupt events that you want.
NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event
becomes active.
2. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. To
interrupt the CPU, PSCn_ALLINT must be enabled in the device interrupt controller. See the ARM
Interrupt Controller (AINTC) chapter for more information on interrupts.
The CPU enters the interrupt service routine (ISR) when it receives the interrupt.
1. Read the P[n] bit in PERRPR, and/or the M[n] bit in MERRPR0, the M[n] bit in MERRPR1, to
determine the source of the interrupt(s).
2. For each active event that you want to service:
(a) Read the event status bits in PDSTATn and MDSTATn, depending on the status bits read in the
previous step to determine the event that caused the interrupt.
(b) Service the interrupt as required by your application.
(c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status.
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt
controller, if there are still any active interrupt events.
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9.6
PSC Registers
Table 9-6 lists the memory-mapped registers for the PSC0 and Table 9-7 lists the memory-mapped
registers for the PSC1.
Table 9-6. Power and Sleep Controller 0 (PSC0) Registers
Address
Acronym
Register Description
01C1 0000h
REVID
Revision Identification Register
Section 9.6.1
Section
01C1 0018h
INTEVAL
Interrupt Evaluation Register
Section 9.6.2
01C1 0040h
MERRPR0
Module Error Pending Register 0 (module 0-15)
Section 9.6.3
01C1 0050h
MERRCR0
Module Error Clear Register 0 (module 0-15)
Section 9.6.5
01C1 0060h
PERRPR
Power Error Pending Register
Section 9.6.7
01C1 0068h
PERRCR
Power Error Clear Register
Section 9.6.8
01C1 0120h
PTCMD
Power Domain Transition Command Register
Section 9.6.9
01C1 0128h
PTSTAT
Power Domain Transition Status Register
Section 9.6.10
01C1 0200h
PDSTAT0
Power Domain 0 Status Register
Section 9.6.11
01C1 0204h
PDSTAT1
Power Domain 1 Status Register
Section 9.6.12
01C1 0300h
PDCTL0
Power Domain 0 Control Register
Section 9.6.13
01C1 0304h
PDCTL1
Power Domain 1 Control Register
Section 9.6.14
01C1 0400h
PDCFG0
Power Domain 0 Configuration Register
Section 9.6.15
01C1 0404h
PDCFG1
Power Domain 1 Configuration Register
Section 9.6.16
01C1 0800h01C1 083Ch
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15)
Section 9.6.17
01C1 0A00h01C1 0A3Ch
MDCTL0MDCTL15
Module Control n Register (modules 0-15)
Section 9.6.18
Table 9-7. Power and Sleep Controller 1 (PSC1) Registers
Address
Acronym
Register Description
01E2 7000h
REVID
Revision Identification Register
Section 9.6.1
Section
01E2 7018h
INTEVAL
Interrupt Evaluation Register
Section 9.6.2
01E2 7040h
MERRPR0
Module Error Pending Register 0 (module 0-31)
Section 9.6.4
01E2 7050h
MERRCR0
Module Error Clear Register 0 (module 0-31)
Section 9.6.6
01E2 7060h
PERRPR
Power Error Pending Register
Section 9.6.7
01E2 7068h
PERRCR
Power Error Clear Register
Section 9.6.8
01E2 7120h
PTCMD
Power Domain Transition Command Register
Section 9.6.9
01E2 7128h
PTSTAT
Power Domain Transition Status Register
Section 9.6.10
01E2 7200h
PDSTAT0
Power Domain 0 Status Register
Section 9.6.11
01E2 7204h
PDSTAT1
Power Domain 1 Status Register
Section 9.6.12
01E2 7300h
PDCTL0
Power Domain 0 Control Register
Section 9.6.13
01E2 7304h
PDCTL1
Power Domain 1 Control Register
Section 9.6.14
01E2 7400h
PDCFG0
Power Domain 0 Configuration Register
Section 9.6.15
01E2 7404h
PDCFG1
Power Domain 1 Configuration Register
Section 9.6.16
01E2 7800h01E2 787Ch
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31)
Section 9.6.17
01E2 7A00h01E2 7A7Ch
MDCTL0MDCTL31
Module Control n Register (modules 0-31)
Section 9.6.19
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9.6.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 9-1 and described in Table 9-8.
Figure 9-1. Revision Identification Register (REVID)
31
0
REV
R-4482 5A00h
LEGEND: R = Read only; -n = value after reset
Table 9-8. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4482 5A00h
Description
Peripheral revision ID.
9.6.2 Interrupt Evaluation Register (INTEVAL)
The interrupt evaluation register (INTEVAL) is shown in Figure 9-2 and described in Table 9-9.
Figure 9-2. Interrupt Evaluation Register (INTEVAL)
31
16
Reserved
R-0
15
1
0
Reserved
ALLEV
R-0
W-0
LEGEND: R = Read only; W= Write only; -n = value after reset
Table 9-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit
31-1
0
174
Field
Reserved
Value
0
ALLEV
Description
Reserved
Evaluate PSC interrupt (PSCn_ALLINT).
0
A write of 0 has no effect.
1
A write of 1 re-evaluates the interrupt condition.
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9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 9-3 and described in
Table 9-10.
Figure 9-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31
16
Reserved
R-0
15
14
M[15]
M[14]
13
Reserved
0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit
31-16
15
14
13-0
Field
Reserved
Value
0
Reserved
M[15]
Module interrupt status bit for module 15 (DSP).
0
Module 15 does not have an error condition.
1
Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
M[14]
Reserved
Description
Module interrupt status bit for module 14 (ARM).
0
Module 14 does not have an error condition.
1
Module 14 has an error condition. See the module status 14 register (MDSTAT14) for the error
condition.
0
Reserved
9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 9-4.
Figure 9-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
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9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 9-5 and described in Table 9-11.
Figure 9-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31
16
Reserved
R-0
15
14
M[15]
M[14]
13
Reserved
0
W-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit
31-16
15
14
13-0
Field
Reserved
Value
0
M[15]
Reserved
Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0
A write of 0 has no effect.
1
A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
M[14]
Reserved
Description
Clears the interrupt status bit (M[14]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 14 register (MDSTAT14).
0
A write of 0 has no effect.
1
A write of 1 clears the M[14] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT14.
0
Reserved
9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 9-6.
Figure 9-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31
0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
176
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9.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 9-7 and described in Table 9-12.
Figure 9-7. Power Error Pending Register (PERRPR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
RAM/Pseudo (PD1) power domain interrupt status.
0
RAM/Pseudo power domain does not have an error condition.
1
RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0
Reserved
9.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 9-8 and described in Table 9-13.
Figure 9-8. Power Error Clear Register (PERRCR)
31
16
Reserved
R-0
15
1
0
Reserved
2
P[1]
Rsvd
R-0
W-0
R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
P[1]
Reserved
Description
Reserved
Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0
A write of 0 has no effect.
1
A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0
Reserved
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9.6.9 Power Domain Transition Command Register (PTCMD)
The power domain transition command register (PTCMD) is shown in Figure 9-9 and described in
Table 9-14.
Figure 9-9. Power Domain Transition Command Register (PTCMD)
31
16
Reserved
R-0
15
1
0
Reserved
2
GO[1]
GO[0]
R-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 9-14. Power Domain Transition Command Register (PTCMD) Field Descriptions
Bit
31-2
1
0
178
Field
Reserved
Value
0
GO[1]
Description
Reserved
RAM/Pseudo (PD1) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
PDCTL.NEXT for this domain, and MDCTL.NEXT for all the modules residing on this domain). If any of
the NEXT fields are not matching the corresponding current state (PDSTAT.STATE, MDSTAT.STATE),
the PSC will transition those respective domain/modules to the new NEXT state.
GO[0]
Always ON (PD0) power domain GO transition command.
0
A write of 0 has no effect.
1
A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching
the corresponding current state (MDSTAT.STATE), the PSC will transition those respective
domain/modules to the new NEXT state.
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9.6.10 Power Domain Transition Status Register (PTSTAT)
The power domain transition status register (PTSTAT) is shown in Figure 9-10 and described in
Table 9-15 .
Figure 9-10. Power Domain Transition Status Register (PTSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
GOSTAT[1]
GOSTAT[0]
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
GOSTAT[1]
Description
Reserved
RAM/Pseudo (PD1) power domain transition status.
0
No transition in progress.
1
RAM/Pseudo power domain is transitioning (that is, either the power domain is transitioning or modules
in this power domain are transitioning).
GOSTAT[0]
Always ON (PD0) power domain transition status.
0
No transition in progress.
1
Modules in Always ON power domain are transitioning. Always On power domain is transitioning.
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9.6.11 Power Domain 0 Status Register (PDSTAT0)
The power domain 0 status register (PDSTAT0) is shown in Figure 9-11 and described in Table 9-16.
Figure 9-11. Power Domain 0 Status Register (PDSTAT0)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
180
Reserved
Emulation alters domain state.
POR
7-5
Description
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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9.6.12 Power Domain 1 Status Register (PDSTAT1)
The power domain 1 status register (PDSTAT1) is shown in Figure 9-12 and described in Table 9-17.
Figure 9-12. Power Domain 1 Status Register (PDSTAT1)
31
16
Reserved
R-0
15
11
10
9
8
Reserved
12
EMUIHB
Rsvd
PORDONE
POR
7
Reserved
5
4
STATE
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions
Bit
Field
31-12
Reserved
11
EMUIHB
10
Reserved
9
PORDONE
8
Value
0
Reserved
4-0
STATE
Reserved
Emulation alters domain state.
0
Interrupt is not active. No emulation altering user-desired power domain states.
1
Interrupt is active. Emulation alters user-desired power domain state.
0
Reserved
Power_On_Reset (POR) Done status
0
Power domain POR is not done.
1
Power domain POR is done.
POR
7-5
Description
Power Domain Power_On_Reset (POR) status. This bit reflects the POR status for this power
domain including all modules in the domain.
0
Power domain POR is asserted.
1
Power domain POR is de-asserted.
0
Reserved
0-1Fh
Power Domain Status.
0
Power domain is in the off state.
1h
Power domain is in the on state.
2h-Fh
Reserved
10h-1Ah
Power domain is in transition.
1Bh-1Fh
Reserved
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9.6.13 Power Domain 0 Control Register (PDCTL0)
The power domain 0 control register (PDCTL0) is shown in Figure 9-13 and described in Table 9-18.
Figure 9-13. Power Domain 0 Control Register (PDCTL0)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
Reserved
9
EMUIHBIE
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
0-Fh
Power down mode.
0-Eh
Reserved
Fh
11-10
Description
0
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
182
NEXT
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect
since internally this power domain always remains in the on state.
0
Power domain off.
1
Power domain on.
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9.6.14 Power Domain 1 Control Register (PDCTL1)
The power domain 1 control register (PDCTL1) is shown in Figure 9-14 and described in Table 9-19.
Figure 9-14. Power Domain 1 Control Register (PDCTL1)
31
24
15
23
16
Reserved
WAKECNT
R-0
R/W-1Fh
9
8
PDMODE
12
11
Reserved
10
EMUIHBIE
Rsvd
7
Reserved
1
NEXT
0
R-Fh
R-0
R/W-0
R-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions
Bit
Field
31-24
Reserved
23-16
WAKECNT
15-12
PDMODE
Value
0
0-FFh
0-Fh
Core off, RAM array retention, RAM periphery off (deep sleep).
Reserved
4h
Core retention, RAM array off, RAM periphery off.
5h
Core retention, RAM array retention, RAM periphery off (deep sleep).
Reserved
8h
Core on, RAM array off, RAM periphery off.
9h
Core on, RAM array retention, RAM periphery off (deep sleep).
Ah
Core on, RAM array retention, RAM periphery off (light sleep).
Bh
Core on, RAM array retention, RAM periphery on.
Fh
EMUIHBIE
Power down mode.
Core off, RAM array off, RAM periphery off.
Ch-Eh
Reserved
RAM wake count delay value. Not recommended to change the default value (1Fh). Bits 23-30:
GOOD2ACCESS wake delay. Bits 19-16: ON2GOOD wake delay.
1h
6h-7h
9
Reserved
0
2h-3h
11-10
Description
0
Reserved
Core on, RAM array on, RAM periphery on.
Reserved
Emulation alters power domain state interrupt enable.
0
Disable interrupt.
1
Enable interrupt.
8
Reserved
1
Reserved
7-1
Reserved
0
Reserved
0
NEXT
User-desired power domain next state.
0
Power domain off.
1
Power domain on.
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9.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 9-15 and described in
Table 9-20.
Figure 9-15. Power Domain 0 Configuration Register (PDCFG0)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
1
R-0
R-1
R-1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 9-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
184
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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9.6.16 Power Domain 1 Configuration Register (PDCFG1)
The power domain 1 configuration register (PDCFG1) is shown in Figure 9-16 and described in
Table 9-21.
Figure 9-16. Power Domain 1 Configuration Register (PDCFG1)
31
16
Reserved
R-0
15
3
2
Reserved
4
PD_LOCK
ICEPICK
R-0
R-1
R-1
1
0
RAM_PSM ALWAYSON
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 9-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
Bit
Field
31-4
Reserved
3
PD_LOCK
2
1
0
Value
0
Description
Reserved
PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0
PDCTL.NEXT bit is locked and cannot be changed in software.
1
PDCTL.NEXT bit is not locked.
ICEPICK
IcePick support.
0
Not present
1
Present
RAM_PSM
RAM power domain.
0
Not a RAM power domain.
1
RAM power domain.
ALWAYSON
Always ON power domain.
0
Not an Always ON power domain.
1
Always ON power domain.
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9.6.17 Module Status n Register (MDSTATn)
The module status n register (MDSTATn) is shown in Figure 9-17 and described in Table 9-22.
Figure 9-17. Module Status n Register (MDSTATn)
31
18
15
13
17
16
Reserved
EMUIHB
EMURST
R-0
R-0
R-0
12
11
10
9
8
Reserved
MCKOUT
Rsvd
MRST
LRSTDONE
LRST
Reserved
7
6
5
STATE
0
R-0
R-0
R-1
R-0
R-1
R-1
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 9-22. Module Status n Register (MDSTATn) Field Descriptions
Bit
Field
31-18
Reserved
17
EMUIHB
16
Reserved
12
MCKOUT
11
Reserved
10
MRST
8
0
No emulation altering user-desired module state programmed in the NEXT bit in the module control
14 register (MDCTL14) and the module control 15 register (MDCTL15).
1
Emulation altered user-desired state programmed in the NEXT bit in MDCTL14 and MDCTL15. If
you desire to generate a PSCINT upon this event, you must set the EMUIHBIE bit in MDCTL14 and
MDCTL15.
Emulation alters module reset. This bit applies to ARM module (module 14) and DSP module
(module 15). This field is 0 for all other modules.
0
No emulation altering user-desired module reset state.
1
Emulation altered user-desired module reset state. If you desire to generate a PSCINT upon this
event, you must set the EMURSTIE bit in the module control 14 register (MDCTL14) and the
module control 15 register (MDCTL15).
0
Reserved
Module clock output status. Shows status of module clock.
0
Module clock is off.
1
Module clock is on.
1
Reserved
Module reset status. Reflects actual state of module reset.
0
Module reset is asserted.
1
Module reset is de-asserted.
Local reset done. Software is responsible for checking if local reset is done before accessing this
module. This bit applies to ARM module (module 14) and DSP module (module 15). This field is 1
for all other modules.
0
Local reset is not done.
1
Local reset is done.
LRST
Reserved
5-0
STATE
Module local reset status. This bit applies to ARM module (module 14) and DSP module (module
15).
0
Local reset is asserted.
1
Local reset is de-asserted.
0
Reserved
0-3Fh
Module state status: indicates current module status.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
4h-3Fh
186
Reserved
0
LRSTDONE
7-6
Description
Emulation alters module state. This bit applies to ARM module (module 14) and DSP module
(module 15). This field is 0 for all other modules.
EMURST
15-13
9
Value
Indicates transition
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9.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn)
The PSC0 module control n register (MDCTLn) is shown in Figure 9-18 and described in Table 9-23.
Figure 9-18. PSC0 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
10
9
8
Reserved
11
EMUIHBIE
EMURSTIE
LRST
7
Reserved
3
2
NEXT
0
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14) and the module control 15 register (MDCTL15), ignoring and bypassing all the
clock stop request handshakes managed by the PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-11
Reserved
10
EMUIHBIE
9
8
0
Force is disabled.
1
Force is enabled.
0
Reserved
Interrupt enable for emulation alters module state. This bit applies to ARM module (module 14) and
DSP module (module 15).
0
Disable interrupt.
1
Enable interrupt.
EMURSTIE
Interrupt enable for emulation alters reset. This bit applies to ARM module (module 14) and DSP
module (module 15).
0
Disable interrupt.
1
Enable interrupt.
LRST
7-3
Reserved
2-0
NEXT
Module local reset control. This bit applies to ARM module (module 14) and DSP module (module 15).
0
Assert local reset
1
De-assert local reset
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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9.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn)
The PSC1 module control n register (MDCTLn) is shown in Figure 9-19 and described in Table 9-24.
Figure 9-19. PSC1 Module Control n Register (MDCTLn)
31
30
16
FORCE
Reserved
R/W-0
R-0
15
3
2
0
Reserved
NEXT
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions
Bit
Field
31
FORCE
Value
Description
Force enable. This bit forces the module state programmed in the NEXT bit in the module control 14
register (MDCTL14) and the module control 15 register (MDCTL15), ignoring and bypassing all the
clock stop request handshakes managed by the PSC to change the state of the clocks to the module.
Note: It is not recommended to use the FORCE bit to disable the module clock, unless specified.
30-3
Reserved
2-0
NEXT
188
0
Force is disabled.
1
Force is enabled.
0
Reserved
0-3h
Module next state.
0
SwRstDisable state
1h
SyncReset state
2h
Disable state
3h
Enable state
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Chapter 10
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Power Management
Topic
...........................................................................................................................
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
Introduction ....................................................................................................
Power Consumption Overview ..........................................................................
PSC and PLLC Overview ..................................................................................
Features .........................................................................................................
Clock Management ..........................................................................................
ARM Sleep Mode Management ..........................................................................
DSP Sleep Mode Management ...........................................................................
RTC-Only Mode ...............................................................................................
Dynamic Voltage and Frequency Scaling (DVFS) .................................................
Deep Sleep Mode ...........................................................................................
Additional Peripheral Power Management Considerations ..................................
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10.1 Introduction
Power management is an important aspect for most embedded applications. For several applications and
target markets, there may be a specific power budget and requirements to minimize power consumption
for both power supply sizing and battery life considerations. Additionally, lower power consumption results
in more optimal and efficient designs from cost, design, and energy perspectives. This device has several
means of managing the power consumption. This chapter discusses the various power management
features.
10.2 Power Consumption Overview
Power consumed by semiconductor devices has two components: dynamic and static. This can be shown
as:
Ptotal = Pdynamic + Pstatic
The dynamic power is the power consumed to perform work when the device is in active modes (clocks
applied, busses, and I/O switching), that is, analog circuits changing states. The dynamic power is defined
by:
Pdynamic = Capacitance × Voltage2 × Frequency
From the above formula, the dynamic power scales with the clock frequency (device/module frequency for
core operations and switching frequency for I/O). Dynamic power can be reduced by controlling the clocks
in such a way as to either operate at a clock setting just high enough to complete the required operation in
the required timeline or to run at a clock setting until the work is complete and then drastically reduce the
clock frequency or cut off the clocks until additional work must be performed.
In the formula, the dynamic power varies with the voltage squared, so the voltage of operations has
significant impact on overall power consumption and, thus, on the battery life. Dynamic power can be
reduced by scaling the operating voltage, when the performance requirements are not that high and the
device can be operated at a corresponding lower frequency.
The capacitance is the capacitance of the switching nodes, or the load capacitances on the switching I/O
pins.
The static power, as the name suggests, is independent of the switching frequency of the logic. It can be
shown as:
Pstatic = f(leakage current)
It is essentially a function of the “leakage”, or the power consumed by the logic when it is not switching or
is not performing any work. Leakage current is dependent mostly on the manufacturing process used, the
size of the die, etc. Leakage current is unavoidable while power is applied and scales roughly with the
operating junction temperatures. Leakage power can only be avoided by removing power completely from
a device or subsystem. The static power consumption plays a significant role in the Standby Modes (when
the application is not running and in a dormant state) and plays an important role in the battery life for
portable applications, etc.
10.3 PSC and PLLC Overview
The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling
of the clocks to the core and various peripheral modules. The PSC provides a granular support to turn
on/off clocks on a module by module basis. Similarly, the two PLL controllers (PLLC0 and PLLC1) play an
important role in device and module clock generation, and manage the frequency scaling operations for
the device. Together these modules play a significant role in managing the clocks from a power
management feature standpoint. For detailed information on the PSC, see the Power and Sleep Controller
(PSC) chapter. For detailed information on the PLLC0 and PLLC1, see the Device Clocking chapter and
the Phase-Locked Loop Controller (PLLC) chapter.
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10.4 Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 10-1 describes the power management features.
Table 10-1. Power Management Features
Power Management
Description
Features
Clock Management
PLL bypass and
power-down
Both PLLs can be powered-down and run in
bypass mode when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON
Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic power consumption of the
core and I/O (if any free running I/O clocks).
ARM subsystem
sleep modes
The ARM CPU can be put in sleep mode.
Additionally, the ARM subsystem clock can be
completely gated when not in use.
Reduces the dynamic power consumption.
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode.
Additionally, the DSP subsystem clock can be
completely gated when not in use.
Reduces the dynamic power consumption.
RTC-only mode
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Dynamic Voltage and
Frequency Scaling
(DVFS)
The operating voltage and frequency of the device
can be dynamically scaled to meet the
requirements of the application.
Deep Sleep Mode
All internal clocks of the device can be turned
on/off at the OSCIN level. The deep sleep function
can be controlled externally through the
DEESLEEP pin or internally through the
RTC_ALARM pin.
USB PHY power-down
The USB2.0 PHY can be powered-down.
Minimizes the USB2.0 I/O power consumption
when not in use.
DDR2/mDDR
self-refresh mode
Allows memory to retain its contents while the rest
of the system is powered down.
mDDR and DDR2 can be clock gated to reduce the
dynamic power consumption or the entire device
can be powered down to reduce the static power
consumption.
LVCMOS I/O buffer
receiver disable
LVCMOS I/O buffer receivers are disabled.
Minimizes the I/O power consumption.
Internal pull-up and
pull-down resistor
control
The internal pull-ups and pull-downs are
enabled/disabled by groups.
Reduces the I/O leakage power.
Core Sleep Management
Voltage Management
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Dynamic Voltage and Frequency Scaling
Reduces the dynamic power consumption of the
core and I/O as well as standby power
System/Device Sleep Management
Reduces the dynamic power consumption of the
core and I/O.
Peripheral I/O Power Management
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10.5 Clock Management
10.5.1 Module Clock ON/OFF
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's dynamic/switching power consumption down to zero. This device is designed in full static
CMOS; thus, when a module clock stops, the module's state is preserved and retained. When the clock is
restarted, the module resumes operating from the stopping point.
NOTE: Stopping clocks to a module only affects dynamic power consumption, it does not affect
static power consumption of the module or the device.
The power and sleep controller (PSC) module controls module clock gating. If a module's clock(s) is
stopped while being accessed, the access may not occur, and it can potentially result in unexpected
behavior. The PSC provides some protection against such erroneous conditions by monitoring the internal
bus activity to ensure there are no accesses to the module from the internal bus, before allowing module’s
internal clock to be gated. However, it is still recommended that software must ensure that all of the
transactions to the module are finished prior to disabling the clocks.
The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller
(PSC) chapter.
NOTE: To preserve the state of the module, the module state in the PSC must be set to Disable. In
this state, the module reset is not asserted and only the module clock is turned off.
Furthermore, special consideration must be given to DSP/ARM clock on/off. The procedure to turn the
core clock on/off is further described in Section 10.7.4.
Additionally some peripherals implement additional power saving features by automatically shutting of
clock to components within the module, when the logic is not active. This is transparent to you, but
reduces overall dynamic power consumption when modules are not active.
10.5.2 Module Clock Frequency Scaling
Module clock frequency is scalable by programming the PLL multiply and divide parameters. Additionally,
some modules might also have internal clock dividers. Reducing the clock frequency reduces the
dynamic/switching power consumption, which scales linearly with frequency.
The Device Clocking chapter details the clocking structure of the device. The Phase-Locked Loop
Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency
constraints.
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10.5.3 PLL Bypass and Power Down
You can bypass each PLL in this device. Bypassing the PLL sends a bypass clock instead of the PLL
VCO output (PLLOUT) to the system clocks of the PLLC. For PLLC0, the bypass clock is selected from
either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. For PLLC1, the bypass clock is always
OSCIN. The OSCIN frequency is typically, at most, up to 50 MHz.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity. This can lower the
overall dynamic power consumption, which is linearly proportional to the frequency.
When the PLL controller is placed in bypass mode, the PLL retains its frequency lock. This allows you to
switch between bypass mode and PLL mode without having to wait for the PLL to relock. However,
keeping the PLL locked consumes power. You can also power-down the PLL when bypassing it to
minimize the overall power consumed by the PLL module. The advantage of bypassing the PLL without
powering it down is that you do not have to incur the PLL lock time when switching back to a normal
operating level.
The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass
and PLL power down.
10.6 ARM Sleep Mode Management
10.6.1 ARM Wait-For-Interrupt Sleep Mode
The ARM module can be put into a low-power state using a special sleep mode called wait-for-interrupt
(WFI). When the wait-for-interrupt mode is enabled, all internal clocks within the ARM9 module are shut
off, the core is completely inactive and only resumes operation after receiving an interrupt. This is a
feature for dynamic power management of the ARM processor itself, it does not impact the static power.
NOTE: To enable the WFI mode, the ARM needs to be in supervisor mode.
You can enable the WFI mode via the CP15 register #7 using the following instruction:
• MCR p15, #0, <Rd>, c7, c0, #4
Once the ARM module transitions into the WFI mode, it will remain in this state until an interrupt request
(IRQ/FIQ) occurs.
The following sequence exemplifies how to enter the WFI mode:
• Enable any interrupt (for example, an external interrupt) that you plan to use as the wake-up interrupt
to exit from the WFI mode.
• Enable the WFI mode using the following CP15 instruction:
– MCR p15, #0, r3, c7, c0, #4
The following sequence describes the procedure to wake-up from the WFI mode:
• To wake-up from the WFI mode, trigger any enabled interrupt (for example, an external interrupt).
• The ARM’s PC jumps to the IRQ/FIQ vector and you must handle the interrupt in an interrupt service
routine (ISR).
Exit the ISR and continue normal program execution starting from the instruction immediately following the
instruction that enabled the WFI mode.
NOTE: The ARM interrupt controller (AINTC) and the module sourcing the wake-up interrupt (for
example, GPIO or watchdog timer) must not be disabled, or the device will never wake up.
For more information on this sleep mode, see the ARM926EJ-S Technical Reference Manual
(TRM), downloadable from http://infocenter.arm.com/help/index.jsp.
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10.6.2 ARM Clock OFF
The software must be structured such that no peripheral is allowed to access the ARM resources before
disabling the clocks to the ARM subsystem. The ARM must check for the completion of all its master
peripheral initiated requests (that is, CFG and DMA port operations, etc.). The DSP must check for the
completion of all transactions initiated by it and the peripherals controls by the DSP to the ARM resources.
ARM module clock off sequence:
1. The DSP stops all masters from accessing the ARM and ARM memory.
2. The DSP polls all masters for write-completion status (or wait n number of cycles, if the transfer
completion status is not implemented).
3. The ARM must have the ARM Clock Stop Request interrupt (ARMCLKSTOPREQ, ARM interrupt # 90)
enabled and the associated interrupt service routine (ISR) set up before the DSP initiates the following
ARM clock shutdown procedure.
(a) Initiate the ARM clock off sequence by issuing the ARM clock stop command (PSC DISABLE
Command) to the ARM subsystem by writing a 2h to the NEXT bit field in the ARM local power
sleep controller (LPSC) module control register (PSC0.MDCTL14).
(b) Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the
ARM module. This generates the ARMCLKSTOPREQ interrupt to the ARM.
(c) Check (poll for 0) the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[0] bit transitions to 0 when the ARM
executes the wait-for-interrupt instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the ARM LPSC module status register
(PSC0.MDSTAT14) indicating the ARM clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the ARM within the ARM Clock Stop Request interrupt
ISR:
1. Check for completion of all ARM master requests (the ARM polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as the “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[0], CHIPSIG[1], etc.) that will be used to wake-up the ARM during the ARM
clock-on sequence.
3. Execute the wait-for-interrupt (WFI) ARM instruction.
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10.6.3 ARM Subsystem Clock ON
The ARM module defaults to the SwRstDisable state; therefore, the DSP side software is responsible for
enabling the clock and releasing the reset to the ARM at power-on reset. If the DSP has put the ARM in
the clock off/Disable state, the following clock on sequence is applicable only when it is required to
wake-up the ARM. Perform the following sequence for the DSP to enable clocks to the ARM:
1. Wait for the GOSTAT[0] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit in the ARM local power sleep controller (LPSC) module control register
(PSC0.MDCTL14) to prepare the ARM module for an enable transition.
3. Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power
domain transition command register (PSC0.PTCMD) to start the state transition sequence for the ARM
module.
4. Check (poll for 0) the GOSTAT[0] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.
5. Wait for the STATE bit field in the ARM LPSC module status register (PSC0.MDSTAT14) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the ARM (to exit the
wait-for-interrupt mode). This example assumes that the ARM enabled this interrupt before
entering its wait-for-interrupt sleep mode state.
For the DSP to wake the ARM if transitioning from the Disable state, trigger an ARM interrupt that has
previously been configured as a wake-up interrupt.
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10.7 DSP Sleep Mode Management
10.7.1 DSP Sleep Modes
The C674x megamodule has an internal power down controller (PDC) module that provides additional
power management features in addition to clock management control provided by the device-level power
and sleep controller (PSC) module. For information on the PDC module, see the TMS320C674x DSP
Megamodule Reference Guide (SPRUFK5).
10.7.2 C674x DSP CPU Sleep Mode
The DSP CPU can be put in a low-power state by executing the IDLE instruction. For information on the
IDLE instruction, see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8).
10.7.3 C674x Megamodule Sleep Mode
The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule, by
the power-down controller (PDC) module. In shutting down the entire C674x megamodule, the PDC can
internally clock gate off the following components of the megamodule and internal memories of the DSP
subsystem:
• C674x CPU
• Level 1 Program Memory Controller (PMC)
• Level 1 Data Memory Controller (DMC)
• Level 2 Unified Memory Controller (UMC)
• Extended Memory Controller (EMC)
• L1P Memory
• L1D Memory
• L2 Memory
Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a
lot more power, as compared to just executing the IDLE instruction to put only the CPU in idle mode.
For information on putting the C674x megamodule in the low-power mode using the PDC, see the
TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).
10.7.4 C674x Megamodule Clock ON/OFF
The C674x megamodule can clock gate its own components to save power. Additional power saving can
be achieved by stopping the clock sourced (PLL output) to the C674x megamodule by programming the
power and sleep controller (PSC) module to place the megamodule in the Disable state. The DSP cannot
perform this programming task on its own, because the DSP will not be able to complete the PSC
programming sequence if its clock source is gated in the middle of the process.
If additional power saving is desired (more then just power savings obtained by using the power down
controller), then you can choose to disable the clock to the DSP using the PSC. The ARM is responsible
for programming the PSC to disable the clock going to the C674x megamodule at the root level (stopping
PLL0_SYSCLK1 at the PLL output). By clock gating the megamodule at the root, this enables saving
additional clock tree power (for the path from the PLL to the megamodule boundary). The ARM is also
responsible for programming the PSC to enable the C674x megamodule.
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10.7.4.1 C674x Megamodule Clock OFF
The software must be structured such that no peripheral is allowed to access the DSP resources before
disabling the DSP clocks. The DSP must check for the completion of all its master peripheral initiated
requests (that is, IDMA, MDMA, EDMA, cache operations, etc.). The ARM must check for the completion
of all transactions initiated by it and the peripherals controls by it to the DSP resources.
1. The ARM stops all masters from accessing the DSP and DSP memory.
2. The ARM polls all masters for write-completion status (or wait n number of cycles, if the transfer
completion status is not implemented).
3. The DSP must have the power-down controller interrupt PDC_INT (DSP interrupt #118) enabled and
the PDC interrupt service routine (ISR) set up before the ARM initiates the following DSP clock
shutdown procedure.
(a) Initiate the DSP clock off sequence by issuing the DSP clock stop command (PSC DISABLE
Command) to the DSP subsystem by writing a 2h to the NEXT bit field in the DSP local power
sleep controller (LPSC) module control register (PSC0.MDCTL15).
(b) Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP
module. This generates the PDC_INT interrupt to the DSP.
(c) Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT)
for power transition sequence completion. The GOSTAT[1] bit transitions to 0 when the DSP
executes the IDLE instruction from inside its interrupt service routine (ISR).
(d) Check (poll for 2h) the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15)
indicating the DSP clock stop sequence completion (STATE: Disable).
The following sequence should be executed by the DSP within the PDC interrupt ISR:
1. Check for completion of all DSP master requests (the DSP polls transfer completion statuses of all
Master peripherals).
2. Enable the interrupt to be used as “wake-up” interrupt (for example, one of the CHIPSIG interrupts
controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module
chapter—CHIPSIG[2], CHIPSIG[3], or CHIPSIG[4]/NMI interrupt) that will be used to wake-up the DSP
during the DSP clock-on sequence.
NOTE: The power-down command register (PDCCMD) in the power-down controller (PDC) can only
be written while the DSP is in Supervisor mode.
3. Write a 0001 5555h to PDCCMD.
4. Execute the IDLE instruction.
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10.7.4.2 C674x Megamodule Clock ON
The C674x megamodule defaults to the Enable state; therefore, the DSP subsystem clock is on, and the
following sequence is typically not needed. This clock on sequence is only required to wake-up the DSP, if
the ARM put the DSP in a clock off state. Perform the following sequence for the ARM to enable clocks to
the DSP:
1. Wait for the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) to clear to
0. You must wait for the power domain to finish any previously initiated transitions before initiating a
new transition.
2. Write a 3h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition.
3. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
4. Check (poll for 0) the GOSTAT[1] bit in PSC0.PTSTAT for power transition sequence completion. The
domain is only safely in the new state after the GOSTAT[1] bit is cleared to 0.
5. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
NOTE: This only applies if you are transitioning from the Disable state. If previously in the Disable
state, a wake-up interrupt must be triggered in order to wake the DSP. This example
assumes that the DSP enabled this interrupt before entering its IDLE state. See the DSP
Subsystem chapter for more information on DSP interrupts.
For the ARM to wake the DSP if transitioning from the Disable state, trigger a DSP interrupt that has
previously been configured as a wake-up interrupt.
10.8 RTC-Only Mode
In real-time clock (RTC)-only mode, the RTC is powered on and the rest of the device is completely
powered off (all supplies except the RTC supply are removed). In this mode, the RTC is fully functional
and keeps track of date, hours, minutes, and seconds. In this mode, the overall power consumption would
be significantly lower, as voltage from the rest of the core and I/O logic can be completely removed,
eliminating most of the active and static power of the device, except for what is consumed by the RTC
module, running at 32 kHz.
NOTE: To put the device in RTC-only mode, there is no software control sequence. You can put the
device in the RTC-only mode by removing the power supply from all core and I/O logic,
except for the RTC core logic supply (RTC_CVDD). During wake up, all power sequencing
requirements described in the device-specific data manual must be followed.
Some limitations apply in the RTC-only mode. First, the RTC_ALARM pin is not available as an option for
use as a control to signal an external power supply to reapply power to the rest of the device. This is
because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.
Second, in RTC-only mode, only the RTC register contents are preserved, all other internal memory and
register contents are lost. Mobile DDR and DDR2 contents can be preserved through the use of
self-refresh (see Section 10.10.2). However, software must be in place to restore the context of the
device, for example, reinitialize internal registers, setup cache memory configurations, interrupt vectors,
etc.
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10.9 Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. The
DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be
performed in the required amount of time. This reduces the total power consumption of the device while
still meeting task requirements. DVFS requires control over the clock frequency and the operating voltage
of the device elements. By intelligently switching these elements to their optimal operating points, it is
possible to minimize the power consumption of the device for a given task.
For reasons related to the device (clock architecture, process, etc.), DVFS is used only for a few discrete
steps, not over a continuum of voltage and frequency values. Each step, or operating performance point
(OPP), is composed of a voltage and frequency pair. For an OPP, the frequency corresponds to the
maximum frequency allowed at a voltage, or reciprocally; the voltage corresponds to the minimum voltage
allowed for a frequency. See your device data manual for a list of the OPPs supported by the device.
When applying DVFS, a processor or system always runs at the lowest OPP that meets the performance
requirement at a given time. You determine the optimal OPP for a given task and then switch to that OPP
to save power.
10.9.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See the Device Clocking chapter for information on the clock architecture of the device and
see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. A few things
must be noted when changing the various internal frequencies of the device:
• Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
• SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the CPU clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see the Device
Clocking chapter.
• PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
• Peripheral immunity from CPU clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
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Furthermore, PLL0_SYSCLK2 must always be /2 of the CPU clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the CPU frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the CPU clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
10.9.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
• Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
• Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
10.10 Deep Sleep Mode
This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is
shut down to save power. Registers and memory contents are preserved, thus, upon recovery, the
program may continue from where it left off with minimal overhead involved.
The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The device wakes up from
Deep Sleep mode when the DEEPSLEEP pin is driven high. The DEEPSLEEP pin can be driven by an
external controller or it can be driven internally by the real-time clock (RTC). The RTC method allows for
automatic wake-up at a programmed time.
NOTE: Due to pin multiplexing, the DEEPSLEEP pin can only be driven by an external controller or
its internal real-time clock (RTC). The DEEPSLEEP pin cannot be driven by both an external
controller and its internal real-time clock at the same time.
10.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up
10.10.1.1 Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the
device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register
in the System Configuration (SYSCFG) Module chapter.
6. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep).
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
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9. Begin polling the SLEEPCOMPLETE bit until it is set to 1. This bit is set once the device is woken up
from Deep Sleep mode.
10. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.1.2 Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the
device:
1. The external controller drives the DEEPSLEEP pin high.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 8.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up
10.10.2.1 Entering Deep Sleep Mode
Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device:
1. To preserve DDR2/mDDR memory contents, activate the self-refresh mode and gate the clocks to the
DDR2/mDDR memory controller. You can use partial array self-refresh (PASR) for additional power
savings for mDDR memory.
2. The USB2.0 (USB0) PHY should be disabled, if this interface is used and internal clocks are selected
(see Section 10.11.1).
3. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control
register (PLLCTL) of each PLLC to 0).
4. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each
PLLC to 1).
5. Configure the desired wake-up time as an alarm in the RTC.
6. Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The pin is driven low
since the alarm has not yet occurred.
7. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in
the System Configuration (SYSCFG) Module chapter. This count determines the delay before the
Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).
8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. This automatically clears the SLEEPCOMPLETE bit.
Also, the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low.
For more details on the clock stop procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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10.10.2.2 Exiting Deep Sleep Mode
Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device:
1. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the
DEEPSLEEP pin). This causes the Deep Sleep logic to exit the Deep Sleep mode.
2. When the SLEEPCOUNT delay is complete, the Deep Sleep logic releases the clock to the device and
sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. This automatically clears the SLEEPCOMPLETE
bit.
4. Initialize the PLL controllers as described in Section 8.2.2.2. Note that the state of the PLL controller
registers is preserved during Deep Sleep mode. Therefore, it is not necessary to reprogram all the PLL
controller registers unless a new setting is desired. At minimum, steps 3, 4, and 7-10 of the PLL
initialization procedure must be followed.
5. Enable the clocks to the DDR2/mDDR memory controller, reset the DDR PHY, and then take the
DDR2/mDDR out of self-refresh mode.
6. Configure the desired states to the peripherals and enable as required.
For more details on the clock enable procedure of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
10.10.3 Deep Sleep Sequence
Figure 10-1 illustrates the Deep Sleep sequence:
1. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System
Configuration (SYSCFG) Module chapter.
2. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. The Deep
Sleep mode begins.
3. The PLL controller reference clock is gated.
4. The on-chip oscillator is disabled. If the device is being clocked by an external source, this clock may
stay enabled; the power savings from turning off this clock is minimal.
5. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled.
6. The Deep Sleep counter beings counting valid clock cycles.
7. The count has reached the number specified in the SLEEPCOUNT bit field and the
SLEEPCOMPLETE bit is set. The PLL reference clock is enabled and the Deep Sleep mode ends.
8. Software clears the SLEEPENABLE bit. The SLEEPCOMPLETE bit is automatically cleared.
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Figure 10-1. Deep Sleep Mode Sequence
See Note:
1
2
3
4
5
6
7
8
SLEEPENABLE
(internal)
DEEPSLEEP
CLKGATE
(internal)
PLLC Ref Clk
(internal)
OSC_GZ
(internal)
OSCIN
SLEEPCOMPLETE
(internal)
10.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking
Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the
software to ensure that all peripheral accesses have been completed and peripheral interfaces
appropriately configured for clocks to stop. Therefore, before an external controller drives the
DEESPLEEP pin, a handshaking mechanism must be in place to give software time to prepare the device
for Deep Sleep mode. The implementation of the handshake mechanism is up to the system designer.
10.10.4.1 Entering Deep Sleep Mode
The following example sequence can be used to activate the Deep Sleep mode using a handshaking
mechanism between your device and an external device:
1. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration
(SYSCFG) Module chapter to 0. The DEEPSLEEP pin has no effect until software running on the
device sets this bit.
2. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits
in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. When the pin is
configured for GPIO functionality, the internal DEEPSLEEP signal is still driven by the value on the pin.
3. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal.
4. An external device drives the GP0[8] pin low.
5. Software prepares the device for Deep Sleep mode.
6. Set the SLEEPENABLE bit in DEEPSLEEP to 1. The Deep Sleep mode is immediately started and all
device clocks are stopped. Also, the SLEEPCOMPLETE bit is automatically cleared.
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10.10.4.2 Exiting Deep Sleep Mode
To exit the Deep Sleep mode, follow this sequence:
1. An external device drives the GP0[8] pin high.
2. The device exits the Deep Sleep mode. When the SLEEPCOUNT delay is complete, the Deep Sleep
logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register
(DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter.
3. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.
10.11 Additional Peripheral Power Management Considerations
This section lists additional power management features and considerations that might be part of other
chip-level or peripheral logic, apart from the features supported by the core, PLL controller (PLLC), and
power and sleep controller (PSC).
10.11.1 USB PHY Power Down Control
The USB modules can be clock gated using the PSC; however, this does not power down/clock gate the
PHY logic. You can put the USB2.0 PHY and OTG module in the lowest power state, when not in use, by
writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the Chip Configuration 2 Register
(CFGCHIP2) in the System Configuration (SYSCFG) Module chapter.
10.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode
The DDR2/mDDR memory controller supports different methods for reducing its power consumption
including self-refresh mode, power-down mode, and clock gating. Additionally, the DDR2/mDDR memory
controller DLL, PHY, and the receivers at the I/O pins can be disabled. Even if the PHY is active, the
receivers can be configured to disable whenever writes are in progress and the receivers are not needed.
Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR
memory controller is clock gated or when the device is placed in RTC-only mode. However, in the
RTC-only mode, care must be taken to correctly take the DDR2/mDDR out of self-refresh mode.
NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller
is clock gated, its self-refresh mode must be enabled before the DDR2/mDDR memory
controller clock is turned off.
In RTC-only mode, all portions of the device except for the RTC are powered down, including the
DDR2/mDDR memory controller. During power-up, the DDR2/mDDR memory controller defaults to its
reset state. When the DDR2/mDDR memory controller is taken out of reset, it automatically runs its
memory initialization routine; the self-refresh state of the memory is ignored. This hardware sequence
cannot be stopped by software running on the device.
To correctly take the memory out of self-refresh after coming back from RTC-only mode, follow these
steps:
1. Before going into RTC-only mode, disconnect the DDR2/mDDR memory controller CKE output pin
from the memory; ensure the memory’s CKE input pin continues to be driven low.
2. After coming back from RTC-only mode, configure the device to the desired operating state.
3. Program the DDR2/mDDR memory controller following the normal sequence.
4. Enable the self-refresh mode of the DDR2/mDDR memory controller.
5. Connect the DDR2/mDDR memory controller CKE output pin to the memory.
6. Disable the self-refresh mode of the DDR2/mDDR memory controller.
After this sequence, the DDR2/mDDR memory controller is ready for use. Note that hardware logic is
needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.
For more details on the power management features of the DDR2/mDDR memory controller, see the
DDR2/mDDR Memory Controller chapter.
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10.11.3 LVCMOS I/O Buffer Receiver Disable
This device supports two types of LVCMOS I/Os: 1.8V I/Os and low-static current dual-voltage I/Os that
operate at either 1.8V or 3.3V. The receivers on the LCVMOS I/Os are enabled and disabled by software
(see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module
chapter). In the event that certain receivers are not used (such as in a low-power state), they can be
disabled to conserve power.
10.11.4 Pull-Up/Pull-Down Disable
In general, you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level.
A floating input pin can consume a small amount of I/O leakage current. The I/O leakage current can be
greatly multiplied in the case of several floating inputs pins.
This device includes internal pull-up and pull-down resistors that prevent floating input pins. These internal
resistors are generally very weak and their use is intended for pins that are not connected on the board
design. For pins that are connected, external pull-up and pull-down resistors are recommended.
When an input pin is externally driven to a valid logic level, through an external pull-up resistor or by an
external device for example, it is recommended to disable the internal resistor. Opposing an internal
pull-up or pull-down resistor can consume a small amount of current. Internal resistors are disabled
through the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module
chapter.
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Chapter 11
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System Configuration (SYSCFG) Module
Topic
11.1
11.2
11.3
11.4
11.5
...........................................................................................................................
Introduction ....................................................................................................
Privilege Mode Protection .................................................................................
Master Priority Control .....................................................................................
ARM-DSP Communication Interrupts .................................................................
SYSCFG Registers ...........................................................................................
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208
208
209
210
211
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11.1 Introduction
The system configuration (SYSCFG) module is a system-level module containing status and top level
control logic required by the device. The system configuration module consists of a set of
memory-mapped status and control registers, accessible by the CPU, supporting all of the following
system features, and miscellaneous functions and operations.
• Device Identification
• Device Configuration
– Pin multiplexing control
– Device Boot Configuration Status
• Master Priority Control
– Controls the system priority for all master peripherals (including EDMA3TC)
• Emulation Control
– Emulation suspend control for peripherals that support the feature
• Special Peripheral Status and Control
– Locking of PLL control settings
– Default burst size configuration for EDMA3 transfer controllers
– Event source selection for the eCAP peripheral input capture
– McASP0 AMUTEIN selection and clearing of AMUTE
– USB PHY Control
– Clock source selection for EMIFA and DDR2/mDDR
• ARM-DSP Integration
– On-chip inter-processor interrupts and status for signaling between ARM and DSP
The system configuration module controls several global operations of the device; therefore, the module
supports protection against erroneous and illegal accesses to the registers in its memory-map. The
protection mechanisms that are present in the module are:
• A special key sequence that needs to be written into a set of registers in the system configuration
module, to allow write ability to the rest of registers in the system configuration module.
• Several registers in the module are only accessible when the CPU requesting read/write access is in
privileged mode.
11.2 Privilege Mode Protection
The CPU supports two privilege levels: Supervisor and User. Several registers in the SYSCFG
memory-map can only be accessed when the accessing host (CPU or master peripheral) is operating in
privileged mode, that is, in Supervisor mode. The registers that can only be accessed in privileged mode
are listed in Section 11.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide
(SPRUFE8) and the ARM926EJ-S Technical Reference Manual (TRM), downloadable from
http://infocenter.arm.com/help/index.jsp for details on privilege levels.
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11.3 Master Priority Control
The on-chip peripherals/modules are essentially divided into two broad categories, masters and slaves.
The master peripherals are typically capable of initiating their own read/write data access requests, this
includes the ARM, DSP, EDMA3 transfer controllers, and peripherals that do not rely on the CPU or
EDMA3 for initiating the data transfer to/from them. In order to determine allowed connection between
masters and slave, each master request source must have a unique master ID (mstid) associated with it.
The master ID is shown in Table 11-1. See the device-specific data manual to determine the masters
present on your device.
Each switched central resource (SCR) performs prioritization based on priority level of the master that
sends the read/write requests. For all peripherals/ports classified as masters on the device, the priority is
programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. The default priority
levels for each bus master is shown in Table 11-2. Application software is expected to modify these values
to obtain the desired performance.
Table 11-1. Master IDs
Master ID
ARM - Instruction
1
ARM - Data
2
DSP MDMA
3
DSP CFG
4-7
Reserved
8
PRU0
9
PRU1
10
EDMA3_0_CC0
11
EDMA3_1_CC0
12-15
Reserved
16
EDMA3_0_TC0 - read
17
EDMA3_0_TC0 - write
18
EDMA3_0_TC1 - read
19
EDMA3_0_TC1 - write
20
EDMA3_1_TC0 – read
21
EDMA3_1_TC0 – write
22-33
Reserved
34
USB2.0 CFG
35
USB2.0 DMA
36-37
38
Reserved
EMAC
39-255
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Table 11-2. Default Master Priority
Master
Default Priority
0
MSTPRI1
PRU1
0
MSTPRI1
EDMA3_0_TC0 (2)
0
MSTPRI1
(2)
0
MSTPRI1
ARM - Instruction
2
MSTPRI0
ARM - Data
2
MSTPRI0
DSP MDMA (3)
2
MSTPRI0
DSP CFG
(2)
(3)
Master Priority Register
PRU0
EDMA3_0_TC1
(1)
(1)
(3)
2
MSTPRI0
EDMA3_1_TC0 (2)
4
MSTPRI1
EMAC
4
MSTPRI2
USB2.0 CFG
4
MSTPRI2
USB2.0 DMA
4
MSTPRI2
The default priority settings might not be optimal for all applications. The master priority should be changed from default based
on application specific requirement, in order to get optimal performance and prioritization for masters moving data that is real
time sensitive.
The priority for EDMA3_0_TC0, EDMA3_0_TC1, and EDMA3_1_TC0 is configurable through fields in the master priority 1
register (MSTPRI1), not the EDMA3CC QUEPRI register.
The priority for DSP MDMA and DSP CFG is controlled by fields in the master priority 0 register (MSTPRI0) and not
DSP.MDMAARBE.PRI (DSP Bandwidth manager module).
11.4 ARM-DSP Communication Interrupts
The SYSCFG module also has a set of registers to facilitate interprocessor communication. This is
generally used to allow the ARM and the DSP to coordinate. For example, the ARM may interrupt the
DSP when it is ready to have the DSP process some data buffer in shared memory. A typical sequence,
often referred to as ARM-DSP communication, is as follows:
1. ARM writes command in shared memory.
2. ARM interrupts DSP.
3. DSP responds to interrupt and reads command in shared memory.
4. DSP executes a task based on the command.
5. DSP interrupts ARM upon completion of the task.
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other
processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller.
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11.5 SYSCFG Registers
Table 11-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and
Table 11-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1). These
tables also indicate whether a particular register can be accessed only when the CPU is in privileged
mode.
Table 11-3. System Configuration Module 0 (SYSCFG0) Registers
Address
Acronym
Register Description
Access
01C1 4000h
REVID
Revision Identification Register
—
Section 11.5.1
01C1 4008h
DIEIDR0 (1)
Die Identification Register 0
—
—
01C1 400Ch
DIEIDR1 (1)
Die Identification Register 1
—
—
01C1 4010h
DIEIDR2 (1)
Die Identification Register 2
—
—
01C1 4014h
DIEIDR3
(1)
Die Identification Register 3
—
01C1 4018h
DEVIDR0
Device Identification Register 0
Privileged mode
Section 11.5.2
01C1 4020h
BOOTCFG
Boot Configuration Register
Privileged mode
Section 11.5.3
01C1 4038h
KICK0R
Kick 0 Register
Privileged mode
Section 11.5.4.1
01C1 403Ch
KICK1R
Kick 1 Register
Privileged mode
Section 11.5.4.2
01C1 4040h
HOST0CFG
Host 0 Configuration Register
—
Section 11.5.5
01C1 4044h
HOST1CFG
Host 1 Configuration Register
—
Section 11.5.6
01C1 40E0h
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
Section 11.5.7.1
01C1 40E4h
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
Section 11.5.7.2
01C1 40E8h
IENSET
Interrupt Enable Register
Privileged mode
Section 11.5.7.3
01C1 40ECh
IENCLR
Interrupt Enable Clear Register
Privileged mode
Section 11.5.7.4
01C1 40F0h
EOI
End of Interrupt Register
Privileged mode
Section 11.5.7.5
01C1 40F4h
FLTADDRR
Fault Address Register
Privileged mode
Section 11.5.8.1
01C1 40F8h
FLTSTAT
Fault Status Register
—
Section 11.5.8.2
01C1 4110h
MSTPRI0
Master Priority 0 Register
Privileged mode
Section 11.5.9.1
01C1 4114h
MSTPRI1
Master Priority 1 Register
Privileged mode
Section 11.5.9.2
01C1 4118h
MSTPRI2
Master Priority 2 Register
Privileged mode
Section 11.5.9.3
01C1 4120h
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
Section 11.5.10.1
01C1 4124h
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
Section 11.5.10.2
01C1 4128h
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
Section 11.5.10.3
01C1 412Ch
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
Section 11.5.10.4
01C1 4130h
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
Section 11.5.10.5
01C1 4134h
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
Section 11.5.10.6
01C1 4138h
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
Section 11.5.10.7
01C1 413Ch
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
Section 11.5.10.8
01C1 4140h
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
Section 11.5.10.9
01C1 4144h
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
Section 11.5.10.10
01C1 4148h
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
Section 11.5.10.11
01C1 414Ch
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
Section 11.5.10.12
01C1 4150h
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
Section 11.5.10.13
01C1 4154h
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
Section 11.5.10.14
01C1 4158h
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
Section 11.5.10.15
01C1 415Ch
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
Section 11.5.10.16
01C1 4160h
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
Section 11.5.10.17
01C1 4164h
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
Section 11.5.10.18
01C1 4168h
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
Section 11.5.10.19
(1)
Section
—
This register is for internal-use only.
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Table 11-3. System Configuration Module 0 (SYSCFG0) Registers (continued)
Address
Acronym
Register Description
Access
01C1 416Ch
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
Section 11.5.10.20
Section
01C1 4170h
SUSPSRC
Suspend Source Register
Privileged mode
Section 11.5.11
01C1 4174h
CHIPSIG
Chip Signal Register
—
Section 11.5.12
01C1 4178h
CHIPSIG_CLR
Chip Signal Clear Register
—
Section 11.5.13
01C1 417Ch
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
Section 11.5.14
01C1 4180h
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
Section 11.5.15
01C1 4184h
CFGCHIP2
Chip Configuration 2 Register
Privileged mode
Section 11.5.16
01C1 4188h
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
Section 11.5.17
01C1 418Ch
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
Section 11.5.18
Table 11-4. System Configuration Module 1 (SYSCFG1) Registers
Address
Acronym
Register Description
Access
01E2 C000h
VTPIO_CTL
VTP I/O Control Register
Privileged mode
Section 11.5.19
Section
01E2 C004h
DDR_SLEW
DDR Slew Register
Privileged mode
Section 11.5.20
01E2 C008h
DEEPSLEEP
Deep Sleep Register
Privileged mode
Section 11.5.21
01E2 C00Ch
PUPD_ENA
Pullup/Pulldown Enable Register
Privileged mode
Section 11.5.22
01E2 C010h
PUPD_SEL
Pullup/Pulldown Selection Register
Privileged mode
Section 11.5.23
01E2 C014h
RXACTIVE
RXACTIVE Control Register
Privileged mode
Section 11.5.24
11.5.1 Revision Identification Register (REVID)
The revision identification register (REVID) provides the revision information for the SYSCFG module. The
REVID is shown in Figure 11-1 and described in Table 11-5.
Figure 11-1. Revision Identification Register (REVID)
31
0
REV
R-4E84 0102h
LEGEND: R = Read only; -n = value after reset
Table 11-5. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E84 0102h
212
Description
Revision ID. Revision information for the SYSCFG module.
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11.5.2 Device Identification Register 0 (DEVIDR0)
The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID
device. Software can use this register to determine the version of the device on which it is executing. The
DEVIDR0 is shown in Figure 11-2 and described in Table 11-6.
Figure 11-2. Device Identification Register 0 (DEVIDR0)
31
0
DEVID0
R-1B7D 102Fh
LEGEND: R = Read only; -n = value after reset
Table 11-6. Device Identification Register 0 (DEVIDR0) Field Descriptions
Bit
31-0
Field
DEVID0
Value
Description
1B7D 102Fh
Device identification.
11.5.3 Boot Configuration Register (BOOTCFG)
The device boot and configuration settings are latched at device reset, and captured in the boot
configuration register (BOOTCFG). See your device-specific data manual and the Boot Considerations
chapter for details on boot and configuration settings. The BOOTCFG is shown in Figure 11-3 and
described in Table 11-7.
Figure 11-3. Boot Configuration Register (BOOTCFG)
31
16
Reserved
R-0
15
0
BOOTMODE
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-7. Boot Configuration Register (BOOTCFG) Field Descriptions
Bit
Field
31-16
Reserved
15-0
BOOTMODE
Value
0
0-FFFFh
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Description
Reserved
Boot Mode. This reflects the state of the boot mode pins.
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11.5.4 Kick Registers (KICK0R-KICK1R)
NOTE: The kick registers are disabled in this device. The SYSCFG registers are always unlocked
and writes to the kick registers have no functional effect.
The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of
the modules memory-mapped registers. At power-on reset, none of the SYSCFG module registers are
writeable (they are readable). To allow writing to the registers in the module, it is required to “unlock” the
registers by writing to two memory-mapped registers in the SYSCFG module, Kick0 and Kick1, with exact
data values. Once these values are written, then all the registers in the SYSCFG module that are
writeable can be written to. See for the exact key values and sequence of steps. Writing any other data
value to either of these kick registers will cause the memory mapped registers to be “locked” again and
block out any write accesses to registers in the SYSCFG module.
11.5.4.1 Kick 0 Register (KICK0R)
The KICK0R is shown in Figure 11-4 and described in Table 11-8.
Figure 11-4. Kick 0 Register (KICK0R)
31
0
KICK1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-8. Kick 0 Register (KICK0R) Field Descriptions
Bit
Field
Value
31-0
KICK0
0-FFFF FFFFh
Description
KICK0R allows writing to unlock the kick0 data. The written data must be 83E7 0B13h to unlock
this register. It must be written before writing to the kick1 register. Writing any other value will lock
the other MMRs.
11.5.4.2 Kick 1 Register (KICK1R)
The KICK1R is shown in Figure 11-5 and described in Table 11-9.
Figure 11-5. Kick 1 Register (KICK1R)
31
0
KICK0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-9. Kick 1 Register (KICK1R) Field Descriptions
Bit
Field
Value
31-0
KICK1
0-FFFF FFFFh
214
Description
KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written
before writing to the kick1 register. Writing any other value will lock the other MMRs.
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11.5.5 Host 0 Configuration Register (HOST0CFG)
The ARM subsystem is held in reset when 0 is written to the BOOTRDY bit in the host 0 configuration
register (HOST0CFG). In a typical application, the BOOTRDY bit should not be cleared.
The HOST0CFG is shown in Figure 11-6 and described in Table 11-10.
NOTE: In addition to writing to HOST0CFG, the ARM subsystem must be enabled via the power
and sleep controller (PSC) module. By default, the ARM subsystem is in a SwRstDisable
state (see the Power and Sleep Controller (PSC) chapter for additional details).
Figure 11-6. Host 0 Configuration Register (HOST0CFG)
31
16
Reserved
R-0
15
1
0
Reserved
BOOTRDY
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-10. Host 0 Configuration Register (HOST0CFG) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
BOOTRDY
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Description
Reserved
ARM boot ready bit allowing ARM to boot.
0
ARM held in reset mode.
1
ARM released from wait in reset mode.
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11.5.6 Host 1 Configuration Register (HOST1CFG)
The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at
power-on reset. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The address field is
read/writeable after reset and can be modified to allow execution from an alternate location after a module
level or local reset on the DSP. The HOST1CFG is shown in Figure 11-7 and described in Table 11-11.
Figure 11-7. Host 1 Configuration Register (HOST1CFG)
31
16
DSP_ISTP_RST_VAL
R/W-0070h
15
10
9
0
DSP_ISTP_RST_VAL
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions
Bit
Field
31-10 DSP_ISTP_RST_VAL
9-0
216
Reserved
Value
Description
0-3F FFFFh
0
DSP boot address vector.
Reserved
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11.5.7 Interrupt Registers
The interrupt registers are a set of registers that provide control for the address and protection violation
error interrupt generated by the SYSCFG module when there is an address or protection violation to the
module's memory-mapped register address space. This includes enable control, interrupt set and clear
control, and end of interrupt (EOI) control.
11.5.7.1 Interrupt Raw Status/Set Register (IRAWSTAT)
The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt
and allows setting of the interrupt status. The IRAWSTAT is shown in Figure 11-8 and described in
Table 11-12.
Figure 11-8. Interrupt Raw Status/Set Register (IRAWSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the raw status of the interrupt before
enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
PROTERR
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 sets the status.
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11.5.7.2 Interrupt Enable Status/Clear Register (IENSTAT)
The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows
clearing of the interrupt status. The IENSTAT is shown in Figure 11-9 and described in Table 11-13.
Figure 11-9. Interrupt Enable Status/Clear Register (IENSTAT)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR
PROTERR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit
31-2
1
0
218
Field
Reserved
Value
0
ADDRERR
Description
Reserved. Always read 0.
Addressing violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
PROTERR
Protection violation error. Reading this bit field reflects the interrupt enabled status.
0
Indicates the interrupt is not set. Writing 0 has no effect.
1
Indicates the interrupt is set. Writing 1 clears the status.
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11.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 11-10 and described in Table 11-14.
Figure 11-10. Interrupt Enable Register (IENSET)
31
16
Reserved
R-0
15
1
0
Reserved
2
ADDRERR_EN
PROTERR_EN
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_EN
Description
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
PROTERR_EN
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 enables this interrupt.
11.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 11-11 and described in Table 11-15.
Figure 11-11. Interrupt Enable Clear Register (IENCLR)
31
16
Reserved
R-0
15
2
Reserved
1
0
ADDRERR_CLR PROTERR_CLR
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit
31-2
1
0
Field
Value
Reserved
0
ADDRERR_CLR
Reserved. Always read 0.
Addressing violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
PROTERR_CLR
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Description
Protection violation error.
0
Writing a 0 has not effect.
1
Writing a 1 clears/disables this interrupt.
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11.5.7.5 End of Interrupt Register (EOI)
The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of
the SYSCFG interrupt (for address/protection violation). You should write a value of 0 to the EOI register
bit 0 after the software has processed the SYSCFG interrupt, this acts as an acknowledgement of
completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts.
The EOI is shown in Figure 11-12 and described in Table 11-16.
Figure 11-12. End of Interrupt Register (EOI)
31
16
Reserved
R-0
15
8
7
0
Reserved
EOIVECT
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-16. End of Interrupt Register (EOI) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7-0
EOIVECT
0-FFh
Description
Reserved. Always read 0.
EOI vector value. Write the interrupt distribution value of the chip.
11.5.8 Fault Registers
The fault registers are a group of registers responsible for capturing the details on the faulty
(address/protection violation errors) accesses, such as address and type of error.
11.5.8.1 Fault Address Register (FLTADDRR)
The fault address register (FLTADDRR) captures the address of the first transfer that causes the address
or memory violation error. The FLTADDRR is shown in Figure 11-13 and described in Table 11-17.
Figure 11-13. Fault Address Register (FLTADDRR)
31
0
FLTADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-17. Fault Address Register (FLTADDRR) Field Descriptions
Bit
31-0
220
Field
FLTADDR
Value
0-FFFF FFFFh
Description
Fault address for the first fault transfer.
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11.5.8.2 Fault Status Register (FLTSTAT)
The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous
transaction. This includes things like the master id for the master that caused the address/memory
violation error, details on whether it is a user or supervisor level read/write or execute fault. The FLTSTAT
is shown in Figure 11-14 and described in Table 11-18.
Figure 11-14. Fault Status Register (FLTSTAT)
31
24
15
13
23
16
ID
MSTID
R-0
R-0
12
9
8
6
5
0
Reserved
PRIVID
Reserved
TYPE
R-0
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-18. Fault Status Register (FLTSTAT) Field Descriptions
Field
Value
Description
31-24
Bit
ID
0-FFh
Transfer ID of the first fault transfer.
23-16
MSTID
0-FFh
Master ID of the first fault transfer.
15-13
Reserved
12-9
PRIVID
8-6
Reserved
5-0
TYPE
0
0-Fh
0
Reserved. Always read 0
Privilege ID of the first fault transfer.
Reserved. Always read 0
Fault type of first fault transfer.
0
No transfer fault
1h
User execute fault
2h
User write fault
3h
Reserved
4h
User read fault
5h-7h
8h
9h-Fh
10h
11h-1Fh
20h
21h-3Fh
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Reserved
Supervisor execute fault
Reserved
Supervisor write fault
Reserved
Supervisor read fault
Reserved
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11.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
11.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 11-15 and described in Table 11-19.
Figure 11-15. Master Priority 0 Register (MSTPRI0)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
DSP_CFG
Rsvd
DSP_MDMA
Rsvd
ARM_D
Rsvd
ARM_I
R/W-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
4h
Reserved. Write the default value when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
DSP_CFG
0-7h
11
Reserved
0
10-8
7
6-4
3
2-0
222
DSP_MDMA
Reserved
ARM_D
Reserved
ARM_I
0-7h
0
0-7h
0
0-7h
DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_D port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
ARM_I port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.9.2 Master Priority 1 Register (MSTPRI1)
The master priority 1 register (MSTPRI1) is shown in Figure 11-16 and described in Table 11-20.
Figure 11-16. Master Priority 1 Register (MSTPRI1)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
EDMA31TC0
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-4h
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
EDMA30TC1
Rsvd
EDMA30TC0
Rsvd
PRU1
Rsvd
PRU0
R/W-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-20. Master Priority 1 Register (MSTPRI1) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
4h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
4h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
15
14-12
11
10-8
7
6-4
3
2-0
EDMA31TC0
Reserved
EDMA30TC1
Reserved
EDMA30TC0
Reserved
PRU1
Reserved
PRU0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
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EDMA3_1_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
EDMA3_0_TC0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU1 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Always read as 0.
PRU0 port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.9.3 Master Priority 2 Register (MSTPRI2)
The master priority 2 register (MSTPRI2) is shown in Figure 11-17 and described in Table 11-21.
Figure 11-17. Master Priority 2 Register (MSTPRI2)
31
30
28
27
26
24
23
22
20
19
18
16
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
Rsvd
Reserved
R/W-0
R/W-5h
R/W-0
R/W-4h
R/W-0
R/W-6h
R/W-0
R/W-0
15
14
12
11
10
8
7
6
4
3
2
0
Rsvd
USB0CDMA
Rsvd
USB0CFG
Rsvd
Reserved
Rsvd
EMAC
R/W-0
R/W-4h
R/W-0
R/W-4h
R/W-0
R/W-0
R/W-0
R/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-21. Master Priority 2 Register (MSTPRI2) Field Descriptions
Bit
Field
31
Reserved
Value
0
Description
Reserved. Write the default value when modifying this register.
30-28
Reserved
5h
Reserved. Write the default value when modifying this register.
27
Reserved
0
Reserved. Write the default value when modifying this register.
26-24
Reserved
4h
Reserved. Write the default value when modifying this register.
23
Reserved
0
Reserved. Write the default value when modifying this register.
22-20
Reserved
6h
Reserved. Write the default value when modifying this register.
19
Reserved
0
Reserved. Write the default value when modifying this register.
18-16
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
15
Reserved
0
Reserved. Write the default value when modifying this register.
14-12
USB0CDMA
0-7h
11
Reserved
0
10-8
USB0CFG
0-7h
USB0 (USB2.0) CDMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
Reserved. Write the default value when modifying this register.
USB0 (USB2.0) CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
6-4
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
3
Reserved
0
Reserved. Write the default value when modifying this register.
2-0
224
EMAC
0-7h
EMAC port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
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11.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the
smallest possible package. On the device, pin multiplexing can be controlled on a pin by pin basis. This is
done by the pin multiplexing registers (PINMUX0-PINMUX19). Each pin that is multiplexed with several
different functions has a corresponding 4-bit field in PINMUXn. Pin multiplexing selects which of several
peripheral pin functions control the pins I/O buffer output data and output enable values only. Note that the
input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers
have no effect on input from a pin. Hardware does not attempt to ensure that the proper pin multiplexing is
selected for the peripherals or that interface mode is being used. Detailed information about the pin
multiplexing and control is covered in the device-specific data manual. Access to the pin multiplexing utility
is available in OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility Application Report
(SPRAB63).
11.5.10.1 Pin Multiplexing Control 0 Register (PINMUX0)
Figure 11-18. Pin Multiplexing Control 0 Register (PINMUX0)
31
28
27
24
23
20
19
16
PINMUX0_31_28
PINMUX0_27_24
PINMUX0_23_20
PINMUX0_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX0_15_12
PINMUX0_11_8
PINMUX0_7_4
PINMUX0_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
Bit
31-28
Field
Value
PINMUX0_31_28
(1)
RTC_ALARM/UART2_CTS/GP0[8]/DEEPSLEEP Control
Selects Function DEEPSLEEP
1h
Reserved
X
2h
Selects Function RTC_ALARM
O
3h
Reserved
X
4h
Selects Function UART2_CTS
I
8h
9h-Fh
PINMUX0_27_24
I
Reserved
X
Selects Function GP0[8]
I/O
Reserved
X
AMUTE/PRU0_R30[16]/UART2_RTS/GP0[9]/PRU0_R31[16] Control
0
Selects Function PRU0_R31[16]
1h
Selects Function AMUTE
I/O
2h
Selects Function PRU0_R30[16]
O
3h
Reserved
X
4h
Selects Function UART2_RTS
O
Reserved
X
5h-7h
8h
9h-Fh
(1)
Type
0
5h-7h
27-24
Description
I
Selects Function GP0[9]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued)
Bit
Field
23-20
Value
PINMUX0_23_20
0
Selects Function PRU0_R31[17]
1h
Selects Function AHCLKX
2h
Selects Function USB_REFCLKIN
I
3h
Reserved
X
4h
Selects Function UART1_CTS
I
Reserved
X
8h
9h-Fh
PINMUX0_19_16
Reserved
X
Selects Function AHCLKR
I/O
2h
Selects Function PRU0_R30[18]
O
3h
Reserved
X
4h
Selects Function UART1_RTS
O
PINMUX0_15_12
Reserved
Selects Function GP0[11]
Reserved
I
X
I/O
X
AFSX/GP0[12]/PRU0_R31[19] Control
0
Selects Function PRU0_R31[19]
1h
Selects Function AFSX
8h
9h-Fh
PINMUX0_11_8
Reserved
Selects Function GP0[12]
Reserved
I
I/O
X
I/O
X
AFSR/GP0[13]/PRU0_R31[20] Control
0
Selects Function PRU0_R31[20]
1h
Selects Function AFSR
2h-7h
8h
9h-Fh
PINMUX0_7_4
Reserved
Selects Function GP0[13]
Reserved
I
I/O
X
I/O
X
ACLKX/PRU0_R30[19]/GP0[14]/PRU0_R31[21] Control
0
Selects Function PRU0_R31[21]
1h
Selects Function ACLKX
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX0_3_0
I
I/O
Reserved
X
Selects Function PRU0_R30[19]
O
Reserved
Selects Function GP0[14]
Reserved
X
I/O
X
ACLKR/PRU0_R30[20]/GP0[15]/PRU0_R31[22] Control
0
Selects Function PRU0_R31[22]
1h
Selects Function ACLKR
2h-3h
4h
5h-7h
8h
9h-Fh
226
I/O
1h
2h-7h
3-0
Selects Function GP0[10]
Selects Function PRU0_R31[18]
9h-Fh
7-4
I
I/O
0
8h
11-8
(1)
AHCLKR/PRU0_R30[18]/UART1_RTS/GP0[11]/PRU0_R31[18] Control
5h-7h
15-12
Type
AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]/PRU0_R31[17] Control
5h-7h
19-16
Description
I
I/O
Reserved
X
Selects Function PRU0_R30[20]
O
Reserved
Selects Function GP0[15]
Reserved
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X
I/O
X
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11.5.10.2 Pin Multiplexing Control 1 Register (PINMUX1)
Figure 11-19. Pin Multiplexing Control 1 Register (PINMUX1)
31
28
27
24
23
20
19
16
PINMUX1_31_28
PINMUX1_27_24
PINMUX1_23_20
PINMUX1_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX1_15_12
PINMUX1_11_8
PINMUX1_7_4
PINMUX1_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
Bit
31-28
Field
Value
PINMUX1_31_28
Selects Function PRU0_R31[8]
1h
Selects Function AXR8
2h
Selects Function CLKS1
I
3h
Reserved
X
4h
Selects Function ECAP1_APWM1
8h
PINMUX1_27_24
I/O
Reserved
X
Selects Function GP0[0]
I/O
Reserved
X
0
Pin is 3-stated.
1h
Selects Function AXR9
I/O
2h
Selects Function DX1
O
8h
9h-Fh
PINMUX1_23_20
Z
Reserved
X
Selects Function GP0[1]
I/O
Reserved
X
AXR10/DR1/GP0[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR10
2h
Selects Function DR1
3h-7h
8h
9h-Fh
PINMUX1_19_16
Z
I/O
I
Reserved
X
Selects Function GP0[2]
I/O
Reserved
X
AXR11/FSX1/GP0[3] Control
0
Pin is 3-stated.
1h
Selects Function AXR11
I/O
2h
Selects Function FSX1
I/O
3h-7h
8h
9h-Fh
(1)
I
I/O
AXR9/DX1/GP0[1] Control
3h-7h
19-16
(1)
AXR8/CLKS1/ECAP1_APWM1/GP0[0]/PRU0_R31[8] Control
9h-Fh
23-20
Type
0
5h-7h
27-24
Description
Z
Reserved
X
Selects Function GP0[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX1_15_12
0
Pin is 3-stated.
1h
Selects Function AXR12
I/O
2h
Selects Function FSR1
I/O
8h
9h-Fh
PINMUX1_11_8
Selects Function GP0[4]
Reserved
X
I/O
X
0
Pin is 3-stated.
Selects Function AXR13
I/O
2h
Selects Function CLKX1
I/O
9h-Fh
PINMUX1_7_4
Reserved
Selects Function GP0[5]
Reserved
Z
X
I/O
X
AXR14/CLKR1/GP0[6] Control
0
Pin is 3-stated.
1h
Selects Function AXR14
I/O
2h
Selects Function CLKR1
I/O
3h-7h
8h
9h-Fh
PINMUX1_3_0
Reserved
Selects Function GP0[6]
Reserved
Z
X
I/O
X
AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] Control
0
Pin is 3-stated.
1h
Selects Function AXR15
2h
Selects Function EPWM0TZ[0]
3h
Reserved
4h
Selects Function ECAP2_APWM2
5h-7h
8h
9h-Fh
228
Reserved
Z
1h
8h
3-0
(1)
AXR13/CLKX1/GP0[5] Control
3h-7h
7-4
Type
AXR12/FSR1/GP0[4] Control
3h-7h
11-8
Description
Reserved
Selects Function GP0[7]
Reserved
System Configuration (SYSCFG) Module
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Z
I/O
I
X
I/O
X
I/O
X
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11.5.10.3 Pin Multiplexing Control 2 Register (PINMUX2)
Figure 11-20. Pin Multiplexing Control 2 Register (PINMUX2)
31
28
27
24
23
20
19
16
PINMUX2_31_28
PINMUX2_27_24
PINMUX2_23_20
PINMUX2_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX2_15_12
PINMUX2_11_8
PINMUX2_7_4
PINMUX2_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
Bit
31-28
Field
Value
PINMUX2_31_28
Selects Function CLKS0
I
1h
Selects Function AXR0
I/O
2h
Selects Function ECAP0_APWM0
I/O
3h
Reserved
4h
Selects Function GP8[7]
9h-Fh
PINMUX2_27_24
X
I/O
Reserved
X
Selects Function MII_TXD[0]
O
Reserved
X
AXR1/DX0/GP1[9]/MII_TXD[1] Control
0
Pin is 3-stated.
1h
Selects Function AXR1
I/O
2h
Selects Function DX0
O
3h
Reserved
4h
Selects Function GP1[9]
5h-7h
8h
9h-Fh
PINMUX2_23_20
Z
X
I/O
Reserved
X
Selects Function MII_TXD[1]
O
Reserved
X
AXR2/DR0/GP1[10]/MII_TXD[2] Control
0
Pin is 3-stated.
1h
Selects Function AXR2
2h
Selects Function DR0
3h
Reserved
4h
Selects Function GP1[10]
5h-7h
8h
9h-Fh
(1)
(1)
AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0 Control
8h
23-20
Type
0
5h-7h
27-24
Description
Z
I/O
I
X
I/O
Reserved
X
Selects Function MII_TXD[2]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX2_19_16
0
Pin is 3-stated.
1h
Selects Function AXR3
I/O
2h
Selects Function FSX0
I/O
3h
Reserved
4h
Selects Function GP1[11]
8h
9h-Fh
PINMUX2_15_12
I/O
Reserved
X
Selects Function MII_TXD[3]
O
Reserved
X
1h
Selects Function AXR4
I/O
2h
Selects Function FSR0
I/O
3h
Reserved
4h
Selects Function GP1[12]
PINMUX2_11_8
Z
X
I/O
Reserved
X
Selects Function MII_COL
I
Reserved
X
AXR5/CLKX0/GP1[13]/MII_TXCLK Control
0
Pin is 3-stated.
1h
Selects Function AXR5
I/O
2h
Selects Function CLKX0
I/O
3h
Reserved
4h
Selects Function GP1[13]
5h-7h
8h
9h-Fh
PINMUX2_7_4
Z
X
I/O
Reserved
X
Selects Function MII_TXCLK
I
Reserved
X
AXR6/CLKR0/GP1[14]/MII_TXEN/PRU0_R31[6] Control
0
Selects Function PRU0_R31[6]
1h
Selects Function AXR6
I/O
2h
Selects Function CLKR0
I/O
3h
Reserved
4h
Selects Function GP1[14]
5h-7h
8h
9h-Fh
PINMUX2_3_0
I
X
I/O
Reserved
X
Selects Function MII_TXEN
O
Reserved
X
AXR7/EPWM1TZ[0]/PRU0_R30[17]/GP1[15]/PRU0_R31[7] Control
0
Selects Function PRU0_R31[7]
1h
Selects Function AXR7
2h
Selects Function EPWM1TZ[0]
I
3h
Reserved
X
4h
Selects Function PRU0_R30[17]
O
5h-7h
8h
9h-Fh
230
X
Pin is 3-stated.
9h-Fh
3-0
Z
0
8h
7-4
(1)
AXR4/FSR0/GP1[12]/MII_COL Control
5h-7h
11-8
Type
AXR3/FSX0/GP1[11]/MII_TXD[3] Control
5h-7h
15-12
Description
Reserved
Selects Function GP1[15]
Reserved
System Configuration (SYSCFG) Module
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I
I/O
X
I/O
X
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11.5.10.4 Pin Multiplexing Control 3 Register (PINMUX3)
Figure 11-21. Pin Multiplexing Control 3 Register (PINMUX3)
31
28
27
24
23
20
19
16
PINMUX3_31_28
PINMUX3_27_24
PINMUX3_23_20
PINMUX3_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX3_15_12
PINMUX3_11_8
PINMUX3_7_4
PINMUX3_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
Bit
31-28
Field
Value
PINMUX3_31_28
Pin is 3-stated.
1h
Selects Function SPI0_SCS[2]
I/O
2h
Selects Function UART0_RTS
O
3h
Reserved
4h
Selects Function GP8[1]
8h
PINMUX3_27_24
Z
X
I/O
Reserved
X
Selects Function MII_RXD[0]
I
Reserved
X
SPI0_SCS[3]/UART0_CTS/GP8[2]/MII_RXD[1] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[3]
I/O
2h
Selects Function UART0_CTS
I
3h
Reserved
4h
Selects Function GP8[2]
5h-7h
8h
9h-Fh
PINMUX3_23_20
Z
X
I/O
Reserved
X
Selects Function MII_RXD[1]
I
Reserved
X
SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[4]
I/O
2h
Selects Function UART0_TXD
O
3h
Reserved
X
4h
Selects Function GP8[3]
5h-7h
8h
9h-Fh
(1)
(1)
SPI0_SCS[2]/UART0_RTS/GP8[1]/MII_RXD[0] Control
9h-Fh
23-20
Type
0
5h-7h
27-24
Description
Z
I/O
Reserved
X
Selects Function MII_RXD[2]
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX3_19_16
0
Pin is 3-stated.
1h
Selects Function SPI0_SCS[5]
2h
Selects Function UART0_RXD
I
3h
Reserved
X
4h
Selects Function GP8[4]
8h
9h-Fh
PINMUX3_15_12
X
Selects Function MII_RXD[3]
I
Reserved
X
1h
Selects Function SPI0_SIMO
I/O
2h
Selects Function EPWMSYNCO
O
3h
Reserved
4h
Selects Function GP8[5]
PINMUX3_11_8
Reserved
Z
X
I/O
X
Selects Function MII_CRS
I
Reserved
X
SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER Control
0
Pin is 3-stated.
1h
Selects Function SPI0_SOMI
2h
Selects Function EPWMSYNCI
I
3h
Reserved
X
4h
Selects Function GP8[6]
5h-7h
8h
9h-Fh
PINMUX3_7_4
Reserved
Z
I/O
I/O
X
Selects Function MII_RXER
I
Reserved
X
SPI0_ENA/EPWM0B/PRU0_R30[6]/MII_RXDV Control
0
Pin is 3-stated.
1h
Selects Function SPI0_ENA
I/O
2h
Selects Function EPWM0B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[6]
O
Reserved
X
Selects Function MII_RXDV
I
Reserved
X
5h-7h
8h
9h-Fh
PINMUX3_3_0
Z
SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK Control
0
Pin is 3-stated.
1h
Selects Function SPI0_CLK
I/O
2h
Selects Function EPWM0A
I/O
3h
Reserved
4h
Selects Function GP1[8]
5h-7h
8h
9h-Fh
232
I/O
Reserved
Pin is 3-stated.
9h-Fh
3-0
Z
I/O
0
8h
7-4
(1)
SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS Control
5h-7h
11-8
Type
SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] Control
5h-7h
15-12
Description
Reserved
Z
X
I/O
X
Selects Function MII_RXCLK
I
Reserved
X
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11.5.10.5 Pin Multiplexing Control 4 Register (PINMUX4)
Figure 11-22. Pin Multiplexing Control 4 Register (PINMUX4)
31
28
27
24
23
20
19
16
PINMUX4_31_28
PINMUX4_27_24
PINMUX4_23_20
PINMUX4_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX4_15_12
PINMUX4_11_8
PINMUX4_7_4
PINMUX4_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
Bit
31-28
Field
Value
PINMUX4_31_28
Pin is 3-stated.
1h
Selects Function SP1_SCS[2]
I/O
2h
Selects Function UART1_TXD
O
9h-Fh
PINMUX4_27_24
Reserved
X
Selects Function GP1[0]
I/O
Reserved
X
SPI1_SCS[3]/UART1_RXD/GP1[1] Control
Pin is 3-stated.
1h
Selects Function SPI1_SCS[3]
2h
Selects Function UART1_RXD
I
Reserved
X
8h
9h-Fh
PINMUX4_23_20
Z
I/O
Selects Function GP1[1]
I/O
Reserved
X
SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[4]
I/O
2h
Selects Function UART2_TXD
O
3h
Reserved
4h
Selects Function I2C1_SDA
5h-7h
8h
9h-Fh
PINMUX4_19_16
Z
X
I/O
Reserved
X
Selects Function GP1[2]
I/O
Reserved
X
SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[5]
I/O
2h
Selects Function UART2_RXD
I
3h
Reserved
4h
Selects Function I2C1_SCL
5h-7h
8h
9h-Fh
(1)
Z
0
3h-7h
19-16
(1)
SP1_SCS[2]/UART1_TXD/GP1[0] Control
8h
23-20
Type
0
3h-7h
27-24
Description
Z
X
I/O
Reserved
X
Selects Function GP1[3]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX4_15_12
0
Pin is 3-stated.
1h
Selects Function SPI1_SCS[6]
I/O
2h
Selects Function I2C0_SDA
I/O
3h
Reserved
X
4h
Selects Function TM64P3_OUT12
O
8h
9h-Fh
PINMUX4_11_8
Reserved
X
Selects Function GP1[4]
I/O
Reserved
X
Pin is 3-stated.
1h
Selects Function SPI1_SCS[7]
I/O
2h
Selects Function I2C0_SCL
I/O
3h
Reserved
X
4h
Selects Function TM64P2_OUT12
O
9h-Fh
PINMUX4_7_4
Z
Reserved
X
Selects Function GP1[5]
I/O
Reserved
X
SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 Control
0
Selects Function TM64P1_IN12
I
1h
Selects Function SPI0_SCS[0]
I/O
2h
Selects Function TM64P1_OUT12
O
3h
Reserved
4h
Selects Function GP1[6]
5h-7h
8h
9h-Fh
PINMUX4_3_0
X
I/O
Reserved
X
Selects Function MDIO_D
I/O
Reserved
X
SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control
0
Selects Function TM64P0_IN12
I
1h
Selects Function SPI0_SCS[1]
I/O
2h
Selects Function TM64P0_OUT12
O
3h
Reserved
4h
Selects Function GP1[7]
5h-7h
8h
9h-Fh
234
Z
0
8h
3-0
(1)
SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] Control
5h-7h
7-4
Type
SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] Control
5h-7h
11-8
Description
X
I/O
Reserved
X
Selects Function MDIO_CLK
O
Reserved
X
System Configuration (SYSCFG) Module
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11.5.10.6 Pin Multiplexing Control 5 Register (PINMUX5)
Figure 11-23. Pin Multiplexing Control 5 Register (PINMUX5)
31
28
27
24
23
20
19
16
PINMUX5_31_28
PINMUX5_27_24
PINMUX5_23_20
PINMUX5_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX5_15_12
PINMUX5_11_8
PINMUX5_7_4
PINMUX5_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
Bit
31-28
Field
Value
PINMUX5_31_28
Pin is 3-stated.
Z
1h
Selects Function EMA_BA[0]
O
9h-Fh
PINMUX5_27_24
I/O
Reserved
X
0
Pin is 3-stated.
Z
Selects Function EMA_BA[1]
O
Reserved
X
8h
PINMUX5_23_20
Selects Function GP2[9]
I/O
Reserved
X
SPI1_SIMO/GP2[10] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SIMO
2h-7h
8h
9h-Fh
PINMUX5_19_16
Z
I/O
Reserved
X
Selects Function GP2[10]
I/O
Reserved
X
SPI1_SOMI/GP2[11] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_SOMI
2h-7h
8h
9h-Fh
PINMUX5_15_12
Z
I/O
Reserved
X
Selects Function GP2[11]
I/O
Reserved
X
SPI1_ENA/GP2[12] Control
0
Pin is 3-stated.
1h
Selects Function SPI1_ENA
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP2[8]
1h
9h-Fh
15-12
Reserved
EMA_BA[1]/GP2[9] Control
2h-7h
19-16
(1)
EMA_BA[0]/GP2[8] Control
8h
23-20
Type
0
2h-7h
27-24
Description
Z
I/O
Reserved
X
Selects Function GP2[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX5_11_8
0
Pin is 3-stated.
1h
Selects Function SPI1_CLK
8h
9h-Fh
PINMUX5_7_4
Z
I/O
Reserved
X
Selects Function GP2[13]
I/O
Reserved
X
0
Selects Function TM64P3_IN12
I
1h
Selects Function SPI1_SCS[0]
I/O
2h
Selects Function EPWM1B
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[7]
O
8h
9h-Fh
PINMUX5_3_0
Reserved
X
Selects Function GP2[14]
I/O
Reserved
X
SPI1_SCS[1]/EPWM1A/PRU0_R30[8]/GP2[15]/TM64P2_IN12 Control
0
Selects Function TM64P2_IN12
I
1h
Selects Function SPI1_SCS[1]
I/O
2h
Selects Function EPWM1A
I/O
3h
Reserved
X
4h
Selects Function PRU0_R30[8]
O
5h-7h
8h
9h-Fh
236
(1)
SPI1_SCS[0]/EPWM1B/PRU0_R30[7]/GP2[14]/TM64P3_IN12 Control
5h-7h
3-0
Type
SPI1_CLK/GP2[13] Control
2h-7h
7-4
Description
Reserved
Selects Function GP2[15]
Reserved
System Configuration (SYSCFG) Module
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X
I/O
X
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11.5.10.7 Pin Multiplexing Control 6 Register (PINMUX6)
Figure 11-24. Pin Multiplexing Control 6 Register (PINMUX6)
31
28
27
24
23
20
19
16
PINMUX6_31_28
PINMUX6_27_24
PINMUX6_23_20
PINMUX6_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX6_15_12
PINMUX6_11_8
PINMUX6_7_4
PINMUX6_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
Bit
31-28
Field
Value
PINMUX6_31_28
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[0]
O
9h-Fh
PINMUX6_27_24
I/O
Reserved
X
0
Selects Function PRU0_R31[1]
Selects Function EMA_WAIT[1]
I
Reserved
X
Selects Function PRU0_R30[1]
O
4h
8h
9h-Fh
PINMUX6_23_20
I
Reserved
X
Selects Function GP2[1]
I/O
Reserved
X
EMA_WE_DQM[1]/GP2[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[1]
O
2h-7h
8h
9h-Fh
PINMUX6_19_16
Reserved
X
Selects Function GP2[2]
I/O
Reserved
X
EMA_WE_DQM[0]/GP2[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE_DQM[0]
O
2h-7h
8h
9h-Fh
PINMUX6_15_12
Reserved
X
Selects Function GP2[3]
I/O
Reserved
X
EMA_CAS/PRU0_R30[2]/GP2[4]/PRU0_R31[2] Control
0
Selects Function PRU0_R31[2]
I
1h
Selects Function EMA_CAS
O
Reserved
X
Selects Function PRU0_R30[2]
O
2h-3h
4h
5h-7h
8h
9h-Fh
(1)
X
Selects Function GP2[0]
1h
5h-7h
15-12
Reserved
EMA_WAIT[1]/PRU0_R30[1]/GP2[1]/PRU0_R31[1] Control
2h-3h
19-16
(1)
EMA_CS[0]/GP2[0] Control
8h
23-20
Type
0
2h-7h
27-24
Description
Reserved
X
Selects Function GP2[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX6_11_8
0
Selects Function PRU0_R31[3]
I
1h
Selects Function EMA_RAS
O
4h
5h-7h
8h
9h-Fh
PINMUX6_7_4
(1)
X
Selects Function PRU0_R30[3]
O
Reserved
Selects Function GP2[5]
Reserved
X
I/O
X
EMA_SDCKE/PRU0_R30[4]/GP2[6]/PRU0_R31[4] Control
Selects Function PRU0_R31[4]
I
1h
Selects Function EMA_SDCKE
O
4h
5h-7h
8h
9h-Fh
PINMUX6_3_0
Reserved
X
Selects Function PRU0_R30[4]
O
Reserved
Selects Function GP2[6]
Reserved
X
I/O
X
EMA_CLK/PRU0_R30[5]/GP2[7]/PRU0_R31[5] Control
0
Selects Function PRU0_R31[5]
I
1h
Selects Function EMA_CLK
O
2h-3h
4h
5h-7h
8h
9h-Fh
238
Reserved
0
2h-3h
3-0
Type
EMA_RAS/PRU0_R30[3]/GP2[5]/PRU0_R31[3] Control
2h-3h
7-4
Description
Reserved
X
Selects Function PRU0_R30[5]
O
Reserved
Selects Function GP2[7]
Reserved
System Configuration (SYSCFG) Module
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X
I/O
X
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11.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 11-25. Pin Multiplexing Control 7 Register (PINMUX7)
31
28
27
24
23
20
19
16
PINMUX7_31_28
PINMUX7_27_24
PINMUX7_23_20
PINMUX7_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX7_15_12
PINMUX7_11_8
PINMUX7_7_4
PINMUX7_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit
31-28
Field
Value
PINMUX7_31_28
Selects Function PRU0_R31[0]
I
1h
Selects Function EMA_WAIT[0]
I
5h-7h
8h
9h-Fh
PINMUX7_27_24
O
Reserved
X
Selects Function GP3[8]
I/O
Reserved
X
Pin is 3-stated.
Z
1h
Selects Function EMA_A_RW
O
9h-Fh
PINMUX7_23_20
Reserved
X
Selects Function GP3[9]
I/O
Reserved
X
EMA_OE/GP3[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_OE
O
2h-7h
8h
9h-Fh
PINMUX7_19_16
Reserved
X
Selects Function GP3[10]
I/O
Reserved
X
EMA_WE/GP3[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_WE
O
2h-7h
8h
9h-Fh
PINMUX7_15_12
Reserved
X
Selects Function GP3[11]
I/O
Reserved
X
EMA_CS[5]/GP3[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[5]
O
Reserved
X
2h-7h
8h
9h-Fh
(1)
X
Selects Function PRU0_R30[0]
0
8h
15-12
Reserved
EMA_A_RW/GP3[9] Control
2h-7h
19-16
(1)
EMA_WAIT[0]/PRU0_R30[0]/GP3[8]/PRU0_R31[0] Control
4h
23-20
Type
0
2h-3h
27-24
Description
Selects Function GP3[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX7_11_8
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[4]
O
8h
9h-Fh
PINMUX7_7_4
Reserved
Selects Function GP3[13]
Reserved
X
I/O
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[3]
O
8h
9h-Fh
PINMUX7_3_0
Reserved
Selects Function GP3[14]
Reserved
X
I/O
X
EMA_CS[2]/GP3[15] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_CS[2]
O
2h-7h
8h
9h-Fh
240
(1)
EMA_CS[3]/GP3[14] Control
2h-7h
3-0
Type
EMA_CS[4]/GP3[13] Control
2h-7h
7-4
Description
Reserved
Selects Function GP3[15]
Reserved
System Configuration (SYSCFG) Module
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X
I/O
X
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11.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 11-26. Pin Multiplexing Control 8 Register (PINMUX8)
31
28
27
24
23
20
19
16
PINMUX8_31_28
PINMUX8_27_24
PINMUX8_23_20
PINMUX8_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX8_15_12
PINMUX8_11_8
PINMUX8_7_4
PINMUX8_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit
31-28
Field
Value
PINMUX8_31_28
Pin is 3-stated.
1h
Selects Function EMA_D[8]
8h
9h-Fh
PINMUX8_27_24
I/O
Reserved
Pin is 3-stated.
Selects Function EMA_D[9]
PINMUX8_23_20
X
Z
I/O
Reserved
X
Selects Function GP3[1]
I/O
Reserved
X
EMA_D[10]/GP3[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[10]
2h-7h
8h
9h-Fh
PINMUX8_19_16
Z
I/O
Reserved
X
Selects Function GP3[2]
I/O
Reserved
X
EMA_D[11]/GP3[3] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[11]
2h-7h
8h
9h-Fh
PINMUX8_15_12
Z
I/O
Reserved
X
Selects Function GP3[3]
I/O
Reserved
X
EMA_D[12]/GP3[4] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[12]
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP3[0]
0
8h
15-12
Z
I/O
Reserved
1h
9h-Fh
19-16
(1)
EMA_D[9]/GP3[1] Control
2h-7h
23-20
Type
EMA_D[8]/GP3[0] Control
0
2h-7h
27-24
Description
Z
I/O
Reserved
X
Selects Function GP3[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX8_11_8
0
Pin is 3-stated.
1h
Selects Function EMA_D[13]
8h
9h-Fh
PINMUX8_7_4
Reserved
Selects Function GP3[5]
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_D[14]
8h
9h-Fh
PINMUX8_3_0
Z
I/O
X
I/O
X
Reserved
Selects Function GP3[6]
Reserved
Z
I/O
X
I/O
X
EMA_D[15]/GP3[7] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[15]
2h-7h
8h
9h-Fh
242
(1)
EMA_D[14]/GP3[6] Control
2h-7h
3-0
Type
EMA_D[13]/GP3[5] Control
2h-7h
7-4
Description
Reserved
Selects Function GP3[7]
Reserved
System Configuration (SYSCFG) Module
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Z
I/O
X
I/O
X
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11.5.10.10 Pin Multiplexing Control 9 Register (PINMUX9)
Figure 11-27. Pin Multiplexing Control 9 Register (PINMUX9)
31
28
27
24
23
20
19
16
PINMUX9_31_28
PINMUX9_27_24
PINMUX9_23_20
PINMUX9_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX9_15_12
PINMUX9_11_8
PINMUX9_7_4
PINMUX9_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
Bit
31-28
Field
Value
PINMUX9_31_28
Pin is 3-stated.
1h
Selects Function EMA_D[0]
8h
9h-Fh
PINMUX9_27_24
I/O
Reserved
Pin is 3-stated.
Selects Function EMA_D[1]
PINMUX9_23_20
X
Z
I/O
Reserved
X
Selects Function GP4[9]
I/O
Reserved
X
EMA_D[2]/GP4[10] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[2]
2h-7h
8h
9h-Fh
PINMUX9_19_16
Z
I/O
Reserved
X
Selects Function GP4[10]
I/O
Reserved
X
EMA_D[3]/GP4[11] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[3]
2h-7h
8h
9h-Fh
PINMUX9_15_12
Z
I/O
Reserved
X
Selects Function GP4[11]
I/O
Reserved
X
EMA_D[4]/GP4[12] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[4]
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP4[8]
0
8h
15-12
Z
I/O
Reserved
1h
9h-Fh
19-16
(1)
EMA_D[1]/GP4[9] Control
2h-7h
23-20
Type
EMA_D[0]/GP4[8] Control
0
2h-7h
27-24
Description
Z
I/O
Reserved
X
Selects Function GP4[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX9_11_8
0
Pin is 3-stated.
1h
Selects Function EMA_D[5]
8h
9h-Fh
PINMUX9_7_4
Reserved
Selects Function GP4[13]
Reserved
0
Pin is 3-stated.
1h
Selects Function EMA_D[6]
8h
9h-Fh
PINMUX9_3_0
Z
I/O
X
I/O
X
Reserved
Selects Function GP4[14]
Reserved
Z
I/O
X
I/O
X
EMA_D[7]/GP4[15] Control
0
Pin is 3-stated.
1h
Selects Function EMA_D[7]
2h-7h
8h
9h-Fh
244
(1)
EMA_D[6]/GP4[14] Control
2h-7h
3-0
Type
EMA_D[5]/GP4[13] Control
2h-7h
7-4
Description
Reserved
Selects Function GP4[15]
Reserved
System Configuration (SYSCFG) Module
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Z
I/O
X
I/O
X
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11.5.10.11 Pin Multiplexing Control 10 Register (PINMUX10)
Figure 11-28. Pin Multiplexing Control 10 Register (PINMUX10)
31
28
27
24
23
20
19
16
PINMUX10_31_28
PINMUX10_27_24
PINMUX10_23_20
PINMUX10_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX10_15_12
PINMUX10_11_8
PINMUX10_7_4
PINMUX10_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
Bit
31-28
Field
Value
PINMUX10_31_28
Pin is 3-stated.
Z
1h
Selects Function EMA_A[16]
O
2h
Selects Function MMCSD0_DAT[5]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[24]
O
Reserved
X
8h
PINMUX10_27_24
Selects Function GP4[0]
I/O
Reserved
X
EMA_A[17]/MMCSD0_DAT[4]/PRU1_R30[25]/GP4[1] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[17]
O
2h
Selects Function MMCSD0_DAT[4]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[25]
O
5h-7h
8h
9h-Fh
PINMUX10_23_20
Reserved
X
Selects Function GP4[1]
I/O
Reserved
X
EMA_A[18]/MMCSD0_DAT[3]/PRU1_R30[26]/GP4[2] Control
0
Pin is 3-stated.
1h
Selects Function EMA_A[18]
O
2h
Selects Function MMCSD0_DAT[3]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[26]
O
5h-7h
8h
9h-Fh
(1)
(1)
EMA_A[16]/MMCSD0_DAT[5]/PRU1_R30[24]/GP4[0] Control
9h-Fh
23-20
Type
0
5h-7h
27-24
Description
Z
Reserved
X
Selects Function GP4[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued)
Bit
Field
19-16
Value
PINMUX10_19_16
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[19]
O
2h
Selects Function MMCSD0_DAT[2]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[27]
O
8h
9h-Fh
PINMUX10_15_12
Reserved
X
I/O
X
1h
Selects Function EMA_A[20]
O
2h
Selects Function MMCSD0_DAT[1]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[28]
O
PINMUX10_11_8
Reserved
Selects Function GP4[4]
Reserved
Z
X
I/O
X
EMA_A[21]/MMCSD0_DAT[0]/PRU1_R30[29]/GP4[5] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[21]
O
2h
Selects Function MMCSD0_DAT[0]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[29]
O
Reserved
X
5h-7h
8h
9h-Fh
PINMUX10_7_4
Selects Function GP4[5]
Reserved
I/O
X
EMA_A[22]/MMCSD0_CMD/PRU1_R30[30]/GP4[6] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[22]
O
2h
Selects Function MMCSD0_CMD
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[30]
O
5h-7h
8h
9h-Fh
PINMUX10_3_0
Reserved
Selects Function GP4[6]
Reserved
X
I/O
X
MMCSD0_CLK/PRU1_R30[31]/GP4[7] Control
0
Pin is 3-stated.
1h
Reserved
X
2h
Selects Function MMCSD0_CLK
O
3h
Reserved
X
4h
Selects Function PRU1_R30[31]
O
5h-7h
8h
9h-Fh
246
Selects Function GP4[3]
Pin is 3-stated.
9h-Fh
3-0
Reserved
0
8h
7-4
(1)
EMA_A[20]/MMCSD0_DAT[1]/PRU1_R30[28]/GP4[4] Control
5h-7h
11-8
Type
EMA_A[19]/MMCSD0_DAT[2]/PRU1_R30[27]/GP4[3] Control
5h-7h
15-12
Description
Reserved
Selects Function GP4[7]
Reserved
System Configuration (SYSCFG) Module
Copyright © 2011, Texas Instruments Incorporated
Z
X
I/O
X
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11.5.10.12 Pin Multiplexing Control 11 Register (PINMUX11)
Figure 11-29. Pin Multiplexing Control 11 Register (PINMUX11)
31
28
27
24
23
20
19
16
PINMUX11_31_28
PINMUX11_27_24
PINMUX11_23_20
PINMUX11_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX11_15_12
PINMUX11_11_8
PINMUX11_7_4
PINMUX11_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
Bit
31-28
Field
Value
PINMUX11_31_28
Pin is 3-stated.
Z
1h
Selects Function EMA_A[8]
O
5h-7h
8h
9h-Fh
PINMUX11_27_24
X
Selects Function PRU1_R30[16]
O
Reserved
X
Selects Function GP5[8]
I/O
Reserved
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[9]
O
4h
5h-7h
8h
9h-Fh
PINMUX11_23_20
Reserved
X
Selects Function PRU1_R30[17]
O
Reserved
X
Selects Function GP5[9]
I/O
Reserved
X
EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18] Control
0
Selects Function PRU1_R31[18]
I
1h
Selects Function EMA_A[10]
O
Reserved
X
Selects Function PRU1_R30[18]
O
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX11_19_16
Reserved
X
Selects Function GP5[10]
I/O
Reserved
X
EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19] Control
0
Selects Function PRU1_R31[19]
I
1h
Selects Function EMA_A[11]
O
2h-3h
4h
5h-7h
8h
9h-Fh
(1)
Reserved
EMA_A[9]/PRU1_R30[17]/GP5[9] Control
2h-3h
19-16
(1)
EMA_A[8]/PRU1_R30[16]/GP5[8] Control
4h
23-20
Type
0
2h-3h
27-24
Description
Reserved
X
Selects Function PRU1_R30[19]
O
Reserved
X
Selects Function GP5[11]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX11_15_12
0
Selects Function PRU1_R31[20]
I
1h
Selects Function EMA_A[12]
O
4h
5h-7h
8h
9h-Fh
PINMUX11_11_8
X
Selects Function PRU1_R30[20]
O
Reserved
X
Selects Function GP5[12]
I/O
Reserved
X
Selects Function PRU1_R31[21]
I
1h
Selects Function EMA_A[13]
O
2h
Selects Function PRU0_R30[21]
O
3h
Reserved
X
4h
Selects Function PRU1_R30[21]
O
Reserved
X
8h
PINMUX11_7_4
Selects Function GP5[13]
I/O
Reserved
X
EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22] Control
0
Selects Function PRU1_R31[22]
I
1h
Selects Function EMA_A[14]
O
2h
Selects Function MMCSD0_DAT[7]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[22]
O
5h-7h
8h
9h-Fh
PINMUX11_3_0
Reserved
X
Selects Function GP5[14]
I/O
Reserved
X
EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23] Control
0
Selects Function PRU1_R31[23]
1h
Selects Function EMA_A[15]
O
2h
Selects Function MMCSD0_DAT[6]
I/O
3h
Reserved
X
4h
Selects Function PRU1_R30[23]
O
5h-7h
8h
9h-Fh
248
(1)
EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21] Control
9h-Fh
3-0
Reserved
0
5h-7h
7-4
Type
EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20] Control
2h-3h
11-8
Description
Reserved
Selects Function GP5[15]
Reserved
System Configuration (SYSCFG) Module
Copyright © 2011, Texas Instruments Incorporated
I
X
I/O
X
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11.5.10.13 Pin Multiplexing Control 12 Register (PINMUX12)
Figure 11-30. Pin Multiplexing Control 12 Register (PINMUX12)
31
28
27
24
23
20
19
16
PINMUX12_31_28
PINMUX12_27_24
PINMUX12_23_20
PINMUX12_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX12_15_12
PINMUX12_11_8
PINMUX12_7_4
PINMUX12_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
Bit
31-28
Field
Value
PINMUX12_31_28
Pin is 3-stated.
Z
1h
Selects Function EMA_A[0]
O
9h-Fh
PINMUX12_27_24
I/O
Reserved
X
0
Pin is 3-stated.
Z
Selects Function EMA_A[1]
O
Reserved
X
8h
PINMUX12_23_20
Selects Function GP5[1]
I/O
Reserved
X
EMA_A[2]/GP5[2] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[2]
O
2h-7h
8h
9h-Fh
PINMUX12_19_16
Reserved
X
Selects Function GP5[2]
I/O
Reserved
X
EMA_A[3]/GP5[3] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[3]
O
2h-7h
8h
9h-Fh
PINMUX12_15_12
Reserved
X
Selects Function GP5[3]
I/O
Reserved
X
EMA_A[4]/GP5[4] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[4]
O
2h-7h
8h
9h-Fh
(1)
X
Selects Function GP5[0]
1h
9h-Fh
15-12
Reserved
EMA_A[1]/GP5[1] Control
2h-7h
19-16
(1)
EMA_A[0]/GP5[0] Control
8h
23-20
Type
0
2h-7h
27-24
Description
Reserved
X
Selects Function GP5[4]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX12_11_8
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[5]
O
8h
9h-Fh
PINMUX12_7_4
Reserved
Selects Function GP5[5]
Reserved
X
I/O
X
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[6]
O
8h
9h-Fh
PINMUX12_3_0
Reserved
Selects Function GP5[6]
Reserved
X
I/O
X
EMA_A[7]/PRU1_R30[15]/GP5[7] Control
0
Pin is 3-stated.
Z
1h
Selects Function EMA_A[7]
O
2h-3h
4h
5h-7h
8h
9h-Fh
250
(1)
EMA_A[6]/GP5[6] Control
2h-7h
3-0
Type
EMA_A[5]/GP5[5] Control
2h-7h
7-4
Description
Reserved
X
Selects Function PRU1_R30[15]
O
Reserved
X
Selects Function GP5[7]
Reserved
System Configuration (SYSCFG) Module
Copyright © 2011, Texas Instruments Incorporated
I/O
X
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11.5.10.14 Pin Multiplexing Control 13 Register (PINMUX13)
Figure 11-31. Pin Multiplexing Control 13 Register (PINMUX13)
31
28
27
24
23
20
19
16
PINMUX13_31_28
PINMUX13_27_24
PINMUX13_23_20
PINMUX13_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX13_15_12
PINMUX13_11_8
PINMUX13_7_4
PINMUX13_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
Bit
31-28
Field
Value
PINMUX13_31_28
Selects Function PRU1_R31[17]
I
1h
Selects Function PRU0_R30[26]
O
9h-Fh
PINMUX13_27_24
I/O
Reserved
X
0
Pin is 3-stated.
Z
Selects Function PRU0_R30[27]
O
Reserved
X
8h
PINMUX13_23_20
Selects Function GP6[9]
I/O
Reserved
X
PRU0_R30[28]/GP6[10] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[28]
O
2h-7h
8h
9h-Fh
PINMUX13_19_16
Reserved
X
Selects Function GP6[10]
I/O
Reserved
X
PRU0_R30[29]/GP6[11] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[29]
O
2h-7h
8h
9h-Fh
PINMUX13_15_12
Reserved
X
Selects Function GP6[11]
I/O
Reserved
X
PRU0_R30[30]/PRU1_R30[11]/GP6[12] Control
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[30]
O
2h-3h
4h
5h-7h
8h
9h-Fh
(1)
X
Selects Function GP6[8]
1h
9h-Fh
15-12
Reserved
PRU0_R30[27]/GP6[9] Control
2h-7h
19-16
(1)
PRU0_R30[26]/GP6[8]/PRU1_R31[17] Control
8h
23-20
Type
0
2h-7h
27-24
Description
Reserved
X
Selects Function PRU1_R30[11]
O
Reserved
X
Selects Function GP6[12]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued)
Bit
11-8
Field
Value
PINMUX13_11_8
0
Pin is 3-stated.
Z
1h
Selects Function PRU0_R30[31]
O
4h
5h-7h
8h
9h-Fh
PINMUX13_7_4
(1)
X
Selects Function PRU1_R30[12]
O
Reserved
Selects Function GP6[13]
Reserved
X
I/O
X
CLKOUT/PRU1_R30[13]/GP6[14] Control
Pin is 3-stated.
Z
1h
Selects Function CLKOUT
O
4h
5h-7h
8h
9h-Fh
PINMUX13_3_0
Reserved
X
Selects Function PRU1_R30[13]
O
Reserved
Selects Function GP6[14]
Reserved
X
I/O
X
RESETOUT/PRU1_R30[14]/GP6[15] Control
0
Selects Function RESETOUT
O
1h
Selects Function RESETOUT
O
2h-3h
4h
5h-7h
8h
9h-Fh
252
Reserved
0
2h-3h
3-0
Type
PRU0_R30[31]/PRU1_R30[12]/GP6[13] Control
2h-3h
7-4
Description
Reserved
X
Selects Function PRU1_R30[14]
O
Reserved
Selects Function GP6[15]
Reserved
System Configuration (SYSCFG) Module
Copyright © 2011, Texas Instruments Incorporated
X
I/O
X
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11.5.10.15 Pin Multiplexing Control 14 Register (PINMUX14)
Figure 11-32. Pin Multiplexing Control 14 Register (PINMUX14)
31
28
27
24
23
20
19
16
PINMUX14_31_28
PINMUX14_27_24
PINMUX14_23_20
PINMUX14_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX14_15_12
PINMUX14_11_8
PINMUX14_7_4
PINMUX14_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
Bit
31-28
Field
Value
PINMUX14_31_28
1h-7h
8h
9h-Fh
PINMUX14_27_24
1h-7h
8h
9h-Fh
PINMUX14_23_20
1h-7h
8h
9h-Fh
PINMUX14_19_16
1h-7h
8h
9h-Fh
PINMUX14_15_12
1h-7h
8h
9h-Fh
PINMUX14_11_8
Selects Function RMII_RXER
I
Reserved
X
Selects Function PRU0_R31[25]
I
Reserved
X
Selects Function RMII_RXD[0]
I
Reserved
X
Selects Function PRU0_R31[26]
I
Reserved
X
Selects Function RMII_RXD[1]
I
Reserved
X
Selects Function PRU0_R31[27]
I
Reserved
X
Selects Function RMII_TXEN
O
Reserved
X
Selects Function PRU0_R31[28]
I
Reserved
X
Selects Function RMII_TXD[0]
O
Reserved
X
RMII_TXD[1]/PRU0_R31[29] Control
0
1h-7h
8h
9h-Fh
(1)
X
RMII_TXD[0]/PRU0_R31[28] Control
0
11-8
I
Reserved
RMII_TXEN/PRU0_R31[27] Control
0
15-12
Selects Function PRU0_R31[24]
RMII_RXD[1]/PRU0_R31[26] Control
0
19-16
(1)
RMII_RXD[0]/PRU0_R31[25] Control
0
23-20
Type
RMII_RXER/PRU0_R31[24] Control
0
27-24
Description
Selects Function PRU0_R31[29]
I
Reserved
X
Selects Function RMII_TXD[1]
O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued)
Bit
Field
7-4
PINMUX14_7_4
Value
0
4h
5h-7h
8h
9h-Fh
PINMUX14_3_0
(1)
Selects Function PRU1_R31[16]
I
Reserved
X
Selects Function PRU1_R30[9]
O
Reserved
X
Selects Function GP6[6]
Reserved
I/O
X
PRU1_R30[10]/GP6[7] Control
0
1h-3h
4h
5h-7h
8h
9h-Fh
254
Type
PRU1_R30[9]/GP6[6]/PRU1_R31[16] Control
1h-3h
3-0
Description
Pin is 3-stated.
Z
Reserved
X
Selects Function PRU1_R30[10]
O
Reserved
Selects Function GP6[7]
Reserved
System Configuration (SYSCFG) Module
Copyright © 2011, Texas Instruments Incorporated
X
I/O
X
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11.5.10.16 Pin Multiplexing Control 15 Register (PINMUX15)
Figure 11-33. Pin Multiplexing Control 15 Register (PINMUX15)
31
28
27
24
23
20
19
16
PINMUX15_31_28
PINMUX15_27_24
PINMUX15_23_20
PINMUX15_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX15_15_12
PINMUX15_11_8
PINMUX15_7_4
PINMUX15_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
Bit
31-28
Field
Value
PINMUX15_31_28
1h-7h
8h
9h-Fh
PINMUX15_27_24
1h-7h
8h
9h-Fh
PINMUX15_23_20
1h-7h
8h
9h-Fh
PINMUX15_19_16
1h-7h
8h
9h-Fh
PINMUX15_15_12
1h-7h
8h
9h-Fh
PINMUX15_11_8
1h-7h
8h
9h-Fh
PINMUX15_7_4
O
Reserved
X
Selects Function PRU0_R31[11]
I
Reserved
X
Selects Function PRU0_R30[11]
O
Reserved
X
Selects Function PRU0_R31[12]
I
Reserved
X
Selects Function PRU0_R30[12]
O
Reserved
X
Selects Function PRU0_R31[13]
I
Reserved
X
Selects Function PRU0_R30[13]
O
Reserved
X
Selects Function PRU0_R31[14]
I
Reserved
X
Selects Function PRU0_R30[14]
O
Reserved
X
Selects Function PRU0_R31[15]
I
Reserved
X
Selects Function PRU0_R30[15]
O
Reserved
X
RMII_CRS_DV/PRU1_R31[29] Control
0
1h-7h
8h
9h-Fh
(1)
Selects Function PRU0_R30[10]
PRU0_R30[15]/PRU0_R31[15] Control
0
7-4
X
PRU0_R30[14]/PRU0_R31[14] Control
0
11-8
I
Reserved
PRU0_R30[13]/PRU0_R31[13] Control
0
15-12
Selects Function PRU0_R31[10]
PRU0_R30[12]/PRU0_R31[12] Control
0
19-16
(1)
PRU0_R30[11]/PRU0_R31[11] Control
0
23-20
Type
PRU0_R30[10]/PRU0_R31[10] Control
0
27-24
Description
Selects Function PRU1_R31[29]
I
Reserved
X
Selects Function RMII_CRS_DV
I
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued)
Bit
Field
3-0
PINMUX15_3_0
Value
Type
(1)
RMII_MHZ_50_CLK/PRU0_R31[23] Control
0
1h-7h
8h
9h-Fh
256
Description
Selects Function PRU0_R31[23]. Enables sourcing of the 50 MHz reference clock
from an external source on the RMII_MHZ_50_CLK pin to the EMAC.
I
Reserved
X
Selects Function RMII_MHZ_50_CLK. Enables sourcing of the 50 MHz reference
clock from PLL0_SYSCLK7 to the EMAC. Also, PLL0_SYSCLK7 is driven out on the
RMII_MHZ_50_CLK pin. Note that the SYSCLK7 output clock does not meet the
RMII reference clock specification of 50 MHz +/-50 ppm. See Section 7.3.4 for more
information.
O
Reserved
X
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11.5.10.17 Pin Multiplexing Control 16 Register (PINMUX16)
Figure 11-34. Pin Multiplexing Control 16 Register (PINMUX16)
31
28
27
24
23
20
19
16
PINMUX16_31_28
PINMUX16_27_24
PINMUX16_23_20
PINMUX16_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX16_15_12
PINMUX16_11_8
PINMUX16_7_4
PINMUX16_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
Bit
31-28
Field
Value
PINMUX16_31_28
1h-7h
8h
9h-Fh
PINMUX16_27_24
1h-7h
8h
9h-Fh
PINMUX16_23_20
1h-7h
8h
9h-Fh
PINMUX16_19_16
1h-7h
8h
9h-Fh
PINMUX16_15_12
1h-7h
8h
9h-Fh
PINMUX16_11_8
1h-7h
8h
9h-Fh
PINMUX16_7_4
I/O
Reserved
X
Selects Function PRU1_R31[11]
I
Reserved
X
Selects Function GP7[11]
I/O
Reserved
X
Selects Function PRU1_R31[12]
I
Reserved
X
Selects Function GP7[12]
I/O
Reserved
X
Selects Function PRU1_R31[13]
I
Reserved
X
Selects Function GP7[13]
I/O
Reserved
X
Selects Function PRU1_R31[14]
I
Reserved
X
Selects Function GP7[14]
I/O
Reserved
X
Selects Function PRU1_R31[15]
I
Reserved
X
Selects Function GP7[15]
I/O
Reserved
X
GP6[5]/PRU1_R31[0] Control
0
1h-7h
8h
9h-Fh
(1)
Selects Function GP7[10]
GP7[15]/PRU1_R31[15] Control
0
7-4
X
GP7[14]/PRU1_R31[14] Control
0
11-8
I
Reserved
GP7[13]/PRU1_R31[13] Control
0
15-12
Selects Function PRU1_R31[10]
GP7[12]/PRU1_R31[12] Control
0
19-16
(1)
GP7[11]/PRU1_R31[11] Control
0
23-20
Type
GP7[10]/PRU1_R31[10] Control
0
27-24
Description
Selects Function PRU1_R31[0]
I
Reserved
X
Selects Function GP6[5]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued)
Bit
Field
3-0
PINMUX16_3_0
Value
Type
(1)
PRU0_R30[9]/PRU0_R31[9] Control
0
1h-7h
8h
9h-Fh
258
Description
Selects Function PRU0_R31[9]
I
Reserved
X
Selects Function PRU0_R30[9]
O
Reserved
X
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11.5.10.18 Pin Multiplexing Control 17 Register (PINMUX17)
Figure 11-35. Pin Multiplexing Control 17 Register (PINMUX17)
31
28
27
24
23
20
19
16
PINMUX17_31_28
PINMUX17_27_24
PINMUX17_23_20
PINMUX17_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX17_15_12
PINMUX17_11_8
PINMUX17_7_4
PINMUX17_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
Bit
31-28
Field
Value
PINMUX17_31_28
1h-7h
8h
9h-Fh
PINMUX17_27_24
1h-7h
8h
9h-Fh
PINMUX17_23_20
1h-7h
8h
9h-Fh
PINMUX17_19_16
1h-7h
8h
9h-Fh
PINMUX17_15_12
1h-7h
8h
9h-Fh
PINMUX17_11_8
1h-7h
8h
9h-Fh
PINMUX17_7_4
I/O
Reserved
X
Selects Function BOOT[3]
I
Reserved
X
Selects Function GP7[3]
I/O
Reserved
X
Selects Function BOOT[4]
I
Reserved
X
Selects Function GP7[4]
I/O
Reserved
X
Selects Function BOOT[5]
I
Reserved
X
Selects Function GP7[5]
I/O
Reserved
X
Selects Function BOOT[6]
I
Reserved
X
Selects Function GP7[6]
I/O
Reserved
X
Selects Function BOOT[7]
I
Reserved
X
Selects Function GP7[7]
I/O
Reserved
X
GP7[8]/PRU1_R31[8] Control
0
1h-7h
8h
9h-Fh
(1)
Selects Function GP7[2]
GP7[7]/BOOT[7] Control
0
7-4
X
GP7[6]/BOOT[6] Control
0
11-8
I
Reserved
GP7[5]/BOOT[5] Control
0
15-12
Selects Function BOOT[2]
GP7[4]/BOOT[4] Control
0
19-16
(1)
GP7[3]/BOOT[3] Control
0
23-20
Type
GP7[2]/BOOT[2] Control
0
27-24
Description
Selects Function PRU1_R31[8]
I
Reserved
X
Selects Function GP7[8]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued)
Bit
Field
3-0
PINMUX17_3_0
Value
Type
(1)
GP7[9]/PRU1_R31[9] Control
0
1h-7h
8h
9h-Fh
260
Description
Selects Function PRU1_R31[9]
I
Reserved
X
Selects Function GP7[9]
Reserved
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I/O
X
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11.5.10.19 Pin Multiplexing Control 18 Register (PINMUX18)
Figure 11-36. Pin Multiplexing Control 18 Register (PINMUX18)
31
28
27
24
23
20
19
16
PINMUX18_31_28
PINMUX18_27_24
PINMUX18_23_20
PINMUX18_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX18_15_12
PINMUX18_11_8
PINMUX18_7_4
PINMUX18_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
Bit
31-28
Field
Value
PINMUX18_31_28
Selects Function PRU1_R31[7]
1h
Selects Function MMCSD1_DAT[6]
4h
5h-7h
8h
9h-Fh
PINMUX18_27_24
X
Selects Function PRU1_R30[6]
O
Reserved
X
Selects Function GP8[10]
I/O
Reserved
Pin is 3-stated.
1h
Selects Function MMCSD1_DAT[7]
5h-7h
8h
9h-Fh
PINMUX18_23_20
X
Z
I/O
Reserved
X
Selects Function PRU1_R30[7]
O
Reserved
X
Selects Function GP8[11]
I/O
Reserved
X
PRU0_R30[22]/PRU1_R30[8]/GP8[12]/PRU1_R31[24] Control
0
Selects Function PRU1_R31[24]
I
1h
Selects Function PRU0_R30[22]
O
2h
Selects Function PRU1_R30[8]
O
3h-7h
8h
9h-Fh
PINMUX18_19_16
Reserved
X
Selects Function GP8[12]
I/O
Reserved
X
PRU0_R30[23]/MMCSD1_CMD/GP8[13]/PRU1_R31[25] Control
0
Selects Function PRU1_R31[25]
I
1h
Selects Function PRU0_R30[23]
O
2h
Selects Function MMCSD1_CMD
I/O
3h-7h
8h
9h-Fh
(1)
I
I/O
Reserved
0
4h
19-16
(1)
MMCSD1_DAT[7]/PRU1_R30[7]/GP8[11] Control
2h-3h
23-20
Type
MMCSD1_DAT[6]/PRU1_R30[6]/GP8[10]/PRU1_R31[7] Control
0
2h-3h
27-24
Description
Reserved
X
Selects Function GP8[13]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined, Z = High-impedance state
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Table 11-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX18_15_12
0
Selects Function PRU1_R31[26]
I
1h
Selects Function PRU0_R30[24]
O
2h
Selects Function MMCSD1_CLK
O
Reserved
X
8h
9h-Fh
PINMUX18_11_8
I/O
Reserved
X
0
Selects Function PRU1_R31[27]
I
Selects Function PRU0_R30[25]
O
2h
Selects Function MMCSD1_DAT[0]
I/O
9h-Fh
PINMUX18_7_4
Reserved
Selects Function GP8[15]
Reserved
X
I/O
X
GP7[0]/BOOT[0] Control
0
1h-7h
8h
9h-Fh
PINMUX18_3_0
Selects Function BOOT[0]
I
Reserved
X
Selects Function GP7[0]
Reserved
I/O
X
GP7[1]/BOOT[1] Control
0
1h-7h
8h
9h-Fh
262
Selects Function GP8[14]
1h
8h
3-0
(1)
PRU0_R30[25]/MMCSD1_DAT[0]/GP8[15]/PRU1_R31[27] Control
3h-7h
7-4
Type
PRU0_R30[24]/MMCSD1_CLK/GP8[14]/PRU1_R31[26] Control
3h-7h
11-8
Description
Selects Function BOOT[1]
Reserved
Selects Function GP7[1]
Reserved
System Configuration (SYSCFG) Module
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I
X
I/O
X
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11.5.10.20 Pin Multiplexing Control 19 Register (PINMUX19)
Figure 11-37. Pin Multiplexing Control 19 Register (PINMUX19)
31
28
27
24
23
20
19
16
PINMUX19_31_28
PINMUX19_27_24
PINMUX19_23_20
PINMUX19_19_16
R/W-0
R/W-0
R/W-0
R/W-0
15
12
11
8
7
4
3
0
PINMUX19_15_12
PINMUX19_11_8
PINMUX19_7_4
PINMUX19_3_0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
Bit
31-28
Field
Value
PINMUX19_31_28
Selects Function RTCK
O
1h
Selects Function RTCK
O
9h-Fh
PINMUX19_27_24
0
8h
9h-Fh
PINMUX19_23_20
X
Selects Function GP8[0]
I/O
Reserved
X
Selects Function PRU1_R31[28]
I
Reserved
X
Selects Function GP6[0]
I/O
Reserved
X
PRU1_R30[0]/GP6[1]/PRU1_R31[1] Control
0
1h-3h
4h
5h-7h
8h
9h-Fh
PINMUX19_19_16
Selects Function PRU1_R31[1]
I
Reserved
X
Selects Function PRU1_R30[0]
O
Reserved
X
Selects Function GP6[1]
I/O
Reserved
X
MMCSD1_DAT[1]/PRU1_R30[1]/GP6[2]/PRU1_R31[2] Control
0
Selects Function PRU1_R31[2]
1h
Reserved
2h
Selects Function MMCSD1_DAT[1]
3h
Reserved
X
4h
Selects Function PRU1_R30[1]
O
5h-7h
8h
9h-Fh
(1)
Reserved
GP6[0]/PRU1_R31[28] Control
1h-7h
19-16
(1)
RTCK/GP8[0] Control
8h
23-20
Type
0
2h-7h
27-24
Description
I
X
I/O
Reserved
X
Selects Function GP6[2]
I/O
Reserved
X
I = Input, O = Output, I/O = Bidirectional, X = Undefined
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Table 11-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued)
Bit
Field
15-12
Value
PINMUX19_15_12
0
Selects Function PRU1_R31[3]
I
1h
Reserved
X
2h
Selects Function MMCSD1_DAT[2]
3h
Reserved
X
4h
Selects Function PRU1_R30[2]
O
8h
9h-Fh
PINMUX19_11_8
Reserved
X
Selects Function GP6[3]
I/O
Reserved
X
Selects Function PRU1_R31[4]
1h
Reserved
2h
Selects Function MMCSD1_DAT[3]
3h
Reserved
X
4h
Selects Function PRU1_R30[3]
O
9h-Fh
PINMUX19_7_4
I
X
I/O
Reserved
X
Selects Function GP6[4]
I/O
Reserved
X
MMCSD1_DAT[4]/PRU1_R30[4]/GP8[8]/PRU1_R31[5] Control
0
Selects Function PRU1_R31[5]
1h
Selects Function MMCSD1_DAT[4]
2h-3h
4h
5h-7h
8h
9h-Fh
PINMUX19_3_0
I
I/O
Reserved
X
Selects Function PRU1_R30[4]
O
Reserved
X
Selects Function GP8[8]
I/O
Reserved
X
MMCSD1_DAT[5]/PRU1_R30[5]/GP8[9]/PRU1_R31[6] Control
0
Selects Function PRU1_R31[6]
1h
Selects Function MMCSD1_DAT[5]
2h-3h
4h
5h-7h
8h
9h-Fh
264
I/O
0
8h
3-0
(1)
MMCSD1_DAT[3]/PRU1_R30[3]/GP6[4]/PRU1_R31[4] Control
5h-7h
7-4
Type
MMCSD1_DAT[2]/PRU1_R30[2]/GP6[3]/PRU1_R31[3] Control
5h-7h
11-8
Description
I
I/O
Reserved
X
Selects Function PRU1_R30[5]
O
Reserved
Selects Function GP8[9]
Reserved
System Configuration (SYSCFG) Module
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X
I/O
X
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11.5.11 Suspend Source Register (SUSPSRC)
The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals
that support emulation suspend. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral,
indicates that the DSP emulator controls the peripheral's emulation suspend signal. You should maintain
this register with its default values. The flexibility of the device architecture allows either the ARM or the
DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is a
matter of software convention, during an emulation halt, the device must know which peripherals are
associated with the halting processor, so that only those modules receive the suspend signal. This allows
peripherals associated with the other (unhalted) processor to continue normal operation.
The SUSPSRC is shown in Figure 11-38 and described in Table 11-42.
Figure 11-38. Suspend Source Register (SUSPSRC)
31
30
29
28
27
26
25
24
Reserved
Reserved
TIMER64P_2SRC
TIMER64P_1SRC
TIMER64P_0SRC
Reserved
Reserved
EPWM1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
23
22
21
20
19
18
17
16
EPWM0SRC
SPI1SRC
SPI0SRC
UART2SRC
UART1SRC
UART0SRC
I2C1SRC
I2C0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USB0SRC
MCBSP1SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
MCBSP0SRC
PRUSRC
EMACSRC
Reserved
TIMER64P_3SRC
ECAP2SRC
ECAP1SRC
ECAP0SRC
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-42. Suspend Source Register (SUSPSRC) Field Descriptions
Bit
31-30
29
28
27
26-25
24
23
22
Field
Value
Reserved
1
TIMER64P_2SRC
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
Timer1 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
TIMER64P_0SRC
Timer0 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
EPWM1SRC
EPWM1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
EPWM0SRC
EPWM0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
SPI1SRC
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Reserved. Write the default value to all bits when modifying this register.
Timer2 64 Emulation Suspend Source.
TIMER64P_1SRC
Reserved
Description
SPI1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
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Table 11-42. Suspend Source Register (SUSPSRC) Field Descriptions (continued)
Bit
Field
21
SPI0SRC
20
19
18
17
16
5
266
1
DSP is the source of the emulation suspend.
UART1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
UART0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
I2C1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
I2C0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
USB0 (USB 2.0) Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
McBSP1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
MCBSP0SRC
McBSP0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
PRUSRC
PRU Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
EMACSRC
3
TIMER64P_3SRC
0
ARM is the source of the emulation suspend.
MCBSP1SRC
Reserved
1
UART2 Emulation Suspend Source.
0
I2C0SRC
4
2
DSP is the source of the emulation suspend.
I2C1SRC
USB0SRC
6
ARM is the source of the emulation suspend.
1
UART0SRC
Reserved
7
0
UART1SRC
9
Description
SPI0 Emulation Suspend Source.
UART2SRC
15-10
8
Value
EMAC Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
1
Reserved. Write the default value to all bits when modifying this register.
Timer3 64 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP2SRC
ECAP2 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP1SRC
ECAP1 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
ECAP0SRC
ECAP0 Emulation Suspend Source.
0
ARM is the source of the emulation suspend.
1
DSP is the source of the emulation suspend.
System Configuration (SYSCFG) Module
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11.5.12 Chip Signal Register (CHIPSIG)
The DSP has access to 4 ARM interrupt events in the ARM interrupt map: SYSCFG_CHIPINT0,
SYSCFG_CHIPINT1, SYSCFG_CHIPINT2, and SYSCFG_CHIPINT3. The ARM has access to 3 DSP
interrupt events in the DSP interrupt event map: SYSCFG_CHIPINT2, SYSCFG_CHIPINT3, and NMI.
NOTE: SYSCFG_CHIPINT2 and SYSCFG_CHIPINT3 are essentially for the ARM to interrupt the
DSP. However, these are additionally mapped to the ARM interrupt controller (AINTC), so
that it can be used as debug interrupts, in case there is a need to halt both processors
simultaneously.
The ARM may generate an interrupt to the DSP by setting one of the two CHIPSIG[3-2] bits or an NMI
interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). The DSP may generate an
interrupt to the ARM by setting one of the four CHIPSIG[3-0] bits. Writing a 1 to these bits sets the
interrupts, writing a 0 has no effect. Reads return the value of these bits and can also be used as status
bits. The CHIPSIG is shown in Figure 11-39 and described in Table 11-43.
Figure 11-39. Chip Signal Register (CHIPSIG)
31
16
Reserved
R-0
15
5
Reserved
4
3
CHIPSIG4 CHIPSIG3
R-0
R/W-0
R/W-0
2
1
CHIPSIG2 CHIPSIG1
R/W-0
R/W-0
0
CHIPSIG0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-43. Chip Signal Register (CHIPSIG) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1
0
Value
0
Description
Reserved
Asserts DSP NMI interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG3
Asserts SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG2
Asserts SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG1
Asserts SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Asserts interrupt
CHIPSIG0
Asserts SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Asserts interrupt
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11.5.13 Chip Signal Clear Register (CHIPSIG_CLR)
The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register
(CHIPSIG). Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in
CHIPSIG; writing a 0 has no effect. After servicing the interrupt, the interrupted processor can clear the
bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. The other processor may poll
the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. The
CHIPSIG_CLR is shown in Figure 11-40 and described in Table 11-44.
For more information on ARM interrupts, see the ARM Interrupt Controller (AINTC) chapter. For more
information on DSP interrupts, see the DSP Subsystem chapter.
Figure 11-40. Chip Signal Clear Register (CHIPSIG_CLR)
31
16
Reserved
R-0
15
5
Reserved
4
3
CHIPSIG4 CHIPSIG3
R-0
R/W-0
R/W-0
2
1
CHIPSIG2 CHIPSIG1
R/W-0
R/W-0
0
CHIPSIG0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
Bit
Field
31-5
Reserved
4
CHIPSIG4
3
2
1
0
268
Value
0
Description
Reserved
Clears DSP NMI interrupt.
0
No effect
1
Clears interrupt
CHIPSIG3
Clears SYSCFG_CHIPINT3 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG2
Clears SYSCFG_CHIPINT2 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG1
Clears SYSCFG_CHIPINT1 interrupt.
0
No effect
1
Clears interrupt
CHIPSIG0
Clears SYSCFG_CHIPINT0 interrupt.
0
No effect
1
Clears interrupt
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11.5.14 Chip Configuration 0 Register (CFGCHIP0)
The chip configuration 0 register (CFGCHIP0) controls the following functions:
• PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space.
• EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP0
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_0 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
The CFGCHIP0 is shown in Figure 11-41 and described in Table 11-45.
Figure 11-41. Chip Configuration 0 Register (CFGCHIP0)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PLL_MASTER_LOCK
EDMA30TC1DBS
EDMA30TC0DBS
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Reserved
Value
0
PLL_MASTER_LOCK
Reserved.
PLLC0 MMRs lock.
0
PLLC0 MMRs are freely accessible.
1
All PLLC0 MMRs are locked.
EDMA30TC1DBS
EDMA3_0_TC1 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
EDMA30TC0DBS
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Description
EDMA3_0_TC0 Default Burst Size (DBS).
0
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
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11.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP0 TX/RX events as eCAP event input sources.
• EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of
bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on
the device. By default for all transfer controllers, the burst size is set to 16 bytes. However, CFGCHIP1
allows configurability of this parameter so that the TC can have a burst size of 16, 32, or 64 bytes. The
burst size determines the intra packet efficiency for the EDMA3_1 transfers. Additionally, it also
facilitates preemption at a system level, as all transfer requests are internally broken down by the
transfer controller up to DBS size byte chunks and on a system level, each master’s priority
(configured by the MSTPRI register) is evaluated at burst size boundaries. The DBS value can
significantly impact the standalone throughput performance depending on the source and destination
(bus width/frequency/burst support etc) and the TC FIFO size, etc. Therefore, the DBS size
configuration should be carefully analyzed to meet the system’s throughput/performance requirements.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP0 AMUTEIN signal.
The CFGCHIP1 is shown in Figure 11-42 and described in Table 11-46.
Figure 11-42. Chip Configuration 1 Register (CFGCHIP1)
31
27
15
26
22
21
17
16
CAP2SRC
CAP1SRC
CAP0SRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
14
13
12
11
8
Reserved
EDMA31TC0DBS
TBCLKSYNC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
7
4
3
0
Reserved
AMUTESEL0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
270
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Table 11-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
Bit
31-27
Field
Value
CAP2SRC
Selects the eCAP2 module event input.
0
eCAP2 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
Reserved
7h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
26-22
Description
CAP1SRC
Reserved
Selects the eCAP1 module event input.
0
eCAP1 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
13h-1Fh
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Reserved
7h
Reserved
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Table 11-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued)
Bit
21-17
Field
Value
CAP0SRC
Selects the eCAP0 module event input.
0
eCAP0 Pin input
1h
McASP0 TX DMA Event
2h
McASP0 RX DMA Event
3h-6h
Reserved
14-13
EDMA31TC0DBS
12
EMAC C0 RX Threshold Pulse Interrupt
8h
EMAC C0 RX Pulse Interrupt
9h
EMAC C0 TX Pulse Interrupt
Ah
EMAC C0 Miscellaneous Interrupt
Bh
EMAC C1 RX Threshold Pulse Interrupt
Ch
EMAC C1 RX Pulse Interrupt
Dh
EMAC C1 TX Pulse Interrupt
Eh
EMAC C1 Miscellaneous Interrupt
Fh
EMAC C2 RX Threshold Pulse Interrupt
10h
EMAC C2 RX Pulse Interrupt
11h
EMAC C2 TX Pulse Interrupt
12h
EMAC C2 Miscellaneous Interrupt
0
Reserved
3-0
AMUTESEL0
Reserved. Write the default value to all bits when modifying this register.
EDMA3_1_TC0 Default Burst Size.
16 bytes
1h
32 bytes
2h
64 bytes
3h
Reserved
eHRPWM Module Time Base Clock Synchronization. Allows you to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
0
Time base clock (TBCLK) within each enabled eHRPWM module is stopped.
1
All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. For
perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each eHRPWM
module must be set identically.
0
Reserved. Write the default value to all bits when modifying this register.
Selects the source of McASP0 AMUTEIN signal.
0
Drive McASP0 AMUTEIN signal low.
1h
GPIO Interrupt from Bank 0
2h
GPIO Interrupt from Bank 1
3h
GPIO Interrupt from Bank 2
4h
GPIO Interrupt from Bank 3
5h
GPIO Interrupt from Bank 4
6h
GPIO Interrupt from Bank 5
7h
GPIO Interrupt from Bank 6
8h
GPIO Interrupt from Bank 7
9h-Fh
272
Reserved
0
TBCLKSYNC
11-4
Reserved
7h
13h-1Fh
16-15
Description
Reserved
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11.5.16 Chip Configuration 2 Register (CFGCHIP2)
The chip configuration 2 register (CFGCHIP2) controls the following functions:
• USB2.0 OTG PHY
The CFGCHIP2 is shown in Figure 11-43 and described in Table 11-47.
Figure 11-43. Chip Configuration 2 Register (CFGCHIP2)
31
24
Reserved
R-0
23
18
15
14
17
16
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
R-0
R-0
R-0
12
11
10
9
8
RESET
USB0OTGMODE
13
Reserved
USB0PHYCLKMUX
USB0PHYPWDN
USB0OTGPWRDN
USB0DATPOL
R/W-1
R/W-3h
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
3
7
6
5
4
Reserved
USB0PHY_PLLON
USB0SESNDEN
USB0VBDTCTEN
USB0REF_FREQ
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
Bit
31-18
17
16
15
14-13
Field
Reserved
Clock is not present, power is not good, and PLL has not locked.
1
Clock is present, power is good, and PLL has locked.
Status of USB2.0 PHY VBUS sense.
0
PHY is not sensing voltage presence on the VBUS pin.
1
PHY is sensing voltage presence on the VBUS pin.
USB2.0 PHY reset.
0
Not in reset.
1
USB2.0 PHY in reset.
USB0OTGMODE
USB0PHYCLKMUX
USB2.0 OTG subsystem mode.
0
No override. PHY drive signals to controller based on its comparators for VBUS and ID pins.
1h
Override phy values to force USB host operation.
2h
Override phy values to force USB device operation.
3h
Override phy values to force USB host operation with VBUS low.
0
Reserved. Write the default value when modifying this register.
USB2.0 PHY reference clock input mux.
0
USB2.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.
1
USB2.0 PHY reference clock (AUXCLK) is internally generated from the PLL.
USB0PHYPWDN
USB2.0 PHY operation state control.
0
USB2.0 PHY is enabled and is in operating state (normal operation).
1
USB2.0 PHY is disabled and powered down.
USB0OTGPWRDN
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Reserved
Status of USB2.0 PHY.
RESET
Reserved
Description
0
USB0VBUSSENSE
11
9
0
USB0PHYCLKGD
12
10
Value
USB2.0 OTG subsystem (SS) operation state control.
0
OTG SS is enabled and is in operating state (normal operation).
1
OTG SS is disabled and is powered down.
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Table 11-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued)
Bit
8
Field
7
Reserved
6
USB0PHY_PLLON
5
4
3-0
Value
USB0DATPOL
USB2.0 differential data lines polarity selector.
0
Differential data polarities are inverted (USB_DP is connected to D- and USB_DM is
connected to D+).
1
Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is
connected to D-).
0
Reserved. Write the default value when modifying this register.
Drives USB2.0 PHY, allowing or preventing it from stopping the 48 MHz clock during
USB SUSPEND.
0
USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.
1
USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND
USB0SESNDEN
USB2.0 Session End comparator enable.
0
Session End comparator is disabled.
1
Session End comparator is enabled.
USB0VBDTCTEN
USB2.0 VBUS line comparators enable.
0
All VBUS line comparators are disabled.
1
All VBUS line comparators are enabled.
USB0REF_FREQ
USB2.0 PHY reference clock input frequencies.
0
Reserved
1h
12 MHz
2h
24 MHz
3h
48 MHz
4h
19.2 MHz
5h
38.4 MHz
6h
13 MHz
7h
26 MHz
8h
20 MHz
9h
40 MHz
Ah-Fh
274
Description
Reserved
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11.5.17 Chip Configuration 3 Register (CFGCHIP3)
The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions:
• EMAC MII/RMII Mode Select.
• PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped
registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space.
• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock.
• PRU Event Input Select.
• DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.5) hardware clock divider is provided to generate
133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this
clock divider.
• EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock.
The CFGCHIP3 is shown in Figure 11-44 and described in Table 11-48.
Figure 11-44. Chip Configuration 3 Register (CFGCHIP3)
31
16
Reserved
R-0
15
9
8
Reserved
RMII_SEL
R/W-7Fh
R/W-1
7
6
5
4
3
2
1
0
Reserved
Reserved
PLL1_MASTER_LOCK
ASYNC3_CLKSRC
PRUEVTSEL
DIV45PENA
EMA_CLKSRC
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
Bit
Field
Value
31-16
Reserved
0
15-9
Reserved
7Fh
8
RMII_SEL
7-6
5
4
3
2
1
Reserved
Reserved
Reserved. Write the default value to all bits when modifying this register.
EMAC MII/RMII mode select.
0
MII mode
1
RMII mode
0
Reserved. Write the default value when modifying this register.
PLL1_MASTER_LOCK
PLLC1 MMRs lock.
0
PLLC1 MMRs are freely accessible.
1
All PLLC1 MMRs are locked.
ASYNC3_CLKSRC
Clock source for ASYNC3.
0
Clock driven by PLL0_SYSCLK2.
1
Clock driven by PLL1_SYSCLK2.
PRUEVTSEL
PRU event input select.
0
Normal mode
1
Alternate mode
DIV45PENA
Controls the fixed DIV4.5 divider in the PLL controller.
0
Divide by 4.5 is disabled.
1
Divide by 4.5 is enabled.
EMA_CLKSRC
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Description
Clock source for EMIFA clock domain.
0
Clock driven by PLL0_SYSCLK3
1
Clock driven by DIV4.5 PLL output
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Table 11-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions (continued)
Bit
0
Field
Value
Reserved
Description
0
Reserved. Write the default value when modifying this register.
11.5.18 Chip Configuration 4 Register (CFGCHIP4)
The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0.
Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0, if it was
previously set; reads always return a value of 0. The CFGCHIP4 is shown in Figure 11-45 and described
in Table 11-49.
Figure 11-45. Chip Configuration 4 Register (CFGCHIP4)
31
16
Reserved
R-0
15
8
7
1
0
Reserved
Reserved
AMUTECLR0
R/W-FFh
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
15-8
Reserved
FFh
Reserved. Write the default value to all bits when modifying this register.
7-1
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
0
276
AMUTECLR0
Reserved
Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1.
0
No effect
1
Clears interrupt
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11.5.19 VTP I/O Control Register (VTPIO_CTL)
The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory
controller I/Os with respect to voltage, temperature, and process (VTP). The voltage, temperature, and
process information is used to control the IO's output impedance. The VTPIO_CTL is shown in
Figure 11-46 and described in Table 11-50.
Figure 11-46. VTP I/O Control Register (VTPIO_CTL)
31
24
Reserved
R-0
23
19
18
17
16
Reserved
VREFEN
VREFTAP
R-0
R/W-0
R/W-0
15
14
13
12
9
READY
IOPWRDN
CLKRZ
Reserved
PWRSAVE
R-0
R/W-0
R/W-0
R/W-0
R/W-0
5
7
6
LOCK
POWERDN
D
3
F
R/W-0
R/W-1
R/W-6h
R/W-7h
8
2
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions
Bit
Field
31-19
Reserved
18
VREFEN
17-16
Value
0
Internal DDR I/O Vref enable.
Connected to pad, external reference.
1
Reserved
VREFTAP
Selection for internal reference voltage level.
1h-3h
14
13
12-9
8
7
6
Reserved
0
0
15
Description
READY
Vref = 50.0% of VDDS
Reserved
VTP Ready status.
0
VTP is not ready.
1
VTP is ready.
IOPWRDN
Power down enable for DDR input buffer.
0
Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
1
Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).
CLKRZ
0
VTP clear. Write 0 to clear VTP flops.
Reserved
0
Reserved. Write the default value to all bits when modifying this register.
PWRSAVE
VTP power save mode. Turn off power to the external resistor when it is not needed. The
PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.
0
Disable power save mode.
1
Enable power save mode.
LOCK
VTP impedance lock. Lock impedance value so that the VTP controller can be powered down.
0
Unlock impedance.
1
Lock impedance.
POWERDN
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VTP power down. Power down the VTP controller. The PWRSAVE bit setting is only valid when
the POWERDN bit is cleared to 0.
0
Disable power down.
1
Enable power down.
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Table 11-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions (continued)
Bit
Field
5-3
D
Value
Drive strength control bit.
0-5h
2-0
Reserved
6h
100% drive strength
7h
Reserved
F
Digital filter control bit.
0-6h
7h
278
Description
Reserved
Digital filter is enabled.
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11.5.20 DDR Slew Register (DDR_SLEW)
The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse.
The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR
compatible). The DDR_SLEW is shown in Figure 11-47 and described in Table 11-51.
Figure 11-47. DDR Slew Register (DDR_SLEW)
31
16
Reserved
R-0
15
12
7
11
10
9
8
Reserved
ODT_TERMON
ODT_TERMOFF
R-0
R/W-0
R/W-0
5
4
Reserved
6
DDR_PDENA
CMOSEN
3
DDR_DATASLEW
2
1
DDR_CMDSLEW
0
R-0
R/W-0
R/W-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-51. DDR Slew Register (DDR_SLEW) Field Descriptions
Bit
Field
31-12
Reserved
11-10
ODT_TERMON
Value
0
0
ODT_TERMOFF
5
4
3-2
Reserved
No termination
Reserved
0
Reserved
DDR_PDENA
Enables pull downs for mDDR mode (should be disabled for DDR2).
0
Pull downs are disabled. Disable pull downs when using DDR2.
1
Pull downs are enabled. Enable pull downs when using mDDR.
CMOSEN
Selects mDDR LVCMOS RX / SSTL18 differential RX.
0
SSTL Receiver. Select SSTL when using DDR2.
1
LVCMOS Receiver. Select LVCMOS when using mDDR.
DDR_DATASLEW
Slew rate mode control status for data macro. Slew rate control is not supported on this
device.
0
DDR_CMDSLEW
Slew rate control is off.
Reserved
Slew rate mode control status for command macro. Slew rate control is not supported on
this device.
0
1h-3h
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Reserved
1h-3h
1h-3h
1-0
No termination
Controls Thevenin termination mode while I/O is not in read or write mode. Termination is
not supported on this device.
0
7-6
Reserved
Controls Thevenin termination mode while I/O is in read or write mode. Termination is not
supported on this device.
1h-3h
9-8
Description
Slew rate control is off.
Reserved
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11.5.21 Deep Sleep Register (DEEPSLEEP)
The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. See your device-specific data
manual and the Boot Considerations chapter for details on boot and configuration settings. The
DEEPSLEEP is shown in Figure 11-48 and described in Table 11-52.
Figure 11-48. Deep Sleep Register (DEEPSLEEP)
31
30
SLEEPENABLE
SLEEPCOMPLETE
29
Reserved
16
R/W-0
R-0
R-0
15
0
SLEEPCOUNT
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions
Bit
Field
31
SLEEPENABLE
30
Reserved
15-0
SLEEPCOUNT
Description
Deep sleep enable. The software must clear this bit to 0 when the device is awakened from
deep sleep.
0
Device is in normal operating mode; DEEPSLEEP pin has no effect.
1
Deep sleep mode is enabled; setting DEEPSLEEP pin low initiates oscillator shut down.
SLEEPCOMPLETE
29-16
280
Value
Deep sleep complete. Once the deep sleep process starts, the software must poll the
SLEEPCOMPLETE bit; when the SLEEPCOMPLETE bit is read as 1, the software should
clear the SLEEPENABLE bit and continue operation.
0
SLEEPCOUNT delay is not complete.
1
SLEEPCOUNT delay is complete.
0
Reserved
0-FFFFh
Deep sleep counter. Number of cycles to count prior to the oscillator being stable. All 16
bits are tied directly to the counter in the Deep Sleep logic.
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11.5.22 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin
group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 11-49 and
described in Table 11-53.
Figure 11-49. Pullup/Pulldown Enable Register (PUPD_ENA)
31
0
PUPDENA[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions
Bit
31-0
Field
Value
PUPDENA[n]
Description
Enables internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The internal pull-up or pull-down functionality
selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown
select register (PUPD_SEL).
0
Internal pull-up or pull-down functionality for pin group n is disabled.
1
Internal pull-up or pull-down functionality for pin group n is enabled.
11.5.23 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for
the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 11-50 and
described in Table 11-54 and Table 11-55.
NOTE: The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the
CP[n] pins are pulled down. If the application requires a pull-up during reset, an external
pull-up should be used.
Figure 11-50. Pullup/Pulldown Select Register (PUPD_SEL)
31
0
PUPDSEL[n]
R/W-C3FF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions
Bit
31-0
Field
Value
PUPDSEL[n]
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Description
Selects between the internal pull-up or pull-down functionality for pin group CP[n]. See your
device-specific data manual for pin group information. The selection for bit position n in PUPD_SEL
is only valid when the same bit position n is set in the pullup/pulldown enable register
(PUPD_ENA).
0
Internal pull-down functionality for pin group n is enabled.
1
Internal pull-up functionality for pin group n is enabled.
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Table 11-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values
282
Default
Value
Bit
Field
31
PUPDSEL[31]
1
Description
Pin Group CP[31] is configured for pull-up by default.
30
PUPDSEL[30]
1
Pin Group CP[30] is configured for pull-up by default.
29
PUPDSEL[29]
0
Pin Group CP[29] is configured for pull-down by default.
28
PUPDSEL[28]
0
Pin Group CP[28] is configured for pull-down by default.
27
PUPDSEL[27]
0
Pin Group CP[27] is configured for pull-down by default.
26
PUPDSEL[26]
0
Pin Group CP[26] is configured for pull-down by default.
25
PUPDSEL[25]
1
Pin Group CP[25] is configured for pull-up by default.
24
PUPDSEL[24]
1
Pin Group CP[24] is configured for pull-up by default.
23
PUPDSEL[23]
1
Pin Group CP[23] is configured for pull-up by default.
22
PUPDSEL[22]
1
Pin Group CP[22] is configured for pull-up by default.
21
PUPDSEL[21]
1
Pin Group CP[21] is configured for pull-up by default.
20
PUPDSEL[20]
1
Pin Group CP[20] is configured for pull-up by default.
19
PUPDSEL[19]
1
Pin Group CP[19] is configured for pull-up by default.
18
PUPDSEL[18]
1
Pin Group CP[18] is configured for pull-up by default.
17
PUPDSEL[17]
1
Pin Group CP[17] is configured for pull-up by default.
16
PUPDSEL[16]
1
Pin Group CP[16] is configured for pull-up by default.
15
PUPDSEL[15]
1
Pin Group CP[15] is configured for pull-up by default.
14
PUPDSEL[14]
1
Pin Group CP[14] is configured for pull-up by default.
13
PUPDSEL[13]
1
Pin Group CP[13] is configured for pull-up by default.
12
PUPDSEL[12]
1
Pin Group CP[12] is configured for pull-up by default.
11
PUPDSEL[11]
1
Pin Group CP[11] is configured for pull-up by default.
10
PUPDSEL[10]
1
Pin Group CP[10] is configured for pull-up by default.
9
PUPDSEL[9]
1
Pin Group CP[9] is configured for pull-up by default.
8
PUPDSEL[8]
1
Pin Group CP[8] is configured for pull-up by default.
7
PUPDSEL[7]
1
Pin Group CP[7] is configured for pull-up by default.
6
PUPDSEL[6]
1
Pin Group CP[6] is configured for pull-up by default.
5
PUPDSEL[5]
1
Pin Group CP[5] is configured for pull-up by default.
4
PUPDSEL[4]
1
Pin Group CP[4] is configured for pull-up by default.
3
PUPDSEL[3]
1
Pin Group CP[3] is configured for pull-up by default.
2
PUPDSEL[2]
1
Pin Group CP[2] is configured for pull-up by default.
1
PUPDSEL[1]
1
Pin Group CP[1] is configured for pull-up by default.
0
PUPDSEL[0]
1
Pin Group CP[0] is configured for pull-up by default.
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11.5.24 RXACTIVE Control Register (RXACTIVE)
The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group
n defined in your device-specific data manual. The RXACTIVE is shown in Figure 11-51 and described in
Table 11-56.
Figure 11-51. RXACTIVE Control Register (RXACTIVE)
31
0
RXACTIVE[n]
R/W-FFFF FFFFh
LEGEND: R/W = Read/Write; -n = value after reset
Table 11-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions
Bit
31-0
Field
Value
RXACTIVE[n]
Description
Enables the LVCMOS receivers on pin group n. See your device-specific data manual for pin group
information. Receivers should only be disabled if the associated pin group is not being used.
0
LVCMOS receivers for pin group n are disabled.
1
LVCMOS receivers for pin group n are enabled.
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Chapter 12
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ARM Interrupt Controller (AINTC)
Topic
12.1
12.2
12.3
12.4
...........................................................................................................................
Introduction ....................................................................................................
Interrupt Mapping ............................................................................................
AINTC Methodology .........................................................................................
AINTC Registers ..............................................................................................
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Page
286
286
289
293
285
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12.1 Introduction
The ARM interrupt controller (AINTC) is an interface between interrupts coming from different parts of the
system (these are referred to as system interrupts in this document), and the ARM9 interrupt interface.
ARM9 supports two types of interrupts: FIQ and IRQ (these are referred to as host interrupts in this
document). The AINTC has the following features:
• Supports up to 101 system interrupts.
• Supports up to 32 interrupt channels.
• Channels 0 and 1 are mapped (hard-wired) to the FIQ ARM interrupt and channels 2-31 are mapped to
IRQ ARM interrupt.
• Each system interrupt can be enabled and disabled.
• Each host interrupt can be enabled and disabled.
• Hardware prioritization of interrupts.
• Combining of interrupts from IPs to a single system interrupt.
• Supports two active low debug interrupts.
See the ARM926EJ Technical Reference Manual for information about the ARM's FIQ and IRQ interrupts.
12.2 Interrupt Mapping
The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels
inside the AINTC (see Figure 12-1). Interrupts from these 32 channels are further mapped to either an
ARM FIQ interrupt or an ARM IRQ interrupt.
•
•
•
•
•
•
•
Any of the 101 system interrupts can be mapped to any of the 32 channels.
Multiple interrupts can be mapped to a single channel.
An interrupt should not be mapped to more than one channel.
Interrupts from channels 0 and 1 are mapped to FIQ ARM interrupt on host side.
Interrupts from channels 2 to 31 are mapped to IRQ ARM interrupt on host side.
For I < k, interrupts on channel-I have higher priority than interrupts on channel-k.
For interrupts on same channel, priority is determined by the hardware interrupt number. The lower the
interrupt number, the higher the priority.
Table 12-1 shows the system interrupt assignments for the AINTC.
Figure 12-1. AINTC Interrupt Mapping
Host Interrupt Mapping
of Channels
AINTC
ARM
Channel 0
Channel Mapping
of System Interrupts
Intr 0
Intr 1
FIQ
Peripheral A
Channel 1
Channel 2
Intr (n–1)
IRQ
Channel m
Intr n
Peripheral Z
n ≤ 100
m ≤ 31
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Table 12-1. AINTC System Interrupt Assignments
Event
Interrupt Name
Source
0
COMMTX
ARM
1
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRUSS Interrupt
4
PRU_EVTOUT1
PRUSS Interrupt
5
PRU_EVTOUT2
PRUSS Interrupt
6
PRU_EVTOUT3
PRUSS Interrupt
7
PRU_EVTOUT4
PRUSS Interrupt
8
PRU_EVTOUT5
PRUSS Interrupt
9
PRU_EVTOUT6
PRUSS Interrupt
10
PRU_EVTOUT7
PRUSS Interrupt
11
EDMA3_0_CC0_INT0
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
12
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrupt
13
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrupt
14
EMIFA_INT
EMIFA Interrupt
15
IIC0_INT
I2C0 interrupt
16
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
17
MMCSD0_INT1
MMCSD0 SDIO Interrupt
18
PSC0_ALLINT
PSC0 Interrupt
19
RTC_IRQS[1:0]
RTC Interrupt
20
SPI0_INT
SPI0 Interrupt
21
T64P0_TINT12
Timer64P0 Interrupt (TINT12)
22
T64P0_TINT34
Timer64P0 Interrupt (TINT34)
23
T64P1_TINT12
Timer64P1 Interrupt (TINT12)
24
T64P1_TINT34
Timer64P1 Interrupt (TINT34)
25
UART0_INT
UART0 Interrupt
26
—
Reserved
27
PROTERR
SYSCFG Protection Shared Interrupt
28
SYSCFG_CHIPINT0
SYSCFG CHIPSIG Register
29
SYSCFG_CHIPINT1
SYSCFG CHIPSIG Register
30
SYSCFG_CHIPINT2
SYSCFG CHIPSIG Register
31
SYSCFG_CHIPINT3
SYSCFG CHIPSIG Register
32
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrupt
33
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
34
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
35
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
36
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
37
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
38
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
39
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
40
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
41
DDR2_MEMERR
DDR2 Controller Interrupt
42
GPIO_B0INT
GPIO Bank 0 Interrupt
43
GPIO_B1INT
GPIO Bank 1 Interrupt
44
GPIO_B2INT
GPIO Bank 2 Interrupt
45
GPIO_B3INT
GPIO Bank 3 Interrupt
46
GPIO_B4INT
GPIO Bank 4 Interrupt
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Table 12-1. AINTC System Interrupt Assignments (continued)
Event
Interrupt Name
Source
47
GPIO_B5INT
GPIO Bank 5 Interrupt
48
GPIO_B6INT
GPIO Bank 6 Interrupt
49
GPIO_B7INT
GPIO Bank 7 Interrupt
50
GPIO_B8INT
GPIO Bank 8 Interrupt
51
IIC1_INT
I2C1 Interrupt
52
—
Reserved
53
UART_INT1
UART1 Interrupt
54
MCASP_INT
McASP0 Combined RX/TX Interrupt
55
PSC1_ALLINT
PSC1 Interrupt
56
SPI1_INT
SPI1 Interrupt
57
—
Reserved
58
USB0_INT
USB0 (USB2.0) Interrupt
—
Reserved
61
UART2_INT
UART2 Interrupt
62
—
Reserved
63
EHRPWM0
HiResTimer / PWM0 Interrupt
64
EHRPWM0TZ
HiResTimer / PWM0 Trip Zone Interrupt
65
EHRPWM1
HiResTimer / PWM1 Interrupt
66
EHRPWM1TZ
HiResTimer / PWM1 Trip Zone Interrupt
67
—
Reserved
68
T64P2_ALL
Timer64P2 Combined Interrupt (TINT12 and TINT34)
69
ECAP0
eCAP0 Interrupt
70
ECAP1
eCAP1 Interrupt
71
ECAP2
eCAP2 Interrupt
72
MMCSD1_INT0
MMCSD1 MMC/SD Interrupt
73
MMCSD1_INT1
MMCSD1 SDIO Interrupt
74
T64P2_CMPINT0
Timer64P2 - Compare Interrupt 0
75
T64P2_CMPINT1
Timer64P2 - Compare Interrupt 1
76
T64P2_CMPINT2
Timer64P2 - Compare Interrupt 2
77
T64P2_CMPINT3
Timer64P2 - Compare Interrupt 3
78
T64P2_CMPINT4
Timer64P2 - Compare Interrupt 4
79
T64P2_CMPINT5
Timer64P2 - Compare Interrupt 5
80
T64P2_CMPINT6
Timer64P2 - Compare Interrupt 6
81
T64P2_CMPINT7
Timer64P2 - Compare Interrupt 7
82
T64P3_CMPINT0
Timer64P3 - Compare Interrupt 0
83
T64P3_CMPINT1
Timer64P3 - Compare Interrupt 1
84
T64P3_CMPINT2
Timer64P3 - Compare Interrupt 2
85
T64P3_CMPINT3
Timer64P3 - Compare Interrupt 3
86
T64P3_CMPINT4
Timer64P3 - Compare Interrupt 4
87
T64P3_CMPINT5
Timer64P3 - Compare Interrupt 5
88
T64P3_CMPINT6
Timer64P3 - Compare Interrupt 6
89
T64P3_CMPINT7
Timer64P3 - Compare Interrupt 7
90
ARMCLKSTOPREQ
PSC0 Interrupt
—
Reserved
93
EDMA3_1_CC0_INT0
EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
94
EDMA3_1_CC0_ERRINT
EDMA3_1 Channel Controller 0 Error Interrupt
95
EDMA3_1_TC0_ERRINT
EDMA3_1 Transfer Controller 0 Error Interrupt
59-60
91-92
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Table 12-1. AINTC System Interrupt Assignments (continued)
Event
Interrupt Name
Source
96
T64P3_ALL
Timer64P3 Combined Interrupt (TINT12 and TINT34)
97
MCBSP0_RINT
McBSP0 Receive Interrupt
98
MCBSP0_XINT
McBSP0 Transmit Interrupt
99
MCBSP1_RINT
McBSP1 Receive Interrupt
100
MCBSP1_XINT
McBSP1 Transmit Interrupt
12.3 AINTC Methodology
The AINTC module controls the system interrupt mapping to the host interrupt interface. System interrupts
are generated by the device peripherals. The AINTC receives the system interrupts and maps them to
internal channels. The channels are used to combine and prioritize system interrupts. These channels are
then mapped onto the host interface that is typically a smaller number of host interrupts or a vector input.
Interrupts from system side are active high in polarity. Also, they are pulse type of interrupts.
The AINTC encompasses many functions to process the system interrupts and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, vectorization, debug, and host interfacing. Figure 12-2 illustrates the flow of system interrupts
through the functions to the host. The following subsections describe each part of the flow.
Figure 12-2. Flow of System Interrupts to Host
Status
Enabling
Processing
System
Interrupts
Prioritization
Channel
Mapping
Vectorization
Host
Interfacing
Host Interrupts
Host Int
Mapping
12.3.1 Interrupt Processing
The interrupt processing block does the following tasks:
• Synchronization of slower and asynchronous interrupts
• Conversion of polarity to active high
• Conversion of interrupt type to pulse interrupts
After the processing block, all interrupts will be active-high pulses.
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12.3.2 Interrupt Enabling
The AINTC interrupt enable system allows individual interrupts to be enabled or disabled. Use the
following sequence to enable interrupts:
1. Enable global host interrupts. All host interrupts are enabled by setting the ENABLE bit in the global
enable register (GER). Individual host interrupts are enabled or disabled from their individual enables
and are not overridden by the global enable.
2. Enable host interrupt lines. Host interrupt lines (FIQ and IRQ) can be enabled through one of two
methods:
(a) Set the desired mapped bit(s) in the host interrupt enable register (HIER), or
(b) Write the host interrupt index (0-1) to the host interrupt enable indexed set register (HIEISR) for
every interrupt line to enable.
3. Enable system interrupts. System interrupts can be individually enabled through one of two methods:
(a) Set the desired mapped bit(s) in the system interrupt enable set registers (ESR1-ESR4), or
(b) Write the system interrupt index (0-100) to the system interrupt enable indexed set register (EISR)
for every system interrupt to enable.
12.3.3 Interrupt Status Checking
The next stage is to capture which system interrupts are pending. There are two kinds of pending status:
raw status and enabled status. Raw status is the pending status of the system interrupt without regards to
the enable bit for the system interrupt. Enabled status is the pending status of the system interrupts with
the enable bits active. When the enable bit is inactive, the enabled status will always be inactive.
The enabled status of system interrupts is captured in system interrupt status enabled/clear registers
(SECR1-SECR4). Status of system interrupt 'N' is indicated by the Nth bit of SECR1-SECR4. Since there
exists 101 system interrupts, four 32-bit registers are used to capture the enabled status of interrupts.
The pending status reflects whether the system interrupt occurred since the last time the status register bit
was cleared. Each bit in the status register is individually clearable.
12.3.4 Interrupt Channel Mapping
The AINTC has 32 internal channels to which enabled system interrupts can be mapped. Higher priority
interrupts should be mapped to channels 0 and 1. Other interrupts can be mapped to any of the channels
from 2 to 31. Channel 0 has highest priority and channel 31 has the lowest priority. Channels 0 and 1 are
connected to FIQ ARM interrupt. Channels 2 to 31 are connected to IRQ ARM interrupt. Channels are
used to group the system interrupts into a smaller number of priorities that can be given to a host interface
with a very small number of interrupt inputs. When multiple system interrupts are mapped to the same
channel their interrupts are ORed together so that when either is active the output is active.
The channel map registers (CMRm) define the channel for each system interrupt. There is one register
per 4 system interrupts; therefore, there are 26 channel map registers (CMR0-CMR25) for a system of
101 interrupts. Channel for each system interrupt can be set using these registers.
12.3.5 Host Interrupt Mapping Interrupts
The Host is ARM9, which has two lines: FIQ and IRQ. The 32 channels from the AINTC are mapped to
these two lines. The AINTC has a fixed host interrupt mapping scheme. Channels 0 and 1 are mapped to
FIQ and channels 2-31 are mapped to IRQ. Thus, system interrupts mapped to channels 0 and 1 are
propagated as FIQ to the host and system interrupts mapped to channels 2-31 are propagated as IRQ to
the host. When multiple channels are mapped to the same host interrupt, then prioritization is done to
select which interrupt is in the highest-priority channel and which should be sent first to the host.
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12.3.6 Interrupt Prioritization
The next stage of the AINTC is prioritization. Since multiple interrupts feed into a single channel and
multiple channels feed into a single host interrupt, it is necessary to prioritize between all the system
interrupts/channels to decide on a single system interrupt to handle. The AINTC provides hardware to
perform this prioritization with a given scheme so that software does not have to do this. There are two
levels of prioritizations:
1. The first level of prioritization is between the active channels for a host interrupt. Channel 0 has the
highest priority and channel 31 has the lowest. So the first level of prioritization picks the lowest
numbered active channel.
2. The second level of prioritization is between the active system interrupts for the prioritized channel.
The system interrupt in vector position 0 has the highest priority and system interrupt 100 has the
lowest priority. So the second level of prioritization picks the lowest vector position active system
interrupt.
The prioritized system interrupt for each host interrupt line (FIQ and IRQ) can be obtained from the host
interrupt prioritized index registers (HIPIR1 and HIPIR2). The host interrupt prioritized index register
values update dynamically as interrupts arrive at AINTC so care should be taken to avoid register race
conditions.
The AINTC features a prioritization hold mode that is intended to prevent race conditions while servicing
interrupts. This mode is enabled by setting the priority hold mode (PRHOLDMODE) bit in the control
register (CR). When enabled, a read of either the host interrupt prioritized index register (HIPIRn) or the
host interrupt prioritized vector register (HIPVRn) will freeze both the HIPIRn and HIPVRn values for the
respective host interrupt n. The values are frozen until one of the following actions is taken to release the
registers:
1. Write to the host interrupt prioritized index register (HIPIRn)
2. Write to the host interrupt prioritized vector register (HIPVRn)
3. Write-set bit n of the host interrupt enable register (HIER)
4. Write-set the active interrupt index to the host interrupt enable index set register (HIEISR)
5. Write-clear the active interrupt index to the host interrupt enable index clear register (HIEICR)
12.3.7 Interrupt Nesting
If interrupt service routines (ISRs) consume a large number of CPU cycles and may delay the servicing of
other interrupts, the AINTC can perform a nesting function in its prioritization. Nesting is a method of
disabling certain interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those
desired interrupts can trigger to the host while it is servicing the current interrupt. The typical usage is to
nest on the current interrupt and disable all interrupts of the same or lower priority (or channel). Then the
host will only be interrupted from a higher priority interrupt.
Nesting is available in 1 of 3 methods selectable by the NESTMODE bit in the control register (CR):
1. Nesting for all host interrupts, based on channel priority: When an interrupt is taken, the nesting level is
set to its channel priority. From then, that channel priority and all lower priority channels will be
disabled from generating host interrupts and only higher priority channels are allowed. When the
interrupt is completely serviced, the nesting level is returned to its original value. When there is no
interrupt being serviced, there are no channels disabled due to nesting. The global nesting level
register (GNLR) allows the checking and setting of the global nesting level across all host interrupts.
The nesting level is the channel (and all of lower priority channels) that are nested out because of a
current interrupt.
2. Nesting for individual host interrupts, based on channel priority: Always nest based on channel priority
for each host interrupt individually. When an interrupt is taken on a host interrupt, then, the nesting
level is set to its channel priority for just that host interrupt, and other host interrupts do not have their
nesting affected. Then for that host interrupt, equal or lower priority channels will not interrupt the host
but may on other host interrupts if programmed. When the interrupt is completely serviced the nesting
level for the host interrupt is returned to its original value. The host interrupt nesting level registers
(HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The nesting level
controls which channel and lower priority channels are nested. There is one register per host interrupt.
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3. Software manually performs the nesting of interrupts. When an interrupt is taken, the software will
disable all the host interrupts, manually update the enables for any or all the system interrupts, and
then re-enable all the host interrupts. This now allows only the system interrupts that are still enabled
to trigger to the host. When the interrupt is completely serviced the software must reverse the changes
to re-enable the nested out system interrupts. This method requires the most software interaction but
gives the most flexibility if simple channel based nesting mechanisms are not adequate.
The recommended approach is the automatic host interrupt nesting method (second method). Because
higher priority interrupts can preempt lower priority interrupts in this method, a software stack is used to
keep track of nest priorities. The base stack value should be initialized to the default nest priority of the
application. Take the following steps within the ARM hardware interrupt service routine to handle interrupts
using host interrupt priority nesting:
1. Disable the ARM hardware interrupt.
2. Clear the OVERRIDE bit in the host interrupt nesting level register n (HINLRn) to expose the priority
level of the active interrupt.
3. Push the active (or desired) interrupt priority value into the nest priority stack.
4. Write the active (or desired) priority level into HINLRn by setting the OVERRIDE bit.
5. Calculate and store the ISR address for the active interrupt. Unfreeze the host interrupt prioritized
index register n (HIPIRn) and the host interrupt prioritized vector register n (HIPVRn), if the
PRHOLDMODE bit in the control register (CR) is set.
6. Clear the system interrupt status by setting the appropriate bit in the system interrupt status
enabled/clear register n (SECRn) or by writing the appropriate index to the system interrupt status
indexed clear register (SICR).
7. Acknowledge and enable the ARM hardware interrupt.
8. Execute the ISR at the address stored from step 5. During this step, interrupts enabled by the new
nest priority level will be able to preempt the ISR.
9. Disable the ARM hardware interrupt.
10. Discard the most recent priority level in the nest priority stack and restore the previous priority level to
HINLRn by setting the OVERRIDE bit.
11. Enable the ARM hardware interrupt.
12.3.8 Interrupt Vectorization
The next stage of the AINTC is vectorization. Vectorization is an advanced feature that allows the host to
receive an interrupt service routine (ISR) address in addition to just the interrupt status. Without
vectorization the host would receive the interrupt and enter a general ISR that gets the prioritized system
interrupt to service from the AINTC, looks up the specific ISR address for that system interrupt, and then
jumps to that address. With vectorization the host can read a register that has the ISR address already
calculated and jump to that address immediately.
Vectorization uses a base and universal size where all the ISR code is placed in a contiguous memory
region with each ISR code a standard size. For this calculation, the vector base register (VBR) is
programmed by software to hold the base address of all the ISR code and the vector size register (VSR)
is programmed for the size in words between ISR code for each system interrupt. The index number of
each system interrupt is used to calculate the final offset. The specific system interrupt ISR address is
then calculated as:
ISR address = base + (index × size)
There is also a special case when there is no interrupt pending and then the ISR address is the ISR Null
address. This is in case the vector address is executed when there is no pending interrupt so that a Null
handler can be in place to just return from the interrupt. The vector null address register (VNR) holds the
address of the ISR null address. When there is a pending interrupt then the ISR address is calculated as
exact base + offset for that interrupt number.
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12.3.9 Interrupt Status Clearing
After servicing the interrupt (after execution of the ISR), interrupt status is to be cleared. If a system
interrupt status is not cleared, then another host interrupt may not be triggered or another host interrupt
may be triggered incorrectly. For clearing the status of an interrupt, whose interrupt number is N, write a 1
to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR4). System
interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear
register (SICR).
12.3.10 Interrupt Disabling
At any time, if any interrupt is not to be propagated to the host, then that interrupt should be disabled. For
disabling an interrupt whose interrupt number is N, write a 1 to the Nth bit in the system interrupt enable
clear registers (ECR1-ECR4). System interrupt N can also be disabled by writing the value N in the
system interrupt enable indexed clear register (EICR).
12.4 AINTC Registers
Table 12-2 lists the memory-mapped registers for the AINTC.
Table 12-2. ARM Interrupt Controller (AINTC) Registers
Address
Acronym
Register Description
Section
FFFE E000h
REVID
Revision Identification Register
Section 12.4.1
FFFE E004h
CR
Control Register
Section 12.4.2
FFFE E010h
GER
Global Enable Register
Section 12.4.3
FFFE E01Ch
GNLR
Global Nesting Level Register
Section 12.4.4
FFFE E020h
SISR
System Interrupt Status Indexed Set Register
Section 12.4.5
FFFE E024h
SICR
System Interrupt Status Indexed Clear Register
Section 12.4.6
FFFE E028h
EISR
System Interrupt Enable Indexed Set Register
Section 12.4.7
FFFE E02Ch
EICR
System Interrupt Enable Indexed Clear Register
Section 12.4.8
FFFE E034h
HIEISR
Host Interrupt Enable Indexed Set Register
Section 12.4.9
FFFE E038h
HIEICR
Host Interrupt Enable Indexed Clear Register
Section 12.4.10
FFFE E050h
VBR
Vector Base Register
Section 12.4.11
FFFE E054h
VSR
Vector Size Register
Section 12.4.12
FFFE E058h
VNR
Vector Null Register
Section 12.4.13
FFFE E080h
GPIR
Global Prioritized Index Register
Section 12.4.14
FFFE E084h
GPVR
Global Prioritized Vector Register
Section 12.4.15
FFFE E200h
SRSR1
System Interrupt Status Raw/Set Register 1
Section 12.4.16
FFFE E204h
SRSR2
System Interrupt Status Raw/Set Register 2
Section 12.4.17
FFFE E208h
SRSR3
System Interrupt Status Raw/Set Register 3
Section 12.4.18
FFFE E20Ch
SRSR4
System Interrupt Status Raw/Set Register 4
Section 12.4.19
FFFE E280h
SECR1
System Interrupt Status Enabled/Clear Register 1
Section 12.4.20
FFFE E284h
SECR2
System Interrupt Status Enabled/Clear Register 2
Section 12.4.21
FFFE E288h
SECR3
System Interrupt Status Enabled/Clear Register 3
Section 12.4.22
FFFE E28Ch
SECR4
System Interrupt Status Enabled/Clear Register 4
Section 12.4.23
FFFE E300h
ESR1
System Interrupt Enable Set Register 1
Section 12.4.24
FFFE E304h
ESR2
System Interrupt Enable Set Register 2
Section 12.4.25
FFFE E308h
ESR3
System Interrupt Enable Set Register 3
Section 12.4.26
FFFE E30Ch
ESR4
System Interrupt Enable Set Register 4
Section 12.4.27
FFFE E380h
ECR1
System Interrupt Enable Clear Register 1
Section 12.4.28
FFFE E384h
ECR2
System Interrupt Enable Clear Register 2
Section 12.4.29
FFFE E388h
ECR3
System Interrupt Enable Clear Register 3
Section 12.4.30
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Table 12-2. ARM Interrupt Controller (AINTC) Registers (continued)
Address
Acronym
Register Description
FFFE E38Ch
ECR4
System Interrupt Enable Clear Register 4
Section 12.4.31
Section
FFFE E400h–
FFFE E464h
CMR0-CMR25
Channel Map Registers 0-25
Section 12.4.32
FFFE E900h
HIPIR1
Host Interrupt Prioritized Index Register 1
Section 12.4.33
FFFE E904h
HIPIR2
Host Interrupt Prioritized Index Register 2
Section 12.4.34
FFFE F100h
HINLR1
Host Interrupt Nesting Level Register 1
Section 12.4.35
FFFE F104h
HINLR2
Host Interrupt Nesting Level Register 2
Section 12.4.36
FFFE F500h
HIER
Host Interrupt Enable Register
Section 12.4.37
FFFE F600h
HIPVR1
Host Interrupt Prioritized Vector Register 1
Section 12.4.38
FFFE F604h
HIPVR2
Host Interrupt Prioritized Vector Register 2
Section 12.4.39
12.4.1 Revision Identification Register (REVID)
The revision identification register (REVID) is shown in Figure 23-35 and described in Table 12-3.
Figure 12-3. Revision Identification Register (REVID)
31
0
REV
R-4E82 A900h
LEGEND: R = Read only; -n = value after reset
Table 12-3. Revision Identification Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4E82 A900h
294
Description
Revision ID of the AINTC.
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12.4.2 Control Register (CR)
The control register (CR) holds global control parameters. The CR is shown in Figure 12-4 and described
in Table 12-4.
Figure 12-4. Control Register (CR)
31
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
PRHOLDMODE
NESTMODE
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-4. Control Register (CR) Field Descriptions
Bit
31-5
4
3-2
1-0
Field
Value
Reserved
0
PRHOLDMODE
NESTMODE
Description
Reserved
Enables priority holding mode.
0
No priority holding. Prioritized MMRs will continually update.
1
Priority holding enabled. Prioritized Index and Vector Address MMRs will hold their value after the
first is read. See Section 12.3.6 for details.
0-3h
Reserved
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Nesting mode.
0
No nesting
1h
Automatic individual nesting (per host interrupt)
2h
Automatic global nesting (over all host interrupts)
3h
Manual nesting
0
Reserved
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12.4.3 Global Enable Register (GER)
The global enable register (GER) enables all the host interrupts. Individual host interrupts are still enabled
or disabled from their individual enables and are not overridden by the global enable. The GER is shown
in Figure 12-5 and described in Table 12-5.
Figure 12-5. Global Enable Register (GER)
31
16
Reserved
R-0
15
1
0
Reserved
ENABLE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-5. Global Enable Register (GER) Field Descriptions
Bit
Field
Value
31-1
Reserved
0
0
ENABLE
0-1
Description
Reserved
The current global enable value when read. Writes set the global enable.
12.4.4 Global Nesting Level Register (GNLR)
The global nesting level register (GNLR) allows the checking and setting of the global nesting level across
all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of
lower priority) that are nested out because of a current interrupt. The GNLR is shown in Figure 12-6 and
described in Table 12-6.
Figure 12-6. Global Nesting Level Register (GNLR)
31
30
16
OVERRIDE
Reserved
R/W-0
R-0
15
9
8
0
Reserved
NESTLVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-6. Global Nesting Level Register (GNLR) Field Descriptions
Bit
Field
31
OVERRIDE
Value
0-1
30-9
Reserved
0
8-0
NESTLVL
0-1FFh
296
Description
Always read as 0. Writes of 1 override the automatic nesting and set the NESTLVL to the written
data.
Reserved
The current global nesting level (highest channel that is nested). Writes set the nesting level. In
autonesting mode this value is updated internally, unless the auto_override bit is set.
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12.4.5 System Interrupt Status Indexed Set Register (SISR)
The system interrupt status indexed set register (SISR) allows setting the status of an interrupt. The
interrupt to set is the INDEX value written. This sets the Raw Status Register bit of the given INDEX. The
SISR is shown in Figure 12-7 and described in Table 12-7.
Figure 12-7. System Interrupt Status Indexed Set Register (SISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-7. System Interrupt Status Indexed Set Register (SISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the status of the interrupt given in the INDEX value. Reads return 0.
12.4.6 System Interrupt Status Indexed Clear Register (SICR)
The system interrupt status indexed clear register (SICR) allows clearing the status of an interrupt. The
interrupt to clear is the INDEX value written. This clears the Raw Status Register bit of the given INDEX.
The SICR is shown in Figure 12-8 and described in Table 12-8.
Figure 12-8. System Interrupt Status Indexed Clear Register (SICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-8. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
Value
0
0-7Fh
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Description
Reserved
Writes clear the status of the interrupt given in the INDEX value. Reads return 0.
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12.4.7 System Interrupt Enable Indexed Set Register (EISR)
The system interrupt enable indexed set register (EISR) allows enabling an interrupt. The interrupt to
enable is the INDEX value written. This sets the Enable Register bit of the given INDEX. The EISR is
shown in Figure 12-9 and described in Table 12-9.
Figure 12-9. System Interrupt Enable Indexed Set Register (EISR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions
Bit
Field
Value
31-7
Reserved
6-0
INDEX
Description
0
Reserved
0-7Fh
Writes set the enable of the interrupt given in the INDEX value. Reads return 0.
12.4.8 System Interrupt Enable Indexed Clear Register (EICR)
The system interrupt enable indexed clear register (EICR) allows disabling an interrupt. The interrupt to
disable is the INDEX value written. This clears the Enable Register bit of the given INDEX. The EICR is
shown in Figure 12-10 and described in Table 12-10.
Figure 12-10. System Interrupt Enable Indexed Clear Register (EICR)
31
16
Reserved
R-0
15
7
6
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions
Bit
Field
31-7
Reserved
6-0
INDEX
298
Value
0
0-7Fh
Description
Reserved
Writes clear the enable of the interrupt given in the INDEX value. Reads return 0.
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12.4.9 Host Interrupt Enable Indexed Set Register (HIEISR)
The host interrupt enable indexed set register (HIEISR) allows enabling a host interrupt output. The host
interrupt to enable is the INDEX value written. This enables the host interrupt output or triggers the output
again if already enabled. The HEISR is shown in Figure 12-11 and described in Table 12-11.
Figure 12-11. Host Interrupt Enable Indexed Set Register (HEISR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions
Bit
31-1
0
Field
Value
Reserved
0
INDEX
Description
Reserved
Writes set the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 sets FIQ.
1
Writing a 1 sets IRQ.
12.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR)
The host interrupt enable indexed clear register (HIEICR) allows disabling a host interrupt output. The host
interrupt to disable is the INDEX value written. This disables the host interrupt output. The HIEICR is
shown in Figure 12-12 and described in Table 12-12.
Figure 12-12. Host Interrupt Enable Indexed Clear Register (HIEICR)
31
16
Reserved
R-0
15
1
0
Reserved
INDEX
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions
Bit
31-1
0
Field
Reserved
Value
0
INDEX
Description
Reserved
Writes clear the enable of the host interrupt given in the INDEX value. Reads return 0.
0
Writing a 0 clears FIQ.
1
Writing a 1 clears IRQ.
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12.4.11 Vector Base Register (VBR)
The vector base register (VBR) holds the base address of the ISR vector addresses. The VBR is shown in
Figure 12-13 and described in Table 12-13.
Figure 12-13. Vector Base Register (VBR)
31
0
BASE
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-13. Vector Base Register (VBR) Field Descriptions
Bit
Field
Value
31-0
BASE
0-FFFF FFFFh
Description
ISR Base Address.
12.4.12 Vector Size Register (VSR)
The vector size register (VSR) holds the sizes of the individual ISR routines in the vector table. This is
only the sizes to space the calculated vector addresses for the initial ISR targets (the ISR targets could
branch off to the full ISR routines). The VSR is shown in Figure 12-14 and described in Table 12-14.
NOTE: The VSR must be configured even if the desired value is equal to the default value.
Figure 12-14. Vector Size Register (VSR)
31
16
Reserved
R-0
15
8
7
0
Reserved
SIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-14. Vector Size Register (VSR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
SIZE
Value
0
0-FFh
Description
Reserved
Size of ISR address spaces.
0
4 bytes
1h
8 bytes
2h
16 bytes
3h
32 bytes
4h
64 bytes
5h-FFh ...
300
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12.4.13 Vector Null Register (VNR)
The vector null register (VNR) holds the address of the ISR null address that handles no pending
interrupts (if accidentally branched to when no interrupts are pending). The VNR is shown in Figure 12-15
and described in Table 12-15.
Figure 12-15. Vector Null Register (VNR)
31
0
NULL
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-15. Vector Null Register (VNR) Field Descriptions
Bit
Field
Value
31-0
NULL
0-FFFF FFFFh
Description
ISR Null Address.
12.4.14 Global Prioritized Index Register (GPIR)
The global prioritized index register (GPIR) shows the interrupt number of the highest priority interrupt
pending across all the host interrupts. The GPIR is shown in Figure 12-16 and described in Table 12-16.
Figure 12-16. Global Prioritized Index Register (GPIR)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-16. Global Prioritized Index Register (GPIR) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
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Description
No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are
pending.
Reserved
The currently highest priority interrupt index pending across all the host interrupts.
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12.4.15 Global Prioritized Vector Register (GPVR)
The global prioritized vector register (GPVR) shows the interrupt vector address of the highest priority
interrupt pending across all the host interrupts. The GPVR is shown in Figure 12-17 and described in
Table 12-17.
Figure 12-17. Global Prioritized Vector Register (GPVR)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-17. Global Prioritized Vector Register (GPVR) Field Descriptions
Bit
Field
Value
Description
31-0
ADDR
0-FFFF FFFFh
The currently highest priority interrupts vector address across all the host interrupts.
12.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1)
The system interrupt status raw/set register 1 (SRSR1) shows the pending enabled status of the system
interrupts 0 to 31. Software can write to SRSR1 to set a system interrupt without a hardware trigger. There
is one bit per system interrupt. The SRSR1 is shown in Figure 12-18 and described in Table 12-18.
Figure 12-18. System Interrupt Status Raw/Set Register 1 (SRSR1)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions
Bit
31-0
302
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n.
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12.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2)
The system interrupt status raw/set register 2 (SRSR2) shows the pending enabled status of the system
interrupts 32 to 63. Software can write to SRSR2 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR2 is shown in Figure 12-19 and described in Table 12-19.
Figure 12-19. System Interrupt Status Raw/Set Register 2 (SRSR2)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
Description
System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 32.
12.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3)
The system interrupt status raw/set register 3 (SRSR3) shows the pending enabled status of the system
interrupts 64 to 95. Software can write to SRSR3 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR3 is shown in Figure 12-20 and described in Table 12-20.
Figure 12-20. System Interrupt Status Raw/Set Register 3 (SRSR3)
31
0
RAW_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions
Bit
31-0
Field
Value
RAW_STATUS[n]
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Description
System interrupt raw status and setting of the system interrupts 64 to 95. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 64.
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12.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4)
The system interrupt status raw/set register 4 (SRSR4) shows the pending enabled status of the system
interrupts 96 to 100. Software can write to SRSR4 to set a system interrupt without a hardware trigger.
There is one bit per system interrupt. The SRSR4 is shown in Figure 12-21 and described in Table 12-21.
Figure 12-21. System Interrupt Status Raw/Set Register 4 (SRSR4)
31
5
4
0
Reserved
RAW_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
RAW_STATUS[n]
Description
0
Reserved
System interrupt raw status and setting of the system interrupts 96 to 100. Reads return the raw
status.
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the status of the system interrupt n + 96.
12.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1)
The system interrupt status enabled/clear register 1 (SECR1) shows the pending enabled status of the
system interrupts 0 to 31. Software can write to SECR1 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR1 is
shown in Figure 12-22 and described in Table 12-22.
Figure 12-22. System Interrupt Status Enabled/Clear Register 1 (SECR1)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions
Bit
31-0
304
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n.
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12.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2)
The system interrupt status enabled/clear register 2 (SECR2) shows the pending enabled status of the
system interrupts 32 to 63. Software can write to SECR2 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR2 is
shown in Figure 12-23 and described in Table 12-23.
Figure 12-23. System Interrupt Status Enabled/Clear Register 2 (SECR2)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
Description
System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 32.
12.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3)
The system interrupt status enabled/clear register 3 (SECR3) shows the pending enabled status of the
system interrupts 64 to 95. Software can write to SECR3 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR3 is
shown in Figure 12-24 and described in Table 12-24.
Figure 12-24. System Interrupt Status Enabled/Clear Register 3 (SECR3)
31
0
ENBL_STATUS[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions
Bit
31-0
Field
Value
ENBL_STATUS[n]
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Description
System interrupt enabled status and clearing of the system interrupts 64 to 95. Reads return the
enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 64.
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12.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4)
The system interrupt status enabled/clear register 4 (SECR4) shows the pending enabled status of the
system interrupts 96 to 100. Software can write to SECR4 to clear a system interrupt after it has been
serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or
another host interrupt may be triggered incorrectly. There is one bit per system interrupt. The SECR4 is
shown in Figure 12-25 and described in Table 12-25.
Figure 12-25. System Interrupt Status Enabled/Clear Register 4 (SECR4)
31
5
4
0
Reserved
ENBL_STATUS[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
0
4-0
ENBL_STATUS[n]
Description
Reserved
System interrupt enabled status and clearing of the system interrupts 96 to 100. Reads return
the enabled status (before enabling with the Enable Registers).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the status of the system interrupt n + 96.
12.4.24 System Interrupt Enable Set Register 1 (ESR1)
The system interrupt enable set register 1 (ESR1) enables system interrupts 0 to 31 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR1 is shown in Figure 12-26 and described in Table 12-26.
Figure 12-26. System Interrupt Enable Set Register 1 (ESR1)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions
Bit
31-0
306
Field
Value
ENABLE[n]
Description
System interrupt 0 to 31 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n.
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12.4.25 System Interrupt Enable Set Register 2 (ESR2)
The system interrupt enable set register 2 (ESR2) enables system interrupts 32 to 63 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR2 is shown in Figure 12-27 and described in Table 12-27.
Figure 12-27. System Interrupt Enable Set Register 2 (ESR2)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 32 to 63 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 32.
12.4.26 System Interrupt Enable Set Register 3 (ESR3)
The system interrupt enable set register 3 (ESR3) enables system interrupts 64 to 95 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR3 is shown in Figure 12-28 and described in Table 12-28.
Figure 12-28. System Interrupt Enable Set Register 3 (ESR3)
31
0
ENABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions
Bit
31-0
Field
Value
ENABLE[n]
Description
System interrupt 64 to 95 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 64.
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12.4.27 System Interrupt Enable Set Register 4 (ESR4)
The system interrupt enable set register 4 (ESR4) enables system interrupts 96 to 100 to trigger outputs.
System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. The
ESR4 is shown in Figure 12-29 and described in Table 12-29.
Figure 12-29. System Interrupt Enable Set Register 4 (ESR4)
31
5
4
0
Reserved
ENABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions
Bit
Field
Value
31-5
Reserved
4-0
ENABLE[n]
0
Description
Reserved
System interrupt 96 to 100 enable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to set the enable for system interrupt n + 96.
12.4.28 System Interrupt Enable Clear Register 1 (ECR1)
The system interrupt enable clear register 1 (ECR1) disables system interrupts 0 to 31 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR1 is shown in Figure 12-30 and described in Table 12-30.
Figure 12-30. System Interrupt Enable Clear Register 1 (ECR1)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions
Bit
31-0
308
Field
Value
DISABLE[n]
Description
System interrupt 0 to 31 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n.
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12.4.29 System Interrupt Enable Clear Register 2 (ECR2)
The system interrupt enable clear register 2 (ECR2) disables system interrupts 32 to 63 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR2 is shown in Figure 12-31 and described in Table 12-31.
Figure 12-31. System Interrupt Enable Clear Register 2 (ECR2)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions
Bit
31-0
Field
Value
DISABLE[n]
Description
System interrupt 32 to 63 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 32.
12.4.30 System Interrupt Enable Clear Register 3 (ECR3)
The system interrupt enable clear register 3 (ECR3) disables system interrupts 64 to 95 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR3 is shown in Figure 12-32 and described in Table 12-32.
Figure 12-32. System Interrupt Enable Clear Register 3 (ECR3)
31
0
DISABLE[n]
W-0
LEGEND: W = Write only; -n = value after reset
Table 12-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions
Bit
27-0
Field
Value
DISABLE[n]
Description
System interrupt 64 to 95 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 64.
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12.4.31 System Interrupt Enable Clear Register 4 (ECR4)
The system interrupt enable clear register 4 (ECR4) disables system interrupts 96 to 100 to map to
channels. System interrupts that are not enabled do not interrupt the host. There is one bit per system
interrupt. The ECR4 is shown in Figure 12-33 and described in Table 12-33.
Figure 12-33. System Interrupt Enable Clear Register 4 (ECR4)
31
5
4
0
Reserved
DISABLE[n]
R-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 12-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions
Bit
Field
31-5
Reserved
4-0
DISABLE[n]
Value
0
Description
Reserved
System interrupt 96 to 100 disable. Read returns the enable value (0 = disabled, 1 = enabled).
0
Writing a 0 has no effect.
1
Write a 1 in bit position [n] to clear the enable for system interrupt n + 96.
12.4.32 Channel Map Registers (CMR0-CMR25)
The channel map registers (CMR0-CMR25) define the channel for each system interrupt. There is one
register per 4 system interrupts. The CMRn is shown in Figure 12-34 and described in Table 12-34.
Figure 12-34. Channel Map Registers (CMRn)
31
24
23
16
CHNL_NPLUS3
CHNL_NPLUS2
R/W-0
R/W-0
15
8
7
0
CHNL_NPLUS1
CHNL_N
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-34. Channel Map Registers (CMRn) Field Descriptions
Bit
Field
Value
Description
31-24
CHNL_NPLUS3
0-FFh
Sets the host interrupt for channel N + 3.
23-16
CHNL_NPLUS2
0-FFh
Sets the host interrupt for channel N + 2.
15-8
CHNL_NPLUS1
0-FFh
Sets the host interrupt for channel N + 1.
7-0
CHNL_N
0-FFh
Sets the channel for the system interrupt N. (N ranges from 0 to 100).
310
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12.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1)
The host interrupt prioritized index register 1 (HIPIR1) shows the highest priority current pending interrupt
for the FIQ interrupt. The HIPIR1 is shown in Figure 12-35 and described in Table 12-35.
Figure 12-35. Host Interrupt Prioritized Index Register 1 (HIPIR1)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for FIQ host interrupt.
12.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2)
The host interrupt prioritized index register 2 (HIPIR2) shows the highest priority current pending interrupt
for the IRQ interrupt. The HIPIR2 is shown in Figure 12-36 and described in Table 12-36.
Figure 12-36. Host Interrupt Prioritized Index Register 2 (HIPIR2)
31
30
16
NONE
Reserved
R-1
R-0
15
10
9
0
Reserved
PRI_INDX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions
Bit
Field
Value
31
NONE
0-1
30-10
Reserved
0
9-0
PRI_INDX
0-3FFh
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Description
No Interrupt is pending.
Reserved
Interrupt number of the highest priority pending interrupt for IRQ host interrupt.
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12.4.35 Host Interrupt Nesting Level Register 1 (HINLR1)
The host interrupt nesting level register 1 (HINLR1) displays and controls the nesting level for FIQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR1 is
shown in Figure 12-37 and described in Table 12-37.
Figure 12-37. Host Interrupt Nesting Level Register 1 (HINLR1)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 12-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions
Bit
Field
31
OVERRIDE
Value
30-9
Reserved
8-0
NEST_LVL
0-1
0
0-1FFh
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the FIQ host interrupt. Writes set the nesting level for the
FIQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
12.4.36 Host Interrupt Nesting Level Register 2 (HINLR2)
The host interrupt nesting level register 2 (HINLR2) displays and controls the nesting level for IRQ host
interrupt. The nesting level controls which channel and lower priority channels are nested. The HINLR2 is
shown in Figure 12-38 and described in Table 12-38.
Figure 12-38. Host Interrupt Nesting Level Register 2 (HINLR2)
31
30
16
OVERRIDE
Reserved
W-0
R-0
15
9
8
0
Reserved
NEST_LVL
R-0
R/W-100h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 12-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions
Bit
Field
31
OVERRIDE
30-9
Reserved
8-0
NEST_LVL
312
Value
0-1
0
0-1FFh
Description
Reads return 0. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.
Reserved
Reads return the current nesting level for the IRQ host interrupt. Writes set the nesting level for the
IRQ host interrupt. In auto mode the value is updated internally, unless the OVERRIDE is set and
then the write data is used.
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12.4.37 Host Interrupt Enable Register (HIER)
The host interrupt enable register (HIER) enables or disables individual host interrupts (FIQ and IRQ).
These work separately from the global enables. There is one bit per host interrupt. These bits are updated
when writing to the host interrupt enable indexed set register (HIEISR) and the host interrupt disable
indexed clear register (HIDISR). The HIER is shown in Figure 12-39 and described in Table 12-39.
Figure 12-39. Host Interrupt Enable Register (HIER)
31
16
Reserved
R-0
15
1
0
Reserved
2
IRQ
FIQ
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-39. Host Interrupt Enable Register (HIER) Field Descriptions
Bit
31-2
1
0
Field
Reserved
Value
0
IRQ
Description
Reserved
Enable of IRQ
0
IRQ is disabled.
1
IRQ is enabled.
FIQ
Enable of FIQ
0
FIQ is disabled.
1
FIQ is enabled.
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12.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1)
The host interrupt prioritized vector register 1 (HIPVR1) shows the interrupt vector address of the highest
priority interrupt pending for FIQ host interrupt. The HIPVR1 is shown in Figure 12-40 and described in
Table 12-40.
Figure 12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
Description
The currently highest priority interrupt vector address across for the FIQ host interrupt.
12.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2)
The host interrupt prioritized vector register 2 (HIPVR2) shows the interrupt vector address of the highest
priority interrupt pending for IRQ host interrupt. The HIPVR2 is shown in Figure 12-41 and described in
Table 12-41.
Figure 12-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2)
31
0
ADDR
R-0
LEGEND: R = Read only; -n = value after reset
Table 12-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions
Bit
Field
Value
31-0
ADDR
0-FFFF FFFFh
314
Description
The currently highest priority interrupt vector address across for the IRQ host interrupt.
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Chapter 13
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Boot Considerations
Topic
13.1
13.2
...........................................................................................................................
Page
Introduction .................................................................................................... 316
DSP Wake Up .................................................................................................. 317
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13.1 Introduction
This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ARM ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• I2C0/I2C1 boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0/SPI1 boot
– Serial Flash (Master Mode)
– Serial EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0/1/2 boot
– External Host
• MMC/SD0 boot
See Using the OMAP-L132/L138 Bootloader Application Report (SPRAB41) for more details on the ROM
Boot Loader, a list of boot pins used, and the complete list of supported boot modes.
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13.2 DSP Wake Up
Following deassertion of device reset, the DSP intializes the ARM296 so that it can execute the ARM
ROM bootloader. Upon successful wake up, the ARM places the DSP in a reset and clock gated
(SwRstDisable) state that is controlled by the LPSC and the SYSCFG modules.
Perform the following steps to wake up the DSP:
1. Write the truncated DSP boot address vector to the DSP_ISTP_RST_VAL field in the host 1
configuration register (HOST1CFG) of the SYSCFG module. The least-significant bits of the boot
address are fixed at 0.
2. Write a 3h to the NEXT bit in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition (to enable the clocks and all
transitioning from the SwRstDisable state to Enable state).
3. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
4. Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) for
power transition sequence completion. The domain is only safely in the new state after the GOSTAT[1]
bit is cleared to 0.
5. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
6. Write a 1 to the LRST bit in PSC0.MDCTL15 to release the DSP local reset controlled by the PSC
module.
NOTE: Step 6 can also be combined with Step 2. You can write a 103h to the PSC0.MDCTL15 in
Step 2 to release the DSP local reset and transition it from a SwRstDisable to Enable state.
The step to release the DSP reset by the SYSCFG module (Step 3) is only required at
device reset/system reset/warm reset. Disabling/enabling clocks to the DSP module at any
other time can be independently controlled by the PSC module alone. Guidelines to
enable/disable clocks for power management are provided in the Power Management
chapter.
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Chapter 14
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Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of:
• Two programmable real-time units (PRU0 and PRU1) and their associated memories.
• An interrupt controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed
memory-mapped data structures, handling of system events that have tight realtime constraints and
interfacing with systems external to the device.
The PRUSS documentation (peripheral guide) is on the external wiki: Programmable_Realtime_Unit.
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Chapter 15
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DDR2/mDDR Memory Controller
This chapter describes the DDR2/mobile DDR (mDDR) memory controller.
Topic
15.1
15.2
15.3
15.4
...........................................................................................................................
Introduction ....................................................................................................
Architecture ....................................................................................................
Supported Use Cases .......................................................................................
Registers ........................................................................................................
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324
352
357
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15.1 Introduction
15.1.1 Purpose of the Peripheral
The DDR2/mDDR memory controller is used to interface with JESD79D-2 standard compliant DDR2
SDRAM devices and JESD209 standard mobile DDR (mDDR) SDRAM devices. Memories types such as
DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The
DDR2/mDDR memory is the major memory location for program and data storage.
15.1.2 Features
The DDR2/mDDR memory controller supports the following features:
• JESD79D-2 standard compliant DDR2 SDRAM
• JESD209 standard compliant mobile DDR (mDDR)
• Data bus width of 16 bits
• CAS latencies:
– DDR2: 2, 3, 4, and 5
– mDDR: 2 and 3
• Internal banks:
– DDR2: 1, 2, 4, and 8
– mDDR: 1, 2, and 4
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM auto-initialization
• Self-refresh mode
• Partial array self-refresh (for mDDR)
• Power-down mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little-endian mode
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15.1.3 Functional Block Diagram
The DDR2/mDDR memory controller is the main interface to external DDR2/mDDR memory. Figure 15-1
displays the general data paths to on-chip peripherals and external DDR2/mDDR SDRAM.
Master peripherals, EDMA, and the CPU can access the DDR2/mDDR memory controller through the
switched central resource (SCR).
Figure 15-1. Data Paths to DDR2/mDDR Memory Controller
CPU
Master
peripherals
SCR
BUS
DDR2/mDDR
memory
controller
BUS
External
DDR2/mDDR SDRAM
EDMA
15.1.4 Supported Use Case Statement
The DDR2/mDDR memory controller supports JESD79D-2 DDR2 SDRAM memories and the JESD209
mobile DDR (mDDR) SDRAM memories utilizing 16 bits of the DDR2/mDDR memory controller data bus.
See Section 15.3 for more details.
15.1.5 Industry Standard(s) Compliance Statement
The DDR2/mDDR memory controller is compliant with the JESD79D-2 DDR2 SDRAM standard and the
JESD209 mobile DDR (mDDR) standard with the following exception:
• On-Die Termination (ODT). The DDR2/mDDR memory controller does not include any on-die
terminating resistors. Furthermore, the on-die terminating resistors of the DDR2/mDDR SDRAM device
must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground.
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15.2 Architecture
This section describes the architecture of the DDR2/mDDR memory controller as well as how it is
structured and how it works within the context of the system-on-a-chip. The DDR2/mDDR memory
controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such
features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through
programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
The following sections include details on how to interface and properly configure the DDR2/mDDR
memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM
devices. Also, Section 15.3 provides a detailed example of interfacing the DDR2/mDDR memory controller
to a common DDR2/mDDR SDRAM device.
15.2.1 Clock Control
The DDR2/mDDR memory controller receives two input clocks from internal clock sources, VCLK and
2X_CLK (Figure 15-2). VCLK is a divided-down version of the PLL0 clock. 2X_CLK is the PLL1 clock.
2X_CLK should be configured to clock at the frequency of the desired data rate, or stated similarly, it
should operate at twice the frequency of the desired DDR2/mDDR memory clock. DDR_CLK and
DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock
to the DDR2/mDDR SDRAM memory. These two clocks operate at a frequency of 2X_CLK/2.
15.2.1.1 Clock Source
VCLK and 2X_CLK are sourced from two independent PLLs (Figure 15-2). VCLK is sourced from PLL
controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1).
VCLK is clocked at a fixed divider ratio of PLL0. This divider is fixed at 2, meaning VCLK is clocked at a
frequency of PLL0/2.
The clock from PLLC1 is not divided before reaching 2X_CLK. PLLC1 should be configured to supply
2X_CLK at the desired frequency. For example, if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is
desired, then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK.
Figure 15-2. DDR2/mDDR Memory Controller Clock Block Diagram
DDR_CLK
DDR_CLK
DDR2
memory
controller
VCLK
2X_CLK
/1
PLLC1
/2
PLLC0
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15.2.1.2 Clock Configuration
The frequency of 2X_CLK is configured by selecting the appropriate PLL multiplier. The PLL multiplier is
selected by programming registers within PLLC1. The PLLC1 divider ration is fixed at 1. For information
on programming the PLL controllers, see the Phase-Locked Loop Controller (PLLC) chapter. For
information on supported clock frequencies, see the Device Clocking chapter and your device-specific
data manual.
NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the
DDR2/mDDR memory controller from reset.
15.2.1.3 DDR2/mDDR Memory Controller Internal Clock Domains
There are two clock domains within the DDR2/mDDR memory controller. The two clock domains are
driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. The command FIFO, write
FIFO, and read FIFO described in Section 15.2.6 are all on the VCLK domain. From this, VCLK drives the
interface to the peripheral bus.
The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped
registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.
To conserve power within the DDR2/mDDR memory controller, VCLK, MCLK, and 2X_CLK may be
stopped. See Section 15.2.16 for proper clock stop procedures.
15.2.2 Signal Descriptions
The DDR2/mDDR memory controller signals are shown in Figure 15-3 and described in Table 15-1. The
following features are included:
•
•
•
•
•
The maximum data bus is 16-bits wide.
The address bus is 14-bits wide with an additional three bank address pins.
Two differential output clocks driven by internal clock sources.
Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
One chip select signal and one clock enable signal.
Figure 15-3. DDR2/mDDR Memory Controller Signals
DDR_CLK
DDR_CLK
DDR_CKE
DDR2
memory
controller
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_BA[2:0]
DDR_A[13:0]
DDR_D[15:0]
DDR_DQGATE0
DDR_DQGATE1
DDR_VREF
50 Ω
DDR_ZP
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Table 15-1. DDR2/mDDR Memory Controller Signal Descriptions
(1)
Pin
Type
DDR_CLK,
DDR_CLK
O/Z
Clock: Differential clock outputs.
DDR_CKE
O/Z
Clock enable: Active high.
DDR_CS
O/Z
Chip select: Active low.
DDR_WE
O/Z
Write enable strobe: Active low, command output.
DDR_RAS
O/Z
Row address strobe: Active low, command output.
DDR_CAS
O/Z
Column address strobe: Active low, command output.
DDR_DQM[1:0]
O/Z
Data mask: Active high, output mask signal for write data.
DDR_DQS[1:0]
I/O/Z
Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0]
O/Z
Bank select: Output, defining which bank a given command is applied.
DDR_A[13:0]
O/Z
Address: Address bus.
DDR_D[15:0]
I/O/Z
Data: Bi-directional data bus. Input for read data, output for write data.
DDR_DQGATE0
O/Z
Strobe Enable: Active high.
DDR_DQGATE1
I/O/Z
Strobe Enable Delay: Loopback signal for timing adjustment (DQS gating). Route from
DDR_DQGATE0 to DDR device and back to DDR_DQGATE1 with same constraints as used
for DDR clock and data.
DDR_ZP
I/O/Z
Output drive strength reference: Reference output for drive strength calibration of N and P
channel outputs. Tie to ground via 50 ohm .5% tolerance 1/16th watt resistor (49.9 ohm .5%
tolerance is acceptable).
DDR_VREF
pwr
Voltage reference input: Voltage reference input for the SSTL_18 I/O buffers. Note even in
the case of mDDR an external resistor divider connected to this pin is necessary.
(1)
Description
Legend: I = input, O = Output, Z = high impedance, pwr = power
15.2.3 Protocol Description(s)
The DDR2/mDDR memory controller supports the DDR2/mDDR SDRAM commands listed in Table 15-2.
Table 15-3 shows the signal truth table for the DDR2/mDDR SDRAM commands.
Table 15-2. DDR2/mDDR SDRAM Commands
Command
Function
ACTV
Activates the selected bank and row.
DCAB
Precharge all command. Deactivates (precharges) all banks.
DEAC
Precharge single command. Deactivates (precharges) a single bank.
DESEL
Device Deselect.
EMRS
Extended Mode Register set. Allows altering the contents of the mode register.
MRS
Mode register set. Allows altering the contents of the mode register.
NOP
No operation.
Power Down
Power-down mode.
READ
Inputs the starting column address and begins the read operation.
READ with
autoprecharge
Inputs the starting column address and begins the read operation. The read operation is followed by a
precharge.
REFR
Autorefresh cycle.
SLFREFR
Self-refresh mode.
WRT
Inputs the starting column address and begins the write operation.
WRT with
autoprecharge
Inputs the starting column address and begins the write operation. The write operation is followed by a
precharge.
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Table 15-3. Truth Table for DDR2/mDDR SDRAM Commands
DDR2/mDDR
SDRAM:
DDR2/mDDR
memory
controller:
CKE
CS
RAS
CAS
WE
BA[2:0]
A[13:11, 9:0]
A10
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_CKE
Previous
Cycles
Current
Cycle
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA[2:0]
ACTV
H
H
L
L
H
H
Bank
DCAB
H
H
L
L
H
L
X
X
DEAC
H
H
L
L
H
L
Bank
X
MRS
H
H
L
L
L
L
BA
EMRS
H
H
L
L
L
L
BA
READ
H
H
L
H
L
H
BA
Column Address
L
READ with
precharge
H
H
L
H
L
H
BA
Column Address
H
WRT
H
H
L
H
L
L
BA
Column Address
L
WRT with
precharge
H
H
L
H
L
L
BA
Column Address
H
REFR
H
H
L
L
L
H
X
X
X
SLFREFR
entry
H
L
L
L
L
H
X
X
X
SLFREFR
exit
L
H
H
X
X
X
X
X
X
L
H
H
H
X
X
X
NOP
H
X
L
H
H
H
X
X
X
DESEL
H
X
H
X
X
X
X
X
X
Power Down
entry
H
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
Power Down
exit
L
H
X
X
X
X
X
X
L
H
H
H
X
X
X
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Row Address
H
L
OP Code
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15.2.3.1 Refresh Mode
The DDR2/mDDR memory controller issues refresh commands to the DDR2/mDDR SDRAM memory
(Figure 15-4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE
spaces and banks selected. Following the DCAB command, the DDR2/mDDR memory controller begins
performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register
(SDRCR). Page information is always invalid before and after a REFR command; thus, a refresh cycle
always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands
may not be disabled within the DDR2/mDDR memory controller. See Section 15.2.7 for more details on
REFR command scheduling.
Figure 15-4. Refresh Command
DDR_CLK
DDR_CLK
RFR
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
DDR_BA[2:0]
DDR_DQM[1:0]
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15.2.3.2 Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2/mDDR memory
controller or following the initialization sequence. DDR2/mDDR SDRAMs also require this cycle prior to a
refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command,
DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 15-5 shows the timing diagram for
a DCAB command.
Figure 15-5. DCAB Command
DCAB
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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The DEAC command closes a single bank of memory specified by the bank select signals. Figure 15-6
shows the timings diagram for a DEAC command.
Figure 15-6. DEAC Command
DEAC
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:11, 9:0]
DDR_A[10]
DDR_BA[2:0]
DDR_DQM[1:0]
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15.2.3.3 Activation (ACTV)
The DDR2/mDDR memory controller automatically issues the activate (ACTV) command before a read or
write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses
(reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of
DDR_A[13:0] selects the row. When the DDR2/mDDR memory controller issues an ACTV command, a
delay of tRCD is incurred before a read or write command is issued. Figure 15-7 shows an example of an
ACTV command. Reads or writes to the currently active row and bank of memory can achieve much
higher throughput than reads or writes to random areas because every time a new row is accessed, the
ACTV command must be issued and a delay of tRCD incurred.
Figure 15-7. ACTV Command
DDR_CLK
DDR_CLK
ACTV
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
ROW
DDR_BA[2:0]
BANK
DDR_DQM[1:0]
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15.2.3.4 READ Command
Figure 15-8 shows the DDR2/mDDR memory controller performing a read burst from DDR2/mDDR
SDRAM. The READ command initiates a burst read operation to an active row. During the READ
command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on
DDR_A[13:0], and the bank address is driven on DDR_BA[2:0].
The DDR2/mDDR memory controller uses a burst length of 8, and has a programmable CAS latency of 2,
3, 4, or 5. The CAS latency is three cycles in Figure 15-8. Read latency is equal to CAS latency plus
additive latency. The DDR2/mDDR memory controller always configures the memory to have an additive
latency of 0, so read latency equals CAS latency. Since the default burst size is 8, the DDR2/mDDR
memory controller returns 8 pieces of data for every read command. If additional accesses are not
pending to the DDR2/mDDR memory controller, the read burst completes and the unneeded data is
disregarded. If additional accesses are pending, depending on the scheduling result, the DDR2/mDDR
memory controller can terminate the read burst and start a new read burst. Furthermore, the DDR2/mDDR
memory controller does not issue a DAB/DEAC command until page information becomes invalid.
Figure 15-8. DDR2/mDDR READ Command
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
CAS Latency
DDR_D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
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15.2.3.5 Write (WRT) Command
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the
WRT command, a write latency is incurred. For DDR2, write latency is equal to CAS latency minus 1
cycles. For mDDR, write latency is equal to 1 cycle, always. All writes have a burst length of 8. The use of
the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 15-9 shows the timing for a
DDR2 write on the DDR2/mDDR memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pending
commands, the DDR2/mDDR memory controller can:
• Mask out the additional data using DDR_DQM outputs
• Terminate the write burst and start a new write burst
The DDR2/mDDR memory controller does not perform the DEAC command until page information
becomes invalid.
Figure 15-9. DDR2/mDDR WRT Command
DDR_CLK
DDR_CLK
Sample
Write Latency
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
DDR_A[10]
DDR_DQM[1:0]
DDR_D[15:0]
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8
D0
D1
D2
D3
D4
D5
D6
D7
DDR_DQS[1:0]
NOTE: This diagrams shows write latency for DDR2. For mDDR, write latency is always equal to 1 cycle.
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15.2.3.6 Mode Register Set (MRS and EMRS)
DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on DDR2/mDDR device), single-ended strobe, differential strobe etc.
The DDR2/mDDR memory controller programs the mode and extended mode registers of the
DDR2/mDDR memory by issuing MRS and EMRS commands. When the MRS or EMRS command is
executed, the value on DDR_BA[2:0] selects the mode register to be written and the data on DDR_A[13:0]
is loaded into the register. Figure 15-10 shows the timing for an MRS and EMRS command.
The DDR2/mDDR memory controller only issues MRS and EMRS commands during the DDR2/mDDR
memory controller initialization sequence. See Section 15.2.13 for more information.
Figure 15-10. DDR2/mDDR MRS and EMRS Command
MRS/EMRS
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]
COL
DDR_BA[2:0]
BANK
15.2.4 Memory Width and Byte Alignment
The DDR2/mDDR memory controller supports memory widths of 16 bits. Table 15-4 summarizes the
addressable memory ranges on the DDR2/mDDR memory controller. Only little-endian format is
supported. Figure 15-11 shows the byte lanes used on the DDR2/mDDR memory controller. The external
memory is always right aligned on the data bus.
Table 15-4. Addressable Memory Ranges
Memory Width
Maximum addressable bytes per CS space
Description
×16
512 Mbytes
Halfword address
Figure 15-11. Byte Alignment
DDR2 memory controller data bus
DDR_D[15:8]
DDR_D[7:0]
16-bit memory device
334
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15.2.5 Address Mapping
The memory controller views the DDR2/mDDR SDRAM device as one continuous block of memory. The
memory controller receives memory access requests with a 32-bit logical address, and it uses the logical
address to generate a row, column, and bank address for accessing the DDR2/mDDR SDRAM device.
The memory controller supports two address mapping schemes: normal address mapping and special
address mapping. Special address mapping is typically used only with mDDR devices using partial array
self-refresh.
When the internal bank position (IBANKPOS) bit in the SDRAM configuration register (SDCR) is cleared,
the memory controller operates with normal address mapping. In this case, the number of column and
bank address bits is determined by the IBANK and PAGESIZE fields in SDCR. The number of row
address bits is determined by the number of valid address pins for the device and does not need to be set
in a register.
When IBANKPOS is set to 1, the memory controller operates with special address mapping. In this case,
the number of column, row, and bank address bits is determined by the PAGESIZE, ROWSIZE, and
IBANK fields. The ROWSIZE field is in the SDRAM configuration register 2 (SDCR2). See Table 15-5 for a
descriptions of these bit fields.
Table 15-5. Configuration Register Fields for Address Mapping
Bit Field
Bit Value
IBANK
Defines the number of internal banks in the external DDR2/mDDR memory.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
PAGESIZE
Defines the page size of each page in the external DDR2/mDDR memory.
0
256 words (requires 8 column address bits)
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
ROWSIZE
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Bit Description
Defines the row size of each row in the external DDR2/mDDR memory
0
512 (requires 9 row address bits)
1h
1024 (requires 10 row address bits)
2h
2048 (requires 11 row address bits)
3h
4096 (requires 12 row address bits)
4h
8192 (requires 13 row address bits)
5h
16384 (requires 14 row address bits)
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15.2.5.1 Normal Address Mapping (IBANKPOS = 0)
As stated in Table 15-5, the IBANK and PAGESIZE fields of SDCR control the mapping of the logical,
source address of the DDR2/mDDR memory controller to the DDR2/mDDR SDRAM row, column, and
bank address bits. The DDR2/mDDR memory controller logical address always contains up to 14 row
address bits, whereas the number of column and bank bits are determined by the IBANK and PAGESIZE
fields. Table 15-6 show how the logical address bits map to the DDR2/mDDR SDRAM row, column, and
bank bits for combinations of IBANK and PAGESIZE values. The same DDR2/mDDR memory controller
pins provide the row and column address to the DDR2/mDDR SDRAM, thus the DDR2/mDDR memory
controller appropriately shifts the address during row and column address selection.
Figure 15-12 shows how this address-mapping scheme organizes the DDR2/mDDR SDRAM rows,
columns, and banks into the device memory-map. Note that during a linear access, the DDR2/mDDR
memory controller increments the column address as the logical address increments. When the
DDR2/mDDR memory controller reaches a page/row boundary, it moves onto the same page/row in the
next bank. This movement continues until the same page has been accessed in all banks. To the
DDR2/mDDR SDRAM, this process looks as shown in Figure 15-13.
By traversing across banks while remaining on the same row/page, the DDR2/mDDR memory controller
maximizes the number of activated banks for a linear access. This results in the maximum number of
open pages when performing a linear access being equal to the number of banks. Note that the
DDR2/mDDR memory controller never opens more than one page per bank.
Ending the current access is not a condition that forces the active DDR2/mDDR SDRAM row to be closed.
The DDR2/mDDR memory controller leaves the active row open until it becomes necessary to close it.
This decreases the deactivate-reactivate overhead.
Table 15-6. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM
SDCR Bit
336
Logical Address
IBANK
PAGESIZE
31
0
0
-
1
0
-
2h
0
-
3h
0
-
0
1
-
1
1
-
2h
1
-
3h
1
-
0
2h
-
1
2h
-
2h
2h
-
3h
2h
-
0
3h
-
1
3h
-
2h
3h
-
3h
3h
-
30
29
28
27
26
25
24
23
22
21:15
14
13
12
11
10
9
nrb=14
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
0
ncb=8
ncb=8
nbb=3
ncb=8
nrb=14
ncb=9
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=9
ncb=9
nbb=3
ncb=9
nrb=14
ncb=10
nrb=14
nbb=1
nrb=14
nbb=2
nrb=14
ncb=10
ncb=10
nbb=3
ncb=10
nrb=14
ncb=11
nrb=14
nbb=1
nrb=14
nrb=14
8:1
ncb=8
nbb=2
nbb=3
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ncb=11
ncb=11
ncb=11
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Figure 15-12. Logical Address-to-DDR2/mDDR SDRAM Address Map
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 0, bank 0
Row 0, bank 1
Row 0, bank 2
Row 0, bank P
Row 1, bank 0
Row 1, bank 1
Row 1, bank 2
Row 1, bank P
Row N, bank 0
Row N, bank 1
Row N, bank 2
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
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Figure 15-13. DDR2/mDDR SDRAM Column, Row, and Bank Access
Bank 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Bank 1
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Bank 2
Row 2
Row 0
Row 1
Bank P
Row 2
Row 0
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 1
Row 2
Row N
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1.
15.2.5.2 Special Address Mapping (IBANKPOS = 1)
When the internal bank position (IBANKPOS) bit is set to 1, the PAGESIZE, ROWSIZE, and IBANK fields
control the mapping of the logical source address of the memory controller to the column, row, and bank
address bits of the SDRAM device. Table 15-7 shows which source address bits map to the SDRAM
column, row, and bank address bits for all combinations of PAGESIZE, ROWSIZE, and IBANK.
When IBANKPOS is set to 1, the effect of the address-mapping scheme is that as the source address
increments across an SDRAM page boundary, the memory controller proceeds to the next page in the
same bank. This movement along the same bank continues until all the pages have been accessed in the
same bank. The memory controller then proceeds to the next bank in the device. This sequence is shown
in Figure 15-14 and Figure 15-15.
Since, in this address mapping scheme, the memory controller can keep only one bank open, this scheme
is lower in performance than the case when IBANKPOS is cleared to 0. Therefore, this case is only
recommended to be used with Partial Array Self-refresh for mDDR SDRAM where performance may be
traded-off for power savings.
Table 15-7. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1)
31
Source Address
Bank Address
Number of bank bits is defined by
IBANK nbb = 1, 2, or 3
338
Row Address
Number of row bits is defined by
ROWSIZE: nrb = 9, 10, 11, 12, 13, or 14
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Column Address
Number of column bits is defined by
PAGESIZE: ncb = 8, 9, 10, or 11
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Figure 15-14. Address Mapping Diagram (IBANKPOS = 1)
Col. 0
Col. 1
Col. 2
Col. 3
Col. 4
Col. M−1
Col. M
Row 1, bank 0
Row 2, bank 0
Row 3, bank 0
Row N, bank 0
Row 1, bank 1
Row 2, bank 1
Row 3, bank 1
Row N, bank 1
Row 1, bank P
Row 2, bank P
Row 3, bank P
Row N, bank P
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
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Figure 15-15. SDRAM Column, Row, Bank Access (IBANKPOS = 1)
Bank 0
C C C
o o o
l l l
0 1 2 3
Row 0
Row 1
Row 2
C
o
l
M
Bank 1
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 0
Row 1
Row 2
Bank 2
Row 0
Row 1
Row 2
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Bank P
Row 0
Row 1
Row N
C C C
o o o
l l l
0 1 2 3
C
o
l
M
Row 2
Row N
Row N
Row N
NOTE: M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by
IBANK) minus 1, and N is number of rows (as determined by ROWSIZE) minus 1.
15.2.6 DDR2/mDDR Memory Controller Interface
To move data efficiently from on-chip resources to external DDR2/mDDR SDRAM memory, the
DDR2/mDDR memory controller makes use of a command FIFO, a write FIFO, a read FIFO, and
command and data schedulers. Table 15-8 describes the purpose of each FIFO.
Figure 15-16 shows the block diagram of the DDR2/mDDR memory controller FIFOs. Commands, write
data, and read data arrive at the DDR2/mDDR memory controller parallel to each other. The same
peripheral bus is used to write and read data from external memory as well as internal memory-mapped
registers.
Table 15-8. DDR2/mDDR Memory Controller FIFO Description
340
FIFO
Description
Depth (64-bit doublewords)
Command
Stores all commands coming from on-chip requestors
7
Write
Stores write data coming from on-chip requestors to memory
11
Read
Stores read data coming from memory to on-chip requestors
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Figure 15-16. DDR2/mDDR Memory Controller FIFO Block Diagram
Command FIFO
Command/Data
Scheduler
Command
to Memory
Write FIFO
Write Data
to Memory
Read FIFO
Read Data
from
Memory
Registers
Command
Data
15.2.6.1 Command Ordering and Scheduling, Advanced Concept
The DDR2/mDDR memory controller performs command re-ordering and scheduling in an attempt to
achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data,
address, and command buses while hiding the overhead of opening and closing DDR2/mDDR SDRAM
rows. Command re-ordering takes place within the command FIFO.
Typically, a given master issues commands on a single priority. EDMA transfer controller read and write
ports are different masters. The DDR2/mDDR memory controller first reorders commands from each
master based on the following rules:
• Selects the oldest command (first command in the queue)
• Selects a read before a write if:
– The read is to a different block address (2048 bytes) than the write
– The read has greater or equal priority
The second bullet above may be viewed as an exception to the first bullet. This means that for an
individual master, all of its commands will complete from oldest to newest, with the exception that a read
may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master
may have one command ready for execution.
Next, the DDR2/mDDR memory controller examines each of the commands selected by the individual
masters and performs the following reordering:
• Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes
to rows already open.
• Selects the highest priority command from pending reads and writes to open rows. If multiple
commands have the highest priority, then the DDR2/mDDR memory controller selects the oldest
command.
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The DDR2/mDDR memory controller may now have a final read and write command. If the Read FIFO is
not full, then the read command will be performed before the write command, otherwise the write
command will be performed first.
Besides commands received from on-chip resources, the DDR2/mDDR memory controller also issues
refresh commands. The DDR2/mDDR memory controller attempts to delay refresh commands as long as
possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2/mDDR
memory controller issues read, write, and refresh commands to DDR2/mDDR SDRAM memory, it adheres
to the following rules:
1. Refresh request resulting from the Refresh Must level of urgency being reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency being reached
6. Request to enter self-refresh mode
The following results from the above scheduling algorithm:
• All writes from a single master will complete in order
• All reads from a single master will complete in order
• From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
15.2.6.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/mDDR memory controller. Command
starvation results from the following conditions:
• A continuous stream of high-priority read commands can block a low-priority write command
• A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/mDDR memory controller can momentarily raises the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers
that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest
command.
15.2.6.3 Possible Race Condition
A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait
for indication that the write completes, when master B attempts to read the software message it may read
stale data and therefore receive an incorrect message. In order to confirm that a write from master A has
landed before a read from master B is performed, master A must wait for the write completion status from
the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. If
master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register.
3. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The EDMA peripheral does not need to implement the above workaround. The above workaround is
required for all other peripherals. See your device-specific data manual for more information.
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15.2.7 Refresh Scheduling
The DDR2/mDDR memory controller issues autorefresh (REFR) commands to DDR2/mDDR SDRAM
devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR).
A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until
it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. Each time
the interval counter expires, a refresh backlog counter increments by 1. Conversely, each time the
DDR2/mDDR memory controller performs a REFR command, the backlog counter decrements by 1. This
means the refresh backlog counter records the number of REFR commands the DDR2/mDDR memory
controller currently has outstanding.
The DDR2/mDDR memory controller issues REFR commands based on the level of urgency. The level of
urgency is defined in Table 15-9. Whenever the refresh must level of urgency is reached, the
DDR2/mDDR memory controller issues a REFR command before servicing any new memory access
requests. Following a REFR command, the DDR2/mDDR memory controller waits T_RFC cycles, defined
in the SDRAM timing register 1 (SDTIMR1), before rechecking the refresh urgency level.
In addition to the refresh counter previously mentioned, a separate backlog counter ensures the interval
between two REFR commands does not exceed 8× the refresh rate. This backlog counter increments by 1
each time the interval counter expires and resets to zero when the DDR2/mDDR memory controller issues
a REFR command. When this backlog counter is greater than 7, the DDR2/mDDR memory controller
issues four REFR commands before servicing any new memory requests.
The refresh counters do not operate when the DDR2/mDDR memory is in self-refresh mode.
Table 15-9. Refresh Urgency Levels
Urgency Level
Description
Refresh May
Backlog count is greater than 0. Indicates there is a backlog of REFR commands, when the DDR2/mDDR
memory controller is not busy it will issue the REFR command.
Refresh Release
Backlog count is greater than 3. Indicates the level at which enough REFR commands have been performed
and the DDR2/mDDR memory controller may service new memory access requests.
Refresh Need
Backlog count is greater than 7. Indicates the DDR2/mDDR memory controller should raise the priority level
of a REFR command above servicing a new memory access.
Refresh Must
Backlog count is greater than 11. Indicates the level at which the DDR2/mDDR memory controller should
perform a REFR command before servicing new memory access requests.
15.2.8 Self-Refresh Mode
Clearing the self refresh/low power (SR_PD) bit to 0 and then setting the low power mode enable
(LPMODEN) bit to 1 in the SDRAM refresh control register (SDRCR) , forces the DDR2/mDDR memory
controller to place the external DDR2/mDDR SDRAM in a low-power mode (self refresh), in which the
DDR2/mDDR SDRAM maintains valid data while consuming a minimal amount of power. When the
LPMODEN bit is set to 1, the DDR2/mDDR memory controller continues normal operation until all
outstanding memory access requests have been serviced and the refresh backlog has been cleared. At
this point, all open pages of DDR2/mDDR SDRAM are closed and a self-refresh (SLFRFR) command (an
autorefresh command with self refresh/low power) is issued.
The memory controller exits the self-refresh state when a memory access is received, when the
LPMODEN bit in SDRCR is cleared to 0, or when the SR_PD bit in SDRCR changed to 1. While in the
self-refresh state, if a request for a memory access is received, the DDR2/mDDR memory controller
services the memory access request, returning to the self-refresh state upon completion. The
DDR2/mDDR memory controller will not wake up from the self-refresh state (whether from a memory
access request, from clearing the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles
have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM
timing register 2 (SDTIMR2).
In the case of DDR2, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR + 1 clock cycles before issuing non-read/write
commands and T_SXRD + 1 clock cycles before issuing read or write commands. The SDRAM timing
register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD.
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In the case of mDDR, after exiting from the self-refresh state, the memory controller will not immediately
start executing commands. Instead, it will wait T_SXNR+1 clock cycles and then execute auto-refresh
command before issuing any other commands. The SDRAM timing register 2 (SDTIMR2) programs the
value of T_SXNR.
Once in self-refresh mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK) may be
gated off or changed in frequency. Stable clocks must be present before exiting self-refresh mode. See
Section 15.2.16 for more information describing the proper procedure to follow when shutting down
DDR2/mDDR memory controller input clocks.
See Section 15.2.16.1 for a description of the self-refresh programming sequence.
15.2.9 Partial Array Self Refresh for Mobile DDR
For additional power savings during self-refresh, the partial array self-refresh (PASR) feature of the mDDR
allows you to select the amount of memory that will be refreshed during self-refresh. Use the partial array
self-refresh (PASR) bit field in the SDRAM configuration register 2 (SDCR2) to select the amount of
memory to refresh during self-refresh. As shown in Table 15-10 you may select either 4, 2, 1, 1/2, or 1/4
bank(s). The PASR bits are loaded into the extended mode register of the mDDR device, during
autoinitialization (see Section 15.2.13).
The mDDR performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM
configuration register (SDCR) is cleared to 0. Since the SDRAM banks are only partially refreshed during
partial array self-refresh, it is recommended that you set IBANKPOS to 1 to avoid bank interleaving. When
IBANKPOS is cleared to 0, it is the responsibility of software to move critical data into the banks that are
to be refreshed during partial array self-refresh. Refer to Section 15.2.5.2 for more information on
IBANKPOS and addressing mapping in general.
Table 15-10. Configuration Bit Field for Partial Array Self-refresh
Bit Field
Bit Value
PASR
Bit Description
Partial array self refresh.
0
Refresh banks 0, 1, 2, and 3
1h
Refresh banks 0 and 1
2h
Refresh bank 0
5h
Refresh 1/2 of bank 0
6h
Refresh 1/4 of bank 0
15.2.10 Power-Down Mode
Setting the self-refresh/low power (SR_PD) bit and the low-power mode enable (LPMODEN) bit in the
SDRAM refresh control register (SDRCR) to 1, forces the DDR2/mDDR memory controller to place the
external DDR2 SDRAM in the power-down mode. When the LPMODEN bit is asserted, the DDR2/mDDR
memory controller continues normal operation until all outstanding memory access requests have been
serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are
closed and a Power Down command (same as NOP command but driving DDR_CKE low on the same
cycle) is issued.
The DDR2/mDDR memory controller exits the power-down state when a memory access is received,
when a Refresh Must level is reached, when the LPMODEN bit in SDRCR is cleared to 0, or when the
SR_PD bit in SDRCR changed to 0. While in the power-down state, if a request for a memory access is
received, the DDR2/mDDR memory controller services the memory access request, returning to the
power-down state upon completion. The DDR2/mDDR memory controller will not wake-up from the
power-down state (whether from a memory access request, from reaching a Refresh Must level, from
clearing the LPMODEN bit, or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the
power-down command was issued. The value of T_CKE is defined in the SDRAM timing register 2
(SDTIMR2).
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After exiting from the power-down state, the DDR2/mDDR memory controller will drive DDR_CKE high
and then not immediately start executing commands. Instead, it will wait T_XP + 1 clock cycles before
issuing commands. The SDRAM timing register 2 (SDTIMR2) programs the values of T_XP.
See Section 15.2.16.1 for a description of the power-down mode programming sequence.
NOTE: Power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
15.2.11 Reset Considerations
The DDR2/mDDR memory controller has two reset signals, chip_rst_n and mod_g_rst_n. The chip_rst_n
is a module-level reset that resets both the state machine as well as the DDR2/mDDR memory controller
memory-mapped registers. The mod_g_rst_n resets the state machine only; it does not reset the
controller's registers, which allows soft reset (from PSC or WDT) to reset the module without resetting the
configuration registers and reduces the programming overhead for setting up access to the DDR2/mDDR
device. If the DDR2/mDDR memory controller is reset independently of other peripherals, the user's
software should not perform memory, as well as register accesses, while chip_rst_n or mod_g_rst_n are
asserted. If memory or register accesses are performed while the DDR2/mDDR memory controller is in
the reset state, other masters may hang. Following the rising edge of chip_rst_n or mod_g_rst_n, the
DDR2/mDDR memory controller immediately begins its initialization sequence. Command and data stored
in the DDR2/mDDR memory controller FIFOs are lost. Table 15-11 describes the different methods for
asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power
management for all of the peripherals on the device. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. Figure 15-17 shows the
DDR2/mDDR memory controller reset diagram.
Table 15-11. Reset Sources
Reset Signal
Reset Source
chip_rst_n
Hardware/device reset
mod_g_rst_n
Power and sleep controller
Figure 15-17. DDR2/mDDR Memory Controller Reset Block Diagram
Hard
Reset from
PLLC0
DDR
PSC
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15.2.12 VTP IO Buffer Calibration
The DDR2/mDDR memory controller is able to control the impedance of the output IO. This feature allows
the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB
board. Control of the output impedance of the IO is an important feature because impedance matching
reduces reflections, creating a cleaner board design. Calibrating the output impedance of the IO will also
reduce the power consumption of the DDR2/mDDR memory controller. The calibration is performed with
respect to voltage, temperature, and process (VTP). The VTP information obtained from the calibration is
used to control the output impedance of the IO.
The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP.
The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm, 5.0% tolerance, 1/16th
watt resistor (49.9 ohm, 0.5% tolerance is acceptable).
The VTP IO control register (VTPIO_CTL) is written to begin the calibration process. The VTP calibration
process is described in the DDR2/mDDR initialization sequence in Section 15.2.13.1.
NOTE: VTP IO calibration must be performed following device power up and device reset. If the
DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the
VTP input clock is disabled, accesses to the DDR2/mDDR memory controller will not
complete. To re-enable accesses to the DDR2/mDDR memory controller, enable the VTP
input clock and then perform the VTP calibration sequence again.
15.2.13 Auto-Initialization Sequence
The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR
memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable
(on the DDR2/mDDR device), single-ended strobe, differential strobe, etc. The DDR2/mDDR memory
controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS
and EMRS commands during the initialization sequence. The SDRAMEN, MSDRAMEN, DDREN, and
DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory
controller will perform a DDR2 or mobile DDR initialization sequence. Set these bits as follows for DDR2:
SDRAMEN = 1, MSDRAMEN = 0, DDREN = 1, DDR2EN = 1. Set these bits as follow for mDDR:
SDRAMEN = 1, MSDRAMEN = 1, DDREN = 1, DDR2EN = 0. The DDR2 initialization sequence
performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the
mDDR initialization sequence is compliant with the JESD209 specification. The DDR2/mDDR memory
controller performs an initialization sequence under the following conditions:
• Following reset (rising edge of chip_rst_n or mod_g_rst_n)
• Following a write to the DDRDRIVE, CL, IBANK, or PAGESIZE bit fields in the SDRAM configuration
register (SDCR)
During the initialization sequence, the memory controller issues MRS and EMRS commands that
configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. The register
values for DDR2 are described in Table 15-12 and Table 15-13, and the register values for mDDR are
described in Table 15-14 and Table 15-15. The extended mode registers 2 and 3 are configured with a
value of 0h. At the end of the initialization sequence, the memory controller performs an autorefresh cycle,
leaving the memory controller in an idle state with all banks deactivated.
When a reset occurs, the DDR2/mDDR memory controller immediately begins the initialization sequence.
Under this condition, commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost.
However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR,
data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the
DDR2/mDDR memory controller will ensure read and write commands are completed before starting the
initialization sequence.
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Table 15-12. DDR2 SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Power Down Exit
Fast exit
DDR_A[11:9]
t_WR
11:9
Write Recovery
Write recovery from autoprecharge. Value of
2, 3, 4, 5, or 6 is programmed based on
value of the T_WR bit in the SDRAM timing
register 1 (SDTIMR1 ).
DDR_A[8]
0
8
DLL Reset
Out of reset
DDR_A[7]
0
7
Mode: Test or Normal
Normal mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2, 3, 4, or 5 is programmed based
on value of the CL bit in the SDRAM
configuration register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
Table 15-13. DDR2 SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
DDR2/mDDR
SDRAM
Register Bit
DDR2/mDDR
SDRAM Field
Function Selection
DDR_A[12]
0
12
Output Buffer Enable
Output buffer enable
DDR_A[11]
0
11
RDQS Enable
RDQS disable
DDR_A[10]
1
10
DQS enable
Disables differential DQS signaling.
DDR_A[9:7]
0
9:7
OCD Calibration Program
Exit OCD calibration
DDR_A[6]
0
6
ODT Value (Rtt)
Cleared to 0 to select 75 ohms. This feature
is not supported because the DDR_ODT
signal is not pinned out.
DDR_A[5:3]
0
5:3
Additive Latency
0 cycles of additive latency
DDR_A[2]
1
2
ODT Value (Rtt)
Set to 1 to select 75 ohms. This feature is not
supported because the DDR_ODT signal is
not pinned out.
DDR_A[1]
DDRDRIVE[0]
1
Output Driver Impedance
Value of 0 or 1 is programmed based on
value of DDRDRIVE0 bit in SDRAM
configuration register (SDCR).
DDR_A[0]
0
0
DLL enable
DLL enable
Table 15-14. Mobile DDR SDRAM Configuration by MRS Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating mode
Normal operating mode
DDR_A[6:4]
CL bit
6:4
CAS Latency
Value of 2 or 3 is programmed based on
value of CL bit in SDRAM configuration
register (SDCR).
DDR_A[3]
0
3
Burst Type
Sequential
DDR_A[2:0]
3h
2:0
Burst Length
Value of 8
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Table 15-15. Mobile DDR SDRAM Configuration by EMRS(1) Command
Memory
Controller
Address Bus
Value
mDDR SDRAM
Register Bit
mDDR SDRAM Field
Function Selection
DDR_A[11:7]
0
11:7
Operating Mode
Normal operating mode
DDR_A[6:5]
DDRDRIVE[1:0]
6:5
Output Driver Impedance
Value of 0, 1, 2, or 3 is programmed based
on value of DDRDRIVE[1:0] bits in SDRAM
configuration register (SDCR).
DDR_A[4:3]
0
4:3
Temperature Compensated
Self Refresh
Value of 0
DDR_A[2:0]
PASR bits
2:0
Partial Array Self Refresh
Value of 0, 1, 2, 5, or 6 is programmed based
on value of PASR bits in SDRAM
configuration register 2 (SDCR2).
15.2.13.1 Initializing Following Device Power Up or Reset
Following device power up or reset, the DDR2/mDDR memory controller is held in reset with the internal
clocks to the module gated off. Before releasing the DDR2/mDDR memory controller from reset, the
clocks to the module must be turned on. Perform the following steps when turning the clocks on and
initializing the module:
1. Program PLLC1 registers to start the PLL1_SYSCLK1 (that drives 2X_CLK). For information on
programming PLLC1, see the Phase-Locked Loop Controller (PLLC) chapter.
2. Program Power and Sleep Controller (PSC) to enable the DDR2/mDDR memory controller clock.
3. Perform VTP IO calibration:
(a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).
(b) Clear LOCK bit in VTPIO_CTL.
(c) Pulse CLKRZ bit in VTPIO_CTL:
(i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by
performing a read-modify-write of VTPIO_CTL in the next step).
(iii) Set CLKRZ bit.
(d) Poll READY bit in VTPIO_CTL until it changes to 1.
(e) Set LOCK bit in VTPIO_CTL. VTP is locked and dynamic calibration is disabled.
(f) Set POWERDN bit in VTPIO_CTL to save power.
4. Set IOPWRDN bit in VTPIO_CTL to allow the input receivers to save power when the PWRDNEN bit in
the DDR PHY control register 1 (DRPYC1R) is set.
5. Configure DRPYC1R. All of the following steps may be done with a single register write to DRPYC1R:
(a) Set EXT_STRBEN bit to select external DQS strobe gating.
(b) Set PWRDNEN bit to allow the input receivers to power down when they are idle.
(c) Program RL bit value to meet the memory data sheet specification.
6. Configure the DDR slew register (DDR_SLEW):
(a) For DDR2, clear DDR_PDENA and CMOSEN bits.
(b) For mDDR, set the DDR_PDENA and CMOSEN bits.
7. Set the BOOTUNLOCK bit (unlocked) in the SDRAM configuration register (SDCR).
8. Program SDCR to the desired value with BOOTUNLOCK bit cleared to 0 and TIMUNLOCK bit set to 1
(unlocked).
9. For mDDR only, program the SDRAM configuration register 2 (SDCR2) to the desired value.
10. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the
desired values to meet the memory data sheet specification.
11. Clear TIMUNLOCK bit (locked) in SDCR.
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12. Program the SDRAM refresh control register (SDRCR). All of the following steps may be done with a
single register write to SDRCR:
(a) Set LPMODEN bit to enable self-refresh. This is necessary for the next two steps.
(b) Set MCLKSTOPEN bit to enable MCLK stopping. This is necessary for the next two steps.
(c) Clear SR_PD bit to select self-refresh. This is necessary for the next two steps.
(d) Program RR refresh rate value to meet the memory data sheet specification.
13. Program the Power and Sleep Controller (PSC) to reset (SyncReset) the DDR2/mDDR memory
controller.
14. Program the Power and Sleep Controller (PSC) to re-enable the DDR2/mDDR memory controller.
15. Clear LPMODEN and MCLKSTOPEN bits in SDRCR to disable self-refresh.
16. Configure the peripheral bus burst priority register (PBBPR) to a value lower than the default value of
FFh. A lower value reduces the likelihood of prolonged command starvation for accesses made from
different master/peripherals to mDDR/DDR2 memory. The optimal value should be determined based
on system considerations; however, a value of 20h or 30h is sufficient for typical applications.
NOTE: Some memory data sheet timing values such as those programmed into the SDRAM timing
register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) may need to be relaxed in
order to compensate for signal delays introduced by board layout.
15.2.14 Interrupt Support
The DDR2/mDDR memory controller supports two addressing modes, linear incrementing and cache line
wrap. Upon receipt of an access request for an unsupported addressing mode, the DDR2/mDDR memory
controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). The DDR2/mDDR
memory controller will then treat the request as a linear incrementing request.
This interrupt is called the line trap interrupt and is the only interrupt the DDR2/mDDR memory controller
supports. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register
(IMSR). This interrupt is mapped to the CPU and is multiplexed with RTCINT.
15.2.15 DMA Event Support
The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA
events. Data read and write requests may be made directly by masters and by the DMA.
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15.2.16 Power Management
Power dissipation from the DDR2/mDDR memory controller may be managed by the following methods:
• Self-refresh mode (see Section 15.2.8)
• Power-down mode (see Section 15.2.10)
• Disabling the DDR PHY to reduce power
The DDR2/mDDR memory controller supports low-power modes where the DLL internal to the PHY
and the receivers at the I/O pins can be disabled. These functions are controlled through the
DDR2/mDDR memory controller. Even if the PHY is active, the receivers can be configured to disable
whenever writes are in progress and the receivers are not needed.
• Gating input clocks to the module off
Gating input clocks off to the DDR2/mDDR memory controller achieves higher power savings when
compared to the power savings of self-refresh mode and power-down mode. The input clocks are
turned off outside of the DDR2/mDDR memory controller through the use of the Power and Sleep
Controller (PSC) and the PLL controller 1 (PLLC1). Figure 15-18 shows the connections between the
DDR2/mDDR memory controller, PSC, and PLLC1. For detailed information on power management
procedures using the PSC, see the Power and Sleep Controller (PSC) chapter.
Before gating clocks off, the DDR2/mDDR memory controller must place the DDR2/mDDR SDRAM
memory in self-refresh mode. If the external memory requires a continuous clock, the DDR2/mDDR
memory controller clock provided by PLLC1 must not be turned off because this may result in data
corruption. See the following subsections for the proper procedures to follow when stopping the
DDR2/mDDR memory controller clocks. Once the clocks are stopped, to re-enable the clocks follow
the clock stop procedure in each respective subsection in reverse order.
Figure 15-18. DDR2/mDDR Memory Controller Power Sleep Controller Diagram
PLL0_SYSCLK2/2
CLKSTOP_REQ
VCLKSTOP_REQ
CLKSTOP_ACK
VCLKSTOP_ACK
DDR
PST
MODCLK
MODRST
LRST
DDR2/mDDR
memory
VCLK
controller
chip_rst_n
mod_g_rst_n
2X_CLK
PLLC1
/1
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15.2.16.1 DDR2/mDDR Memory Controller Clock Stop Procedure
NOTE: If a data access occurs to the DDR2/mDDR memory after completing steps 1-4, the DLL will
wake up and lock, then the MCLK will turn on and the access will be performed. Following
steps 5 and 6, in which the clocks are disabled , all DDR2/mDDR memory accesses are not
possible until the clocks are reenabled.
In power-down mode, the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK)
may not be gated off. This is a limitation of the DDR2/mDDR controller. For this reason,
power-down mode is best suited as a power savings mode when SDRAM is being used
intermittently and the system requires power savings as well as a short recovery time. You
may use self-refresh mode if you desire additional power savings from disabling clocks.
To achieve maximum power savings VCLK, MCLK, 2X_CLK, DDR_CLK, and DDR_CLK should be gated
off. The procedure for clock gating is described in the following steps.
1. Allow software to complete the desired DDR transfers.
2. Change the SR_PD bit to 0 and set the LPMODEN bit to 1 in the DDR2 SDRAM refresh control
register (SDRCR) to enable self-refresh mode. The DDR2/mDDR memory controller will complete any
outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR
memory in self-refresh mode.
3. Set the MCLKSTOPEN bit in SDRCR to 1. This enables the DDR2/mDDR memory controller to shut
off the MCLK.
4. Wait 150 CPU clock cycles to allow the MCLK to stop.
5. Program the PSC to disable the DDR2/mDDR memory controller VCLK. You must not disable VCLK in
power-down mode; use only for self-refresh mode (see notes in this section).
6. For maximum power savings, the PLL/PLLC1 should be placed in bypass and powered-down mode to
disable 2X_CLK. You must not disable 2X_CLK in power-down mode; use only for self-refresh mode
(see notes in this section). For information on programming PLLC1, see the Phase-Locked Loop
Controller (PLLC) chapter.
To
1.
2.
3.
turn clocks back on:
Place the PLL/PLLC1 in PLL mode to start 2X_CLK to the DDR2/mDDR memory controller.
Once 2X_CLK is stable, program the PSC to enable VCLK.
Set the RESET_PHY bit in the DDR PHY reset control register (DRPYRCR) to 1. This resets the
DDR2/mDDR memory controller PHY. This bit will self-clear to 0 when reset is complete.
4. Clear the MCLKSTOPEN bit in SDRCR to 0.
5. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.
15.2.17 Emulation Considerations
The DDR2/mDDR memory controller will remain fully functional during emulation halts to allow emulation
access to external memory.
NOTE: VTP IO calibration must be performed before emulation tools attempt to access the register
or data space of the DDR2/mDDR memory controller. A bus lock-up condition will occur if the
emulation tool attempts to access the register or data space of the DDR2/mDDR memory
controller before completing VTP IO calibration. See Section 15.2.12 for information on VTP
IO calibration.
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15.3 Supported Use Cases
The DDR2/mDDR memory controller allows a high degree of programmability for shaping DDR2/mDDR
accesses. The programmability inherent to the DDR2/mDDR memory controller provides the DDR2/mDDR
memory controller with the flexibility to interface with a variety of DDR2/mDDR devices. By programming
the SDRAM configuration register (SDCR), SDRAM refresh control register (SDRCR), SDRAM timing
register 1 (SDTIMR1), and SDRAM timing register 2 (SDTIMR2), the DDR2/mDDR memory controller can
be configured to meet the data sheet specification for DDR2 SDRAM as well as mDDR memory devices.
This section presents an example describing how to interface the DDR2 memory controller to a
DDR2/mDDR-400 512-Mbyte device. The DDR2/mDDR memory controller is assumed to be operating at
150 MHz. A similar procedure can be followed when interfacing to a mDDR memory device.
15.3.1 Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory
Figure 15-19 shows how to connect the DDR2/mDDR memory controller to a DDR2 device. Figure 15-19
displays a 16-bit interface; you can see that all signals are point-to-point connection.
Figure 15-19. Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR2/mDDR
DDR_WE
memory
DDR_RAS
controller
DDR_CAS
DDR_DQM[0]
DDR_DQM[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[15:0]
CK
CK
CKE
DDR2
CS
memory
WE
x16−bit
RAS
CAS
LDM
UDM
LDQS
UDQS
BA[2:0]
A[12:0]
DQ[15:0]
DDR_ZP
50 Ω
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15.3.2 Configuring Memory-Mapped Registers to Meet DDR2 Specification
As previously stated, four memory-mapped registers must be programmed to configure the DDR2/mDDR
memory controller to meet the data sheet specification of the attached DDR2/mDDR device. The registers
are:
• SDRAM configuration register (SDCR)
• SDRAM refresh control register (SDRCR)
• SDRAM timing register 1 (SDTIMR1)
• SDRAM timing register 2 (SDTIMR2)
In addition to these registers, the DDR PHY control register (DRPYC1R) must also be programmed. The
configuration of DRPYC1R is not dependent on the DDR2 device specification but rather on the board
layout.
The following sections describe how to configure each of these registers. See Section 15.4 for more
information on the DDR2/mDDR memory controller registers.
NOTE: When interfacing the DDR2/mDDR memory controller to a mDDR device, the SDRAM
configuration register 2 (SDCR2) must be programmed in addition to the registers mentioned
above.
15.3.2.1 Configuring SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains register fields that configure the DDR2/mDDR
memory controller to match the data bus width, CAS latency, number of banks, and page size of the
attached memory. In this example, we assume the following DDR2 configuration:
• Data bus width = 16 bits
• CAS latency = 3
• Number of banks = 8
• Page size = 1024 words
Table 15-16 shows the resulting SDCR configuration. Note that the value of the TIMING_UNLOCK field is
dependent on whether or not it is desirable to unlock SDTIMR1 and SDTIMR2. The TIMING_UNLOCK bit
should only be set to 1 when the SDTIMR1 and SDTIMR2 needs to be updated.
Table 15-16. SDCR Configuration
Field
Value
Function Selection
TIMING_UNLOCK
x
Set to 1 to unlock the SDRAM timing register 1 and SDRAM timing register 2.
Cleared to 0 to lock the SDRAM timing register 1 and SDRAM timing register 2.
NM
1h
To configure the DDR2/mDDR memory controller for a 16-bit data bus width.
CL
3h
To select a CAS latency of 3.
IBANK
3h
To select 8 internal DDR2 banks.
PAGESIZE
2h
To select 1024-word page size.
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15.3.2.2 Configuring SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) configures the DDR2/mDDR memory controller to meet the
refresh requirements of the attached memory device. SDRCR also allows the DDR2/mDDR memory
controller to enter and exit self refresh and enable and disable the MCLK stopping. In this example, we
assume that the DDR2/mDDR memory controller is not is in self-refresh mode or power-down mode and
that MCLK stopping is disabled.
The RR field in SDRCR is defined as the rate at which the attached memory device is refreshed in
DDR2/mDDR cycles. The value of this field may be calculated using the following equation:
RR = DDR2/mDDR clock frequency × DDR2/mDDR memory refresh period
Table 15-17 displays the DDR2-400 refresh rate specification.
Table 15-17. DDR2 Memory Refresh Specification
Symbol
Description
Value
tREF
Average Periodic Refresh Interval
7.8 μs
Therefore, the following results assuming 150 MHz DDR2/mDDR clock frequency.
RR = 150 MHz × 7.8 μs = 1170
Therefore, RR = 1170 = 492h.
Table 15-18 shows the resulting SDRCR configuration.
Table 15-18. SDRCR Configuration
354
Field
Value
Function Selection
LPMODEN
0
DDR2/mDDR memory controller is not in power-down mode.
MCLKSTOP_EN
0
MCLK stopping is disabled.
SR_PD
0
Leave a default value.
RR
492h
Set to 492h DDR2 clock cycles to meet the DDR2/mDDR memory refresh rate requirement.
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15.3.2.3 Configuring SDRAM Timing Registers (SDTIMR1 and SDTIMR2)
The SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) configure the
DDR2/mDDR memory controller to meet the data sheet timing parameters of the attached memory device.
Each field in SDTIMR1 and SDTIMR2 corresponds to a timing parameter in the DDR2/mDDR data sheet
specification. Table 15-19 and Table 15-20 display the register field name and corresponding DDR2 data
sheet parameter name along with the data sheet value. These tables also provide a formula to calculate
the register field value and displays the resulting calculation. Each of the equations include a minus 1
because the register fields are defined in terms of DDR2/mDDR clock cycles minus 1. See Section 15.4.5
and Section 15.4.6 for more information.
Table 15-19. SDTIMR1 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
Description
Data Manual
Value (nS)
Formula
(Register field must be ≥)
Register
Value
T_RFC
tRFC
Refresh cycle time
127.5
(tRFC × fDDR2/mDDR_CLK) - 1
19
T_RP
tRP
Precharge command to
refresh or activate
command
15
(tRP × fDDR2/mDDR_CLK) - 1
2
T_RCD
tRCD
Activate command to
read/write command
15
(tRCD × fDDR2/mDDR_CLK) - 1
2
T_WR
tWR
Write recovery time
15
(tWR × fDDR2/mDDR_CLK) - 1
2
T_RAS
tRAS
Active to precharge
command
40
(tRAC × fDDR2/mDDR_CLK) - 1
5
T_RC
tRC
Activate to Activate
command in the same
bank
55
(tRC × fDDR2/mDDR_CLK) - 1
8
T_RRD (1)
tRRD
Activate to Activate
command in a different
bank
10
((4 × tRRD) + (2 × tCK))/(4 × tCK) - 1
1
T_WTR
tWTR
Write to read command
delay
10
(tWTR × fDDR2/mDDR_CLK) - 1
1
(1)
The formula for the T_RRD field applies only for 8 bank DDR2/mDDR memories; when interfacing to DDR2/mDDR memories
with less than 8 banks, the T_RRD field should be calculated using the following formula: (tRRD × fDDR2/mDDR_CLK) - 1.
Table 15-20. SDTIMR2 Configuration
Register
Field Name
DDR2 Data
Manual
Parameter
Name
T_RASMAX
tRAS(MAX)
T_XP
Data Manual
Value
Formula
(Register field must be ≥)
Register
Value
Active to precharge
command
70 μs
tRAS(MAX)/DDR refresh rate- 1
8
tXP
Exit power down to a
non-read command
2(tCK cycles)
If tXP > tCKE,
then T_XP = tXP- 1,
else T_XP = tCKE- 1
2
T_XSNR
tXSNR
Exit self refresh to a
non-read command
137.5 nS
(tXSNR × fDDR2/mDDR_CLK) - 1
18
T_XSRD
tXSRD
Exit self refresh to a read
command
200 (tCK cycles)
tXSRD - 1
199
T_RTP
tRTP
Read to precharge
command delay
15 nS
(tRTP × fDDR2/mDDR_CLK) - 1
1
T_CKE
tCKE
CKE minimum pulse width
3 (tCK cycles)
tCKE - 1
2
Description
DDR2/mDDR Memory Controller 355
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15.3.2.4 Configuring DDR PHY Control Register (DRPYC1R)
The DDR PHY control register (DRPYC1R) contains a read latency (RL) field that helps the DDR2/mDDR
memory controller determine when to sample read data. The RL field should be programmed to a value
equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency
plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to
these values minus 1). Table 15-21 shows the resulting DRPYC1R configuration.
When calculating round trip board delay the signals of primary concern are the differential clock signals
(DDR_CLK and DDR_CLK) and data strobe signals (DDR_DQS). For these signals, calculate the round
trip board delay from the DDR memory controller to the memory and then choose the maximum delay to
determine the RL value. In this example, we will assume the round trip board delay is one DDR_CLK
cycle; therefore, RL can be calculated as:
RL = CAS latency + round trip board delay – 1 = 4 + 1 – 1 = 4
Table 15-21. DRPYC1R Configuration
356
Field
Value
Function Selection
EXT_STRBEN
1h
Programs to select external strobe gating
RL
4h
Read latency is equal to CAS latency plus round trip board delay for data minus 1
PWRDNEN
0
Programmed to power up the DDR2/mDDR memory controller receivers
DDR2/mDDR Memory Controller
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15.4 Registers
Table 15-22 lists the memory-mapped registers for the DDR2/mDDR memory controller. Note that the
VTP IO control register (VTPIO_CTL) resides in the System Configuration Module.
Table 15-22. DDR2/mDDR Memory Controller Registers
Address Offset
(1)
Acronym
Register Description
0h
REVID
Revision ID Register
Section 15.4.1
Section
4h
SDRSTAT
SDRAM Status Register
Section 15.4.2
8h
SDCR
SDRAM Configuration Register
Section 15.4.3
Ch
SDRCR
SDRAM Refresh Control Register
Section 15.4.4
10h
SDTIMR1
SDRAM Timing Register 1
Section 15.4.5
14h
SDTIMR2
SDRAM Timing Register 2
Section 15.4.6
1Ch
SDCR2
SDRAM Configuration Register 2
Section 15.4.7
20h
PBBPR
Peripheral Bus Burst Priority Register
Section 15.4.8
40h
PC1
Performance Counter 1 Register
Section 15.4.9
44h
PC2
Performance Counter 2 Register
Section 15.4.10
48h
PCC
Performance Counter Configuration Register
Section 15.4.11
4Ch
PCMRS
Performance Counter Master Region Select Register
Section 15.4.12
50h
PCT
Performance Counter Time Register
Section 15.4.13
60h
DRPYRCR
DDR PHY Reset Control Register
Section 15.4.14
C0h
IRR
Interrupt Raw Register
Section 15.4.15
C4h
IMR
Interrupt Masked Register
Section 15.4.16
C8h
IMSR
Interrupt Mask Set Register
Section 15.4.17
CCh
IMCR
Interrupt Mask Clear Register
Section 15.4.18
E4h
DRPYC1R
DDR PHY Control Register 1
Section 15.4.19
01E2 C000h (1)
VTPIO_CTL
VTP IO Control Register
Section 11.5.19
01E2 C004h (1)
DDR_SLEW
DDR Slew Register
Section 11.5.20
This register resides in the register space of the System Configuration (SYSCFG) Module. It is listed in the register space of the
DDR2/mDDR controller because it is applicable to the DDR2/mDDR controller.
15.4.1 Revision ID Register (REVID)
The revision ID register (REVID) contains the current revision ID for the DDR2/mDDR memory controller.
The REVID is shown in Figure 15-20 and described in Table 15-23.
Figure 15-20. Revision ID Register (REVID)
31
0
REV
R-4031 1B1Fh
LEGEND: R = Read only; -n = value after reset
Table 15-23. Revision ID Register (REVID) Field Descriptions
Bit
Field
Value
31-0
REV
4031 1B1Fh
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Description
Revision ID value of the DDR2/mDDR memory controller.
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15.4.2 SDRAM Status Register (SDRSTAT)
The SDRAM status register (SDRSTAT) is shown in Figure 15-21 and described in Table 15-24.
Figure 15-21. SDRAM Status Register (SDRSTAT)
31
30
29
Rsvd
DUALCLK
Reserved
16
R-0
R-1
R-0
15
3
2
1
0
Reserved
PHYRDY
Reserved
R-0
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-24. SDRAM Status Register (SDRSTAT) Field Descriptions
Bit
Field
31
Reserved
30
DUALCLK
29-3
Reserved
2
PHYRDY
1-0
358
Reserved
Value
0
Description
Reserved
Dual clock. Specifies whether the VCLK and MCLK inputs are asynchronous. This bit should always be
read as 1.
0
VCLK and MCLK are not asynchronous.
1
VCLK and MCLK are asynchronous.
0
Reserved
DDR2/mDDR memory controller DLL ready. Specifies whether the DDR2/mDDR memory controller DLL
is powered up and locked.
0
DLL is not ready, either powered down, in reset, or not locked.
1
DLL is powered up, locked, and ready for operation.
0
Reserved
DDR2/mDDR Memory Controller
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15.4.3 SDRAM Configuration Register (SDCR)
The SDRAM configuration register (SDCR) contains fields that program the DDR2/mDDR memory
controller to meet the specification of the attached DDR2/mDDR memory. These fields configure the
DDR2/mDDR memory controller to match the data bus width, CAS latency, number of internal banks, and
page size of the attached DDR2/mDDR memory. Writing to the DDRDRIVE[1:0], CL, IBANK, and
PAGESIZE bit fields causes the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM
initialization sequence. The SDCR is shown in Figure 15-22 and described in Table 15-25.
Figure 15-22. SDRAM Configuration Register (SDCR)
31
27
26
25
24
Reserved
28
DDR2TERM1
IBANK_POS
MSDRAMEN
DDRDRIVE1
R-0
R/W-1
R/W-0
R/W-0
R/W-0
23
22
21
20
19
18
17
16
BOOTUNLOCK
DDR2DDQS
DDR2TERM0
DDR2EN
DDRDLL_DIS
DDRDRIVE0
DDREN
SDRAMEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
13
12
11
15
14
TIMUNLOCK
NM
Reserved
CL
Reserved
R/W-0
R/W-1
R-0
R/W-5h
R-0
7
6
4
3
9
2
8
0
Reserved
IBANK
Reserved
PAGESIZE
R-0
R/W-2h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-25. SDRAM Configuration Register (SDCR) Field Descriptions
Bit
31-28
Field
27
DDR2TERM1
26
IBANK_POS
25
Value
Reserved
0
0-3h
Description
Reserved
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM0 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDR2TERM0
bit. Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00
to disable the termination because the ODT feature is not supported.
Internal Bank position.
0
Normal addressing
1
Special addressing. Typically used with mobile DDR partial array self-refresh.
MSDRAMEN
Mobile SDRAM enable. Use this bit in conjunction with DDR2EN, DDREN, and SDRAMEN to
enable/disable mobile SDRAM. To change this bit value, use the following sequence:
1.
2.
24
DDRDRIVE1
23
BOOTUNLOCK
0
Disable mobile SDRAM
1
Enable mobile SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE0 bit to make a 2-bit field.
This bit is writeable only when the BOOTUNLOCK bit is unlocked. See the DDRDRIVE0 bit.
Boot Unlock. Controls the write permission settings for the DDR2TERM[1:0], MSDRAMEN,
DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and SDRAMEN bit fields. To
change these bits, use the following sequence:
1.
2.
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Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the MSDRAMEN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0],
MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN and
SDRAMEN bits.
0
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may not be changed.
1
DDR2TERM[1:0], MSDRAMEN, DDRDRIVE[1:0], DDR2DDQS, DDR2EN, DDRDLL_DIS, DDREN
and SDRAMEN bit fields may be changed.
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Table 15-25. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
22
DDR2DDQS
Value
Description
DDR2 SDRAM differential DQS enable. This bit is writeable only when the BOOTUNLOCK bit is
unlocked. To change this bit value, use the following sequence:
1.
2.
21
DDR2TERM0
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2DDQS bit.
0
Single-ended DQS
1
Reserved
0-3h
DDR2 termination resistor value. This bit is used in conjunction with the DDR2TERM1 bit to make a
2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2TERM[1:0] bits.
Note that the reset value of DDR2TERM[1:0] = 10, these bits must be cleared and forced to 00 to
disable the termination because the ODT feature is not supported.
0
1h-3h
20
DDR2EN
Disable termination
Reserved
DDR2 enable. This bit is used in conjunction with the DDREN and SDRAMEN bits to enable/disable
DDR2. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
1.
2.
19
0
Disable DDR2
1
Enable DDR2
DDRDLL_DIS
DLL disable for DDR SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked.
To change this bit value, use the following sequence:
1.
2.
18
DDRDRIVE0
Enable DLL
1
Disable DLL inside DDR SDRAM
0-3h
SDRAM drive strength. This bit is used in conjunction with the DDRDRIVE1 bit to make a 2-bit field.
The DDRDRIVE[1:0] bits configure the output driver impedance control value of the SDRAM
memory. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
0
For DDR2, normal drive strength. For mobile DDR, full drive strength.
For DDR2, weak drive strength. For mobile DDR, 1/2 drive strength.
2h
For DDR2, reserved. For mobile DDR, 1/4 drive strength.
3h
For DDR2, reserved. For mobile DDR, 3/4 drive strength.
DDREN
DDR enable. This bit is used in conjunction with the DDR2EN and SDRAMEN bits to enable/disable
DDR. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value,
use the following sequence:
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDREN bit.
0
Disable DDR
1
Enable DDR
SDRAMEN
SDRAM enable. This bit is used in conjunction with the DDR2EN and DDREN bits to enable/disable
SDRAM. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit
value, use the following sequence:
1.
2.
360
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDRIVE[1:0] bits.
1h
1.
2.
16
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDLL_DIS bit.
0
1.
2.
17
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDR2EN bit.
Write a 1 to the BOOTUNLOCK bit.
Write a 0 to the BOOTUNLOCK bit along with the desired value of the SDRAMEN bit.
0
Disable SDRAM
1
Enable SDRAM
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Table 15-25. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit
Field
15
TIMUNLOCK
Value
Description
Timing unlock. Controls the write permission settings for the CL bit field, and the SDRAM timing
register 1 (SDTIMR1) and the SDRAM timing register 2 (SDTIMR2) bit fields. To change these bits,
use the following sequence:
1.
2.
14
0
CL bit, and SDTIMR1 and SDTIMR2 bit fields may not be changed.
1
CL bit, and SDTIMR1 and SDTIMR2 bit fields may be changed.
NM
13-12
Reserved
11-9
CL
SDRAM data bus width.
0
Reserved
1
16-bit bus width.
0
Reserved
0-7h
SDRAM CAS latency. This bit is writeable only when the TIMUNLOCK bit is unlocked. To change
this bit value, use the following sequence:
1.
2.
0-1h
8-7
Reserved
6-4
IBANK
3
2-0
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit.
Reserved
2h
CAS Latency = 2
3h
CAS Latency = 3
4h
CAS Latency = 4
5h
CAS Latency = 5
6h-7h
Reserved
0
Reserved
0-7h
Internal SDRAM bank setup. Defines the number of internal banks on the external SDRAM device.
0
1 bank
1h
2 banks
2h
4 banks
3h
8 banks
4h-7h
Reserved
0
Reserved
Reserved
PAGESIZE
Write a 1 to the TIMUNLOCK bit.
Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit and SDTIMR1 and
SDTIMR2 bit fields.
0-7h
256-word page requiring 8 column address bits.
1h
512-word page requiring 9 column address bits.
2h
1024-word page requiring 10 column address bits.
3h
2048-word page requiring 11 column address bits.
4h-7h
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Page Size. Defines the page size of the SDRAM device.
0
Reserved
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15.4.4 SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) is used to configure the DDR2/mDDR memory controller to:
• Enter and Exit the self-refresh and power-down states.
• Enable and disable MCLK, stopping when in the self-refresh state.
• Meet the refresh requirement of the attached DDR2/mDDR device by programming the rate at which
the DDR2/mDDR memory controller issues autorefresh commands.
The SDRCR is shown in Table 15-26 and described in Figure 15-23.
Figure 15-23. SDRAM Refresh Control Register (SDRCR)
31
30
LPMODEN
MCLKSTOPEN
29
Reserved
24
SR_PD
23
22
Reserved
16
R/W-0
R/W-0
R-0
R/W-0
R-0
15
0
RR
R/W-884h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-26. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit
Field
31
LPMODEN
30
29-24
23
Value
Low-power mode enable.
0
Disable low-power mode.
1
Enable low-power mode. The state of bit SR_PD selects either self-refresh or power-down
mode.
MCLKSTOPEN
Reserved
MCLK stop enable.
0
Disables MCLK stopping, MCLK may not be stopped.
1
Enables MCLK stopping, MCLK may be stopped. The LPMODEN bit must be set to 1 before
setting the MCLKSTOPEN bit to 1.
0
Reserved
SR_PD
22-16
Reserved
15-0
RR
Description
Self-refresh or Power-down select. This bit is only in effect when the LPMODEN bit is set to 1;
this bit is ignored when the LPMODEN bit is cleared to 0.
0
Self-refresh mode.
1
Power-down mode.
0
Reserved
0-FFFFh
Refresh rate. Defines the rate at which the attached SDRAM devices will be refreshed. The
value of this field may be calculated with the following equation:
RR = SDRAM frequency/SDRAM refresh rate
where SDRAM refresh rate is derived from the SDRAM data sheet.
362
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15.4.5 SDRAM Timing Register 1 (SDTIMR1)
The SDRAM timing register 1 (SDTIMR1) configures the DDR2/mDDR memory controller to meet many of
the AC timing specification of the DDR2/mDDR memory. The SDTIMR1 is programmable only when the
TIMUNLOCK bit is set to 1 in the SDRAM configuration register (SDCR). Note that DDR_CLK is equal to
the period of the DDR_CLK signal. See the DDR2/mDDR memory data sheet for information on the
appropriate values to program each field. The SDTIMR1 is shown in Figure 15-24 and described in
Table 15-27.
Figure 15-24. SDRAM Timing Register 1 (SDTIMR1)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-Fh
R/W-2h
R/W-2h
R/W-2h
15
11
10
6
5
3
2
1
0
T_RAS
T_RC
T_RRD
Rsvd
T_WTR
R/W-6h
R/W-9h
R/W-1
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-27. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions
Bit
31-25
Field
Value
Description
T_RFC
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the trfc AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RFC = (trfc/DDR_CLK) - 1
24-22
T_RP
0-7h
21-19
T_RCD
0-7h
18-16
T_WR
0-7h
Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the trp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RP = (trp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the trcd AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RCD = (trcd/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the twr AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_WR = (twr/DDR_CLK) - 1
When the value of this field is changed from its previous value, the initialization sequence will begin.
15-11
T_RAS
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the tras AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RAS = (tras/DDR_CLK) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
5-3
T_RRD
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the trc AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RC = (trc/DDR_CLK) - 1
0-7h
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the trrd AC timing parameter in the DDR2/mDDR data
sheet. Calculate by:
T_RRD = (trrd/DDR_CLK) - 1
For an 8 bank DDR2/mDDR device, this field must be equal to ((4 × tRRD) + (2 × tCK)) / (4 × tCK) - 1.
2
1-0
Reserved
T_WTR
0
0-3h
Reserved
Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
Corresponds to the twtr AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_WTR = (twtr/DDR_CLK) - 1
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15.4.6 SDRAM Timing Register 2 (SDTIMR2)
Like the SDRAM timing register 1 (SDTIMR1), the SDRAM timing register 2 (SDTIMR2) also configures
the DDR2/mDDR memory controller to meet the AC timing specification of the DDR2/mDDR memory. The
SDTIMR2 is programmable only when the TIMUNLOCK bit is set to 1 in the SDRAM configuration register
(SDCR). Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2/mDDR data
sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 15-25
and described in Table 15-28.
Figure 15-25. SDRAM Timing Register 2 (SDTIMR2)
31
30
27
26
25
24
23
22
16
Rsvd
T_RASMAX
T_XP
T_ODT
T_XSNR
R-0
R/W-8h
R/W-2h
R/W-2h
R/W-32h
15
8
7
5
4
0
T_XSRD
T_RTP
T_CKE
R/W-A7h
R/W-1
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-28. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
Bit
Field
31
Reserved
30-27
T_RASMAX
Value
0
0-Fh
Description
Any writes to these bit(s) must always have a value of 0.
Specifies the maximum number of refresh rate intervals from Activate to Precharge command.
Corresponds to the tras AC timing parameter and the refresh rate in the DDR2/mDDR data sheet.
Calculate by:
T_RASMAX = (trasmax/refresh_rate) - 1
Round down to the nearest cycle.
26-25
T_XP
0-3h
Specifies the minimum number of DDR_CLK cycles from Power Down exit to any other command
except a read command, minus 1. Corresponds to the txp or tcke AC timing parameter in the
DDR2/mDDR data sheet. This field must satisfy the greater of tXP or tCKE.
If txp > tcke, then calculate by T_XP = txp - 1
If txp < tcke, then calculate by T_XP = tcke - 1
24-23
T_ODT
0-3h
Specifies the minimum number of DDR_CLK cycles from ODT enable to write data driven for DDR2
SDRAM. T_ODT must be equal to (CAS latency - tAOND -1). T_ODT must be less than CAS latency
minus 1. This feature is not supported because the DDR_ODT signal is not pinned out.
22-16
T_XSNR
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to any other command
except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2/mDDR
data sheet. Calculate by:
15-8
T_XSRD
0-FFh
7-5
T_RTP
0-7h
4-0
T_CKE
0-1Fh
T_XSNR = (txsnr/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles from a self_refresh exit to a read command, minus
1. Corresponds to the txsrd AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_XSRD = txsrd - 1
Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2/mDDR data sheet.
Calculate by:
T_RTP = (trtp/DDR_CLK) - 1
Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
Corresponds to the tcke AC timing parameter in the DDR2/mDDR data sheet. Calculate by:
T_CKE = tcke - 1
364
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15.4.7 SDRAM Configuration Register 2 (SDCR2)
The SDRAM configuration register 2 (SDCR2) contains fields to configure partial array self-refresh and
rowsize of the mDDR. This register is applicable only when the IBANK_POS bit in the SDRAM
configuration register (SDCR) is set to 1 for special addressing. Writing to the PASR and ROWSIZE bit
fields will cause the DDR2/mDDR memory controller to start the DDR2/mDDR SDRAM initialization
sequence. SDCR2 is shown in Figure 15-26 and described in Table 15-29.
Figure 15-26. SDRAM Configuration Register 2 (SDCR2)
31
19
18
16
Reserved
PASR
R-0
R/W-0
15
3
2
0
Reserved
ROWSIZE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-29. SDRAM Configuration Register 2 (SDCR2) Field Descriptions
Bit
Field
31-19
Reserved
18-16
PASR
Value
0
Description
Reserved
0-7h
Partial array self-refresh.
0
4 banks will be refreshed.
1h
2 banks will be refreshed.
2h
1 bank will be refreshed.
3h-4h
Reserved
5h
1/2 bank will be refreshed.
6h
1/4 bank will be refreshed.
7h
Reserved
Reserved
15-3
Reserved
0
2-0
ROWSIZE
0-7h
Row size. Defines the number of row address bit for DDR device.
0
9 row address bits
1h
10 row address bits
2h
11 row address bits
3h
12 row address bits
4h
13 row address bits
5h
14 row address bits
6h
15 row address bits
7h
16 row address bits
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15.4.8 Peripheral Bus Burst Priority Register (PBBPR)
The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the
DDR2/mDDR memory controller. To avoid command starvation, the DDR2/mDDR memory controller
momentarily raises the priority of the oldest command in the command FIFO after a set number of
transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made
before the DDR2/mDDR memory controller raises the priority of the oldest command. See
Section 15.2.6.2 for more details on command starvation.
Proper configuration of the PBBPR is critical to correct system operation. The DDR2/mDDR memory
controller always prioritizes accesses to open rows as highest, if there is any bank conflict regardless of
master priority. This is done to allow most efficient utilization of the DDR2/mDDR. However, it could lead
to excessive blocking of high priority masters. If the PR_OLD_COUNT bits are cleared to 00h, then the
DDR2/mDDR memory controller always honors the master priority, regardless of open row/bank status.
For most systems, the PBBPR should be set to a moderately low value to provide an acceptable balance
of DDR2/mDDR efficiency and latency for high priority masters (for example, 10h or 20h).
The PBBPR is shown in Figure 15-27 and described in Table 15-30.
Figure 15-27. Peripheral Bus Burst Priority Register (PBBPR)
31
16
Reserved
R-0
15
8
7
0
Reserved
PR_OLD_COUNT
R-0
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-30. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
PR_OLD_COUNT
Value
0
0-FFh
Description
Any writes to these bit(s) must always have a value of 0.
Priority raise old counter. Specifies the number of memory transfers after which the
DDR2/mDDR memory controller will elevate the priority of the oldest command in the command
FIFO. Clearing to 00h will ensure master priority is strictly honored (at the cost of decreased
DDR2/mDDR memory controller efficiency, as open row will always be closed immediately if
any bank conflict occurs). Recommended setting for typical system operation is between 10h
and 20h.
0
1 memory transfer
1h
2 memory transfers
2h
3 memory transfers
3h-FFh 4 to 256 memory transfers
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15.4.9 Performance Counter 1 Register (PC1)
For debug or gathering performance statistics, the PC1 and PC2 counters and associated configuration
registers are provided. These are intended for debug and analysis only. By configuring the performance
counter configuration register (PCC) to define the type of statistics to gather and configuring the
performance counter master region select register (PCMRS) to filter accesses only to specific chip select
regions, performing system applications and then reading these counters, different statistics can be
gathered. To reset the counters, you must reset (mod_g_rst_n) the DDR2/mDDR memory controller
through the PSC. For details on the PSC, see the Power and Sleep Controller (PSC) chapter.
The performance counter 1 register (PC1) is shown in Figure 15-28 and described in Table 15-31.
Figure 15-28. Performance Counter 1 Register (PC1)
31
0
Counter1
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-31. Performance Counter 1 Register (PC1) Field Descriptions
Bit
31-0
Field
Counter1
Value
Description
0-FFFF FFFFh
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
15.4.10 Performance Counter 2 Register (PC2)
The performance counter 2 register (PC2) is shown in Figure 15-29 and described in Table 15-32.
Figure 15-29. Performance Counter 2 Register (PC2)
31
0
Counter2
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-32. Performance Counter 2 Register (PC2) Field Descriptions
Bit
31-0
Field
Counter2
Value
0-FFFF FFFFh
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Description
32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register (PCMRS).
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15.4.11 Performance Counter Configuration Register (PCC)
The performance counter configuration register (PCC) is shown in Figure 15-30 and described in
Table 15-33.
Table 15-34 shows the possible filter configurations for the two performance counters. These filter
configurations can be used in conjunction with a Master ID and/or an external chip select to obtain
performance statistics for a particular master and/or an external chip select.
Figure 15-30. Performance Counter Configuration Register (PCC)
31
30
CNTR2_MSTID_EN
CNTR2_REGION_EN
29
Reserved
20
CNTR2_CFG
R/W-0
R/W-0
R-0
R/W-1
13
4
19
16
15
14
CNTR1_MSTID_EN
CNTR1_REGION_EN
Reserved
3
CNTR1_CFG
0
R/W-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-33. Performance Counter Configuration Register (PCC) Field Descriptions
Bit
Field
31
CNTR2_MSTID_EN
30
Value
Description
Master ID filter enable for performance counter 2 register (PC2). Refer to Table 15-34 for
details.
0
Master ID filter is disabled. PC2 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC2 counts accesses from the master, corresponding to the
Master ID value in the MST_ID2 bit field of the performance counter master region select
register (PCMRS).
CNTR2_REGION_EN
Chip select filter enable for performance counter 2 register (PC2). Refer to Table 15-34 for
details.
0
Chip select filter is disabled. PC2 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL2
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL2 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL2 = 0: PC2 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL2 = 7h: PC2 counts accesses to DDR2/mDDR memory controller
memory-mapped registers.
29-20
Reserved
19-16
CNTR2_CFG
15
14
0
0-Fh
CNTR1_MSTID_EN
Any writes to these bit(s) must always have a value of 0.
Filter configuration for performance counter 2 register (PC2). Refer to Table 15-34 for
details.
Master ID filter enable for performance counter 1 register (PC1). Refer to Table 15-34 for
details.
0
Master ID filter is disabled. PC1 counts accesses from all masters to DDR2/mDDR SDRAM.
1
Master ID filter is enabled. PC1 counts accesses from the master, corresponding to the
Master ID value in the MST_ID1 bit field of the performance counter master region select
register (PCMRS).
CNTR1_REGION_EN
Chip select filter enable for performance counter 1 register (PC1). Refer to Table 15-34 for
details.
0
Chip select filter is disabled. PC1 counts total number of accesses (DDR2/mDDR SDRAM +
DDR2/mDDR memory controller memory-mapped register accesses). The REGION_SEL1
bit field value in the performance counter master region select register (PCMRS) is a don’t
care.
1
Chip select filter is enabled. If the REGION_SEL1 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL1 = 0: PC1 counts accesses to DDR2/mDDR SDRAM memory.
REGION_SEL1 = 7h: PC1 counts accesses to DDR2/mDDR memory controller
memory-mapped registers.
13-4
368
Reserved
0
Any writes to these bit(s) must always have a value of 0.
DDR2/mDDR Memory Controller
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Table 15-33. Performance Counter Configuration Register (PCC) Field Descriptions (continued)
Bit
Field
3-0
CNTR1_CFG
Value
0-Fh
Description
Filter configuration for performance counter 1 register (PC1). Refer to Table 15-34 for
details.
Table 15-34. Performance Counter Filter Configuration
Performance Counter Configuration Register (PCC) Bit
CNTRn_CFG
CNTRn_REGION_EN
0
0
CNTRn_MSTID_EN Description
0 or 1
Counts the total number of READ/WRITE commands the
external memory controller receives.
The size of counter increments are determines by the size of the
transfer and the default burst size (DBS). The counter breaks up
transfers into sizes according to DBS. Therefore, counter
increments for transfers aligned to DBS are equal to the transfer
size divided by the DBS.
1h
0
0
Counts the total number of ACTIVATE commands the
external memory controller issues to DDR2/mDDR memory.
The counter increments by a value of 1 for every request to
read/write data to a closed bank in DDR2/mDDR memory by the
external memory controller.
2h
0 or 1
0 or 1
Counts the total number of READ commands (read accesses)
the DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size divided by the DBS.
3h
0 or 1
0 or 1
Counts the total number of WRITE commands the
DDR2/mDDR memory controller receives.
Counter increments for transfers aligned to the default burst size
(DBS) are equal to the transfer size of data written to the
DDR2/mDDR memory controller divided by the DBS.
4h
0
0
Counts the number of external memory controller cycles
(DDR_CLK cycles) that the command FIFO is full.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in a sample period
As the value of this counter approaches 100%, the DDR2/mDDR
memory controller is approaching a congestion point where the
command FIFO is full 100% of the time and a command will have
to wait at the SCR to be accepted in the command FIFO.
5h-7h
0
0
8h
0 or 1
0 or 1
Reserved
Counts the number of commands (requests) in the command
FIFO that require a priority elevation.
To avoid command starvation, the DDR2/mDDR memory
controller can momentarily raise the priority of the oldest
command in the command FIFO after a set number of transfers
have been made. The PR_OLD_COUNT bit field in the peripheral
bus burst priority register (PBBPR) sets the number of the
transfers that must be made before the DDR2/mDDR memory
controller will raise the priority of the oldest command.
9h
0
0
Counts the number of DDR2/mDDR memory controller cycles
(DDR_CLK cycles) that a command is pending in the
command FIFO. This counter increments every cycle the
command FIFO is not empty.
Use the following to calculate the counter value as a percentage:
% = counter value / total DDR_CLK cycles in sample period
As the value of this counter approaches 100%, the number of
cycles the DDR2/mDDR memory controller has a command in the
command FIFO to service approaches 100%.
Ah-Fh
0
0
Reserved
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15.4.12 Performance Counter Master Region Select Register (PCMRS)
The performance counter master region select register (PCMRS) is shown in Figure 15-31 and described
in Table 15-35.
Figure 15-31. Performance Counter Master Region Select Register (PCMRS)
31
24
23
20
19
16
MST_ID2
Reserved
REGION_SEL2
R/W-0
R-0
R/W-0
15
8
7
4
3
0
MST_ID1
Reserved
REGION_SEL1
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-35. Performance Counter Master Region Select Register (PCMRS) Field Descriptions
Bit
Field
Value
Description
31-24
MST_ID2
0-FFh
Master ID for performance counter 2 register (PC2). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
23-20
Reserved
0
Any writes to these bit(s) must always have a value of 0.
19-16
REGION_SEL2
0-Fh
Region select for performance counter 2 register (PC2).
0
1h-6h
7h
15-8
MST_ID1
7-4
Reserved
3-0
REGION_SEL1
Reserved
PC2 counts total DDR2/mDDR memory controller memory-mapped register accesses.
8h-Fh
Reserved
0-FFh
Master ID for performance counter 1 register (PC1). For the Master ID value for master peripherals
in the device, see the System Configuration (SYSCFG) Module chapter.
0
Any writes to these bit(s) must always have a value of 0.
0-Fh
Region select for performance counter 1 register (PC1).
0
1h-6h
7h
8h-Fh
370
PC2 counts total DDR2/mDDR accesses.
PC1 counts total DDR2/mDDR accesses.
Reserved
PC1 counts total DDR2/mDDR memory controller memory-mapped register accesses.
Reserved
DDR2/mDDR Memory Controller
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15.4.13 Performance Counter Time Register (PCT)
The performance counter time register (PCT) is shown in Figure 15-32 and described in Table 15-36.
Figure 15-32. Performance Counter Time Register (PCT)
31
0
TOTAL_TIME
R-0
LEGEND: R = Read only; -n = value after reset
Table 15-36. Performance Counter Time Register (PCT) Field Description
Bit
31-0
Field
Value
TOTAL_TIME
Description
0-FFFF FFFFh
32-bit counter that continuously counts number for DDR_CLK cycles elapsed after the
DDR2/mDDR memory controller is brought out of reset.
15.4.14 DDR PHY Reset Control Register (DRPYRCR)
The DDR PHY reset control register (DRPYRCR) is used to reset the DDR PHY. The DRPYRCR is shown
in Figure 15-33 and described in Table 15-37.
Figure 15-33. DDR PHY Reset Control Register (DRPYRCR)
31
16
Reserved
R-0
15
11
10
9
0
Reserved
RESET_PHY
Reserved
R-04h
R/W-0
R-091h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-37. DDR PHY Reset Control Register (DRPYRCR)
Bit
31-11
10
9-0
Field
Reserved
Value
0000 04h
RESET_PHY
Reserved
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Description
Always write the default value to these bits.
Reset DDR PHY.
0
No effect.
1
Resets DDR PHY.
091h
Always write the default value to these bits.
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15.4.15 Interrupt Raw Register (IRR)
The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs,
the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is
shown in Figure 15-34 and described in Table 15-38.
Figure 15-34. Interrupt Raw Register (IRR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LT
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 15-38. Interrupt Raw Register (IRR) Field Descriptions
Bit
31-3
2
1-0
Field
Reserved
Value
0
Reserved
LT
Reserved
Description
Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type. See Section 15.2.14 for more details.
0
Reserved
15.4.16 Interrupt Masked Register (IMR)
The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt
condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR
bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in Figure 15-35
and described in Table 15-39.
Figure 15-35. Interrupt Masked Register (IMR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTM
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 15-39. Interrupt Masked Register (IMR) Field Descriptions
Bit
31-3
2
1-0
372
Field
Reserved
Value
0
LTM
Reserved
Description
Reserved
Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
has no effect.
0
A line trap condition has not occurred.
1
Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 15.2.14 for more
details.
0
Reserved
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15.4.17 Interrupt Mask Set Register (IMSR)
The interrupt mask set register (IMSR) enables the DDR2/mDDR memory controller interrupt. The IMSR is
shown in Figure 15-36 and described in Table 15-40.
NOTE: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask
clear register (IMCR), the interrupt is not enabled and neither bit is set to 1.
Figure 15-36. Interrupt Mask Set Register (IMSR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMSET
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-40. Interrupt Mask Set Register (IMSR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMSET
1-0
Reserved
Value
0
Description
Reserved
Line trap interrupt set. Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register
(IMCR); a write of 0 has no effect.
0
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred.
1
Line trap interrupt is enabled.
0
Reserved
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15.4.18 Interrupt Mask Clear Register (IMCR)
The interrupt mask clear register (IMCR) disables the DDR2/mDDR memory controller interrupt. Once an
interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 15-37
and described in Table 15-41.
NOTE: If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set
register (IMSR), the interrupt is not enabled and neither bit is set to 1.
Figure 15-37. Interrupt Mask Clear Register (IMCR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMCLR
Reserved
R-0
R/W1C-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 15-41. Interrupt Mask Clear Register (IMCR) Field Descriptions
Bit
Field
31-3
Reserved
2
LTMCLR
1-0
374
Reserved
Value
0
Description
Reserved
Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
register (IMSR); a write of 0 has no effect.
0
Line trap interrupt is not enabled.
1
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
0
Reserved
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15.4.19 DDR PHY Control Register (DRPYC1R)
The DDR PHY control register 1 (DRPYC1R) configures the DDR2/mDDR memory controller read latency.
The DRPYC1R is shown in Figure 15-38 and described in Table 15-42.
Figure 15-38. DDR PHY Control Register 1 (DRPYC1R)
31
16
Reserved
R-0
15
7
6
Reserved
8
EXT_STRBEN
PWRDNEN
5
Reserved
3
2
RL
0
R-0
R/W-0
R/W-1
R-0
R/W-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-42. DDR PHY Control Register 1 (DRPYC1R) Field Descriptions
Bit
31-8
7
6
Field
Value
Reserved
0
EXT_STRBEN
Reserved
2-0
RL
Reserved
Internal/External strobe gating.
0
Internal strobe gating mode.
1
External strobe gating mode.
PWRDNEN
5-3
Description
Power down receivers.
0
Receivers powered up when idle.
1
Receivers powered down when idle.
0
Reserved
0-7h
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Read latency. Read latency is equal to CAS latency plus round trip board delay for data minus 1.
The maximum value of read latency that is supported is CAS latency plus 2. The minimum read
latency value that is supported is CAS latency plus 1. The read latency value is defined in number
of MCLK/DDR_CLK cycles.
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Chapter 16
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Enhanced Capture (eCAP) Module
The enhanced capture (eCAP) module is essential in systems where accurate timing of external events is
important. This chapter describes the eCAP module.
Topic
16.1
16.2
16.3
16.4
...........................................................................................................................
Introduction ....................................................................................................
Architecture ....................................................................................................
Applications ....................................................................................................
Registers ........................................................................................................
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378
379
388
404
377
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16.1 Introduction
16.1.1 Purpose of the Peripheral
Uses for eCAP include:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
16.1.2 Features
The eCAP module includes the following features:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event time-stamps
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources dedicated to a single input pin
• When not used in capture mode, the ECAP module can be configured as a single channel PWM output
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16.2 Architecture
The eCAP module represents one complete capture channel that can be instantiated multiple times
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
• Dedicated input capture pin
• 32-bit time base counter
• 4 × 32-bit time-stamp capture registers (CAP1-CAP4)
• 4-stage sequencer (Modulo4 counter) that is synchronized to external events, ECAP pin rising/falling
edges.
• Independent edge polarity (rising/falling edge) selection for all 4 events
• Input capture signal prescaling (from 2-62)
• One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
• Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme
• Interrupt capabilities on any of the 4 capture events
Multiple identical eCAP modules can be contained in a system as shown in Figure 16-1. The number of
modules is device-dependent and is based on target application needs. In this chapter, the letter x within a
signal or module name is used to indicate a generic eCAP instance on a device.
Figure 16-1. Multiple eCAP Modules
VBus32
From EPWM
SyncIn
ECAP1
module
ECAP1
ECAP1INT
SyncOut
SyncIn
Interrupt
Controller
ECAP2/
APWM2
module
ECAP2
GPIO
MUX
ECAP2INT
SyncOut
SyncIn
ECAPx/
APWMx
module
ECAPx
ECAPxINT
SyncOut
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16.2.1 Capture and APWM Operating Mode
You can use the eCAP module resources to implement a single-channel PWM generator (with 32 bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 16-2 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 16-2. Capture and APWM Modes of Operation
SyncIn
Capture
mode
Counter (”timer”)
32
Note:
Same pin
depends on
operating
mode
CAP1 reg
CAP2 reg
CAP3 reg
Sequencing
Edge detection
Edge polarity
Prescale
ECAPx
pin
CAP4 reg
ECAPxINT
Interrupt I/F
Or
SyncIn
APWM
mode
Counter (”timer”)
32
Syncout
Period reg
(active) (”CAP1”)
Compare reg
(active) (”CAP2”)
Period reg
(shadow) (”CAP3”)
PWM
Compare logic
APWMx
pin
Compare reg
(shadow) (”CAP4”)
ECAPxINT
380
Interrupt I/F
(1)
A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it
is an output.
(2)
In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 invokes the shadow mode.
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16.2.2 Capture Mode Description
Figure 16-3 shows the various components that implement the capture function.
Figure 16-3. Capture Function Diagram
ECCTL2[SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
SYNC
CTRPHS
(phase register-32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
TSCTR
(counter-32 bit)
SYNCOut
PRD [0-31]
Delta-mode
RST
CTR [0-31]
PWM
compare
logic
CMP [0-31]
32
CTR=PRD
CTR [0-31]
CTR=CMP
32
PRD [0-31]
ECCTL1 [ CAPLDEN, CTRRSTx]
CAP1
(APRD active)
APRD
shadow
LD1
Polarity
select
LD2
Polarity
select
LD
MODE SELECT
ECAPx
32
32
CMP [0-31]
32
32
CAP2
(ACMP active)
32
32
32
LD
Event
qualifier
ACMP
shadow
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Event
Prescale
Polarity
select
LD3
LD4
ECCTL1[EVTPS]
Polarity
select
4
Capture events
Edge Polarity Select
ECCTL1[CAPxPOL]
4
CEVT[1:4]
to Interrupt
Controller
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
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16.2.2.1 Event Prescaler
An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler. This is useful when very high frequency signals are used as inputs. Figure 16-4 shows a
functional diagram and Figure 16-5 shows the operation of the prescale function.
Figure 16-4. Event Prescale Control
Event prescaler
0
PSout
1
By−pass
ECAPx pin
(from GPIO)
/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)
(1)
When a prescale value of 1 is chosen (ECCTL1[13:9] = 0000) the input capture signal by-passes the
prescale logic completely.
Figure 16-5. Prescale Function Waveforms
ECAPx
PSout
div 2
PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10
382
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16.2.2.2 Edge Polarity Select and Qualifier
• Four independent edge polarity (rising edge/falling edge) selection multiplexers are used, one for each
capture event.
• Each edge (up to 4) is event qualified by the Modulo4 sequencer.
• The edge event is gated to its respective CAPn register by the Mod4 counter. The CAPn register is
loaded on the falling edge.
16.2.2.3
•
•
•
Continuous/One-Shot Control
The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
The continuous/one-shot block (Figure 16-6) controls the start/stop and reset (zero) functions of the Mod4
counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed
via software control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 16-6. Continuous/One-shot Block Diagram
0 1 2 3
2:4 MUX
2
CEVT1
CEVT2
CEVT3
CEVT4
CLK
Modulo 4
counter Stop
RST
Mod_eq
One−shot
control logic
Stop value (2b)
ECCTL2[STOP_WRAP]
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ECCTL2[RE−ARM]
ECCTL2[CONT/ONESHT]
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16.2.2.4 32-Bit Counter and Phase Control
This counter (Figure 16-7) provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.
Figure 16-7. Counter and Synchronization Block Diagram
SYNC
ECCTL2[SWSYNC]
ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable
ECCTL2[SYNCI_EN]
SYNCO
Sync out
select
CTRPHS
LD_CTRPHS
RST
Delta−mode
TSCTR
(counter 32b)
SYSCLK
CLK
OVF
CTR−OVF
CTR[31−0]
384
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16.2.2.5 CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a
time-stamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this
bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.
16.2.2.6 Interrupt Control
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events
(CTR = PRD, CTR = CMP). See Figure 16-8.
A counter overflow event (FFFF FFFFh->0000 0000h) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer qualified (that is, ordered in time) by the polarity select and
Mod4 gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPn module) going to the
interrupt controller.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR = PRD, CTR = CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated to the interrupt controller only if any of the
interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must
clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any
other interrupt pulses are generated. You can force an interrupt event via the interrupt force register
(ECFRC). This is useful for test purposes.
16.2.2.7 Shadow Load and Lockout Control
In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
• Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
• On period equal, CTR[31:0] = PRD[31:0]
NOTE: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode
(ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM
mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes.
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Figure 16-8. Interrupts in eCAP Module
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT1
ECFLG
Clear
ECCLR
ECFRC
Latch
ECFLG
ECEINT
ECCLR
Set
ECFLG
Clear
Clear
Latch
ECEINT
Generate
interrupt
pulse when
input=1
ECCLR
ECFRC
Latch
Set
ECAPxINT
CEVT2
1
Set
CEVT3
ECFLG
0
Clear
0
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT4
ECFLG
Clear
ECCLR
ECFRC
Latch
CTROVF
Set
ECEINT
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
PRDEQ
Set
ECFLG
Clear
Latch
ECEINT
386
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Set
ECCLR
ECFRC
CMPEQ
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16.2.2.8 APWM Mode Operation
Main operating highlights of the APWM section:
• The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
• When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
• Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers either immediately upon a write, or on a CTR = PRD
trigger.
• In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
• During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 16-9. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
The behavior of APWM active-high mode (APWMPOL == 0) is:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period
The behavior of APWM active-low mode (APWMPOL == 1) is:
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
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CMP > PERIOD+1, output low for complete period
16.3 Applications
The following sections will provide Applications examples and code snippets to show how to configure and
operate the eCAP module. For clarity and ease of use, below are useful #defines which will help in the
understanding of the examples.
388
// ECCTL1 ( ECAP Control Reg 1)
//==========================
// CAPxPOL bits
#define
EC_RISING
#define
EC_FALLING
0x0
0x1
// CTRRSTx bits
#define
EC_ABS_MODE
#define
EC_DELTA_MODE
0x0
0x1
// PRESCALE bits
#define
EC_BYPASS
#define
EC_DIV1
#define
EC_DIV2
#define
EC_DIV4
#define
EC_DIV6
#define
EC_DIV8
#define
EC_DIV10
0x0
0x0
0x1
0x2
0x3
0x4
0x5
// ECCTL2 ( ECAP Control Reg 2)
//==========================
// CONT/ONESHOT bit
#define
EC_CONTINUOUS
#define
EC_ONESHOT
0x0
0x1
// STOPVALUE bit
#define
EC_EVENT1
#define
EC_EVENT2
#define
EC_EVENT3
#define
EC_EVENT4
0x0
0x1
0x2
0x3
// RE-ARM bit
#define
EC_ARM
0x1
// TSCTRSTOP bit
#define
EC_FREEZE
#define
EC_RUN
0x0
0x1
// SYNCO_SEL bit
#define
EC_SYNCIN
#define
EC_CTR_PRD
#define
EC_SYNCO_DIS
0x0
0x1
0x2
// CAP/APWM mode bit
#define
EC_CAP_MODE
#define
EC_APWM_MODE
0x0
0x1
// APWMPOL bit
#define
EC_ACTV_HI
#define
EC_ACTV_LO
0x0
0x1
// Generic
#define
EC_DISABLE
#define
EC_ENABLE
#define
EC_FORCE
0x0
0x1
0x1
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16.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
Figure 16-10 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFF FFFFh (maximum value), it wraps around to 0000 0000h (not
shown in Figure 16-10), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
time-stamps are valid at the point indicated by the diagram, after the 4th event, hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPn registers.
Figure 16-10. Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
CEVT1
CEVT2
CEVT3
CEVT4
CEVT1
CAPx pin
t5
t4
FFFFFFFF
t3
t2
t1
CTR[0−31]
00000000
MOD4
CTR
CAP1
0
1
2
XX
3
0
1
t5
t1
CAP2
XX
t2
XX
CAP3
t3
XX
CAP4
t4
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 16-1. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-1. Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising edge trigger
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt2-TSt1;
Period2 = TSt3-TSt2;
Period3 = TSt4-TSt3;
390
captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate 2nd period
// Calculate 3rd period
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16.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
In Figure 16-11 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information:
Period1 = t3 – t1, Period2 = t5 – t3, …etc. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x 100%, etc. Duty
Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, etc.
Figure 16-11. Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT1
CEVT4
CEVT1
CEVT3
CAPx pin
FFFFFFFF
t6
t5
CTR[0−31]
t3
t9
t8
t7
t4
t2
t1
00000000
MOD4
CTR
CAP1
CAP2
0
1
2
XX
3
0
1
t1
XX
0
t6
t3
XX
CAP4
3
t5
t2
XX
CAP3
2
t7
t4
t8
tt
Polarity selection
Capture registers [1−4]
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Table 16-2. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_ABS_MODE
ECCTL1
CTRRST2
EC_ABS_MODE
ECCTL1
CTRRST3
EC_ABS_MODE
ECCTL1
CTRRST4
EC_ABS_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-2. Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising & Falling edge triggers
// Run Time ( e.g. CEVT4 triggered ISR call)
//==========================================
TSt1 = ECAPxRegs.CAP1;
// Fetch Time-Stamp
TSt2 = ECAPxRegs.CAP2;
// Fetch Time-Stamp
TSt3 = ECAPxRegs.CAP3;
// Fetch Time-Stamp
TSt4 = ECAPxRegs.CAP4;
// Fetch Time-Stamp
Period1 = TSt3-TSt1;
DutyOnTime1 = TSt2-TSt1;
DutyOffTime1 = TSt3-TSt2;
392
captured
captured
captured
captured
at
at
at
at
t1
t2
t3
t4
// Calculate 1st period
// Calculate On time
// Calculate Off time
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16.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
Figure 16-12 shows how the eCAP module can be used to collect Delta timing data from pulse train
waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter
wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here
Capture events are qualified as Rising edge only. On an event, TSCTR contents (time-stamp) is captured
first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If TSCTR
reaches FFFF FFFFh (maximum value), before the next event, it wraps around to 0000 0000h and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPn contents directly give timing data without the need for CPU
calculations: Period1 = T1, Period2 = T2,…etc. As shown in Figure 16-12, the CEVT1 event is a good
trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 16-12. Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
CEVT1
CEVT3
CEVT2
CEVT4
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T2
T4
CTR[0−31]
00000000
MOD4
CTR
CAP1
0
1
2
XX
3
0
1
CTR value at CEVT1
t4
XX
CAP2
t1
XX
CAP3
t2
XX
CAP4
t3
t
Polarity selection
Capture registers [1−4]
All capture values valid
(can be read) at this time
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Table 16-3. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_RISING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_RISING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-3. Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
// Code snippet for CAP mode Delta Time, Rising edge trigger
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Period value.
Period4 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
Period1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
Period2 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
Period3 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
394
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T2
T3
T4
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16.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
In Figure 16-13 the eCAP operating mode is almost the same as in previous section except Capture
events are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle
information: Period1 = T1 + T2, Period2 = T3 + T4, …etc Duty Cycle1 (on-time %) = T1 / Period1 × 100%,
etc Duty Cycle1 (off-time %) = T2 / Period1 × 100%, etc
During initialization, you must write to the active registers for both period and compare. This will then
automatically copy the init values into the shadow values. For subsequent compare updates, that is,
during run-time, only the shadow registers must be used.
Figure 16-13. Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
CEVT2
CEVT4
CEVT1
CEVT2
CEVT3
CEVT4
CEVT5
CEVT3
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T5
T8
T2
T6
T4
T7
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
0
1
XX
2
3
0
1
2
CAP3
CAP4
t5
t1
XX
t2
XX
0
t4
CTR value at CEVT1
XX
3
t6
t3
t7
t
Polarity selection
Capture registers [1−4]
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Table 16-4. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
Register
Bit
Value
ECCTL1
CAP1POL
EC_RISING
ECCTL1
CAP2POL
EC_FALLING
ECCTL1
CAP3POL
EC_RISING
ECCTL1
CAP4POL
EC_FALLING
ECCTL1
CTRRST1
EC_DELTA_MODE
ECCTL1
CTRRST2
EC_DELTA_MODE
ECCTL1
CTRRST3
EC_DELTA_MODE
ECCTL1
CTRRST4
EC_DELTA_MODE
ECCTL1
CAPLDEN
EC_ENABLE
ECCTL1
PRESCALE
EC_DIV1
ECCTL2
CAP_APWM
EC_CAP_MODE
ECCTL2
CONT_ONESHT
EC_CONTINUOUS
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-4. Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Delta Time, Rising and Falling edge triggers
// Run Time ( e.g. CEVT1 triggered ISR call)
//==========================================
// Note: here Time-stamp directly represents the Duty cycle values.
DutyOnTime1 = ECAPxRegs.CAP2;
// Fetch Time-Stamp captured at
DutyOffTime1 = ECAPxRegs.CAP3;
// Fetch Time-Stamp captured at
DutyOnTime2 = ECAPxRegs.CAP4;
// Fetch Time-Stamp captured at
DutyOffTime2 = ECAPxRegs.CAP1;
// Fetch Time-Stamp captured at
T2
T3
T4
T1
Period1 = DutyOnTime1 + DutyOffTime1;
Period2 = DutyOnTime2 + DutyOffTime2;
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16.3.5
16.3.5.1
Application of the APWM Mode
Simple PWM Generation (Independent Channel/s) Example
In this example, the eCAP module is configured to operate as a PWM generator. Here a very simple
single channel PWM waveform is generated from output pin APWMn. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time.
Figure 16-14. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
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Table 16-5. ECAP Initialization for APWM Mode
Register
Bit
Value
0x1000
CAP1
CAP1
CTRPHS
CTRPHS
0x0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-5. Code Snippet for APWM Mode
// Code snippet for APWM mode Example 1
// Run Time (Instant 1, e.g. ISR call)
//======================
ECAPxRegs.CAP2 = 0x300;
// Set Duty cycle i.e. compare value
// Run Time (Instant 2, e.g. another ISR call)
//======================
ECAPxRegs.CAP2 = 0x500;
// Set Duty cycle i.e. compare value
16.3.5.2
Multichannel PWM Generation with Synchronization Example
Figure 16-15 takes advantage of the synchronization feature between eCAP modules. Here 4 independent
PWM channels are required with different frequencies, but at integer multiples of each other to avoid
"beat" frequencies. Hence one eCAP module is configured as the Master and the remaining 3 are Slaves
all receiving their synch pulse (CTR = PRD) from the master. Note the Master is chosen to have the lower
frequency (F1 = 1/20,000) requirement. Here Slave2 Freq = 2 × F1, Slave3 Freq = 4 × F1 and Slave4
Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is
shown.
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Figure 16-15. Multichannel PWM Example Using 4 eCAP Modules
DC bus
Motor
dc
brush
APWM1
Motor
dc
brush
APWM2
Motor
dc
brush
APWM3
Motor
dc
brush
APWM4
TSCTR
FFFF FFFFh
Master APWM(1) module
20,000
APRD(1)
ACMP(1)
0000 0000
7,000
APWM1
(o/p pin)
CTR=PRD
(SyncOut)
Time
Phase = 0°
Slave APWM(2−4) module/s
10,000
APRD(2)
0
5,000
APRD(3)
0
4,000
APRD(4)
Time
0
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Table 16-6. ECAP1 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
20000
CAP1
CAP1
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 16-7. ECAP2 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
10000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 16-8. ECAP3 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
5000
CAP1
CAP1
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 16-9. ECAP4 Initialization for Multichannel PWM Generation with Synchronization
Register
Bit
Value
CAP1
CAP1
4000
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
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Example 16-6. Code Snippet for Multichannel PWM Generation with Synchronization
// Code snippet for APWM mode Example 2
// Run Time (Note: Example execution of one run-time instant)
//============================================================
ECAP1Regs.CAP2 = 7000;
// Set Duty cycle i.e., compare value
ECAP2Regs.CAP2 = 2000;
// Set Duty cycle i.e., compare value
ECAP3Regs.CAP2 = 550;
// Set Duty cycle i.e., compare value
ECAP4Regs.CAP2 = 6500;
// Set Duty cycle i.e., compare value
16.3.5.3
=
=
=
=
7000
2000
550
6500
Multichannel PWM Generation with Phase Control Example
In Figure 16-16, the Phase control feature of the APWM mode is used to control a 3 phase Interleaved
DC/DC converter topology. This topology requires each phase to be off-set by 120° from each other.
Hence if “Leg” 1 (controlled by APWM1) is the reference Leg (or phase), that is, 0°, then Leg 2 need 120°
off-set and Leg 3 needs 240° off-set. The waveforms in Figure 16-16 show the timing relationship between
each of the phases (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves
(modules 2, 3) whenever TSCTR = Period value.
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Figure 16-16. Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
Comple−
mentary
and
deadband
logic
APWM1
APWM2
APWM3
Vout
TSCTR
APRD(1)
APRD(1)
1200
700
SYNCO pulse
(CTR=PRD)
APWM1
Φ2=120°
CTRPHS(2)=800
APWM2
Φ3=240°
CTRPHS(3)=400
APWM3
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Table 16-10. ECAP1 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
1200
CAP1
CAP1
CTRPHS
CTRPHS
0
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_DISABLE
ECCTL2
SYNCO_SEL
EC_CTR_PRD
ECCTL2
TSCTRSTOP
EC_RUN
Table 16-11. ECAP2 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
CAP1
CAP1
1200
CTRPHS
CTRPHS
800
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCI
ECCTL2
TSCTRSTOP
EC_RUN
Table 16-12. ECAP3 Initialization for Multichannel PWM Generation with Phase Control
Register
Bit
Value
1200
CAP1
CAP1
CTRPHS
CTRPHS
400
ECCTL2
CAP_APWM
EC_APWM_MODE
ECCTL2
APWMPOL
EC_ACTV_HI
ECCTL2
SYNCI_EN
EC_ENABLE
ECCTL2
SYNCO_SEL
EC_SYNCO_DIS
ECCTL2
TSCTRSTOP
EC_RUN
Example 16-7. Code Snippet for Multichannel PWM Generation with Phase Control
// Code snippet for APWM mode Example 3
// Run Time (Note: Example execution of one run-time instant)
//============================================================
// All phases are set to the same duty cycle
ECAP1Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP2Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
ECAP3Regs.CAP2 = 700;
// Set Duty cycle i.e. compare value = 700
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16.4 Registers
Table 16-13 shows the eCAP module control and status register set. All 32-bit registers are aligned on
even address boundaries and are organized in little-endian mode. The 16 least-significant bits of a 32-bit
register are located on lowest address (even address).
NOTE:
In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the
shadow registers CAP3/CAP4 invokes the shadow mode.
Table 16-13. Control and Status Register Set
Offset
Acronym
0h
TSCTR
4h
CTRPHS
8h
CAP1
Ch
Description
Size (×16)
Section
Time-Stamp Counter Register
2
Section 16.4.1
Counter Phase Offset Value Register
2
Section 16.4.2
Capture 1 Register
2
Section 16.4.3
CAP2
Capture 2 Register
2
Section 16.4.4
10h
CAP3
Capture 3 Register
2
Section 16.4.5
14h
CAP4
Capture 4 Register
2
Section 16.4.6
28h
ECCTL1
Capture Control Register 1
1
Section 16.4.7
Section 16.4.8
2Ah
ECCTL2
Capture Control Register 2
1
2Ch
ECEINT
Capture Interrupt Enable Register
1
Section 16.4.9
2Eh
ECFLG
Capture Interrupt Flag Register
1
Section 16.4.10
30h
ECCLR
Capture Interrupt Clear Register
1
Section 16.4.11
32h
ECFRC
Capture Interrupt Force Register
1
Section 16.4.12
5Ch
REVID
Revision ID Register
2
Section 16.4.13
16.4.1 Time-Stamp Counter Register (TSCTR)
The time-stamp counter register (TSCTR) is shown in Figure 16-17 and described in Table 16-14.
Figure 16-17. Time-Stamp Counter Register (TSCTR)
31
0
TSCTR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-14. Time-Stamp Counter Register (TSCTR) Field Descriptions
Bit
31-0
404
Field
TSCTR
Value
0-FFFF FFFFh
Description
Active 32-bit counter register that is used as the capture time-base
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16.4.2 Counter Phase Control Register (CTRPHS)
The counter phase control register (CTRPHS) is shown in Figure 16-18 and described in Table 16-15.
Figure 16-18. Counter Phase Control Register (CTRPHS)
31
0
CTRPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-15. Counter Phase Control Register (CTRPHS) Field Descriptions
Bit
31-0
Field
CTRPHS
Value
0-FFFF FFFFh
Description
Counter phase value register that can be programmed for phase lag/lead. This register
shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a
control bit. Used to achieve phase control synchronization with respect to other eCAP and
EPWM time-bases.
16.4.3 Capture 1 Register (CAP1)
The capture 1 register (CAP1) is shown in Figure 16-19 and described in Table 16-16.
Figure 16-19. Capture 1 Register (CAP1)
31
0
CAP1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-16. Capture 1 Register (CAP1) Field Descriptions
Bit
Field
Value
31-0
CAP1
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• APRD active register when used in APWM mode
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16.4.4 Capture 2 Register (CAP2)
The capture 2 register (CAP2) is shown in Figure 16-20 and described in Table 16-17.
Figure 16-20. Capture 2 Register (CAP2)
31
0
CAP2
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-17. Capture 2 Register (CAP2) Field Descriptions
Bit
Field
Value
31-0
CAP2
0-FFFF FFFFh
Description
This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• ACMP active register when used in APWM mode
16.4.5 Capture 3 Register (CAP3)
The capture 3 register (CAP3) is shown in Figure 16-21 and described in Table 16-18.
Figure 16-21. Capture 3 Register (CAP3)
31
0
CAP3
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-18. Capture 3 Register (CAP3) Field Descriptions
Bit
Field
Value
31-0
CAP3
0-FFFF FFFFh
406
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow
(APRD) register. You update the PWM period value through this register. In this mode, CAP3
shadows CAP1.
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16.4.6 Capture 4 Register (CAP4)
The capture 4 register (CAP4) is shown in Figure 16-22 and described in Table 16-19.
Figure 16-22. Capture 4 Register (CAP4)
31
0
CAP4
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-19. Capture 4 Register (CAP4) Field Descriptions
Bit
Field
Value
31-0
CAP4
0-FFFF FFFFh
Description
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare
shadow (ACMP) register. You update the PWM compare value through this register. In this
mode, CAP4 shadows CAP2.
16.4.7 ECAP Control Register 1 (ECCTL1)
The ECAP control register 1 (ECCTL1) is shown in Figure 16-23 and described in Table 16-20.
Figure 16-23. ECAP Control Register 1 (ECCTL1)
15
14
13
9
8
FREE/SOFT
PRESCALE
CAPLDEN
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CTRRST4
CAP4POL
CTRRST3
CAP3POL
CTRRST2
CAP2POL
CTRRST1
CAP1POL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-20. ECAP Control Register 1 (ECCTL1) Field Descriptions
Bit
15-14
13-9
Field
FREE/SOFT
PRESCALE
Value
0-3h
Description
Emulation Control
0
TSCTR counter stops immediately on emulation suspend
1h
TSCTR counter runs until = 0
2h-3h
TSCTR counter is unaffected by emulation suspend (Run Free)
0-1Fh
Event Filter prescale select
0
Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1
Divide by 2
2h
Divide by 4
3h
Divide by 6
4h
Divide by 8
5h
Divide by 10
...
8
1Eh
Divide by 60
1Fh
Divide by 62
CAPLDEN
Enable Loading of CAP1-4 registers on a capture event
0
Disable CAP1-4 register loads at capture event time.
1
Enable CAP1-4 register loads at capture event time.
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Table 16-20. ECAP Control Register 1 (ECCTL1) Field Descriptions (continued)
Bit
7
6
5
4
3
2
1
0
408
Field
Value
CTRRST4
Description
Counter Reset on Capture Event 4
0
Do not reset counter on Capture Event 4 (absolute time stamp operation)
1
Reset counter after Capture Event 4 time-stamp has been captured
(used in difference mode operation)
CAP4POL
Capture Event 4 Polarity select
0
Capture Event 4 triggered on a rising edge (RE)
1
Capture Event 4 triggered on a falling edge (FE)
CTRRST3
Counter Reset on Capture Event 3
0
Do not reset counter on Capture Event 3 (absolute time stamp)
1
Reset counter after Event 3 time-stamp has been captured
(used in difference mode operation)
CAP3POL
Capture Event 3 Polarity select
0
Capture Event 3 triggered on a rising edge (RE)
1
Capture Event 3 triggered on a falling edge (FE)
CTRRST2
Counter Reset on Capture Event 2
0
Do not reset counter on Capture Event 2 (absolute time stamp)
1
Reset counter after Event 2 time-stamp has been captured
(used in difference mode operation)
CAP2POL
Capture Event 2 Polarity select
0
Capture Event 2 triggered on a rising edge (RE)
1
Capture Event 2 triggered on a falling edge (FE)
CTRRST1
Counter Reset on Capture Event 1
0
Do not reset counter on Capture Event 1 (absolute time stamp)
1
Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)
CAP1POL
Capture Event 1 Polarity select
0
Capture Event 1 triggered on a rising edge (RE)
1
Capture Event 1 triggered on a falling edge (FE)
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16.4.8 ECAP Control Register 2 (ECCTL2)
The ECAP control register 2 (ECCTL2) is shown in Figure 16-24 and described in Table 16-21.
Figure 16-24. ECAP Control Register 2 (ECCTL2)
15
11
7
10
9
8
Reserved
APWMPOL
CAP/APWM
SWSYNC
R-0
R/W-0
R/W-0
R/W-0
2
1
5
4
3
SYNCO_SEL
6
SYNCI_EN
TSCTRSTOP
REARM
STOP_WRAP
CONT/ONESHT
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-21. ECAP Control Register 2 (ECCTL2) Field Descriptions
Bit
15-11
10
9
Field
Value
Reserved
0
APWMPOL
Description
Reserved
APWM output polarity select. This is applicable only in APWM operating mode
0
Output is active high (Compare value defines high time)
1
Output is active low (Compare value defines low time)
CAP/APWM
CAP/APWM operating mode select
0
ECAP module operates in capture mode. This mode forces the following configuration:
•
•
•
•
1
ECAP module operates in APWM mode. This mode forces the following configuration:
•
•
•
•
8
SWSYNC
Inhibits TSCTR resets via CTR = PRD event
Inhibits shadow loads on CAP1 and 2 registers
Permits user to enable CAP1-4 register load
ECAPn/APWMn pin operates as a capture input
Resets TSCTR on CTR = PRD event (period boundary
Permits shadow loading on CAP1 and 2 registers
Disables loading of time-stamps into CAP1-4 registers
ECAPn/APWMn pin operates as a APWM output
Software-forced Counter (TSCTR) Synchronizing. This provides a convenient software method to
synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via
the CTR = PRD event.
0
Writing a zero has no effect. Reading always returns a zero
1
Writing a one forces a TSCTR shadow load of current ECAP module and any ECAP modules
down-stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a zero.
Note: Selection CTR = PRD is meaningfu