MPC5200B User`s Manual

MPC5200B User’s Manual
MPC5200BUM
Rev. 3
5/2010
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MPC5200BUM
Rev. 3
5/2010
Table of Contents
Chapter 1
Introduction
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.1 Embedded e300 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2.2 BestComm I/O Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.2.3 Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.4 Byte Data Link Controller - Digital BDLC-D . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.5 System Level Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2.6 SDRAM Controller and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.7 Multi-Function External LocalPlus Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.9 Systems Debug and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.10 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Chapter 2
Signal Descriptions
2.1
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Chapter 3
Memory Map
3.1
3.2
3.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPC5200B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 MPC5200B Internal Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 External Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Memory Map Space Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-3
3-3
3-4
3-6
Chapter 4
Resets and Reset Configuration
4.1
4.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Hard and Soft Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2.1 Power-On Reset—PORRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Freescale Semiconductor
Table of Contents-iii
4.3
4.4
4.5
4.6
4.2.2 Hard Reset—HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Soft Reset—SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
4-2
4-3
4-4
4-5
4-5
Chapter 5
Clocks and Power Management
5.1
5.2
5.3
5.4
5.5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Clock Distribution Module (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
MPC5200B Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.1 MPC5200B Top Level Clock Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2 e300 Core Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3.3 Processor Bus (XLB) Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.4 SDRAM Memory Controller Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.5 IPB Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3.6 PCI Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4.1 Full-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.4.2 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.4.3 e300 Core Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.4.4 Deep-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
CDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.5.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Chapter 6
e300 Processor Core
6.1
6.2
6.3
6.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPC5200B e300 Processor Core Functional Overview . . . . . . . . . . . . . . . . . . . . . . . .
e300 Core Reference Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Not Supported e300 Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Not Supported Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Not Supported XLB Parity Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-2
6-3
6-3
6-3
Chapter 7
System Integration Unit (SIU)
7.1
7.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents-iv
7-1
7-1
7-1
7-4
Freescale Semiconductor
7.3
7.4
7.5
7.6
7.2.3 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.4 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
7.3.1 GPIO Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.3.2 GPIO Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
7.4.1 Timer Configuration Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
7.4.2 Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
7.4.3 Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-66
7.4.4 GPT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-66
Slice Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
7.5.1 SLT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-77
7.6.1 Real-Time Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-78
7.6.2 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-78
7.6.3 RTC Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-79
Chapter 8
SDRAM Memory Controller
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Terminology and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2.1 “Endian”-ness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3.1 Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.4.1 External Signals (SDRAM Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.4.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.3 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.4.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.5.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.5.2 Read Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Programming the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8.6.1 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Address Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
8.7.1 Example—Physical Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38
Chapter 9
LocalPlus Bus (External Bus Interface)
9.1
9.2
9.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Freescale Semiconductor
Table of Contents-v
9.4
9.5
9.6
9.7
9.3.1 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.4.1 Non-MUXed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.4.2 MUXed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.5.1 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.5.2 Chip Selects Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.5.3 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
DMA (BestComm) Interface (SCLPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.7.1 Chip Select/LPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.7.2 SCLPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.7.3 SCLPC FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
Chapter 10
PCI Controller
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2 PCI External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.1 PCI_AD[31:0] — Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.2 PCI_CBE[3:0] — Command/Byte Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3 PCI_DEVSEL — Device Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.4 PCI_FRAME — Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.5 PCI_IDSEL — Initialization Device Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.6 PCI_IRDY — Initiator Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.7 PCI_CLK — PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.8 PCI_PERR — Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.9 PCI_RST — Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.10PCI_SERR — System Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.11PCI_STOP — Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.12PCI_TRDY — Target Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.1 PCI Controller Type 0 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.3.2 General Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.3.3 Communication Sub-System Interface Registers . . . . . . . . . . . . . . . . . . . . . 10-30
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-56
10.4.1 PCI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-56
10.4.2 Initiator Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-64
10.4.3 Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65
10.4.4 XL bus Initiator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65
10.4.5 XL bus Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-73
10.4.6 Communication Sub-System Initiator Interface . . . . . . . . . . . . . . . . . . . . . . 10-76
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10.4.7 PCI - Supported Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.1 XL bus Initiated Transaction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.2 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.3 XL bus Arbitration Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-80
10-80
10-80
10-81
10-81
10-82
10-85
Chapter 11
ATA Controller
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 BestComm Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 BestComm Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 BestComm Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3 ATA Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.1 ATA Host Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.2 ATA FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.3 ATA Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.4 ATA Host Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
11.4.1 PIO State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32
11.4.2 DMA State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
11.5 Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
11.6 ATA Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36
11.7 ATA Bus Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.7.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38
11.7.2 ATA Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
11.7.3 ATA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
11.7.4 ATA Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
11.8 ATA RESET/Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51
11.8.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51
11.8.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51
11.9 ATA I/O Cable Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52
Chapter 12
Universal Serial Bus (USB)
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Data Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Host Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.1 Communication Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Host Control (HC) Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.1 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12-1
12-2
12-2
12-2
12-4
12-6
12-7
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12.4.2 Control and Status Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.4.3 Memory Pointer Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
12.4.4 Frame Counter Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.4.5 Root Hub Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
Chapter 13
BestComm
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 BestComm Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.4 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.6 Memory Map/ Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.7 Task Table (Entry Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.8 Task Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.9 Variable Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.10Function Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.11Context Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.12External DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.13External DMA Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.14BestComm XLB Address Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.15BestComm DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.15.1Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.16On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.17Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.17.1Task Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.17.2Variable Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36
Chapter 14
Fast Ethernet Controller (FEC)
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1 Full- and Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2 10Mbps and 100Mbps MII Interface Operation . . . . . . . . . . . . . . . . . . . . . . .
14.2.3 10Mbps 7-Wire Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.4 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.5 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 I/O Signal Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 FEC Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1 Control and Status (CSR) Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents-viii
14-1
14-3
14-3
14-3
14-3
14-4
14-4
14-4
14-4
14-5
14-8
14-9
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14.4.2 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3 FEC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.4 FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1 Hardware Controlled Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.2 User Initialization (Prior to Asserting ETHER_EN) . . . . . . . . . . . . . . . . . . . .
14.5.3 Frame Control/Status Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.4 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.5 FEC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.6 Ethernet Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.7 Full-Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.8 Inter-Packet Gap Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.9 Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.10Internal and External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.11Ethernet Error-Handling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-10
14-13
14-36
14-46
14-46
14-47
14-48
14-50
14-51
14-51
14-56
14-57
14-57
14-58
14-58
Chapter 15
Programmable Serial Controller (PSC)
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1 PSC Functions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.3 PSC Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52
15.3.1 PSC in UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53
15.3.2 PSC in Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-59
15.3.3 PSC in AC97 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-74
15.3.4 PSC in IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-80
15.4 PSC FIFO System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-88
15.4.1 RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-90
15.4.2 TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-91
15.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-92
15.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-93
Chapter 16
XLB Arbiter
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.1 XLB Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.2 Arbiter Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
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Chapter 17
Serial Peripheral Interface (SPI)
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.1 Master In/Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.2 Master Out/Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.4 Slave-Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.5 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.4.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.8 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.4.9 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
Chapter 18
Inter-Integrated Circuit (I 2 C)
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2 I
18.2.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.2 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
18.5 Transfer Initiation and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
18.5.1 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
18.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25
18.5.3 Special Note on AKF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25
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Chapter 19
Controller Area Network (MSCAN)
19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.4 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.5 Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.5.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.6 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.6.1 Identifier Registers (IDR0–IDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
19.6.2 Data Segment Registers (DSR0–DSR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.7.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.7.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
19.7.4 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38
19.7.5 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-38
19.7.6 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40
19.7.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
19.7.8 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
19.7.9 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-45
19.7.10Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46
19.7.11Recovery from STOP or WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46
Chapter 20
Byte Data Link Controller (BDLC)
20.1
20.2
20.3
20.4
20.5
20.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.6.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.7.2 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
20.7.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
20.8.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
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Table of Contents-xi
20.8.2 Mux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.3 Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.4 Transmitting A Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.5 Receiving A Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.6 Transmitting An In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.7 Receiving An In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.8 Special BDLC Module Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.8.9 BDLC Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.9.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-36
20-38
20-40
20-44
20-48
20-57
20-59
20-60
20-64
20-64
Chapter 21
Debug Support and JTAG Interface
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 TAP Link Module (TLM) and Slave TAP Implementation . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.3 TLM and TAP Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.1 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.2 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3.4 Test Data In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3.5 Test Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4 Slave Test Reset (STRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4.1 Enable Slave—ENA[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4.2 Select DR Link—SEL[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.4.3 Slave Test Data Out—STDO[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.5 TAP State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.6 e300 Core JTAG/COP Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.7 TLM Link DR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.7.1 TLM:TLMENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.7.2 TLM:PPCENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.8 TLM Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.8.1 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.8.2 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.8.3 SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.8.4 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.8.5 CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.8.6 HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.9 e300 COP/BDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
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Freescale Semiconductor
Appendix A
Acronyms and Terms
Appendix B
Revision History
B.1 Changes Between Revisions 1.3 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.2 Changes Between Revisions 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
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Table of Contents-xiv
Freescale Semiconductor
Chapter 1
Introduction
1.1
Overview
The digital communication networking and consumer markets require significant processor performance
to enable operating systems and applications such as VxWorks™, QNX™, JAVA and soft modems. High
integration is essential to reducing device and systems costs. The MPC5200B is specifically designed to
meet these market needs while building on the family of microprocessors that use PowerPC™ architecture.
For more information on PowerPC architecture, see “The Programming Environments Manual for 32-bit
Implementations of the PowerPC Architecture”.
The MPC5200B integrates a high performance e300 core with a rich set of peripheral functions focused
on communications and systems integration. The e300 core design is based on the PowerPC™ core
architecture. The MPC5200B incorporates an innovative I/O subsystem, which isolates routine
maintenance of peripheral functions from the embedded e300 core.
The MPC5200B supports a dual external bus architecture. It has a high speed SDRAM Bus interface that
connects directly to the e300 core. In addition, the MPC5200B has a LocalPlus Bus used as a generalized
interface to system level peripheral devices and debug environments.
1.1.1
Features
Key features are shown below.
• e300 core
— Superscalar architecture
— 760MIPS at 400MHz (-40 to +85°C)
— 16k Instruction cache, 16k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard & Critical interrupt capability
• SDRAM / DDR Memory Interface
— up to 132MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per Chip Select (Two CS lines available)
— 32-bit data bus
— Built-in initialization and refresh
MPC5200B User’s Manual, Rev. 3
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Introduction
•
•
•
•
•
•
•
•
•
•
•
Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit data bus with up to 26 bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit data bus with up to 25 bit address
Peripheral Component Interconnect (PCI) Controller
— Version 2.2 PCI compatibility
— PCI initiator and target operation
— 32-bit PCI Address/Data bus
— 33 and 66 MHz operation
— PCI arbitration function
ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16kBytes)
6 Programmable Serial Controllers (PSC), configurable for:
— UART or RS232 interface
— CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97
— Full duplex SPI mode
— IrDA mode from 2400 bps to 4 Mbps
Fast Ethernet Controller (FEC)
— Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface
Universal Serial Bus Controller (USB)
— USB Revision 1.1 Host
— Open Host Controller Interface (OHCI)
— Integrated USB Hub, with two ports.
Two Inter-Integrated Circuit Interfaces (I2C)
Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
— Motorola Scalable CAN (MSCAN) architecture
— Implementation of version 2.0A/B CAN protocol
— Standard and extended data frames
J1850 Byte Data Link Controller (BDLC)
— J1850 Class B data communication network interface compatible and ISO compatible for low
speed (<125kbps) serial data communications in automotive applications.
— Supports 4X mode, 41.6 kbps
— In-frame response (IFR) types 0, 1, 2, and 3 supported
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Introduction
•
•
•
•
1.2
Systems level features
— Interrupt Controller supports 4 external interrupt request lines and 47 internal interrupt sources
— GPIO/Timer functions
– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a
variety of interrupt/Wake Up capabilities.
– 8 GPIO pins with timer capability supporting input capture, output compare and pulse width
modulation (PWM) functions
— Real-time Clock with 1 second resolution
— Systems Protection (watch dog timer, bus monitor)
— Individual control of functional block clock sources
— Power management: Nap, Doze, Sleep, Deep Sleep modes
— Support of Wake Up from low power modes by different sources (GPIO, RTC, CAN)
Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-Chip Processor (COP) debug port
On-board PLL and clock generation
Software
— QNX
— VXWorks
— Linux
— Software Modem capable
— JAVA
Architecture
The following areas comprise the MPC5200B system architecture:
• Embedded e300 Core
• BestComm I/O Subsystem
• Controller Area Network (CAN)
• Byte Data Link Controller - Digital BDLC-D
• System Level Interfaces
• SDRAM Controller and Interface
• Multi-Function External LocalPlus Bus
• Power Management
• Systems Debug and Test
• Physical Characteristics
A dynamically managed external pin multiplexing scheme minimizes overall pin count. The result is low
cost packaging and board assembly costs.
Figure 1-1 shows a simplified MPC5200B block diagram.
MPC5200B User’s Manual, Rev. 3
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Introduction
1-4
SDRAM / DDR
Systems Interface Unit (SIU)
Real-Time Clock
SDRAM / DDR
Memory Controller
e300 Core
System Functions
InterruptController
GPIO/Timers
Reset / Clock
Generation
Local
Bus
BestComm DMA
JTAG / COP
Interface
SRAM 16K
MPC5200B User’s Manual, Rev. 3
LocalPlus Controller
PCI Bus Controller
ATA Host Controller
CommBus
MSCAN
2x
J1850
USB
2x
SPI
I2C
2x
Ethernet
PSC
6x
Freescale Semiconductor
Figure 1-1. Simplified Block Diagram—MPC5200B
Introduction
The MPC5200B supports a dual external bus architecture consisting of:
1. An SDRAM Bus
2. A multi-function LocalPlus Bus
The SDRAM Bus has a Memory Controller interface which supports standard SDRAM and Double Data
Rate (DDR) SDRAM devices. The Memory Controller has 13 Memory Address (MA) lines multiplexed
with 32 Data Bus lines. Standard SDRAM control signals are included.
The high-speed Memory Controller SDRAM interface connects directly to the microprocessor, allowing
optimized instruction and data bursting. The dedicated memory interface, coupled with on-chip
16 Kilobyte instruction and 16Kilobyte data caches, enables high performance for computer intensive
applications, such as Java and soft modems. Still, plenty of processing power remains for peripheral
management and system control tasks.
The LocalPlus Bus provides for connection of external peripheral devices, disk storage, and slower speed
memory. The LocalPlus Bus also supports an external Boot ROM/FLASH/SRAM interface.
The MPC5200B integrates a high performance e300 core with an I/O subsystem containing an intelligent
Direct Memory Access (DMA) unit, BestComm. The BestComm unit is capable of:
• Responding to peripheral interrupts, independent of the e300 core.
• Providing low level peripheral management, protocol processing, and peripheral data movement
functions.
The MPC5200B has an optimized peripheral mix to support today’s embedded automotive and telematics
requirements.
Figure 1-2 shows an MPC5200B-based system.
1.2.1
Embedded e300 Core
The MPC5200B embedded e300 core is derived from Freescale’s (formerly Motorola) MPC603e family
of Reduced Instruction Set Computer (RISC) microprocessors. The e300 core is a high-performance,
low-power implementation of the PowerPC superscalar architecture. The MPC5200B e300 core contains:
• 16 KBytes of instruction cache
• 16 KBytes of data cache
Caches are 4-way set associative and use the Least Recently Used (LRU) replacement algorithm.
Four independent execution units are used:
1. Branch Processing Unit (BPU)
2. Integer Unit (IU)
3. Load/Store Unit (LSU)
4. System Register Unit (SRU)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
1-5
Introduction
SDRAM/DDR Controller
Demodulator
MPC5200
Audio
Memory
Controller
SIU
Transport &
Video Decoder/
Encoder
PCI Bus
Embedded
e300 Core
(MPC603e)
SDRAM
ATA Interface
SRAM Interface
Control
Video
SRAM
Graphics
SDRAM
DMA
Ethernet
IrDA Rx/Tx
I2C1
USB
ENET
PSC6
PSC5
PSC4
PSC3
PSC2
PSC1
Flash,
Boot ROM
IDE Disk
Interface
IC Control
Printer or I/O port
UART
UART
Codec
AC97
Debug Interface
Figure 1-2. MPC5200B-Based System
Up to 3 instructions can be issued and retired per clock. Most instructions execute in a single cycle. The
core contains an integrated Floating Point Unit (FPU), a Data Cache Memory Management Unit and an
Instruction Cache Memory Management Unit. The core implements the 32-bit portion of the PowerPC
architecture, which provides 32-bit effective addressing and integer data types of 8-, 16-, and 32-bits.
Enhancements in this core version, specific to embedded automotive/telematics include:
• Improved interrupt latency (critical interrupt)
• New MMU with additional 8 BAT (16 total) registers and 1KByte page management
MPC5200B User’s Manual, Rev. 3
1-6
Freescale Semiconductor
Introduction
The e300 core performance for SPEC95 benchmark integer operations, ranges between 4.4 and 5.1 at
200MHz. In Drystone 2.1MIPS, the e300 core is 280 MIPS at 200 MHz.
1.2.2
BestComm I/O Subsystem
BestComm contains an intelligent DMA unit. This unit provides a front-line interrupt control and data
movement interface via a separate peripheral bus to the on-chip peripheral functions. This leaves the e300
core free for higher level activities. The concurrent operation enables a significant boost in overall systems
performance.
BestComm supports up to 16 simultaneously enabled DMA tasks from up to 32 DMA requestors. Also
included is:
• A hardware logic unit
• A hardware CRC unit
BestComm uses internal buffers for prefetched reads and post writes. Bursting is used whenever possible.
This optimizes both internal and external bus activity.
1.2.2.1
Programmable Serial Controllers (PSCs)
The MPC5200B supports six PSCs. Each can be configured to operate in different modes. PSCs support
both synchronous and asynchronous protocols. They are used to interface to external full-function modems
or external CODECs for soft modem support. 8, 16, 24 and 32-bit data widths are supported. PSCs can be
configured to support 1200 baud POTS modem, SPI, I2S, V.34 or V.90 protocols. The standard UART
interface supports connection to an external terminal/computer for debug support.
1.2.2.2
10/100 Ethernet Controller
The Ethernet Controller supports the following standard MAC-PHY interfaces:
• 100 Mbps IEEE 802.3 MII
• 10 Mbps IEEE 802.3 MII
• 10 Mbps 7-wire interface
The controller is full duplex, supports a programmable maximum frame length and retransmission from
the Tx FIFO following a collision.
1.2.2.3
Universal Serial Bus (USB)
The MPC5200B supports two USB channels. The USB Controller implements the USB Host
Controller/Root Hub in compliance with the USB1.1 specification. The user may choose to have either one
or two USB ports on the root hub, each of which can interface to an off-chip USB transceiver. The Host
Controller supports the Open Host Controller Interface (OHCI) standard.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
1-7
Introduction
1.2.2.4
Infrared Support
The MPC5200B supports the IrDA format. All three IrDA modes are supported (SIR, MIR, FIR) to
4.0 Mbps. The required 48 MHz clock can be generated internally or supplied externally on an input pin.
1.2.2.5
Inter-Integrated Circuit (I 2 C)
The MPC5200B supports two I2C channels. Both master and slave interfaces can be controlled directly by
the processor or can use the BestComm Controller to buffer Tx/Rx data when the I2C data rate is high.
1.2.2.6
Serial Peripheral Interface (SPI)
The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and
peripheral devices. It supports master and slave mode, double-buffered operation and can operate in a
polling or interrupt driven environment.
1.2.3
Controller Area Network (CAN)
The MPC5200B supports two CAN channels. The CAN is an asynchronous communications protocol used
in automotive and industrial control systems. It is a high speed, short distance, priority based protocol that
runs on a variety of mediums. For example, transmission media of fiber optic cable or unshielded twisted
wire pairs can be used.
MSCAN supports both standard and extended identifier (ID) message formats specified in BOSCH CAN
protocol specification, revision 2.0, part B. Each MSCAN module contains:
• 4 receive buffers (with FIFO storage scheme)
• 3 transmit buffers
• Flexible maskable identifier filters
1.2.4
Byte Data Link Controller - Digital BDLC-D
The MPC5200B supports J1850 Class B data communication network interface compatible and ISO
compatible for low speed (<125 kbps) serial data communications in automotive applications.
• Hardware cyclical redundancy check (CRC) generation and checking
• Two power saving modes with automatic wake up on network activity
• Polling and CPU interrupt available
• Block mode receive/transmit supported
• Supports 4X mode, 41.6 kbps
• In-frame response (IFR) types 0, 1, 2, and 3 supported
• Wake up on J1850 message
MPC5200B User’s Manual, Rev. 3
1-8
Freescale Semiconductor
Introduction
1.2.5
System Level Interfaces
System Level Interfaces are listed below and described in the sections that follow:
• Chip Selects
• Interrupt Controller
• Timers
• General Purpose Input/Outputs (GPIO)
• Functional Pin Multiplexing
• Real-Time Clock (RTC)
1.2.5.1
Chip Selects
The MPC5200B integrates the most common system integration interfaces and signals. There are 8 fully
programmable external chip selects, which are independent of the SDRAM interface. LP_CS0 has special
features to support a Boot ROM. Two of the chip selects may be used by the IDE disk drive interface, when
enabled.
1.2.5.2
Interrupt Controller
The Interrupt Controller has 4 external interrupt signals and manages both external and internal interrupts.
All interrupt levels and priorities are programmable.
The Interrupt Controller takes advantage of the new critical interrupt feature defined by the PowerPC
architecture. This allows e300 core interrupts outside operating system boundaries, for critical functions
such as real-time packet processing.
1.2.5.3
Timers
MPC5200B integrates several timer functions required by most embedded systems:
• Two internal Slice timers can create short-cycle periodic interrupts.
• A WatchDog timer can interrupt the processor if not regularly serviced, catching software
hang-ups.
A bus monitor monitors bus cycles and provides an interrupt if transactions take longer than a prescribed
time.
1.2.5.4
General Purpose Input/Outputs (GPIO)
A total of 56 pins on the MPC5200B can be programmed as GPIOs.
• 8 pins can interrupt the processor.
• 8 pins can support a “Wake Up” capability that brings the MPC5200B out of low power modes.
• 8 pins are “output only” GPIOs.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
1-9
Introduction
The remaining GPIO pins support a simple “set the output level” or “detect the input level” type GPIO
function. Eight I/Os can be connected to one of eight general purpose timers to support input capture,
output compare or pulse width modulation functions.
The number of GPIOs available in the various modes depends on the peripheral functionality required. See
pin descriptions and I/O port maps below for more information.
1.2.5.5
Functional Pin Multiplexing
Many serial/parallel port pins serve multiple functions, allowing flexibility in optimizing the system to
meet a specific set of integration requirements. For example, when PSC3 interfaces to a full function
external modem, 10 pins are required:
• PSC3_TXD—Transmit Data
• PSC3_RXD—Receive Data
• PSC3_RTS—Ready to Send
• PSC3_CTS—Clear to Send
• PSC3_CD—Carrier Detect
• MODEM_RI—Ring Indicator
• MODEM_DSR—Hook Switch
• MODEM_IO—Control I/O (A0 gain)
• MODEM_IO—Control I/O (Mode 1)
• MODEM_IO—Control I/O (Mode 2)
If PSC3 connects to a simple UART, only the first four signals (shown above) are required. The remaining
6 signals can be used as GPIOs.
If a 7-wire Ethernet connection is adequate, the additional 11 Ethernet I/Os can be used as GPIOs.
1.2.5.6
Real-Time Clock (RTC)
An RTC is included on the MPC5200B. The RTC provides a 2-pin interface to an external 32.768 kHz
crystal. This allows internal time-of-day/calendar tracking, as well as clock based periodic interrupts.
1.2.6
SDRAM Controller and Interface
The MPC5200B high speed SDRAM Controller supports both standard SDRAM and Double Data Rate
(DDR) SDRAM devices. It supports up to 256 MBytes per chip select (2 Chip Select lines available) with
a 32-bit interface. Memory sizes of 64 Mbit, 128 Mbit, 256 Mbit and 512 Mbit are supported.
1.2.7
Multi-Function External LocalPlus Bus
The MPC5200B supports a multi-function external LocalPlus Bus to allow connections to PCI and ATA
compliant devices, as well as external ROM/SRAM.
The MPC5200B integrates a 3.3 V, PCI V2.2 compatible external LocalPlus Bus controller and interface.
This bus is a 32-bit multiplexed address/data bus.
MPC5200B User’s Manual, Rev. 3
1-10
Freescale Semiconductor
Introduction
The external LocalPlus Bus provides support for an ATA disk drive interface. ATA control signals (chip
selects, write/read, etc.) are provided independent of the PCI control signals. This prevents bus contention.
However, the 32-bit data bus is shared. When The MPC5200B recognizes an external LocalPlus Bus
access meant for the ATA Controller, ATA control logic arbitrates for PCI interface control. The 32-bit
address/data bus function is transformed into 16bits of ATA data and 3bits of ATA address.
The external LocalPlus Bus also allows connection to external memory or peripheral devices that adhere
to a ROM or SRAM-like interface. These devices occupy a separate location in the memory map and have
independent control signals. When an internal access is decoded to fall in the SRAM/ROM memory space,
the 32-bit PCI address/data bus is transformed into either:
• 24bits of address and 8bits of data
• 16bits of address and 16bits of data.
The MPC5200B supports a reset configuration mode common on the family of processors that use the
PowerPC architecture. 16 bits of configuration information is driven and sampled during reset to establish
the initial processor configuration.
1.2.8
Power Management
The MPC5200B is processed in a low-power static CMOS technology. In addition, it supports the dynamic
power management modes available on the MPC52xx series processors using the e300 core. These modes
include:
• Nap
• Dose
• Sleep
• Deep sleep
In deep sleep, all internal clocks can be disabled, thus, reducing the power draw to CMOS leakage levels.
A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the
MPC5200B can be shut down to a low-power standby mode, then re-enabled by one of the Wake Up inputs
without resetting the MPC5200B.
1.2.9
Systems Debug and Test
The MPC5200B supports the Common On-chip Processor (COP) debug capability common on other
microprocessors that use the PowerPC architecture. The COP interface supports features such as:
• Memory down load
• Single step instruction execution
• Break/watch point capability
• Access to internal registers
• Pipeline tracking, etc.
The MPC5200B also supports a JTAG IEEE 1149.1 controller and test access port (TAP).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
1-11
Introduction
1.2.10
•
•
•
Physical Characteristics
1.5 V internal, 3.3 V external operation (2.5 V for DDR interface)
TTL compatible I/O pins
272-pin Plastic Ball Grid Array (PBGA)
MPC5200B User’s Manual, Rev. 3
1-12
Freescale Semiconductor
Chapter 2
Signal Descriptions
2.1
Overview
The MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks
and associated I/O ports. There are two external data/address bus structures, the LocalPlus bus and
SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure 1-1.
In general, the LocalPlus bus connects to external SRAM, FLASH, peripheral devices, etc. The LocalPlus
bus is capable of executing standard memory cycles, PCI cycles and ATA cycles. In addition to the data
and address bus pins on the LocalPlus bus, there are pins specifically dedicated to ATA transactions, PCI
transactions and standard memory transactions. When the MPC5200B is released from reset, Chip Select 0
is the only active chip select. Program execution must always start from the “boot device” on the LocalPlus
bus. There are 8 chip select signals associated with the LocalPlus bus. It’s possible to execute from every
CS. Also every CS can address “data space”.
The SDRAM bus interfaces to Synchronous DRAM. Both Single Data Rate and Double Data Rate
DRAMs are supported. Executable programs are generally loaded into memory residing on the SDRAM
bus. The SDRAM bus has a 32-bit wide data/address bus structure and is capable of burst accesses. It is
possible to execute program code over the LocalPlus bus. However, the data transfer rate on the SDRAM
bus is many times faster than LocalPlus.
There are 16 peripheral functional blocks on the MPC5200B. These are General Purpose I/O, I2C,
TIMER, PSC1, PSC2, PSC3, PSC4, PSC5, PSC6, Ethernet, USB, MSCAN, SPI and J1850. Each of these
functional blocks are routed to one or more I/O ports through a system of multiplexers. A functional block
can only be routed to one I/O port at a time and in many cases, several functional blocks can be routed to
the same I/O port.
The I/O ports are Dedicated GPIO Group, I2C Group, Timer Group, PSC1 Group, PSC2 Group, PSC3
Group, PSC6 Group, Ethernet Group, and the USB Group.
Figure 2-3 through Figure 2-12 present detailed on the multiplexing options for each I/O port.
MPC5200B is packaged in a 272-pin Plastic Ball Gate Array (PBGA). Package ball locations are shown
in Figure 2-1. See Figure 2-2 for case diagram.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-1
Signal Descriptions
Y1 signal:
ext_ad_27
View Looking at Pins (Balls)
Y20 signal:
timer0
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 signal:
test_mode_1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A20 signal:
mem_dqm_2
Notes:Table 2-1 and Table 2-2 give the signals on each pin/ball.
Figure 2-1. 272-Pin PBGA Pin Detail
Table 2-1 gives a list of MPC5200B I/O signals sorted by package ball name. Table 2-2 gives the same
list sorted by signal name.
Many signal pins can have multiple functions depending on internal register settings. These additional
functions are described in Table 2-3 through Table 2-31.
MPC5200B User’s Manual, Rev. 3
2-2
Freescale Semiconductor
Freescale Semiconductor
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
TEST_MODE_1
JTAG_TDO
JTAG_TDI
JTAG_TMS
PSC3_8
PSC3_5
PSC3_2
PSC2_4
PSC2_2
PSC1_4
PSC1_1
PSC6_2
PORRESET
SRESET
SYS_XTAL_IN
MEM_MA_1
MEM_MBA_1
MEM_RAS
MEM_WE
MEM_DQM_2
B02
B03
B14
B15
B01
TEST_SEL_0
C01
TEST_MODE_0 JTAG_TRST
C02
C03
RTC_XTAL_OUT RTC_XTAL_IN TEST_SEL_1
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
JTAG_TCK
PSC3_7
PSC3_4
PSC3_1
PSC2_3
PSC2_1
PSC1_3
PSC1_0
PSC6_0
HRESET
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
PSC3_9
PSC3_6
PSC3_3
PSC3_0
CORE_PLL_AVDD
PSC2_0
PSC1_2
PSC6_1
GPIO_WKUP_7
PSC6_3
D11
D12
D13
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
TIMER_4
TIMER_3
TIMER_2
VSS
VDD_CORE
VDD_IO
VDD_CORE
LP_OE
VDD_IO
VDD_CORE
E01
E02
E03
E04
TIMER_7
TIMER_6
TIMER_5
VDD_IO
F01
F02
F03
F04
USB_7
USB_8
USB_9
VDD_IO
G01
G02
G03
G04
USB_3
USB_4
USB_5
USB_6
H01
H02
H03
H04
SYS_PLL_AVDD SYS_PLL_TPA
C14
C15
SYS_PLL_AVSS GPIO_WKUP_6
D14
D15
VDD_CORE VDD_MEM_IO VDD_MEM_IO SYS_XTAL_OUT VDD_MEM_IO
B16
B17
B18
B19
B20
MEM_MA_2
MEM_MA_10
MEM_CS_0
MEM_CAS
MEM_MA_4
C16
C17
C18
C19
C20
MEM_MA_3
MEM_MA_0
MEM_MBA_0
MEM_MA_5
MEM_MA_6
D17
D18
D16
VSS
VDD_MEM_IO MEM_MDQS_2
E17
Key for IO Balls:
<– Ball
A6
<– Signal Name
PSC3_5
F17
G17
H17
d
MPC5200B User’s Manual, Rev. 3
USB_1
USB_2
VDD_IO
J02
J03
J04
J09
J10
J11
J12
ETH_3
ETH_4
ETH_10
ETH_17
VSS
VSS
VSS
VSS
K01
K02
K03
K04
K09
K10
K11
K12
VSS
VSS
VSS
VSS
J17
K17
d
ETH_1
ETH_2
VDD_CORE
L02
L03
L04
L09
L10
L11
L12
L17
ETH_9
ETH_16
ETH_5
ETH_11
VSS
VSS
VSS
VSS
MEM_DQM_3
M01
M02
M03
M04
M09
M10
M11
M12
VSS
VSS
VSS
VSS
pl
M17
d
ETH_13
ETH_12
ETH_8
VDD_CORE
VDD_MEM_IO
N02
N03
N04
N17
ETH_7
ETH_6
ETH_15
ETH_14
P01
P02
P03
P04
P17
d
Core and IO VSS
VDD_CORE 1.5V Core VDD
VDD IO
3.3V IO VDD
VDD_MEM_IO Memory VDD
VSS
VDD_CORE
R02
R03
R04
EXT_AD_30
PCI_GNT
T01
T02
T03
T04
PCI_CLOCK
EXT_AD_26
EXT_AD_28
VDD_IO
E19
E20
MEM_MA_9
MEM_MA_11
F19
F20
MEM_MA_12
MEM_CLK_EN
G19
G20
MEM_CLK
MEM_CLK
H19
204
H20
206
MEM_DQM_1
MEM_MDQS_1
J19
J20
MEM_MDQ_8
MEM_MDQ_9
K19
194
K20
196
L18
M18
182
N18
P18
172
R18
MEM_MDQ_28 MEM_MDQ_29
T17
L20
M19
184
M20
186
MEM_MDQ_24 MEM_MDQ_14 MEM_MDQ_15
VDD_MEM_IO MEM_MDQ_27
R17
L19
MEM_MDQS_3 MEM_MDQ_12 MEM_MDQ_13
MEM_MDQ_25 MEM_MDQ_26
Key for PWR/GND Balls:
PCI_RESET
K18
193
D20
MEM_MA_8
VDD_MEM_IO MEM_MDQ_23 MEM_MDQ_10 MEM_MDQ_11
N01
IRQ3
J18
MEM_MDQ_22 MEM_MDQ_21
ETH_0
R01
H18
203
VDD_MEM_IO MEM_MDQ_20
L01
IRQ0
G18
MEM_MDQ_18 MEM_MDQ_19
USB_0
IRQ2
F18
VDD_MEM_IO MEM_MDQ_17
J01
IRQ1
E18
VDD_MEM_IO MEM_MDQ_16
D19
MEM_MA_7
T18
VDD_MEM_IO MEM_MDQ_30
N19
N20
MEM_DQM_0
MEM_MDQS_0
P19
174
P20
176
MEM_MDQ_7
MEM_MDQ_6
R19
R20
MEM_MDQ_5
MEM_MDQ_4
T19
T20
MEM_MDQ_3
MEM_MDQ_2
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
PCI_IDSEL
EXT_AD_24
VSS
VDD_IO
VDD_IO
VDD_CORE
EXT_AD_15
VDD_IO
VDD_IO
EXT_AD_6
VDD_CORE
VDD_IO
LP_ACK
VDD_CORE
VDD_IO
VSS
MEM_MDQ_31
MEM_MDQ_1
MEM_MDQ_0
V03
V04
V05
V20
V01
V02
EXT_AD_31
EXT_AD_20
W01
W02
EXT_AD_29
EXT_AD_25
Y01
Y02
EXT_AD_27
PCI_CBE_3
EXT_AD_22 EXT_AD_18 PCI_FRAME
W03
W04
EXT_AD_23 EXT_AD_16
Y03
Y04
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
PCI_STOP
PCI_PAR
EXT_AD_13
EXT_AD_11
EXT_AD_9
EXT_AD_4
EXT_AD_2
EXT_AD_0
LP_ALE
LP_CS2
LP_CS5
ATA_DRQ
TIMER_1
I2C_0
I2C_2
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W05 W06 W07
PCI_TRDY
Y05
EXT_AD_21 EXT_AD_19 EXT_AD_17
PCI_CBE_2 PCI_DEVSEL
PCI_SERR
EXT_AD_14
PCI_CBE_0
EXT_AD_8
EXT_AD_5
EXT_AD_1
LP_CS0
LP_CS3
LP_RW
ATA_IOW
ATA_IOCHRDY
I2C_1
I2C_3
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
PCI_IRDY
PCI_PERR
PCI_CBE_1
EXT_AD_7
EXT_AD_3
LP_TS
LP_CS1
LP_CS4
ATA_ISOLATION
ATA_IOR
ATA_DACK
ATA_INTRQ
TIMER_0
EXT_AD_12 EXT_AD_10
2-3
Figure 2-2. 272-Pin PBGA — Top View
Signal Descriptions
U01
PCI_REQ
Signal Descriptions
M
S
C
A
N
SDRAM
CS1
S
P
I
P
S
C
5
System
chip
selects
TSIZE_1
4
G
P
I
O
I
2
C
4
T
I
M
E
R
S
4
P
S
C
1
8
P
S
C
2
5
5
P
S
C
3
5
P
S
C
4
5
4
2
E
T
H
E
R
5
U
S
B
P2
10 100
7
2
ATA chip
selects
P
S
C
6
J
1
8
5
0
P1
10 10
18
4
Reset
Conf.
2
2
mux
mux
8
2
5
4
5
10
mux
mux
mux
mux
8 Pins
5 pins
5 pins
10 pins
14
mux
mux
8
2
5
4
mux
mux
18 pins
10 pins
4 pins
Ethernet
Group
USB
Group
PSC6
Group
1
1
Dedicated
GPIO
4 pins
I2C
Group
Timer
Group
PSC1
Group
PSC2
Group
PSC3
Group
Figure 2-3. MPC5200B Peripheral Muxing
MPC5200B User’s Manual, Rev. 3
2-4
Freescale Semiconductor
Signal Descriptions
2.2
Pinout Tables
Table 2-1. Signals by Ball/Pin (Sheet 1 of 4)
Ball/Pin
Pin Name
Ball/Pin
Pin Name
A01
TEST_MODE_1
B16
MEM_MA_2
A02
JTAG_TDO
B17
MEM_MA_10
A03
JTAG_TDI
B18
MEM_CS_0
A04
JTAG_TMS
B19
MEM_CAS
A05
PSC3_8
B20
MEM_MA_4
A06
PSC3_5
C01
RTC_XTAL_OUT
A07
PSC3_2
C02
RTC_XTAL_IN
A08
PSC2_4
C03
TEST_SEL_1
A09
PSC2_2
C04
PSC3_9
A10
PSC1_4
C05
PSC3_6
A11
PSC1_1
C06
PSC3_3
A12
PSC6_2
C07
PSC3_0
A13
PORRESET
C08
CORE_PLL_AVDD
A14
SRESET
C09
PSC2_0
A15
SYS_XTAL_IN
C10
PSC1_2
A16
MEM_MA_1
C11
PSC6_1
A17
MEM_MBA_1
C12
GPIO_WKUP_7
A18
MEM_RAS
C13
PSC6_3
A19
MEM_WE
C14
SYS_PLL_AVSS
A20
MEM_DQM_2
C15
GPIO_WKUP_6
B01
TEST_SEL_0
C16
MEM_MA_3
B02
TEST_MODE_0
C17
MEM_MA_0
B03
JTAG_TRST
C18
MEM_MBA_0
B04
JTAG_TCK
C19
MEM_MA_5
B05
PSC3_7
C20
MEM_MA_6
B06
PSC3_4
D01
TIMER_4
B07
PSC3_1
D02
TIMER_3
B08
PSC2_3
D03
TIMER_2
B09
PSC2_1
D04
VSS_IO/CORE
B10
PSC1_3
D05
VDD_CORE
B11
PSC1_0
D06
VDD_IO
B12
PSC6_0
D07
VDD_CORE
B13
HRESET
D08
LP_OE
B14
SYS_PLL_AVDD
D09
VDD_IO
B15
SYS_PLL_TPA
D10
VDD_CORE
D11
VDD_CORE
H04
VDD_IO
D12
VDD_MEM_IO
H17
VDD_MEM_IO
D13
VDD_MEM_IO
H18
MEM_MDQ_20
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-5
Signal Descriptions
Table 2-1. Signals by Ball/Pin (Sheet 2 of 4)
Ball/Pin
Pin Name
Ball/Pin
Pin Name
D14
SYS_XTAL_OUT
H19
MEM_DQM_1
D15
VDD_MEM_IO
H20
MEM_MDQS_1
D16
VSS_IO/CORE
J01
ETH_3
D17
VDD_MEM_IO
J02
ETH_4
D18
MEM_MDQS_2
J03
ETH_10
D19
MEM_MA_7
J04
ETH_17
D20
MEM_MA_8
J09
VSS_IO/CORE
E01
TIMER_7
J10
VSS_IO/CORE
E02
TIMER_6
J11
VSS_IO/CORE
E03
TIMER_5
J12
VSS_IO/CORE
E04
VDD_IO
J17
MEM_MDQ_22
E17
VDD_MEM_IO
J18
MEM_MDQ_21
E18
MEM_MDQ_16
J19
MEM_MDQ_8
E19
MEM_MA_9
J20
MEM_MDQ_9
E20
MEM_MA_11
K01
ETH_0
F01
USB_7
K02
ETH_1
F02
USB_8
K03
ETH_2
F03
USB_9
K04
VDD_CORE
F04
VDD_IO
K09
VSS_IO/CORE
F17
VDD_MEM_IO
K10
VSS_IO/CORE
F18
MEM_MDQ_17
K11
VSS_IO/CORE
F19
MEM_MA_12
K12
VSS_IO/CORE
F20
MEM_CLK_EN
K17
VDD_MEM_IO
G01
USB_3
K18
MEM_MDQ_23
G02
USB_4
K19
MEM_MDQ_10
G03
USB_5
K20
MEM_MDQ_11
G04
USB_6
L01
ETH_9
G17
MEM_MDQ_18
L02
ETH_16
G18
MEM_MDQ_19
L03
ETH_5
G19
MEM_CLK
L04
ETH_11
G20
MEM_CLK
L09
VSS_IO/CORE
H01
USB_0
L10
VSS_IO/CORE
H02
USB_1
L11
VSS_IO/CORE
H03
USB_2
L12
VSS_IO/CORE
L17
MEM_DQM_3
R18
MEM_MDQ_29
L18
MEM_MDQS_3
R19
MEM_MDQ_5
L19
MEM_MDQ_12
R20
MEM_MDQ_4
L20
MEM_MDQ_13
T01
PCI_CLOCK
M01
ETH_13
T02
EXT_AD_26
M02
ETH_12
T03
EXT_AD_28
MPC5200B User’s Manual, Rev. 3
2-6
Freescale Semiconductor
Signal Descriptions
Table 2-1. Signals by Ball/Pin (Sheet 3 of 4)
Ball/Pin
Pin Name
Ball/Pin
Pin Name
M03
ETH_8
T04
VDD_IO
M04
VDD_CORE
T17
VDD_MEM_IO
M09
VSS_IO/CORE
T18
MEM_MDQ_30
M10
VSS_IO/CORE
T19
MEM_MDQ_3
M11
VSS_IO/CORE
T20
MEM_MDQ_2
M12
VSS_IO/CORE
U01
PCI_REQ
M17
VDD_MEM_IO
U02
PCI_IDSEL
M18
MEM_MDQ_24
U03
EXT_AD_24
M19
MEM_MDQ_14
U04
VSS_IO/CORE
M20
MEM_MDQ_15
U05
VDD_IO
N01
ETH_7
U06
VDD_IO
N02
ETH_6
U07
VDD_CORE
N03
ETH_15
U08
EXT_AD_15
N04
ETH_14
U09
VDD_IO
N17
MEM_MDQ_25
U10
VDD_IO
N18
MEM_MDQ_26
U11
EXT_AD_6
N19
MEM_DQM_0
U12
VDD_CORE
N20
MEM_MDQS_0
U13
VDD_IO
P01
IRQ1
U14
LP_ACK
P02
IRQ2
U15
VDD_CORE
P03
IRQ0
U16
VDD_IO
P04
VDD_CORE
U17
VSS_IO/CORE
P17
VDD_MEM_IO
U18
MEM_MDQ_31
P18
MEM_MDQ_27
U19
MEM_MDQ_1
P19
MEM_MDQ_7
U20
MEM_MDQ_0
P20
MEM_MDQ_6
V01
EXT_AD_31
R01
IRQ3
V02
EXT_AD_20
R02
PCI_RESET
V03
EXT_AD_22
R03
EXT_AD_30
V04
EXT_AD_18
R04
PCI_GNT
V05
PCI_FRAME
R17
MEM_MDQ_28
V06
PCI_STOP
V07
PCI_PAR
Y04
EXT_AD_19
V08
EXT_AD_13
Y05
EXT_AD_17
V09
EXT_AD_11
Y06
PCI_IRDY
V10
EXT_AD_9
Y07
PCI_PERR
V11
EXT_AD_4
Y08
PCI_CBE_1
V12
EXT_AD_2
Y09
EXT_AD_12
V13
EXT_AD_0
Y10
EXT_AD_10
V14
LP_ALE
Y11
EXT_AD_7
V15
LP_CS2
Y12
EXT_AD_3
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-7
Signal Descriptions
Table 2-1. Signals by Ball/Pin (Sheet 4 of 4)
Ball/Pin
Pin Name
Ball/Pin
Pin Name
V16
LP_CS5
Y13
LP_TS
V17
ATA_DRQ
Y14
LP_CS1
V18
TIMER_1
Y15
LP_CS4
V19
I2C_0
Y16
ATA_ISOLATION
V20
I2C_2
Y17
ATA_IOR
W01
EXT_AD_29
Y18
ATA_DACK
W02
EXT_AD_25
Y19
ATA_INTRQ
W03
EXT_AD_23
Y20
TIMER_0
W04
EXT_AD_16
W05
PCI_TRDY
W06
PCI_CBE_2
W07
PCI_DEVSEL
W08
PCI_SERR
W09
EXT_AD_14
W10
PCI_CBE_0
W11
EXT_AD_8
W12
EXT_AD_5
W13
EXT_AD_1
W14
LP_CS0
W15
LP_CS3
W16
LP_RW
W17
ATA_IOW
W18
ATA_IOCHRDY
W19
I2C_1
W20
I2C_3
Y01
EXT_AD_27
Y02
PCI_CBE_3
Y03
EXT_AD_21
MPC5200B User’s Manual, Rev. 3
2-8
Freescale Semiconductor
Signal Descriptions
Table 2-2. Signals by Signal Name (Sheet 1 of 4)
Signal Name
Ball/Pin
Signal Name
Ball/Pin
ATA_DACK
Y18
EXT_AD_6
U11
ATA_DRQ
V17
EXT_AD_7
Y11
ATA_INTRQ
Y19
EXT_AD_8
W11
ATA_IOCHRDY
W18
EXT_AD_9
V10
ATA_IOR
Y17
EXT_AD_10
Y10
ATA_IOW
W17
EXT_AD_11
V09
ATA_ISOLATION
Y16
EXT_AD_12
Y09
LP_CS0
W14
EXT_AD_13
V08
LP_CS1
Y14
EXT_AD_14
W09
LP_CS2
V15
EXT_AD_15
U08
LP_CS3
W15
EXT_AD_16
W04
LP_CS4
Y15
EXT_AD_17
Y05
LP_CS5
V16
EXT_AD_18
V04
ETH_0
K01
EXT_AD_19
Y04
ETH_1
K02
EXT_AD_20
V02
ETH_2
K03
EXT_AD_21
Y03
ETH_3
J01
EXT_AD_22
V03
ETH_4
J02
EXT_AD_23
W03
ETH_5
L03
EXT_AD_24
U03
ETH_6
N02
EXT_AD_25
W02
ETH_7
N01
EXT_AD_26
T02
ETH_8
M03
EXT_AD_27
Y01
ETH_9
L01
EXT_AD_28
T03
ETH_10
J03
EXT_AD_29
W01
ETH_11
L04
EXT_AD_30
R03
ETH_12
M02
EXT_AD_31
V01
ETH_13
M01
GPIO_WKUP_6
C15
ETH_14
N04
GPIO_WKUP_7
C12
ETH_15
N03
CORE_PLL_AVDD
C08
ETH_16
L02
CORE_PLL_AVSS
NC (no connection)
ETH_17
J04
HRESET
B13
EXT_AD_0
V13
I2C_0
V19
EXT_AD_1
W13
I2C_1
W19
EXT_AD_2
V12
I2C_2
V20
EXT_AD_3
Y12
I2C_3
W20
EXT_AD_4
V11
PSC6_0
B12
EXT_AD_5
W12
PSC6_2
A12
PSC6_3
C13
MEM_MBA_1
A17
PSC6_1
C11
MEM_MDQ_0
U20
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-9
Signal Descriptions
Table 2-2. Signals by Signal Name (Sheet 2 of 4)
Signal Name
Ball/Pin
Signal Name
Ball/Pin
IRQ0
P03
MEM_MDQ_1
U19
IRQ1
P01
MEM_MDQ_2
T20
IRQ2
P02
MEM_MDQ_3
T19
IRQ3
R01
MEM_MDQ_4
R20
JTAG_TCK
B04
MEM_MDQ_5
R19
JTAG_TDI
A03
MEM_MDQ_6
P20
JTAG_TDO
A02
MEM_MDQ_7
P19
JTAG_TMS
A04
MEM_MDQ_8
J19
JTAG_TRST
B03
MEM_MDQ_9
J20
LP_ACK
U14
MEM_MDQ_10
K19
LP_ALE
V14
MEM_MDQ_11
K20
LP_OE
D08
MEM_MDQ_12
L19
LP_RW
W16
MEM_MDQ_13
L20
LP_TS
Y13
MEM_MDQ_14
M19
MEM_CAS
B19
MEM_MDQ_15
M20
MEM_CLK_EN
F20
MEM_MDQ_16
E18
MEM_CS_0
B18
MEM_MDQ_17
F18
MEM_DQM_0
N19
MEM_MDQ_18
G17
MEM_DQM_1
H19
MEM_MDQ_19
G18
MEM_DQM_2
A20
MEM_MDQ_20
H18
MEM_DQM_3
L17
MEM_MDQ_21
J18
MEM_MA_0
C17
MEM_MDQ_22
J17
MEM_MA_1
A16
MEM_MDQ_23
K18
MEM_MA_2
B16
MEM_MDQ_24
M18
MEM_MA_3
C16
MEM_MDQ_25
N17
MEM_MA_4
B20
MEM_MDQ_26
N18
MEM_MA_5
C19
MEM_MDQ_27
P18
MEM_MA_6
C20
MEM_MDQ_28
R17
MEM_MA_7
D19
MEM_MDQ_29
R18
MEM_MA_8
D20
MEM_MDQ_30
T18
MEM_MA_9
E19
MEM_MDQ_31
U18
MEM_MA_10
B17
MEM_MDQS_0
N20
MEM_MA_11
E20
MEM_MDQS_1
H20
MEM_MA_12
F19
MEM_MDQS_2
D18
MEM_MBA_0
C18
MEM_MDQS_3
L18
MEM_CLK
G19
PSC3_5
A06
MEM_CLK
G20
PSC3_6
C05
MEM_RAS
A18
PSC3_7
B05
MEM_WE
A19
PSC3_8
A05
PCI_CBE_0
W10
PSC3_9
C04
MPC5200B User’s Manual, Rev. 3
2-10
Freescale Semiconductor
Signal Descriptions
Table 2-2. Signals by Signal Name (Sheet 3 of 4)
Signal Name
Ball/Pin
Signal Name
Ball/Pin
PCI_CBE_1
Y08
RTC_XTAL_IN
C02
PCI_CBE_2
W06
RTC_XTAL_OUT
C01
PCI_CBE_3
Y02
SRESET
A14
PCI_CLOCK
T01
SYS_PLL_AVDD
B14
PCI_DEVSEL
W07
SYS_PLL_AVSS
C14
PCI_FRAME
V05
SYS_PLL_TPA
B15
PCI_GNT
R04
SYS_XTAL_IN
A15
PCI_IDSEL
U02
SYS_XTAL_OUT
D14
PCI_IRDY
Y06
TEST_MODE_0
B02
PCI_PAR
V07
TEST_MODE_1
A01
PCI_PERR
Y07
TEST_SEL_0
B01
PCI_REQ
U01
TEST_SEL_1
C03
PCI_RESET
R02
TIMER_0
Y20
PCI_SERR
W08
TIMER_1
V18
PCI_STOP
V06
TIMER_2
D03
PCI_TRDY
W05
TIMER_3
D02
PORRESET
A13
TIMER_4
D01
PSC1_0
B11
TIMER_5
E03
PSC1_1
A11
TIMER_6
E02
PSC1_2
C10
TIMER_7
E01
PSC1_3
B10
USB_0
H01
PSC1_4
A10
USB_1
H02
PSC2_0
C09
USB_2
H03
PSC2_1
B09
USB_3
G01
PSC2_2
A09
USB_4
G02
PSC2_3
B08
USB_5
G03
PSC2_4
A08
USB_6
G04
PSC3_0
C07
USB_7
F01
PSC3_1
B07
USB_8
F02
PSC3_2
A07
USB_9
F03
PSC3_3
C06
VDD_CORE
D05
PSC3_4
B06
VSS_IO/CORE
J12
VDD_CORE
D10
VSS_IO/CORE
K09
VDD_CORE
D11
VSS_IO/CORE
K10
VDD_CORE
K04
VSS_IO/CORE
K11
VDD_CORE
M04
VSS_IO/CORE
K12
VDD_CORE
P04
VSS_IO/CORE
L09
VDD_CORE
U07
VSS_IO/CORE
L10
VDD_CORE
U12
VSS_IO/CORE
L11
VDD_CORE
U15
VSS_IO/CORE
L12
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-11
Signal Descriptions
Table 2-2. Signals by Signal Name (Sheet 4 of 4)
Signal Name
Ball/Pin
Signal Name
Ball/Pin
VDD_IO
D06
VSS_IO/CORE
M09
VDD_IO
D09
VSS_IO/CORE
M10
VDD_IO
E04
VSS_IO/CORE
M11
VDD_IO
F04
VSS_IO/CORE
M12
VDD_IO
H4
VSS_IO/CORE
U04
VDD_IO
T4
VSS_IO/CORE
U17
VDD_IO
U05
VDD_CORE
D07
VDD_IO
U06
VDD_IO
U09
VDD_IO
U10
VDD_IO
U13
VDD_IO
U16
VDD_MEM_IO
D12
VDD_MEM_IO
D13
VDD_MEM_IO
D15
VDD_MEM_IO
D17
VDD_MEM_IO
E17
VDD_MEM_IO
F17
VDD_MEM_IO
H17
VDD_MEM_IO
K17
VDD_MEM_IO
M17
VDD_MEM_IO
P17
VDD_MEM_IO
T17
VSS_IO/CORE
D04
VSS_IO/CORE
D16
VSS_IO/CORE
J09
VSS_IO/CORE
J10
VSS_IO/CORE
J11
MPC5200B User’s Manual, Rev. 3
2-12
Freescale Semiconductor
Signal Descriptions
Table 2-3. LocalPlus Bus Address / Data Pin Assignments
E
X
T
_
A
D
1
4
E
X
T
_
A
D
1
3
E
X
T
_
A
D
1
2
E
X
T
_
A
D
1
1
E
X
T
_
A
D
1
0
E
X
T
_
A
D
9
E
X
T
_
A
D
8
E
X
T
_
A
D
7
E
X
T
_
A
D
6
E
X
T
_
A
D
5
E
X
T
_
A
D
4
E
X
T
_
A
D
3
E
X
T
_
A
D
2
E
X
T
_
A
D
1
E
X
T
_
A
D
0
16 bit Adr,
16 bit Data
D D D D D D D D D D D D D D D D A A
1 1 1 1 1 1 0 8 7 6 5 4 3 2 1 0 1 1
5 4
5 4 3 2 1 0 9
A
1
3
A
1
2
A A
1 1
1 0
A
9
A
8
A A
7 6
A
5
A
4
A A
3 2
A
1
A
0
24 bit Adr,
8 bit Data
D D D D D D D D A A
7 6 5 4 3 2 1 0 2 2
3 2
A
2
1
A
2
0
A A
1 1
9 8
A
1
7
A
1
6
A A
1 1
5 4
A
1
3
A
1
2
A A
1 1
1 0
A
9
A
8
A A
7 6
A
5
A
4
A A
3 2
A
1
A
0
A A
2 2
3 2
A
2
1
A
2
0
A A
1 1
9 8
A
1
7
A
1
6
A A
1 1
5 4
A
1
3
A
1
2
A A
1 1
1 0
A
9
A
8
A A
7 6
A
5
A
4
A A
3 2
A
1
A
0
0
0
0
0
0
0
0
0
0
0
0
0
MPC5200B
LocaLPlus Bus
Address / Data
Pins
E
X
T
_
A
D
3
1
E
X
T
_
A
D
3
0
E
X
T
_
A
D
2
9
E
X
T
_
A
D
2
8
E
X
T
_
A
D
2
7
E
X
T
_
A
D
2
6
E
X
T
_
A
D
2
5
E
X
T
_
A
D
2
4
E
X
T
_
A
D
2
3
E
X
T
_
A
D
2
2
E
X
T
_
A
D
2
1
E
X
T
_
A
D
2
0
E
X
T
_
A
D
1
9
E
X
T
_
A
D
1
8
E
X
T
_
A
D
1
7
E
X
T
_
A
D
1
6
E
X
T
_
A
D
1
5
Muxed modes
0
All Muxed mode
Address tenures
8 bit Data
tenure
T
S
1
Z
E
2
T
S
1
Z
E
1
T
S
1
Z
E
0
0
B
S
1
B
S
0
A
2
4
D D D D D D D D
7 6 5 4 3 2 1 0
0
0
0
0
16 bit Data tenure
D D D D D D D D D D D D D D D D
1 1 1 1 1 1 9 8 7 6 5 4 3 3 2 0
5 4 3 2 1 0
32 bit Data tenure
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-13
Signal Descriptions
Table 2-4. LocalPlus Pin Functions (Sheet 1 of 3)
LocalPlus
Non-mux
LocalPlus
MULTIPLEXED BUS
PCI BUS
Pin
Name
BALL
MOST
Large
Flash
EXT_AD_31
V01
D7
D15
0
D31
D15
D7
A31
D31
0
0
D31
D15
EXT_AD_30
R03
D6
D14
TSIZ0
D30
D14
D6
A30
D30
0
0
D30
D14
EXT_AD_29
W01
D5
D13
TSIZ1
D29
D13
D5
A29
D29
0
0
D29
D13
EXT_AD_28
T03
D4
D12
TSIZ2
D28
D12
D4
A28
D28
0
0
D28
D12
EXT_AD_27
Y01
D3
D11
0
D27
D11
D3
A27
D27
0
0
D27
D11
EXT_AD_26
T02
D2
D10
BS1
D26
D10
D2
A26
D26
0
0
D26
D10
EXT_AD_25
W02
D1
D9
BS0
D25
D9
D1
A25
D25
0
0
D25
D9
EXT_AD_24
U03
D0
D8
A24
D24
D8
D0
A24
D24
0
0
D24
D8
EXT_AD_23
W03
A23
D7
A23
D23
D7
0
A23
D23
0
0
D23
D7
EXT_AD_22
V03
A22
D6
A22
D22
D6
0
A22
D22
0
0
D22
D6
EXT_AD_21
Y03
A21
D5
A21
D21
D5
0
A21
D21
0
0
D21
D5
EXT_AD_20
V02
A20
D4
A20
D20
D4
0
A20
D20
0
0
D20
D4
EXT_AD_19
Y04
A19
D3
A19
D19
D3
0
A19
D19
0
0
D19
D3
EXT_AD_18
V04
A18
D2
A18
D18
D2
0
A18
D18
0
0
SA_2
D18
D2
EXT_AD_17
Y05
A17
D1
A17
D17
D1
0
A17
D17
0
0
SA_1
D17
D1
EXT_AD_16
W04
A16
D0
A16
D16
D0
0
A16
D16
0
0
SA_0
D16
D0
EXT_AD_15
U08
A15
A15
A15
D15
0
0
A15
D15
D15
0
D15
D15
A15
EXT_AD_14
W09
A14
A14
A14
D14
0
0
A14
D14
D14
0
D14
D14
A14
EXT_AD_13
V08
A13
A13
A13
D13
0
0
A13
D13
D13
0
D13
D13
A13
EXT_AD_12
Y09
A12
A12
A12
D12
0
0
A12
D12
D12
0
D12
D12
A12
EXT_AD_11
V09
A11
A11
A11
D11
0
0
A11
D11
D11
0
D11
D11
A11
EXT_AD_10
Y10
A10
A10
A10
D10
0
0
A10
D10
D10
0
D10
D10
A10
EXT_AD_9
V10
A9
A9
A9
D9
0
0
A9
D9
D9
0
D9
D9
A9
EXT_AD_8
W11
A8
A8
A8
D8
0
0
A8
D8
D8
0
D8
D8
A8
EXT_AD_7
Y11
A7
A7
A7
D7
0
0
A7
D7
D7
D7
D7
D7
A7
EXT_AD_6
U11
A6
A6
A6
D6
0
0
A6
D6
D6
D6
D6
D6
A6
EXT_AD_5
W12
A5
A5
A5
D5
0
0
A5
D5
D5
D5
D5
D5
A5
EXT_AD_4
V11
A4
A4
A4
D4
0
0
A4
D4
D4
D4
D4
D4
A4
EXT_AD_3
Y12
A3
A3
A3
D3
0
0
A3
D3
D3
D3
D3
D3
A3
EXT_AD_2
V12
A2
A2
A2
D2
0
0
A2
D2
D2
D2
D2
D2
A2
EXT_AD_1
W13
A1
A1
A1
D1
0
0
A1
D1
D1
D1
D1
D1
A1
EXT_AD_0
V13
A0
A0
A0
D0
0
0
A0
D0
D0
D0
D0
D0
A0
Addr Addr
32-bit 16-bit 8-bit
PCI
32-bit 16-bit 8-bit
Address
/Data /Data
Data Data Data Address Data Data Data
Phase
24/8 16/16
Phase Phase Phase Phase Phase Phase Phase
ATA
RESET
MPC5200B User’s Manual, Rev. 3
2-14
Freescale Semiconductor
Signal Descriptions
Table 2-4. LocalPlus Pin Functions (Sheet 2 of 3)
LocalPlus
Non-mux
Pin
Name
BALL
LocalPlus
MULTIPLEXED BUS
PCI BUS
Addr Addr
32-bit 16-bit 8-bit
PCI
32-bit 16-bit 8-bit
Address
/Data /Data
Data Data Data Address Data Data Data
Phase
24/8 16/16
Phase Phase Phase Phase Phase Phase Phase
ATA
MOST
Large
Flash
RESET
PCI Dedicated Signals
PCI_PAR
V07
PCI_PAR
A0
A16
PCI_CBE_0
W10
PCI_CBE_0
A1
A17
PCI_CBE_1
Y08
PCI_CBE_1
A2
A18
PCI_CBE_2
W06
PCI_CBE_2
A3
A19
PCI_CBE_3
Y02
PCI_CBE_3
A4
A20
PCI_TRDY
W05
PCI_TRDY
A5
A21
PCI_IRDY
Y06
PCI_IRDY
A6
A22
PCI_STOP
V06
PCI_STOP
A7
A23
PCI_DEVSEL
W07
PCI_DEVSEL
A8
A24
PCI_FRAME
V05
PCI_FRAME
A9
A25
PCI_SERR
W08
PCI_SERR
A10
Note 1
PCI_PERR
Y07
PCI_PERR
A11
Note 1
PCI_IDSEL
U02
PCI_IDSEL
A12
Note 1
PCI_REQ
U01
PCI_REQ
A13
Note 1
PCI_GNT
R04
PCI_GNT
A14
Note 1
PCI_CL0CK
T01
Same as PCI_CLOCK
CLK
OUT
CLK
OUT
PCI_RESET
R02
PCI_RESET
A15
Note 1
CLK
OUT
CLK
OUT
CLK
OUT
CLK
OUT
CLK
OUT
CLK
OUT
ATA Dedicated Signals
ATA_DRQ
V17
ATA_DRQ
A16
ATA_DACK
Y18
ATA_DACK
A17
RST_CFG0
ATA_IOR
Y17
ATA_IOR
A18
RST_CFG1
ATA_IOW
W17
ATA_IOW
A19
RST_CFG2
ATA_IOCHRDY
W18
ATA_IOCHRDY
A20
ATA_INTRQ
Y19
ATA_INTRQ
A21
ATA_ISOLATION
Y16
ATA_ISOLATION
A22
LocalPlus Dedicated Signals
LP_RW
W16
LP_RW
LP_RW
LP_ALE
V14
LP_ACK
U14
LP_TS
Y13
LP_OE
D08
LP_OE
LP_OE
LP_CS0
W14
CS_0 / CS_BOOT
CS_0 / CS_BOOT
LP_CS1
Y14
CS_1
CS_1
LP_ALE
LP_ACK
A23
RST_CFG3
RST_CFG4
LP_ACK, Note 2
LP_TS
LP_TS
RST_CFG5
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-15
Signal Descriptions
Table 2-4. LocalPlus Pin Functions (Sheet 3 of 3)
LocalPlus
Non-mux
LocalPlus
MULTIPLEXED BUS
PCI BUS
Pin
Name
BALL
LP_CS2
V15
CS_2
CS_2
LP_CS3
W15
CS_3
CS_3
LP_CS4
Y15
CS_4
ATA_CS_0
CS_4
LP_CS5
V16
CS_5
ATA_CS_1
CS_5
ATA
Addr Addr
32-bit 16-bit 8-bit
PCI
32-bit 16-bit 8-bit
Address
/Data /Data
Data Data Data Address Data Data Data
Phase
24/8 16/16
Phase Phase Phase Phase Phase Phase Phase
MOST
Large
Flash
RESET
PSC 3 Dedicated Signals
PSC3_4
B06
CS_6
CS_6
PSC3_5
A06
CS_7
CS_7
GPIO_WKUP Dedicated Signals
GPIO_WKUP_7
C12
TSIZ1
JTAG Access Dedicated Signals
TEST_SEL_1
C03
TSIZ2
1. The PCI signals, which are not used as address in Large Flash mode, are drive low during a Large Flash access.
2. For a burst transaction LP_ACK signal indicates the burst
.
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 1 of 17)
PIN / BALL NUMBER
Pin EXT_AD_31
Reset
Value
Function
Description
Ball V01
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
logic 0
D7
D15
D31
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D15
D7
LFLASH
logic 0
LocalPlus Data Bit 7
LocalPlus Data Bit 15
LocalPlus Data Bit 31
hi - z
logic 0
LocalPlus Data Bit 15
D15
hi - z
Large Flash Data Bit D15
MOST Graphics
D31
hi - z
MOST Graphics Data Bit D31
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A31
logic 0
logic 0
D31
hi - z
PCI Address Bit A31
logic 0
logic 0
PCI Data Bit 31
MPC5200B User’s Manual, Rev. 3
2-16
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 2 of 17)
PIN / BALL NUMBER
Pin EXT_AD_30
Reset
Value
Function
Description
Ball R03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
TSIZE0
D6
D14
D30
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D14
D6
LFLASH
D14
hi - z
Large Flash Data Bit D14
MOST Graphics
D30
hi - z
MOST Graphics Data Bit D30
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A30
logic 0
logic 0
D30
Pin EXT_AD_29
hi - z
LocalPlus TSIZE0
LocalPlus Data Bit 6
LocalPlus Data Bit 14
LocalPlus Data Bit 30
hi - z
LocalPlus Data Bit 14
LocalPlus Data Bit 6
hi - z
PCI Address Bit A30
logic 0
logic 0
PCI Data Bit 30
Ball W01
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
TSIZE1
D5
D13
D29
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D13
D5
LFLASH
D13
hi - z
Large Flash Data Bit D13
MOST Graphics
D29
hi - z
MOST Graphics Data Bit D29
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A31
logic 0
logic 0
D29
LocalPlus TSIZE1
LocalPlus Data Bit 5
LocalPlus Data Bit 13
LocalPlus Data Bit 29
hi - z
LocalPlus Data Bit 13
LocalPlus Data Bit 5
hi - z
PCI Address Bit A29
logic 0
logic 0
PCI Data Bit 29
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-17
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 3 of 17)
PIN / BALL NUMBER
Pin EXT_AD_28
Reset
Value
Function
Description
Ball T03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
TSIZE2
D4
D12
D28
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D12
D4
LFLASH
D12
hi - z
Large Flash Data Bit D12
MOST Graphics
D28
hi - z
MOST Graphics Data Bit D28
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A28
logic 0
logic 0
D28
Pin EXT_AD_27
hi - z
TSIZE2
LocalPlus Data Bit 4
LocalPlus Data Bit 12
LocalPlus Data Bit 28
hi - z
LocalPlus Data Bit 12
LocalPlus Data Bit 4
hi - z
PCI Address Bit A28
logic 0
logic 0
PCI Data Bit 28
Ball Y01
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
logic 0
D3
D11
D27
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D11
D3
LFLASH
D11
hi - z
Large Flash Data Bit D11
MOST Graphics
D27
hi - z
MOST Graphics Data Bit D27
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A27
logic 0
logic 0
D27
logic 0
LocalPlus Data Bit 3
LocalPlus Data Bit 11
LocalPlus Data Bit 27
hi - z
LocalPlus Data Bit 11
LocalPlus Data Bit 3
hi - z
PCI Address Bit A27
logic 0
logic 0
PCI Data Bit 27
MPC5200B User’s Manual, Rev. 3
2-18
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 4 of 17)
PIN / BALL NUMBER
Pin EXT_AD_26
Reset
Value
Function
Description
Ball T02
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
BS1
D2
D10
D26
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D10
D2
LFLASH
D10
hi - z
Large Flash Data Bit D10
MOST Graphics
D26
hi - z
MOST Graphics Data Bit D26
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A26
logic 0
logic 0
D26
Pin EXT_AD_25
hi - z
LocalPlus BS1
LocalPlus Data Bit 2
LocalPlus Data Bit 10
LocalPlus Data Bit 26
hi - z
LocalPlus Data Bit 10
LocalPlus Data Bit 2
hi - z
PCI Address Bit A26
logic 0
logic 0
PCI Data Bit 26
Ball W02
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
BS0
D1
D9
D25
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D9
D1
LFLASH
D9
hi - z
Large Flash Data Bit D9
MOST Graphics
D25
hi - z
MOST Graphics Data Bit D25
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A25
logic 0
logic 0
D25
BS0
LocalPlus Data Bit 1
LocalPlus Data Bit 9
LocalPlus Data Bit 25
hi - z
LocalPlus Data Bit 9
LocalPlus Data Bit 1
hi - z
PCI Address Bit A25
logic 0
logic 0
PCI Data Bit 25
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-19
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 5 of 17)
PIN / BALL NUMBER
Pin EXT_AD_24
Reset
Value
Function
Description
Ball U03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A24
D0
D8
D24
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D8
D0
LFLASH
D8
hi - z
Large Flash Data Bit D8
MOST Graphics
D24
hi - z
MOST Graphics Data Bit D24
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A24
logic 0
logic 0
D24
Pin EXT_AD_23
hi - z
LocalPlus Address Bit 24
LocalPlus Data Bit 0
LocalPlus Data Bit 8
LocalPlus Data Bit 24
hi - z
LocalPlus Data Bit 8
LocalPlus Data Bit 0
hi - z
PCI Address Bit A24
logic 0
logic 0
PCI Data Bit 24
Ball W03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A23
logic 0
D7
D23
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D7
A23
LFLASH
D7
hi - z
Large Flash Data Bit D7
MOST Graphics
D23
hi - z
MOST Graphics Data Bit D23
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A23
logic 0
logic 0
D23
Local Address Bit A23
logic 0
LocalPlus Data Bit 7
LocalPlus Data Bit 23
hi - z
LocalPlus Data Bit 7
LocalPlus Address Bit A23
hi - z
PCI Address Bit A23
logic 0
logic 0
PCI Data Bit D23
MPC5200B User’s Manual, Rev. 3
2-20
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 6 of 17)
PIN / BALL NUMBER
Pin EXT_AD_22
Reset
Value
Function
Description
Ball V03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A22
logic 0
D6
D22
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D6
A22
LFLASH
D6
hi - z
Large Flash Data Bit D6
MOST Graphics
D22
hi - z
MOST Graphics Data Bit D22
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A22
logic 0
logic 0
D22
Pin EXT_AD_21
hi - z
LocalPlus Address Bit A22
logic 0
LocalPlus Data Bit 6
LocalPlus Data Bit D22
hi - z
LocalPlus Data Bit D6
LocalPlus Address Bit A22
hi - z
PCI Address Bit A22
logic 0
logic 0
PCI Data Bit D22
Ball Y03
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A21
logic 0
D5
D21
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D5
A21
LFLASH
D5
hi - z
Large Flash Data Bit D5
MOST Graphics
D21
hi - z
MOST Graphics Data Bit D21
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A21
logic 0
logic 0
D21
LocalPlus Address Bit A21
logic 0
LocalPlus Data Bit 5
LocalPlus Data Bit D21
hi - z
LocalPlus Data Bit D5
LocalPlus Address Bit A21
hi - z
PCI Address Bit A21
logic 0
logic 0
PCI Data Bit D21
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-21
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 7 of 17)
PIN / BALL NUMBER
Pin EXT_AD_20
Reset
Value
Function
Description
Ball V02
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A20
logic 0
D4
D20
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D4
A20
LFLASH
D4
hi - z
Large Flash Data Bit D4
MOST Graphics
D20
hi - z
MOST Graphics Data Bit D20
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A20
logic 0
logic 0
D20
Pin EXT_AD_19
hi - z
LocalPlus Address Bit A20
logic 0
LocalPlus Data Bit 4
LocalPlus Data Bit D20
hi - z
LocalPlus Data Bit D4
LocalPlus Address Bit A20
hi - z
PCI Address Bit A20
logic 0
logic 0
PCI Data Bit D20
Ball Y04
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A19
logic 0
D3
D19
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D3
A19
LFLASH
D3
hi - z
Large Flash Data Bit D3
MOST Graphics
D19
hi - z
MOST Graphics Data Bit D19
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A19
logic 0
logic 0
D19
LocalPlus Address Bit A19
logic 0
LocalPlus Data Bit 3
LocalPlus Data Bit D19
hi - z
LocalPlus Data Bit D3
LocalPlus Address Bit A19
hi - z
PCI Address Bit A19
logic 0
logic 0
PCI Data Bit D19
MPC5200B User’s Manual, Rev. 3
2-22
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 8 of 17)
PIN / BALL NUMBER
Pin EXT_AD_18
Reset
Value
Function
Description
Ball V04
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A18
logic 0
D2
D18
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D2
A18
LFLASH
D2
hi - z
Large Flash Data Bit D2
MOST Graphics
D18
hi - z
MOST Graphics Data Bit D18
ATA
ATA_SA_2
hi - z
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A18
logic 0
logic 0
D18
Pin EXT_AD_17
hi - z
LocalPlus Address Bit A18
logic 0
LocalPlus Data Bit 2
LocalPlus Data Bit D18
hi - z
LocalPlus Data Bit D2
LocalPlus Address Bit A18
hi - z
PCI Address Bit A18
logic 0
logic 0
PCI Data Bit D18
Ball Y05
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A17
logic 0
D1
D17
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D1
A17
LFLASH
D1
hi - z
Large Flash Data Bit D1
MOST Graphics
D17
hi - z
MOST Graphics Data Bit D17
ATA
—
—
—
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A17
logic 0
logic 0
D17
LocalPlus Address Bit A17
logic 0
LocalPlus Data Bit 1
LocalPlus Data Bit D17
hi - z
LocalPlus Data Bit D1
LocalPlus Address Bit A17
hi - z
PCI Address Bit A17
logic 0
logic 0
PCI Data Bit D17
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-23
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 9 of 17)
PIN / BALL NUMBER
Pin EXT_AD_16
Function
Reset
Value
Description
Ball W04
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A16
logic 0
D0
D16
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
D0
A16
LFLASH
D0
hi - z
Large Flash Data Bit D0
MOST Graphics
D16
hi - z
MOST Graphics Data Bit D16
ATA
ATA_SA_0
hi - z
ATA_SA_0
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A16
logic 0
logic 0
D16
Pin EXT_AD_15
hi - z
LocalPlus Address Bit A16
logic 0
LocalPlus Data Bit 0
LocalPlus Data Bit D16
hi - z
LocalPlus Data Bit D0
LocalPlus Address Bit A16
hi - z
PCI Address Bit A16
logic 0
logic 0
PCI Data Bit D16
Ball U08
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A15
logic 0
logic 0
D15
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A15
A15
LFLASH
A15
hi - z
Large Flash Address Bit A15
MOST Graphics
D15
hi - z
MOST Graphics Data Bit D15
ATA
ATA_DATA_15 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A15
logic 0
D15
D15
LocalPlus Address Bit A15
logic 0
logic 0
LocalPlus Data Bit D15
hi - z
LocalPlus Address Bit A15
LocalPlus Address Bit A15
ATA Data Bit 15
hi - z
PCI Address Bit A15
logic 0
PCI Data Bit D15
PCI Data Bit D15
MPC5200B User’s Manual, Rev. 3
2-24
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 10 of 17)
PIN / BALL NUMBER
Pin EXT_AD_14
Function
Reset
Value
Description
Ball W09
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A14
logic 0
logic 0
D14
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A14
A14
LFLASH
A14
hi - z
Large Flash Address Bit A14
MOST Graphics
D14
hi - z
MOST Graphics Data Bit D14
ATA
ATA_DATA_14 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A14
logic 0
D14
D14
Pin EXT_AD_13
hi - z
LocalPlus Address Bit A14
logic 0
logic 0
LocalPlus Data Bit D14
hi - z
LocalPlus Address Bit A14
LocalPlus Address Bit A14
ATA_DATA_14
hi - z
PCI Address Bit A14
logic 0
PCI Data Bit D14
PCI Data Bit D14
Ball V08
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A13
logic 0
logic 03
D13
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A13
A13
LFLASH
A13
hi - z
Large Flash Address Bit A13
MOST Graphics
D13
hi - z
MOST Graphics Data Bit D13
ATA
ATA_DATA_13 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A13
logic 0
D13
D13
LocalPlus Address Bit A13
logic 0
logic 0
LocalPlus Data Bit D13
hi - z
LocalPlus Address Bit A13
LocalPlus Address Bit A13
ATA Data Bit D13
hi - z
PCI Address Bit A13
logic 0
PCI Data Bit D13
PCI Data Bit D13
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-25
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 11 of 17)
PIN / BALL NUMBER
Pin EXT_AD_12
Function
Reset
Value
Description
Ball Y09
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A12
logic 0
logic 0
D12
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A12
A12
LFLASH
A12
hi - z
Large Flash Address Bit A12
MOST Graphics
D12
hi - z
MOST Graphics Data Bit D12
ATA
ATA_DATA_12 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A12
logic 0
D12
D12
Pin EXT_AD_11
hi - z
LocalPlus Address Bit A12
logic 0
logic 0
LocalPlus Data Bit D12
hi - z
LocalPlus Address Bit A12
LocalPlus Address Bit A12
ATA_DATA_12
hi - z
PCI Address Bit A12
logic 0
PCI Data Bit D12
PCI Data Bit D12
Ball V09
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A11
logic 0
logic 0
D11
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A11
A11
LFLASH
A11
hi - z
Large Flash Address Bit A11
MOST Graphics
D11
hi - z
MOST Graphics Data Bit D11
ATA
ATA_DATA_11 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A11
logic 0
D11
D11
LocalPlus Address Bit A11
logic 0
logic 0
LocalPlus Data Bit D11
hi - z
LocalPlus Address Bit A11
LocalPlus Address Bit A11
ATA_DATA_11
hi - z
PCI Address Bit A11
logic 0
PCI Data Bit D11
PCI Data Bit D11
MPC5200B User’s Manual, Rev. 3
2-26
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 12 of 17)
PIN / BALL NUMBER
Pin EXT_AD_10
Function
Reset
Value
Description
Ball Y10
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A10
logic 0
logic 0
D10
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A10
A10
LFLASH
A10
hi - z
Large Flash Address Bit A10
MOST Graphics
D10
hi - z
MOST Graphics Data Bit D10
ATA
ATA_DATA_10 hi - z
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A10
logic 0
D10
D10
Pin EXT_AD_9
hi - z
LocalPlus Address Bit A10
logic 0
logic 0
LocalPlus Data Bit D10
hi - z
LocalPlus Address Bit A10
LocalPlus Address Bit A10
ATA_DATA_10
hi - z
PCI Address Bit A10
logic 0
PCI Data Bit D10
PCI Data Bit D10
Ball V10
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A9
logic 0
logic 0
D9
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A9
A9
LFLASH
A9
hi - z
Large Flash Address Bit A9
MOST Graphics
D9
hi - z
MOST Graphics Data Bit D22
ATA
ATA_DATA_9
hi - z
ATA_DATA_9
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A9
logic 0
D9
D9
LocalPlus Address Bit A9
logic 0
logic 0
LocalPlus Data Bit D9
hi - z
LocalPlus Address Bit A9
LocalPlus Address Bit A9
hi - z
PCI Address Bit A9
logic 0
PCI Data Bit D9
PCI Data Bit D9
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-27
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 13 of 17)
PIN / BALL NUMBER
Pin EXT_AD_8
Function
Reset
Value
Description
Ball W11
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A8
logic 0
logic 0
D8
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A8
A8
LFLASH
A8
hi - z
Large Flash Address Bit A8
MOST Graphics
D8
hi - z
MOST Graphics Data Bit D8
ATA
ATA_DATA_8
hi - z
ATA_DATA_8
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A8
logic 0
D8
D8
Pin EXT_AD_7
hi - z
LocalPlus Address Bit A8
logic 0
logic 0
LocalPlus Data Bit D8
hi - z
LocalPlus Address Bit A8
LocalPlus Address Bit A8
hi - z
PCI Address Bit A8
logic 0
PCI Data Bit D8
PCI Data Bit D8
Ball Y11
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A7
logic 0
logic 0
D7
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A7
A7
LFLASH
A7
hi - z
Large Flash Address Bit A7
MOST Graphics
D7
hi - z
MOST Graphics Data Bit D7
ATA
ATA_DATA_7
hi - z
ATA_DATA_7
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A7
D7
D7
D7
LocalPlus Address Bit A7
logic 0
logic 0
LocalPlus Data Bit D7
hi - z
LocalPlus Address Bit A7
LocalPlus Address Bit A7
hi - z
PCI Address Bit A7
PCI Data Bit D7
PCI Data Bit D7
PCI Data Bit D7
MPC5200B User’s Manual, Rev. 3
2-28
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 14 of 17)
PIN / BALL NUMBER
Pin EXT_AD_6
Function
Reset
Value
Description
Ball U11
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A6
logic 0
logic 0
D6
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A6
A6
LFLASH
A6
hi - z
Large Flash Address Bit A6
MOST Graphics
D6
hi - z
MOST Graphics Data Bit D6
ATA
ATA_DATA_6
hi - z
ATA_DATA_6
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A6
D6
D6
D6
Pin EXT_AD_5
hi - z
LocalPlus Address Bit A6
logic 0
logic 0
LocalPlus Data Bit D6
hi - z
LocalPlus Address Bit A6
LocalPlus Address Bit A6
hi - z
PCI Address Bit A6
PCI Data Bit D6
PCI Data Bit D6
PCI Data Bit D6
Ball W12
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A5
logic 0
logic 0
D5
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A5
A5
LFLASH
A5
hi - z
Large Flash Address Bit A5
MOST Graphics
D5
hi - z
MOST Graphics Data Bit D5
ATA
ATA_DATA_5
hi - z
ATA_DATA_5
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A5
D5
D5
D5
LocalPlus Address Bit A5
logic 0
logic 0
LocalPlus Data Bit D5
hi - z
LocalPlus Address Bit A5
LocalPlus Address Bit A5
hi - z
PCI Address Bit A5
PCI Data Bit D5
PCI Data Bit D5
PCI Data Bit D5
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-29
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 15 of 17)
PIN / BALL NUMBER
Pin EXT_AD_4
Function
Reset
Value
Description
Ball V11
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A4
logic 0
logic 0
D4
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A4
A4
LFLASH
A4
hi - z
Large Flash Address Bit A4
MOST Graphics
D4
hi - z
MOST Graphics Data Bit D4
ATA
ATA_DATA_4
hi - z
ATA_DATA_4
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A4
D4
D4
D4
Pin EXT_AD_3
hi - z
LocalPlus Address Bit A4
logic 0
logic 0
LocalPlus Data Bit D4
hi - z
LocalPlus Address Bit A4
LocalPlus Address Bit A4
hi - z
PCI Address Bit A4
PCI Data Bit D4
PCI Data Bit D4
PCI Data Bit D4
Ball Y12
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A3
logic 0
logic 0
D3
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A3
A3
LFLASH
A3
hi - z
Large Flash Address Bit A3
MOST Graphics
D3
hi - z
MOST Graphics Data Bit D3
ATA
ATA_DATA_3
hi - z
ATA_DATA_3
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A3
D3
D3
D3
LocalPlus Address Bit A3
logic 0
logic 0
LocalPlus Data Bit D3
hi - z
LocalPlus Address Bit A3
LocalPlus Address Bit A3
hi - z
PCI Address Bit A3
PCI Data Bit D3
PCI Data Bit D3
PCI Data Bit D3
MPC5200B User’s Manual, Rev. 3
2-30
Freescale Semiconductor
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 16 of 17)
PIN / BALL NUMBER
Pin EXT_AD_2
Function
Reset
Value
Description
Ball V12
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A2
logic 0
logic 0
D2
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A2
A2
LFLASH
A2
hi - z
Large Flash Address Bit A2
MOST Graphics
D2
hi - z
MOST Graphics Data Bit D2
ATA
ATA_DATA_2
hi - z
ATA_DATA_2
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A2
D2
D2
D2
Pin EXT_AD_1
hi - z
LocalPlus Address Bit A2
logic 0
logic 0
LocalPlus Data Bit D2
hi - z
LocalPlus Address Bit A2
LocalPlus Address Bit A2
hi - z
PCI Address Bit A2
PCI Data Bit D2
PCI Data Bit D2
PCI Data Bit D2
Ball W13
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A1
logic 0
logic 0
D1
hi - z
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A1
A1
LFLASH
A1
hi - z
Large Flash Address Bit A1
MOST Graphics
D1
hi - z
MOST Graphics Data Bit D1
ATA
ATA_DATA_1
hi - z
ATA_DATA_1
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A1
D1
D1
D1
LocalPlus Address Bit A1
logic 0
logic 0
LocalPlus Data Bit D1
hi - z
LocalPlus Address Bit A1
LocalPlus Address Bit A1
hi - z
PCI Address Bit A1
PCI Data Bit D1
PCI Data Bit D1
PCI Data Bit D1
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-31
Signal Descriptions
Table 2-5. LocalPlus Bus Address / Data Signals (Sheet 17 of 17)
PIN / BALL NUMBER
Pin EXT_AD_0
Function
Reset
Value
Description
Ball V13
LocalPlus Bus multiplexed mode
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A0
logic 0
logic 0
D0
LocalPlus non-mux
16-bit addr/16-bit data
24-bit addr/8-bit data
A0
A0
LFLASH
A0
hi - z
Large Flash Address Bit A0
MOST Graphics
D0
hi - z
MOST Graphics Data Bit D0
ATA
ATA_DATA_0
hi - z
ATA_DATA_0
PCI
Address Phase
8-Bit Data Phase
16-Bit Data Phase
32-Bit Data Phase
A0
logic 0
logic 0
D0
hi - z
LocalPlus Address Bit A0
logic 0
logic 0
LocalPlus Data Bit D0
hi - z
LocalPlus Address Bit A0
LocalPlus Address Bit A0
hi - z
PCI Address Bit A0
PCI Data Bit 0
PCI Data Bit 0
PCI Data Bit D0
MPC5200B User’s Manual, Rev. 3
2-32
Freescale Semiconductor
Signal Descriptions
Table 2-6. PCI Dedicated Signals
Pin / Ball Number
Pin PCI_PAR
Function
Reset
Value
Description
Ball V07
PCI
PCI_PAR
logic 1
PCI Bus Parity
LFLASH
A16
logic 1
Large Flash Address Bit A16
MOST Graphics
A0
logic 1
MOST Graphics Address Bit A0
PCI
PCI_CBE_0
logic 1
PCI Command Byte Enable 0
LFLASH
A17
logic 1
Large Flash Address Bit A17
MOST Graphics
A1
logic 1
MOST Graphics Address Bit A1
PCI
PCI_CBE_1
logic 1
PCI Command Byte Enable 1
LFLASH
A18
logic 1
Large Flash Address Bit A18
MOST Graphics
A2
logic 1
MOST Graphics Address Bit A2
PCI
PCI_CBE_2
logic 1
PCI Command Byte Enable 2
LFLASH
A19
logic 1
Large Flash Address Bit A19
MOST Graphics
A3
logic 1
MOST Graphics Address Bit A3
PCI
PCI_CBE_3
logic 1
PCI Command Byte Enable 3
LFLASH
A20
logic 1
Large Flash Address Bit A20
MOST Graphics
A4
logic 1
MOST Graphics Address Bit A4
PCI
PCI_TRDY
logic 1
PCI_TRDY
PCI Target Ready
LFLASH
A21
logic 1
Large Flash Address Bit A21
MOST Graphics
A5
logic 1
MOST Graphics Address Bit A5
PCI
PCI_IRDY
logic 1
PCI Initiator (HOST) Ready
LFLASH
A22
logic 1
Large Flash Address Bit A22
MOST Graphics
A6
logic 1
MOST Graphics Address Bit A6
Pin PCI_CBE_0
Pin PCI_CBE_1
Pin PCI_CBE_2
Pin PCI_CBE_3
Pin PCI_TRDY
Pin PCI_IRDY
Ball W10
Ball Y08
Ball W06
Ball Y02
Ball W05
Ball Y06
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-33
Signal Descriptions
Table 2-6. PCI Dedicated Signals (continued)
Pin / Ball Number
Pin PCI_STOP
Reset
Value
Function
Description
Ball V06
PCI
PCI_STOP
logic 1
PCI Transition Stop
LFLASH
A23
logic 1
Large Flash Address Bit A23
MOST Graphics
A7
logic 1
MOST Graphics Address Bit A7
PCI
PCI_DEVSEL
logic 1
PCI Device Select
LFLASH
A24
logic 1
Large Flash Address Bit A24
MOST Graphics
A8
logic 1
MOST Graphics Address Bit A8
PCI
PCI_FRAME
logic 1
PCI Frame Start
LFLASH
A25
logic 1
Large Flash Address Bit A25
MOST Graphics
A9
logic 1
MOST Graphics Address Bit A9
PCI
PCI_SERR
logic 1
PCI System Error (open drain)
MOST Graphics
A10
logic 1
MOST Graphics Address Bit A10
PCI
PCI_SERR
logic 1
PCI Parity Error
MOST Graphics
A11
logic 1
MOST Graphics Address Bit A11
PCI
PCI_IDSEL
logic 1
PCI Initial Device Select
MOST Graphics
A12
logic 1
MOST Graphics Address Bit A12
PCI
PCI_REQ
logic 1
PCI Bus Request
MOST Graphics
A13
logic 1
MOST Graphics Address Bit A13
PCI
PCI_GNT
logic 1
PCI Bus Grant
MOST Graphics
A14
logic 1
MOST Graphics Address Bit A14
PCI_CLOCK
clk
PCI Clock
PCI
PCI_RESET
logic 0
PCI Reset Output (open drain)
MOST Graphics
A15
logic 0
MOST Graphics Address Bit A15
Pin PCI_DEVSEL
Pin PCI_FRAME
Pin PCI_SERR
Pin PCI_PERR
Pin PCI_IDSEL
Pin PCI_REQ
Pin PCI_GNT
Pin PCI_CLOCK
Ball W07
Ball V05
Ball W08
Ball Y07
Ball U02
Ball U01
Ball R04
Ball T01
PCI
Pin PCI_RESET
Ball R02
MPC5200B User’s Manual, Rev. 3
2-34
Freescale Semiconductor
Signal Descriptions
Table 2-7. ATA Dedicated Signals
PIN / BALL NUMBER
Pin ATA_DRQ
Function
Reset
Value
Description
Ball V17
ATA
ATA_DRQ
logic 0
ATA DMA Request
MOST Graphics
A16
logic 0
MOST Graphics Address Bit A16
ATA
ATA_DACK
logic 1
ATA DMA Request
MOST Graphics
A17
logic 1
MOST Graphics Address Bit A17
Pin ATA_DACK
Ball Y18
RESET Config.
Pin ATA_IOR
bit 0 - ppc_pll_cfg_4
Ball Y17
ATA
ATA_IOR
logic 1
ATA read - 0, no read - 1
MOST Graphics
A18
logic 1
MOST Graphics Address Bit A18
RESET Config.
RST_CFG1
Pin ATA_IOW
bit 1- ppc_pll_cfg_3
Ball W17
ATA
ATA_IOW
logic 1
ATA write - 0, no write - 1
MOST Graphics
A19
logic 1
MOST Graphics Address Bit A19
RESET Config.
RST_CFG2
Pin ATA_IOCHDRY
bit 2 - ppc_pll_cfg_2
Ball W18
ATA
ATA_IOCHDRY
logic 1
ATA negated to extend transfer
MOST Graphics
A20
logic 1
MOST Graphics Address Bit A20
ATA
ATA_INTRQ
logic 1
ATA Interrupt Request
MOST Graphics
A21
logic 1
MOST Graphics Address Bit A21
ATA
ATA_ISOLATION
logic 1
ATA Levelshifter control signal
MOST Graphics
A22
logic 1
MOST Graphics Address Bit A22
Pin ATA_INTRQ
Pin ATA_ISOLATION
Ball Y19
Ball Y16
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-35
Signal Descriptions
Table 2-8. LocalPlus Dedicated Signals
PIN / BALL NUMBER
Pin LP_RW
Function
Reset
Value
Description
Ball W16
LocalPlus
Read/Write
logic 1
LocalPlus Read/Write LIne
Reset Configuration
RST_CFG3
logic 1
Bit 3 - ppc_pll_cfg_1
LocalPlus
Address Latch
Enable
logic 1
LocalPlus Address Latch Enable for Multiplexed Transitions
MOST Graphics
A23
logic 1
MOST Graphics Address Bit A23
Reset Configuration
RST_CFG4
logic 1
Bit 4 ppc_pll_cfg_0
Pin LP_ALE
Pin LP_ACK
Ball V14
Ball U14
LocalPlus
LP Acknowledge logic 1
Acknowledge signal for LP peripherals. Acknowledge signal
for Large Flash or MOST Graphics, if bursts are not enabled.
LFLASH
BRST
logic 1
BURST indication for Large Flash, if bursts are enabled
MOST Graphics
BRST
logic 1
BURST indication for MOST Graphics, if bursts are enabled
Pin LP_TS
Ball Y13
LocalPlus
LP Transfer Start logic 1
LocalPlus Transfer Start
Reset Configuration 5
RST_CFG5
logic 1
Bit 5 - xlb_clk_sel
bit = 0: XLB_CLK = fsystem / 4
bit = 1: XLB_CLK = fsystem / 8
LP Output
Enable
logic 1
LocalPlus Output Enable
Pin LP_OE
LocalPlus
Ball D08
MPC5200B User’s Manual, Rev. 3
2-36
Freescale Semiconductor
Signal Descriptions
UART1(e)
CODEC1
5
4
AC971
GPIO
5
5
Pin Drivers and MUX Logic
PSC_0
PSC_2
PSC_1
PSC_3
PSC_4
Function
Port_conf
[29:31]
GPIO
00X
GPIO
AC97_1
01X
AC97_1_SDATA_OUT AC97_1_SDATA_IN AC97_1_SYNC AC97_1_BITCLK AC97_1_RES
UART1
100
UART1_TXD
UART1_RXD
UART1_RTS
UART2_CTS
GPIO_W/WAKE_UP
UART1e
101
UART1e_TXD
UART1e_RXD
UART1e_RTS
UART1e_CTS
UART1e_DCD
CODEC1
110
CODEC1_TXD
CODEC1_RXD
GPIO
CODEC1_CLK
CODEC1_FRAME
CODEC1
w/ MCLK
111
CODEC1_w/
MCLK_TXD
CODEC1_w/
MCLK_RXD
CODEC1_w/
MCLK_MCLK
CODEC1_w/
MCLK_CLK
CODEC1_w/
MCLK_FRAME
PSC_0
PSC_1
GPIO
PSC_2
GPIO
PSC_3
PSC_4
GPIO
GPIO_W/WAKE_UP
Notes:
1. CODEC usage leaves pin 3 open for simple GPIO.
2. If port otherwise unused, all five pins are available as GPIO.
3. CODEC plus additional GPIO from elsewhere can implement Soft Modem or RS-232 functionality.
4. AC’97 usage is limited to PSC1 and PSC2.
Figure 2-4. PSC1 Port Map—5 Pins
Table 2-9. PSC1 Pin Functions
Pin Name
Dir.
GPIO
AC97_1
UART1
UART1e
CODEC1
CODEC1 w/
MCLK
PSC1_0
I/O
GPIO
AC97_1_SDATA_
OUT
UART1_TXD
UART1e_TXD
CODEC1_
TXD
CODEC1_w/
MCLK_TXD
PSC1_1
I/O
GPIO
AC97_1_SDATA_IN
UART1_RXD
UART1e_RXD
CODEC1_
RXD
CODEC1_w/
MCLK_RXD
PSC1_2
I/O
GPIO
AC97_1_SYNC
UART1_RTS
UART1e_RTS
GPIO
CODEC1_w/
MCLK_MCLK
PSC1_3
I/O
GPIO
AC97_1_BITCLK
UART1_CTS
UART1e_CTS
CODEC1_CLK
CODEC1_w/
MCLK_CLK
PSC1_4
I/O
GPIO_W/
WAKE_
UP
AC97_1_RES
GPIO_W/
WAKE_UP
UART1e_DCD
CODEC1_
FRAME
CODEC1_w/
MCLK_FRAME
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-37
Signal Descriptions
Table 2-10. PSC1 Functions by Pin
Pin / Ball Number
Pin PSC1_0
Function
Reset
Value
Description
Ball B11
GPIO
hi - z
GPIO
Simple General Purpose I/O
AC97_1
hi - z
AC97_1_SDATA_OUT
AC97 Serial Data Out
UART1
hi - z
UART1_TXD
Transmit Data
UART1e
hi - z
UART1e_TXD
Transmit Data
CODEC1
hi - z
CODEC1_TXD
Transmit Data
CODEC1_w/MCLK
hi - z
CODEC1_w/MCLK_TXD
Transmit Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
AC97_1
hi - z
AC97_1_SDATA_IN
AC97 Serial Data In
UART1
hi - z
UART1_RXD
Receive Data
UART1e
hi - z
UART1e_RXD
Receive Data
CODEC1
hi - z
CODEC1_RXD
Receive Data
CODEC1_w/MCLK
hi - z
CODEC1_w/MCLK_RXD
Receive Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
AC97_1
hi - z
AC97_1_SYNC
AC97 Frame Sync
UART1
hi - z
UART1_RTS
Ready To Send
UART1e
hi - z
UART1e_RTS
Ready To Send
CODEC1
hi - z
GPIO
Simple General Purpose I/O
CODEC1_w/MCLK
hi - z
CODEC1_w/MCLK _MCLK
Pin PSC1_1
Pin PSC1_2
Ball A11
Ball C10
MPC5200B User’s Manual, Rev. 3
2-38
Freescale Semiconductor
Signal Descriptions
Table 2-10. PSC1 Functions by Pin (continued)
Pin / Ball Number
Pin PSC1_3
Function
Reset
Value
Description
Ball B10
GPIO
hi - z
GPIO
Simple General Purpose I/O
AC97_1
hi - z
AC97_1_BITCLK
AC97 Bit Clock
UART1
hi - z
UART1_CTS
UART Clear To Send
UART1e
hi - z
UART1e_CTS
UARTe Clear To Send
CODEC1
hi - z
CODEC1_CLK
CODEC Bit Clock
CODEC1_w/MCLK
hi - z
CODEC1_w/MCLK_CLK
CODEC Bit Clock
GPIO
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
AC97_1
hi - z
AC97_1_RES
AC97 Reset
UART1
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
UART1e
hi - z
UART1e_DCD
UARTe Carrier Detect
CODEC1
hi - z
CODEC1_FRAME
CODEC Frame Sync
CODEC1_w/MCLK
hi - z
CODEC1_w/MCLK_FRAME
CODEC Frame Sync
Pin PSC1_4
Ball A10
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-39
Signal Descriptions
UART2(e)
CODEC2
5
AC972
4
CAN1/2
GPIO
4
5
5
Pin Drivers and MUX Logic
PSC2_0
PSC2_1
PSC2_2
PSC2_3
PSC2_4
Function
Port_conf
[25:27]
GPIO
000
GPIO
GPIO
GPIO
GPIO
GPIO_W/WAKE_UP
CAN1/2
001
CAN1_TX
CAN1_RX
CAN2_TX
CAN2_RX
GPIO_W/WAKE_UP
AC97_2
01X
AC97_2_SDATA_OUT AC97_2_SDATA_IN AC97_2_SYNC AC97_2_BITCLK AC97_2_RES
UART2
100
UART2_TXD
UART2_RXD
UART2_RTS
UART2_CTS
GPIO_W/WAKE_UP
UART2e
101
UART2e_TXD
UART2e_RXD
UART2e_RTS
UART2e_CTS
UART2e_DCD
CODEC2
110
CODEC2_TXD
CODEC2_RXD
GPIO
CODEC2_CLK
CODEC2_FRAME
CODEC2 w/
MCLK
111
CODEC2_w/
MCLK_TXD
CODEC2_w/
MCLK_RXD
CODEC2_w/
MCLK_MCLK
CODEC2_w/
MCLK_CLK
CODEC2_w/
MCLK_FRAME
PSC_0
PSC_1
PSC_2
PSC_3
PSC_4
Notes:
1.
2.
3.
4.
5.
CODEC usage leaves pin 3 open for simple GPIO.
CAN usage leaves pin 5 open for WakeUp GPIO.
CODEC plus additional GPIO from elsewhere can implement Soft Modem or RS-232 functionality.
AC97 usage is limited to PSC1 or PSC2.
MSCAN ports 1 and 2 can be configured here or on timer/I2C ports. They cannot be split.
(i.e., put CAN1 on PSC2 and CAN2 on the timer port).
6. CAN RX input supports WakeUp functionality.
Figure 2-5. PSC2 Port Map—5 Pins
Table 2-11. PSC2 Pin Functions
Pin
Name
Dir.
GPIO
CAN1/2
AC97_2
UART2
UART2e
CODEC2
PSC2_0
I/O
GPIO
CAN1_TX
AC97_2_SDATA_OUT
UART2_TXD
UART2e_TXD
CODEC2_TXD
CODEC2_w/
MCLK_TXD
PSC2_1
I/O
GPIO
CAN1_RX
AC97_2_SDATA_IN
UART2_RXD
UART2e_RXD
CODEC2_RXD
CODEC2_w/
MCLK_RXD
PSC2_2
I/O
GPIO
CAN2_TX
AC97_2_SYNC
UART2_RTS
UART2e_RTS
GPIO
CODEC2_w/
MCLK_MCLK
PSC2_3
I/O
GPIO
CAN2_RX
AC97_2_BITCLK
UART2_CTS
UART2e_CTS
CODEC2_CLK
CODEC2_w/
MCLK_CLK
PSC2_4
I/O
GPIO_w/
WAKE_UP
GPIO_w/
WAKE_UP
AC97_2_RES
GPIO_w/
WAKE_UP
UART2e_DCD CODEC2_FRAME
CODEC2 w/
MCLK
CODEC2_w/
MCLK_FRAME
MPC5200B User’s Manual, Rev. 3
2-40
Freescale Semiconductor
Signal Descriptions
Table 2-12. PSC2 Functions by Pin
Pin / Ball Number
Pin PSC2_0
Function
Reset
Value
Description
Ball C09
GPIO
hi - z
GPIO
Simple General Purpose I/O
CAN1, CAN2
hi - z
CAN1_TX
CAN Transmit
AC97_2
hi - z
AC97_2_SDATA_OUT
AC97 Serial Data Out
UART2
hi - z
UART2_TXD
Transmit Data
UART2e
hi - z
UART2e_TXD
Transmit Data
CODEC2
hi - z
CODEC2_TXD
Transmit Data
CODEC2_w/MCLK
hi - z
CODEC2_w/MCLK_TXD
Transmit Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
CAN_1, CAN_2
hi - z
CAN1_RX
CAN Receive
AC97_2
hi - z
AC97_2_SDATA_IN
AC97 Serial Data In
UART2
hi - z
UART2_RXD
Receive Data
UART2e
hi - z
UART2e_RXD
Receive Data
CODEC2
hi - z
CODEC2_RXD
Receive Data
Pin PSC2_1
Ball B09
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-41
Signal Descriptions
Table 2-12. PSC2 Functions by Pin (continued)
Pin / Ball Number
Pin PSC2_2
Function
Reset
Value
Description
Ball A09
GPIO
hi - z
GPIO
Simple General Purpose I/O
CAN1, CAN2
hi - z
CAN2_TX
CAN Transmit
AC97_2
hi - z
AC97_2_SYNC
AC97 Frame Sync
UART2
hi - z
UART2_RTS
Ready To Send
UART2e
hi - z
UART2e_RTS
Ready To Send
CODEC2
hi - z
GPIO
Simple General Purpose I/O
GPIO
hi - z
GPIO
Simple General Purpose I/O
CAN1, CAN2
hi - z
CAN2_RX
CAN Receive Data
AC97_2
hi - z
AC97_2_BITCLK
AC97 Bit Clock
UART2
hi - z
UART2_CTS
UART Clear To Send
UART2e
hi - z
UART2e_CTS
UARTe Clear To Send
CODEC2
hi - z
CODEC2_CLK
CODEC Bit Clock
GPIO
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
CAN1, CAN2
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
AC97_2
hi - z
AC97_2_RES
AC97 Reset
UART2
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
UART2e
hi - z
UART2e_DCD
UARTe Carrier Detect
CODEC2
hi - z
CODEC2_FRAME
CODEC Frame
Pin PSC2_3
Pin PSC2_4
Ball B08
Ball A08
MPC5200B User’s Manual, Rev. 3
2-42
Freescale Semiconductor
Signal Descriptions
UART3(e)
CODEC3
5
4
USB2
SPI
10
GPIO
10
4
Pin Drivers and MUX Logic
PSC3_0
Function
Port_
conf
[20:23]
GPIO
0000
GPIO
GPIO
USB2
0001
USB2_OE
UART3
0100
UART3e
PSC3_0
PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8
PSC3_1
PSC3_2
GPIO
PSC3_3
GPIO
PSC3_4
PSC3_5
PSC3_6
LP_CS_6_ LP_CS_7_ GPIO
GPIO/
GPIO/
INTERRUPT INTERRUPT
PSC3_7
PSC3_8
PSC3_9
PSC3_9
GPIO
GPIO/
GPIO_W/
INTERRUPT WAKE-UP
USB2_TXN USB2_TXP USB2_RXD USB2_RXP USB2_RXN USB2_
PRTPWR
USB2_
SPEED
USB2_
SUSPEND
UART3_
TXD
UART3_
RXD
UART3_
RTS
UART3_
CTS
LP_CS_6
LP_CS_7
GPIO
GPIO
GPIO/
GPIO_W/
INTERRUPT WAKE_UP
0101
UART3e_
TXD
UART3e_
RXD
UART3e_
RTS
UART3e_
CTS
UART3e_
DCD
LP_CS_7
GPIO
GPIO
GPIO/
GPIO_W/
INTERRUPT WAKE_UP
CODEC3
0110
CODEC3_
TXD
CODEC3_
RXD
CODEC3_
CLK
CODEC3_
FRAME
LP_CS_6
LP_CS_7
GPIO
GPIO
GPIO/
GPIO_W/
INTERRUPT WAKE_UP
CODEC3 w/
MCLK
0111
CODEC3_ CODEC3_ CODEC3_
w/
w/
w/MCLK_
MCLK_TXD MCLK_RXD CLK
CODEC3_w LP_CS_6
/MCLK_
FRAME
LP_CS_7
CODEC3_w GPIO
/MCLK_
MCLK
GPIO/
GPIO_W/
INTERRUPT WAKE-UP
SPI
100X
GPIO
GPIO
GPIO
GPIO
LP_CS_6
LP_CS_7
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
UART3 /
SPI
1100
UART3_
TXD
UART3_
RXD
UART3_
RTS
UART3_
CTS
LP_CS_6
LP_CS_7
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
UART3e /
SPI
1101
UART3e_
TXD
UART3e_
RXD
UART3e_
RTS
UART3e_
CTS
UART3e_
DCD
LP_CS_7
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
CODEC3 /
SPI
111X
CODEC3_
TXD
CODEC3_
RXD
CODEC3_
CLK
CODEC3_
FRAME
LP_CS_6
LP_CS_7
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
USB2_OVRCNT
Notes:
1. If Soft Modem or RS-232 functionality is desired, use UARTe/CODEC function and use available
GPIO from this or any other port.
2. Second USB port (USB2) can be configured on PSC3 or on the Ethernet port, but not both locations.
3. PSC3_4 can be configured to be LP_CS6 or an interrupt GPIO, except when PS3 is in USB2 or UART3e modes
In these modes, CS6 is not available.
4. PSC3_5 can be configured to be LP_CS7 or an interrupt GPIO, except when PS3 is in USB2 mode.
In this mode, LP_CS7 is not available.
Figure 2-6. PSC3 Port Map—10 Pins
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-43
Signal Descriptions
Table 2-13. PSC3 Pin Functions
Pin Name
Dir.
GPIO
USB2
UART3
UART3e
CODEC3
PSC3_0
I/O (O)
GPIO
USB2_OE
UART3_TXD
UART3e_TXD
CODEC3_TXD
PSC3_1
I/O(I)
GPIO
USB2_TXN
UART3_RXD
UART3e_RXD
CODEC3_RXD
PSC3_2
I/O(I)
GPIO
USB2_TXP
UART3_RTS
UART3e_RTS
CODEC3_CLK
PSC3_3
I/O(I)
GPIO
USB2_RXD
UART3_CTS
UART3e_CTS
CODEC3_FRAME
PSC3_4
I/O(I)
LP_CS_6_
GPIO/INTERRUPT
USB2_RXP
LP_CS_6
UART3e_DCD
LP_CS_6
PSC3_5
I/O
LP_CS_7_
GPIO/INTERRUPT
USB2_RXN
LP_CS_7
LP_CS_7
LP_CS_7
PSC3_6
I/O
GPIO
USB2_PRTPWR
GPIO
GPIO
GPIO
PSC3_7
I/O
GPIO
USB2_SPEED
GPIO
GPIO
GPIO
PSC3_8
I/O
GPIO_
INTERRUPT_8
USB2_SUSPEND
GPIO_INTERRUPT
GPIO_INTERRUPT
GPIO_INTERRUPT
PSC3_9
I/O
GPIO_W/WAKE-UP
USB2_OVRCNT
GPIO_W/WAKE_UP
GPIO_W/WAKE_UP
GPIO_W/WAKE_UP
Table 2-14. PSC3 Pin Functions
Pin Name
Dir.
CODEC3 w/ M
SPI
UART3 / SPI
UART3e / SPI
CODEC3 / SPI
PSC3_0
I/O
CODEC3_w/MCLK_TXD
GPIO
UART3_TXD
UART3e_TXD
CODEC3_TXD
PSC3_1
I/O
CODEC3_w/MCLK_RXD
GPIO
UART3_RXD
UART3e_RXD
CODEC3_RXD
PSC3_2
I/O
CODEC3_w/MCLK_CLK
GPIO
UART3_RTS
UART3e_RTS
CODEC3_CLK
PSC3_3
I/O
CODEC3_w/MCLK_FRAME
GPIO
UART3_CTS
UART3e_CTS
CODEC3_FRAME
PSC3_4
I/O
LP_CS_6
LP_CS_6
LP_CS_6
UART3e_DCD
LP_CS_6
PSC3_5
I/O
LP_CS_7
LP_CS_7
LP_CS_7
LP_CS_7
LP_CS_7
PSC3_6
I/O
CODEC3_w/MCLK_MCLK
SPI_MOSI
SPI_MOSI
SPI_MOSI
SPI_MOSI
PSC3_7
I/O
GPIO
SPI_MISO
SPI_MISO
SPI_MISO
SPI_MISO
PSC3_8
I/O
GPIO_INTERRUPT
SPI_SS
SPI_SS
SPI_SS
SPI_SS
PSC3_9
I/O
GPIO_W/WAKE-UP
SPI_CLK
SPI_CLK
SPI_CLK
SPI_CLK
MPC5200B User’s Manual, Rev. 3
2-44
Freescale Semiconductor
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 1 of 7)
Pin / Ball Number
Pin PSC3_0
Function
Reset
Value
Description
Ball C07
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_OE
USB Output Enable
UART3
hi - z
UART3_TXD
Uart Transmit Data
UART3e
hi - z
UART3e_TXD
Uart Transmit Data
CODEC3
hi - z
CODEC3_TXD
CODEC Transmit Data
CODEC3_w/MCLK
hi - z
CODEC3_w/MCLK_TXD
CODEC Transmit Data
SPI
hi - z
GPIO
Simple General Purpose I/O
UART3, SPI
hi - z
UART3_TXD
Uart Transmit Data
UART3e,SPI
hi - z
UART3e_TXD
Uart Transmit Data
CODEC3, SPI
hi - z
CODEC3_TXD
CODEC Transmit Data
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-45
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 2 of 7)
Pin / Ball Number
Pin PSC3_1
Function
Reset
Value
Description
Ball B07
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_TXN
USB Transmit Negative
UART3
hi - z
UART3_RXD
Uart Receive Data
UART3e
hi - z
UART3e_RXD
Uart Receive Data
CODEC3
hi - z
CODEC3_RXD
CODEC Receive Data
CODEC3_w/MCLK
hi - z
CODEC3_w/MCLK_RXD
CODEC Receive Data
SPI
hi - z
GPIO
Simple General Purpose I/O
UART3, SPI
hi - z
UART3_RXD
Uart Receive Data
UART3e,SPI
hi - z
UART3e_RXD
Uart Receive Data
CODEC3, SPI
hi - z
CODEC3_RXD
CODEC Receive Data
MPC5200B User’s Manual, Rev. 3
2-46
Freescale Semiconductor
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 3 of 7)
Pin / Ball Number
Pin PSC3_2
Function
Reset
Value
Description
Ball A07
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_TXP
USB Transmit Positive
UART3
hi - z
UART3_RTS
Uart Ready To Send
UART3e
hi - z
UART3e_RTS
Uart Ready To Send
CODEC3
hi - z
CODEC3_CLK
CODEC Bit Clock
CODEC3_w/MCLK
hi - z
CODEC3_w/MCLK_CLK
CODEC Bit Clock
SPI
hi - z
GPIO
Simple General Purpose I/O
UART3, SPI
hi - z
UART3_RTS
Uart Ready to Send
UART3e, SPI
hi - z
UART3_RTS
Uart Ready To Send
CODEC3, SPI
hi - z
CODEC3_CLK
CODEC Clock
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-47
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 4 of 7)
Pin / Ball Number
Pin PSC3_3
Function
Reset
Value
Description
Ball C06
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_RXD
USB Receive Data
UART3
hi - z
UART3_CTS
Uart Clear To Send
UART3e
hi - z
UART3e_CTS
Uart Clear To Send
CODEC3
hi - z
CODEC3_FRAME
CODEC Frame Sync
CODEC3_w/MCLK
hi - z
CODEC3_w/MCLK_FRAME
CODEC Frame Sync
SPI
hi - z
GPIO
Simple General Purpose I/O
UART3, SPI
hi - z
UART3_CTS
Uart Clear to Send
UART3e, SPI
hi - z
UART3e_CTS
Uart Clear To Send
CODEC3, SPI
hi - z
CODEC3_FRAME
CODEC Frame Sync
GPIO
hi - z
LP_CS_6_GPIO_INTERRUPT
USB2
hi - z
USB2_RXP
USB Receive Positive
UART3
hi - z
LP_CS_6_GPIO_INTERRUPT
UART3e
hi - z
UART3e_DCD
UART3e Carrier Detect
CODEC3
hi - z
LP_CS_6
CODEC3_w/MCLK
hi - z
LP_CS_6
SPI
hi - z
LP_CS_6
UART3, SPI
hi - z
LP_CS_6
UART3e,SPI
hi - z
UART3e_DCD
UART3e Carrier Detect
CODEC3, SPI
hi - z
LP_CS_6
Pin PSC3_4
Ball B06
MPC5200B User’s Manual, Rev. 3
2-48
Freescale Semiconductor
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 5 of 7)
Pin / Ball Number
Pin PSC3_5
Function
Reset
Value
Description
Ball A06
GPIO
hi - z
LP_CS_7_GPIO_INTERRUPT
USB2
hi - z
USB2_RXN
USB Receive Positive
UART3
hi - z
LP_CS_7
UART3e
hi - z
LP_CS_7
CODEC3
hi - z
LP_CS_7
CODEC3_w/MCLK
hi - z
CODEC3_w/MCLK_MCLK
CODEC Clock
SPI
hi - z
LP_CS_7
UART3, SPI
hi - z
LP_CS_7
UART3e,SPI
hi - z
LP_CS_7
CODEC3, SPI
hi - z
LP_CS_7
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_PRTPWR
USB Port Power
UART3
hi - z
GPIO
Simple General Purpose I/O
UART3e
hi - z
GPIO_
Simple General Purpose I/O
CODEC3
hi - z
GPIO
Simple General Purpose I/O
CODEC3_w/MCLK
hi - z
LP_CS_7
SPI
hi - z
SPI_MOSI
SPI_Master Out Slave In
UART3, SPI
hi - z
SPI_MOSI
SPI_Master Out Slave In
UART3e, SPI
hi - z
SPI_MOSI
SPI_Master Out Slave In
CODEC3, SPI
hi - z
SPI_MOSI
SPI_Master Out Slave In
Pin PSC3_6
Ball C05
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-49
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 6 of 7)
Pin / Ball Number
Pin PSC3_7
Function
Reset
Value
Description
Ball B05
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB2
hi - z
USB2_SPEED
USB Speed
UART3
hi - z
GPIO
Simple General Purpose I/O
UART3e
hi - z
GPIO
Simple General Purpose I/O
CODEC3
hi - z
GPIO
Simple General Purpose I/O
CODEC3_w/MCLK
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
SPI_MISO
SPI Master In Slave Out
UART3, SPI
hi - z
SPI_MISO
SPI Master In Slave Out
UART3e, SPI
hi - z
SPI_MISO
SPI Master In Slave Out
CODEC3, SPI
hi - z
SPI_MISO
SPI Master In Slave Out
GPIO
hi - z
GPIO/INTERRUPT
Simple General Purpose I/O/INTERRUPT
USB_2
hi - z
USB2_SUSPEND
USB Suspend
UART3
hi - z
GPIO_INTERRUPT
UART3e
hi - z
GPIO_INTERRUPT
CODEC3
hi - z
GPIO_INTERRUPT
CODEC3_w/MCLK
hi - z
GPIO_INTERRUPT
SPI
hi - z
SPI_SS
SPI Slave Select
UART_3, SPI
hi - z
SPI_SS
SPI Slave Select
UART3e, SPI
hi - z
SPI_SS
SPI Slave Select
CODEC3, SPI
hi - z
SPI_SS
SPI Slave Select
Pin PSC3_8
Ball A05
MPC5200B User’s Manual, Rev. 3
2-50
Freescale Semiconductor
Signal Descriptions
Table 2-15. PSC3 Functions by Pin (Sheet 7 of 7)
Pin / Ball Number
Pin PSC3_9
Function
Reset
Value
Description
Ball C04
GPIO
hi - z
GPIO_W/WAKE_UP
Simple General Purpose I/O with WAKE UP
USB2
hi - z
USB2_OVRCRNT
USB Over Current
UART3
hi - z
GPIO_W/WAKE_UP
Simple General Purpose I/O with WAKE UP
UART3e
hi - z
GPIO_W/WAKE_UP
Simple General Purpose I/O with WAKE UP
CODEC3
hi - z
GPIO_W/WAKE_UP
Simple General Purpose I/O with WAKE UP
CODEC3_w/MCLK
hi - z
GPIO_W/WAKE_UP
Simple General Purpose I/O with WAKE UP
SPI
hi - z
SPI_CLK
SPI Clock
UART3, SPI
hi - z
SPI_CLK
SPI Clock
UART3e, SPI
hi - z
SPI_CLK
SPI Clock
CODEC3, SPI
hi - z
SPI_CLK
SPI Clock
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-51
Signal Descriptions
USB Clock
from PSC6 Port
USB Host
10
PSC4
PSC5
4
4
RST_CFG
GPIO
5
2
Pin Drivers and MUX Logic
USB_0
Function
Port_conf
[18:19]
RST_CFG
—
GPIO
00
GPIO
USB
01
USB1_
OE
2x UART4/5
10
GPIO
USB_0
USB_1
USB_2
USB_1
USB_2
RST_
CFG6
RST_
CFG7
USB1_
TXN
USB1_
TXP
UART4_ UART4_
RTS
TXD
USB_3
USB_3
USB_4
USB_4
USB_5
USB_5
USB_6
USB_7
USB_8
USB_9
USB_6
USB_7
USB_8
USB_9
GPIO
GPIO
GPIO
GPIO_
INTERRUPT
USB1_S
USPEND
USB1_
OVERCNT
USB1_
RXD
USB1_
RXP
USB1_
USB1_
RXN PORTPWR
USB1_
SPEED
UART4_
RXD
UART4_
CTS
UART5_
RXD
UART5_
RTS
UART5_
TXD
UART5_ INTERRUPT
CTS
Notes:
1. If not used for USB, this port is available as a GPIO resource.
2. USB clock source can be generated internally or sourced from USB_CLK input.
3. Pins 3–5 are not mapped to any function other than USB.
4. RST_config bits are sampled only during Reset.
5. PSC4/5 can be used here or on the Ethernet port, but not in both places.
Figure 2-7. USB Port Map—10 Pins
Table 2-16. USB Pin Functions
Pin Name
Dir.
USB_0
I/O
USB_1
I/O
USB_2
I/O
USB_3
Reset Configuration
GPIO
USB
2x UART4/5
GPIO
USB1_OE
GPIO
RST_CFG6
USB1_TXN
UART4_RTS
RST_CFG7
USB1_TXP
UART4_TXD
I
USB1_RXD
UART4_RXD
USB_4
I
USB1_RXP
UART4_CTS
USB_5
I
USB1_RXN
UART5_RXD
USB_6
I/O
GPIO
USB1_PORTPWR
UART5_TXD
USB_7
I/O
GPIO
USB1_SPEED
UART5_RTS
USB_8
I/O
GPIO
USB1_SUSPEND
UART5_CTS
USB_9
I/O
INTERRUPT
USB1_OVERCNT
GPIO_INTERRUPT
MPC5200B User’s Manual, Rev. 3
2-52
Freescale Semiconductor
Signal Descriptions
Table 2-17. USB Pin Functions by Pin
Pin / Ball Number
Pin USB_0
Function
Reset
Value
Description
Ball H01
GPIO
hi - z
GPIO
USB1
hi - z
USB1_OE
RESET Config.
hi - z
—
UART4, UART5
hi - z
GPIO
GPIO
hi - z
—
USB1
hi - z
USB1_TXN
USB1 Transmit Negative
RESET Config.
hi - z
RST_CFG6 - sys_pll_cfg_0
bit =0 : fsystem = 16x SYS_XTAL_IN
bit =1 : fsystem = 12x SYS_XTAL_IN
UART4, UART5
hi - z
UART4_RTS
GPIO
hi - z
—
USB1
hi - z
USB1_TXP
USB1 Transmit Positive
RESET Config.
hi - z
RST_CFG7
(Pull bit low)
UART4, UART5
hi - z
UART4_TXD
Uart Transmit Data
GPIO
hi - z
—
USB1
hi - z
USB1_RXD
USB1 Receive Data
RESET Config.
hi - z
—
UART4, UART5
hi - z
UART4_RXD
Uart Receive Data
GPIO
hi - z
—
USB1
hi - z
USB1_RXP
USB1 Receive Positive
RESET Config.
hi - z
—
UART_, UART5
hi - z
UART4_CTS
Uart Clear To Send
Pin USB_1
Pin USB_2
Pin USB_3
Pin USB_4
Ball H02
Ball H03
Ball G01
Ball G02
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-53
Signal Descriptions
Table 2-17. USB Pin Functions by Pin (continued)
Pin / Ball Number
Pin USB_5
Function
Reset
Value
Description
Ball G03
GPIO
hi - z
—
USB1
hi - z
USB1_RXN
USB1 Receive Negative
RESET Config.
hi - z
—
UART4, UART5
hi - z
UART5_RXD
Uart Receive Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB1
hi - z
USB1_PRTPWR
USB Receive Negative
RESET Config.
hi - z
—
UART4, UART5
hi - z
UART5_TXD
Uart Transmit Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB1
hi - z
USB1_SPEED
USB Speed
RESET Config.
hi - z
—
UART4, UART5
hi - z
UART5_RTS
Uart Ready To Send
GPIO
hi - z
GPIO
Simple General Purpose I/O
USB1
hi - z
USB1_SUSPEND
USB Suspend
RESET Config.
hi - z
—
UART4, UART5
hi - z
UART5_CTS
Uart Clear To Send
Pin USB_6
Pin USB_7
Pin USB_8
Ball G04
Ball F01
Ball F02
MPC5200B User’s Manual, Rev. 3
2-54
Freescale Semiconductor
Signal Descriptions
Table 2-17. USB Pin Functions by Pin (continued)
Pin / Ball Number
Pin USB_9
Reset
Value
Function
Description
Ball F03
GPIO
hi - z
GPIO/INTERRUPT
Simple General Purpose I/O/INTERRUPT
USB1
hi - z
USB1_OVRCRNT
USB1 Over Current
RESET Config.
hi - z
—
UART4, UART5
hi - z
INTERRUPT
J1850
PSC4
PSC5
Ethernet
(Outputs)
RST_CFG
2
5
5
8
8
USB2
(output portion)
6
GPIO
8
Pin Drivers and MUX Logic
ETH_0
Function
Port_conf
[12:15]
ETH_0
ETH_1
ETH_1
ETH_2
ETH_2
ETH_3
ETH_3
ETH_4
ETH_4
ETH_5
ETH_5
ETH_6
ETH_6
ETH_7
ETH_7
RST_CFG
—
RST_CFG8
RST_CFG15
RST_CFG10
RST_CFG11
RST_CFG12
RST_CFG13
RST_CFG14
—
GPIO
0000
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
USB2
0001
OUTPUT
OUTPUT
USB2_TXP
USB2_
PRTPWR
USB2_SPEED USB2_
SUSPEND
USB2_OE
USB2_TXN
ETH7
0010
ETH7_TXEN
ETH7_TXD_0 OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
ETH7 / USB2
0011
ETH7_TXEN
ETH7_TXD_0 USB2_TXP
USB2_
PRTPWR
USB2_SPEED USB2_
SUSPEND
USB2_OE
USB2_TXN
OUTPUT
OUTPUT
OUTPUT
ETH_18 no MD 0100
ETH18_TXEN ETH18_TXD_0 ETH18_TXD_1 ETH18_TXD_2 ETH18_TXD_3 ETH18_
TXERR
ETH_18 w/ MD 0101
ETH18_w/MD_ ETH18_w/
TXEN
MD_TXD_0
ETH7 /
1000
UART4e/J1850
ETH7_TXEN
ETH7_TXD_0 OUTPUT
UART4e_TXD J1850_TX
ETH7 /J1850
1001
ETH7_TXEN
ETH7_TXD_0 OUTPUT
OUTPUT
UART4/
5e/J1850
1010
OUTPUT
UART5e_TXD UART5e_RTS UART4_TXD
UART5e/J1850 1011
OUTPUT
UART5e__
TXD
J1850
OUTPUT
OUTPUT
1100
ETH18_w/
MD_TXD_1
ETH18_w/
MD_TXD_2
ETH18_w/MD_ ETH18_w/MD_ ETH18_w/MD_ ETH18_w/MD_
TXD_3
TXERR
MDC
MDIO
UART4e_RTS OUTPUT
OUTPUT
J1850_TX
OUTPUT
OUTPUT
OUTPUT
J1850_TX
UART4_RTS
OUTPUT
OUTPUT
UART5e_RTS OUTPUT
J1850_TX
OUTPUT
OUTPUT
OUTPUT
OUTPUT
J1850_TX
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Figure 2-8. Ethernet Output Port Map—8 Pins
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-55
Signal Descriptions
J1850
PSC4
PSC5
2
5
5
USB2
(I/O portion)
Ethernet
(Inputs)
10
GPIO
4
9
Pin Drivers and MUX Logic
ETH_8
ETH_9
ETH_10
ETH_11
ETH_12 ETH_13
ETH_14
ETH_15
ETH_16
ETH_17
Port_
conf
[12:15]
ETH_8
ETH_9
ETH_10
ETH_11
GPIO
0000
GPIO
GPIO
GPIO
USB2
0001
GPIO
GPIO
GPIO
ETH7
0010
ETH7_CD
ETH7_RXCLK ETH7_COL
ETH7_
TXCLK
ETH7/USB2
0011
ETH7_CD
ETH7_RXCLK ETH7_COL
ETH7_
TXCLK
ETH_18 no
MD
0100
ETH18_RXDV
ETH_18 w/
MD
0101
ETH18_w/MD_ ETH18_w/MD_ ETH18_w/M ETH18_TXD ETH18_w/ ETH18_w/M ETH18_w/MD ETH18_w/M ETH18_w/M ETH18_W/MD
RXDV
RXCLK
D_COL
MD_RXD_0 D_RXD_1
_RXD_2
D_RXD_3
D_RXERR
_CRS
ETH7 /
UART4e/
J1850
1000
ETH7_CD
ETH7_RXCLK ETH7_COL
ETH7_
TXCLK
ETH7_RXD
_0
J1850_RX
UART4e_RXD
ETH7/J1850
1001
ETH7_CD
ETH7_RXCLK ETH7_COL
ETH7_
TXCLK
ETH7_RXD
_0
J1850_RX
GPIO/
INTERRUPT
UART4/5e/
J1850
1010
UART5e_CD
UART5e/
J1850
1011
J1850
1100
Function
ETH_12
ETH_13
ETH_14
ETH_15
ETH_16
ETH_17
GPIO
GPIO/
INTERRUPT
GPIO/
INTERRUPT
GPIO/
GPIO/
GPIO_W/WAK
INTERRUPT INTERRUPT
E_UP
GPIO
USB2_RXD
USB2_RXP
USB2_RXN
GPIO/
INTERRUPT
GPIO/
INTERRUPT
GPIO/
GPIO/
INTERRUPT INTERRUPT
GPIO_W/
WAKE_UP
ETH7_RXD USB2_RXD
_0
USB2_RXP
USB2_RXN
GPIO_W/
WAKE_UP
RST_CFG
ETH18_
RXCLK
ETH18_COL
ETH18_
TXCLK
ETH7_
RXD_0
ETH18_
RXD_0
ETH18_
RXD_1
USB2_
OVRCNT
USB2_
OVRCNT
GPIO_W/
WAKE_UP
ETH18_RXD_ ETH18_RXD ETH18_RXE ETH18_CRS
2
_3
RR
UART4e_
CTS
UART4_DCD
GPIO_W/
WAKE_UP
GPIO/
GPIO/
INTERRUPT INTERRUPT
GPIO_W/
WAKE_UP
UART5e_CTS
OUTPUT
OUTPUT
UART5e_
RXD
J1850_RX
UART4_RXD UART4_CTS UART4_CD
GPIO_W/
WAKE_UP
UART5e_DCD UART5e_CTS
OUTPUT
OUTPUT
UART5e_
RXD
J1850_RX
GPIO/
INTERRUPT
GPIO/
GPIO/
INTERRUPT INTERRUPT
GPIO_W/
WAKE_UP
OUTPUT
OUTPUT
J1850_RX
GPIO/
INTERRUPT
GPIO/
GPIO/
INTERRUPT INTERRUPT
GPIO_W/
WAKE_UP
GPIO
OUTPUT
Figure 2-9. Ethernet Input / Control Port Map—10 Pins
MPC5200B User’s Manual, Rev. 3
2-56
Freescale Semiconductor
Signal Descriptions
Table 2-18. Ethernet Pin Functions
Pin Name
Dir.
Reset
Configuration
GPIO
USB2
ETH7
ETH7 / USB2
ETH_0
I/O
RST_CFG8
OUTPUT
OUTPUT
ETH7_TXEN
ETH7_TXEN
ETH_1
I/O
RST_CFG15
OUTPUT
OUTPUT
ETH7_TXD_0
ETH7_TXD_0
ETH_2
I/O
RST_CFG10
OUTPUT
USB2_TXP
OUTPUT
USB2_TXP
ETH_3
I/O
RST_CFG11
OUTPUT
USB2_PRTPWR
OUTPUT
USB2_PRTPWR
ETH_4
I/O
RST_CFG12
OUTPUT
USB2_SPEED
OUTPUT
USB2_SPEED
ETH_5
I/O
RST_CFG13
OUTPUT
USB2_SUSPEND
OUTPUT
USB2_SUSPEND
ETH_6
I/O
RST_CFG14
OUTPUT
USB2_OE
OUTPUT
USB2_OE
ETH_7
I/O
—
OUTPUT
USB2_TXN
OUTPUT
USB2_TXN
ETH_8
I/O
—
GPIO
GPIO
ETH7__CD
ETH7__CD
ETH_9
I/O
—
GPIO
GPIO
ETH7_RXCLK
ETH7_RXCLK
ETH_10
I/O
—
GPIO
GPIO
ETH7_COL
ETH7_COL
ETH_11
I/O
—
GPIO
GPIO
ETH7_TXCLK
ETH7_TXCLK
ETH_12
I
—
—
—
ETH7_RXD_0
ETH7_RXD_0
ETH_13
I/O
—
GPIO/INTERRUPT
USB2_RXD
GPIO/INTERRUPT
USB2_RXD
ETH_14
I/O
—
GPIO/INTERRUPT
USB2_RXP
GPIO/INTERRUPT
USB2_RXP
ETH_15
I/O
—
GPIO/INTERRUPT
USB2_RXN
GPIO/INTERRUPT
USB2_RXN
ETH_16
I/O
—
GPIO/INTERRUPT
USB2_OVRCNT
GPIO/INTERRUPT
USB2_OVRCNT
ETH_17
I/O
—
GPIO_W/WAKE-UP
GPIO_W/WAKE-UP
GPIO_W/WAKE-UP
GPIO_W/
WAKE-UP
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-57
Signal Descriptions
Table 2-19. Ethernet Pin Functions
Pin name Dir.
ETH_18
no MD
ETH_18
w/ MD
ETH7 /
UART4e/
J1850
ETH7/J1850
2UART4/5e/J
1850
UART5e/J
1850
J1850
ETH_0
I/O
ETH18_TXEN ETH18_w/|MD
_TXEN
ETH7_TXEN
ETH7_TXEN
OUTPUT
OUTPUT
OUTPUT
ETH_1
I/O
ETH18_TXD_0
ETH18_w/
MD_TXD_0
ETH7_TXD_0
ETH7_TXD_0
UART5e__TXD
UART5e__TXD
OUTPUT
ETH_2
I/O
ETH18_TXD_1
ETH18_w/
MD_TXD_1
OUTPUT
OUTPUT
UART5e__RTS
UART5e__RTS
OUTPUT
ETH_3
I/O
ETH18_TXD_2
ETH18_w/
MD_TXD_2
UART4e_TXD
OUTPUT
P4_TXD
OUTPUT
OUTPUT
ETH_4
I/O
ETH18_TXD_3
ETH18_w/
MD_TXD_3
J1850_TX
J1850_TX
J1850_TX
J1850_TX
J1850_TX
ETH_5
I/O
ETH18_
TXERR
ETH18_w/
MD_TXERR
UART4e__
RTS
OUTPUT
UART4_RTS
OUTPUT
OUTPUT
ETH_6
I/O
OUTPUT
ETH18_w/
MD_MDC
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
ETH_7
I/O
OUTPUT
ETH18_w/
MD_MDIO
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
ETH_8
I/O
ETH18_RXDV
ETH18_w/
MD_RXDV
ETH7__CD
ETH7__CD
UART5e__DCD
UART5e__DCD
GPIO
ETH_9
I/O
ETH18_
RXCLK
ETH18_w/
MD_RXCLK
ETH7_RXCLK
ETH7_RXCLK
UART5e__CTS
UART5e__CTS
GPIO
ETH_10
I/O
ETH18_COL
ETH18_w/
MD_COL
ETH7_COL
ETH7_COL
GPIO
GPIO
GPIO
ETH_11
I/O
ETH18_
TXCLK
ETH18_w/
MD_TXCLK
ETH7_TXCLK
ETH7_TXCLK
GPIO
GPIO
GPIO
ETH_12
I
ETH18_
RXD_0
ETH18_w/
MD_RXD_0
ETH7_RXD_O
ETH7_RXD_O
UART5e__RXD
UART5e__RXD
—
ETH_13
I/O
ETH18_
RXD_1
ETH18_w/
MD_RXD_1
J1850_RX
J1850_RX
J1850_RX
J1850_RX
J1850_RX
ETH_14
I/O
ETH18_
RXD_2
ETH18_w/
MD_RXD_2
UART4e__
RXD
GPIO/
INTERRUPT
UART4_RXD
GPIO/
INTERRUPT
GPIO/
INTERRUPT
ETH_15
I/O
ETH18_
RXD_3
ETH18_w/
MD_RXD_3
UART4e__
CTS
GPIO/
INTERRUPT
UART4_CTS
GPIO/
INTERRUPT
GPIO/
INTERRUPT
ETH_16
I/O
ETH18_
RXERR
ETH18_w/
MD_RXERR
UART4e__
DCD
GPIO/
INTERRUPT
UART4_CD
GPIO/
INTERRUPT
GPIO/
INTERRUPT
ETH_17
I/O
ETH18_CRS
ETH18_w/
MD_CRS
GPIO_W/
WAKE-UP
GPIO_W/
WAKE-UP
GPIO_W/
WAKE-UP
GPIO_W/
WAKE-UP
GPIO_W/
WAKE-UP
MPC5200B User’s Manual, Rev. 3
2-58
Freescale Semiconductor
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 1 of 8)
Pin / Ball Number
Pin ETH_0
Reset
Value
Description
Ball K01
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_TX_EN
Ethernet Transmit Enable
ETH7 Wire / USB2
hi - z
ETH_TX_EN
Ethernet Transmit Enable
ETH18 Wire w/o MD
hi - z
ETH_TX_EN
Ethernet Transmit Enable
ETH18 Wire w/ MD
hi - z
ETH_TX_EN
Ethernet Transmit Enable
ETH7 Wire, UART4e, J1850
hi - z
ETH_TX_EN
Ethernet Transmit Enable
ETH7 Wire, J1850
hi - z
ETH_TX_EN
Ethernet Transmit Enable
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config. 8
hi - z
bit 8 - most_graphics_sel
bit = 0: Most Graphics boot not enabled
bit = 1: Most Graphics boot enabled.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-59
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 2 of 8)
Pin / Ball Number
Pin ETH_1
Reset
Value
Description
Ball K02
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
ETH7 Wire / USB2
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
ETH18 Wire w/o MD
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
ETH18 Wire w/ MD
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
EHT7 Wire, UART4e, J1850
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
ETH7 Wire, J1850
hi - z
ETH_TXD_0
Ethernet Transmit Data Output
UART_4, UART5e, J1850
hi - z
UART5e_TXD
Uart Transmit Data
UART5e, J1850
hi - z
UART5e_TXD
Uart Transmit Data
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config.
hi - z
bit 15 - large_flash_sel
bit = 0: Large Flash boot not enabled
bit = 1: Large Flash boot enabled.
See Note 3.
MPC5200B User’s Manual, Rev. 3
2-60
Freescale Semiconductor
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 3 of 8)
Pin / Ball Number
Pin ETH_2
Reset
Value
Description
Ball K03
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_TXP
USB Transmit Positive
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2_TXP
USB Transmit Positive
ETH18 Wire w/o MD
hi - z
ETH_TXD_1
Ethernet Transmit Data Output
ETH18 Wire w/ MD
hi - z
ETH_TXD_1
Ethernet Transmit Data Output
EHT7 Wire, UART4e, J1850
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output
UART_4, UART5e, J1850
hi - z
UART5e_RTS
Uart Transmit Data
UART5e, J1850
hi - z
UART5e_RTS
Uart Transmit Data
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config.
hi - z
bit 10 - ppc_msrip PPC Boot Address / Exception Table
Loc.
bit = 0: 0000 0100 (hex)
bit = 1: fff0 0100 (hex)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-61
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 4 of 8)
Pin / Ball Number
Pin ETH_3
Reset
Value
Description
Ball J01
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_PrtPWR
USB Port Power
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2_PrtPWR
USB Port Power
ETH18 Wire w/o MD
hi - z
ETH_TXD_2
Ethernet Transmit Data Output
ETH18 Wire w/ MD
hi - z
ETH_TXD_2
Ethernet Transmit Data Output
EHT7 Wire, UART4e, J1850
hi - z
UART_4_TXD
Uart Transmit Data
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output
UART_4, UART5e, J1850
hi - z
UART_4_TXD
Uart Transmit Data
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config.
hi - z
bit 11 - boot_rom_wait
bit = 0: 4 IPbus clocks of waitstate*
bit = 1: 48 IPbus clocks of waitstate*
MPC5200B User’s Manual, Rev. 3
2-62
Freescale Semiconductor
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 5 of 8)
Pin / Ball Number
Pin ETH_4
Reset
Value
Description
Ball J02
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_Speed
USB Speed
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2_Speed
USB Speed
ETH18 Wire w/o MD
hi - z
ETH_TXD_3
Ethernet Transmit Data Output
ETH18 Wire w/ MD
hi - z
ETH_TXD_3
Ethernet Transmit Data Output
EHT7 Wire, UART4e, J1850
hi - z
J1850_TX
J1850 Transmit Data
ETH7 Wire, J1850
hi - z
J1850_TX
J1850 Transmit Data
UART_4, UART5e, J1850
hi - z
J1850_TX
J1850 Transmit Data
UART5e, J1850
hi - z
J1850_TX
J1850 Transmit Data
J1850
hi - z
J1850_TX
J1850 Transmit Data
RESET Config.
hi - z
bit 12 - boot_rom_swap
bit = 0: no byte lane swap - same endian ROM image
bit = 1: byte lane swap - different endian ROM image
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-63
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 6 of 8)
Pin / Ball Number
Pin ETH_5
Reset
Value
Description
Ball L03
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_Suspend
USB Suspend
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2_Suspend
USB Suspend
ETH18 Wire w/o MD
hi - z
ETH_TXERR
Ethernet Transmit Error Output
ETH18 Wire w/ MD
hi - z
ETH_TXERR
Ethernet Transmit Error Output
EHT7 Wire, UART4e, J1850
hi - z
UART_4_RTS
Uart Ready To Send
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output
UART_4, UART5e, J1850
hi - z
UART_4_RTS
Uart Ready To Send
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config.
hi - z
bit 13 - boot_rom_size For “non-muxed” boot ROMs
bit = 0: 8-bit boot ROM data bus / 24-bit boot ROM
address
bit = 1: 16-bit boot ROM data bus / 16-bit boot ROM
address
For muxed boot ROMs boot ROM addr is max 25
significant bits during address tenure.
bit = 0: 16-bit ROM data bus
bit = 1: 32-bit ROM data bus
For large flash boot case boot Flash addr is 25 bits.
bit = 0: 8-bit Flash data bus
bit = 1: 16-bit Flash data bus
MPC5200B User’s Manual, Rev. 3
2-64
Freescale Semiconductor
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 7 of 8)
Pin / Ball Number
Pin ETH_6
Reset
Value
Description
Ball N02
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_OE
USB Output Enable
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2__OE
USB Output Enable
ETH18 Wire w/o MD
hi - z
GPIO
Simple General Purpose Output
ETH18 Wire w/ MD
hi - z
ETH_MDC
Ethernet Transmit Error Output
EHT7 Wire, UART4e, J1850
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
RESET Config.
hi - z
bit 14 - boot_rom_wait
bit = 0: non-muxed boot ROM bus, single tenure
transfer.
bit = 1: muxed boot ROM bus, PPC like with address &
data tenures,
Alibi & TS_b active.
Note 3.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-65
Signal Descriptions
Table 2-20. Ethernet Output Functions by Pin (Sheet 8 of 8)
Pin / Ball Number
Pin ETH_7
Reset
Value
Description
Ball N01
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
USB2_TXN
USB Transmit Negative
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire / USB2
hi - z
USB2_TXN
USB Transmit Negative
ETH18 Wire w/o MD
hi - z
GPIO
Simple General Purpose Output
ETH18 Wire w/ MD
hi - z
ETH_MDIO
Ethernet Management Data I/O
EHT7 Wire, UART4e, J1850
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
Notes:
1. The external bus clock (pci_clk) will be 1/2 the frequency of the internal bus clock (ipb_clk) at powerup. Therefore, 4 IPbus
wait states will translate to as little as 1 external wait state (i.e. peripheral must respond within 2 external clocks). The “slow”
setting represents 48 IPbus clocks of wait, or 23 external clocks of wait External waits are minus-1 because Chip Select
may assert on falling edge of external bus clock (dependant on internal timing).
2. For muxed boot ROM types, the width of ALE_b & TS_b will be 2 IPbus clocks (i.e. 1 external clock). This represents the
wide ALE setting in the LocalPlus Controller (LPC). Care must be taken if these clock relationships are to be changed
during the boot process. For the 1-to-1 internal-to-external clock setting (which must be programmed by software into the
CDM), be sure to change the ALE width setting (in LPC) *after* adjusting the clock relationship. Any fetches to the boot
device between these two settings will result in ALE and TS being 2 external clocks wide.
3. Only one boot mode can be enabled at a time. Large Flash and Most Graphics cannot be enabled at the same time. If
neither Large Flash or Most Graphics is enabled, boot will occur from the normal LocalPlus mode, either muxed or
nonmuxed (depending on the boot_rom_type configuration input).
MPC5200B User’s Manual, Rev. 3
2-66
Freescale Semiconductor
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 1 of 7)
PIN / BALL NUMBER
Pin ETH_8
Reset
Value
Description
Ball M03
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_CD
Ethernet Carrier Detect
ETH7 Wire / USB2
hi - z
ETH_CD
Ethernet Carrier Detect
ETH18 Wire w/o MD
hi - z
ETH_RXDV
Ethernet Receive Data Valid
ETH18 Wire w/ MD
hi - z
ETH_RXDV
Ethernet Receive Data Valid
EHT7 Wire, UART4e, J1850
hi - z
ETH_CD
Ethernet Carrier Detect
ETH7 Wire, J1850
hi - z
ETH_CD
Ethernet Carrier Detect
UART_4, UART5e, J1850
hi - z
UART5e_DCD
Uart Carrier Detect
UART5e, J1850
hi - z
UART5e_DCD
Uart Carrier Detect
J1850
hi - z
GPIO
Simple General Purpose Output
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-67
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 2 of 7)
PIN / BALL NUMBER
Pin ETH_9
Reset
Value
Description
Ball L01
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_RXCLK
Ethernet Receive Clock
ETH7 Wire / USB2
hi - z
ETH_RXCLK
Ethernet Receive Clock
ETH18 Wire w/o MD
hi - z
ETH_RXCLK
Ethernet Receive Clock
ETH18 Wire w/ MD
hi - z
ETH_RXCLK
Ethernet Receive Clock
EHT7 Wire, UART4e, J1850
hi - z
ETH_RXCLK
Ethernet Receive Clock
ETH7 Wire, J1850
hi - z
ETH_RXCLK
Ethernet Receive Clock
UART_4, UART5e, J1850
hi - z
ETH_RXCLK
Ethernet Receive Clock
UART5e, J1850
hi - z
UART5e_CTS
Uart Clear To Send
J1850
hi - z
UART5e_CTS
Uart Clear To Send
MPC5200B User’s Manual, Rev. 3
2-68
Freescale Semiconductor
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 3 of 7)
PIN / BALL NUMBER
Pin ETH_10
Reset
Value
Description
Ball J03
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_COL
Ethernet Collision Detect Input
ETH7 Wire / USB2
hi - z
ETH_COL
Ethernet Collision Detect Input
ETH18 Wire w/o MD
hi - z
ETH_COL
Ethernet Collision Detect Input
ETH18 Wire w/ MD
hi - z
ETH_COL
Ethernet Collision Detect Input
EHT7 Wire, UART4e, J1850
hi - z
ETH_COL
Ethernet Collision Detect Input
ETH7 Wire, J1850
hi - z
ETH_COL
Ethernet Collision Detect Input
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-69
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 4 of 7)
PIN / BALL NUMBER
Pin ETH_11
Reset
Value
Description
Ball L04
GPIO
hi - z
GPIO
Simple General Purpose Output
USB2
hi - z
GPIO
Simple General Purpose Output
ETH7 Wire
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
ETH7 Wire / USB2
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
ETH18 Wire w/o MD
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
ETH18 Wire w/ MD
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
EHT7 Wire, UART4e, J1850
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
ETH7 Wire, J1850
hi - z
ETH_TXCLK
Ethernet Transmit Clock Input
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output
J1850
hi - z
GPIO
Simple General Purpose Output
MPC5200B User’s Manual, Rev. 3
2-70
Freescale Semiconductor
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 5 of 7)
PIN / BALL NUMBER
Pin ETH_12
Reset
Value
Description
Ball M02
GPIO
hi - z
USB2
hi - z
ETH7 Wire
hi - z
ETH_RXD0
Ethernet Receive Data Input
ETH7 Wire / USB2
hi - z
ETH_RXD0
Ethernet Receive Data Input
ETH18 Wire w/o MD
hi - z
ETH_RXD0
Ethernet Receive Data Input
ETH18 Wire w/ MD
hi - z
ETH_RXD0
Ethernet Receive Data Input
EHT7 Wire, UART4e, J1850
hi - z
ETH_RXD0
Ethernet Receive Data Input
ETH7 Wire, J1850
hi - z
ETH_RXD0
Ethernet Receive Data Input
UART_4, UART5e, J1850
hi - z
UART5e_RXD
Uart Receive Data
UART5e, J1850
hi - z
UART5e_RXD
Uart Receive Data
J1850
hi - z
—
GPIO
hi - z
GPIO/INTERRUPT
USB2
hi - z
USB_2_RECEIVE DIFFERENTIAL
ETH7 Wire
hi - z
GPIO/INTERRUPT
ETH7 Wire / USB2
hi - z
USB_2_RECEIVE DIFFERENTIAL
ETH18 Wire w/o MD
hi - z
ETH_RXD1
Ethernet Receive Data Input
ETH18 Wire w/ MD
hi - z
ETH_RXD1
Ethernet Receive Data Input
EHT7 Wire, UART4e, J1850
hi - z
J1850_RX
J1850 Receive Data
ETH7 Wire, J1850
hi - z
J1850_RX
J1850 Receive Data
UART_4, UART5e, J1850
hi - z
J1850_RX
J1850 Receive Data
UART5e, J1850
hi - z
J1850_RX
J1850 Receive Data
J1850
hi - z
J1850_RX
J1850 Receive Data
Pin ETH_13
Ball M01
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-71
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 6 of 7)
PIN / BALL NUMBER
Pin ETH_14
Reset
Value
Description
Ball N04
GPIO
hi - z
GPIO/INTERRUPT
USB2
hi - z
USB_2_RXP
USB Receive Positive
ETH7 Wire
hi - z
GPIO/INTERRUPT
ETH7 Wire / USB2
hi - z
USB_2_RXP
USB Receive Positive
ETH18 Wire w/o MD
hi - z
ETH_RXD2
Ethernet Receive Data Input
ETH18 Wire w/ MD
hi - z
ETH_RXD2
Ethernet Receive Data Input
EHT7 Wire, UART4e, J1850
hi - z
UART4e_RXD
Uart Receive Data
ETH7 Wire, J1850
hi - z
GPIO/INTERRUPT
UART_4, UART5e, J1850
hi - z
UART4e_RXD
Uart Receive Data
UART5e, J1850
hi - z
GPIO/INTERRUPT
J1850
hi - z
GPIO/INTERRUPT
GPIO
hi - z
GPIO/INTERRUPT
USB2
hi - z
USB_2_RXN
USB Receive Negative
ETH7 Wire
hi - z
GPIO/INTERRUPT
ETH7 Wire / USB2
hi - z
USB_2_RXN
USB Receive Negative
ETH18 Wire w/o MD
hi - z
ETH_RXD3
Ethernet Receive Data Input
ETH18 Wire w/ MD
hi - z
ETH_RXD3
Ethernet Receive Data Input
EHT7 Wire, UART4e, J1850
hi - z
UART4e_CTS
Uart Clear To Send
ETH7 Wire, J1850
hi - z
GPIO/INTERRUPT
UART_4, UART5e, J1850
hi - z
UART4e_CTS
Uart Clear To Send
UART5e, J1850
hi - z
GPIO/INTERRUPT
J1850
hi - z
GPIO/INTERRUPT
Pin ETH_15
Ball N03
MPC5200B User’s Manual, Rev. 3
2-72
Freescale Semiconductor
Signal Descriptions
Table 2-21. Ethernet Input / Control Functions by Pin (Sheet 7 of 7)
PIN / BALL NUMBER
Pin ETH_16
Reset
Value
Description
Ball L02
GPIO
hi - z
GPIO/INTERRUPT
USB2
hi - z
USB_2_OVRCNT
USB Over Current
ETH7 Wire
hi - z
GPIO/INTERRUPT
ETH7 Wire / USB2
hi - z
USB_2_OVRCNT
USB Over Current
ETH18 Wire w/o MD
hi - z
ETH_RXERR
Ethernet Receive Error Input
ETH18 Wire w/ MD
hi - z
ETH_RXERR
Ethernet Receive Error Input
EHT7 Wire, UART4e, J1850
hi - z
UART4e_DCD
Uart Carrier Detect
ETH7 Wire, J1850
hi - z
GPIO/INTERRUPT
UART_4, UART5e, J1850
hi - z
GPIO/INTERRUPT
UART5e, J1850
hi - z
GPIO/INTERRUPT
J1850
hi - z
GPIO/INTERRUPT
GPIO
hi - z
GPIO
Simple General Purpose Output with WAKE UP
USB2
hi - z
GPIO
Simple General Purpose Output with WAKE UP
ETH7 Wire
hi - z
GPIO
Simple General Purpose Output with WAKE UP
ETH7 Wire / USB2
hi - z
GPIO
Simple General Purpose Output with WAKE UP
ETH18 Wire w/o MD
hi - z
ETH_CRS
Ethernet Carrier Sense Input
ETH18 Wire w/ MD
hi - z
ETH_CRS
Ethernet Carrier Sense Input
EHT7 Wire, UART4e, J1850
hi - z
GPIO
Simple General Purpose Output with WAKE UP
ETH7 Wire, J1850
hi - z
GPIO
Simple General Purpose Output with WAKE UP
UART_4, UART5e, J1850
hi - z
GPIO
Simple General Purpose Output with WAKE UP
UART5e, J1850
hi - z
GPIO
Simple General Purpose Output with WAKE UP
J1850
hi - z
GPIO
Simple General Purpose Output with WAKE UP
Pin ETH_17
Ball J04
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-73
Signal Descriptions
Timer0
(IC/OC/PWM)
Timer1
(IC/OC/PWM)
1
Timer7
(IC/OC/PWM)
1
ATA Chip
Selects
1
2
CAN2
2
SPI
GPIO
8
4
Pin Drivers and MUX Logic
TMR_0
Function
Port_config
[2:3_6:7]
TIMER0
TMR_1
TIMER1
TMR_2
TIMER2
TMR_3
TIMER3
TMR_4
TIMER4
TMR_5
TIMER5
TMR_6
TIMER6
TMR_7
TIMER7
GPIO
TIMER
00_0X
00_10
GPIO
TIMER_0
GPIO
TIMER_1
GPIO
TIMER_2
GPIO
TIMER_3
GPIO
TIMER_4
GPIO
TIMER_5
GPIO
TIMER_6
GPIO
TIMER_7
ATA_CS
00_11
ATA_CS_0
ATA_CS_1
GPIO
TIMER_2
GPIO
TIMER_3
GPIO
TIMER_4
GPIO
TIMER_5
GPIO
TIMER_6
GPIO
TIMER_7
CAN2
01_00
CAN2_TX
CAN2_RX
GPIO
TIMER_2
GPIO
TIMER_3
GPIO
TIMER_4
GPIO
TIMER_5
GPIO
TIMER_6
GPIO
TIMER_7
SPI
10_00
GPIO
TIMER_0
GPIO
TIMER_1
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
GPIO
TIMER_6
GPIO
TIMER_7
SPI/ATA_CS 10_11
ATA_CS_0
ATA_CS_1
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
GPIO
TIMER_6
GPIO
TIMER_7
CAN2/SPI
CAN2_TX
CAN2_RX
SPI_MOSI
SPI_MISO
SPI_SS
SPI_CLK
GPIO
TIMER_6
GPIO
TIMER_7
11_00
Notes:
1. Each pin is individually selectable as a Timer or GPIO. Each Timer can be individually
configured as Input Capture (IC), Output Compare (OC), or Pulse Width Modulator (PWM)
(GPT X Enable and Mode Select Register).
If a timer pin is configured as a GPIO or some other function (SPI, chip select or CAN), the
timer module can still be used internally by software.
2. Timers 6 and 7, when configured as input capture, contain WakeUp functionality.
3. All Timer and GPIO function controls are within the Timer module register set.
4. CAN RX input supports WakeUp functionality.
Figure 2-10. Timer Port Map—8 Pins
MPC5200B User’s Manual, Rev. 3
2-74
Freescale Semiconductor
Signal Descriptions
Table 2-22. Timer Pin Functions
Pin Name
Dir.
GPIO
TIMER
ATA CHIP SEL
CAN2
SPI
CAN2 / SPI
TIMER 0
I/O
SIMPLE GPIO
TIMER 0
ATA_CS_0
CAN2_TX
SIMPLE GPIO
CAN2_TX
TIMER 1
I/O
SIMPLE GPIO
TIMER 1
ATA_CS_1
CAN2_RX
SIMPLE GPIO
CAN2_RX
TIMER 2
I/O
SIMPLE GPIO
TIMER 2
SIMPLE GPIO
SIMPLE GPIO
SPI_MOSI
SPI_MOSI
TIMER 3
I/O
SIMPLE GPIO
TIMER 3
SIMPLE GPIO
SIMPLE GPIO
SPI_MISO
SPI_MISO
TIMER 4
I/O
SIMPLE GPIO
TIMER 4
SIMPLE GPIO
SIMPLE GPIO
SPI_SS
SPI_SS
TIMER 5
I/O
SIMPLE GPIO
TIMER 5
SIMPLE GPIO
SIMPLE GPIO
SPI_CLK
SPI_CLK
TIMER 6
I/O
SIMPLE GPIO
TIMER 6
SIMPLE GPIO
SIMPLE GPIO
SIMPLE GPIO
SIMPLE GPIO
TIMER 7
I/O
SIMPLE GPIO
TIMER 7
SIMPLE GPIO
SIMPLE GPIO
SIMPLE GPIO
SIMPLE GPIO
Table 2-23. Timer Functions by Pin
Pin / Ball Number
Pin TIMER_0
Reset
Value
Description
Ball Y20
TIMER
hi - z
TIMER_0
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
ATA_CS0
ATA Chip Select 0
CAN2
hi - z
CAN2_TX
CAN 2 Transmit Data
SPI
hi - z
GPIO
Simple General Purpose I/O
CAN2 / SPI
hi - z
CAN2_TX
CAN 2 Transmit Data
TIMER
hi - z
TIMER_1
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
ATA_CS0
ATA Chip Select 1
CAN2
hi - z
CAN2_RX
CAN 2 Receive Data
SPI
hi - z
GPIO
Simple General Purpose I/O
CAN2 / SPI
hi - z
CAN2_RX
CAN 2 Receive Data
Pin TIMER_1
Ball V18
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-75
Signal Descriptions
Table 2-23. Timer Functions by Pin (continued)
Pin / Ball Number
Pin TIMER_2
Reset
Value
Description
Ball D03
TIMER
hi - z
TIMER_2
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
SPI _MOSI
SPI Master Out Slave In
CAN2 / SPI
hi - z
SPI MOSI
SPI Master Out Slave In
TIMER
hi - z
TIMER_3
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
SPI _MISO
SPI Master In Slave Out
CAN2 / SPI
hi - z
SPI MISO
SPI Master In Slave Out
TIMER
hi - z
TIMER_4
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
SPI _SS
SPI Slave Select
CAN2 / SPI
hi - z
SPI SS
SPI Slave Select
Pin TIMER_3
Pin TIMER_4
Ball D02
Ball D01
MPC5200B User’s Manual, Rev. 3
2-76
Freescale Semiconductor
Signal Descriptions
Table 2-23. Timer Functions by Pin (continued)
Pin / Ball Number
Pin TIMER_5
Reset
Value
Description
Ball E03
TIMER
hi - z
TIMER_5
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
SPI _CLK
SPI Clock
CAN2 / SPI
hi - z
SPI CLK
SPI Clock
TIMER
hi - z
TIMER_6
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
GPIO
Simple General Purpose I/O
CAN2 / SPI
hi - z
GPIO
Simple General Purpose I/O
TIMER
hi - z
TIMER_7
GPIO
hi - z
GPIO
Simple General Purpose I/O
ATA CHIP SELECTS
hi - z
GPIO
Simple General Purpose I/O
CAN2
hi - z
GPIO
Simple General Purpose I/O
SPI
hi - z
GPIO
Simple General Purpose I/O
CAN2 / SPI
hi - z
GPIO
Simple General Purpose I/O
Pin TIMER_6
Pin TIMER_7
Ball E02
Ball E01
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-77
Signal Descriptions
PSC6
GPIO
4
4
Pin Drivers and MUX Logic
PSC6_0
Port_conf
[9:11]
Function
PSC6_0
PSC6_2
PSC6_1
PSC6_1
PSC6_3
PSC6_2
PSC6_3
GPIO
000
GPIO_W/WAKE_ GPIO_W/WAKE_UP GPIO
UP
GPIO
UART6/
IrDA
101
UART6_RXD/
IrDA_RX
UART6_CTS
UART6_TXD/
IrDA_TX
UART6_RTS
CODEC6/
IrDA
111
CODEC6_RXD/
IrDA_RX
CODEC6_FRAME
CODEC6_TXD/
IrDA_TX
CODEC6_CLK/
IR_USB_CLK
Figure 2-11. PSC6 Port Map—4 Pins
Table 2-24. PSC6 Pin Functions
Pin Name
Dir.
GPIO
UART6/ IrDA
CODEC6 / IrDA
PSC6_0
I/O
WAKE_UP
UART6_RXD
IrDA_RX
CODEC6_RXD
Irda_RX
PSC6_1
I/O
WAKE_UP
UART6_CTS
CODEC6_FRAME
PSC6_2
I/O
SIMPLE GPIO
UART6_TXD
IrDA_TX
CODEC6_TXD
IrDA_TX
PSC6_3
I/O
SIMPLE GPIO
UART6_RTS
CODEC6_CLK/
IR_USB_CLK
Table 2-25. PSC6 Functions by Pin
Pin / Ball Number
Pin PSC6_0
Reset
Value
Description
Ball B12
GPIO
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
UART6 / IrDA
hi - z
UART6_RXD
Uart Receive Data
IrDA_RX IrDA Receive Data
CODEC6 / IrDA
hi - z
CODEC6_RXD
CODEC Receive Data
IrDA_RX IrDA Receive Data
MPC5200B User’s Manual, Rev. 3
2-78
Freescale Semiconductor
Signal Descriptions
Table 2-25. PSC6 Functions by Pin (continued)
Reset
Value
Pin / Ball Number
Pin PSC6_1
Description
Ball C11
GPIO
hi - z
GPIO
Simple General Purpose I/O with WAKE UP
UART6
hi - z
UART6_CTS
Uart Clear To Send
CODEC6
hi - z
CODEC6_FRAME
CODEC Frame Sync
GPIO
hi - z
GPIO
Simple General Purpose I/O
UART6 / IrDA
hi - z
UART6_TXD
Uart Transmit Data
IrDA_TX Irda Transmit Data
CODEC6 / IrDA
hi - z
CODEC6_TXD
CODEC Transmit Data
IrDA_TX Irda Transmit Data
GPIO
hi - z
GPIO
Simple General Purpose I/O
UART6
hi - z
UART6_RTS
Uart Clear To Send
CODEC6 / IrDA
hi - z
CODEC6_CLK
IR_USB_CLK
Pin PSC6_2
Ball A12
Pin PSC6_3
Ball C13
I2C2
I2C1
2
ATA Chip
Selects
CAN1
2
2
2
Pin Drivers and MUX Logic
I2C_0
Function
Port_conf
I2C_0
I2C_1
I2C_1
I2C_2
I2C_2
I2C_3
I2C_3
I2C1 / I2C2
default
I2C1_CLK
I2C1_IO
I2C2_CLK
I2C2_IO
CAN1 / I2C2
Port_conf[2:3]=01
CAN1_TX
CAN1_RX
I2C2_CLK
I2C2_IO
I2C1 / ATA CHIP Port_conf[6:7]=10
SELECTS
I2C1_CLK
I2C1_IO
ATA_CS_0
ATA_CS_1
Note:
1. CAN RX input supports WakeUp functionality.
Figure 2-12. I2C Port Map—4 Pins (two pins each, for two I2Cs)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-79
Signal Descriptions
Table 2-26. I2C Functions by Pin
Pin / Ball Number
Pin I2C_0
Reset
Value
Description
Ball V19
I2C_1 / I2C_2
I2C_1_CLK
I2C Clock
CAN_1/I2C_2
CAN1_TX
CAN Transmit Data
I2C_1/ATA_CS
I2C_1_CLK
I2C Clock
Pin I2C_1
Ball W19
I2C_1 / I2C_2
I2C_1_I/O
CAN1/CAN2
CAN1_RX
I2C_1/ATA_CS
I2C_1_I/O
Pin I2C_2
Ball V20
I2C_1 / I2C_2
I2C_2_CLK
I2C Clock
CAN1/CAN2
I2C_2_CLK
I2C Clock
I2C_1/ATA_CS
ATA_CS0
ATA Chip Select 0
Pin I2C_3
Ball W20
I2C_1 / I2C_2
I2C_2_I/O
I2C I/O line
CAN1/CAN2
I2C_2_I/O
I2C I/O line
I2C_1/ATA_CS
ATA_CS1
ATA Chip Select 1
MPC5200B User’s Manual, Rev. 3
2-80
Freescale Semiconductor
Signal Descriptions
Table 2-27. SDRAM Bus Pin Functions (Sheet 1 of 4)
Pin / Ball Number
Reset
Value
Description
Pin MEM_RAS
Ball A18
logic 0
SDRAM Bus Row Address Strobe
Pin MEM_CAS
Ball B19
logic 0
SDRAM Bus Column Address Strobe
Pin MEM_WE
Ball A19
logic 0
SDRAM Bus Write enable
Pin MEM_CS_0
Ball B18
logic 1
SDRAM Bus Chip Select 0
Pin MEM_CS_1
Ball C15 (GPIO_WKUP_6)
logic 1
SDRAM Bus Chip Select 1
(shared with GPIO_WKUP_6)
Pin MEM_CLK_EN
Ball F20
logic 0
SDRAM Bus Clock Enable
Pin MEM_CLK
Ball G19
logic 0
SDRAM Bus Memory Clock
Pin MEM_CLK
Ball G20
logic 1
SDRAM Bus Inverted Memory Clock
Pin MEM_MBA_1
Ball A17
logic 0
SDRAM Bus Memory Bank Address 1
Pin MEM_MBA_0
Ball C18
logic 0
SDRAM Bus Memory Bank Address 0
Pin MEM_MDQS_3
Ball L18
hi - z
SDRAM Bus Bidirectional Data Bus Strobe 3
Pin MEM_MDQS_2
Ball D18
hi - z
SDRAM Bus Bidirectional Data Bus Strobe 2
Pin MEM_MDQS_1
Ball H20
hi - z
SDRAM Bus Bidirectional Data Bus Strobe 1
Pin MEM_MDQS_0
Ball N20
hi - z
SDRAM Bus Bidirectional Data Bus Strobe 0
Pin MEM_DQM_3
Ball L17
SDRAM Bus Data Mask 3
Pin MEM_DQM_2
Ball A20
SDRAM Bus Data Mask 2
Pin MEM_DQM_1
Ball H19
SDRAM Bus Data Mask 1
Pin MEM_DQM_0
Ball N19
SDRAM Bus Data Mask 0
Pin MEM_MA_12
Ball F19
logic 0
SDRAM Bus Memory Address 12
Pin MEM_MA_11
Ball E20
logic 0
SDRAM Bus Memory Address 11
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-81
Signal Descriptions
Table 2-27. SDRAM Bus Pin Functions (Sheet 2 of 4)
Pin / Ball Number
Reset
Value
Description
Pin MEM_MA_10
Ball B17
logic 0
SDRAM Bus Memory Address 10
Pin MEM_MA_9
Ball E19
logic 0
SDRAM Bus Memory Address 9
Pin MEM_MA_8
Ball D20
logic 0
SDRAM Bus Memory Address 8
Pin MEM_MA_7
Ball D19
logic 0
SDRAM Bus Memory Address 7
Pin MEM_MA_6
Ball C20
logic 0
SDRAM Bus Memory Address 6
Pin MEM_MA_5
Ball C19
logic 0
SDRAM Bus Memory Address 5
Pin MEM_MA_4
Ball B20
logic 0
SDRAM Bus Memory Address 4
Pin MEM_MA_3
Ball C16
logic 0
SDRAM Bus Memory Address 3
Pin MEM_MA_2
Ball B16
logic 0
SDRAM Bus Memory Address 2
Pin MEM_MA_1
Ball A16
logic 0
SDRAM Bus Memory Address 1
Pin MEM_MA_0
Ball C17
logic 0
SDRAM Bus Memory Address 0
Pin MEM_MDQ_31
Ball U18
hi - z
SDRAM Bus Data 31
Pin MEM_MDQ_30
Ball T18
hi - z
SDRAM Bus Data 30
Pin MEM_MDQ_29
Ball R18
hi - z
SDRAM Bus Data 29
Pin MEM_MDQ_28
Ball R17
hi - z
SDRAM Bus Data 28
Pin MEM_MDQ_27
Ball P18
hi - z
SDRAM Bus Data 27
Pin MEM_MDQ_26
Ball N18
hi - z
SDRAM Bus Data 26
Pin MEM_MDQ_25
Ball N17
hi - z
SDRAM Bus Data 25
Pin MEM_MDQ_24
Ball M18
hi - z
SDRAM Bus Data 24
Pin MEM_MDQ_23
Ball K18
hi - z
SDRAM Bus Data 23
MPC5200B User’s Manual, Rev. 3
2-82
Freescale Semiconductor
Signal Descriptions
Table 2-27. SDRAM Bus Pin Functions (Sheet 3 of 4)
Pin / Ball Number
Reset
Value
Description
Pin MEM_MDQ_22
Ball J17
hi - z
SDRAM Bus Data 22
Pin MEM_MDQ_21
Ball J18
hi - z
SDRAM Bus Data 21
Pin MEM_MDQ_20
Ball H18
hi - z
SDRAM Bus Data 20
Pin MEM_MDQ_19
Ball G18
hi - z
SDRAM Bus Data 19
Pin MEM_MDQ_18
Ball G17
hi - z
SDRAM Bus Data 18
Pin MEM_MDQ_17
Ball F18
hi - z
SDRAM Bus Data 17
Pin MEM_MDQ_16
Ball E18
hi - z
SDRAM Bus Data 16
Pin MEM_MDQ_15
Ball M20
hi - z
SDRAM Bus Data 15
Pin MEM_MDQ_14
Ball M19
hi - z
SDRAM Bus Data 14
Pin MEM_MDQ_13
Ball L20
hi - z
SDRAM Bus Data 13
Pin MEM_MDQ_12
Ball L19
hi - z
SDRAM Bus Data 12
Pin MEM_MDQ_11
Ball K20
hi - z
SDRAM Bus Data 11
Pin MEM_MDQ_10
Ball K19
hi - z
SDRAM Bus Data 10
Pin MEM_MDQ_9
Ball J20
hi - z
SDRAM Bus Data 9
Pin MEM_MDQ_8
Ball J19
hi - z
SDRAM Bus Data 8
Pin MEM_MDQ_7
Ball P19
hi - z
SDRAM Bus Data 7
Pin MEM_MDQ_6
Ball P20
hi - z
SDRAM Bus Data 6
Pin MEM_MDQ_5
Ball R19
hi - z
SDRAM Bus Data 5
Pin MEM_MDQ_4
Ball R20
hi - z
SDRAM Bus Data 4
Pin MEM_MDQ_3
Ball T19
hi - z
SDRAM Bus Data 3
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-83
Signal Descriptions
Table 2-27. SDRAM Bus Pin Functions (Sheet 4 of 4)
Pin / Ball Number
Reset
Value
Description
Pin MEM_MDQ_2
Ball T20
hi - z
SDRAM Bus Data 2
Pin MEM_MDQ_1
Ball U19
hi - z
SDRAM Bus Data 1
Pin MEM_MDQ_0
Ball U20
hi - z
SDRAM Bus Data 0
Pin MEM_RDCLK
Ball not pinned out
clk
SDRAM Bus Memory Read Clock
(not pinned out)
Table 2-28. JTAG and Test Pin Functions
Pin / Ball Number
Reset
Value
Description
Pin JTAG_TCK
Ball B04
JTAG Test Clock
Pin JTAG_TMS
Ball A04
JTAG Test Mode Select
Pin JTAG_TDI
Ball A03
JTAG Test Data In
Pin JTAG_TRST
Ball B03
JTAG Reset
Pin JTAG_TDO
Ball A02
JTAG Test Data Out
Pin TEST_MODE_0
Ball B02
Test Mode Select 0 (for production test)
NOTE: This pin requires a pull-down resistor.
Pin TEST_MODE_1
Ball A01
Test Mode Select 1 (for production test)
NOTE: This pin requires a pull-down resistor.
Pin TEST_SEL_0
Ball B01
Scan Enable (for production test), PLL_BYPASS - input,
CK_STOP - output
Pin TEST_SEL_1
Ball C03
ENID Input in Test Mode (for production test)
NOTE: This pin requires a pull-down resistor.
MPC5200B User’s Manual, Rev. 3
2-84
Freescale Semiconductor
Signal Descriptions
Table 2-29. CLOCK / RESET Pin Functions
Reset
Value
Clock / Reset
Description
Pin PORRESET
Ball A13
logic 1
Power On Reset
Pin HRESET
Ball B13
logic 1
Hard Reset
Pin SRESET
Ball A14
logic 1
Soft Reset
Pin SYS_XTAL_IN
Ball A15
APLL Chip clock crystal / external clock input
Pin SYS_XTAL_OUT
Ball D14
clk
Pin SYS_PLL_TPA
Ball B15
APLL Chip Clock Crystal
MPC5200B System Test Pll Output (analog output)
Table 2-30. Dedicated GPIO Pin Function
Dedicated GPIO
Reset
Value
Description
Pin GPIO_WKUP_6 Ball C15
GPIO Wakeup
logic 0
Asynchronous GPIO with Wakeup Capability
GPIO_WKUP_6
Memory Chip Select
logic 0
SDRAM Chip Select 1
GPIO Wakeup
hi - z
Asynchronous GPIO with Wakeup Capability
GPIO_WKUP_7
LocalPlus MOST/Graphics TSIZ
hi - z
TSIZ1 for LocalPlus MOST/GRAPHICS mode
Pin GPIO_WKUP_7 Ball C12
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
2-85
Signal Descriptions
Table 2-31. Systems Integration Unit Pin Functions
Systems Integration Unit
Reset
Value
Descriptions
Pin LP_CS0
Ball W14
logic 1
LocalPlus Bus Chip Select 0
Pin LP_CS1
Ball Y14
logic 1
LocalPlus Bus Chip Select 1
Pin LP_CS2
Ball V15
logic 1
LocalPlus Bus Chip Select 2
Pin LP_CS3
Ball W15
logic 1
LocalPlus Bus Chip Select 3
Pin LP_CS4
Ball Y15
logic 1
LocalPlus Bus Chip Select 4
Pin LP_CS5
Ball V16
logic 1
LocalPlus Bus Chip Select 5
Pin LP_OE
Ball D08
logic 1
LocalPlus Bus Output Enable
Pin IRQ0
Ball P03
External Interrupt 0
Pin IRQ1
Ball P01
External Interrupt 1
Pin IRQ2
Ball P02
External Interrupt 2
Pin IRQ3
Ball R01
External Interrupt 3
Pin RTC_XTAL_IN
Ball C02
Real Time Clock Crystal Input / External Clock Input
Pin RTC_XTAL_OUT
Ball C01
Real Time Clock Crystal Output
MPC5200B User’s Manual, Rev. 3
2-86
Freescale Semiconductor
Chapter 3
Memory Map
3.1
Overview
The following sections are contained in this document:
• MPC5200B Internal Register Memory Map
• MPC5200B Memory Map
• SDRAM Bus
• LocalPlus Bus
— Memory Cycles
– Boot Chip Select
– Chip Selects
— ATA Cycles
— PCI Cycles
• MPC5200B Register Summaries
— Memory Map Registers — MBAR + 0x0000
— SDRAM Registers — MBAR + 0x0100
— Clock Distribution Module Registers — MBAR + 0x0200
— Chip Select Configuration Registers — MBAR + 0x0300
— Interrupt Controller Registers — MBAR + 0x0500
— General Purpose Timer Registers — MBAR + 0x0600
— Slice Timer Control Registers — MBAR + 0x0700
— Real Time Clock Registers — MBAR + 0x0800
— MSCAN Registers — MBAR + 0x0900
— Simple GPIO Registers — MBAR + 0x0B00
— Wake-up GPIO Registers — MBAR + 0x0C00
— PCI Registers — MBAR + 0x0D00
— Serial Peripheral Interface Registers — MBAR + 0x0F00
— USB Host Registers — MBAR + 0x1000
— BestComm Registers — MBAR + 0x1200
— J1850 (BDLC Controller) Registers — MBAR + 0x1300
— XL BUS ARbitration Registers — MBAR + 0x1F00
— PSC1 Registers — MBAR + 0x2000
— PSC2 Registers — MBAR + 0x2200
— PSC3 Registers — MBAR + 0x2400
— PSC4 Registers — MBAR + 0x2600
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
3-1
Memory Map
—
—
—
—
—
—
—
—
3.2
PSC5 Registers — MBAR + 0x2800
PSC6 Registers — MBAR + 0x2C00
Ethernet Registers — MBAR + 0x3000
BestComm / PCI Interface Registers — MBAR + 0x3800
ATA Bus Configuration Registers — MBAR + 0x3A00
BestComm / LocalPlus Interface Registers — MBAR + 0x3C00
I2C Configuration Registers — MBAR + 0x3D00
SRAM Module — MBAR + 0x8000
Internal Register Memory Map
Table 3-1. Internal Register Memory Map
Address
Name
Description
Reference
MBAR + 0x0000
MM
MBAR + 0x0100
SDRAM
MBAR + 0x0200
CDM
Clock Distribution Module registers.
MBAR + 0x0300
CSC
Chip Select Controller registers.
Section 9.7.1
MBAR + 0x0500
ICTL
Interrupt Controller registers.
Section 7.2.4
MBAR + 0x0600
GPT
General Purpose Timer registers.
Section 7.4.4
MBAR + 0x0700
SLT
Slice Time registers.
Section 7.5.1
MBAR + 0x0800
RTC
Real-Time Clock registers.
Section 7.6.3
MBAR + 0x0900
CAN
MSCAN registers.
Section 19.5.2
MBAR + 0x0B00
GPS
GPIO Standard registers
Section 7.3.2.1
MBAR + 0x0C00
GPW
GPIO Wake up registers.
Section 7.3.2.2
MBAR + 0x0D00
PCI
PCI XLB Configuration registers
Section 10.3
MBAR + 0x0F00
SPI
Serial Peripheral Interface registers.
Section 17.3
MBAR + 0x1000
USB
Universal Serial Bus registers.
Section 12.4
MBAR + 0x1200
BDMA
BestComm DMA registers.
Section 13.15
MBAR + 0x1300
BDLC
J1850 (BDLC) registers
Section 20.7
MBAR + 0x1F00
XLARB
MBAR + 0x2000
Memory Map Registers
Section 3.3.3
SDRAM Memory Controller registers.
Section 8.6.1
Section 5.5
XL BUS ARBITRATION Registers
Section 16.2.1
PSC1
Programmable Serial Controller 1 registers.
Section 15.2.2
MBAR + 0x2200
PSC2
Programmable Serial Controller 2 registers.
Section 15.2.2
MBAR + 0x2400
PSC3
Programmable Serial Controller 3 registers.
Section 15.2.2
MBAR + 0x2600
PSC4
Programmable Serial Controller 4 registers.
Section 15.2.2
MBAR + 0x2800
PSC5
Programmable Serial Controller 5 registers.
Section 15.2.2
MBAR + 0x2C00
PSC6
Programmable Serial Controller 6 / Infrared Data
Association registers.
Section 15.2.2
MBAR + 0x3000
ETH
Ethernet registers.
Section 14.4.3
MBAR + 0x3800
BPCI
BestComm DMA PCI registers.
Section 10.3.3
MPC5200B User’s Manual, Rev. 3
3-2
Freescale Semiconductor
Memory Map
Table 3-1. Internal Register Memory Map (continued)
Address
Name
MBAR + 0x3A00
ATA
MBAR + 0x3C00
BLPC
MBAR + 0x3D00
2
I C
MBAR + 0x8000
SRAM
3.3
Description
Reference
Advanced Technology Attachment registers.
Section 11.3.1
Section 11.3.2
Section 11.3.3
BestComm DMA LocalPlus registers
Section 9.7.2
Inter-Integrated Circuit registers.
Section 18.3
On-chip Static RAM memory locations.
Section 13.16
MPC5200B Memory Map
The MPC5200B memory map has the following main regions:
• MPC5200B Internal Register Space
• External Busses
— SDRAM Bus
— LocalPlus Bus
– External Chip Selects 0–7
– Memory Space
– Boot Space
– Program Space
– Data Space
• ATA Space
3.3.1
MPC5200B Internal Register Space
The internal registers of the MPC5200B are memory mapped, just like external RAM or any other
peripheral devices. The addresses of the internal registers are expressed as offsets to the contents of the
MBAR Register (Memory Base Address Register).
The Memory Base Address Register contains the upper 16 bits of the register address space. This sixteen
bit value is contained in the lower 16 bits (bit 16 - bit 31) of the Memory Base Address Register. The
default value at the release of RESET contained in the MBAR Register is 0x0000 8000. To form a register
address, the lower sixteen bits of MBAR are left-justified, forming address bits A31 - A16. Then the 16-bit
register offset address for a particular register is concatenated with this value to form a 32-bit address.
NOTE
On the LocalPlus Bus, A31 is the Most Significant Bit and A0 is the Least
Significant Bit. It is most important to note that the internal registers of the
MPC5200B use bit 0 as the Most Significant Bit and bit 31 as the Least
Significant Bit.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
3-3
Memory Map
NOTE
The Memory Base Address Register is memory mapped, itself, and it is also
the first register in the Internal Register Space. Because the default value in
MBAR from the release of RESET is 0x0000 8000 and the MBAR register
has an offset address of 0x0000 0000, the absolute address of MBAR
becomes 0x8000 0000.
For an additional example, the offset addresses of the Clock Distribution Module Registers start at 0x0200.
Using the default value in MBAR, the address of the first register in the Clock Distribution Module is
0x8000 0200.
NOTE
The MBAR register is a memory mapped register. In fact, the contents of the
MBAR register hold the Most Significant 16 bits of its own address. When
the contents of the MBAR register are changed, a copy of this value should
be written to Special Purpose Register SPR (0d311). This location should be
used to store the present Memory Base Address for the System Memory
map. It is the responsibility of the system programmer to ensure the present
value is current with the system’s memory base offset.
3.3.2
External Busses
There are two external data / address bus structures on the MPC5200B. These are the LocalPlus Bus and
the SDRAM Bus. The MPC5200B always begins execution from the release of RESET on the LocalPlus
Bus and from the memory device connected to LP_CS0.
3.3.2.1
SDRAM Bus
The SDRAM BUS is designed to accommodate Synchronous Single Data Rate DRAM and Synchronous
Double Data Rate DRAM. Program execution generally occurs from programs stored in the memory
located on the SDRAM Bus. The SDRAM bus has burst read capability which greatly enhances the
bandwidth of the SDRAM Bus. The Memory Clock that drives the SDRAM bus is equal to the XL Bus
clock frequency.
From Power On Reset the SDRAM Bus is inactive, that is, the chip select line for the SDRAMs is inactive.
The appropriate registers must first be programmed to configure the SDRAM Bus chip select line and
make it active before program execution can begin on the SDRAM bus. In general, when a system begins
operation from a Power On Reset, “programs stored as data” in memory devices on the LocalPlus Bus are
transferred to the SDRAM bus memory by a program stored in the Boot Device on the LocalPlus Bus.
Once the “programs stored as data” are transferred to the SDRAM bus memory, the Boot program then
causes the CPU to jump to the start address of the program which is now located in SDRAM Bus memory
and execution continues from the SDRAM Bus memory.
MPC5200B User’s Manual, Rev. 3
3-4
Freescale Semiconductor
Memory Map
3.3.2.2
LocalPlus Bus
The LocalPlus Bus is designed to connect to ROM, FLASH, static RAM and other peripheral devices. It
is not designed to accommodate DRAM’s. Program execution begins from the LocalPlus Bus memory
device connected to LP_CS0. In actual practice, the only programs that are usually executed from
LocalPlus Bus memory are those used to initialize the MPC5200B and to transfer data from LocalPlus Bus
memory to SDRAM bus memory. In general, programs are stored as data in non-volatile memory on the
LocalPlus Bus and then transferred to the SDRAM Bus. Once the transfer occurs, program execution is
transferred to a program residing in memory on the SDRAM Bus.
The LocalPlus Bus can be accessed by the CPU to perform direct reads and writes of external memory or
the LocalPlus Bus can be a BestComm Peripheral. In this case, the CPU programs the BestComm
Controller to automatically transfer data from a particular source address to the LocalPlus memory or from
the LocalPlus memory to a particular destination address. Almost all peripheral modules, such as the PSC
modules, and both the SDRAM Bus and LocalPlus Bus can be BestComm data sources or destinations.
There are 8 chip select lines, CS0 - CS7, associated with the LocalPlus Bus. Also, there are three basic
memory access types that can be run on the LocalPlus bus. These are normal memory accesses, PCI cycles
and ATA cycles.
The LocalPlus LP_CS0 pin can have two configurations. It can be the BOOT Chip Select line, which is its
default condition from the release of RESET, and it can be configured after RESET to be LP_CS0. When
configured as the BOOT Chip Select, this chip select line can select Program Space. Thus, program
execution can occur from the memory device selected by LP_CS0. If the LP_CS0 pin is configured for
data space by user software, then only Data Space Memory can be read or written.
Associated with each Chip Select line is a Start Address Register and a Stop Address Register. There are
two Chip Select Start/Stop Address Register pairs associated with the LP_CS0 pin. One Chip Select
Start/Stop Register pair is used to configure the LP_CS0 pin as the BOOT Chip Select and the other
register pair configures the LP_CS0 pin to run normal memory access cycles in data space, only. Only one
of the LP_CS0 Chip Select Start/Stop Address Register pairs should be active at any given time.
When enabled as the Boot Chip Select, only reads are possible. Reads of 64-bits are supported for
instruction fetches. Burst reads are also supported. When enabled as a data space memory chip select, only
Data Space reads and writes are supported. Code cannot be executed from a memory device connected to
LP_CS0 when it is configured as a data space chip select. Bursting is not supported and reads are limited
to 32-bits.
There are two additional Start/Stop Address Register pairs used for PCI cycles. These registers are not
associated with any chip select line. Chip Select 4 and Chip Select 5 can be configured to run normal
memory cycles or ATA cycles. Chip Select 1 - 3 and Chip Select 6 - 7 can only run normal memory cycles.
All the address related registers in this module are in the form of Start/Stop pairs. An address appearing
on XL Bus is compared as equal-to-or-greater than the Start value and less-than-or-equal-to the Stop value.
If both tests pass then a valid address “hit” occurs for the associated space. For Start values the unused bits
are assumed to be zero, for Stop values the unused bits are assumed to be high.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
3-5
Memory Map
Address registers (and the MBAR itself) have only 16 significant bits. Although these bits are
right-justified in the registers they are actually interpreted as the most significant 16 bits of the address for
comparison tests. For this reason, software must right shift an absolute address by 16 before writing it as
a value into the desired START or STOP Address register. The same is true when reading values from these
registers.
Start/Stop comparisons are enabled only if the corresponding enable bit in the MM Address Space Enable
Register is high. The proper method for updating Start/Stop registers is to first write the enable bit to zero,
update both the Start and Stop registers, and then re-enable the corresponding enable bit by writing it high.
NOTE
Failure to follow the above procedure could result in bus hanging and
machine check errors.
3.3.3
Memory Map Space Register Description
These registers exist in the Memory Map register space relative to Memory Base Address Register
(MBAR).
3.3.3.1
Memory Address Base Register
Address MBAR + 0x0000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
R
Base Address Register
W
Reset
1
0
0
0
0
0
0
0
0
0
Figure 3-1. Memory Address Base Register
Table 3-2. Memory Address Base Register Field Descriptions
Bits
Name
0:15
Reserved
16:31
Base Address
Register
Description
These bits are reserved.
Provides the offset to which all register space for MPC5200B is accessed. The reset value of this
register is 0x8000, which provides for a MBAR of 0x8000 0000. All of MPC5200B registers are then
accessible at MBAR+offset, where offset refers to the given value in <Cross Refs Helv 9>Table 3-1
for the respective module.
MPC5200B User’s Manual, Rev. 3
3-6
Freescale Semiconductor
Memory Map
3.3.3.2
Boot and Chip Select Addresses
Table 3-3. Boot and Chip Select Address Registers
MBAR
offset
Name
0x0004
CS0 Start
Address
0x0008
CS0 Stop
Address
0x000C
CS1 Start
Address
0x0010
CS1 Stop
Address
0x0014
CS2 Start
Address
0x0018
CS2 Stop
Address
0x001C
CS3 Start
Address
0x0020
CS3 Stop
Address
0x0024
CS4 Start
Address
0x0028
CS4 Stop
Address
0x002C
CS5 Start
Address
0x0030
CS5 Stop
Address
0x004C
Boot Start
Address
0x0050
Boot Stop
Address
0x0058
CS6 Start
Address
0x005C
CS6 Stop
Address
0x0060
CS7 Start
Address
0x0064
CS7 Stop
Address
Description
Chip Select 0 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 1 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 2 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 3 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 4 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 5 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Boot Addressing through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses accesses the boot space. By default, the address space accessed starts at
0x0000 0000 or 0xFFF0 0000 depends on the reset configuration. The size of the boot address
space after reset is 512Kbytes.
Chip Select 6 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
Chip Select 7 through the LocalPlus Bus. Any access on an address between the Start and
Stop Addresses enables this chip select.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
3-7
Memory Map
All of these Base Address Registers work the same
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
R
Base Address
W
Reset
1
1
1
1
1
1
1
1
1
Figure 3-2. Boot and Chip Select Address Register
Table 3-4. Boot and Chip Select Address Register Field Descriptions
Bits
Name
0:15
Reserved
16:31
Base Address
3.3.3.3
Description
These bits are reserved.
The 16 most significant bits of the Base Address. A value of 0x4000 would translate into a base
address of 0x4000 0000.
SDRAM Chip Select Configuration Registers
Table 3-5. SDRAM Chip Select Configuration Registers
MBAR
offset
Name
0x0034
SDRAM Chip
Select 0
0x0038
SDRAM Chip
Select 1
Description
Contains the Base Addresses and configurations for SDRAM’s connected to the SDRAM
controller.
MPC5200B User’s Manual, Rev. 3
3-8
Freescale Semiconductor
Memory Map
R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
W
Base XLB Address
Reserved
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
Reserved
SDRAM Size
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-3. SDRAM Chip Select Configuration Register
Table 3-6. SDRAM Chip Select Configuration Register Field Descriptions
Bits
Name
Description
0:11
Base XLB
Address
Start address for memory
12:26
Reserved
These bits are reserved.
27:31
SDRAM size
Should be set to size of SDRAM at corresponding SDRAM chip select. Settings are included in the
following table.
Note: The Base XLB Address has to be SDRAM size aligned.
Table 3-7. SDRAM Size Bit Settings
SDRAM Memory Size
SDRAM Size Bit Setting
11111
4GB
11110
2GB
11101
1GB
11100
512MB
11011
256MB
11010
128MB
11001
64MB
11000
32MB
10111
16MB
10110
8MB
10101
4MB
10100
2MB
10011
1MB
00001–10010
Reserved
0000
Disable
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
3-9
Memory Map
3.3.3.4
IPBI Control Register and Wait State Enable
The IPBI Control Register consists of the Enables for the Base Addresses set in Memory Map Space
Address MBAR + 0x0054
0
1
2
3
R
Reserved
W
Reset
4
5
6
CS7
Ena
CS6
Ena
Boot
Ena
7
8
9
Reserved
10
11
12
13
14
15
CS5
Ena
CS4
Ena
CS3
Ena
CS2
Ena
CS1
Ena
CS0
Ena
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
WSE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 3-4. IPBI Control Register
Table 3-8. IPBI Control Register Field Descriptions
Bits
Name
Description
0:3
Reserved
These bits are reserved.
4
CS7 Ena
Chip Select 7 Enable
5
CS6 Ena
Chip Select 6 Enable
6
Boot Ena
Boot Enable
7:9
Reserved
These bits are reserved.
10
CS5 Ena
Chip Select 5 Enable
11
CS4 Ena
Chip Select 4 Enable
12
CS3 Ena
Chip Select 3 Enable
13
CS2 Ena
Chip Select 2 Enable
14
CS1 Ena
Chip Select 1 Enable
15
CS0 Ena
Chip Select 0 Enable
16:30
Reserved
These bits are reserved.
31
WSE
Wait State Enable bit. This bit should always be enabled when running an IP bus frequency of
>66MHz.
MPC5200B User’s Manual, Rev. 3
3-10
Freescale Semiconductor
Chapter 4
Resets and Reset Configuration
4.1
Overview
The following sections are contained in this document:
• Hard and Soft Reset Pins
• Reset Sequence
• Reset Operation
• Other Resets
• Reset Configuration
4.2
Hard and Soft Reset Pins
MPC5200B has three primary reset pins, which are implemented as open drain I/Os1:
• Power-On Reset—PORRESET
• Hard Reset—HRESET
• Soft Reset—SRESET
PORRESET is a power-on reset input. It is asserted by an external source and must be held active for a
specified period of time until power is stable to the MPC5200B.
HRESET and SRESET can be asserted by an external source or they can be asserted by reset generation
logic internal to MPC5200B.
Internal reset logic analyzes all internal and external reset sources and asserts internal and external reset
signals appropriately.
When a hard reset (HRESET) is detected, reset logic counters hold internal and external HRESET for a
minimum of 4096 reference clock cycles or until the external HRESET source is released, whichever is
longer.
1. All “open drain” outputs of MPC5200B are actually regular 3-state output drivers with the output data tied low, and the output
enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power
rail if the external signal is driven above the MPC5200B I/O power rail voltage.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
4-1
Resets and Reset Configuration
4.2.1
Power-On Reset—PORRESET
PORRESET must be asserted externally when power is applied to the system for a required period of time
(see Section 4.4, “Reset Operation”). When PORRESET is asserted, internal logic forces HRESET and
SRESET active. PORRESET must remain asserted until the MPC5200B system oscillator begins
oscillation and the system APLL establishes a locked condition.
During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of
various vital internal MPC5200B functions. The reset configuration word is latched internally when
HRESET is released.
When initiated by PORRESET, HRESET asserts and remains asserted for 4096 reference clocks after
PORRESET is released.
Source of power-on reset is an external, board level reset source like a push button, reset control logic, etc.
4.2.2
Hard Reset—HRESET
HRESET is a bidirectional signal with a Schmitt-trigger input and an open drain output. HRESET requires
an external pull-up. Assertion of external HRESET causes external HRESET and SRESET, and internal
hard and soft resets, to be asserted for at least 4096 reference clock cycles.
During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of
various vital internal MPC5200B functions. The reset configuration word is latched internally when
PORRESET or HRESET is released.
HRESET can also be asserted by internal sources. When HRESET is asserted internally, external HRESET
and SRESET are also asserted.
Sources of hard reset are:
• PORRESET or HRESET pins asserted
• Hard reset asserted by debug module
• Reset signal asserted by watchdog timer or checkstop reset
4.2.3
Soft Reset—SRESET
External SRESET is an open drain signal. SRESET requires an external pull-up. Assertion of SRESET
causes assertion of the internal soft reset. Internal soft reset is actually an interrupt that takes the same
exception vector as HRESET. In particular, this means that SRESET cannot abort a hung XLB operation,
and no device should use SRESET in a way that interferes with any bus operation in progress.
SRESET can also be asserted by internal sources. When SRESET is asserted internally, external SRESET
is also asserted.
Sources of soft reset:
• PORRESET, HRESET, or SRESET external pins asserted
• Soft reset bit in Clock Distribution Module (CDM) register asserted by processor
• Soft reset asserted by debug module
MPC5200B User’s Manual, Rev. 3
4-2
Freescale Semiconductor
Resets and Reset Configuration
4.3
Reset Sequence
Assert internal and external
HRESET and SRESET
PORRESET is asserted
Power-On Reset
Sample configuration from
RST_CONFIG[15:0]
Power becomes stable
PORRESET is negated and
Reset configuration is latched
Internal or External
HRESET is asserted
HRESET
Reset Hold
Assert internal and external
HRESET for 4096
reference clock cycles
APLLs Lock
Sample configuration from
RST_CONFIG[15:0]
Internal or External
SRESET is asserted
Wait
No Reset signals
recognized for 2
reference clock cycles
Additional HRESET, SRESET Recognized
Figure 4-1. Reset sequence
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
4-3
Resets and Reset Configuration
4.4
Reset Operation
PORRESET must remain asserted for at least 100μs after all power supplies and the system oscillator input
are stable and operating within specs. Following deassertion of power-on reset, HRESET and SRESET
remain low for 4096 reference clock cycles.
≥100 μs
4096 ref cycles
All Power
Supplies
SYS_XTAL
PORRESET
HRESET
SRESET
Figure 4-2. PORRESET Assertion
When external HRESET is asserted, internal reset logic catches the reset signal held low and asserts
internal hard and soft resets for 4096 reference clock cycles. The external reset signal must be held low for
at least 4 reference clock cycles (must catch 4 rising edges of reference clock) to be recognized and assert
the internal reset signals.
4
Reference Clock
HRESET
1 Edge
4096 ref cycles
2 Edges
3 Edges
Internal
Reset
Figure 4-3. Internal Hard Reset vs External HRESET Assertion
The Clock Distribution Module contains a register that can be written by the microprocessor to assert soft
reset. Writing the SRESET bit in this register to zero causes external SRESET and internal soft reset to be
asserted.
MPC5200B User’s Manual, Rev. 3
4-4
Freescale Semiconductor
Resets and Reset Configuration
4.5
Other Resets
MPC5200B has four other reset signals. These signals are specific to certain peripheral modules and are
controlled in the context of that module, not globally.
.
Table 4-1. Module Specific Reset Signals
Definition
PCI_RESET
PCI bus reset output. Generated by processor write to a PCI register.
AC97_1_RES
AC97 reset output. Generated from the AC97 PSC1 module.
AC97_2_RES
AC97 reset output. Generated from the AC97 PSC2 module.
JTAG_TRST
JTAG reset input. Generated externally from JTAG or debug control logic. This input only resets the JTAG
logic. Other system resets (PORRESET, HRESET, and SRESET) do not reset the JTAG logic.
Note: For information on the reset signal JTAG_TRST and the relationship to other reset signals refer to
the MPC5200 Hardware Specifications.
ATA Reset
This is NOT a reset pin on MPC5200B. The ATA reset for the external drive must be supplied by the board
level reset source, or if software control is required, generated via a GPIO.
4.6
Reset Configuration
The MPC5200B is initialized by sampling values found on specific device pins during power-on reset
(PORRESET) or hard-reset (HRESET). These pins are outputs in normal operation, but are sampled as
inputs during power-on reset or hard-reset. External pull-up or pull-down resistors on the board are used
to force a value on these pins during power-on reset or hard-reset. These values are latched into the CDM
Reset Configuration register at the end of power-on reset or hard-reset, then distributed to various
peripherals. After power-on reset or hard-reset, these outputs overdrive the external pull-up or pull-down
resistors and behave as functional outputs. Only during power-on reset or hard-reset these pins are inputs.
Table 4-2 gives the power-on reset or hard-reset configuration inputs.
Table 4-2. Reset Configuration Word Source Pins
Pkg
Ball
Reset
Config Pin
I/O Signal
Name
CDM Reset
Config
Register Bit
Config Signal
from CDM
Y18
RST_CFG0
ATA_DACK
PORCFG[31]
ppc_pll_cfg_4
Y17
RST_CFG1
ATA_IOR
PORCFG[30]
ppc_pll_cfg_3
W17
RST_CFG2
ATA_IOW
PORCFG[29]
ppc_pll_cfg_2
W16
RST_CFG3
LP_RWB
PORCFG[28]
ppc_pll_cfg_1
V14
RST_CFG4
LP_ALE
PORCFG[27]
ppc_pll_cfg_0
Y13
RST_CFG5
LP_TS
PORCFG[26]
xlb_clk_sel
H02
RST_CFG6
USB1_1
PORCFG[25]
sys_pll_cfg_0
bit=0:fsystem =16 x SYS_XTAL_IN
bit=1:fsystem =12 x SYS_XTAL_IN
H03
RST_CFG7
USB1_2
PORCFG[24]
sys_pll_cfg1
bit=0:fvcosys = fsystem
bit=1:fvcosys = 2 x fsystem
Description
MPC5200B G2_LE PPC Core PLL
Configuration
bit=0:XLB_CLK=fsystem / 4
bit=1:XLB_CLK=fsystem / 8
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
4-5
Resets and Reset Configuration
Table 4-2. Reset Configuration Word Source Pins (continued)
Pkg
Ball
Reset
Config Pin
I/O Signal
Name
CDM Reset
Config
Register Bit
Config Signal
from CDM
K01
RST_CFG8
ETH0
PORCFG[23]
boot_rom_mg
bit=0:No Boot in Most Graphics Mode 1
bit=1:Boot in Most Graphics Mode 1,2,4
K03
RST_CFG10
ETH2
PORCFG[21]
ppc_msrip
Microprocessor Boot Address/Exception
table location.
bit=0:0000_0100 (hex)
bit=1:FFF0_0100 (hex)
J01
RST_CFG11
ETH3
PORCFG[20]
boot_rom_wait
bit=0:4 PCI bus clocks of wait state
bit=1:48 PCI bus clocks of wait state
J02
RST_CFG12
ETH4
PORCFG[19]
boot_rom_swap
bit=0:no byte lane swap, same
endian ROM image
bit=1:byte lane swap, different
endian ROM image
L03
RST_CFG13
ETH5
PORCFG[18]
boot_rom_size
For non-muxed boot ROMs: 2,3
bit=0:8bit boot ROM data bus, 24bit
max boot ROM address bus
bit=1:16bit boot ROM data bus, 16bit
boot ROM address bus
For muxed boot ROMs:
boot ROM address is max 25 significant bits
during address tenure.
bit=0:16bit ROM data bus
bit=1:32bit ROM data bus
N02
RST_CFG14
ETH6
PORCFG[17]
boot_rom_type
bit=0:non-muxed boot ROM bus,
single tenure transfer. 1
bit=1:muxed boot ROM bus, with
address and data tenures,
ALE and TS active. 1
K02
RST_CFG15
ETH1
PORCFG[16]
large_flash_sel
bit=0:No Boot in Large Flash Mode 1
bit=1:Boot in Large Flash Mode 1,3,4
Description
Note:
1. If multiple settings are chosen, the following priorities are valid:
large_flash_sel
boot_rom_mg
boot_rom_type
2. The boot_rom_size configuration signal doesn’t influence the address and data bus width of the MOST Graphics boot mode
configuration. The maximum address bus width is fixed to 24 bit and the data bus width is fixed to 32 bit.
3. The boot_rom_size configuration signal doesn’t influence the address bus width of the Large Flash boot mode configuration. The
maximum address bus width is fixed to 26 bit.
4. The PCI controller is disabled, if booting in Large Flash or MOST Graphics mode is selected.
MPC5200B User’s Manual, Rev. 3
4-6
Freescale Semiconductor
Chapter 5
Clocks and Power Management
5.1
Overview
The following sections are contained in this document:
• Clock Distribution Module (CDM)
• MPC5200B Clock Domains
• Power Management
• CDM Registers
5.2
Clock Distribution Module (CDM)
The CDM is the source of all internally generated clocks and reset signals. The MPC5200B clock
generation uses two analog phase locked loop (APLL) blocks. The system APLL takes an external
reference frequency (nominal 27–33MHz) and generates the following internal clocks. See Table 5-1.
Table 5-1. Clock Distribution Module
Clock Name
XLB CLOCK
(xlb_clk)
MEM_CLOCK
(mem_clock)
IPB CLock
(ipb_clk)
PCI CLOCK
(pci_clk)
Description
Microprocessor on-chip 64-bit XLB clock. This is the fundamental MPC5200B frequency.
SDRAM Controller memory clock supplied to external SDRAM devices. Max frequency is 132MHz. The
memory clock frequency is always equal to the XLB frequency.
Intellectual Property Bus (IPB) clock.
PCI Controller clock.
CORE CLOCK
Clock for the e300 Core. The core APLL takes the XLB clock and generates the e300 clock.
48MHz CLOCK
USB CLOCK
48MHz clock for USB and IrDA (PSC6). This clock can be sourced internally from the CDM or from an
external source via the IrDA_USB_CLK pin.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-1
Clocks and Power Management
5.3
MPC5200B Clock Domains
The MPC5200B has 5 major clock domains, which are listed below. Details are given in the sections that
follow.
• e300 Core Clock Domain—internal processor core frequency
• Processor Bus (XLB) Clock Domain —internal e300 Core processor bus
• SDRAM Memory Controller Clock Domain
• IPB Clock Domain—programming register and peripheral interface frequency
• PCI Clock Domain
The following smaller peripheral clock domains can be asynchronous to the fundamental clock
frequencies on MPC5200B:
• Ethernet—The Ethernet Controller requires a 10MHz (10 Mbit operation) or 25MHz (100 Mbit
operation) Tx/Rx clock. Both clocks are inputs to the MPC5200B, supplied from the Ethernet
physical device (ETH_RXCLK, ETH_TXCLK pins). The Ethernet Controller Tx/Rx portion of
the MPC5200B is asynchronous to the rest of MPC5200B.
• USB—The Universal Serial Bus module Tx/Rx portion can be clocked by an external clock source
(IR_USB_CLK pin) or by an internally generated clock. Clock frequency must be 48MHz. When
the clock source is externally supplied, the USB module Tx/Rx portion is asynchronous to the rest
of MPC5200B.
• PSC—The PSC (Programmable Serial Controller) module is instantiated in the MPC5200B 6
times (PSC1 to PSC6). The PSC has different modes of operation. In some cases the logic is
clocked by internally generated clocks (i.e., UART mode), and in others the PSC is clocked by
external clock sources (i.e., CODEC mode). If the PSC logic is clocked from an external source
then the logic is asynchronous to the rest of the chip.
• When the PSC6 is configured as IrDA—The Infrared Data Association module Tx/Rx portion can
be clocked by an external clock source (IR_USB_CLK pin) or by an internally generated clock.
— When generated internally, the clock source can be a fix 48MHz clock generator or a
programmable clock generator (Mclk).
— When generated externally, the frequency can be different
NOTE
Only one pin is allocated to supply the USB and PSC6/IrDA clock. If both
modules require external clock generation, the frequency must be 48MHz.
•
•
•
SPI—The SPI (Serial Peripheral Interface) has a clock input pin, SPI_CLK. When the SPI is
configured as a slave, the clock is supplied externally. The SPI module therefore has a small
asynchronous clock domain.
I2C—There are two I2C (Inter-Integrated Circuit) modules on MPC5200B. Both have input source
clocks (I2Cx_CLK) and therefore asynchronous clock domains.
RTC—The RTC (Real-Time Clock) has its own clock domain, clocked by an external 32.768KHz
oscillator. The two oscillator pins are RTC_XTAL_IN and RTC_XTAL_OUT. There is an
asynchronous boundary between this clock domain and the IPB register interface.
MPC5200B User’s Manual, Rev. 3
5-2
Freescale Semiconductor
Clocks and Power Management
•
JTAG—The JTAG (Joint Test Action Group) has its own clock domain clocked by the
JTAG_TCK pin.
The following peripheral functions use clocks generated from CDM.
• MSCAN—The MSCAN (Freescale [formerly Motorola] Scalable Controller Area Network)
internal baud rate generator also uses the ipb_clk or can be derived from the oscillator clock
sys_xtal_in. The resultant divided clock samples an incoming CAN data stream and generates an
outgoing data stream.
SDRAM / DDR
Memory Controller
e300 Core
Clock System
Divider PLL
XL Bus
Arbiter
XLB
XLB
IPB
CommBus
IPBI
CONF
REG
PCI Bus
Controller
ATA
Controller
IPB
SIO
timers
interrupt
PCI Bus
Control
LocalPlus Bus
Controller
BestComm
DMA
BestComm
SRAM
SYS_XTAL Clock Domain
VCO Clock Domain
Processor Clock Domain
MEM_CLK Clock Domain
XLB_CLK Clock Domain
IPB_CLK Clock Domain
PCI_CLK Clock Domain
Shared External Bus
Local Bus
Control
ATA
Control
IPB
USB
GPIO WKUP
CommBus
GPIO
MSCAN1
MSCAN2
J1850
SPI
I2C_1
I2C_2
PSC_1 PSC_6
Ethernet
PERIPHERAL/FUNCTIONAL PIN MUXING
Figure 5-1. Primary Synchronous Clock Domains
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-3
Clocks and Power Management
5.3.1
MPC5200B Top Level Clock Relations
Figure 5-2 shows the CDM clock divide circuitry. This picture shows only the functional clocks. The clock
network regarding the scan and bypass modes is not included.
VCO
fVCOcore
divide by
2 or 4
e300
CORE CLOCK
e300
Core APLL
divide by
2, 2.5,3.0...7.5, 8
Core APLL
Control Logic
rst_cfg[0:4]
ppc_pll_cfg[0:4]
XLB CLOCK
MEM CLOCK
XLB Clock Divider
fsystem / (8 or 4)
xlb_clk_sel
0
divide
by 2
IPB CLOCK
1
ipb_clk_sel
PCI Clock Divider
PCI CLOCK
xlb_clk_sel
ipb_clk_sel
pci_clk_sel[1:0]
fsystem
VCO
fVCOsys
divide
by 2
SYS_XTAL_IN
0
1
Fractional Divider
fsystem / (6, 6.25, 6.5.11)
USB CLOCK
48 MHz CLOCK
System APLL
sys_pll_cfg[1]
1
divide
by 12
0
divide
by 16
sys_pll_cfg[0]
PSC1 MCLK DIVIDER
fsystem / (MclkDiv[8:0]+1)
PSC1 MCLK
PSC2 MCLK DIVIDER
fsystem / (MclkDiv[8:0]+1)
PSC2 MCLK
PSC3 MCLK DIVIDER
fsystem / (MclkDiv[8:0]+1)
PSC3 MCLK
PSC6 MCLK DIVIDER
fsystem / (MclkDiv[8:0]+1)
PSC6 MCLK
Figure 5-2. MPC5200 Clock Relations
MPC5200B User’s Manual, Rev. 3
5-4
Freescale Semiconductor
Clocks and Power Management
Table 5-2 shows the System PLL configuration and the corresponding fsystem frequencies for a 27.0 MHz
and 33.0 MHz input clock. Table 5-3 shows all possible clock ratios.
Table 5-2. System PLL Ratios
SYS_XTAL_IN
sys_pll_cfg[1]
sys_pll_cfg[0]
fVCOsys [MHz]
fsystem [MHz]
0
0
432.0
432.0
0
1
324.0
324.0
1
1
0
864.0
432.0
1
1
648.0
324.0
0
0
528.0
528.0
0
1
396.0
396.0
1
1
0
1056.0
528.0
1
1
792.0
396.0
27.0
33.0
1
These are invalid configurations. The fVCOsys frequencies exceed the maximum operation frequency. See MPC5200B
Hardware Specification.
Table 5-3. MPC5200B Clock Ratios
xlb_clk_sel
XLB CLOCK
ipb_clk_sel
IPB CLOCK
pci_clk_sel[1:0]
PCI CLOCK
CLOCK Ratio
XLB:IPB:PCI
0
fsystem / 4
0
XLB
00
XLB
4:4:4
0
fsystem / 4
0
XLB
01
XLB/2
4:4:2
0
fsystem / 4
0
XLB
10
XLB/4
4:4:1
0
fsystem / 4
0
XLB
11
XLB/4
4:4:1
0
fsystem / 4
1
XLB /2
00
XLB/2
4:2:2
0
fsystem / 4
1
XLB /2
01
XLB/4
4:2:1
0
fsystem / 4
1
XLB /2
10
XLB/4
4:2:1
0
fsystem / 4
1
XLB /2
11
XLB/4
4:2:1
1
fsystem / 8
0
XLB
00
XLB
2:2:2
1
fsystem / 8
0
XLB
01
XLB/2
2:2:1
1
fsystem / 8
0
XLB
10
XLB/4
2:2:0.5
1
fsystem / 8
0
XLB
11
XLB/4
2:2:0.5
1
fsystem / 8
1
XLB /2
00
XLB/2
2:1:1
1
fsystem / 8
1
XLB /2
01
XLB/4
2:1:0.5
1
fsystem / 8
1
XLB /2
10
XLB/4
2:1:0.5
1
fsystem / 8
1
XLB /2
11
XLB/4
2:1:0.5
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-5
Clocks and Power Management
Table 5-4. Typical System Clock Frequencies
fsystem
[MHz]
XLB Clock
[MHz]
IPB CLock
[MHz]
PCI CLOCK
[MHz]
Clock Ratio
XLB:IPB:PCI
132.0
66.0
4:4:2
33.0
4:4:1
66.0
4:2:2
33.0
4:2:1
33.0
33.0
4:1:1
66.0
66.0
2:2:2
33.0
2:2:1
33.0
2:1:1
132.0
528.0
66.0
66.0
33.0
Table 5-4 shows the typical clock ratios with a 33.0 MHz clock input on the SYS_XTAL_IN pin and a
System PLL divide value 16 (sys_pll_cfg[0] = 0).
NOTE
Frequency ranges in Table 5-3 and Table 5-4 represent possible ranges of
operation. A variety of conditions may prevent the part from actually
performing at these frequency ranges. For data relating to actual
performance, see Section A.2, AC Timing.
MPC5200B User’s Manual, Rev. 3
5-6
Freescale Semiconductor
Clocks and Power Management
5.3.2
e300 Core Clock Domain
The e300 Core has its own APLL and clock domain, which is separate from, but synchronous with, the
rest of the chip. The reference for the processor APLL is the XLB clock. The e300 Core can run at all
integer and half-integer multiples of xlb_clk from 2x to 8x (i.e., 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x,
6.5x, 7x, 7.5x, 8x) to a maximum frequency of 396MHz. Table 5-5 shows the available core frequencies
based on the xlb_clk frequency range.
NOTE
These frequencies are not guaranteed. Actual operation frequencies will
depend on silicon characterization and operating conditions.
Table 5-5. e300 Core Frequencies vs. XLB Frequencies
132
108
99
81
66
54
49.5
40.5
33
27
x1
—
—
—
—
—
—
—
—
—
—
x1.5
—
—
—
—
—
—
—
—
—
—
x2
264
216
198
162
132
108
99
81
66
54
x2.5
330
270
247.5
202.5
165
135
123.8
101.3
82.5
67.5
x3
396
324
297
243
198
162
148.4
121.5
99
81
378
346.5
283.5
231
189
173.3
141.8
115.5
94.5
396
324
264
216
198
162
132
108
364.5
297
243
222.8
182.3
148.5
121.5
x5
330
270
247.5
202.5
165
135
x5.5
363
297
272.3
222.8
181.5
148.5
x6
396
324
297
243
198
162
x6.5
351
321.8
263.3
214.5
175.5
x7
378
346.5
283.5
231
189
x7.5
371.3
303.8
247.5
202.5
x8
396
324
264
216
e300 Core PLL Bus to Core Multiplier1
XLB Clock (MHz)
x3.5
x4
x4.5
Note: 1x and 1.5x multiply ratios are not available in this version of the MPC5200B.
1
See Table 5-6, XLB to CORE clock ratio.
Table 5-6 gives the e300 Core APLL and operating frequency options compared to the xlb_clk reference
input (shown in Figure 5-2). The selection of an e300 Core frequency is made at Power-On Reset (POR)
via the reset configuration inputs. For more information see Section 4.6, “Reset Configuration”.
Frequency ranges indicated in Table 5-6 represent possible ranges for the processor APLL. A variety of
conditions may prevent the part from actually performing at these frequency ranges. For data relating to
actual performance, see the MPC5200B Hardware Specification.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-7
Clocks and Power Management
Table 5-6. e300 Core APLL Configuration Options
ppc_pll_cfg
hex
[0:1:2:3:4]
Bus:Core Ratio
(XLB : CORE CLOCK)
Core:VCO Ratio
(CORE CLOCK: fVCOcore)
Bus:VCO Ratio
(XLB : fVCOcore)
0x00
00000
—
—
—
0x01
00001
—
—
—
0x02
00010
—
—
—
0x04
00100
1:2
1:2
1:4
0x05
00101
1:2
1:4
1:8
0x06
00110
1:2.5
1:2
1:5
0x07
00111
1:4.5
1:2
1:9
0x08
01000
1:3
1:2
1:6
0x09
01001
1:5.5
1:2
1:11
0x0A
01010
1:4
1:2
1:8
0x0B
01011
1:5
1:2
1:10
0x0C
01100
—
—
—
0x0D
01101
1:6
1:2
1:12
0x0E
01110
1:3.5
1:2
1:7
0x10
10000
1:3
1:4
1:12
0x11
10001
1:2.5
1:4
1:10
0x12
10010
1:6.5
1:2
1:13
0x14
10100
1:7
1:2
1:14
0x16
10110
1:7.5
1:2
1:15
0x18
11000
—
—
—
0x1C
11100
1:8
1:2
1:16
0x03
0x13
00011
10011
PLL off/bypassed
xlb_clk clocks core directly, 1x bus-to-core
0x0F
0x1F
01111
11111
PLL off, no core clocking occurs.
0x15
0x17
0x19
0x1A
0x1B
0x1D
0x1E
10101
10111
11001
11010
11011
11101
11110
Reserved, should not be used.
Note: Shading implies same mode can be configured with ppc_pll_cfg[0]=0
NOTE
The XLB CLOCK frequency and the ppc_pll_cfg[0:4] must be chosen such
that resulting CORE CLOCK frequency and PLL (fVCOcore) frequency do
not exceed their respective maximum or minimum operating frequencies.
Refer to Table 5-5 and MPC5200B Hardware Specification.
MPC5200B User’s Manual, Rev. 3
5-8
Freescale Semiconductor
Clocks and Power Management
5.3.3
Processor Bus (XLB) Clock Domain
The XLB clock (xlb_clk) is the fundamental MPC5200B clock frequency. The following operate at this
frequency:
• The internal processor address/data bus
• The internal SDRAM Controller
• External SDRAM
All functional blocks that interface to the XLB must operate at this frequency, or have a section of logic
that operates at this frequency.
5.3.4
SDRAM Memory Controller Clock Domain
The Memory Controller uses the clocks shown in Table 5-7.
Table 5-7. SDRAM Memory Controller Clock Domain
Bits
Description
mem_clk
mem_clk is always the same frequency as xlb_clk.
mem_2x_clk,
mem_2x_clk
These internal clocks are twice the frequency of xlb_clk and are used to add more resolution to
SDRAMC control signals
mem2x1x_clk
(becomes
mem_rd_clk)
This is the source of the internal memory read clock. It always operates at the memory data rate,
1x mem_clk for SDR, 2x mem_clk for DDR. The physical circuit path of mem2x1x_clk is matched
as closely as possible to the on-chip portion of the memory clock output and the read data input;
a tapped delay chain is used to match off-chip portions of the memory clock and read data path.
Figure 5-3 shows the clock relationships for the SDRAM Controller.
SDR SDRAM Memory Clocks
xlb_clk
MEM_MEMCLK, mem_clk
mem_2x_clk
mem_2x_clk
mem2x1x_clk
DDR SDRAM Memory Clocks
xlb_clk
MEM_MEMCLK, mem_clk
mem_2x_clk
mem_2x_clk
mem2x1x_clk
Figure 5-3. Timing Diagram—Clock Waveforms for SDRAM and DDR Memories
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-9
Clocks and Power Management
The XLB is 64bits and the SDRAM external bus is 32bits. When SDR (single data rate) SDRAM memory
is used, the XLB bandwidth is only half utilized. When DDR (dual data rate) memory is used, the XLB
bandwidth is fully used on SDRAM transactions.
MPC5200B supplies 2 external memory clocks as part of the SDRAM interface:
• MEM_MEMCLK
• MEM_MEMCLK
MEM_MEMCLK and MEM_MEMCLK are always the same frequency as XLB clock. SDR memory uses
MEM_MEMCLK only; DDR memory uses both MEM_MEMCLK and MEM_MEMCLK.
5.3.5
IPB Clock Domain
IPB clock can run at the same frequency as XLB clock, or 1/2 the frequency. BestComm runs at the IPB
clock frequency as does all IPB control register access logic.
5.3.6
PCI Clock Domain
The PCI bus clock is the fundamental frequency of the PCI bus interface. The PCI clock can run at the
XLB clock frequency, or 1/2 the XLB clock frequency, or 1/4 the XLB clock frequency. The PCI clock
cannot be faster than IPB Clock.
5.4
Power Management
Power Management modes are listed below. Details are given in the sections that follow.
• Full-Power Mode
• Power Conservation Modes
The MPC5200B design is equipped with many power conservation features, which are supported in the
peripherals and system logic. The e300 Core has its own power-down modes:
• nap
• doze
• sleep
Individual peripheral functions can be disabled by stopping the module’s clock. In addition to clock control
of individual peripheral functions, clock control sequencer (CCS) logic sequences the MPC5200B clock
system to enter and exit a deep-sleep power mode. This limits power consumption to device leakage levels.
The MPC5200B system is driven by:
• a 27/33MHz system OSC, and
• a 32KHz real-time clock (RTC) OSC.
The 27/33MHz OSC drives the main clock system through a PLL that multiplies the frequency for the
system buses and peripherals on the chip. The e300 Core uses the XLB frequency as an input to the
microprocessor PLL that generates the internal core frequencies.
MPC5200B User’s Manual, Rev. 3
5-10
Freescale Semiconductor
Clocks and Power Management
The RTC clock domain is completely separate from the 27/33MHz clock domain. All interactions between
the RTC clock domain and any other are handled with synchronizers.
5.4.1
Full-Power Mode
In Full-Power mode both the system PLL and microprocessor PLL are locked and the main system clocks
are supplied to the MPC5200B system. In this mode, the e300 Core may use the Dynamic Power Mode
(DPM). If this mode is enabled, logic not required for instruction execution, is not activated. This results
in power reduction over a design that would be fully clocked during normal operation.
Performance in not decreased in Dynamic Power Mode, so it is recommended that it should never be
disabled (although it is possible) when running the core at full speed.
MPC5200B peripherals can be individually enabled based on what functionality is required by the
application running and the external stimulus presented to MPC5200B. Peripherals not required can be
powered-down through a write to an MPC5200B system control register which disables the peripheral and
gates the peripheral clock.
5.4.2
Power Conservation Modes
Sleep modes in the MPC5200B design can be exercised through microprocessor sleep mode control and
peripheral clock disables. In all modes except Deep-Sleep mode, the system crystal oscillator is enabled,
and the system PLL and microprocessor PLL remain locked. Response time to WakeUP interrupts is faster
than in the deep-sleep mode (see Section 5.4.4, “Deep-Sleep Mode”). Since clocks are still running in the
MPC5200B chip, any interrupt normally present in the MPC5200B design can be used to wake up the
power-down logic. See Section 5.5.1.6, “CDM Clock Enable Register”, Clock Enable register.
5.4.3
e300 Core Power Modes
The e300 Core power management modes are listed below. Details are given in the sections that follow.
• Dynamic Power Mode (default power state)
• Doze Mode
• Nap Mode
• Sleep Mode
These modes are controlled by writes to an internal e300 Core control register. These modes only apply to
the e300 Core. Logic outside the e300 Core remains active unless separately disabled. In any of these
modes, peripherals can be enabled or disabled by writing to an MPC5200B system control register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-11
Clocks and Power Management
5.4.3.1
Dynamic Power Mode
This is the default power state mode. The core is fully powered and internal functional units are operating
at the full processor clock speed. If Dynamic Mode is enabled, idle functional units automatically enter a
low-power state. This does not effect:
• Performance
• Software execution
• External hardware
5.4.3.2
Doze Mode
All functional e300 Core units are disabled except for the time base/decrementer registers and the bus
snooping logic. When the processor is in Doze Mode, any of the following actions returns the core to
Full-Power Mode:
• An external asynchronous interrupt
• A system management interrupt
• A decrementer (DEC) exception
• A hard or soft reset
• A machine check input (MCP) signal
In Doze Mode, the core maintains the PLL in a fully powered state and locked to the system XLB clock
input. Transition to Full-Power Mod takes only a few processor clock cycles.
5.4.3.3
Nap Mode
The Nap Mode further reduces e300 Core power consumption by disabling bus snooping, leaving only the
time base register and the PLL in a powered state. When in Nap Mode, any of the following actions returns
the core to Full-Power Mod:
• An external asynchronous interrupt
• A system management interrupt
• A DEC exception
• A hard or soft reset
• An MCP signal
Transition to Full-Power Mode takes only a few processor clock cycles.
NOTE
It is not allowed to set the ccs_sleep_en bit of CDM Clock Control
Sequencer Configuration Register before entering the nap mode. Otherwise
all clocks will be disabled by entering the nap mode.
MPC5200B User’s Manual, Rev. 3
5-12
Freescale Semiconductor
Clocks and Power Management
5.4.3.4
Sleep Mode
Sleep Mode reduces e300 Core power consumption to a minimum. It does this by disabling all internal
functional units.
Any of the following actions returns the core to Full-Power Mode:
• An external asynchronous interrupt
• A system management interrupt
• A hard or soft reset
• An MCP signal
In Sleep Mode it is possible to disable the e300 Core PLL, further reducing power. this requires special
sequencing logic external to the e300 Core and is discussed in Section 5.4.4, “Deep-Sleep Mode”.
5.4.4
Deep-Sleep Mode
The MPC5200B system provides a very low power consumption mode where the 27/33MHz system
oscillator, system PLL and e300 Core PLL are shut down and disabled. Once MPC5200B is sequenced
into this mode and clocks are static, the current draw of the device (except the RTC) is reduced to leakage
levels. The internal state of the device is maintained in Deep Sleep as long as power is maintained.
The real-time clock (RTC) is not disabled in Deep Sleep. If the RTC is used, that portion of the chip still
consumes power in Deep Sleep.
Exiting Deep Sleep mode is initiated in one of the following ways:
• An interrupt from the RTC logic
• An external asynchronous interrupt (wake up interrupt)
• An interrupt from one of the MSCAN modules (which occurs when a data transition occurs on the
serial input).
The RTC clock is necessary to wake up MPC5200B using an RTC interrupt. However, no clock is required
to trigger the wake up process in the case of an external interrupt or the MSCAN module interrupt. This
means the RTC clock does not have to be present to use Deep Sleep mode. The e300 Core must enable the
deep sleep process in the CDM module, then put itself into sleep mode before the e300 Core PLL can be
disabled.
Since MPC5200B clocks are stopped in Deep Sleep mode, the wake-up time is longer than in the e300
Core-only power down modes. A power-on sequence must occur which re-locks both the MPC5200B
system and processor PLLs.
The sequence of events to enter and exit Deep Sleep mode are initiated by the e300 Core under software
control and then sequenced in hardware by the Clock Control Sequencer (CCS) in CDM.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-13
Clocks and Power Management
5.4.4.1
Entering Deep Sleep
When entering Deep Sleep mode, the following occurs:
• e300 Core prepares the system for Deep Sleep power down.
This could involve disabling peripheral interfaces, waiting for transmit/receive messages to
complete, putting the SDRAM into self refresh mode, etc.
• e300 Core finishes instructions in the execution pipeline.
• e300 Core software enables the Deep Sleep mode with a write to a MPC5200B control register.
• e300 Core Processor software writes sleep mode configuration to e300 Core Processor control
register.
• e300 Core Processor asserts the QREQ signal indicating that it would like to enter sleep mode.
• CCS waits for e300 Core Processor sleep (initiated by QREQ, since QACK is always asserted in
MPC5200B).
• CCS disables interrupts.
• CCS waits for the e300 Core Processor to enter the sleep mode.
• CCS disables the OSC, system PLL, e300 Core Processor PLL and gates the system clocks.
5.4.4.2
Exiting Deep Sleep
When exiting Deep Sleep mode, the following occurs:
• CCS receives an interrupt from a GPIO pin, RTC or a MSCAN peripheral.
• CCS enables the OSC and waits for the OSC to stabilize.
• CCS enables the system PLL and waits for the PLL to lock to the OSC clock.
• CCS enables system clocks.
• CCS enables the e300 Core Processor PLL and waits for the PLL to lock to the system PLL clock.
• CCS enables interrupts, which triggers a wakeup interrupt to the e300 Core Processor (from the
WakeUp source).
• e300 Core Processor wakes up and puts MPC5200B into full power mode and then services the
wakeup interrupt
Waking up from Deep Sleep mode does not require the system to be reset or a boot sequence. The
functional state of MPC5200B should remain the same as when it went into Deep Sleep. If the SDRAM
was put into self refresh mode, its contents should also remain unchanged.
MPC5200B User’s Manual, Rev. 3
5-14
Freescale Semiconductor
Clocks and Power Management
5.5
CDM Registers
The Clock Distribution Module (CDM) contains 14 32-bit registers. All registers are located at an offset
from the value in the Module Base Address Register (MBAR). The CDM base offset is 0x0200.
5.5.1
Register Descriptions
Hyperlinks to the CDM registers are provided below:
• CDM JTAG ID Number Register (0x0200), read-only
• CDM Power On Reset Configuration Register (0x0204)
• CDM Bread Crumb Register (0x0208), never reset
• CDM Configuration Register (0x020C)
• CDM 48 MHz Fractional Divider Configuration Register Field Descriptions (0x0210)
• CDM Clock Enable Register (0x0214)
• CDM System Oscillator Configuration Register (0x0218)
• CDM Clock Control Sequencer Configuration Register (0x021C)
• CDM Soft Reset Register (0x0220)
• CDM System PLL Status Register (0x0224)
• PSC1 Mclock Configuration Register (0x0228)
• CDM PSC2 Mclock Configuration Register (0x022C)
• CDM PSC3 Mclock Configuration Register (0x0230)
• CDM PSC6 Mclock Configuration Register Field Descriptions (0x0234)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-15
Clocks and Power Management
5.5.1.1
CDM JTAG ID Number Register
The CDM JTAG ID Number Register is a read-only register that contains the JTAG Identification number
identifying MPC5200B. The value is hard coded (1001 101D hex) and cannot be modified.
Address MBAR + 0x0200
0
1
2
3
4
5
6
7
8
9
R
JTAG Identification Number Register
W
Unused
Reset
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
1
1
0
1
R
JTAG Identification Number Register
W
Unused7
Reset
10
0
0
0
1
0
0
0
0
0
0
Figure 5-4. CDM JTAG ID Number Register
Device I.D. Register = 1001 101D hex
Table 5-8. CDM JTA ID Numbering
Version
Device (MPC5200B)
Manufacturer (Freescale)
0001
0000 0000 0001 0001
0000 0001 110
1
MPC5200B User’s Manual, Rev. 3
5-16
Freescale Semiconductor
Clocks and Power Management
5.5.1.2
CDM Power On Reset Configuration Register
This is a mostly read-only register containing the configuration value latched at POR.
Address MBAR + 0x0204
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R
Reserved
Write 0
Reserved
15
sys_pll
_bypass
0
Reserved, Read Only
0
0
0
1
0
0
0
0
0
0
0
0
0
0
V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
boot_
ram_size
boot_
ram_swap
boot_
ram_wait
ppc_
msrip
boot_
ram_mg
sys_pll_
cfg_1
sys_pll_
cfg_0
xlb_
clk_sel
ppc_pll
_cfg_0
ppc_pll
_cfg_1
ppc_pll
_cfg_2
ppc_pll
_cfg_3
ppc_pll
_cfg_4
R
0
boot_
ram_type
Reset
boot_
ram_lf
W
V
V
V
V
V
V
W
Reset
Reserved, Read Only
V
V
V
V
V
V
—
V
V
V
Figure 5-5. CDM Power On Reset Configuration Register
Table 5-9. CDM Power On Reset Configuration Register Field Descriptions
Bit
Name
Description
0–2
—
Reserved for future use. Write 0.
3–7
—
Reserved.
8-14
—
Read Only. Do not write.
15
sys_pll_bypass
16
boot_rom_lf
17
boot_rom_type
Latched pin value at reset.
bit=0:non-muxed boot ROM bus, single tenure transfer.
bit=1:muxed boot ROM bus, with address and data tenures, ALE and TS active.
18
boot_rom_size
Latched pin value at reset.
For non-muxed boot ROMs:
bit=0:8bit boot ROM data bus, 24bit max boot ROM address bus
bit=1:16bit boot ROM data bus, 16bit boot ROM address bus
For muxed boot ROMs:
boot ROM address is max 25 significant bits during address tenure.
bit=0:16bit ROM data bus
bit=1:32bit ROM data bus
bit=0:Normal mode. The SYS OSC clock input is multiplied up by the system PLL, then the
PLL VCO is divided down to produce internal clocks.
bit=1:The SYS OSC clock input is used directly, bypassing the system PLL. No multiplication
of the input frequency is performed, but the input frequency is divided to produce internal
clocks just as the system PLL VCO frequency would be. sys_pll_cfg_1 and sys_pll_cfg_0 are
ignored.
Large Flash mode is selected
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-17
Clocks and Power Management
Table 5-9. CDM Power On Reset Configuration Register Field Descriptions (continued)
Bit
Name
Description
19
boot_rom_swap
Latched pin value at reset.
bit=0:no byte lane swap, same
endian ROM image
bit=1:byte lane swap, different
endian ROM image
20
boot_rom_wait
Latched pin value at reset.
bit=0:4 PCI clocks of wait state
bit=1:48 PCI clocks of wait state
21
ppc_msrip
22
—
23
boot_rom_mg
Most/Graphic Mode is selected as BOOT mode
24
sys_pll_cfg_1
Latched pin value at reset.
bit=0:No operation.
bit=1:Internal System PLL frequency multiplication ratio specified by sys_pll_cfg_0 is doubled
(24x, 32x). No net effect on any internal clocks, except that PLL VCO runs twice as fast. Useful
in low frequency applications to keep VCO frequency (fvcosys) above min, see MPC5200B
Hardware Specification.
25
sys_pll_cfg_0
Latched pin value at reset.
bit=0: fsystem =16x SYS_XTAL_IN Frequency
bit=1: fsystem =12x SYS_XTAL_IN Frequency
26
xlb_clk_sel
27
ppc_pll_cfg_0
28
ppc_pll_cfg_1
29
ppc_pll_cfg_2
30
ppc_pll_cfg_3
31
ppc_pll_cfg_4
Latched pin value at reset.
microprocessor Boot Address/Exception table location.
bit=0:0000_0100 (hex)
bit=1:FFF0_0100 (hex)
Read Only. Do not write.
Latched pin value at reset.
bit=0:XLB_CLK= fsystem / 4
bit=1:XLB_CLK= fsystem / 8
e300 Core core pll configuration pins. See also Table 5-6
MPC5200B User’s Manual, Rev. 3
5-18
Freescale Semiconductor
Clocks and Power Management
5.5.1.3
CDM Bread Crumb Register
The CDM Bread Crumb Register is a 32-bit register that is not reset. Its purpose is to let firmware
designers leave some status code before entering a reset condition. Since this register is never reset, the
value written is available after the reset condition has ended. There is no additional functionality to this
register.
Address MBAR + 0x0208
0
1
2
3
4
R
7
8
9
10
11
12
13
14
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
—
—
—
—
R
CDM Bread Crumb Register (Never Reset)
W
Reset
6
CDM Bread Crumb Register (Never Reset)
W
Reset
5
—
—
—
—
—
—
—
—
—
—
—
Figure 5-6. CDM Bread Crumb Register
5.5.1.4
CDM Configuration Register
The CDM Configuration Register contains 3 bits that set IPB_CLK and PCI_CLK ratios.
Address MBAR + 0x020C
1
2
3
4
5
6
8
9
10
ddr_
mode
7
Reserved
Write 0
11
12
13
14
15
xlb_
clk_sel
0
R
Reserved
Write 0
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
Write 0
W
Reset
ipb_
clk_sel
Reset
0
0
0
0
0
0
0
1
Reserved
Write 0
0
0
0
0
pci_
clk_sel
0
0
0
1
Figure 5-7. CDM Configuration Register
Table 5-10. CDM Configuration Register Field Descriptions
Bit
Name
0–6
—
7
ddr_mode
Description
Reserved for future use. Write 0.
SDRAM Controller DDR memory mode, read-only.
bit=0:SDRAM Controller configured for SDR SDRAM (single data rate)
bit=1:SDRAM Controller configured for DDR SDRAM (double data rate)
This register location is a read-only status bit; write 0. The controlling register is in the SDRAM
Controller register map. In the CDM this bit determines the frequency and phase of memory read
clock.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-19
Clocks and Power Management
Table 5-10. CDM Configuration Register Field Descriptions (continued)
Bit
Name
Description
8–14
—
Reserved for future use. Write 0.
15
xlb_clk_sel
XLB Clock Frequency
bit=0:XLB CLK = fsystem /4
bit=1:XLB CLK = fsystem /8
This register location is a read-only status bit. The controlling register is the POR Configuration
register - cdm configuration register [26].
16–22
—
Reserved for future use. Write 0.
23
ipb_clk_sel
IPB Clock Select
bit=0:IPB CLK = XLB_CLK
bit=1:IPB CLK = XLB_CLK/2
24–29
—
30-31
pci_clk_sel
Reserved for future use. Write 0.
PCI Clock Select
00–PCI_CLK = IPB_CLK
01–PCI_CLK = IPB_CLK/2
10–PCI_CLK = XLB_CLK/4
See also Table 5-3 and Table 5-4.
NOTE
The clock ratio should only be changed if no module, which is clocked by
the IPB and/or PCI clock, is currently running. Suggestion is to change the
clock ratio during the boot time only.
MPC5200B User’s Manual, Rev. 3
5-20
Freescale Semiconductor
Clocks and Power Management
5.5.1.5
CDM 48MHz Fractional Divider Configuration Register
The CDM 48MHz Fractional Divider Configuration Register contains the control bits used in the 48MHz
fractional divider.
Address MBAR + 0x210
3
4
Reset
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
cfgd_p2_cntt
0
0
0
0
cfgd_p1_cnt
0
0
fd_en
Rsrvd
Write 0
cfgd_p3_cnt
Reserved
Write 0
Rsrvd
Write 0
Rsrvd
Write 0
Rsrvd
Write 0
R
W
6
0
Reserved
Write 0
W
Reset
5
ext_irda_
48mhz_en
2
ext_usb_
48mhz_en
1
ext_usb_
sync_en
0
R
0
0
cfgd_p0_cnt
0
0
0
Figure 5-8. CDM 48 MHz Fractional Divider Configuration Register
Table 5-11. CDM 48 MHz Fractional Divider Configuration Register Field Descriptions
Bit
Name
0–4
—
5
ext_usb_sync_en
Description
Reserved for future use. Write 0.
Enable the synchronization logic which synchronize the external ext_usb_48Mhz clock to
the internal clock system.
bit=1:ext USB 48MHz clock is synchronized to the internal clock system.
bit=0:ext USB 48MHz clock is not synchronized to the internal clock system.
6
ext_usb_48MHz_en
USB External 48MHz Clock Select
bit=1:USB 48MHz clock tree sourced from external clock from GPIO.
bit=0:USB 48MHz clock tree sourced from CDM Fractional Divider.
7
ext_irda_48MHz_en
IrDA (PSC6) External 48MHz Clock Select
bit=1:IRDA 48MHz clock tree sourced from external clock from GPIO.
bit=0:IRDA 48MHz clock tree sourced from CDM Fractional Divider.
8–14
—
15
fd_en
Reserved for future use. Write 0.
16
—
17–19
cgfd_p3_cnt[2:0]
20
—
21–23
cgfd_p2_cnt[2:0]
24
—
25–27
cgfd_p1_cnt[2:0]
010–fractional counter divide ratio fsystem/10
28
—
011–fractional counter divide ratio fsystem/11
29–31
cgfd_p0_cnt[2:0]
10X–fractional counter divide ratio fsystem/11
CDM 48MHz Fractional Divider Enable
bit=1:enable CDM Fractional Divider.
bit=0:disable CDM Fractional Divider.
These fields hold 4 phase divide ratios used by the fractional divider. The fields are
incompletely decoded; fsystem /11 is obtained with 3 values.
110–fractional counter divide ratio fsystem /6
111–fractional counter divide ratio fsystem/7
000–fractional counter divide ratio fsystem/8
001–fractional counter divide ratio fsystem /9
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-21
Clocks and Power Management
5.5.1.6
CDM Clock Enable Register
The CDM Clock Enable Register, or power management register, contains control bits that enable/disable
peripheral clocks. Unused peripherals can have their clock stopped, reducing power consumption.
Address MBAR + 0x0214
0
1
2
3
4
mem_
clk_en
pci_
clk_en
lpc_
clk_en
slt_
clk_en
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
psc2_
clk_en
psc1_
clk_en
psc6
clk_en
mscan_
clk_en
i2c_
clk_en
timer_
clk_en
gpio_
clk_en
15
psc3_
clk_en
14
psc4_
clk_en
13
psc5_
clk_en
12
bdlc_clk_
en
11
spi_
clk_en
10
usb_
clk_en
Reset
9
eth_
clk_en
W
8
ata_
clk_en
R
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reserved
Write 0
W
Reset
6
scom_
clk_en
R
5
Figure 5-9. CDM Clock Enable Register
Table 5-12. CDM Clock Enable Register Field Descriptions
Bit
Name
Description
0
—
Reserved for test. Write 0.
1–11
—
Reserved for future use. Write 0.
12
mem_clk_en
13
pci_clk_en
PCI Bus Clock Enable—controls PCI bus control module clocks
Note: PCI Arbiter and external PCI Bus clocks are not controlled by pci_clk_en.
14
lpc_clk_en
Local Plus Bus Clock Enable—controls LP bus control module clocks
15
slt_clk_en
Slice Timer Clock Enable—controls slice timer module clocks
16
scom_clk_en
BestComm Clock Enable—controls BestComm module clocks
17
ata_clk_en
ATA Clock Enable—controls ATA disk drive control module clocks
18
eth_clk_en
Ethernet Clock Enable—controls Ethernet Controller module clocks
19
usb_clk_en
Universal Serial Bus Clock Enable—controls USB module clock
20
spi_clk_en
SPI Clock Enable—controls SPI module clocks
21
bdlc_clk_en
BDLC Clock Enable—controls BDLC module clocks
22
psc5_clk_en
PSC5 Clock Enable—control clock to the PSC5 module
23
psc4_clk_en
PSC4 Clock Enable—control clock to the PSC4 module
24
psc3_clk_en
PSC3 Clock Enable—control clock to the PSC3 module
25
psc2_clk_en
PSC2 Clock Enable—control clock to the PSC2 module
26
psc1_clk_en
PSC1 Clock Enable—control clock to the PSC1 module
Memory Clock Enable—controls SDRAM Controller module clocks
Memory Controller IPB_CLK is not controlled by mem_clk_en.
MPC5200B User’s Manual, Rev. 3
5-22
Freescale Semiconductor
Clocks and Power Management
Table 5-12. CDM Clock Enable Register Field Descriptions (continued)
Bit
Name
Description
27
psc6_clk_en
PSC6 Clock Enable—control clock to the PSC6 module
28
mscan_clk_en
MSCAN Clock Enable—controls MSCAN module clocks
29
i2c_clk_en
30
timer_clk_en
Timer Clock Enable—controls timer module clocks
Note: 2 timers for wake-up mode do not have gated clocks.
31
gpio_clk_en
GPIO Clock Enable—controls some GPIO module clocks
Note: GPIO wake-up mode circuitry uses free running IPB_CLK
I2C Clock Enable—controls I2C module clocks
Note: An enable value of 1 enables the corresponding clock. An enable value of 0 disables corresponding clock.
5.5.1.7
CDM System Oscillator Configuration Register
This register contains the System Oscillator disable bit. The system oscillator is disabled if an external
clock source (not a crystal) drives the oscillator in package pin. The crystal oscillator pad cell is disabled
to reduce power consumption (~6mW for system oscillator).
Address MBAR + 0x0218
1
2
R
4
5
6
Reserved
Write 0
W
Reset
3
8
9
10
11
12
13
14
15
Reserved
Write 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
Write 0
W
Reset
7
sys_osc_
disable
0
0
0
0
0
0
0
0
0
0
Figure 5-10. CDM System Oscillator Configuration Register
Table 5-13. CDM System Oscillator Configuration Register Field Descriptions
Bit
Name
0–6
—
7
sys_osc_disable
Description
Reserved for future use. Write 0.
CDM System Oscillator Disable
bit=1:System Oscillator is disabled. External clock source is required.
bit=0:System Oscillator is enabled. 27–33MHz crystal is being used.
8–31
—
Reserved for future use. Write 0.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-23
Clocks and Power Management
5.5.1.8
CDM Clock Control Sequencer Configuration Register
This register contains the configuration that controls the CCS module. The CCS module lets MPC5200B
enter deep sleep power down mode (all clocks stopped).
Address MBAR + 0x021C
1
2
3
4
5
6
9
10
11
12
13
14
Reserved
Write 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
Write 0
W
Reset
15
ccs_qreq
_test
Reset
8
ccs_
sleep_en
Reserved
Write 0
W
7
ccs_osc_
sleep_en
0
R
0
0
0
0
0
0
0
0
1
Figure 5-11. CDM Clock Control Sequencer Configuration Register
Table 5-14. CDM Clock Control Sequencer Configuration Register Field Descriptions
Bit
Name
0–6
—
7
ccs_sleep_en
Description
Reserved for future use. Write 0.
CCS Module Enable
bit=1:CCS enabled. e300 Core QREQ signal triggers deep sleep cycle.
bit=0:CCS disabled and inactive. No deep sleep mode possible.
Note: This bit should only be set before the processor should go into deep sleep mode. And
it should be reset after wake up.
Note: It is not allowed to set this bit if a JTAG debugger or the nap mode should be used.
8–14
—
15
ccs_osc_sleep_en
Reserved for future use. Write 0.
CCS System Oscillator Disable Control
bit=1:CCS can disable System Oscillator in deep sleep mode.
bit=0:CCS cannot disable System Oscillator in deep sleep mode. Oscillator remains
active.
16–30
—
31
ccs_qreq_test
Reserved for future use. Write 0.
CCS Test bit—Used in CCS module functional simulation to simulate a QREQ signal.
bit=0:QREQ input to CCS forced active.
bit=1:QREQ input to CCS comes directly from e300 Core.
MPC5200B User’s Manual, Rev. 3
5-24
Freescale Semiconductor
Clocks and Power Management
5.5.1.9
CDM Soft Reset Register
This register contains 2 reset control bits.
Address MBAR + 0x0220
1
2
3
4
5
6
Reset
9
10
11
12
13
14
15
Reserved
Write 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
Write 0
W
Reset
8
cdm_soft
_reset
Reserved
Write 0
W
7
cdm_no_
ckstp_reset
0
R
0
0
0
0
0
0
0
0
0
Figure 5-12. CDM Soft Reset Register
Table 5-15. CDM Soft Reset Register Field Descriptions
Bit
Name
0–6
—
7
cdm_soft_reset
Description
Reserved for future use. Write 0.
CDM Soft Reset bit.
bit=0:requests CDM soft reset.
bit=1:CDM soft reset request inactive.
8–14
—
15
cdm_no_ckstp_reset
Reserved for future use. Write 0.
CDM No reset on checkstop.
bit=0:Checkstop assertion causes HRESET.
bit=1:Checkstop assertion does not cause HRESET.
16–31
—
Reserved for future use. Write 0.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-25
Clocks and Power Management
5.5.1.10
CDM System PLL Status Register
This register contains control and status bits of the CDM PLL lock detect module.
Address MBAR + 0x0224
2
4
5
6
8
9
10
11
12
13
14
15
Reserved
Write 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
pll_small_
lock_window
0
R
Reserved
Write 0
W
Reset
7
Reserved
Write 0
W
Reset
3
pll_lost
_lock
1
pll_lock
0
R
0
0
0
0
0
0
0
1
Reserved
Write 0
0
0
0
0
0
Figure 5-13. CDM System PLL Status Register
Table 5-16. CDM System PLL Status Register Field Descriptions
Bit
Name
0–6
—
7
pll_lock
Description
Reserved for future use. Write 0.
1
CDM System PLL Lock Detect—read-only status bit.
bit=1:CDM has detected System PLL lock condition.
bit=0:CDM has NOT detected System PLL lock condition.
8–14
—
15
pll_lost_lock
Reserved for future use. Write 0.
CDM System PLL Lock Lost—hardware can only set this bit, register write must clear bit.
bit=1:CDM detected loss of PLL lock after PLL lock has been achieved.
bit=0:CDM has not detected loss of PLL lock (state before PLL lock occurs).
16–22
—
23
pll_small_
lock_window
Reserved for future use. Write 0.
PLL Small Lock Window—pulse width used to detect rising edge of PLL FREF clock.
bit=1:lock window pulse width 2 fVCOsys clock periods.
bit=0:lock window pulse width 4 fVCOsys clock periods.
24–31
—
Reserved for future use. Write 0.
Note:
1. System PLL Lock Condition—256 System PLL FREF clock rising edges within PLL_Lock_Window (System PLL FFB rising edge). In
PLL bypass mode, Lock is active after 256 System Oscillator clock rising edges.
2. In current MPC5200B CDM the PLL Lock Circuitry is for information only. CDM does not wait for PLL lock to start clocks or use
PLL_LOST_LOCK as an interrupt source.
MPC5200B User’s Manual, Rev. 3
5-26
Freescale Semiconductor
Clocks and Power Management
5.5.1.11
PSC1 Mclock Configuration Register
This register controls the generation of the Mclk for PSC1. Before modify the register value the divider
must be disabled.
Address MBAR + 0x0228
0
1
2
3
4
5
6
R
W
Reset
9
10
11
12
13
14
15
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
Mclock
Enable
R
8
Reserved
Write 0
W
Reset
7
1
Reserved
Write 0
0
0
0
0
MclkDiv[8:0]
0
0
0
0
0
0
0
Figure 5-14. CDM PSC1 Mclock Configuration Register
Table 5-17. CDM PSC1 Mclock Configuration Register Field Descriptions
Bit
Name
0–15
—
16
Mclock Enable
Description
Reserved for future use. Write 0.
PSC1 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
17-22
—
23-31
MclkDiv[8:0]
Reserved for future use. Write 0.
The counter divide the fsystem frequency by MclkDiv+1. A value of 0x00 in this register turns
off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of 528MHz
would result in a Mclock rate of 528/8, or 66 MHz.
Note: fsystem clock is always 12 or 16 times the reference clock, sys_xtal_in, depending on
sys_pll_cfg_0 at reset.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-27
Clocks and Power Management
5.5.1.12
PSC2 Mclock Configuration Register
This register controls the generation of the Mclock for PSC2. Before modify the register value the divider
must be disabled.
Address MBAR + 0x022C
0
1
2
3
4
5
6
R
W
Reset
9
10
11
12
13
14
15
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
Mclock
Enable
R
8
Reserved
Write 0
W
Reset
7
1
Reserved
Write 0
0
0
0
0
MclkDiv[8:0]
0
0
0
0
0
0
0
Figure 5-15. CDM PSC2 Mclock Configuration Register
Table 5-18. CDM PSC2 Mclock Configuration Register Field Descriptions
Bit
Name
0–15
—
16
Mclock Enable
Description
Reserved for future use. Write 0.
PSC2 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
17-22
—
23-31
MclkDiv[8:0]
Reserved for future use. Write 0.
The counter divide the fsystem frequency by MclkDiv+1. A value of 0x00 in this register turns
off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of 528MHz
would result in a Mclock rate of 528/8, or 66 MHz.
Note: fsystem clock is always 12 or 16 times the reference clock, sys_xtal_in, depending on
sys_pll_cfg_0 at reset.
MPC5200B User’s Manual, Rev. 3
5-28
Freescale Semiconductor
Clocks and Power Management
5.5.1.13
PSC3 Mclock Configuration Register
This register controls the generation of the Mclock for PSC3. Before modify the register value the divider
must be disabled.
Address MBAR + 0x0230
0
1
2
3
4
5
6
R
W
Reset
9
10
11
12
13
14
15
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
Mclock
Enable
R
8
Reserved
Write 0
W
Reset
7
1
Reserved
Write 0
0
0
0
0
MclkDiv[8:0]
0
0
0
0
0
0
0
Table 5-19. CDM PSC3 Mclock Configuration Register
Table 5-20. CDM PSC3 Mclock Configuration Register Field Descriptions
Bit
Name
0–15
—
16
Mclock Enable
Description
Reserved for future use. Write 0.
PSC3 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
17-22
—
23-31
MclkDiv[8:0]
Reserved for future use. Write 0.
The counter divide the fsystem frequency by MclkDiv+1. A value of 0x00 in this register turns
off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of 528MHz
would result in a Mclock rate of 528/8, or 66 MHz.
Note: fsystem clock is always 12 or 16 times the reference clock, sys_xtal_in, depending on
sys_pll_cfg_0 at reset.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
5-29
Clocks and Power Management
5.5.1.14
PSC6 (IrDA) Mclock Configuration Register
This register controls the generation of the Mclock for PSC6. Before modify the register value the divider
must be disabled.
Address MBAR + 0x0234
0
1
2
3
4
5
6
R
W
Reset
9
10
11
12
13
14
15
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
—
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
Mclock
Enable
R
8
Reserved
Write 0
W
Reset
7
1
Reserved
Write 0
0
0
0
0
MclkDiv[8:0]
0
0
0
0
0
0
0
Figure 5-16. CDM PSC6 Mclock Configuration Register
Table 5-21. CDM PSC6 Mclock Configuration Register Field Descriptions
Bit
Name
0–15
—
16
Mclock Enable
Description
Reserved for future use. Write 0.
PSC6 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
17-22
—
23-31
MclkDiv[8:0]
Reserved for future use. Write 0.
The counter divide the fsystem frequency by MclkDiv+1. A value of 0x00 in this register turns
off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of 528MHz
would result in a Mclock rate of 528/8, or 66 MHz.
Note: fsystem clock is always 12 or 16 times the reference clock, sys_xtal_in, depending on
sys_pll_cfg_0 at reset.
MPC5200B User’s Manual, Rev. 3
5-30
Freescale Semiconductor
Chapter 6
e300 Processor Core
6.1
Overview
The following sections are contained in this document:
• MPC5200B e300 Processor Core Functional Overview
• e300 Core Reference Manual
• Not Supported e300 Core Features
6.2
MPC5200B e300 Processor Core Functional Overview
The MPC5200B integrates a e300 processor core based on, and compatible with, the 603e which is a
PowerPC compliant microprocessor. The e300 core is completely embedded, as its address, data, and
control signals are not visible external to MPC5200B. The e300 core has the following features:
• 603e series PowerPC compliant processor core
• Dual Issue, superscalar architecture
• 16K instruction cache, 16K data cache
• Double precision FPU
• Instruction and data MMU
• Power management modes:
— Nap
— Doze
— Sleep
— Deep Sleep
• Standard & critical interrupt capability
For additional information on the capabilities and features of the e300 core, refer to 603e user
documentation.
The e300 processor has a 32-bit address/64-bit data bus referred to as the 60X Local Bus (XLB). This bus
is the main system connecting all internal mastering and slave modules. In addition to the e300 core, the
USB host controller, PCI controller (as target) and BestComm controller can master the XLB.
The e300 core fetches 32-bit instructions (one word), two words at a time. After power-on reset, initial
boot instructions are fetched from the LocalPlus bus, with CS0 active. The processor can execute code
from the local bus or from the SDRAM controller. To facilitate high speed execution, boot code is typically
copied from a Flash or ROM device attached to the LocalPlus bus, to SDRAM. The e300 core can execute
code from the on-chip SRAM.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
6-1
e300 Processor Core
The e300 core has memory mapped access to all MPC5200B resources including:
• all on-chip programming registers
• all on-chip FIFOs and memories
• external SDRAM
• internal SRAM
• PCI-controlled address space
• external disk drive control register space (via PIO mode), etc.
When a master device wants access to the XLB, a request is made to the XLB Arbiter. When access is
granted, the mastering device controls the XLB during the subsequent address tenure and data tenure.
Bursting is supported on the XLB. Critical Word First protocol is employed when the e300 core attempts
to fill its address and data caches. Pipelining and cache coherency support (XLB address snooping) has
been added to the MPC5200B to improve performance.
MPC5200B use the version 1.4 of the e300 core. The Processor version register (PVR) is 0x80822014.
The e300 core has a System version register (SVR). The SVR numbers of MPC5200B are:
Table 6-1. SVR Values
6.3
Revision
SVR
M08A
80110020
M62C
80110021
e300 Core Reference Manual
A complete specification for the e300 core implementation used on the MPC5200B is obtained through a
collection of documentation.
• PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors,
Rev. 2: MPCFPE32B/AD
• G2 PowerPC Core Reference Manual, Rev. 1: G2CORERM/D
The programming environments manual provides information about resources defined by the PowerPC
architecture that are common to PowerPC processors. Implementation variances relative to Rev. 2 of the
Programming Environments Manual are available in the G2 Core Reference Manual.
The G2 Core Reference Manual can be obtained from the Freescale (formerly Motorola) Literature
Distribution center at http://e-www.freescale.com. Click on the Documentation link to proceed to the
Semiconductor Documentation Library. In the documentation form window, select “Reference Manual”
and set the matching pages option button to “All”. An alphabetical list of reference manuals will appear
and the G2 core document ID is ‘G2CORERM/D’. From this line entry, you may order hard copies of the
G2 Core Reference Manual or download a PDF copy of the manual.
MPC5200B User’s Manual, Rev. 3
6-2
Freescale Semiconductor
e300 Processor Core
6.4
6.4.1
Not Supported e300 Core Features
Not Supported Instruction
The e300 core supports two instructions that are not available by the MPC5200B. These two instructions
are eciowx and ecowx. The execution of both instructions will generate a TEA signal on XLB. This will
cause a machine check exception or a checkstop.
6.4.2
Not Supported XLB Parity Feature
The e300 core supports an address and data parity error detection for the XL bus. This feature is not
supported by the MPC5200B. The core input signals core_ap_in [0:3] are pulled-down to 0 and the core
input signals core_dp_in [0:7] are pulled-up to 1. Enabling of the address or data parity error check by the
HID0 [EBA, EBD] bits will generate a machine check exception or a checkstop depending on the HID0
[EMCP] bit.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
6-3
e300 Processor Core
MPC5200B User’s Manual, Rev. 3
6-4
Freescale Semiconductor
Chapter 7
System Integration Unit (SIU)
7.1
Overview
The following sections are contained in this document:
• Interrupt Controller, includes:
— Interrupt Controller Registers
• General Purpose I/O (GPIO), includes:
— GPIO Standard Registers (MBAR + 0x0B00)
— WakeUp GPIO Registers (MBAR + 0x0C00)
• General Purpose Timers (GPT), includes:
— GPT Registers (MBAR + 0x0600)
• Slice Timers, includes:
— SLT Registers (MBAR + 0x700)
• Real-Time Clock, includes:
— RTC Interface Registers (MBAR + 0x800)
NOTE
Watchdog timer functions are included in the GPT section.
The System Integration Unit (SIU) controls and support the functions listed above.
7.2
Interrupt Controller
A highly configurable Interrupt Controller directs all interrupt sources to the following e300 core interrupt
pins:
• core_cint — critical interrupt
• core_smi — system management interrupt
• core_int — standard interrupt
7.2.1
Block Description
The Interrupt Controller MUXes a variety of interrupt sources to the limited interrupt pins on the e300
core. The interrupt sources and their descriptions are summarized in Table 7-1.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-1
System Integration Unit (SIU)
Table 7-1. Interrupt Sources
Source
No.
Description
External IRQ Interrupts
4
Can be programmed as level or edge sensitive. Provides interrupt requests to Interrupt
Controller for external devices.
Slice Timers
2
“Tick” generators. Suitable for operating system update tick.
General Timers
8
Generates interrupt in Input Capture mode or Internal Timer mode. Timers 6 and 7 can
interrupt from NAP/DOZE power-down.
BestComm and
Peripherals
19
Various peripherals are priority programmed and encoded into HI or LO interrupt to the
Interrupt Controller. BestComm Controller interrupt is connected to HI interrupt.
RTC
2
Stopwatch and periodic
WakeUp
8
These are special GPIO pins with WakeUP capability. There are 8 such pins funneled into
one interrupt. The source module is gpio_wkup.
GPIO
8
GPIO pins with simple interrupt capability (not available in power down mode). The source
module is gpio_std.
WatchDog Timer
0
No vector handler, generates SRESET output indication.
Total
51
Table 7-1 does not include machine-check bus errors or transaction handshaking. e300 core interrupt pins
given in Section 7.2.1.1, “Machine Check Pin—core_mcp” through Section 7.2.1.3, “Standard
Interrupt—core_int” show e300 core interrupt priority.
7.2.1.1
Machine Check Pin—core_mcp
NOTE
The core_mcp pin is not used. Bus errors occur on the XL bus, thus
generating an internal machine-check exception, or are reflected as a normal
interrupt from the offending source module.
Internally, bus errors (TEA, APE, DPE, etc.) cause a machine check exception to a single exception vector.
This pin allows additional, external to the e300 core, interrupts of the same type, but is not connected in this
device.
7.2.1.2
System Management Interrupt—core_smi
The core_smi is a e300 core pin for high priority interrupts. Table 7-2 defines the interrupts.
Table 7-2. System Management Interrupt Pin Interrupts
Interrupt
Description
Enables
The MSR[ee] bit must be set to enable interrupts at this e300 core pin. The MSR[ee] bit is
automatically cleared when an interrupt occurs. Therefore, the exception handler must re-set this bit
when interrupt is cleared.
Recovery/Status
Recovery is highly dependant on system and software design. Where multiple sources are tied to the
same interrupt, a status register is provided to distinguish the interrupting source.
MPC5200B User’s Manual, Rev. 3
7-2
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-2. System Management Interrupt Pin Interrupts (continued)
Interrupt
Description
Timing
Assertion of this interrupt is persistent (i.e., interrupt remains until cleared). If other interrupts are
pending when first interrupt is cleared, the core_smi pin should remain asserted for handling once the
current exception handler re-sets the MSR[ee] bit.
Connections
Standard external and internal interrupts can be connected to this high priority interrupt. Slice timer 1
is a dedicated connection.
7.2.1.3
Standard Interrupt—core_int
Identical to core_smi, but of lower priority. This interrupt is shared by a variety of internal low priority
interrupts such as GPIO and RTC functions. Some programmable connection are provided. Table 7-3 gives
a summary of the interrupt pins. Figure 7-2 shows the interrupt sources and e300 core pins.
Table 7-3. e300 core Interrupt Pins Summary
Pin
Description
Sources
To Enable
Timing
core_mcp
Machine Check Pin
Tied inactive
—
—
core_cint
Critical Interrupt
BestComm HI, IRQ0,
Slice Timer 0, CCS WakeUp
MSR[ce]
Persistent
(remains until cleared)
core_smi
System Management
Interrupt
Slice Timer 1,
Programmable interrupts
MSR[ee]
Persistent
core_int
Standard Interrupt
Programmable interrupts
MSR[ee]
Persistent
IRQ[0]
Slice Timer 0
CCS Wkup
core_cint
BestComm
HI_int
Peripherals
(ATA/PCI etc.)
LO_int
Slice Timer 1
core_smi
IRQ[1:3]
core_int
SIU interrupts
(RTC/GPIO/WKUP/TMRS)
Indicates it can be masked in controller.
Indicates priority encoding programmability.
Figure 7-1. Interrupt Sources and e300 core Interrupt Pins
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-3
System Integration Unit (SIU)
IRQ[0:3] Interrupt Requests
IRQ[0:3] provides interrupt requests to Interrupt Controllers for external devices such as:
• Graphics controllers
• PCI interrupt controller
• ATAs
• Transport de-multiplexers
• External I/O devices, etc.
These interrupts are programmable as edge or level sensitive. See Figure 7-1.
7.2.2
Interface Description
Timers
(IC, OC,
PWM)
Slice
Timers
4
e300 Core
4
core_mcp
0
core_cint
1
core_smi
Real Time
Clock
8
8
core_int
GPIO/Std
Main Interrupt
Controller
GPIO/WakeUp
IRQ0
cint_ded
Peripheral 1
IRQ1
Peripheral 2
IRQ2
Peripheral 3
IRQ3
Peripheral 4
Peripheral 5
Encoder
smi_ded
int_ded
Grouper
Encoder
programmable inputs
Grouper
Encoder
HI
Peripheral 6
LO
Peripheral …
XLB Arbiter
BestComm
Controller
NOTE:
1. Grouper and Encoder functions imply programmability in software.
Figure 7-2. Interrupt Controller Routing Scheme
MPC5200B User’s Manual, Rev. 3
7-4
Freescale Semiconductor
System Integration Unit (SIU)
7.2.3
Programming Note
Under specific conditions, the Interrupt Controller may not support nested interrupts. The Interrupt
Controller may prevent the assertion of a core_cint interrupt if a core_int or a core_smi is pending.
Similarly, the Interrupt Controller may block a core_smi if a core_int is pending. If the e300 core received
the core_cint assertion during an core_int or core_smi assertion, it would preempt the current interrupt
service routine and process the Critical Interrupt Service routine immediately. Since the MPC5200B
Interrupt Controller postpones the core_cint assertion until after a current core_int or core_smi is finished,
there can be a delay before the 603e receives and services Critical Interrupt Sources.
The interrupt Controller always supports nested interrupt if the Critical Interrupt sources come from IRQ0,
Slice TImer 0 or the wakeup logic. There is a difference when the critical source comes from HI_int
(Peripheral Interrupt Group). As shown in Figure 7-2, each Peripheral Interrupt can assert a HI_int or
LO_int condition. But only one Peripheral Interrupt can be active at the time, so the Interrupt Controller
has not the ability to simultaneously assert both HI_int and LO_int. Therefore, the peripheral 2 which
generated by default a core_int (LO_int) interrupt will prevent a BestComm Interrupt to generate a
core_cint (HI_int) interrupt.
In addition, a Peripheral Interrupt directed to a core_cint can be prevented by a pending core_smi interrupt.
Each Peripheral Interrupt (LO_int) can be programmed to cause a core_smi by setting the Main4_pri msb.
Once again, the Interrupt Controller does not has the ability to simultaneously generate the HI_int and
LO_int. Then, a Peripheral Interrupt, which generates a core_smi, prevents any Peripheral Interrupts to
assert a core_cint.
Similarly, the Interrupt Controller can activate only one Main Interrupt source at the time. Main4 source
is the collection of all LO_int Peripheral Interrupts. The Main4_pri can be programmed in order to
generate a core_smi or a core_int. As result, a Peripheral Interrupt that causes a core_int will prevent all
other Main Interrupt sources to generate a core_smi. Although the Interrupt Controller does not exhibit the
correct behavior, the e300 core always completes the core_int before treating the core_smi. In this case,
the CPU does not authorize nested interrupt at the exception if the ISR set the 603e’s MSR[EE] to support
nested interrupt (core_smi and core_int).
In order to guaranty the assertion of the core_cint when a core_int is pending, the ISR needs to force the
re-evaluation of the Peripheral Interrupt condition by writing “1” to the Peripheral Status Encoded Pse
msb. The ISR has to repeatedly set this bit since the interrupt events are indeterministic. Moreover, the
Peripheral Interrupt sources directed to core_cint needs to have their priorities to be higher than the LO_int
Peripheral Interrupt sources. The Interrupt Controller always activates first the pending interrupt having
the highest priority. Like for the Peripheral Interrupt Group, the ISR needs to set the Main Status Encoded
MSe msb to force re-evaluation of the Main Interrupt Condition and each Main Interrupt Priority needs to
be properly programmed.
7.2.4
Interrupt Controller Registers
The Interrupt Controller uses 13 32-bit registers. These registers are located at an offset from MBAR of
0x0500. Register addresses are relative to this offset. Therefore, the actual register address is: MBAR +
0x0500 + register address.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-5
System Integration Unit (SIU)
Hyperlinks to the Interrupt Controller registers are provided below:
• ICTL Peripheral Interrupt Mask Register (0x0500)
• ICTL Peripheral Priority and HI/LO Select 1 Register (0x0504)
• ICTL Peripheral Priority and HI/LO Select 2 Register (0x0508)
• ICTL Peripheral Priority and HI/LO Select 3 Register (0x050C)
• ICTL External Enable and External Types Register (0x0510)
• ICTL Critical Priority and Main Interrupt Mask Register (0x0514)
• ICTL Main Interrupt Priority and INT/SMI Select 1 Register (0x0518)
• ICTL Main Interrupt Priority and INT/SMI Select 2 Register (0x051C)
• ICTL PerStat, MainStat, CritStat Encoded Register (0x0524)
• ICTL Critical Interrupt Status All Register (0x0528)
• ICTL Main Interrupt Status All Register (0x052C)
• ICTL Peripheral Interrupt Status All Register (0x0530)
• ICTL Bus Error Status Register (0x0538)
• ICTL Main Interrupt Emulation All Register (0x0540)
• ICTL Peripheral Interrupt Emulation All Register (0x0544)
• ICTL IRQ Interrupt Emulation All Register (0x0544)
7.2.4.1
ICTL Peripheral Interrupt Mask Register
Address MBAR + 0x0500
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Reserved
Per_mask
W
Reset
8
Per_mask
W
Reset
7
1
1
1
1
1
1
1
1
0
0
0
0
0
Figure 7-3. ICTL Peripheral Interrupt Mask Register
MPC5200B User’s Manual, Rev. 3
7-6
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-4. ICTL Peripheral Interrupt Mask Register Field Descriptions
Bits
Name
Description
—
Per_mask
Bits 0:23—To mask/accept individual peripheral interrupt sources. This masking is in addition to
interrupt enables, which may exist in each source module.
0 Accept interrupt from source module.
1 Ignore interrupt from source module.
Important—See Note 1.
0
Per_mask
BestComm interrupt source
1
Per_mask
Peripheral 1 (PSC1)
2
Per_mask
Peripheral 2 (PSC2)
3
Per_mask
Peripheral 3 (PSC3)
4
Per_mask
Peripheral 4 (PSC6)
5
Per_mask
Peripheral 5 (Ethernet)
6
Per_mask
Peripheral 6 (USB)
7
Per_mask
Peripheral 7 (ATA)
8
Per_mask
Peripheral 8 (PCI Control module)
9
Per_mask
Peripheral 9 (PCI SC Initiator RX)
10
Per_mask
Peripheral 10 (PCI SC Initiator TX)
11
Per_mask
Peripheral 11 (PSC4)
12
Per_mask
Peripheral 12 (PSC5)
13
Per_mask
Peripheral 13 (SPI modf)
14
Per_mask
Peripheral 14 (SPI spif)
15
Per_mask
Peripheral 15 (I2C1)
16
Per_mask
Peripheral 16 (I2C2)
17
Per_mask
Peripheral 17 (CAN1)
18
Per_mask
Peripheral 18 (CAN2)
19
Per_mask
Reserved
20
Per_mask
Reserved
21
Per_mask
Peripheral 21 (XLB Arbiter)
22
Per_mask
Peripheral 22 (BDLC)
23
Per_mask
Peripheral 23 (BestComm LocalPlus)
24:31
—
Reserved
Note:
1. Setting these bits prevents an interrupt being presented to the e300 core pins for the masked sources. Encoded status indications in
the ICTL Perstat, MainStat, CritiStat Encoded Register are suppressed, but the binary all status bits (PSa in ICTL Peripheral Interrupt
Status All Register) are active as long as the source module is presenting an active input to the Interrupt Controller.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-7
System Integration Unit (SIU)
7.2.4.2
ICTL Peripheral Priority and HI/LO Select 1 Register
Address MBAR + 0x0504
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Per0_pri
Per1_pri
Per2_pri
Per3_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Per4_pri
Per5_pri
Per6_pri
Per7_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-4. ICTL Peripheral Priority and HI/LO Select 1 Register
Table 7-5. CTL Peripheral Priority and HI/LO Select 1 Register Field Descriptions
Bits
Name
Description
—
Per[x]_pri
Priority encoding is done using 4 configuration bits per input source. Each group of 4bits controls
the source priority in relation to other peripheral sources. The most significant bit (msb) of each
config nibble is called the HI/LO or bank bit.
If this bit is high it implies not only a high priority, but causes this interrupt source to assert a HI
interrupt condition. Under most circumstances this creates a Critical Interrupt assertion to the e300
core. See Note 1.
Peripherals with identical priority settings (either zero or non-zero) are default prioritized with lower
peripheral has higher priority. In other words, Per1 has a default priority higher than Per2.
0:3
Per0_pri
Peripheral 0 = BestComm interrupt (fixed as highest peripheral)
4:7
Per1_pri
Peripheral 1 = PSC1 interrupt source
8:11
Per2_pri
Peripheral 2 = PSC2
12:15
Per3_pri
Peripheral 3 = PSC3
16:19
Per4_pri
Peripheral 4 = PSC6
20:23
Per5_pri
Peripheral 5 = Ethernet
24:27
Per6_pri
Peripheral 6 = USB
28:31
Per7_pri
Peripheral 7 = ATA
Note:
1. Per0_pri, associated with the BestComm interrupt source, is not programmable and always has the highest peripheral priority and
always results in a HI interrupt condition to the Interrupt Controller. These bits are writable and readable, but have no effect on controller
operation.
MPC5200B User’s Manual, Rev. 3
7-8
Freescale Semiconductor
System Integration Unit (SIU)
7.2.4.3
ICTL Peripheral Priority and HI/LO Select 2 Register
Address MBAR + 0x0508
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Per8_pri
Per9_pri
Per10_pri
Per11_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Per12_pri
Per13_pri
Per14_pri
Per15_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-5. ICTL Peripheral Priority and HI/LO Select 2 Register
Table 7-6. ICTL Peripheral Priority and HI/LO Select 2 Register Field Descriptions
Bits
Name
Description
—
Per[x]_pri
Identical to Peripheral_Priority 1 Register, but related to peripheral interrupt sources 8 through 15.
All bits are programmable and significant.
0:3
Per8_pri
Peripheral 8 = PCI Control module
4:7
Per9_pri
Peripheral 9 = PCI SC Initiator RX
8:11
Per10_pri
Peripheral 10 = PCI SC Initiator TX
12:15
Per11_pri
Peripheral 11 = PSC4
16:19
Per12_pri
Peripheral 12 = PSC5
20:23
Per13_pri
Peripheral 13 = SPI modf
24:27
Per14_pri
Peripheral 14 = SPI spif
28:31
Per15_pri
Peripheral 15 = I2C1
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-9
System Integration Unit (SIU)
7.2.4.4
ICTL Peripheral Priority and HI/LO Select 3 Register
Address MBAR + 0x050C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Per16_pri
Per17_pri
Per18_pri
Per19_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Per20_pri
Per21_pri
Per22_pri
Per23_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-6. ICTL Peripheral Priority and HI/LO Select 3 Register
Table 7-7. ICTL Peripheral Priority and HI/LO Select 3 Register Field Descriptions
Bits
Name
Description
—
Per[x]_pri
Identical to Peripheral_Priority 2 register, but related to peripheral interrupt sources 16–21. All bits
are programmable and significant.
0:3
Per16_pri
Peripheral 16 = I2C2
4:7
Per17_pri
Peripheral 17 = CAN1
8:11
Per18_pri
Peripheral 18 = CAN2
12:15
Per19_pri
Reserved
16:19
Per20_pri
Reserved
20:23
Per21_pri
Peripheral 21 = XLB Arbiter
24:27
Per22_pri
Peripheral 22 = BDLC
28:31
Per23_pri
Peripheral 23 = BestComm LocalPlus
MPC5200B User’s Manual, Rev. 3
7-10
Freescale Semiconductor
System Integration Unit (SIU)
7.2.4.5
ICTL External Enable and External Types Register
Address MBAR + 0x0510
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ECLR(4)
Etype0
Etype1
Etype2
Etype3
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
MEE
EENA(4)
Reserved
CEb
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-7. ICTL External Enable and External Types Register
Table 7-8. ICTL External Enable and External Types Register Field Descriptions
Bits
Name
Description
0:3
—
—
ECLR[x]
4
ECLR0
IRQ[0], write 1 to clear
5
ECLR1
IRQ[1], write 1 to clear
6
ECLR2
IRQ[2], write 1 to clear
7
ECLR3
IRQ[3], write 1 to clear
8:9
Etype0
These bits control how the Interrupt Controller interprets the IRQ[0] input pin.
00 = Input is level sensitive and active hi
01 = Input is edge sensitive, rising edge active”
10 = Input is edge sensitive, falling edge active”
11 = Input is level sensitive, and active low”
10:11
Etype1
Same as above, but for the IRQ[1] input pin.
12:13
Etype2
Same as above, but for the IRQ[2] input pin.
14:15
Etype3
Same as above, but for the IRQ[3] input pin.
16:18
—
19
MEE
—
EENA[x]
20
EENA0
IRQ[0]
21
EENA1
IRQ[1]
Reserved
These bits clear external IRQ interrupt indications. When an IRQ input is configured as an
edge-sensitive input, the Interrupt Controller must be notified that the specific interrupt has been
serviced. Software must write 1 to the appropriate bit position to clear the interrupt indication. ECLR
bits are always read as 0 (i.e., they do not contain status).
Reserved—unused bits, writing has no effect, always read as 0.
Master External Enable—clearing this bit masks all IRQ input transitions (including status
indications).
Individual enable bits for each IRQ input pin. Setting the associated bit lets the related IRQ pin
generate interrupts. In either case, status indications in PSa and CSa (ICTL Peripheral Interrupt
Status All Register) are active.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-11
System Integration Unit (SIU)
Table 7-8. ICTL External Enable and External Types Register Field Descriptions (continued)
Bits
Name
22
EENA2
IRQ[2]
23
EENA3
IRQ[3]
24:30
—
31
CEb
7.2.4.6
Description
Reserved
Critical Enable—a special control bit, which if set, directs critical interrupt sources to the normal
e300 core Interrupt pin. This is for system programmer who prefers to handle all interrupts in a single
ISR.
The status operation remains unchanged, it is necessary to parse Critical Status information prior
to Normal Status information to detect critical interrupt sources routed to the normal interrupt pin.
ICTL Critical Priority and Main Interrupt Mask Register
Address MBAR + 0x0514
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R
Main_
Mask
Crit0_pri
Crit1_pri
Crit2_pri
Crit3_pri
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Reserved
W
Reset
15
R
Main_Mask
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-8. ICTL Critical Priority and Main Interrupt Mask Register
Table 7-9. ICTL Critical Priority and Main Interrupt Mask Register Field Descriptions
Bits
Name
Description
0:1
Crit0_pri
Priority encoding value for Critical Interrupt 0, IRQ[0] input pin.
There are four Critical Interrupt sources that can be uniquely prioritized (a higher Priority value
creates a higher priority, i.e. a value of 3 is the highest priority value). In the case of identical
priority value, the lower numbered interrupt source has priority. This makes IRQ[0] the highest
default priority (being the lowest numbered source).
2:3
Crit1_pri
Priority encoding value for Slice Timer 0 interrupt source. Hard-wired as critical interrupt source
number 1, it has the second highest default priority.
4:5
Crit2_pri
Priority encoding value for HI_int interrupt source. Hard-wired as critical interrupt source
number 2. It is programmable such that any peripheral source can be directed to it, and thus get
maximum priority service.
6:7
Crit3_pri
Priority encoding value for CCS WakeUp source. Hard-wired as critical interrupt source
number 3.
8:14
—
Reserved
MPC5200B User’s Manual, Rev. 3
7-12
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-9. ICTL Critical Priority and Main Interrupt Mask Register Field Descriptions (continued)
Bits
Name
Description
—
Main_Mask[x]
To mask/accept individual main interrupt sources (as opposed to peripheral or critical interrupt
sources). This masking is in addition to interrupt enables, which may exist in each source
module.
0 Default. Accept interrupt from source module.
1 Ignore interrupt from source module.
Take care if masking LO_int, which is a collection of multiple Peripheral sources in a single
presentation. Masking LO_int essentially prevents any LO Peripheral from generating an
interrupt, even when those interrupts are enabled (i.e., unmasked) in Per_Mask, Reg0.
Important—See Note 1.
15
Main_Mask0
Slice Timer 1, which is hardwired to SMI interrupt output. See Note 2.
—
—
16
Main_Mask1
IRQ[1] (IRQ[1] input pin interrupt)
17
Main_Mask2
IRQ[2] (IRQ[2] input pin interrupt)
18
Main_Mask3
IRQ[3] (IRQ[3] input pin interrupt)
19
Main_Mask4
LO_int (source programmable from Peripheral ints)
20
Main_Mask5
RTC_pint (Real time clock, periodic interrupt)
21
Main_Mask6
RTC_sint (Real time clock, stopwatch and alarm interrupt)
22
Main_Mask7
GPIO_std (collected GPIO interrupts, non-WakeUp)
23
Main_Mask8
GPIO_wkup (collected WakeUp interrupts)
24
Main_Mask9
TMR0 (internal Timer resource)
25
Main_Mask10
TMR1 (internal Timer resource)
26
Main_Mask11
TMR2 (internal Timer resource)
27
Main_Mask12
TMR3 (internal Timer resource)
28
Main_Mask13
TMR4 (internal Timer resource)
29
Main_Mask14
TMR5 (internal Timer resource)
30
Main_Mask15
TMR6 (internal Timer resource)
31
Main_Mask16
TMR7 (internal Timer resource)
Interrupt sources below are bank/priority programmable (in Reg6 and Reg7).
Note:
1. Setting these bits prevents an interrupt being presented to the masked sources e300 core pins. Encoded status indications (MSe in
Reg9) are therefore suppressed, but the binary all status bits (MSa in RegB) are active as long as the source module is presenting an
active input to the Interrupt Controller. Masking IRQ[1:3], is redundant with External ENA bits in Reg4, but both masks are applied.
2. Slice Timer 1 is hard-coded and neither bank nor priority adjustable.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-13
System Integration Unit (SIU)
7.2.4.7
ICTL Main Interrupt Priority and INT/SMI Select 1 Register
Address MBAR + 0x0518
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Main1_pri
Main2_pri
Main3_pri
Main4_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Main5_pri
Main6_pri
Main7_pri
Main8_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-9. ICTL Main Interrupt Priority and INT/SMI Select 1 Register
Table 7-10. ICTL Main Interrupt Priority and INT/SMI Select 1 Register Field Descriptions
Bits
Name
Description
0:3
Main1_pri
Main interrupt source 1 (IRQ[1]) priority encoding value.
All four bits are used to set a priority value (higher value equals higher priority). MSbit is also used
as a bank bit to direct this interrupt source to SMI interrupt output (if bank = 1), or to normal INT
interrupt output (if bank = 0).
For interrupt sources set at the same priority value, default priority is the lower numbered interrupt
has higher priority. This means main source 1 has a higher default priority than main source 2. See
Note 1.
4:7
Main2_pri
Main interrupt source 2 (IRQ[2] input pin) priority encoding value.
8:11
Main3_pri
Main interrupt source 3 (IRQ[3] input pin) priority encoding value.
12:15
Main4_pri
Main interrupt source 4 (LO_int) priority encoding value. LO_int is a collection of any Peripheral
Interrupts directed to this interrupt source. Peripheral interrupts sources are directed to either
LO_int, or to the critical interrupt source HI_int.
16:19
Main5_pri
Main interrupt source 5 (RTC_periodic) priority encoding value.
20:23
Main6_pri
Main interrupt source 6 (RTC_stopwatch and RTC_alarm) priority encoding value.
24:27
Main7_pri
Main interrupt source 7 (GPIO_std) priority encoding value. GPIO_std is a collection of all simple
interrupt GPIO pins enabled for Interrupt operation.
28:31
Main8_pri
Main Interrupt source 8 (GPIO_wkup) priority encoding value.
GPIO_wkup is a collection of all enabled WakeUp capable GPIO sources. WakeUp interrupt
sources also operate in normal powered-up modes so all GPIO interrupt sources are represented
by main interrupt sources 7 and 8 (also see Timer GPIOs in Reg7).
Note:
1. Main source 0 (Slice Timer 1) is not listed, it is fixed as both the highest priority main interrupt and to generate an SMI interrupt output
only.
MPC5200B User’s Manual, Rev. 3
7-14
Freescale Semiconductor
System Integration Unit (SIU)
7.2.4.8
ICTL Main Interrupt Priority and INT/SMI Select 2 Register
Address MBAR + 0x051C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Main9_pri
Main10_pri
Main11_pri
Main12_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Main13_pri
Main14_pri
Main15_pri
Main16_pri
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-10. ICTL Main Interrupt Priority and INT/SMI Select 2 Register
Table 7-11. ICTL Main Interrupt Priority and INT/SMI Select 2 Register Field Descriptions
Bits
Name
Description
0:3
Main9_pri
Main interrupt source 9 (TMR0) priority encoding value.
All 4bits are used to set a priority value (higher value equals higher priority). The msb is also used
as a bank bit to direct this interrupt source to SMI interrupt output (if bank = 1), or to normal INT
interrupt output (if bank = 0).
For interrupt sources set at the same priority value, default priority is the lower numbered interrupt
has higher priority. This means main source 9 has a higher default priority than main source 10.
Timer 0 is one of eight internal timer resources that can be configured as input capture, output
compare, or PWM output. As such, there is an I/O pin associated with each timer. The timer can
use this pin as GPIO, in which case the internal timer function becomes available. These eight
timers complete the MPC5200B GPIO structure. All potential GPIO interrupt sources are
represented by main sources 7, 8, and 9–16.
4:7
Main10_pri
Main interrupt source 10 (TMR1) priority encoding value.
8:11
Main11_pri
Main interrupt source 11 (TMR2) priority encoding value.
12:15
Main12_pri
Main interrupt source 12 (TMR3) priority encoding value.
16:19
Main13_pri
Main interrupt source 13 (TMR4) priority encoding value.
20:23
Main14_pri
Main interrupt source 14 (TMR5) priority encoding value.
24:27
Main15_pri
Main interrupt source 15 (TMR6) priority encoding value. See Note 1.
28:31
Main16_pri
Main interrupt source 16 (TMR7) priority encoding value. See Note 1.
Note:
1. This timer has WakeUp functionality and therefore can provide a WakeUp interrupt source.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-15
System Integration Unit (SIU)
7.2.4.9
ICTL Perstat, MainStat, CritStat Encoded Register
Address MBAR + 0x0524
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
PSe
Reserved
MSe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
CSe
Reserved
CEbSh
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-11. ICTL PerStat, MainStat, CritStat Encoded Register
Table 7-12. ICTL PerStat, MainStat, CritStat Encoded Register Field Descriptions
Bits
Name
0:1
—
2:7
PSe
8:9
—
10:15
MSe
16:20
—
Description
Reserved
Peripheral Status Encoded—makes a singular indication of the current peripheral interrupt (6bits
indicating 1 of 24 possible peripheral interrupts).
The msb operates as a flag bit and is set if any peripheral interrupt is currently being presented by
the Interrupt Controller (e.g., if peripheral interrupt source 0 is current, then this register reads as
0x20). Normally it would not be necessary to clear this status register since all peripheral interrupt
sources are level sensitive.
Once an interrupt source negates at the input of the controller, the new input condition is
re-evaluated without software intervention. However, if ISR does not clear the interrupt source (at
the source module), then the controller is locked on the current interrupt and cannot re-evaluate the
input condition (possibly to detect the presence of a higher priority interrupt). Therefore, ISR can
force a re-evaluation of the input condition by writing 1 to the msb of PSe. This sticky-bit clear
operation is optional and can be used at the discretion of the ISR writer.
The encoded value cross-reference to a specific source is described in ICTL Peripheral Interrupt
Mask Register and re-stated in ICTL Peripheral Interrupt Status All Register. In all cases, the
peripheral status encoded value converts to a single source module (i.e., no additional status
parsing is required at the Interrupt Controller).
Reserved
Main Status Encoded—makes a singular indication of the current main interrupt (6 bits indicating 1
of 17 possible main interrupts).
The msb operates as a flag bit, as described above. The msb can also be written to 1 to force a
re-evaluation of the main interrupt sources.
The cross-reference of the encoded value to a particular source is described in Reg5 (main mask)
and re-stated in ICTL Main Status All Register.
All MSe values convert to a single source module, EXCEPT Main source 4 (LO_int), which indicates
a peripheral source is active. In this case it is necessary to parse the PSe to determine which
peripheral source is active. See Note 1.
Reserved
MPC5200B User’s Manual, Rev. 3
7-16
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-12. ICTL PerStat, MainStat, CritStat Encoded Register Field Descriptions (continued)
Bits
Name
Description
21:23
CSe
Critical Status Encoded—makes a singular indication of the current critical interrupt (3bits indicating
1 of 4 possible interrupts).
The msb operates as a Flag bit, as described above. This msb can also be written to 1 to force a
re-evaluation of the critical interrupt sources.
00 IRQ input pin is the source. See Note 2.
01 Slice Timer 0 is the source.
10 HI_int is the source. See Note 3.
11 CCS module is the source. WakeUp from deep-sleep. See Note 4.
24:30
—
31
CEbSh
Reserved
Critical Enable bar Shadow bit—this is a special bit that shadows the setting programmed into ICTL
External Enable and External Types Register. This bit indicates whether Critical interrupt sources
have or have not been directed to the normal INT e300 core pin.
If Critical interrupts are directed to INT (CEbSh = 1), to detect higher priority interrupt sources, INT
ISR must always parse the CSe prior to MSe or PSe. All other processing remains the same.
This shadow bit is provided here so a single read to this register can obtain all necessary information
to make the interrupt source determination.
Note:
1. For Main sources 1, 2, and 3 that represent IRQ[1:3] respectively, if the IRQ pin is set as edge sensitive, it is REQUIRED that the MSe
flag bit be cleared (i.e., written to 1) or the appropriate ECLR bit in ICTL External Enable and External Types Register be set to clear
this interrupt indication. Only one method should be used, not both (this limit is only true for multiple edge-sensitive IRQ inputs).
2. For IRQ[0] set as edge sensitive, it is REQUIRED that either the CSe flag bit be cleared (i.e., written to 1) or the ECLR[0] bit in ICTL
External Enable and External Types Register be set to clear this interrupt indication. You can do both if desired, and you
can do it regardless of the IRQ[0] interrupt type.
3. This indicates a peripheral source programmed for HI bank priority is the source. It is necessary to parse the PSe value to determine
the peripheral source module.
4. For recovery from deep-sleep mode, it is necessary to acknowledge this WakeUp interrupt by writing 1 to the msb of this field (CSe).
Only then does the CCS module release it's power-down internal signal and let MPC5200B operate normally.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-17
System Integration Unit (SIU)
7.2.4.10
ICTL Critical Interrupt Status All Register
Address MBAR + 0x0528
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
CSa
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-12. ICTL Critical Interrupt Status All Register
Table 7-13. ICTL Critical Interrupt Status All Register Field Descriptions
Bits
Name
Description
0:3
—
—
CSa[x]
4
CSa0
indicates IRQ[0] interrupt
5
CSa1
Slice Timer 0 interrupt
6
CSa2
HI_int interrupt
7
CSa3
WakeUp from deep-sleep mode (CCS) interrupt
8:31
—
Reserved
Critical Interrupt Status All—Indicates all pending interrupts, including the currently active interrupt
(if any). CSa is binary, showing each active interrupt input in its corresponding bit position. See
Note 1.
Number in parenthesis indicates equivalent encoded value in CSe, ICTL PerStat, MainStat, CritStat
Encoded Register.
Reserved
Note:
1. No direct mask register is defined for critical interrupts. However, IRQ[0] can be masked by the MEE bit in Reg4, in which case CSa
status does not occur. If only the EENA[0] bit in ICTL External Enable and External Types Register is cleared, then CSa
status occurs, but controller does not assert a e300 core interrupt.
MPC5200B User’s Manual, Rev. 3
7-18
Freescale Semiconductor
System Integration Unit (SIU)
7.2.4.11
ICTL Main Interrupt Status All Register
Address MBAR + 0x052C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
MSa
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
MSa
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-13. ICTL Main Interrupt Status All Register
Table 7-14. ICTL Main Interrupt Status All Register Field Descriptions
Bits
Name
Description
0:14
—
—
MSa[x]
15
MSa0
Slice_Timer 1 (SMI interrupt only)
16
MSa1
IRQ[1] input pin
17
MSa2
IRQ[2] input pin
18
MSa3
IRQ[3] input pin
19
MSa4
LO_int (some Peripheral source)
20
MSa5
RTC_periodic interrupt
21
MSa6
RTC_stopwatch interrupt
22
MSa7
GPIO std interrupt
23
MSa8
GPIO WakeUp interrupt
24
MSa9
TMR0 interrupt
25
MSa10
TMR1 interrupt
26
MSa11
TMR2 interrupt
27
MSa12
TMR3 interrupt
28
MSa13
TMR4 interrupt
29
MSa14
TMR5 interrupt
30
MSa15
TMR6 interrupt
31
MSa16
TMR7 interrupt
Reserved
Main Interrupt Status All. Indicates all pending interrupts. Is binary, showing each active interrupt in its
corresponding bit position. See Note 1.
Number in parenthesis indicates equivalent encoded value in MSe, Reg9.
Note:
1. All main interrupt sources are directly maskable in Main_Mask, ICTL Critical Priority and Main Interrupt Mask Register. If masked in
Main_Mask, status information still shows in MSa. However, if interrupt is not enabled at the source module (i.e., in source module
registers) the Interrupt Controller cannot observe or record status information for that interrupt.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-19
System Integration Unit (SIU)
7.2.4.12
ICTL Peripheral Interrupt Status All Register
Address MBAR + 0x0530
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
PSa
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
PSa
PSa21
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-14. ICTL Peripheral Interrupt Status All Register
Table 7-15. ICTL Peripheral Interrupt Status All Register Field Descriptions
Bits
Name
Description
0:7
—
—
PSa[x]
Peripheral Interrupt Status All. Indicates all pending interrupts. Is binary, showing each active
interrupt in its corresponding bit position. See Note 1.
Number in parenthesis indicates equivalent encoded value in PSe, ICTL PerStat, MainStat, CritStat
Encoded Register.
8
PSa23
BestComm LocalPlus
9
PSa22
BDLC
10
PSa0
BestComm interrupt source
11
PSa1
PSC1
12
PSa2
PSC2
13
PSa3
PSC3
14
PSa4
PSC6
15
PSa5
Ethernet
16
PSa6
USB
17
PSa7
ATA
18
PSa8
PCI Control module
19
PSa9
PCI SC Initiator Rx
20
PSa10
PCI SC Initiator Tx
21
PSa11
PSC4
22
PSa12
PSC5
23
PSa13
SPI modf
24
PSa14
SPI spif
25
PSa15
I2C1
Reserved
MPC5200B User’s Manual, Rev. 3
7-20
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-15. ICTL Peripheral Interrupt Status All Register Field Descriptions (continued)
Bits
Name
Description
26
PSa16
I2C2
27
PSa17
CAN1
28
PSa18
CAN2
29:30
—
31
PSa21
Reserved
XLB Arbiter
Note:
1. These interrupts are directly maskable by ICTL Peripheral Interrupt Mask Register. However, PSa status occurs regardless of
Per_Mask setting, as long as the source module interrupt is enabled in the source module registers.
7.2.4.13
ICTL Peripheral Interrupt Status All Register
Address MBAR + 0x0538
0
1
2
3
4
5
6
7
8
BE1
BE0
9
10
11
12
13
14
15
R
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-15. ICTL Bus Error Status Register
Table 7-16. ICTL Bus Error Status Register Field Descriptions
Bits
Name
Description
0:5
—
6
BE1
Bus Error 1—Indicates write attempt to read-only register, clear with a write to 1.
7
BE2
Bus Error 0—Indicates access to unimplemented register, clear with a write to 1.
8:31
—
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-21
System Integration Unit (SIU)
7.2.4.14
ICTL Main Interrupt Emulation All Register
Address MBAR + 0x0540
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
MEa
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
MEa
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 7-16. ICTL Main Interrupt Emulation All Register
Table 7-17. ICTL Main Interrupt Emulation All Register Field Descriptions
Bits
Name
0:14
—
—
MEa[x]
Description
Reserved
This register provides a way for software to emulate the assertion of a particular Main/SIU interrupt.
The actual interrupt is the OR or the normal interrupt source and each of these test register bits. The
order is exactly the same as the MSa in
ICTL Main Interrupt Status All Register.
The MEa[x] bits ARE masked by the Main_Mask setting, so they operate as
much as possible as the real interrupt source. Even the IRQ sources, which may be programmed as
edge sensitive, will react just like the pin when emulated here with test bit assertion/negation. One
exception is LO-int, which if asserted here, will NOT create a corresponding Peripheral Status
indication.
If relying on MEa [x] assertion/negation to emulate and test an ISR routine it is
important to disable all source modules so that real source interrupts will not disturb
the test generated interrupt.
15
MEa0
Slice_Timer 1 (SMI interrupt only)
16
MEa1
IRQ[1] input pin
17
MEa2
IRQ[2] input pin
18
MEa3
IRQ[3] input pin
19
MEa4
LO_int (some Peripheral source)
20
MEa5
RTC_periodic interrupt
21
MEa6
RTC_stopwatch interrupt
22
MEa7
GPIO std interrupt
23
MEa8
GPIO WakeUp interrupt
24
MEa9
TMR0 interrupt
25
MEa10
TMR1 interrupt
26
MEa11
TMR2 interrupt
27
MEa12
TMR3 interrupt
28
MEa13
TMR4 interrupt
29
MEa14
TMR5 interrupt
30
MEa15
TMR6 interrupt
31
MEa16
TMR7 interrupt
MPC5200B User’s Manual, Rev. 3
7-22
Freescale Semiconductor
System Integration Unit (SIU)
7.2.4.15
ICTL Peripheral Interrupt Emulation All Register
Address MBAR + 0x0544
0
1
2
R
4
5
7
8
9
10
11
12
13
14
15
PEa
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
PEa
W
Reset
6
Reserved
W
Reset
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PEa21
0
Figure 7-17. ICTL Peripheral Interrupt Emulation All Register
Table 7-18. ICTL Peripheral Interrupt Emulation All Register Field Descriptions
Bits
Name
Description
0:7
—
—
PEa[x]
This register provides a way for software to emulate the assertion of a particular Peripheral interrupt.
The actual interrupt is the OR or the normal interrupt source and each of these test register bits.
The order is exactly the same as the PSa in ICTL Peripheral Interrupt Status All Register. The
PEa[x] bits ARE masked by the Per_Mask setting, so they operate as much as possible as the real
interrupt source. Test assertion of a peripheral source will cause HI-int or LO-int indications which
will be reflected in the Main or Critical status registers. If relying on PEa[x] assertion/negation to
emulate and test an ISR routine it is important to disable all source modules so that real source
interrupts will not disturb the test generated interrupt.
8
PEa23
BestComm LocalPlus
9
PEa22
BDLC
10
PEa0
BestComm interrupt source
11
PEa1
PSC1
12
PEa2
PSC2
13
PEa3
PSC3
14
PEa4
PSC6
15
PEa5
Ethernet
16
PEa6
USB
17
PEa7
ATA
18
PEa8
PCI Control module
19
PEa9
PCI SC Initiator Rx
20
PEa10
PCI SC Initiator Tx
21
PEa11
PSC4
22
PEa12
PSC5
23
PEa13
SPI modf
24
PEa14
SPI spif
25
PEa15
I2C1
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-23
System Integration Unit (SIU)
Table 7-18. ICTL Peripheral Interrupt Emulation All Register Field Descriptions (continued)
Bits
Name
Description
26
PEa16
I2C2
27
PEa17
CAN1
28
PEa18
CAN2
29:30
—
31
PEa21
7.2.4.16
Reserved
XLB Arbiter
ICTL IRQ Interrupt Emulation All Register
Address MBAR + 0x0548
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
IRQEa
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-18. ICTL IRQ Interrupt Emulation All Register
Table 7-19. ICTL IRQ Interrupt Emulation All Register Field Descriptions
Bits
Name
Description
0:3
—
—
IRQEa[x]
4
IRQEa0
IRQ[0] input pin emulation
5
IRQEa1
IRQ[1] input pin emulation
6
IRQEa2
IRQ[2] input pin emulation
7
IRQEa3
IRQ[3] input pin emulation
8:31
—
Reserved
This register provides a way for software to emulate the assertion of a particular external interrupt
pin. The actual interrupt is the OR of the normal interrupt source and each of these IRQEa[x] bits.
This register represents the four IRQ inputs. This register is redundant with IICTL Main Interrupt
Emulation All Register for IRQ1-3 but is the only source to emulate IRQ0. It provides a single register
with which to test and develop an ISR for the external interrupt sources. Each bit operates as if it
were the pin itself, i.e. edge sensitive operation would require multiple test writes to create the
emulation of a pulsing input. See Note 1
Reserved
Note:
1. The emulation is only possible if the IRQ pins are externally pulled down. Otherwise the OR between the external pin values and the
IRQEa[x] bits is whole the time one.
MPC5200B User’s Manual, Rev. 3
7-24
Freescale Semiconductor
System Integration Unit (SIU)
7.3
General Purpose I/O (GPIO)
There are a total of 56 possible GPIO pins on the MPC5200B. Virtually all of these pins are shared with
alternate hardware functions. Therefore, GPIO availability is entirely dependant on the peripheral set a
particular application requires.
There are 5 basic types of GPIO pins, controlled by separate register groupings, and in some cases,
different register modules:
• 24 “Simple” GPIO, controlled in the standard GPIO register module.
• 8 “Output Only” GPIO, controlled in the standard GPIO register module.
• 8 “Interrupt” GPIO, controlled in the standard GPIO register module.
• 8 “Wakeup” GPIO, controlled in the WakeUp GPIO register module.
• 8 “Timer” GPIO, controlled in the General Purpose Timer register module.
There is a hierarchy of GPIO functionality. Higher function GPIO can be programmed to operate at any
lower functional level. The hierarchy, from lowest to highest, is as follows:
• Output Only—As the name suggests, these GPIO cannot be programmed as Inputs. As outputs,
they can be programmed to emulate an Open-Drain output.
• Simple—Same as Output Only, but with additional capability to be programmed as inputs, with a
corresponding Input Value register that can be read by software.
• Interrupt—Same as Simple, but with additional capability of generating an Interrupt to the CPU
during normal powered-up mode. The Interrupt Type can be programmed as edge
(any/rising/falling/2nd edge) sensitive. These GPIO are sometimes referred to as “Simple
Interrupt”.
• Wakeup—Same as Interrupt, but with additional capability of generating an Interrupt during Deep
Sleep mode. Includes Interrupt Type registers and has an extra enable bit to distinguish between
Simple Interrupt or WakeUp Interrupt operation.
• Timer GPIO—Operates with Simple GPIO capability, but can generate CPU Interrupts if
configured as Input Capture timer mode. These Timer GPIO have special capabilities and
limitations, which are described in Section 7.4, “General Purpose Timers (GPT)”. Timer GPIO
does not fit cleanly into the GPIO functional hierarchy concept, and should therefore be considered
as a unique GPIO function.
GPIO functionality is available on an I/O pin only if the pin is enabled for GPIO usage in the
Section 7.3.2.1.1, “GPS Port Configuration Register”. The GPIOPCR register controls the top level
pin-muxing, which sets an I/O pin’s usage between some hardware function(s) and GPIO. If the pin is
available for GPIO, the associated GPIO registers must be enabled and configured by software to complete
the GPIO operation for that specific pin. If a Timer GPIO is consumed by an alternate hardware function,
it is still available to work as an internal General Purpose Timer (GPT).
Simple GPIO are controlled by a group of registers in the Standard GPIO module. They are organized in
relation to the multi-function hardware port groupings. For example, you will see a GPIO field named
PSC1 (4 bits) that corresponds to the 4 Simple GPIO available on the PSC1 port group. There is also a
WakeUp GPIO on the PSC1 port. However, this pin, as GPIO, would be controlled by a separate register
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-25
System Integration Unit (SIU)
in the Wakeup GPIO module. Even though the pins are physically scattered throughout the multi-function
port groups, register control groupings exist for the:
• 8 Wakeup GPIO pins
• 8 Interrupt GPIO pins, and
• 8 Output-Only GPIO pins.
Only Simple GPIO register groupings correspond to the physical pin groupings.
Table 7-20 lists all 56 GPIO pins.
Table 7-20. GPIO Pin List (Sheet 1 of 2)
GPIO PIN
Alternate Functionality
Interrupt
WakeUp
TIMER_0
Timer_GPIO/ATA/CAN2
Only as Timer
No
TIMER_1
Timer_GPIO/ATA/CAN2
Only as Timer
No
TIMER_2
Timer_GPIO/SPI
Only as Timer
No
TIMER_3
Timer_GPIO/SPI
Only as Timer
No
TIMER_4
Timer_GPIO/SPI
Only as Timer
No
TIMER_5
Timer_GPIO/SPI
Only as Timer
No
TIMER_6
Timer_GPIO
Only as Timer
Yes (Timer IC)
TIMER_7
Timer_GPIO
Only as Timer
Yes (Timer IC)
PSC1_0
UART1/AC971/CODEC1
No
No
PSC1_1
UART1/AC971/CODEC1
No
No
PSC1_2
UART1/AC971
No
No
PSC1_3
UART1/AC971/CODEC1
No
No
PSC1_4
UART1/AC971/CODEC1
Yes
Yes
PSC2_0
UART2/AC972/CODEC2/CAN1
No
No
PSC2_1
UART2/AC972/CODEC2/CAN1
No
No
PSC2_2
UART2/AC972/CAN2
No
No
PSC2_3
UART2/AC972/CODEC2/CAN2
No
No
GPIO_WKUP_1(PSC2_4)
UART2/AC972/CODEC2
Yes
Yes
GPIO_PSC3_0
USB2/CODEC3/UART3
No
No
GPIO_PSC3_1
USB2/CODEC3/UART3
No
No
GPIO_PSC3_2
USB2/CODEC3/UART3
No
No
GPIO_PSC3_3
USB2/CODEC3/UART3
No
No
GPIO_SINT_0(PSC3_4)
USB2/UART3
Yes
No
GPIO_SINT_1(PSC3_5)
USB2
Yes
No
GPIO_PSC3_6
USB2/SPI
No
No
GPIO_PSC3_7
USB2/SPI
No
No
MPC5200B User’s Manual, Rev. 3
7-26
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-20. GPIO Pin List (Sheet 2 of 2)
GPIO PIN
Alternate Functionality
Interrupt
WakeUp
GPIO_SINT_2(PSC3_8)
USB2/SPI
Yes
No
GPIO_WKUP_2(PSC3_9)
USB2/SPI
Yes
Yes
GPIO_USB_0
USB1 (OE)
No
No
GPIO_USB_1
USB1 (PORTPWR)/UART5 (TXD)
No
No
GPIO_USB_2
USB1 (SPEED)/UART5 (RTS)
No
No
GPIO_USB_3
USB1 (SUSPEND)/UART5 (CTS)
No
No
GPIO_SINT_3(USB)
USB1 (OvrCrnt)
Yes
No
GPIO_ETHO_0(out only)
Ethernet
No
No
GPIO_ETHO_1(out only)
Ethernet/UART5
No
No
GPIO_ETHO_2(out only)
Ethernet/USB2/UART5
No
No
GPIO_ETHO_3(out only)
Ethernet/USB2/UART4
No
No
GPIO_ETHO_4(out only)
Ethernet/USB2/J1850
No
No
GPIO_ETHO_5(out only)
Ethernet/USB2/UART4
No
No
GPIO_ETHO_6(out only)
Ethernet/USB2
No
No
GPIO_ETHO_7(out only)
Ethernet/USB2
No
No
GPIO_ETHI_0
Ethernet/UART5
No
No
GPIO_ETHI_1
Ethernet/UART5
No
No
GPIO_ETHI_2
Ethernet
No
No
GPIO_ETHI_3
Ethernet
No
No
GPIO_SINT_4(ETH)
Ethernet/USB2/J1850
Yes
No
GPIO_SINT_5(ETH)
Ethernet/USB2/UART4
Yes
No
GPIO_SINT_6(ETH)
Ethernet/USB2/UART4
Yes
No
GPIO_SINT_7(ETH)
Ethernet/USB2/UART4
Yes
No
GPIO_WKUP_3(ETH)
Ethernet
Yes
Yes
GPIO_IRDA_0
IRDA/UART6/Codec6
No
No
GPIO_IRDA_1
IRDA(and/or USB)/UART6/Codec6
No
No
GPIO_WKUP_4(IRDA)
IRDA/UART6/Codec6
Yes
Yes
GPIO_WKUP_5(IRDA)
IRDA/UART6/Codec6
Yes
Yes
GPIO_WKUP_6
Dedicated GPIO Pin/SDRAM CS1
Yes
Yes
GPIO_WKUP_7
Dedicated GPIO Pin/LocalPlus Most/Graphics mode TSIZ1
Yes
Yes
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-27
System Integration Unit (SIU)
7.3.1
GPIO Pin Multiplexing
Figure 7-19 shows the GPIO/Generic MUX cell.
Alternate Func 1
IN
Pin MUX Logic
OUT
BC
Enabled
Alternate Func 2
IN
OUT
BC
Enabled
I/O Cell
TIMER
MultiFunction
I/O
OUT
IN
BC
Enabled
GPIO/d/W
ODconfig
IN
Awake
OUT
BC
Enabled
Priority
Output Enable
Logic
Interrupt for WakeUp supported GPIO pins only
Note:
1. Open-Drain Emulation is supported on the GPIO function.
2. Pin MUX Logic is controlled by the Port Configuration Register and supersedes any individual GPIO register
programming.
Figure 7-19. GPIO/Generic MUX Cell
7.3.1.1
PSC1 (UART1/AC97/CODEC1)
The PSC1 port has 5 pins with hardware support for:
• CODEC
• UART (4 pins consumed)
• UARTe (expanded with carrier detect input–5 pins consumed)
• AC97
Unused pins can serve as simple GPIOs, with one available as a WakeUp input. For use as AC97, this
WakeUp GPIO becomes available. A special mode is available in which the CD input for UART use can
be unused. This makes a WakeUp GPIO available on this port. CODEC usage makes one simple GPIO
available. Use of this port for AC97 consumes all 5 pins and leaves no GPIO available.
Refer to the port-mapping illustrations Figure 2-4.
MPC5200B User’s Manual, Rev. 3
7-28
Freescale Semiconductor
System Integration Unit (SIU)
7.3.1.2
PSC2 (CAN1/2/UART2/AC97/CODEC2)
The PSC2 port has 5 pins with hardware support for:
• CAN
• CODEC
• UART (4 pins consumed)
• UARTe (expanded with carrier detect input–5 pins consumed)
• AC97
Unused pins can serve as simple GPIOs, with one available as a WakeUp input. For use as AC97, this
WakeUp GPIO becomes available. A special mode is available in which the CD input for UART use can
be unused. This makes a WakeUp GPIO available on this port. CODEC usage makes one simple GPIO
available. Use of this port for AC97 consumes all 5 pins and leaves no GPIO available.
Refer to the port-mapping illustrations Figure 2-5.
7.3.1.3
PSC3 (USB2/CODEC3/SPI/UART3)
The PSC3 port has 10pins with hardware support for:
• CODEC
• Expanded UART (5 pins consumed)
• SPI (4 pins consumed)
• USB secondary port (10 pins consumed)
SPI can simultaneously exist, with no pins leftover for GPIO. Similarly, CODEC or UART can exist with
SPI leaving no leftover pins. Unless, CD input on UART is designated unused, in which case a WakeUp
GPIO becomes available. Any unused pins are available for related RS232 GPIO functionality.
Refer to the port-mapping illustrations Figure 2-6.
7.3.1.4
USB1/RST_CONFIG
This is a 10-bit port dedicated to primary USB. GPIO becomes available only if the USB function is not
used. When this occurs, the following GPIO becomes available:
• 4 Simple GPIO
• 1 Interrupt GPIO
Other pins on this port serve as Reset Configuration inputs.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-29
System Integration Unit (SIU)
7.3.1.5
Ethernet/USB2/UART4/5/J1850/RST_CONFIG
This port consists of 8 output data pins and 10 control pins (in ethernet mode). For GPIO grouping these
are the EthO and EthI ports, respectively. The output-only pins (EthO) are also used for input reset
configuration data, therefore these pins must act as output only in all other cases. No peripheral is allowed
to overdrive the reset configuration pull-up/pull-down settings. The 8 GPIOs on the EthO port are
therefore output-only, and only available if the pin is otherwise unused (beyond reset config).
NOTE
The ethernet pin, MDIO, is actually an I/O. However, there should be no
danger of an external chip driving this pin during power-up.
This port is configured such that 7-wire Ethernet and a secondary USB port can exist simultaneously. This
configuration makes available 1 GPIO WakeUp pin.
Full Ethernet consumes all 18 pins, unless the optional MDIO and MDC pins are specified as unused. In
this case, 2 Output Only GPIO are available.
Meanwhile, there are other cases because many pins can be used for UART, J1850. Please Refer to the
port-mapping illustrations for details.
USB stand-alone usage leaves available:
• 2 Output Only GPIO
• 4 Simple GPIO
• 1 WakeUp GPIO
7-wire Ethernet stand-alone leaves available:
• 6 Output Only GPIO
• 4 Interrupt GPIO
• 1 WakeUp GPIO
1850 stand-alone leaves available:
• 7 Output Only GPIO
• 4 Simple GPIO
• 3 Interrupt GPIO
• 1 WakeUp GPIO
Total GPIO available on this port is:
• 8 Output Only GPIO
• 4 Simple GPIO
• 4 Interrupt GPIO
• 1 WakeUp GPIO
MPC5200B User’s Manual, Rev. 3
7-30
Freescale Semiconductor
System Integration Unit (SIU)
7.3.1.6
PSC6
The PSC6 port has 4 pins, which includes:
• 2 Simple GPIO
• 2 WakeUp GPIO
Hardware functions available are:
• IRDA
— 3 pins with clock input
— 2 pins with internal clock
• UART (4 pins)
• Codec (4 pins)
The IRDA clock pin can be used as a Input USB clock and is separately programmable for this use.
• If unused, the IRDA Receive pins are available as WakeUp GPIO.
• If unused, the IRDA Transmit pin and the Clock pin are available as Simple GPIO.
7.3.1.7
I2C
There are 2 I2C ports consisting of 2 pins each. Although no GPIO is available on these pins, they can be
alternately programmed as CAN1 pins (on I2C1) and/or as the ATA Chip Selects (on I2C2). If the
alternate function is specified, the associated I2C port is consumed and unavailable.
7.3.1.8
GPIO Timer Pins
The GPIO Timer port consists of 8 pins. Each pin is driven by a internal timer module, which can do either
of the following:
• drive the pin in Output Compare mode and Pulse Width Modulation mode, or
• monitor the pin as input in Input Capture mode.
Additionally, the timer module can operate the pin as a Simple GPIO. This GPIO control is handled in the
Timer Module register, see Section 7.4.4, “GPT Registers”. If the pin is controlled as a GPIO, then the
Timer Module timer can be used as an internal CPU timer.
The Timer pins can be reconfigured for alternate functionality in the Port Configuration Register, as
follows:
• Timer pins 0 and 1 can operate as CAN2 Tx/Rx or ATA Chip Selects.
• Timer pins 2–5 can operate as the SPI port.
• Timer pins 6 and 7 are dedicated as Timer GPIO and have no alternate function.
Although the Timer as GPIO only operates to the Simple GPIO level, Interrupt capability can be achieved
by configuring the Timer for Input Capture mode.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-31
System Integration Unit (SIU)
7.3.1.9
Dedicated GPIO Port
There is a dedicated GPIO port group that consists of 2 pins. Both pins operate at the WakeUp GPIO level.
They are designated:
• GPIO_WKUP_6
• GPIO_WKUP_7
However, GPIO_WKUP_6 is not dedicated and can be programmed to operate as a second SDRAM
memory chip select. As such, this pin is connected to the Memory Vdd supply. For Dual Data Rate
memory, the GPIO_WKUP_6 pin is driven at the reduced 2.5V level.
If not used as a memory chip select, the GPIO_WKUP_6 pin serves as a memory voltage compatible
GPIO.
7.3.2
GPIO Programmer’s Model
The GPIO programmer’s model contains 3 separate register sets (or modules), each at different offsets
from MBAR. These register sets are:
1. GPIO Standard Registers. Output Only, Simple, and Interrupt GPIO are controlled by registers
within this module. There are 3 register groupings for individual control of each of the named
GPIO types.
2. WakeUp GPIO Registers. WakeUp GPIO are controlled by this register set
3. GPT Registers. Timer functions and Timer GPIO are controlled by this module.
All GPIO functionality is dependent on the Port Configuration Register (PCR) setting. The PCR is the first
register in the GPIO Standard Module. This register controls the Pin MUX Logic. Therefore, the PCR also
controls the physical routing of MPC5200B I/O pins to and from internal logic. The PCR is expected to
be configured early in the boot process and set to a static value that supports the given peripheral set of a
specific application.
NOTE
The PCR is not accessible during Deep Sleep mode.
MPC5200B User’s Manual, Rev. 3
7-32
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1
GPIO Standard Registers
The GPIO Standard Register set has separate registers for each GPIO type.
• Simple
• Output Only
• Interrupt
These registers are at an offset of MBAR + 0x0B00.
The GPIO Standard Register set uses 16 32-bit registers. These registers are located at an offset from
MBAR of 0x0B00. Register addresses are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0B00 + register address.
Hyperlinks to the GPIO pin type registers are provided below:
• GPS Port Configuration Register (0x0B00)
• GPS Simple GPIO Enables Register (0x0B04)
• GPS Simple GPIO Open Drain Type Register (0x0B08)
• GPS Simple GPIO Data Direction Register (0x0B0C)
• GPS Simple GPIO Data Output Values Register (0x0B10)
• GPS Simple GPIO Data Input Values Register (0x0B14)
• GPS GPIO Output-Only Enables Register (0x0B18)
• GPS GPIO Output-Only Data Value Out Register (0x0B1C)
• GPS GPIO Simple Interrupt Enable Register (0x0B20)
• GPS GPIO Simple Interrupt Open-Drain Emulation Register (0x0B24)
• GPS GPIO Simple Interrupt Data Direction Register (0x0B28)
• GPS GPIO Simple Interrupt Data Value Out Register (0x0B2C)
• GPS GPIO Simple Interrupt Enable Register (0x0B30)
• GPS GPIO Simple Interrupt Types Register (0x0B34)
• GPS GPIO Simple Interrupt Master Enable Register (0x0B38)
• GPS GPIO Simple Interrupt Status Register (0x0B3C)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-33
System Integration Unit (SIU)
7.3.2.1.1
GPS Port Configuration Register
0
1
CS1
LPTZ
Address MBAR + 0x0B00
2
0
0
0
16
17
18
3
4
5
6
7
CS7
CS6
0
0
0
0
0
0
0
0
0
0
0
0
0
19
20
21
22
23
24
25
26
27
28
29
30
31
W
Reset
R PCI_
W DIS
Reset
0
ALTs
USB
_SE
0
USB
0
ATA
PSC3
0
0
0
9
IR_USB_CLK
R
8
0
0
11
12
13
IRDA
Rsvd
0
10
0
15
Ether
PSC2
0
14
Rsvd
0
0
PSC1
0
0
0
Figure 7-20. GPS Port Configuration Register
Table 7-21. GPS Port Configuration Register Field Descriptions (Sheet 1 of 3)
Bit
Name
Description
0
CS1
Memory Chip Select bit
0 gpio_wkup_6
1 mem_cs1 (second SDRAMC chip select) on gpio_wkup_6 pin
1
LPTZ
LocalPlus non-muxed TSIZ bit
0 gpio_wkup_7 and test_sel_1
1 TSIZ 1 on gpio_wkup_7 and TSIZ 2 on test_sel_1
2:3
ALTs
Alternatives, see Note 2
00 No Alternatives: CAN1/2 on PSC2 according to PSC2 setting.
SPI on PSC3 according to PSC3 setting.
01 ALT CAN position: CAN1 on I2C1, CAN2 on Tmr0/1 pins, see Note 1
10 ALT SPI position: SPI on Tmr2/3/4/5 pins, see Note 2
11 Both on ALT
4
CS7
0 Interrupt GPIO on PSC3_5 (see note 6)
1 CS7 on PSC3_5
5
CS6
0 Interrupt GPIO on PSC3_4 (see note 6)
1 CS6 on PSC3_4
6:7
ATA
Advanced Technology Attachment
00 No ATA chip selects, csb_4/5 used as normal chip select
01 ATA cs0/1 on csb_4/5
10 ATA cs0/1 on i2c2 clk/io
11 ATA cs0/1 on Tmr0/1, see Note 1
8
IR_USB_CLK
Infrared USB Clock
0 IrDA/USB 48MHz clock generated internally, pin is GPIO
1 IrDA/USB clock is sourced externally, input only
MPC5200B User’s Manual, Rev. 3
7-34
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-21. GPS Port Configuration Register Field Descriptions (Sheet 2 of 3)
Bit
Name
Description
9:11
IRDA
Infrared Data Association
000 All IrDA pins are GPIOs
001 Reserved
010 Reserved
011 Reserved
100 Reserved
101 UART (without CD) / IrDA
110 Reserved
111 CODEC (without MCLK) / IrDA
12: 15
Ether
Ethernet
0000 All 18 Ethernet pins are GPIOs
0001 USB2 on Ethernet, see Note 3
0010 Ethernet 10Mbit (7-wire) mode
0011 Ethernet 7-wire and USB2, see Note 3
0100 Ethernet 100Mbit without MD
0101 Ethernet 100Mbit with MD
011X Reserved
1000 Ether 7-wire, UARTe, J1850
1001 Ether 7-wire, J1850
1010 Two UARTes, J1850
1011 One UARTe, J1850
1100 J1850
1101 Reserved
111X Reserved
16
PCI_DIS
0 PCI controller enabled
1 PCI controller disabled.
When Large Flash or Most Graphics modes are enabled on the LocalPlus bus interface, the PCI
interface can not be used (PCI control signals are used to support these modes).
When these modes are enabled (see LocalPlus control registers), the PCI controller must be
disabled to prevent interference.
If these modes are enabled at boot, this bit will come out of reset set to 1.
If these modes are not enabled at boot, this bit will come out of reset set to 0.
17
USB_SE
USB Single Ended mode.
The USB interface is able to support both Differential and Single Ended modes. This bit allows the
USB I/O interface to be programmed to Single Ended mode. Differential mode supplies TXP/TXN
and RXP/TXN.
Single ended mode supplies TXP/TX_SE0 and RXP/RX_SE0.
This bit controls all USB ports (i.e. they are not individually programmable). Default is Differential
mode.
0 Differential mode (Default after reset)
1 Single ended mode
18:19
USB
00
01
10
11
4 GPIOs and 1 Interrupt GPIO
USB
Two UARTs
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-35
System Integration Unit (SIU)
Table 7-21. GPS Port Configuration Register Field Descriptions (Sheet 3 of 3)
Bit
Name
Description
20:23
PSC3
Programmable Serial Controller 3
0000 All PSC3 pins are GPIOs
0001 USB2 on PSC3, no GPIOs available, see Note 3
001X Reserved
0100 UART functionality without CD
0101 UARTe functionality with CD
0110 CODEC3 functionality
0111 CODEC3 functionality (with MCLK)
100X SPI
101X Reserved
1100 SPI with UART3
1101 SPI with UART3e
111X SPI with CODEC3
24
—
25:27
PSC2
28
—
29:31
PSC1
Reserved
Programmable Serial Controller 2
000 All PSC2 pins are GPIOs
001 CAN1&2 on PSC2 pins, see Note 1
01X AC97 functionality
100 UART functionality without CD
101 UARTe functionality with CD
110 CODEC2 functionality (without MCLK)
111 CODEC2 functionality (with MCLK)
Reserved
Programmable Serial Controller 1
00X All PSC1 pins are GPIOs
01X AC97 functionality
100 UART functionality without CD
101 UARTe functionality with CD
110 CODEC1 functionality (without MCLK)
111 CODEC1 functionality (with MCLK)
Note:
1.
2.
3.
4.
5.
ALT CAN cannot exist with ATA on Tmr0/1, not with CAN on PSC2.
ALT SPI cannot exist with any SPI on PCS3.
USB cannot exist on both Either and PSC3.
See Section 7.3.1, “GPIO Pin Multiplexing” or Table 2-1 or Table 2-2 to determine GPIO availability for the various PCR field settings.
If Large Flash or Most Graphics mode is enabled at boot, using a reset configuration bit, PCI disable will come out of reset set to 1. If
these modes are not enabled at boot, this bit will come out of reset set to 0.
6. PSC3_4 and PSC3_5 default to zero (interrupt gpio) after reset. However, if the PSC3 is programmed to USB2 mode RXP and RXN
will be on these pins. If PSC is programmed to UARTe mode, CD will be on the PSC3_4 pin.
MPC5200B User’s Manual, Rev. 3
7-36
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.2
GPS Simple GPIO Enables Register
Address MBAR + 0x0B04
0
R
W
Reset
R
W
Reset
1
2
Reserved
3
4
5
IRDA
6
7
8
ETHR
9
10
11
12
13
Reserved
14
15
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
0
PSC3
0
0
0
0
0
PSC2
0
0
0
0
0
PSC1
0
0
0
0
0
Figure 7-21. GPS Simple GPIO Enables Register
Table 7-22. GPS Simple GPIO Enables Register Field Descriptions
Bit
Name
Description
0:1
—
2:3
IRDA
Individual enable bits for the 2 Simple GPIO on IRDA port.
bit 2 controls IR_USB_CLK pin
bit 3 controls IRDA_TX pin
0 Disabled for GPIO (default)
1 Enabled for GPIO
4:7
ETHR
Individual enable bits for the 4 Simple GPIO on ETHR port.
bit 4 controls ETH_11 pin
bit 5 controls ETH_10 pin
bit 6 controls ETH_9 pin
bit 7 controls ETH_8 pin
0 Disabled for GPIO (default)
1 Enabled for GPIO
8:11
—
12:15
USB
16:17
—
18:23
PSC3
Reserved
Reserved
Individual enable bits for the 4 Simple GPIO on USB port.
bit 12 controls USB1_8 pin
bit 13 controls USB1_7 pin
bit 14 controls USB1_6 pin
bit 15 controls USB1_0 pin
0 Disabled for GPIO (default)
1 Enabled for GPIO
Reserved
Individual enable bits for the 6 Simple GPIO on PSC3 port.
bit 18 controls PSC3_7 pin
bit 19 controls PSC3_6 pin
bit 20 controls PSC3_3 pin
bit 21 controls PSC3_2 pin
bit 22 controls PSC3_1 pin
bit 23 controls PSC3_0 pin
0 Disabled for GPIO (default)
1 Enabled for GPIO
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-37
System Integration Unit (SIU)
Table 7-22. GPS Simple GPIO Enables Register Field Descriptions (continued)
Bit
Name
24:27
PSC2
Individual enable bits for the 4 Simple GPIO on PSC2 port.
bit 24 controls GPIO_PSC2_3 (PSC2_3 pin)
bit 25 controls GPIO_PSC2_2 (PSC2_2 pin)
bit 26 controls GPIO_PSC2_1 (PSC2_1 pin)
bit 27 controls GPIO_PSC2_0 (PSC2_0 pin)
0 = Disabled for GPIO (default)
1 = Enabled for GPIO
28:31
PSC1
Individual enable bits for the 4 Simple GPIO on PSC1 port.
bit 28 controls GPIO_PSC1_3 (PSC1_3 pin)
bit 29 controls GPIO_PSC1_2 (PSC1_2 pin)
bit 30 controls GPIO_PSC1_1 (PSC1_1 pin)
bit 31 controls GPIO_PSC1_0 (PSC1_0 pin)
0 = Disabled for GPIO (default)
1 = Enabled for GPIO
7.3.2.1.3
Description
GPS Simple GPIO Open Drain Type Register
Address MBAR + 0x0B08
0
R
W
Reset
R
W
Reset
1
2
3
Reserved
4
5
IRDA
6
7
8
ETHR
9
10
11
12
13
Reserved
14
15
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
0
0
PSC3
0
0
0
0
PSC2
0
0
0
0
0
PSC1
0
0
0
0
0
Figure 7-22. GPS Simple GPIO Open Drain Type Register
Table 7-23. GPS Simple GPIO Open Drain Type Register Field Descriptions
Bit
Name
Description
0:1
—
2:3
IRDA
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 2 controls IR_USB_CLK pin
bit 3 controls IRDA_TX pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
4:7
ETHR
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 4 controls ETH_11 pin
bit 5 controls ETH_10 pin
bit 6 controls ETH_9 pin
bit 7 controls ETH_8 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
Reserved
MPC5200B User’s Manual, Rev. 3
7-38
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-23. GPS Simple GPIO Open Drain Type Register Field Descriptions (continued)
Bit
Name
8:11
—
12:15
USB
16:17
—
18:23
PSC3
Description
Reserved
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 12 controls USB1_8 pin
bit 13 controls GUSB1_7 pin
bit 14 controls USB1_6 pin
bit 15 controls USB1_0 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
Reserved
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 18 controls PSC3_7 pin
bit 19 controls PSC3_6 pin
bit 20 controls PSC3_3 pin
bit 21 controls PSC3_2 pin
bit 22 controls PSC3_1 pin
bit 23 controls PSC3_0 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
24:27
PSC2
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 24 controls PSC2_3 pin
bit 25 controls PSC2_2 pin
bit 26 controls PSC2_1 pin
bit 27 controls PSC2_0 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
28:31
PSC1
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 28 controls PSC1_3 pin
bit 29 controls PSC1_2 pin
bit 30 controls PSC1_1 pin
bit 31 controls PSC1_0 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-39
System Integration Unit (SIU)
7.3.2.1.4
GPS Simple GPIO Data Direction Register
Address MBAR + 0x0B0C
0
R
W
Reset
R
W
Reset
1
2
Reserved
3
4
5
IRDA
6
7
8
ETHR
9
10
11
12
13
Reserved
14
15
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
0
PSC3
0
0
0
0
0
PSC2
0
0
0
0
0
PSC1
0
0
0
0
0
Figure 7-23. GPS Simple GPIO Data Direction Register
Table 7-24. GPS Simple GPIO Data Direction Register Field Descriptions
Bit
Name
Description
0:1
—
2:3
IRDA
Individual bits to control directionality of the pin as GPIO.
bit 2 controls R_USB_CLK pin
bit 3 controls IRDA_TX pin
0 Pin is Input (default)
1 Pin is Output
4:7
ETHR
Individual bits to control directionality of the pin as GPIO.
bit 4 controls ETH_11 pin
bit 5 controls ETH_10 pin
bit 6 controls ETH_9 pin
bit 7 controls ETH_8 pin
0 Pin is Input (default)
1 Pin is Output
8:11
—
12:15
USB
16:17
—
18:23
PSC3
Reserved
Reserved
Individual bits to control directionality of the pin as GPIO.
bit 12 controls USB1_8 pin
bit 13 controls USB1_7 pin
bit 14 controls USB1_6 pin
bit 15 controls USB1_0 pin
0 Pin is Input (default)
1 Pin is Output
Reserved
Individual bits to control directionality of the pin as GPIO.
bit 18 controls PSC3_7 pin
bit 19 controls PSC3_6 pin
bit 20 controls PSC3_3 pin
bit 21 controls PSC3_2 pin
bit 22 controls PSC3_1 pin
bit 23 controls PSC3_0 pin
0 Pin is Input (default)
1 Pin is Output
MPC5200B User’s Manual, Rev. 3
7-40
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-24. GPS Simple GPIO Data Direction Register Field Descriptions (continued)
Bit
Name
24:27
PSC2
Individual bits to control directionality of the pin as GPIO.
bit 24 controls PSC2_3 pin
bit 25 controls PSC2_2 pin
bit 26 controls PSC2_1 pin
bit 27 controls PSC2_0 pin
0 = Pin is Input (default)
1 = Pin is Output
28:31
PSC1
Individual bits to control directionality of the pin as GPIO.
bit 28 controls PSC1_3 pin
bit 29 controls PSC1_2 pin
bit 30 controls PSC1_1 pin
bit 31 controls PSC1_0 pin
0 = Pin is Input (default)
1 = Pin is Output
7.3.2.1.5
Description
GPS Simple GPIO Data Output Values Register
Address MBAR + 0x0B10
0
R
W
Reset
R
W
Reset
1
2
Reserved
3
4
5
IRDA
6
7
8
ETHR
9
10
11
12
13
Reserved
14
15
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
0
0
PSC3
0
0
0
0
PSC2
0
0
0
0
0
PSC1
0
0
0
0
0
Figure 7-24. GPS Simple GPIO Data Output Values Register
Table 7-25. GPS Simple GPIO Data Output Values Register Field Descriptions
Bit
Name
Description
0:1
—
2:3
IRDA
Individual bits to control the state of pins configured as GPIO output.
bit 2 controls IR_USB_CLK pin
bit 3 controls GPIO_IRDA_0 (IRDA_TX pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
4:7
ETHR
Individual bits to control the state of pins configured as GPIO output.
bit 4 controls ETH_11 pin
bit 5 controls ETH_10 pin
bit 6 controls ETH_9 pin
bit 7 controls ETH_8 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-41
System Integration Unit (SIU)
Table 7-25. GPS Simple GPIO Data Output Values Register Field Descriptions (continued)
Bit
Name
Description
8:11
—
12:15
USB
16:17
—
18:23
PSC3
Individual bits to control the state of pins configured as GPIO output.
bit 18 controls PSC3_7 pin
bit 19 controls PSC3_6 pin
bit 20 controls PSC3_3 pin
bit 21 controls PSC3_2 pin
bit 22 controls PSC3_1 pin
bit 23 controls PSC3_0 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
24:27
PSC2
Individual bits to control the state of pins configured as GPIO output.
bit 24 controls PSC2_3 pin
bit 25 controls PSC2_2 pin
bit 26 controls PSC2_1 pin
bit 27 controls PSC2_0 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
28:31
PSC1
Individual bits to control the state of pins configured as GPIO output.
bit 28 controls PSC1_3 pin
bit 29 controls PSC1_2 pin
bit 30 controls PSC1_1 pin
bit 31 controls PSC1_0 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
Reserved
Individual bits to control the state of pins configured as GPIO output.
bit 12 controls USB1_8 pin
bit 13 controls USB1_7 pin
bit 14 controls USB1_6 pin
bit 15 controls USB1_0 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
Reserved
MPC5200B User’s Manual, Rev. 3
7-42
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.6
GPS Simple GPIO Data Input Values Register
Address MBAR + 0x0B14
0
R
W
Reset
R
W
Reset
1
2
3
4
5
IRDA
Reserved
6
7
8
ETHR
9
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
0
0
PSC3
0
0
0
0
11
12
13
0
0
0
0
26
27
28
29
PSC2
0
0
0
0
0
14
15
USB
Reserved
0
Reserved
10
0
0
30
31
PSC1
0
0
0
0
0
Figure 7-25. GPS Simple GPIO Data Input Values Register
Table 7-26. GPS Simple GPIO Data Input Values Register Field Descriptions
Bit
Name
Description
0:1
—
2:3
IRDA
Individual status bits reflecting the state of corresponding GPIO pins.
bit 2 reflects IR_USB_CLK pin
bit 3 reflects RDA_TX pin
4:7
ETHR
Individual status bits reflecting the state of corresponding GPIO pins.
bit 4 reflects ETH_11 pin
bit 5 reflects ETH_10 pin
bit 6 reflects ETH_9 pin
bit 7 reflects ETH_8 pin
8:11
—
12:15
USB
Reserved
Reserved
Individual status bits reflecting the state of corresponding GPIO pins.
bit 12 reflects USB1_8 pin
bit 13 reflects USB1_7 pin
bit 14 reflects USB1_6 pin
bit 15 reflects USB1_0 pin
16:17
—
18:23
PSC3
Individual status bits reflecting the state of corresponding GPIO pins.
bit 18 reflects PSC3_7 pin
bit 19 reflects PSC3_6 pin
bit 20 reflects PSC3_3 pin
bit 21 reflects PSC3_2 pin
bit 22 reflects PSC3_1 pin
bit 23 reflects PSC3_0 pin
Reserved
24:27
PSC2
Individual status bits reflecting the state of corresponding GPIO pins.
bit 24 reflects PSC2_3 pin
bit 25 reflects PSC2_2 pin
bit 26 reflects PSC2_1 pin
bit 27 reflects PSC2_0 pin
28:31
PSC1
Individual status bits reflecting the state of corresponding GPIO pins.
bit 28 reflects PSC1_3 pin
bit 29 reflects PSC1_2 pin
bit 30 reflects PSC1_1 pin
bit 31 reflects PSC1_0 pin
Note: These status bits operate regardless of the function on the pin.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-43
System Integration Unit (SIU)
7.3.2.1.7
GPS GPIO Output-Only Enables Register
Address MBAR + 0x0B18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ETHR
I2C
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-26. GPS GPIO Output-Only Enables Register
Table 7-27. GPS GPIO Output-Only Enables Register Field Descriptions
Bit
Name
Description
0:7
ETHR
8 :11
—
Reserved
12:15
I2C
Individual bits to enable each Output Only GPIO pin—all reside on the I2C ports.
bit 12 controls I2C_2 pin
bit 13 controls I2C_3 pin
bit 14 controls I2C_0 pin
bit 15 controls I2C_1 pin
0 Disabled for GPIO use (default)
1 Enabled for GPIO use
This bits can be used to toggle the clock (SCL) and data (SDA) lines of the I2C interface.
16:31
—
Reserved
Individual bits to enable each Output Only GPIO pin—all reside on the Ethernet port.
bit 0 controls ETH_7 pin
bit 1 controls ETH_6 pin
bit 2 controls ETH_5 pin
bit 3 controls ETH_4 pin
bit 4 controls ETH_3 pin
bit 5 controls ETH_2 pin
bit 6 controls ETH_1 pin
bit 7 controls ETH_0 pin
0 Disabled for GPIO use (default)
1 Enabled for GPIO use
MPC5200B User’s Manual, Rev. 3
7-44
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.8
GPS GPIO Output-Only Data Value Out Register
Address MBAR + 0x0B1C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ETHR
I2C
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-27. GPS GPIO Output-Only Data Value Out Register
Table 7-28. GPS GPIO Output-Only Data Value Out Register Field Descriptions
Bit
Name
Description
0:7
ETHR
8 :11
—
Reserved
12:15
I2C
Individual bits to control the state of enabled Output Only GPIO pins — all reside on the I2C ports.
bit 12 controls I2C_2 pin
bit 13 controls I2C_3 pin
bit 14 controls I2C_0 pin
bit 15 controls I2C_1 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
This bits can be used to toggle the clock (SCL) and data (SDA) lines of the I2C interface.
16:31
—
Reserved
Individual bits to control the state of enabled Output Only GPIO pins.
bit 0 controls ETH_7 pin
bit 1 controls ETH_6 pin
bit 2 controls ETH_5 pin
bit 3 controls ETH_4 pin
bit 4 controls ETH_3 pin
bit 5 controls ETH_2 pin
bit 6 controls ETH_1 pin
bit 7 controls ETH_0 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-45
System Integration Unit (SIU)
7.3.2.1.9
GPS GPIO Simple Interrupt Pin Enable Register
Address MBAR + 0x0B20
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SIGPIOe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Table 7-29. GPS GPIO Simple Interrupt Pin Enable Register
Table 7-30. GPS GPIO Simple Interrupt Pin Enable Register Field Descriptions
Bit
Name
0:7
SIGPIOE
8:31
—
Description
Individual bits to enable each Interrupt GPIO pin (pins are scattered).
bit 0 controls ETH_16 pin
bit 1 controls ETH_15 pin
bit 2 controls ETH_14 pin
bit 3 controls ETH_13 pin
bit 4 controls USB1_9 pin
bit 5 controls PSC3_8 pin
bit 6 controls PSC3_5 pin
bit 7 controls PSC3_4 pin
0 disabled for GPIO use (default)
1 enabled for GPIO use
Reserved
MPC5200B User’s Manual, Rev. 3
7-46
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.10
GPS GPIO Simple Interrupt Open-Drain Emulation Register
Address MBAR + 0x0B24
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SIODe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-28. GPS GPIO Simple Interrupt Open-Drain Emulation Register
Table 7-31. GPS GPIO Simple Interrupt Open-Drain Emulation Register Field Descriptions
Bit
Name
0:7
SIODe
8:31
—
Description
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 0 controls ETH_16 pin
bit 1 controls ETH_15 pin
bit 2 controls ETH_14 pin
bit 3 controls ETH_13 pin
bit 4 controls USB1_9 pin
bit 5 controls PSC3_8 pin
bit 6 controls PSC3_5 pin
bit 7 controls PSC3_4 pin
0 Normal CMOS output (default)
1 Open Drain emulation (a drive to high creates Hi-Z)
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-47
System Integration Unit (SIU)
7.3.2.1.11
GPS GPIO Simple Interrupt Data Direction Register
Address MBAR + 0x0B28
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SIDDR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-29. GPS GPIO Simple Interrupt Data Direction Register
Table 7-32. GPS GPIO Simple Interrupt Data Direction Register Field Descriptions
Bit
Name
0:7
SIDDR
8:31
—
Description
Individual bits to control direction of the pin as GPIO.
bit 0 controls ETH_16 pin
bit 1 controls ETH_15 pin
bit 2 controls ETH_14 pin
bit 3 controls ETH_13 pin
bit 4 controls USB1_9 pin
bit 5 controls PSC3_8 pin
bit 6 controls PSC3_5 pin
bit 7 controls PSC3_4 pin
0 Pin is Input (default)
1 Pin is Output
Reserved
MPC5200B User’s Manual, Rev. 3
7-48
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.12
GPS GPIO Simple Interrupt Data Value Out Register
Address MBAR + 0x0B2C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SIDVO
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-30. GPS GPIO Simple Interrupt Data Value Out Register
Table 7-33. GPS GPIO Simple Interrupt Data Value Out Register Field Descriptions
Bit
Name
0:7
SIDVO
8:31
—
Description
Individual bits to control the state of pins configured as GPIO output.
bit 0 controls ETH_16 pin
bit 1 controls ETH_15 pin
bit 2 controls ETH_14 pin
bit 3 controls ETH_13 pin
bit 4 controls USB1_9 pin
bit 5 controls PSC3_8 pin
bit 6 controls PSC3_5 pin
bit 7 controls PSC3_4 pin
0 Drive 0 on the pin (default)
1 Drive 1 on the pin
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-49
System Integration Unit (SIU)
7.3.2.1.13
GPS GPIO Simple Interrupt Enable Register
Address MBAR + 0x0B30
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
SIINTEN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-31. GPS GPIO Simple Interrupt Enable Register
Table 7-34. GPS GPIO Simple Interrupt Enable Register Field Descriptions
Bit
Name
0:7
SIINTEN
8:31
—
Description
Individual bits to enable Interrupt generation for each GPIO pin configured as an Input.
bit 0 controls ETH_16 pin
bit 1 controls ETH_15 pin
bit 2 controls ETH_14 pin
bit 3 controls ETH_13 pin
bit 4 controls USB1_9 pin
bit 5 controls PSC3_8 pin
bit 6 controls PSC3_5 pin
bit 7 controls PSC3_4 pin
0 Pin cannot generate an Interrupt (default)
1 Pin can generate an Interrupt if configured as an Input GPIO
Reserved
Note: See Interrupt Type data in GPS GPIO Simple Interrupt Types Register Register. Also, the Master Interrupt Enable bit must
be set in the GPS GPIO Simple Interrupt Master Enable Register Register, before any Simple Interrupt pin can generate
an Interrupt.
MPC5200B User’s Manual, Rev. 3
7-50
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.14
GPS GPIO Simple Interrupt Types Register
Address MBAR + 0x0B34
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ITYP7
ITYP6
ITYP5
ITYP4
ITYP3
ITYP2
ITYP1
ITYP0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-32. GPS GPIO Simple Interrupt Types Register
Table 7-35. GPS GPIO Simple Interrupt Types Register Field Descriptions
Bit
Name
0:15
ITYP[0:7]
16:31
—
Description
GPIO Interrupt Type bits for Simple-Interrupt GPIO pin 7.
ITYP7—bits 0:1 controls ETH_16 pin
ITYP6—bits 2:3 controls ETH_15 pin
ITYP5—bits 4:5 controls ETH_14 pin
ITYP4—bits 6:7 controls ETH_13 pin
ITYP3—bits 8:9 controls USB1_9 pin
ITYP2—bits 10:11 controls PSC3_8 pin
ITYP1—bits 12:13 controls PSC3_5 pin
ITYP0—bits 14:15 controls PSC3_4 pin
00 Interrupt on any transition
01 Interrupt on rising edge
10 Interrupt on falling edge
11 Interrupt on pulse (any two transitions)
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-51
System Integration Unit (SIU)
7.3.2.1.15
GPS GPIO Simple Interrupt Master Enable Register
Address MBAR + 0x0B38
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ME
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-33. GPS GPIO Simple Interrupt Master Enable Register
Table 7-36. GPS GPIO Simple Interrupt Master Enable Register Field Descriptions
Bit
Name
Description
0:2
—
Reserved
3
ME
GPIO Simple Interrupt Master Enable pin—This pin must be high before any Simple Interrupt pin
can generate an interrupt. This bit should remain clear while programming individual interrupts,
then set high as a final step. This prevents any spurious interrupt occurring during programming.
4:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
7-52
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.1.16
GPS GPIO Simple Interrupt Status Register
Address MBAR + 0x0B3C
0
1
2
3
R
W
Reset
4
5
6
7
8
9
10
11
ISTAT
12
13
14
15
IVAL
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-34. GPS GPIO Simple Interrupt Status Register
Table 7-37. GPS GPIO Simple Interrupt Status Register Field Descriptions
Bit
Name
Description
0:7
ISTAT
Interrupt Status—status bit for GPIO Simple interrupt pins 7 to 0, where 1 indicates an interrupt
has occurred. Clear bit with a Sticky bit write to 1.
Bit 0 reflects ETH_16 pin
Bit 1 reflects ETH_15 pin
Bit 2 reflects ETH_14 pin
Bit 3 reflects ETH_13 pin
Bit 4 reflects USB1_9 pin
Bit 5 reflects PSC3_8 pin
Bit 6 reflects PSC3_5 pin
Bit 7 reflects PSC3_4 pin
8:15
IVAL
Input Value—status bit for GPIO Simple Interrupt pins 7 to 0. This is the raw state of the input pin
at the time this register is read. It is not latched to the state that caused the Interrupt (if any).
Bit 8 reflects ETH_16 pin
Bit 9 reflects ETH_15 pin
Bit 10 reflects ETH_14 pin
Bit 11 reflects ETH_13 pin
Bit 12 reflects USB1_9 pin
Bit 13 reflects PSC3_8 pin
Bit 14 reflects PSC3_5 pin
Bit 15 reflects PSC3_4 pin
IVAL is always available regardless of enable or setting, even if not used as GPIO.
Writing to this byte has no effect.
16:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-53
System Integration Unit (SIU)
7.3.2.2
WakeUp GPIO Registers
The WakeUp GPIO Register Set provides GPIO control for the 8 WakeUp GPIO pins. These pins are
scattered throughout the pin groups, but are all controlled in this module. It should be noted that WakeUp
GPIO can operate as Simple Interrupt GPIO. Because of this, there are separate registers to enable these
pins as Wakeup interrupts and/or Simple Interrupts. The distinction between these two types of interrupts
is made according to the powered state of MPC5200B.
• In Deep Sleep mode, the WakeUp Interrupt enables are used.
• In all other modes, the Simple Interrupt enables are used.
In either of the above types of interrupts, we are referring to the WakeUp GPIO and the registers in this
module. These are not to be confused with the Simple Interrupt GPIO pins, which are controlled in the
previous module, GPIO Standard.
This WakeUp GPIO register set uses 10 32-bit registers. These registers are located at an offset from
MBAR of 0x0C00. Register addresses are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0C00 + register address
Hyperlinks to the WakeUp GPIO registers are provided below:
• GPW WakeUp GPIO Enables Register (0x0C00)
• GPW WakeUp GPIO Open Drain Emulation Register (0x0C04)
• GPW WakeUp GPIO Data Direction Register (0x0C08)
• GPW WakeUp GPIO Data Value Out Register (0x0C0C)
• GPW WakeUp GPIO Interrupt Enable Register (0x0C10)
• GPW WakeUp GPIO Individual Interrupt Enable Register (0x0C14)
• GPW WakeUp GPIO Interrupt Types Register (0x0C18)
• GPW WakeUp GPIO Master Enables Register (0x0C1C)
• GPW WakeUp GPIO Data Input Values Register (0x0C20)
• GPW WakeUp GPIO Status Register (0x0C24)
MPC5200B User’s Manual, Rev. 3
7-54
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.2.1
GPW WakeUp GPIO Enables Register
Address MBAR + 0x0C00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WGPIOe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-35. GPW WakeUp GPIO Enables Register
Table 7-38. GPW WakeUp GPIO Enables Register Field Descriptions
Bit
Name
0:7
WGPIOe
8:31
—
Description
Bits to enable the operation of individual wakeup GPIO pins.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Pin not enabled for any GPIO use (default).
1 Pin enabled for use as GPIO.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-55
System Integration Unit (SIU)
7.3.2.2.2
GPW WakeUp GPIO Open Drain Emulation Register
Address MBAR + 0x0C04
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WODe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-36. GPW WakeUp GPIO Open Drain Emulation Register
Table 7-39. GPW WakeUp GPIO Open Drain Emulation Register Field Descriptions
Bit
Name
0:7
WODe
8:31
—
Description
Bits to control open drain emulation for individual WakeUp GPIO configured as outputs.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Normal CMOS output (default).
1 Open Drain emulation (a drive to high creates Hi-Z).
Reserved
MPC5200B User’s Manual, Rev. 3
7-56
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.2.3
GPW WakeUp GPIO Data Direction Register
Address MBAR + 0x0C08
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WDDR[7:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-37. GPW WakeUp GPIO Data Direction Register
Table 7-40. GPW WakeUp GPIO Data Direction Register Field Descriptions
Bit
Name
0:7
WDDR[7:0]
8:31
—
Description
Individual bits to control directionality of the pin as GPIO.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Pin is Input (default).
1 Pin is Output.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-57
System Integration Unit (SIU)
7.3.2.2.4
GPW WakeUp GPIO Data Value Out Register
Address MBAR + 0x0C0C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WDVO
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-38. GPW WakeUp GPIO Data Value Out Register
Table 7-41. GPW WakeUp GPIO Data Value Out Register Field Descriptions
Bit
Name
0:7
WDVO
8:31
—
Description
Individual bits to control the state of pins configured as GPIO output.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Drive 0 on the pin (default).
1 Drive 1 on the pin.
Note: If pin is emulating open drain, this setting results in Hi-Z
Reserved
MPC5200B User’s Manual, Rev. 3
7-58
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.2.5
GPW WakeUp GPIO Interrupt Enable Register
Address MBAR + 0x0C10
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WUPe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-39. GPW WakeUp GPIO Interrupt Enable Register
Table 7-42. GPW WakeUp GPIO Interrupt Enable Register Field Descriptions
Bit
Name
0:7
WUPe
8:31
—
Description
Individual bits to enable generation of WakeUp interrupt for WakeUp GPIO configured as input.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Pin cannot generate WakeUp Interrupt (default).
1 Pin can generate WakeUp Interrupt while MPC5200B is in Deep Sleep mode.
Note: These enable bits apply ONLY when MPC5200B is in Deep Sleep mode.
Reserved
Note: Only valid when Port Configuration indicates GPIO usage and pin is configured as input in the associated DDR bit in
GPIOWDO. Also, Master Interrupt Enable bit in GPIOWME must be set.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-59
System Integration Unit (SIU)
7.3.2.2.6
GPW WakeUp GPIO Individual Interrupt Enable Register
Address MBAR + 0x0C14
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WINe
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-40. GPW WakeUp GPIO Individual Interrupt Enable Register
Table 7-43. GPW WakeUp GPIO Individual Interrupt Enable Register Field Descriptions
Bit
Name
0:7
WINe
8:31
—
Description
Individual bits to enable generation of Simple interrupt for WakeUp GPIO configured as input.
Bit 0 controls GPIO_WKUP_7 pin
Bit 1 controls GPIO_WKUP_6 pin
Bit 2 controls PSC6_1 pin
Bit 3 controls PSC6_0 pin
Bit 4 controls ETH_17 pin
Bit 5 controls PSC3_9 pin
Bit 6 controls PSC2_4 pin
Bit 7 controls PSC1_4 pin
0 Pin cannot generate Simple Interrupt (default).
1 Pin can generate Simple Interrupt while MPC5200B is not in Deep Sleep mode.
Note: These enable bits apply only when MPC5200B is not in Deep Sleep mode.
Reserved
Note: Only valid when Port Configuration indicates GPIO usage and pin is configured as input in the associated DDR bit in
GPIOWDO. Also, Master Interrupt Enable bit in GPIOWME must be set.
MPC5200B User’s Manual, Rev. 3
7-60
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.2.7
GPW WakeUp GPIO Interrupt Types Register
Address MBAR + 0x0C18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Ityp7
Ityp6
Ityp5
Ityp4
Ityp3
Ityp2
Ityp7
Ityp0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-41. GPW WakeUp GPIO Interrupt Types Register
Table 7-44. GPW WakeUp GPIO Interrupt Types Register Field Descriptions
Bit
Name
Description
0:1
Ityp7
2:3
Ityp6
4:5
Ityp5
6:7
Ityp4
8:9
Ityp3
10:11
Ityp2
12:13
Ityp1
14:15
Ityp0
GPIO Interrupt Type bits for WakeUp GPIO pins 7–0
00 Interrupt at any transition
01 Interrupt on rising edge
10 Interrupt on falling edge
11 Interrupt on pulse (any 2 transitions)
The above interrupt types describe operation for interrupts occurring while MPC5200B is not in
Deep Sleep mode (i.e., Simple Interrupt types). For operation while in Deep Sleep mode the
interpretation of these bits is slightly different, because no clocking is present in this mode and it
is therefore impossible to detect an edge on the input. For Deep Sleep mode the bits are
interpreted as follows:
00 Not Valid, no interrupt can be detected
01 Level High, any high creates WakeUp from Deep Sleep
10 Level Low, any low creates WakeUp from Deep Sleep
11 Not Valid, no interrupt can be detected.
ITYP7 controls GPIO_WKUP_7 pin
ITYP6 controls GPIO_WKUP_6 pin
ITYP5 controls PSC6_1 pin
ITYP4 controls PSC6_0 pin
ITYP3 controls ETH_17 pin
ITYP2 controls PSC3_9 pin
ITYP1 controls PSC2_4 pin
ITYP0 controls PSC1_4 pin
Note: Any GPIO WakeUp interrupt creates a Main Level 2 interrupt in the Interrupt Controller.
16:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-61
System Integration Unit (SIU)
7.3.2.2.8
GPW WakeUp GPIO Master Enables Register
Address MBAR + 0x0C1C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ME
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-42. GPW WakeUp GPIO Master Enables Register
Table 7-45. GPW WakeUp GPIO Master Enables Register Field Descriptions
Bit
Name
Description
0:6
—
Reserved
7
ME
WakeUp GPIO Master Enable pin. This pin must be high before any WakeUp GPIO pin can
generate an interrupt. This bit should remain clear while programming individual interrupts and
then set high as a final step. This prevents any spurious interrupt occurring during programming.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
7-62
Freescale Semiconductor
System Integration Unit (SIU)
7.3.2.2.9
GPW WakeUp GPIO Data Input Values Register
Address MBAR + 0x0C20
0
1
2
R
3
4
5
6
7
8
9
10
11
12
13
14
15
WIVAL
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-43. GPW WakeUp GPIO Data Input Values Register
Table 7-46. GPW WakeUp GPIO Data Input Values Register Field Descriptions
Bit
Name
Description
0:7
WIVAL
Input Value bits for GPIO WakeUp pins 7–0. This is the raw state of the input pin at the time this
register is read. It is not latched to the state that caused the interrupt (if any).
This status bit is always available, regardless of any enable or setting. For example, even if the pin
is not used as GPIO.
Writing to this byte has no effect.
Bit 0 reflects GPIO_WKUP_7 pin
Bit 1 reflects GPIO_WKUP_6 pin
Bit 2 reflects PSC6_1 pin
Bit 3 reflects PSC6_0 pin
Bit 4 reflects ETH_17 pin
Bit 5 reflects PSC3_9 pin
Bit 6 reflects PSC2_4 pin
Bit 7 reflects PSC1_4 pin
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-63
System Integration Unit (SIU)
7.3.2.2.10
GPW WakeUp GPIO Status Register
Address MBAR + 0x0C24
0
1
2
3
R
4
5
6
7
8
9
10
11
12
13
14
15
Istat
Reserved
W
Reset
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-44. GPW WakeUp GPIO Status Register
Table 7-47. GPW WakeUp GPIO Status Register Field Descriptions
Bit
Name
0:7
Istat
8:31
—
Description
Interrupt status bits for GPIO WakeUp pins 7–0.
1 indicates an interrupt occurred. Cleared with a sticky-bit write to a 1 to clear the interrupt
condition.
Bit 0 reflects interrupt on GPIO_WKUP_7 pin
Bit 1 reflects interrupt on GPIO_WKUP_6 pin
Bit 2 reflects interrupt on PSC6_1 pin
Bit 3 reflects interrupt on PSC6_0 pin
Bit 4 reflects interrupt on ETH_17 pin
Bit 5 reflects interrupt on PSC3_9 pin
Bit 6 reflects interrupt on PSC2_4 pin
Bit 7 reflects interrupt on PSC1_4 pin
Reserved
MPC5200B User’s Manual, Rev. 3
7-64
Freescale Semiconductor
System Integration Unit (SIU)
7.4
General Purpose Timers (GPT)
Eight (8) General-Purpose Timer (GPT) pins are configurable for:
• Input Capture
• Output Compare
• Pulse Width Modulation (PWM) Output
• Simple GPIO
• Internal CPU timer
• Watchdog Timer (on GPT0 only)
Timer modules run off the internal IP bus clock. Each Timer is associated to a single I/O pin. Each Timer
has a 16-bit prescaler and 16-bit counter, thus achieving a 32-bit range (but only 16-bit resolution).
7.4.1
Timer Configuration Method
Use the following method to configure each timer:
1. Determine the Mode Select field (Timer_MS) value for the desired operation.
2. Program any other registers associated with this mode.
3. Program Interrupt enable as desired.
4. Enable the Timer by writing the Mode Select value into the Timer_MS field.
7.4.2
Mode Overview
The following gives a brief description of the available modes:
1. Input Capture—In this mode the I/O pin is an Input. Once enabled, the counters run until the
specified “Capture Event” occurs (rise, fall, either, or pulse). At the Capture Event, the counter
value is latched in the status register. If enabled, a CPU interrupt is generated. The GP Timers 6 &
7 are active during low power modes (except for deep sleep), and therefore have the ability to
initiate a wake up the device from a low-power mode.
2. Output Compare—In this mode the I/O pin is an Output. When enabled the counters run until
they reach the programmed Terminal Count value. At this point, the specified “Output Event” is
generated (toggle, pulse hi, or pulse low). If enabled, a CPU interrupt is generated.
3. PWM—In this mode the I/O pin is an Output. The user can program “Period” and “Width” values
to create an adjustable, repeating output waveform on the I/O pin. A CPU interrupt can be
generated at the beginning of each PWM Period, at which time a new Width value can be loaded.
The new Width value, which represents “ON time”, is automatically applied at the beginning of
the next period. Note that there is no interrupt at the beginning of the first PWM Period. This mode
is suitable for PWM audio encoding.
4. Simple GPIO—In this mode the I/O pin operates as a GPIO pin. It can be specified as Input or
Output, according to the programmable GPIO field. GPIO mode is mutually exclusive of modes 1
through 3 (listed above). In GPIO mode, modes 5 through 6 (listed below) remain available.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-65
System Integration Unit (SIU)
5. CPU Timer—The I/O pin is not used in this mode. Once enabled, the counters run until they reach
a programmed Terminal Count. When this occurs, an interrupt can be generated to the CPU. This
Timer mode can be used simultaneously with the Simple GPIO mode.
6. Watchdog Timer—This is a special CPU Timer mode, available only on Timer 0. The user must
enable the Watchdog Timer mode, which is not active upon reset. The Terminal Count value is
programmable. If the counter is allowed to expire, a full MPC5200B reset occurs. To prevent the
Watchdog Timer from expiring, software must periodically write a specific value to a specific
register (in Timer 0). This causes the counter to reset.
7.4.3
Programming Notes
Programmers should observe the following notes:
1. Intermediate values of the Timer internal counters are not readable by software.
2. The Stop_Cont bit operates differently for different modes. In general, this bit controls whether the
Timer halts at the end of a current mode, or resets and continues with a repetition of the mode. See
the Bit Description for precise operation.
3. The Timer_MS field operates somewhat as a Global Enable. If it is zero, then all Timer modes are
disabled and internal counters are reset. See the Bit Descriptions for more detail.
4. There is a CE (Counter Enable) bit that operates somewhat independently of the Timer_MS field.
This bit controls the Counter for CPU Timer or Watchdog Timer modes only. See the Bit
Descriptions to understand the operation of these bits across the various modes.
7.4.4
GPT Registers
Each GPT uses 4 32-bit registers. These registers are located at an offset from MBAR of 0x0600. Register
addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x0600 + register
address.
Hyperlinks to the Interrupt Controller registers are provided below:
•
•
•
•
GPT0–GPT7 Enable and Mode Select Registers (0x0600, 0x0620, 0x0630, 0x0640, 0x0650,
0x0660, 0x0670)
GPT0–GPT7 Counter Input Registers (0x0604, 0x0614, 0x0624, 0x0634, 0x0644, 0x0654,
0x0664, 0x0674)
GPT0–GPT7 PWM Configuration Registers 0x0608, 0x0618, 0x0628, 0x0638, 0x0648, 0x0658,
0x0668, 0x0678)
GPT0–GPT7 Status Registers (0x060C. 0x061C, 0x062C, 0x063C, 0x064C, 0x065C, 0x066C,
0x067C)
MPC5200B User’s Manual, Rev. 3
7-66
Freescale Semiconductor
System Integration Unit (SIU)
7.4.4.1
GPT0–GPT7 Enable and Mode Select Registers
Address MBAR + 0x0600, 0x0610, 0x0620, 0x0630, 0x0640, 0x0650, 0x0660, 0x0670
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
OCPW
OCT
Reserved
ICT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CE
Rsvd
Open_Drn
Reset
Stop_Cont
W
IntEn
0
0
0
0
0
R
Reserved
WDen
W
Reset
0
0
0
Reserved
0
0
GPIO
0
Rsvd
0
0
Timer_MS
0
0
0
Figure 7-45. GPT0–GPT7 Enable and Mode Select Registers
Table 7-48. GPT0–GPT7 Enable and Mode Select Register Field Descriptions (Sheet 1 of 3)
Bit
Name
Description
0:7
OCPW
Output Compare Pulse Width—Applies to OC Pulse types only. This field specifies the number of IP
bus clocks (non-prescaled) to create a short output pulse at each Output Event. This pulse is
generated at the end of the OC period and overlays the next OC period (rather than adding to the
period).
Note: This field is alternately used as the Watchdog reset field if Watchdog Timer mode is enabled.
8:9
—
10:11
OCT
12:13
—
14:15
ICT
Reserved
Output Compare Type—describes action to occur at each output compare event, as follows:
00=Special case, output is immediately forced low without respect to each output compare event.
01=Output pulse highs, initial value is low (OCPW field applies).
10=Output pulses low, initial value is high (OCPW field applies).
11=Output toggles.
GPIO modalities can be used to achieve an initial output state prior to enabling OC mode. It is
important to move directly from GPIO output mode to OC mode and not to pass through the
Timer_MS=000 state.
To prevent the Internal Timer Mode from engaging during the GPIO state, CE bit should be held low
during the configuration steps.
GPIO initialization is needed when presetting the I/O to 1 in conjunction with a simple toggle OCT
setting.
Note: For Stop Mode operation (see Stop_Cont bit below) it is necessary to pass through the
mode_sel = 0 state to restart the output compare counters with their programmed values. See
prescale and count fields in Table 7-49.
Reserved
Input Capture Type—describes the input transition type required to trigger an input capture event, as
follows:
00=Any input transition causes an IC event.
01=IC event occurs at input rising edge.
10=IC event occurs at input falling edge.
11=IC event occurs at any input pulse (i.e., at 2nd input edge).
BE AWARE: For ICT=11 (pulse capture), status register records only the pulse width.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-67
System Integration Unit (SIU)
Table 7-48. GPT0–GPT7 Enable and Mode Select Register Field Descriptions (Sheet 2 of 3)
Bit
Name
Description
16
WDen
Watchdog enable—bit enables watchdog operation. A timer expiration causes an internal MPC5200B
reset. Watchdog operation requires the Timer_MS field be set for internal timer mode and the CE bit
to be set high.
In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW field
resets the watchdog timer, preventing it from expiring. As long as the timer is properly configured, the
watchdog operation continues.
This bit (and functionality) is implemented only for Timer 0. 1 = enabled
17:18
—
Reserved
19
CE
Counter Enable—bit enables or resets the internal counter during Internal timer modes only. CE must
be high to enable these modes. If low, counter is held in reset.
This bit is secondary to the timer mode select bits (Timer_MS). If Timer_MS is1XX, internal timer
modes are enabled. CE can then enable or reset the internal counter without changing the Timer_MS
field.
GPIO operation is also available in this mode. 1 = enabled
20
—
Reserved
21
Stop_Cont
Stop Continuous—Applies to multiple modes, as follows:
0 = Stop
1 = Continuous
•
•
•
•
•
22
Open_Drn
IC mode
Stop operation—At each IC event, counter is reset.
Continuous operation—counter is not reset at each IC event.
Effect is to create Status count values that are cumulative between Capture events. If the special
Pulse Mode Capture type is specified, the Stop_Cont bit is not used, operation fixed as if it were
Stop.
OC mode
Stop operation—Counter resets and stops at first OC event. Note: Software needs to pass through
Timer_MS=000 state to restart timer.
Continuous operation—counter resets and continues at each OC event.
Effect to is create back-to-back periodic OC events.
BE AWARE—In this mode the polarity of Stop_cont is reversed. Also, in Stop Mode, the output
event falsely retriggers at the expiration of the prescale count.
This means the software has to service and output event prior to the prescale expiring. Service is
defined as programming mode_sel field to 0, which causes the programmed prescale and count
values to be reset.
PWM mode
Bit not used, operation is always Continuous.
CPU Timer mode
Stop operation—On counter expiration, Timer waits until Status bit is cleared by passing through
Timer_MS=000 state before beginning a new cycle.
Continuous operation—On counter expiration, Timer resets and immediately begin a new cycle.
Effect is to generate fixed periodic timeouts.
WatchDog Timer and GPIO modes
Bit not used.
Open Drain
0 = Normal I/O
1 = Open Drain emulation—affects all modes that drive the I/O pin (GPIO, OC, & PWM). Any
output “1” is converted to a tri-state at the I/O pin.
MPC5200B User’s Manual, Rev. 3
7-68
Freescale Semiconductor
System Integration Unit (SIU)
Table 7-48. GPT0–GPT7 Enable and Mode Select Register Field Descriptions (Sheet 3 of 3)
Bit
Name
Description
23
IntEn
Enable interrupt—enables interrupt generation to the CPU for all modes (IC, OC, PWM, and Internal
Timer). IntEn is not required for watchdog expiration to create a reset. 1 = enabled
24:25
—
26:27
GPIO
28
—
29:31
Timer_MS
Reserved
GPIO mode type. Simple GPIO functionality that can be used simultaneously with the Internal Timer
mode. It is not compatible with IC, OC, or PWM modes, since these modes dictate the usage of the
I/O pin.
0x=Timer enabled as simple GPIO input
10=Timer enabled as simple GPIO output, value=0
11=Timer enabled as simple GPIO output, value=1 (tri-state if Open_Drn=1)
While in GPIO modes, internal timer mode is also available. To prevent undesired timer expiration,
keep the CE bit low.
Reserved
Timer Mode Select (and module enable).
000=Timer module not enabled. Associated I/O pin is in input state. All Timer operation is
completely disabled. Control and status registers are still accessible. This mode should be entered
when timer is to be re-configured, except where the user does not want the I/O pin to become an
input.
001=Timer enabled for input capture.
010=Timer enabled for output compare.
011=Timer enabled for PWM.
1xx=timer enabled for simple GPIO. Internal timer modes available. CE bit controls timer counter.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-69
System Integration Unit (SIU)
7.4.4.2
GPT0–GPT7 Counter Input Registers
Address MBAR + 0x0614, 0x0624, 0x0634, 0x0644, 0x0654, 0x0664, 0x0674
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Prescale
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Count
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-46. GPT0–GPT7 Counter Input Registers
Table 7-49. GPT0–GPT7 Counter Input Register Field Descriptions
Bit
Name
Description
0:15
Prescale
Prescale amount applied to internal counter (in IP bus clocks).
BE AWARE—The prescale field should be written prior to enabling any timer mode. A prescale of
0x0001 means one IP bus clock per count increment. If prescale is 0 when any timer mode is started,
it results in an effective prescale of 64K. The counter will immediately begin and an output event will
occur with the 64K prescale, rather than the desired value.
16:31
COUNT
Sets number of prescaled counts applied to reference events, as follows:
IC—Field has no effect, internal counter starts at 0.
OC—Number of prescaled counts counted before creating output event.
PWM—Number of prescaled counts defining the PWM output period.
Internal Timer—Number of prescaled counts counted before timer (or watchdog) expires.
Note: Reading this register only returns the programmed value, intermediate values of the internal
counter are not available to software.
MPC5200B User’s Manual, Rev. 3
7-70
Freescale Semiconductor
System Integration Unit (SIU)
7.4.4.3
GPT0–GPT7 PWM Configuration Registers
Address MBAR + 0x0608, 0x0618, 0x0628, 0x0638, 0x0648, 0x0658, 0x0678
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WIDTH
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
PWMOP
Reserved
LOAD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-47. GPT0–GPT7 PWM Configuration Registers
Table 7-50. GPT0–GPT7 PWM Configuration Register Field Descriptions
Bit
Name
0:15
WIDTH
16:22
—
23
PWMOP
24:30
—
31
LOAD
Description
PWM only. Defines ON time for output in prescaled counts. Similar to count value, which defines the
period. ON time overlays the period time.
If WIDTH = 0, output is always OFF.
If WIDTH exceeds count value, output is always ON.
ON and OFF polarity is set by the PWMOP bit.
Reserved
Pulse Width Mode Output Polarity—Defines PWM output polarity for OFF time. Opposite state is ON
time polarity. PWM cycles begin with ON time.
Reserved
Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with the
current count and width settings.
If LOAD = 0, new count or width settings are not updated until end of current period.
Note: Prescale setting is not part of this process. Changing prescale value while PWM is active causes
unpredictable results for the period in which it was changed. The same is true for PWMOP bit.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-71
System Integration Unit (SIU)
7.4.4.4
GPT0–GPT7 Status Registers
This is a read-only register.
Address MBAR + 0x061C, 0x062C, 0x063C, 0x064C, 0x065C, 0x066C, 0x067C
0
1
2
3
4
5
6
7
R
8
9
10
11
12
13
14
15
0
0
0
0
28
29
30
31
CAPTURE
W
Reset
0
0
16
17
0
0
0
0
0
18
19
20
21
22
OVF
R
0
0
0
0
0
23
24
25
26
27
PIN
Rsvd
TEXP PWMP COMP CAFT
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-48. GPT0–GPT7 Status Registers
Table 7-51. GPT0–GPT7 Status Register Field Descriptions
Bit
Name
Description
0:15
Capture
Read of internal counter, latch at reference event. This is pertinent only in IC mode, in which case it
represents the count value at the time the Input Event occurred. Capture status does not shadow the
internal counter while an event is pending, it is updated only at the time the Input Event occurs.
Note: If ICT is set to 11, which is Pulse Capture Mode, the Capture value records the width of the pulse.
Also, the Stop_Cont bit is irrelevant in Pulse Capture Mode, operation is as if Stop_Cont were 0.
16
—
17:19
OVF
20:22
—
23
PIN
24:27
—
28
TEXP
Timer Expired in Internal Timer mode. Cleared by writing 1 to this bit position. Also cleared if Timer_MS
is 000 (i.e., Timer not enabled). See Note.
29
PWMP
PWM end of period occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS is 000
(i.e., Timer not enabled). See Note.
30
COMP
OC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS is 000
(i.e., Timer not enabled). See Note.
31
CAPT
IC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS is 000
(i.e., Timer not enabled). See Note.
Reserved
Represents how many times internal counter has rolled over. This is pertinent only during IC mode and
would represent an extremely long period of time between Input Events. However, if Stop_Cont = 1
(indicating cumulative reporting of Input Events), this field could come into play.
Note: This field is cleared by any “sticky bit” status write in the 4 bit fields below (28, 29, 30, 31).
Reserved
Registered state of the I/O PIN (all modes). The IP bus Clock registers the state of the I/O input. Valid,
even if Timer is not enabled.
Reserved
Note: To clear any of these bits, it is necessary to clear all of them. An F must be written to bits 28:31.
MPC5200B User’s Manual, Rev. 3
7-72
Freescale Semiconductor
System Integration Unit (SIU)
7.5
Slice Timers
Two Slice Timers are included to provide shorter term periodic interrupts. Each timer consists of a 24-bit
counter with no prescale. Running off the IP bus clock, each timer can generate interrupts from 7.75uS to
508mS in 30nS steps (based on 33MHz IP bus clock). The counters count up from zero and
expire/interrupt when they reach the programmed terminal count. They can be configured to automatically
reset to zero and resume counting or wait until the Status/Interrupt is serviced before beginning a new
cycle.
The current count value can be read without disturbing the count operation. Each Slice Timer has a Status
bit to indicate the Timer has expired. If enabled, a CPU interrupt is generated at count expiration. Each
Timer has a separate Interrupt. Slice Timer 0 represents CPU interrupt Critical Level 2 and Slice Timer 1
represents Main Level 0 (which is hardwired to the core_smi pin). Clearing the Status and/or Interrupt is
accomplished by writing 1 to the Status bit, or disabling the Timer entirely with the Timer Enable (TE) bit.
As a safety, the Timer does not count until a Terminal Count value of greater than 255 is programmed into
it. Also, writing a Terminal Count value of 0 is converted to all 1s, resulting in a maximum duration
timeout.
7.5.1
SLT Registers
There are two SLT Timers. Each one uses four 32-bit registers. These registers are located at an offset from
MBAR of 0x0700. Register addresses are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0700 + register address.
Hyperlinks to the Interrupt Controller registers are provided below:
•
•
•
•
SLT0–SLT1 Terminal Count Registers (0x0700, 0x0710)
SLT0–SLT1 Control Field Registers (0x0704, 0x0714)
SLT0–SLT1 Count Value Registers (0x0708, 0x0718) read only
SLT0–SLT1 Timer Status Registers (0x070C, 0x071C) read only
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-73
System Integration Unit (SIU)
7.5.1.1
SLT0–SLT1 Terminal Count Registers
Address MBAR + 0x0700, 0x0710
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Terminal Count
W
Reset
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
R
Terminal Count
W
Reset
1
1
1
1
1
1
1
1
1
Figure 7-49. SLT0–SLT1 Terminal Count Registers
Table 7-52. SLT0– SLT1 Terminal Count Register Field Descriptions
Bit
Name
0:7
—
8:31
Terminal
Count
Description
Reserved
The user programs this register to set the Terminal Count value to be used by the Timer.
This register can be updated even if the Timer is running, the new value takes effect immediately. The
internal counter is compared to this register to determine if Terminal Count has been reached.
Note: The Timer will not begin counting until a value greater than 255 is programmed into the Terminal
Count Register. A value less than 255 will essentially suspend the Timer.
Writing a value of zero to this register is considered invalid and will be converted to all ones, creating a
maximum duration count period.
Defaults at reset: TerminalCount will default to all ones, all other control bits will default to zero.
MPC5200B User’s Manual, Rev. 3
7-74
Freescale Semiconductor
System Integration Unit (SIU)
7.5.1.2
SLT0–SLT1 Control Registers
Address MBAR + 0x0704, 0x0714
0
1
2
3
4
9
10
11
12
13
14
15
Timer
Enable
8
Interrupt
Enable
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Reserved
W
Reset
6
Run_Wait
R
5
Reserved
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-50. SLT0–SLT1 Control Field Registers
Table 7-53. SLT0–SLT1 Control Field Register Descriptions
Bit
Name
Description
0:4
—
5
Run_ Wait
A high indicates the Timer should run continuously while enabled. When the Timer counter reaches
terminal count it immediately resets to 0 and resumes counting. If the Run/Wait bit is set low, the Timer
Counter expires, but then waits until the Timer is cleared (either by writing 1 to the status bit or by
disabling and re-enabling the Timer), before resuming operation.
6
Interrupt
Enable
CPU Interrupt is generated only if this bit is high. This bit does not affect operation of the Timer Counter
or Status Bit registers.
7
Timer
Enable
8:32
—
Reserved
While this bit is high the Timer operates normally, while low the Timer is reset and remains idle.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-75
System Integration Unit (SIU)
7.5.1.3
SLT0–SLT1 Count Value Registers
Address MBAR + 0x0708, 0x0718
0
1
2
3
R
5
6
7
8
9
10
11
12
13
14
15
TimerCount
Reserved
W
Reset
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TimerCount
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-51. SLT0–SLT1 Count Value Registers
Table 7-54. SLT0– SLT1 Count Value Register Field Descriptions
Bit
Name
0:7
—
8:31
Timer
Count
7.5.1.4
Description
Reserved
Provides current state of the Timer counter. This register does not change while a read is in progress,
but the actual Timer counter continues unaffected.
SLT0–SLT1 Timer Status Registers
Address MBAR + 0x070C, 0x071C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ST
R
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-52. SLT0–SLT1 Timer Status Registers
Table 7-55. SLT0–SLT1 Timer Status Register Field Descriptions
Bit
Name
Description
0:6
—
Reserved
7
ST
This status bit goes high whenever the Timer has reached Terminal Count. The bit is cleared by writing
1 to its bit position. If Interrupts are enabled, clearing this status bit also clears the interrupt.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
7-76
Freescale Semiconductor
System Integration Unit (SIU)
7.6
Real-Time Clock
The Real-Time Clock (RTC) uses an external 32 kHz crystal to provide:
• Alarm
• Stop-watch
• Periodic interrupts
— Minute
— Second
— Midnight rollover (day)
The clock runs as long as power is maintained and the crystal is running, regardless of MPC5200B
power-down states.
The RTC module has the following features:
• Gull clock features
• Minute countdown timer—provides 256-minute capability, slightly over 4 hours
• Programmable alarm—operates on time of day only, not related to calendar
• Periodic interrupts for:
— 1 second
— 1 minute
— 1 day—operates only at midnight rollover
• Calendar features:
— Day
— Date
— Year
• Crystal support (32.768 kHz only)
RTC registers are writable, letting time and date be updated. If software enabled, RTC operates during all
MPC5200B power-down modes. At a reset, control registers are put in a default state such that no
interrupts generate until software enabled.
The RTC has two CPU interrupt signals connected to the Interrupt Controller, they are:
• RTC_Periodic, which is Main Level 5 fed by the Day, Minute, or Second sources.
• RTC_Stopwatch, which is Main Level 6 fed by the Alarm or Stopwatch sources.
Periodic interrupts are separately enabled by control bits, and a global enable must be asserted to allow
any of the periodic sources to generate a CPU interrupt. Clearing Periodic interrupts is accomplished by
writing 1 to the appropriate status bit.
Stopwatch and Alarm interrupts are enabled simply by initiating the function. In the Stopwatch case, this
means starting the Stopwatch, in the Alarm case, this means enabling the Alarm. Clearing Stopwatch or
Alarm interrupts is accomplished by writing 1 to the appropriate status bit.
Either of the RTC interrupts to the CPU can be used to awaken the MPC5200B from any power down
mode.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-77
System Integration Unit (SIU)
7.6.1
Real-Time Clock Signals
Table 7-56. Real-Time Clock Signals
Signal
I/O
Definition
RTC_XTAL_IN
I
Real-time Clock External Crystal/External Clock Input
RTC_XTAL_OUT
O
Real-time Clock External Crystal
Figure 7-53 shows a suggested circuit using an Epson ® MC-405 32.768KHz quartz crystal oscillator.
NOTE
External component values are highly dependent on the crystal. These
values will be different for different brands of crystals.
RTC_XTAL_IN
RTC_XTAL_OUT
R1
20 MΩ
MC-405
C1
12pF
R2
500 kΩ
C2
12pF
Figure 7-53. Diagram—Suggested Crystal Oscillator Circuit
7.6.2
Programming Note
Accesses to the RTC control registers are performed on the IP bus clock domain, but the RTC itself runs
on the (much) slower 32KHz crystal domain. When software initiates a setting of the Time and/or Date, it
must be realized that many IP bus clocks may go by before the setting actually takes effect. If this is a
system concern then it is recommended that software poll the Time and/or Date Status fields to confirm
the setting has occurred. This requires some careful bit manipulation of the expected status versus the
written control values, particularly if the output status is designated as 12-Hour format (input control
format is always 24-Hour).
It should be noted that updates to the RTC control registers, such as time and date set, must be
synchronized with the 32 kHz clock domain. It can take four 32KHz clock cycles for this synchronizing
hand shake to complete. Multiple time/date updates made within this four clock synchronizing period may
not be properly accepted by the RTC logic.
MPC5200B User’s Manual, Rev. 3
7-78
Freescale Semiconductor
System Integration Unit (SIU)
7.6.3
RTC Interface Registers
RTC uses 8 32-bit registers. These registers are located at an offset from MBAR of 0x0800. Register
addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x0800 + register
address.
Hyperlinks to the Interrupt Controller registers are provided below:
• RTC Time Set Register (0x0800)
• RTC Data Set Register (0x0804)
• RTC New Year and Stopwatch Register (0x0808)
• RTC Alarm and Interrupt Enable Register (0x080C)
• RTC Current Time Register (0x0810), read-only
• RTC Current Date Register (0x0814), read-only
• RTC Alarm and Stopwatch Interrupt Register (0x0818), read-only
• RTC Periodic Interrupt and Bus Error Register (0x081C), read-only
• RTC Test Register/Divides Register (0x0820)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-79
System Integration Unit (SIU)
7.6.3.1
RTC Time Set Register
Address MBAR + 0x0800
0
1
2
3
4
5
W
Reset
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
Reserved
0
0
Minute_set
0
0
0
0
SlctHour
pause_time
R
7
Reserved
Reserved
W
Reset
6
set_time
R
C24Hour_set
Reserved
0
0
0
0
Second_set
0
0
0
0
Figure 7-54. RTC Time Set Register
Table 7-57. RTC Time Set Register Field Descriptions
Bits
Name
0:5
—
6
set_time
Description
Reserved
A bit used in conjunction with pause_time bit (below) to cause a new time to be programmed into
the RTC. After a proper software sequence, the values in the *_set fields below are loaded.
The proper software sequence is:
1.
2.
3.
4.
Write register with pause_time 1 and set_time 0
Write register with pause_time 1 and set_time 1
Write register with pause_time 1 and set_time 0
Write register with pause_time 0 and set_time 0
At completion of Step 4, RTC is updated with the new time.
The C24Hour_set, Minute_set, and the Second_set fields should remain consistent values
throughout the four steps (i.e., at the desired new time values).
Note: Read-modify-write operations may disrupt this procedure, it is advised that four simple writes
occur. Byte writes to this byte are also acceptable.
7
pause_time
8:9
—
10
SlctHour
11:15
C24Hour_set
16:17
—
18:23
Minute_set
24:25
—
26:31
Second_set
Used with set_time above to perform time update. Must be zero for normal operation.
Reserved
This bit determines the hour output format.
• low bit = 24-hour format
• high bit = 12-hour format with AM/PM
Note: This bit does NOT affect time set procedure, it only affects how the Hour Status field is
presented.
Hour in 24-hour format written in RTC after successful state machine transition by set_time and
pause_time bits.
Note: This field is always written with 24-Hour format, it is NOT affected by SlctHour bit above.
Reserved
Minute written in RTC after successful state machine transition by set_time and pause_time bits.
Reserved
Second written in RTC after successful state machine transition by set_time and pause_time bits.
MPC5200B User’s Manual, Rev. 3
7-80
Freescale Semiconductor
System Integration Unit (SIU)
7.6.3.2
RTC Date Set Register
Address MBAR + 0x0804
2
3
4
5
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
R
Reserved
W
Reset
6
pause_date
1
set_date
0
Reserved
Month_set
R
Reserved
Weekday_set
Reserved
Day_set
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-55. RTC Data Set Register
Table 7-58. RTC Date Set Field Register Field Descriptions
Bits
Name
0:5
—
6
set_date
7
pause_date
8:10
—
11:15
Month_set
16:17
—
18:23
Weekday_set
24:25
—
26:31
Date_set
Description
Reserved
Operation of pause_date and set_date is similar to pause_time and set_time described in the time
set register.
Used with set_date above to perform date update. Must be zero for normal operation.
Reserved
New month written in RTC after successful state machine transition by set_date and pause_date
bits. Actually the lower 4 bits is used
Reserved
New weekday written in RTC after state machine transition by set_date and pause_date bits. 1 =
Monday; 7 = Sunday. Actually the lower 3 bits is used.
Reserved
New date written in RTC after state machine transition by set_date and pause_date bits. Actually
the lower 5 bits is used.
Note: Year_set in the following register is also part of the date set function.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-81
System Integration Unit (SIU)
7.6.3.3
RTC New Year and Stopwatch Register
Address MBAR + 0x0808
0
1
2
3
4
5
6
Reserved
W
Reset
8
9
10
11
write_SW
R
7
12
13
14
15
SW_set
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
Year_set
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 7-56. RTC New Year and Stopwatch Register
Table 7-59. RTC New Year and Stopwatch Register Field Descriptions
Bits
Name
0:6
—
7
write_SW
8:15
SW_set
16:19
—
20:31
Year_set
Description
Reserved
Typical stopwatch operation is to write initial value into 8-bit wide SW_set and assert write_SW bit.
The write_SW bit is immediately auto cleared, but it triggers the stopwatch minute countdown to
begin.
Number of minutes to be written into stopwatch. Max is 255, a little over 4 hours.
Reserved
New year written in RTC after successful state machine transition by set_date and pause_date bits.
Note: This is part of date set function in the previous register.
MPC5200B User’s Manual, Rev. 3
7-82
Freescale Semiconductor
System Integration Unit (SIU)
7.6.3.4
RTC Alarm and Interrupt Enable Register
Address MBAR + 0x0800, 0x080C
1
2
3
4
5
6
R
Reserved
8
9
10
11
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IntEn_min
IntEn_sec
Alm_24H_set
1
0
0
0
R
Reserved
Alm_Min_set
Reserved
W
Reset
13
IntEn_day
Reserved
12
MPEb
W
Reset
7
Alm_enable
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-57. RTC Alarm and Interrupt Enable Register
Table 7-60. RTC Alarm and Interrupt Enable Register Field Descriptions
Bits
Name
Description
0:6
—
7
Alm_enable
8:10
—
11:15
Alm_24Hset
16:17
—
18:23
Alm_Min_set
24:27
—
28
MPEb
29
IntEn_day
Enable bit of periodic interrupts at midnight rollover.
30
IntEn_min
Enable bit of periodic interrupts at minute rollover.
31
IntEn_sec
Enable bit of periodic interrupts at second rollover.
Reserved
Alarm Enable bit for once-a-day Alarm. If high, Alarm status/interrupt operation is enabled. If low,
Alarm setting is not compared to time of day.
Reserved
Hour setting (in 24 hour format) to be compared to time of day for the purpose of generating Alarm
Status/Interrupt. Can be written at any time.
Reserved
Minute setting to be compared to time of day for the purpose of generating Alarm Status/Interrupt.
Can be written at any time.
Reserved
Master Periodic Enable bar. Must be written low after reset to allow periodic interrupts.
Note: The Interrupt enable bits (28, 29, 30, 31) control the Periodic Interrupt coming from the RTC. The separate
Stopwatch/Alarm Interrupt signal does not have a specific interrupt enable bit. An Alarm interrupt is automatically
generated if Alarm is enabled and the Alarm setting matches time of day. Similarly, a Stopwatch expiration, which shares
the Alarm interrupt signal, automatically occurs once the Stopwatch is initiated and the Stopwatch counter expires.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-83
System Integration Unit (SIU)
7.6.3.5
RTC Current Time Register
This is a read-only register.
Address MBAR + 0x0810
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Hour
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
Minute
R
Second
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-58. RTC Current Time Register
Table 7-61. RTC Current Time Register Field Descriptions
Bits
Name
0:10
—
11:15
Hour
16:17
—
18:23
Minute
24:25
—
26:31
Second
Description
Reserved
Hour format can be either 24-hour or 12-hour with AM/PM.
If 24-hour format is selected (SlctHour low in Reg 0), the whole 5-bit hour field designates current
time in 24-hour format.
If 12-hour format is selected (SlctHour high in Reg 0), the MSB of hour field indicates:
• Hour[0]=0: AM,
• Hour[0]=1: PM and
• Hour[1:4] designates current time in 12-hour format.
Reserved
Shows minutes in current time.
Reserved
Shows seconds in current time.
MPC5200B User’s Manual, Rev. 3
7-84
Freescale Semiconductor
System Integration Unit (SIU)
7.6.3.6
RTC Current Date Register
This is a read-only register.
Address MBAR + 0x0814
0
1
2
3
4
5
6
7
8
Month
R
9
10
11
12
Weekday
13
14
15
Day
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
0
0
0
0
0
0
26
27
28
29
30
31
0
0
0
0
0
Year
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 7-59. RTC Current Date Register
Table 7-62. RTC Current Date Register Field Descriptions
Bits
Name
0:3
—
4:7
Month
8:10
Weekday
11:15
Date
16:19
—
20:31
Year
Description
Reserved
Shows current month. 1 = January; 12 = December
Indicates day of week. (Monday = 1, Sunday = 7)
Shows current date. Calendar feature is implemented, therefore, day rollover at the end of month
including February (and Leap Years) is automatic.
Reserved
Shows current year. Max is 4052.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-85
System Integration Unit (SIU)
7.6.3.7
RTC Alarm and Stopwatch Interrupt Register
This is a read-only register.
Address MBAR + 0x0818
2
3
4
5
6
7
8
9
10
R
Reserved
11
12
13
14
15
Int_SW
1
Int_alm
0
Reserved
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
Alm_status
Reset
R
Reserved
SW_min
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-60. RTC Alarm and Stopwatch Interrupt Register
Table 7-63. RTC Alarm and Stopwatch Interrupt Register Field Descriptions
Bits
Name
0:6
—
7
Int_alm
8:14
—
15
Int_SW
16:22
—
23
Alm_status
24:31
SW_min
Description
Reserved
Status bit indicating that enabled once-a-day Alarm has occurred (active high). Alarm interrupt has
been activated. This bit and the Interrupt is cleared by writing 1 to this bit position.
Note: A Stopwatch interrupt, if also active, must be cleared before the interrupt signal to the CPU is
negated.
Reserved
Status bit indicating that Stopwatch expiration has occurred (active high). Stopwatch interrupt has
been activated. This bit and the Interrupt are cleared by writing 1 to this bit position.
Note: An Alarm interrupt, if also active, must be cleared before the interrupt signal to the CPU is
negated.
Reserved
Status bit indicating that once-a-day Alarm has occurred. Same as Int_alm bit above except that
clearing this bit does NOT clear the interrupt.
Minutes remaining in stopwatch.
MPC5200B User’s Manual, Rev. 3
7-86
Freescale Semiconductor
System Integration Unit (SIU)
7.6.3.8
RTC Periodic Interrupt and Bus Error Register
This is a read-only register.
Address MBAR + 0x081C
2
3
4
5
6
7
8
9
10
R
Reserved
11
12
13
14
15
Int_day
1
Bus_error_1
0
Reserved
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Reserved
Int_sec
0
Int_min
Reset
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-61. RTC Periodic Interrupt and Bus Error Register
Table 7-64. RTC Periodic Interrupt and Bus Error Register Field Descriptions
Bits
Name
0:6
—
7
Bus_error_1
8:14
—
15
Int_day
16:22
—
23
Int_min
24:30
—
31
Int_sec
Description
Reserved
Internal status register—If high, indicates software has attempted a write access to a read-only
register in this module. No actual register contents are corrupted if this happens.
Cleared by writing 1 to this bit position.
Reserved
Periodic interrupt at midnight. High indicates interrupt has occurred.
OR’d function of Int_day, Int_min and Int_sec produces RTC periodic interrupt to CPU interface.
Cleared by writing 1 to this bit position.
Reserved
Periodic interrupt at each minute rollover. High indicates interrupt has occurred.
Cleared by writing 1 to this bit position.
Reserved
Periodic interrupt at each second rollover. High indicates interrupt has occurred.
Cleared by writing 1 to this bit position.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
7-87
System Integration Unit (SIU)
7.6.3.9
RTC Test Register/Divides Register
This register is used during manufacturing test to expedite RTC testing and is not intended to be a user
register. However, no protection from software access is provided.
Address MBAR + 0x0820
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
PTERM
ETERM
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 7-62. RTC Test Register/Divides Register
Table 7-65. RTC Test Register/Divides Register Field Descriptions
Bit
Name
Description
0
—
1:7
PTERM
Prescale Termination value, the number of 32KHz clocks per 7-bit prescale counter.
Default at reset is the maximum (and proper) value of 128 decimal. Any value lower than this
causes the RTC to run fast.
8:15
ETERM
External Termination value, the number of prescaled counts per 8-bit external counter.
Default at reset is the maximum (and proper) value of 256 decimal. Any value lower than this
causes the RTC to run fast.
16:31
—
Reserved
Reserved
Note: The 32.768KHz crystal frequency is divided by PTERM, which is then divided by ETERM to produce a 1 second time
interval. It is conceivable that a system might wish to adjust these values to produce a more locally accurate clock rate.
However, be aware that these values are affected by reset. Therefore, any adjustment value must be stored and retrieved
from non-volatile memory. Further, the adjustment could only increase the clock rate, not decrease it.
MPC5200B User’s Manual, Rev. 3
7-88
Freescale Semiconductor
Chapter 8
SDRAM Memory Controller
8.1
Overview
The following sections are contained in this document:
• Terminology and Notation
• Features
— Devices Supported
• Functional Description
— External Signals (SDRAM Side)
— Block Diagram
— Transfer Size
— Commands
• Operation
— Power-Up Initialization
• Programming the SDRAM Controller
• Memory Controller Registers
8.2
Terminology and Notation
Synchronous DRAM devices (SDR-SDRAM, DDR-SDRAM) are organized internally as columns by
rows by “banks”. Older type asynchronous DRAMs (FP, EDO) had rows and columns, but no internal
banks. Historically, the word “bank” was often used to refer to the set of memory devices all activated for
the same address range (same RAS). To avoid confusion between these two meanings of “bank”, this
document uses the term “bank” for the internal banks of an SDRAM device, and the term “space” to
indicate the memory device(s) activated for a common address range (same CS).
8.2.1
“Endian”-ness
Endian-ness is a source of seemingly endless confusion, yet it need not be. The source of the confusion
usually seems to be that bit number and/or byte address are improperly equated with significance. In fact,
bit number and byte address neither govern, nor imply, significance.
• Significance can only exist within an arithmetic context. An arithmetic context can be explicit or
implicit.
• An explicit arithmetic context is the scope of an arithmetic operator, that is, the operand(s) and
result(s).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-1
SDRAM Memory Controller
•
•
•
An implicit arithmetic context exists within any collection of bits representing an atomic arithmetic
object, that is, a number. Significance does not extend beyond the boundaries of the bit range.
With a single exception, an arithmetic context, and therefore significance, can only exist within an
execution context, that is, an abstract process or the actual hardware to which it is mapped. The
single exception is an implicit context: A byte is an implicit arithmetic context.
Within an atomic object bj[m:n], in an arithmetic context, the most significant bit(byte) is on the
left (m), and the least significant bit(byte) is on the right (n), unless otherwise specified. The bit
numbering and byte addressing order from left to right (ascending or descending) is strictly
cosmetic.
Note that “:” in “m:n” is an arithmetic operator, and therefore m and n are arithmetic objects within
the operator scope. (If they weren’t, then the terms “ascending” and “descending” would be
meaningless.)
Note furthermore that the scope of the “:” operator does not include “obj”: obj could be of a
non-arithmetic type. One particular value (pattern of the bit range) of obj could represent “red”;
another value might represent “cold”. The bit patterns are enumerations of the legal values of obj;
sometimes arithmetic operations on enumeration values are valid for the concepts they represent,
sometimes not.
An enumeration value is not an arithmetic context. An enumeration value is a representation of an
object value; the nature of the object itself need not be numeric.
The enumeration value of a collection of bits (e.g. process variable) is only meaningful in the context of
a process which manipulates those bits in a manner consistent with the concept they represent. (A process
itself may be just a concept represented by a collection of bits manipulated (by a processing unit) in a
manner consistent with the concept they represent.) And in the context of the concept they represent, bits
and bytes may have significance.
But while transporting bits from one location to another, the hardware transport media almost never have
any knowledge of the concepts represented by the data, or the contexts in which they are valid (this does
not include protocol bits of the media, which may be added and stripped along the way). Nor is the
transportation of data an execution context. Without knowledge of atom boundaries and significance (if
any), the following convention is the de facto standard:
• “Bit significance, byte address”: From every observation point in a system, the relative address
order of bytes shall be maintained, and the relative significance of bits within each individual byte
shall be maintained, as if they represented an 8 bit unsigned binary integer. This is the implicit
arithmetic context of bytes. The “native” bit numbering and address significance order of different
observers shall have no bearing on the byte address or bit significance order of visible data.
Byte “swapping”, the intentional transposition of bytes’ relative addresses between a source and a
destination to maintain inter-byte significance, is improper.
Bit “swizzling”, the intentional renumbering of bit positions, is perfectly legal if necessary to
maintain intra-byte bit significance or inter-byte address order. When necessary, it is required;
when not necessary, it is prohibited.
To correctly join data path segments in accordance with this convention, the bit significance and byte
addressing of each segment must be specified.
MPC5200B User’s Manual, Rev. 3
8-2
Freescale Semiconductor
SDRAM Memory Controller
In this document, significance is always msb on the left, lsb on the right, if any significance relationship
exists.
All multi-bit components of the internal XL bus are defined with bit numbers and byte addresses (if any)
ascending from left to right: XLA[0:31], XLD[0:63]. The address of byte XLD[0:7] is a modulo 8
boundary, 8n (0x00, 0x08, 0x10, 0x18); the address of byte XLD[56:63] is a modulo 8 boundary plus offset
7, 8n+7 (0x07, 0x0F, 0x17, 0x1F).
All internal IP busses are defined with bit numbers descending from left to right: IPA[31:0], IPD[31:0].
The byte addresses of IPD[31:0] are defined ascending from left to right: IPD[31:24] is a modulo 4 address
boundary, 4n (0x00, 0x04, 0x08, 0x0C); IPD[7:0] is a modulo 4 address boundary plus offset 3, 4n+3
(0x03, 0x07, 0x0B, 0x0F). IPA[31:0] correspond left-to-right with XLA[0:31]. IPD[31:0] correspond
left-to-right with XLD[0:31] (XLA[29] == 0) or XLD[32:63] (XLA[29] == 1).
The Memory Controller registers are defined with byte addresses and bus bit numbers ascending from left
to right; but object bit fields within the registers may have ascending or descending bit numbers. The
numbering order of bits as a bus does not govern the numbering order of bits within a data object.
All external memory interface busses are defined with descending bit numbers: MEM_MA[12:0],
MEM_MBA[1:0], MEM_MDQ[31:0], MEM_DQM[3:0], MEM_MDQS[3:0]. Byte addressing of
MEM_MDQ[31:0], MEM_DQM[3:0], and MEM_MDQS[3:0] is ascending: MEM_MDQ[31:24],
MEM_DQM[3], and MEM_MDQS[3] are associated with address offset 0 modulo 4 (4n);
MEM_MDQ[7:0], MEM_DQM[0], and MEM_MDQS[0] are associated with address offset 3 modulo 4
(4n+3).
8.3
Features
The MPC5200B SDRAM Memory Controller has the following features:
• Supports either:
— SDR SDRAM—memory I/Os are powered at 3.3V
— DDR SDRAM—memory I/Os are powered at 2.5V
DDR SDRAM transfers data at twice the rate and uses MEM_CLK and MEM_CLK as a
differential pair.
• 32-bit memory data bus
• 16-bit memory data bus (connected only to upper half, bits 31-16, of the data bus).
• Maximum address space 512MB; 256MB per CS, 32-bit memory data bus:
— Up to 13 bits of row address (RA[12:0])
— Up to 12 bits of column address (CA[11:0])
— 2 bits of bank address (BA[1:0])
— Cannot use all 13 bits of RA and all 12 bits of CA at the same time. Maximum total address
bits (RA+CA+BA) ≤ 26; 26 address bits x 4Byte data bus = 256MB.
NOTE
In this document the Auto Precharge control signal (A10 usually), conveyed
on the memory address bus along with column address, is never included in
the stated CA width; it is always in addition to the CA width.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-3
SDRAM Memory Controller
The Memory Controller does not support memory devices with >8 CA bits,
but <13 RA bits.
RA[12:0] correspond directly with MEM_MA[12:0]. CA[7:0] correspond
directly with MEM_MA[7:0]. CA[11:8] do not correspond directly with
MEM_MA[12:8].
•
Maximum address space 512MB; 256MB per CS, 16-bit memory data bus:
— Up to 13 bits of row address (RA[12:0])
— Up to 13 bits of column address (CA[12:0])
— 2 bits of bank address (BA[1:0])
NOTE
In this document the Auto Precharge control signal (A10 usually), conveyed
on the memory address bus along with column address, is never included in
the stated CA width; it is always in addition to the CA width.
The Memory Controller does not support memory devices with >9 CA bits,
but <13 RA bits.
RA[12:0] correspond directly with MEM_MA[12:0]. CA[7:0] correspond
directly with MEM_MA[7:0]. CA[11:8] do not correspond directly with
MEM_MA[12:8].
•
Maximum of 2 pinned-out Chip Selects (CS).
— CS0 is pinned out all the time (i.e., a dedicated pin).
— CS1 is only available if the GPIO_WKUP6 pin is programmed to be an SDRAM chip select.
The default function of the pin is GPIO_WKUP6.
— To configure the GPIO_WKUP6 pin as SDRAM chip select, write 1 to the Port Configuration
register msb.GPS Port Configuration Register
NOTE
The GPIO_WKUP_6 pin, which can be programmed as CS1 for the
SDRAM bus, is powered by the Memory Vdd supply. When using Single
Data Rate SDRAMS, the Memory Vdd supply is 3.3 volts. When using
Double Data Rate SDRAMs, the Memory Vdd supply is 2.5 volts.
If GPIO_WKUP_6 is used as a GPIO pin (as opposed to CS1), the input
levels must be appropriate for the voltage on the Memory Vdd supply. For
instance, if DDR memory is used which requires a Vdd_mem supply of 2.5
volts, then logic levels applied to GPIO_WKUP_6 must not exceed 2.5
volts.
— The size of each CS space is independent. It is possible but not recommended to overlap the
address space pointed to by the 2 independent chip select.
NOTE
Maximum 4 physical memory devices total, all CS.
MPC5200B User’s Manual, Rev. 3
8-4
Freescale Semiconductor
SDRAM Memory Controller
•
Minimum allocatable address space 1MB:
— 8 bits of row address;
— 8 bits of column address for 32-bit interface, 9 bits of column address for 16-bit interface;
— 2 bits of bank address;
— 1 chip select;
NOTE
Minimum allocatable address space is much smaller (8Mb) than the lowest
density available (64Mb). Excess memory bits are not used or simply
wasted.
•
•
•
•
32 Byte PowerPC e300 critical word first burst transfer;
Supports PowerPC e300 bus, 2-stage address/data pipeline (one data tenure in progress, one
pipelined address tenure);
Supports SDRAM Power Down and Self Refresh modes;
Supports page mode and bursting to maximize the data rate;
NOTE
The SDRAM Memory Controller (MC) does not support error detect or
parity check.
8.3.1
Devices Supported
Supported SDRAM devices (SDR and DDR both) are:
• 64Mbit;
• 128Mbit;
• 256Mbit;
• 512Mbit;
• 1Gbit when available, assuming the same interface style;
• 2Gbit when available, assuming the same interface style;
The MPC5200B limits external memory to a maximum of 4 memory chips placed within 5 cm of the
MPC5200B processor. Flight delay on the board should be no more than 0.5 ns each way, and all signals
must be matched. The maximum load is 20pF/pin.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-5
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 1 of 6)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
11
8
2
12
8
2
Physical
Address Range
1
1 x 64Mb
512K x 4bank x 32bit
8MB
2
2 x 64Mb
512K x 4bank x 32bit
16MB
1
2 x 64Mb
1M x 4bank x 16bit
16MB
1 x 128Mb
1M x 4bank x 32bit
2
4 x 64Mb
1M x 4bank x 16bit
32MB
2 x 128Mb
1M x 4bank x 32bit
12
13
9
8
2
2
1
4 x 64Mb
2M x 4bank x 8bit
32MB
2 x 128Mb
2M x 4bank x 16bit
1 x 256Mb
2M x 4bank x 32bit
2
4 x 128Mb
2M x 4bank x 16bit
64MB
2 x 256Mb
2M x 4bank x 32bit
12
13
10
9
2
2
1
4 x 128Mb
4M x 4bank x 8bit
64MB
2 x 256Mb
4M x 4bank x 16bit
1 x 512Mb
4M x 4bank x 32bit
2
4 x 256Mb
4M x 4bank x 16bit
128MB
2 x 512Mb, 2 CS
4M x 4bank x 32bit
12
13
11
10
2
2
1
4 x 256Mb
8M x 4bank x 8bit
128MB
2 x 512Mb
8M x 4bank x 16bit
1 x 1Gb
8M x 4bank x 32bit
2
4 x 512Mb
8M x 4bank x 16bit
256MB
2 x 1Gb
8M x 4bank x 32bit
MPC5200B User’s Manual, Rev. 3
8-6
Freescale Semiconductor
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 2 of 6)
Row Bits
Column Bits
Bank Bits
12
13
12
11
2
2
Spaces
(CS)
1
Physical
Address Range
4 x 512Mb
16M x 4bank x 8bit
256MB
2 x 1Gb
16M x 4bank x 16bit
1 x 2Gb
16M x 4bank x 32bit
2
4 x 1Gb
16M x 4bank x 16bit
512MB
2 x 2Gb
16M x 4bank x 32bit
11
8
2
1
1 x 64Mb
512K x 4bank x 32bit
24MB
+
12
8
2
1
1 x 128Mb
1M x 4bank x 32bit
11
8
2
1
1 x 64Mb
512K x 4bank x 32bit
40MB
+
12
13
9
8
2
1
1 x 256Mb
2M x 4bank x 32bit
11
8
2
1
1 x 64Mb
512K x 4bank x 32bit
72MB
+
12
13
10
9
2
1
1 x 512Mb
4M x 4bank x 32bit
11
8
2
1
1 x 64Mb
512K x 4bank x 32bit
136MB
+
12
13
11
10
2
1
1 x 1Gb
8M x 4bank x 32bit
11
8
2
1
1 x 64Mb
512K x 4bank x 32bit
264MB
+
12
13
12
11
2
1
1 x 2Gb
16M x 4bank x 32bit
12
8
2
1
2 x 64Mb
1M x 4bank x 16bit
48MB
+
12
13
9
8
2
1
2 x 128Mb
2M x 4bank x 16bit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-7
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 3 of 6)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
12
8
2
1
Physical
Address Range
2 x 64Mb
1M x 4bank x 16bit
80MB
+
12
13
10
9
2
1
2 x 256Mb
4M x 4bank x 16bit
12
8
2
1
2 x 64Mb
1M x 4bank x 16bit
144MB
+
12
13
11
10
2
1
2 x 512Mb
8M x 4bank x 16bit
12
8
2
1
2 x 64Mb
1M x 4bank x 16bit
272MB
+
12
13
12
11
2
1
2 x 1Gb
16M x 4bank x 16bit
12
8
2
1
1 x 128Mb
1M x 4bank x 32bit
48MB
+
12
13
9
8
2
1
1 x 256Mb
2M x 4bank x 32bit
12
8
2
1
1 x 128Mb
1M x 4bank x 32bit
80MB
+
12
13
10
9
2
1
1 x 512Mb
4M x 4bank x 32bit
12
8
2
1
1 x 128Mb
1M x 4bank x 32bit
144MB
+
12
13
11
10
2
1
1 x 1Gb
8M x 4bank x 32bit
12
8
2
1
1 x 128Mb
1M x 4bank x 32bit
272MB
+
12
13
12
11
2
1
1 x 2Gb
16M x 4bank x 32bit
12
9
2
1
2 x 128Mb
2M x 4bank x 16bit
96MB
+
12
10
2
1
2 x 256Mb
4M x 4bank x 16bit
MPC5200B User’s Manual, Rev. 3
8-8
Freescale Semiconductor
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 4 of 6)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
13
8
2
1
Physical
Address Range
2 x 128Mb
2M x 4bank x 16bit
96MB
+
13
9
2
1
2 x 256Mb
4M x 4bank x 16bit
12
9
2
1
2 x 128Mb
2M x 4bank x 16bit
160MB
+
12
11
2
1
2 x 512Mb
8M x 4bank x 16bit
13
8
2
1
2 x 128Mb
2M x 4bank x 16bit
160MB
+
13
10
2
1
2 x 512Mb
8M x 4bank x 16bit
12
9
2
1
2 x 128Mb
2M x 4bank x 16bit
288MB
+
12
12
2
1
2 x 1Gb
16M x 4bank x 16bit
13
8
2
1
2 x 128Mb
2M x 4bank x 16bit
288MB
+
13
11
2
1
2 x 1Gb
16M x 4bank x 16bit
12
9
2
1
1 x 256Mb
2M x 4bank x 32bit
96MB
+
12
10
2
1
1 x 512Mb
4M x 4bank x 32bit
13
8
2
1
1 x 256Mb
2M x 4bank x 32bit
96MB
+
13
9
2
1
1 x 512Mb
4M x 4bank x 32bit
12
9
2
1
1 x 256Mb
2M x 4bank x 32bit
160MB
+
12
11
2
1
1 x 1Gb
8M x 4bank x 32bit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-9
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 5 of 6)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
13
8
2
1
Physical
Address Range
1 x 256Mb
2M x 4bank x 32bit
160MB
+
13
10
2
1
1 x 1Gb
8M x 4bank x 32bit
12
9
2
1
1 x 256Mb
2M x 4bank x 32bit
288MB
+
12
12
2
1
1 x 2Gb
16M x 4bank x 32bit
13
8
2
1
1 x 256Mb
2M x 4bank x 32bit
288MB
+
13
11
2
1
1 x 2Gb
16M x 4bank x 32bit
12
10
2
1
2 x256Mb
4M x 4bank x 16bit
192MB
+
12
11
2
1
2 x 512Mb
8M x 4bank x 16bit
13
9
2
1
2 x256Mb
4M x 4bank x 16bit
192MB
+
13
10
2
1
2 x 512Mb
8M x 4bank x 16bit
12
10
2
1
2 x256Mb
4M x 4bank x 16bit
320MB
+
12
12
2
1
2 x 1Gb
16M x 4bank x 16bit
13
9
2
1
2 x256Mb
4M x 4bank x 16bit
320MB
+
13
11
2
1
2 x 1Gb
16M x 4bank x 16bit
12
10
2
1
1 x 512Mb
4M x 4bank x 32bit
192MB
+
12
11
2
1
1 x 1Gb
8M x 4bank x 32bit
MPC5200B User’s Manual, Rev. 3
8-10
Freescale Semiconductor
SDRAM Memory Controller
Table 8-1. 32-Bit External Data Width Legal Memory Configurations (Sheet 6 of 6)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
13
9
2
1
Physical
Address Range
1 x 512Mb
4M x 4bank x 32bit
192MB
+
13
10
2
1
1 x 1Gb
8M x 4bank x 32bit
12
10
2
1
1 x 512Mb
4M x 4bank x 32bit
320MB
+
12
12
2
1
1 x 2Gb
16M x 4bank x 32bit
13
9
2
1
1 x 512Mb
4M x 4bank x 32bit
320MB
+
13
11
2
1
1 x 2Gb
16M x 4bank x 32bit
12
10
2
1
2 x 512Mb
8M x 4bank x 32bit
384MB
+
12
12
2
1
2 x 1Gb
16M x 4bank x 32bit
13
9
2
1
2 x 512Mb
8M x 4bank x 32bit
384MB
+
13
11
2
1
2 x 1Gb
16M x 4bank x 32bit
12
11
2
1
1 x 1Gb
8M x 4bank x 32bit
384MB
+
12
12
2
1
1 x 2Gb
16M x 4bank x 32bit
13
10
2
1
1 x 1Gb
8M x 4bank x 32bit
384MB
+
13
11
2
1
1 x 2Gb
16M x 4bank x 32bit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-11
SDRAM Memory Controller
Table 8-2. 16-Bit External Data Width Legal Memory Configurations (Sheet 1 of 4)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
12
10
2
1
Physical
Address Range
2 x 128Mb
4M x 4bank x 8bit
32MB
1 x 256Mb
4M x 4bank x 16bit
2
4 x 64Mb
1M x 4bank x 16bit
32MB
2 x 128Mb
1M x 4bank x 32bit
12
9
2
1
2 x 64Mb
2M x 4bank x 8bit
16MB
1 x 128Mb
2M x 4bank x 16bit
2
4 x 64Mb
2M x 4bank x 8bit
32MB
2 x 128Mb
2M x 4bank x 16bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
32MB
1 x 256Mb
4M x 4bank x 16bit
2
4 x 128Mb
4M x 4bank x 8bit
64MB
2 x 256Mb
4M x 4bank x 16bit
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
64MB
1 x 512Mb
8M x 4bank x 16bit
2
4 x 256Mb
8M x 4bank x 8bit
128MB
2 x 512Mb
8M x 4bank x 16bit
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
128MB
1 x 1Gb
16M x 4bank x 16bit
2
4 x 512Mb
16M x 4bank x 8bit
256MB
2 x 1Gb
16M x 4bank x 16bit
12
9
2
1
2 x 64Mb
2Mx 4bank x 8bit
32MB
+
12
9
2
1
1 x 128Mb
2M x 4bank x 16bit
MPC5200B User’s Manual, Rev. 3
8-12
Freescale Semiconductor
SDRAM Memory Controller
Table 8-2. 16-Bit External Data Width Legal Memory Configurations (Sheet 2 of 4)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
12
9
2
12
10
12
9
Physical
Address Range
1
2 x 64Mb
2Mx 4bank x 8bit
48MB
2
1
2 x 128Mb
4M x 4bank x 8bit
2
1
2 x 64Mb
2Mx 4bank x 8bit
+
48MB
+
13
9
2
1
1 x 256Mb
4M x 4bank x 16bit
12
9
2
1
2 x 64Mb
2Mx 4bank x 8bit
80MB
+
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
12
9
2
1
2 x 64Mb
2Mx 4bank x 8bit
80MB
+
13
10
2
1
1 x 512Mb
8M x 4bank x 16bit
12
9
2
1
2 x 64Mb
2M x 4bank x 8bit
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
12
9
2
1
2 x 64Mb
2M x 4bank x 8bit
144MB
+
144MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
12
9
2
1
1 x 128Mb
2M x 4bank x 16bit
48MB
+
13
9
2
1
1 x 256Mb
4M x 4bank x 16bit
12
9
2
1
1 x 128Mb
2M x 4bank x 16bit
80MB
+
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-13
SDRAM Memory Controller
Table 8-2. 16-Bit External Data Width Legal Memory Configurations (Sheet 3 of 4)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
12
9
2
13
10
12
9
Physical
Address Range
1
1 x 128Mb
2M x 4bank x 16bit
80MB
2
1
1 x 512Mb
8M x 4bank x 16bit
2
1
1 x 128Mb
2M x 4bank x 16bit
+
144MB
+
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
12
9
2
1
1 x 128Mb
2M x 4bank x 16bit
144MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
64MB
+
13
9
2
1
1 x 256Mb
4M x 4bank x 16bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
64MB
+
80MB
+
13
10
2
1
1 x 512Mb
8M x 4bank x 16bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
160MB
+
13
11
2
1
2 x 256Mb
16M x 4bank x 8bit
12
10
2
1
2 x 128Mb
4M x 4bank x 8bit
160MB
+
13
11
2
1
1 x Gb
16M x 4bank x 16bit
MPC5200B User’s Manual, Rev. 3
8-14
Freescale Semiconductor
SDRAM Memory Controller
Table 8-2. 16-Bit External Data Width Legal Memory Configurations (Sheet 4 of 4)
Row Bits
Column Bits
Bank Bits
Spaces
(CS)
13
9
2
13
10
13
9
Physical
Address Range
1
1 x 256Mb
4M x 4bank x 16bit
96MB
2
1
1 x 512Mb
8M x 4bank x 16bit
2
1
1 x 256Mb
4M x 4bank x 16bit
+
160MB
+
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
13
9
2
1
1 x 256Mb
4M x 4bank x 16bit
160MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
128MB
+
13
10
2
1
1 x 512Mb
8M x 4bank x 16bit
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
13
10
2
1
2 x 256Mb
8M x 4bank x 8bit
192MB
+
192MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
13
10
2
1
1 x 512Mb
8M x 4bank x 16bit
192MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
13
11
2
1
2 x 512Mb
16M x 4bank x 8bit
256MB
+
13
11
2
1
1 x 1Gb
16M x 4bank x 16bit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-15
SDRAM Memory Controller
Figure 8-1 shows an example memory configuration of 1 space (CS) of 4 devices of 128Mbit (4M x 4
banks x 8bit) DDR SDRAM, for a total memory size of 64MB.
7:0
Glue
A_CS
D_CS
SDRAM
Memory Controller
A_CS
D_CS
R/W
DM[0:7]
R/W
DM_I[0:7]
REG_CS
REG_CS
REGD_CS
processor bus
DQ[31:0]
BA[1:0]
CLK
CLK
CKE
0
0
DQ[7:0]
BA[1:0]
15:8
DQ[7:0]
BA[1:0]
CLK
CLK
CLK
CKE
CS
RAS
CLK
CKE
CS
RAS
CAS
DQS
DM
A[11:0]
1
1
WE
CAS
DQS
DM
A[11:0]
WE
REGD_CS
DI[0:63]
ADDR[4:29]
AACK
ARTRY
TBST
DO[0:63]
TA
RESET
CLK
CS[0]
CS[1]
RAS
CAS
DQS[3:0]
DM[3:0]
MA[11:0]
A[11:0]
WE
DQ[31:0]
23:16
Note: For 16-Bit External Data Width,
mem_ps = 1, only DQ[31:16] should
be connected to the external memories.
2
2
31:24
DQ[7:0]
BA[1:0]
DQ[7:0]
BA[1:0]
CLK
CLK
CLK
CKE
CS
RAS
CLK
CKE
CS
RAS
CAS
DQS
DM
A[11:0]
WE
3
3
CAS
DQS
DM
A[11:0]
WE
Figure 8-1. Block Diagram—SDRAM Subsystem Example
Both chip selects contribute together to access the whole memory. Each CS base address and size are
programmed independently. Each CS base address must be size-aligned.
The MPC5200B does not support DIMM memory modules, however it can support a DIMM-compatible
EEPROM using an on-chip I2C chip interface (with appropriate configuration of pin functions).
MPC5200B User’s Manual, Rev. 3
8-16
Freescale Semiconductor
SDRAM Memory Controller
8.4
Functional Description
8.4.1
External Signals (SDRAM Side)
Table 8-3. SDRAM External Signals
Signal Name
Description
Outputs
MEM_CLK
Memory Clock (frequency is the same as the internal XL bus clock). Maximum allowed value is
132 MHz.
MEM_CLK
Inverted Memory Clock, used for DDR-SDRAM devices.
Internally generated “DQS” for SDR-SDRAM devices.
MEM_CLK_EN
MEM_CS[0],
MEM_CS[1]
Memory Clock Enable (CKE). When low, the SDRAM is disabled. Used to switch memory into and
out of self-refresh/power-down modes.
Memory Command Select. Each space has a command select to enable commands
MEM_RAS
Memory Row Address Select
MEM_CAS
Memory Column Address Select
MEM_WE
Memory Write Enable
MEM_MA[12:0]
Memory Multiplexed Address. These are used as row address, column address, or
Mode(Extended Mode) register data, depending on the command issued.
Row address during Active command.
Column address during Read and Write commands. MEM_MA10 is used as a control signal
instead of an address line, to control Auto Precharge operation. The Auto Precharge control bit is
not counted as a column address bit. The Memory Controller does not use Auto Precharge.
Mode register data during Load Mode Register and Load Extended Mode Register (DDR only)
commands.
MEM_MBA[1:0]
Memory Bank Address, or Mode register select, depending on the command issued.
Bank address during Precharge Selected, Active, Read, and Write commands. The Memory
Controller does not use the Precharge Selected command.
Mode register select during Load Mode Register and Load Extended Mode Register (DDR only)
commands. Although SDR memory only has a single internal Mode register, the Bank Address
bits must still be valid.
MEM_DQM[3:0]
Memory Data Mask. Addressing = 0:3
0 Data byte read/write is enabled
1 Data byte read/write is inhibited
SDR memories 3-state inhibited data during reads; DDR memories ignore Data Mask during
reads. The memory controller never masks read data.
Bidirectional Signals
MEM_MDQ[31:0]
Memory Data. Addressing = 0:3.
MEM_MDQS[3:0]
Memory Data Strobe, DDR only. Addressing = 0:3.
Note: Signals MEM_RAS, MEM_CAS, MEM_WE, and MEM_CLK_EN encode the SDRAM commands to control the different
SDRAM operations.
Note: For 16-bit mode external pull-down devices are required on MEM_MDQS[1:0].
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-17
SDRAM Memory Controller
8.4.2
Block Diagram
Figure 8-2 shows the SDRAM MC block diagram. It is important to notice:
• the internal XL bus is 64 bits wide
• the external interface to the SDRAM is only 32 bits wide
Internal XL bus
The SDRAM row, column, and bank address bits are extracted from internal address XLA[4:29];
XLA[29:31], TSIZ[0:2], and TBST control the data path (MDQ, DQM).
Col
Col
ADDR[4:29]
Bk
Address
Input
MUX
Row
Address
Pipeline
Latches
Bk
Row
Sel
A_CS
Address
Output
MUX
A[12:0]
BA[1:0]
CS
MUX
External Interface
CS[1:0]
RAS
SDRAM
Memory Controller
State Machine
D_CS
ADDR[30:31]
WE
CKE
DQM[3:0]
OUT_EN[3:0]
TSIZ[0:2]
DQSOUT
TBST
Internal XL bus
CAS
DQSIN
DIN[0:63]
Write Data Buffer
DOUT[0:63]
MDOUT[31:0]
MDIN[31:0]
Read Data Buffer
Note: For 16-Bit External Data Width,
mem_ps = 1, only MDOUT[31:16] and
MDIN[31:16] should be connected to
the external memories.
Figure 8-2. Block Diagram—SDRAM Memory Controller
MPC5200B User’s Manual, Rev. 3
8-18
Freescale Semiconductor
SDRAM Memory Controller
8.4.3
Transfer Size
All SDRAMs are “burst oriented” for read and write operations. The memory will move a full burst of data
for every Read and Write command unless the command is interrupted by a new command, explicitly
terminated, or the data is masked. (Data mask does not shorten the command, it only inhibits data capture.)
The Memory Controller can interrupt certain commands, by supporting the explicit Burst Terminate
command.
The Memory Controller supports Burst and Non-Burst, or Single, transfers corresponding to the
homonymous XL bus transfer types. A Burst transfer is a 32 Byte block, 4 XLB data beats (8 memory data
beats), spanning a modulo 32 address range. The starting address can be any modulo 8 boundary within
the modulo 32 range; the address “wraps” from the highest address to the lowest address of the range if
the starting address is not aligned at the beginning of the range. No data is masked during a burst.
The beat address order of the XL bus is sequential. Based on the start address issued by the internal master,
the address order of the 4 XLD beats in a burst transfer is one of the following:
• 0x00, 0x08, 0x10, 0x18 (memory data address order 0x00, 0x04, 0x08, 0x0c, ...)
• 0x08, 0x10, 0x18, 0x00
• 0x10, 0x18, 0x00, 0x08
• 0x18, 0x00, 0x08, 0x10
To implement single-beat transfers, the Memory Controller uses DM[3:0] to mask unwanted bytes or
words. The Memory Controller supports all single-beat transfer sizes from 1 to 8 contiguous bytes within
a single modulo 8 address range.
A Single transfer is exactly 1 beat on the XLD bus. The relevant data for a Single transfer is always within
the first 2 beats on the memory bus, allowing the command to be aborted (interrupt) as soon as possible.
8.4.4
Commands
When an internal bus master accesses SDRAM address space, the Memory Controller generates the
corresponding SDRAM command. Table 8-4 lists SDRAM commands supported by the Memory
Controller.
Table 8-4. SDRAM Commands
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A10
Other A
Command Inhibit
INH
H
H
X
X
X
X
X
X
No Operation
NOP
H
L
H
H
H
X
X
X
Read
READ
H
L
H
L
H
V
L
V
Write
WRIT
H
L
H
L
L
V
L
V
Row and Bank Active
ACT
H
L
L
H
H
V
V
V
Burst Terminate
BST
H
L
H
H
L
X
X
X
Precharge All Banks
PALL
H
L
L
H
L
X
H
X
Load Mode Register
LMR
H
L
L
L
L
LL
V
V
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-19
SDRAM Memory Controller
Table 8-4. SDRAM Commands (continued)
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A10
Other A
Load Extended Mode Register
LEMR
H
L
L
L
L
LH
V
V
CBR Auto Refresh
AREF
H
L
L
L
H
X
X
X
Self Refresh
SREF
H→L
L
L
L
H
X
X
X
Power Down
PDWN
H→L
H
X
X
X
X
X
X
Note:
1.
2.
3.
4.
H = High
L = Low
V = Valid
X = Don’t care
Many commands require a delay before the next command may be issued; sometimes the delay depends
on the type of the next command. These delay requirements are managed by the values programmed in the
Memory Controller Configuration registers.
8.4.4.1
Load Mode/Extended Mode Register Command
The Load Mode Register (LMR) and Load Extended Mode Register (LEMR) commands are used during
SDRAM initialization only.
When a bus master writes to the Memory Controller Mode register, the Memory Controller generates the
LMR or LEMR command to forward the data to the memory. In these two operations, data written to the
Memory Controller is put on the SDRAM address and bank select busses. The bank select data selects the
Mode or Extended Mode register.
The Memory Controller Mode register must be enabled before writing, and disabled after all memory
Mode register operations are complete. This is done by setting or clearing the Control register mode_en
bit. See Section 8.6.1.1, “Memory Controller Mode Register.”
Some of the configuration parameters required by the memory are also needed by the Memory Controller
for command generation. The parameters are:
• burst length
• latency
These must be programmed in the Memory Controller Configuration registers separately from setting the
memory Mode register.
MPC5200B User’s Manual, Rev. 3
8-20
Freescale Semiconductor
SDRAM Memory Controller
8.4.4.2
Precharge All Banks Command
The Memory Controller issues the Precharge command only when necessary for one of the following
conditions:
• Access to a new row
• Refresh interval elapsed
• Software commanded Precharge
NOTE
DRAMs also have a maximum bank open period, after which a precharge is
required. The Memory Controller does not time the bank open period
because the refresh interval is always less.
The Precharge command puts SDRAM into an idle state. In this state, the following commands can be
issued:
• Refresh
• Bank Active
• Load Mode/Extended Mode Register
NOTE
The Memory Controller does not support the Precharge Selected Bank
memory command.
8.4.4.3
Row and Bank Active Command
SDRAM devices have 4 internal banks. A particular row and bank of memory must be activated to allow
read and write accesses. For page mode support, the Memory Controller keeps the active row and bank(s)
open as long as possible.
In an SDRAM device each internal bank can have one active row. The Bank Active command activates a
row of one bank. The Memory Controller only supports the same active row in all banks of each CS space
independently. The page size of a CS space is equal to the space size divided by the number of rows; but
the page may not be contiguous in the XLB address space because the XLA bits for memory column
address bits [11:8] and memory column address [7:0] are not consecutive. The size of a contiguous page
segment is 4KB, corresponding to 8 CA bits plus 2 BA bits times 4Bytes of data.
Each CS space almost always has an active row. If no row is already active, any read or write access will
activate one; and the only reasons that a row is deactivated are to activate a different one instead, or to
perform a refresh.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-21
SDRAM Memory Controller
8.4.4.4
Read Command
When the Memory Controller receives a read request via the XL bus, it first checks the row and bank of
the new access. If the address falls within the active row of an active bank, it is a page hit, and the Read
command is issued as soon as possible (pending any delays required by previous commands). If the
address is within the active row, but the needed bank is inactive, or if there is no active row, the Memory
Controller will issue a Bank Active command followed by the Read command. If the address is not within
the active row, the Memory Controller will issue a Precharge command to close the active row, followed
by a Bank Active command to activate the necessary bank and row for the new access, followed finally by
the Read command.
The Precharge and Bank Active commands (if necessary) can sometimes be issued in parallel with an
on-going data movement.
All Reads, whether Burst or Single, must be allowed to complete the entire burst length on the memory
bus. With SDR memory, the Data Masks are negated throughout the entire Read burst length. With DDR
memory, the Data Masks are asserted throughout the entire Read burst length; but DDR memory ignores
the Data Masks during Reads.
8.4.4.5
Write Command
When the Memory Controller receives a write request via the XL bus, it first checks the row and bank of
the new access. If the address falls within the active row of an active bank, it is a page hit, and the Write
command is issued as soon as possible (pending any delays required by previous commands). If the
address is within the active row but the needed bank is inactive, or if there is no active row, the Memory
Controller will issue a Bank Active command followed by the Write command. If the address is not within
the active row, the Memory Controller will issue a Precharge command to close the active row, followed
by a Bank Active command to activate the necessary row and bank for the new access, followed finally by
the Write command.
The Precharge and Bank Active commands (if necessary) can sometimes be issued in parallel with an
on-going data movement.
With both SDR and DDR memory, a Read command can be issued overlapping the masked beats at the
end of a previous Single Write of the same CS; the Read command aborts the remaining (unnecessary)
Write beats. With DDR memory, a Read of one CS can even overlap the masked beats at the end of a
previous Single Write of the other CS. The Write is not aborted, but the masks remain asserted. This is not
possible with SDR memory, because SDR memory cannot be read with the masks asserted.
8.4.4.6
Burst Terminate Command
SDRAMs are burst-only devices, but they provide mechanisms to truncate a burst if not all of the beats are
needed. The burst terminate command is used to truncate read bursts (SDR and DDR) and write bursts
(SDR). The most recently registered read or write command prior to the burst terminate command will be
truncated. The open page which the read or write burst was terminated from remains open.
MPC5200B User’s Manual, Rev. 3
8-22
Freescale Semiconductor
SDRAM Memory Controller
8.4.4.7
Auto Refresh Command
The Memory Controller issues Auto Refresh commands according to the ref_interval value specified in
the Memory Controller Control register. Each time the programmed refresh interval elapses, the Memory
Controller issues a Precharge All Banks command followed by an Auto Refresh command.
If a memory access is in progress at the time the refresh interval elapses, the Memory Controller schedules
the refresh after the transfer is finished; but the interval timer continues counting so that the average refresh
rate is constant.
After refresh, the SDRAM is in an idle state and waits for an Active command.
8.4.4.8
Self Refresh and Power Down Commands
The Memory Controller issues either a Power Down or a Self Refresh command if the Control register cke
bit is changed from asserted to negated. If the ref_en bit of the same register is asserted when cke is
negated, the controller issues a Self Refresh command; if the ref_en bit is negated, the controller issues a
Power Down command. The ref_en bit may be changed in the same register write that changes the cke bit;
the controller will act upon the new value of the ref_en bit.
Unlike an Auto Refresh, the controller does not automatically issue a Precharge command before the Self
Refresh command. It is a software responsibility to command a Precharge, using the Control register
soft_pre bit, by a separate write before negating the cke bit.
The memory is reactivated from Power Down or Self Refresh mode by reasserting the cke bit.
If a normal refresh interval elapses while the memory is in Self Refresh mode, a Precharge and Auto
Refresh will be performed as soon as the memory is reactivated. If the memory is put into and brought out
of Self Refresh all within a single refresh interval, the next automatic refresh will occur on schedule.
In Self Refresh mode, the memory does not require an external clock. The MEM_CLK can be stopped for
maximum power savings by negating the Memory Controller Clock Enable bit of the CDM Clock Enable
register. See Section 5.5.1.6, “CDM Clock Enable Register.” If the Memory Controller clock is stopped,
the refresh interval timer must be reset before the memory is reactivated (if periodic refresh is to be
resumed). The refresh interval timer is reset by negating the Control register ref_en bit. This can be done
at any time while the memory is in Self Refresh mode, before or after the Memory Controller clock is
stopped/restarted, but not with the same Control register write that negates cke; this would put the memory
in Power Down mode. To restart periodic refresh when the memory is reactivated, the ref_en bit must be
reasserted; this can be done before the memory is reactivated, or in the same Control register write that cke
is reasserted.
NOTE
As soon as the CKE signal is negated (set to a logical 0) a SDRAM memory
device does NOT answer any longer to any command (all its input but the
CKE are ignored) until the CKE is re-asserted and a minimum time has
elapsed (as specified by the memory vendor).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-23
SDRAM Memory Controller
8.5
8.5.1
Operation
Power-Up Initialization
The SDRAM and SDRAM MC must be initialized after power-up. SDRAM parameters may be read from
an I2C serial EEPROM, or compiled into the boot ROM. See Section 18.1, Overview if using serial
EEPROM.
The steps below should be followed to initialize the memory system.
NOTE
The sequence might change slightly from device to device. Refer to the
device data sheet for the most up-to-date information. In any case of conflict
between this document and the device data sheet, the data sheet shall
prevail.
Step 1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification.
Usually 100 μs or 200 μs.
Step 2. Determine the number of SDRAM CS spaces. If using both CS spaces, configure
GPIO_WKUP6/CS1 for CS1 mode.
If all the memory and controller register values have been precalculated and stored in ROM, skip
step 3 and go directly to step 4. Otherwise, continue with step 3.
Step 3. Read the SDRAM parameters (type, size, address muxing, timing), and determine the memory
clock frequency. (The memory clock frequency is always equal to the XLB frequency.) Using the
SDRAM parameters and the clock frequency, calculate all the memory and controller register
values now. Certain register fields are mandatory:
— Memory Mode register Burst Mode = Sequential
— Memory Mode register Burst Length = 8
— Controller Configuration register 2 burst_length = 7
— Controller Control register cke = 1
Do not write any registers yet. Use these register values as default values for the following
operations. An operation can override the default, but overrides do not carry forward to subsequent
operations.
Step 4. Write the SDRAMCS Configuration registers and the controller Config registers 1 & 2.
Step 5. Write the controller Control register with these overrides:
— assert the mode_en bit (1).
— negate ref_en (0).
Step 6. (DDR only) Write the controller Control register to issue a Precharge All Banks command
(soft_pre=1); maintain mode_en=1, ref_en=0, all other bits default.
Step 7. (DDR only) Write to the memory Extended Mode register to enable the DLL.
Step 8. (DDR only) Write to the memory Mode register to reset the DLL.
MPC5200B User’s Manual, Rev. 3
8-24
Freescale Semiconductor
SDRAM Memory Controller
Step 9. (DDR only) Pause for the DLL lock time specified by the memory (roughly 100 μs. See memory
data sheet for detailed time).
Step 10.Write to the controller Control register to issue a Precharge All Banks command (soft_pre=1);
maintain mode_en=1, ref_en=0.
Step 11.Write to the controller Control register to issue 2 or more Auto Refresh commands (soft_ref=1);
maintain mode_en=1, ref_en=0. Each command requires a separate write.
Step 12.Write to the memory Mode register to specify normal operation.
Step 13.Write to the controller Control register to specify normal operation.
8.5.2
Read Clock
The MPC5200B implements a self-calibrating, software adjustable, read clock recovery circuit. A 400 tap
master delay chain, continuously measures either the half or full period delay of the memory clock. The
master tap value is used to derive a 1/4 period tap value, for use in 4 independent, 256 tap, slave delay
chains. In DDR mode, the MDQS signal is used to generate the 1/4 period delayed read clock. In SDR
mode, an internally generated “DQS” signal is used to generate the 1/4 period delayed read clock. For both
DDR and SDR memories, the delayed read clock is used to latch the data from the memories.
8.6
Programming the SDRAM Controller
The Memory Controller registers consist of:
• Memory Controller Mode Register / SDRAM MC Extended Mode Register (MBAR+0x0100),
write only
• Memory Controller Control Register (MBAR+0x0104)
• Memory Controller Configuration Register 1 (MBAR+0x0108)
• Memory Controller Configuration Register 2 (MBAR+0x010C)
All registers are 32bit-aligned in memory (modulo 4 address boundary).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-25
SDRAM Memory Controller
8.6.1
Memory Controller Registers
8.6.1.1
Memory Controller Mode Register
Each time the 32-bit write-only mode register (mode[0:31]) is written (and cmd is set to 1), the controller
generates a Load Mode Register or Load Extended Mode Register command to memory.
The memory Mode/Extended Mode registers must be initialized during the system boot sequence; but
before writing to the controller Mode register, the mode_en and cke bits in the Control register must be set
to 1. After memory initialization is complete, the Control register mode_en bit should be cleared to prevent
subsequent access to the controller Mode register.
Address MBAR + 0x0100
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W
Reset
Rsvd
MEM_MBA
[1:0]
MEM_MA[11:0]
cmd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 8-3. Memory Controller Mode Register
Table 8-5. Memory Controller Mode Register Field Descriptions
Bit
Name
Description
0:1
MEM_MBA
[1:0]
See SDRAM data sheet. Select either the memory device Mode register or the memory device
Extended Mode register, if present.
2:13
MEM_MA[11:0]
14
—
15
cmd
16:31
—
See SDRAM data sheet. MPC5200B supports:
Read CAS Latency, SDR: 2, 3
Read CAS Latency, DDR: 2, 2.5
Burst type: Sequential only
Burst length: 8 only
Other fields: As appropriate
Specific bit allocation can vary from device to device. All devices in all CS spaces must have
compatible format(s), because all are written at the same time with the same value.
Reserved
1 Generate a (Extended) Mode Register Set memory command. Applied to all CS at once.
0 Do not generate any memory command.
Reserved
MPC5200B User’s Manual, Rev. 3
8-26
Freescale Semiconductor
SDRAM Memory Controller
8.6.1.2
Memory Controller Control Register
The 32-bit read/write Control register controls specific operations and generates some SDRAM
commands. This register is reset only by a power-up reset signal.
Address MBAR + 0x0104
0
1
2
3
cke
ddr
ref
_en
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
R mode
W _en
Reset
4
5
6
7
8
9
10
11
hi_
drive
Rsvd
addr
_rule
Rsvd
12
13
14
15
0
0
0
29
30
31
soft
_ref
soft
_pre
Rsvd
0
0
0
ref_interval[0:5]
R
W
Reset
Reserved
0
mem_
Rsvd
ps
0
0
0
dqs_oe
0
0
0
Reserved
0
0
0
0
0
0
Figure 8-4. Memory Controller Mode Register
Table 8-6. Memory Controller Control Register Field Descriptions
Bit
Name
Description
0
mode_en
1
cke
0 MEM_CLK_EN negated (low).
1 MEM_CLK_EN asserted (high).
cke must be set to 1 to perform normal read and write operations. Set cke to 0 to put the memory
in Self Refresh or Power Down mode.
2
ddr
0 SDR mode.
1 DDR mode.
3
ref_en
4:6
—
7
hi_addr
8
—
9
drive_rule
0 Mode register locked, cannot be written.
1 Mode register enabled, can be written.
0 Automatic refresh disabled.
1 Automatic refresh enabled.
In general, refresh must be enabled, unless the system is known to access memory in a pattern
that is guaranteed to open every row in every bank within every refresh period tREF. Some
memory data sheets do not spec tREF, but spec tREFI instead. In this case, tREF = tREFI x #rows.
NOTE: The number of Refresh commands required in tREF is #rows; if refresh is disabled, the
number of Read/Write commands required in tREF is #rows x 4banks.
Reserved
Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA bus.
See Table 8-7.
Reserved (must be written 0)
0 “Tri-state except to write” mode: MPC5200B drives the MDQ and MDQS lines only when
necessary to perform write commands.
1 “Drive except to read” mode: MPC5200B tri-states the MDQ and MDQS lines only when
necessary to perform read commands.
“Drive except to read” mode prevents unterminated memory signals from floating for extended
periods. However, terminated routing is always recommended over unterminated.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-27
SDRAM Memory Controller
Table 8-6. Memory Controller Control Register Field Descriptions (continued)
Bit
Name
Description
10:15
ref_interval[0:5]
The average periodic interval at which the controller generates refresh commands to memory;
measured in increments of 64 x MEM_CLK period.
1) Multiply tREFI by the MEM_CLK frequency. (If the memory data sheet does not define tREFI,
it can be calculated by tREFI = tREF / #rows.)
Example: Assume tREF = 64ms, #rows = 4K, MEM_CLK = 133MHz. Then:
tREFI = 64ms / 4K = 15.625μs; 15.625μs x 133MHz = 2078.1
2) Divide the previous result by 64, rounding toward 0
2078.1 / 64 = 32.471; discard the fractional part.
3) Subtract 1 from the previous result. The new result is ref_interval.
32 - 1 = 31 = 0x1f
16:17
—
18
mem_ps
19
—
20:23
dqs_oe[3:0]
24:28
—
29
soft_ref
0 No operation.
1 Generate a non-periodic Auto Refresh command as soon as possible.
This is a write-only bit; always returns 0 on a read. A software requested refresh is completely
independent of the periodic refresh interval counter. Software refresh is only possible when
mode_en==1.
30
soft_pre
0 No operation.
1 Generate a Precharge All command as soon as possible.
This is a write-only bit; always returns 0 on a read. Software precharge is only possible when
mode_en==1.
31
—
Reserved
Memory data port size.
0 32-bit data bus.
1 16-bit data bus (upper two data bytes, MEM_MDQ[31:16]).
Reserved
Each bit individually controls one MEM_MDQS output.
0 The corresponding MEM_MDQS pin is never driven, regardless of memory operation and
drive_rule. Always set to 0000 for SDR.
1 The corresponding MEM_MDQS pin can be driven, depending on memory operations and
drive_rule. DDR only.
Reserved
Reserved
The Table 8-7 indicates how the internal address bits XLA[4:7] are multiplexed internally to support
higher column or row address bits.
Table 8-7. High Address Usage
XL Bus Address Line Mapping to Column or Row Address
hi_addr
4
5
6
7
0
CA12
CA11
CA9
CA8
1
CA11
CA9
CA8
RA12
0
CA13
CA12
CA11
CA9
1
CA12
CA11
CA9
RA8
32-Bit Data Bus
16-Bit Data Bus
MPC5200B User’s Manual, Rev. 3
8-28
Freescale Semiconductor
SDRAM Memory Controller
Table 8-8. 32-Bit SDRAM Address Multiplexing
Device
64Mbit
128Mbit
Row bits ×
Col bits ×
Bank bits
hi_
addr
2Mx32bit
11x8x2
4M×16bit
8M×8bit
Structure
4
5
6
7
8
9:19
20:21
22:29
0
—1
—
—
—
—
RA
[10:0]
BA
[1:0]
CA
[7:0]
12×8×2
0
—
—
—
—
12×9×2
0
—
—
—
CA8
13×8×2
1
—
—
—
RA12
4M×32bit
12×8×2
0
—
—
—
—
RA[11:0]
8M×16bit
12×9×2
0
—
—
—
CA8
BA
[1:0]
CA
[7:0]
13×8×2
1
—
—
—
RA12
12×10×2
0
—
—
CA9
CA8
13×9×2
1
—
—
CA8
RA12
12×9×2
0
—
—
—
CA8
RA[11:0]
13×8×2
1
—
—
—
RA12
BA
[1:0]
CA
[7:0]
12×10×2
0
—
—
CA9
CA8
13×9×2
1
—
—
CA8
RA12
12×11×2
0
—
CA11
CA9
CA8
13×10×2
1
—
CA9
CA8
RA12
12×10×2
0
—
—
CA9
CA8
RA[11:0]
13×9×2
1
—
—
CA8
RA12
BA
[1:0]
CA
[7:0]
12×11×2
0
—
CA11
CA9
CA8
13×10×2
1
—
CA9
CA8
RA12
12×12×2
0
CA12
CA11
CA9
CA8
13×11×2
1
CA11
CA9
CA8
RA12
12×11×2
0
—
CA11
CA9
CA8
RA[11:0]
13×10×2
1
—
CA9
CA8
RA12
BA
[1:0]
CA
[7:0]
12×12×2
0
CA12
CA11
CA9
CA8
13×11×2
1
CA11
CA9
CA8
RA12
12×12×2
0
CA12
CA11
CA9
CA8
RA[11:0]
13×11×2
1
CA11
CA9
CA8
RA12
BA
[1:0]
CA
[7:0]
16M×8bit
256Mbit
8M×32bit
16M×16bit
32M×8bit
512Mbit
16M×32bit
32M×16bit
64M×8bit
1Gbit
32Mx32bit
64Mx16bit
2Gbit
1
Internal XLA[4:29]
64Mx32bit
RA[11:0]
All MEM_MA pins are driven in all cases, but only the bits used by memory are listed.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-29
SDRAM Memory Controller
Table 8-9. 16-Bit SDRAM Address Multiplexing
Device
Structure
hi_
addr
Internal XLA[4:30]
4
5
6
7
8
9:19
20:21
22:30
64Mbit
8Mx8bit
12x9x2
0
—1
—
—
—
RA[11:0]
BA
[1:0]
CA
[8:0]
128Mbit
8Mx16bit
12x9x2
0
—
—
—
—
RA[11:0]
16Mx8bit
12x10x2
0
—
—
—
CA9
BA
[1:0]
CA
[8:0]
13x9x2
1
—
—
—
RA12
8Mx32bit
12x9x2
0
—
—
—
—
RA[11:0]
16Mx16bit
12x10x2
0
—
—
—
CA9
BA
[1:0]
CA
[8:0]
13x9x2
1
—
—
—
RA12
12x11x2
0
—
—
CA11
CA9
13x10x2
1
—
—
CA9
RA12
12x10x2
0
—
—
—
CA9
RA[11:0]
13x9x2
1
—
—
—
RA12
BA
[1:0]
CA
[8:0]
12x11x2
0
—
—
CA11
CA9
13x10x2
1
—
—
CA9
RA12
12x12x2
0
—
CA12
CA11
CA9
13x11x2
1
—
CA11
CA9
RA12
12x11x2
0
—
—
CA11
CA9
RA[11:0]
13x10x2
1
—
—
CA9
RA12
BA
[1:0]
CA
[8:0]
12x12x2
0
—
CA12
CA11
CA9
13x11x2
1
—
CA11
CA9
RA12
12x12x2
0
—
CA12
CA11
CA9
RA[11:0]
13x11x2
1
—
CA11
CA9
RA12
BA
[1:0]
CA
[8:0]
256Mbit
32Mx8bit
512Mbit
16Mx32bit
32Mx16bit
64Mx8bit
1Gbit
32Mx32bit
64Mx16bit
2Gbit
1
Row bits ×
Col bits ×
Bank bits
64Mx32bit
All MEM_MA pins are driven in all cases, but only the bits used by memory are listed.
8.6.1.3
Memory Controller Configuration Register 1
The 32-bit read/write Configuration register 1 stores delay values necessary between specific SDRAM
commands. During initialization, software loads values to the register according to the SDRAM
information obtained from the data sheet. This register is reset only by a power-up reset signal.
The Read and Write Latency fields govern the relative timing of commands and data, and must be exact
values. All other fields govern the relative timing from one command to another, they have minimum
values but any larger value is also legal (but with decreased performance). The “suggested values” are
based on the maximum routing delay of memory signals and the MPC5200B maximum memory frequency
MPC5200B User’s Manual, Rev. 3
8-30
Freescale Semiconductor
SDRAM Memory Controller
of 133MHz; they do not guarantee maximum performance for actual board routing delay or operating
frequency.
The minimum values of certain fields can be different for SDR and DDR SDRAM, even if the data sheet
timing is the same, because:
• In SDR mode, the Memory Controller counts the delay in MEM_CLK
• In DDR mode, the Memory Controller counts the delay in 2xMEM_CLK (also referred to as
MEM_CLK2)
MEM_CLK—Memory Controller clock—is the speed of the SDRAM interface and is equal to the internal
XL bus clock. MEM_CLK is fixed at boot time along with the XL bus clock, via the HW RESET WORD
setting. It is an integer multiple of the external reference clock (e.g., 66MHz, 99MHz or 132MHz if a
33MHz reference is used).
MEM_CLK2—double frequency of MEM_CLK—DDR uses both edges of the bus-frequency clock
(MEM_CLK) to read/write data.
Address MBAR + 0x0108
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
srd2rwp
swt2rwp
rd_latency
Rsvd
act2rw
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Rsvd
pre2act
ref2act
Rsvd
wr_latency
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-5. Memory Controller Configuration Register 1
Table 8-10. Memory Controller Configuration Register 1 Field Descriptions
Bit
Name
0:3
srd2rwp
Description
Single Read to Read/Write/Precharge delay. Limiting case is Read to Write:
For DDR: CL + round trip delay + tHz; round up.
If round trip delay = 1 clk and tHz = 0.75 ns::
If CL==2: 2 + 1 + 0.75 ns = 3 clk + 0.75 ns, round to 0x3.
If CL==2.5: 2.5 + 1 + 0.75 ns = 3.5 clk + 0.75ns, round to 0x4
For SDR: CL + round trip delay + tHz + 1; round up.
If round trip delay = 1 clk and tHz = 5.4 ns:
If CL==2: 2 + 1 + 5.4ns + 1 = 4 clk + 5.4ns, round to 0x5.
If CL==3: 3 + 1 + 5.4ns + 1 = 5 clk + 5.4ns, round to 0x6.
4
—
4:7
swt2rwp
Reserved
Single Write to Read/Write/Precharge delay. Limiting case is Write to Precharge.
For DDR, suggested value = 0x3 (tWR + 1 clk)
For SDR, suggested value = 0x2 (tWR)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-31
SDRAM Memory Controller
Table 8-10. Memory Controller Configuration Register 1 Field Descriptions
Bit
Name
8:11
rd_latency
Description
Read CAS Latency.
For DDR:
If CL==2, write 0x6
If CL==2.5, write 0x7
For SDR:
If CL==2, write 0x2
If CL==3, write 0x3
Note: NOTE: CL=2.5 is not supported for SDR.
12
—
13:15
act2rw
Reserved
Active to Read/Write delay.
Suggested value at 132 MHz = 0x02
Rule: tRCD/MEM_CLK-1. Round up to nearest integer.
EXAMPLE:
If tRCD = 20ns and MEM_CLK = 99 MHz
20ns / 10.1 ns = 1.98; round to 2; write 0x1.
If tRCD = 20 ns and MEM_CLK = 132 MHz
20ns / 7.5 ns = 2.66; round to 3; write 0x2.
16
—
17:19
pre2act
Reserved
Precharge to Active or Refresh delay.
Suggested value at 132 MHz = 0x02
Rule: tRP/MEM_CLK-1. Round up to nearest integer.
EXAMPLE:
If tRP = 20ns and MEM_CLK = 99 MHz
20ns / 10.1 ns = 1.98; round to 2; write 0x1.
If tRP = 20 ns and MEM_CLK = 132 MHz
20ns / 7.5 ns = 2.66; round to 3; write 0x2.
20:23
ref2act
Refresh to Active delay.
Suggested value at 132 MHz = 0x9
Rule: tRFC/MEM_CLK - 1. Round up to nearest integer.
EXAMPLE:
If tRFC = 75ns and MEM_CLK = 99 MHz
75ns / 10.1ns = 7.425; round to 8; write 0x7.
If tRFC = 75ns and MEM_CLK = 132 MHz
75ns / 7.5ns = 10; round to 9; write 0x9.
24
—
25:27
wr_latency
28:31
—
Reserved
Write latency.
For DDR, write 0x3
For SDR, write 0x0
Reserved
MPC5200B User’s Manual, Rev. 3
8-32
Freescale Semiconductor
SDRAM Memory Controller
8.6.1.4
Memory Controller Configuration Register 2
The 32-bit read/write Configuration register 2 stores delay values necessary between specific SDRAM
commands. During initialization, software loads values to the register according to the SDRAM
information obtained from the data sheet. This register is reset only by a power-up reset signal.
The Burst Length field must be exact. All other fields govern the relative timing from one command to
another, they have minimum values but any larger value is also legal (but with decreased performance).
All delays in this register are expressed in MEM_CLK.
Address MBAR + 0x010C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
brd2rp
bwt2rwp
brd2wt
burst_length
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 8-6. Memory Controller Configuration Register 2
Table 8-11. Memory Controller Configuration Register 2 Field Descriptions
Bit
Name
0:3
brd2rp
4:7
bwt2rwp
8:11
brd2wt
Description
Burst Read to Read/Precharge delay. Limiting case is Read to Read.
For DDR, suggested value = 0x4 (BurstLength/2)
For SDR, suggested value = 0x8 (BurstLength)
Burst Write to Read/Write/Precharge delay. Limiting case is Write to Precharge.
For DDR, suggested value = 0x6 (BurstLength/2 + tWR)
For SDR, suggested value = 0x8 (BurstLength + tWR - 2)
Burst Read to Read/Write/Precharge delay. Limiting case is Read to Write:
For DDR: CL + burstlength/2 + round trip delay + tHz - 1.5 clk; round up.
If round trip delay = 1 clk and tHz = 0.75 ns:
If CL==2: 2 + 4 + 1 + 0.75ns -1.5 = 5.5clk + 0.75ns, round to 0x6.
If CL==2.5: 2.5 + 4 + 1 + 0.75ns + 1.5 = 6clk + 0.75ns, round to 0x7.
For SDR: CL + burstlength + round trip delay + tHz - 1 clk:
If CL==2: 2 + 8 + 1 + 5.4ns - 1 = 10clk + 5.4ns, round to 0xB.
If CL==3: 3 + 8 + 1 + 5.4ns - 1 = 11clk + 5.4ns, round to 0xC.
12:15
burst_length
16:31
—
Write 0x07 (Burst Length - 1)
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-33
SDRAM Memory Controller
Figure 8-7 shows the timings which can be programmed by the two Controller Configuration Register. The
timing diagram uses the suggested values for a DDR memory and a 132 MHz memory clock. The
displayed Commands are the limiting cases.
MEM_CLK
Single Read to Read/Write/Precharge
(srd2rwp +1)
Read
Bstrm
Write
wr_latency/3
CL
Data
(srd2rwp +1) or (brd2wt + 1)
Read
Burst Read to Write/Precharge
Write
CL
wr_latency/3
Data
brd2rp + 1
Burst Read to Read
Read
Read
swt2rwp + 1
Single Write to Read/Write/Precharge
Write
Prech
bwt2rwp + 1
Write
Burst Write to Read/Write/Precharge
Prech
pre2act + 1
Prech
Precharge to Active/Refresh
Active
act2rw + 1
Active
Active to Read/Write
Read
ref2act + 1
Ref
Refresh to Active
Active
Figure 8-7. Programmable Command Timings
MPC5200B User’s Manual, Rev. 3
8-34
Freescale Semiconductor
SDRAM Memory Controller
8.6.1.5
Special Configuration Delay Register
This Special Configuration Delay Register (SDelay) MUST be written to a value of 0x0000 0004.
Address MBAR + 0x0190
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
sdelay
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-8. Special Configuration Delay Register
Table 8-12. Special Configuration Delay Register Field Descriptions
Bit
Name
28:31
sdelay
Description
Special Configuration Delay—Must be written to 0x00000004
This register must be written to a value of 0x00000004. This is required to account for changes in delay
caused during normal wafer processing.
For more information, see AN3221, MPC5200B SDRAM Initialization and Configuration.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-35
SDRAM Memory Controller
8.7
Address Bus Mapping
This is an illustration of how the XL bus address enters the Memory Controller and is broken down into Row, Column, and
Bank Address fields. Shown below is the 32-bit XL bus address. The Memory Controller uses bits 4:31.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Can be used as most significant row or column address bits:
{CA12, CA11, CA9, CA8} or {CA11, CA9, CA8, RA12}
XL bus address bits 29:31
control the data mask pins,
MEM_DQM[3:0].
The Memory Controller extracts the Row Address from the XL bus address.
The Row Address is presented on the MPC5200B MEM_MA[12:0] pins during SDRAM Active commands.
Row Address bit 12 depends on the Control register hi_addr bit.
0
8
9 10 11 12 13 14 15 16 17
17 18 19 Internal XL address bus
hi_addr = 0
12 11 10 9 8 7 6 5 4 3 2 1 0 Ext MEM_MA pins, row
7
8
9 10 11 12 13 14 15 16 17 18 19 Internal XL address bus
hi_addr = 1
12 11 10 9 8 7 6 5 4 3 2 1 0 Ext MEM_MA pins, row
XL bus address bits 20:21 select the internal bank of an SDRAM device. Each SDRAM
device has 4 internal banks.
XL bus address bits 20:21 are presented on the MPC5200B MEM_BA[1:0] pins during
SDRAM Active, Read, and Write commands.
The Memory Controller extracts the Column Address from the XL bus address. The Column Address is presented on the
MPC5200B MEM_MA[12:0] pins during SDRAM Read and Write commands.
Column Address bits 12:8 depend on the Control register hi_addr bits. Auto Precharge (MEM_MA[10])is always inhibited
(0).
4
5
0
6
7 22 23 24 25 26 27 28 29
12 11 10 9
8
0
6 22 23 24 25 26 27 28 29
4
0
5
12 11 10 9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Internal XL address bus
hi_addr = 0
External MEM_MA pins, column
Internal XL address bus
hi_addr = 1
External MEM_MA pins, column
Figure 8-9. Address Bus Mapping (32-Bit External Data Width)
MPC5200B User’s Manual, Rev. 3
8-36
Freescale Semiconductor
SDRAM Memory Controller
This is an illustration of how the XL bus address enters the Memory Controller and is broken down into Row, Column, and
Bank Address fields. Shown below is the 32-bit XL bus address. The Memory Controller uses bits [27:0].
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Can be used as most significant row or column address bits:
{CA13, CA112, CA11, CA9} or {CA12, CA11, CA9, RA12}
XL bus address bits 30:31
control the data mask pins,
MEM_DQM[3:2].
The Memory Controller extracts the Row Address from the XL bus address.
The Row Address is presented on the MPC5200B MEM_MA[12:0] pins during SDRAM Active commands.
Row Address bit 12 depends on the Control register hi_addr bit.
0
8
9 10 11 12 13 14 15 16 17 18 19 Internal XL address bus
hi_addr = 0
12 11 10 9 8 7 6 5 4 3 2 1 0 Ext MEM_MA pins, row
7
8
9 10 11 12 13 14 15 16 17 18 19 Internal XL address bus
hi_addr = 1
12 11 10 9 8 7 6 5 4 3 2 1 0 Ext MEM_MA pins, row
XL bus address bits 20:21 select the internal bank of a SDRAM device. Each SDRAM
device has 4 internal banks.
XL bus address bits 20:21 are presented on the MPC5200 MEM_BA[1:0] pins during
SDRAM Active, Read, and Write commands.
The Memory Controller extracts the Column Address from the XL bus address. The Column Address is presented on the
MPC5200B MEM_MA[12:0] pins during SDRAM Read and Write commands.
Column Address bits 12:8 depend on the Control register hi_addr bits. Auto Precharge (MEM_MA[10])is always inhibited
(0).
5
6
0
7 22 23 24 25 26 27 28 29 30
12 11
10 9
4
0
5
12 11
8
7
6
5
4
3
2
1
0
6 22 23 24 25 26 27 28 29 30
10 9
8
7
6
5
4
3
2
1
0
Internal XL address bus
hi_addr = 0
External MEM_MA pins, column
Internal XL address bus
hi_addr = 1
External MEM_MA pins, column
Figure 8-10. Address Bus Mapping (16-Bit External Data Width)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
8-37
SDRAM Memory Controller
8.7.1
Example—Physical Address Multiplexing
The mapping of XL address bus to memory address bus is shown in Figure 8-9. The default mapping is:
• Row address comes from XLA[8:19]
• Column address comes from XLA[4:7, 22:29]
• Bank address comes from XLA[20:21]
Using the MT46V32M16 DDR SDRAM memory from Micron as an example, the device holds 512Mb
organized as 8M x 16bit x 4banks. 2 devices are required to support the MPC5200B 32bit memory data
bus, giving a total 128MB of address space (assuming just one CS).
The Micron data sheet shows the following requirements:
• 13 row address bits
• 10 column address bits
• 2 bank select bits
By default, the Memory Controller only provides 12 row address bits and 12 column address bits. To
enable the 13th row address bit, the hi_addr bit of the Control register must be set to 1 (MBAR+0x0104,
Control[7]). This also reduces the column address width to 11 bits.
MPC5200B User’s Manual, Rev. 3
8-38
Freescale Semiconductor
Chapter 9
LocalPlus Bus (External Bus Interface)
9.1
Overview
The LocalPlus Bus is the external bus interface of the MPC5200B. This multi-function bus system
supports interfacing to external Boot ROM or Flash memories, external SRAM memories or other memory
mapped devices. The following sections are contained herein:
• Overview
• Features
• Interface
— External Signals
— Block Diagram
• Modes of Operation
— Non-MUXed Mode
— MUXed Mode
• Configuration
— Boot Configuration
— Chip Selects Configuration
— Reset Configuration
• DMA (BestComm) Interface (SCLPC)
• Programmer’s Model
— Chip Select/LPC Registers
— Chip Select/LPC Registers
— SCLPC Registers
— SCLPC FIFO Registers
The MPC5200B offers a shared external 32-bit address/data bus, which supports connections to PCI and
ATA compliant devices, as well as memory mapped devices such as Flash memories, ROM, SRAM,
gate-array logic, or other simple target (slave) devices with little or no additional circuitry. Separate control
signals are used by each interface. The on-chip arbiter (called PCI Arbiter) controls the access to the shared
AD bus for the different clients.
NOTE
If the PCI interface is NOT used (and internally disabled) the PCI control
pins must be terminated as indicated by the PCI Local Bus specification.
PCI control signals always require pull-up resistors on the motherboard (not
the expansion board) to ensure that they contain stable values when no agent
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-1
LocalPlus Bus (External Bus Interface)
is actively driving the bus. This includes PCI_FRAME, PCI_TRDY,
PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and
PCI_REQ.
The PCI signals, which are not used as address in Large Flash mode, are
drive low during a Large Flash access. This includes PCI_SERR,
PCI_PERR, PCI_IDSEL, PCI_REQ, PCI_GNT and PCI_RESET.
The PCI interface is described in Chapter 10, “PCI Controller”. The ATA compliant interface is described
in Chapter 11, “ATA Controller”. The interface for memory mapped devices, called LocalPlus Bus, is
described in this chapter. The MPC5200B LocalPlus Controller (LPC) module implements the LocalPlus
Bus interface.
The LocalPlus Bus interface provides a high flexibility and all its different operating modes can be selected
by means of software configuration and in some cases minimal external logic (in multiplexed mode).
9.2
Features
LocalPlus has the following features:
• Interface to memory mapped or chip selected devices
• Two main modes of operation:
— non-MUXed Modes
Legacy Modes (Address 8, 16, or 24 bits, Data 8 or 16 bits)
Most Graphics Mode (Address 24 bits, Data 32 bits)
Large Flash Mode (Address 26 bits, Data 8 or 16 bits)
— MUXed Modes
– (Address 8, 16, 24 or 25 bits, Data 8,16 or 32 bits, 2 Bank Selects)
• 8 Chip Select (CS) signals
— Programmable Wait States per CS
— Programmable Deadcycles per CS
— Programmable Byte Swapping per CS
• Configurable Boot interface supporting PowerPC architecture code execution
• Dynamic bus sizing on some interfaces
• Support of BURST MODE FLASH devices
• DMA (BestComm) support allows data movement independently from the CPU
• NO support of misaligned accesses
MPC5200B User’s Manual, Rev. 3
9-2
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.3
Interface
The LocalPlus interface consists of:
• Address bus
• Data bus
• Chip select signals CS0-7
• Control signals:
— R/W (Read/Write)
— ALE (Address Latch Enable)
— ACK (Acknowledge)
— TS (Transfer Start)
— OE (Output Enable)
— TSIZ bits (Transfer Size)
— Bank Select bits
• Reference clock PCI_CLOCK
The reference clock PCI_CLOCK is always running, even if the PCI Controller is disabled.
9.3.1
External Signals
The external I/O bus is shared with the PCI AD bus and the ATA bus and requires arbitration for access to
the external bus.
Table 9-1. LocalPlus External Signals
Signal
I/O
Definition
CS [7:0]
O
Chip Selects (active low), CS[4] and CS[5] shared with ATA, CS[6] and CS[7] shared with PSC3.
R/W
O
Read/Write. 1 = Read, 0 = Write
EXT_AD[31:0]
I/O
AD Address / Data bus (bi-directional when used as data; bit 31=msb)
ACK
I/O
External Acknowledge input (non-burst transactions),
BURST indication for Most Graphics or Large Flash Modes (Open Drain)
TS
O
Transfer Start
OE
O
Output Enable
TSIZ[1:2]
O
Transfer Size
Note: TSIZ bits are available in non-muxed modes on GPIO_WKUP_7 and TEST_SEL_1 pins, if
the LPTZ bit is set in Section 7.3.2.1.1, “GPS Port Configuration Register”
Note: The MUXed Mode provides 3 bits TSIZ[0:2], which are available on EX_AD[30:28].
ALE
O
Address Latch Enable
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-3
LocalPlus Bus (External Bus Interface)
9.3.2
Block Diagram
The block diagram of the LocalPlus Controller (LPC) is shown in Figure 9-1. This diagram shows the
non-multiplexed implementation of address and data lines.
The LPC is driven by the internal IP bus clock and the PCI_CLOCK. The supported ratios of the IP bus
clock to the reference clock PCI_CLOCK (the one externally seen by peripherals) are 4:1, 2:1 and 1:1.
The reference clock is the PCI_CLOCK and all clock counts are referred to this clock. All transitions are
synchronized to the rising edge of the PCI_CLOCK.
Start/Stop registers to define the CS address range for each CS output are contained in the MPC5200B
MMAP register group, see Section 3.3.3.2, “Boot and Chip Select Addresses”. Registers in the LPC are
accessed through the address range specified in the MPC5200B Internal Register Map. For more
information, see Section 9.7, Programmer’s Model”. These registers control the operation of a particular
CS and peripheral, when a hit occurs in the MMAP module for the corresponding CS space.
XL Bus
IP Bus Data
IPBI
Registers
Variable Width
R/W Data
Shared Data
MMAP
8
cs “hit”
32
ext_add
Variable Width
Address
AD[31:0]
multiplexed
with PCI, ATA
R/W
ACK
LPC
ALE
PCI Arbiter
AD bus Request
TS
AD bus Grant
OE
IPB_CLK
2
TSIZ[1:2]
8
CS[0:7]
CDM
PCI_CLOCK
Figure 9-1. LPC Concept Diagram
NOTE
BestComm Interface + FiFo not shown
Not all pins are used in all modes.
MPC5200B User’s Manual, Rev. 3
9-4
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
For multiplexed bus implementation, external logic is required to capture the address phase as shown in
Figure 9-2.
Peripheral
MPC5200
DATA[31:0]
AD[31:0]
Bank Bits
AD Bus
Address
ALE
External
Logic
ADD[6:5]
ADD[31:7]
TSIZ[0:2]
LPC Interface
TS
CS
TS
CS
ACK
ACK
Figure 9-2. Muxed Mode Address Latching
9.4
Modes of Operation
There are 2 primary modes of operation:
• MUXed
• non-MUXed (Legacy, Large Flash, Most/Graphic modes, Burst and Non-Burst)
Within each mode, there is considerable flexibility to control the operation.
Each CS can be programmed to a different mode of operation (MUXed, non-MUXed, number of wait
states, byte swapping etc.).
The MPC5200B always begins execution from the release of HRESET on the LocalPlus Bus and from the
memory device connected to CS0.
If an ATA Disk drive is present in the system, 2 CS signals may be taken up by the ATA interface. The
ATA CSs can also be programmed to appear on other signals. For more information, see Chapter 11, “ATA
Controller”.
MUXed mode allows devices with a larger address range be attached to the LocalPlus bus. In this mode
the same 32-bit local bus presents an Address in an address tenure and Data in a data tenure, in a
multiplexed fashion (similar to PCI protocol).
MUXed mode provides an ALE during the address phase and a TS during a separate data phase. This mode
requires external logic to latch the address during the address tenure. An ACK input is provided and can
be asserted to shorten (but not extend) wait states. The MUXed mode is available for all CSs, including
CS0 (i.e., Boot Device).
The LocalPlus Bus on MPC5200B provides an Output Enable signal OE to achieve a complete glue less
interface for most devices.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-5
LocalPlus Bus (External Bus Interface)
The logic equation for the internal generation of the OE signal is:
OE = CSx + (NOT R/W)
CSx
OE
R/W
Figure 9-3. Output Enable Signal
MUXed and non MUXed modes support a variety of device configurations and are configurable on a per
CS basis.
9.4.1
Non-MUXed Mode
In Non-MUXed mode the 32-bit address/data bus is divided into address and data lines. Eight different
partitionings of address and data lines can be configured.
Table 9-2. Non-Muxed Mode Options
Category
Address Size
Data Size
Pins used
Memory size
Comments
Small
8
8
16
256 Bytes
Legacy Mode
Small
8
16
24
256 Bytes
Legacy Mode
Small
16
8
24
64 kBytes
Legacy Mode
Small
16
16
32
64 kBytes
Legacy Mode (BOOT OPTION)
Medium
24
8
32
16 MBytes
Legacy Mode (BOOT OPTION)
MOST/G
24
32
56
16 MBytes
MOST Graphics (BOOT OPTION)
Burst support. No PCI or ATA support
Large
26
8
34
64 MBytes
Large Flash Mode (BOOT OPTION). Burst
support. No PCI support.
Large
26
16
42
64 MBytes
Large Flash Mode (BOOT OPTION) Burst
support. No PCI support
NOTE
The 24-bit data width is not supported.
The total pin number requires also the addition of the control signals CS,
R/W, ACK, OE, TS (MOST/Graphis and Large Flash mode) and TSIZ
(MOST/Graphics mode) where available.
The total supported memory size has been calculated taking into account
that when accessing 16/32 bit devices A1 and/or A0 can NOT be used.
The above options defined as BOOT Option are selectable via the reset configuration word. Other
configurations are possible via software configuration (e.g., 8-bit data and 16-bit address). Figure 9-4
shows the operation of Non-MUXed Read/Write accesses.
MPC5200B User’s Manual, Rev. 3
9-6
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
TSIZ bits are available in all non-muxed modes. They appear on GPIO_WKUP_7 (TSIZ most significant
bit, TSIZ 1) and TEST_SEL_1 (TSIZ least significant bit, TSIZ 2), if the LPTZ bit is set in the GPS Port
Configuration Register. Only TSIZEs of 1, 2, or 4 are supported.
TSIZ[1:2] are driven as follows:
01 = Transaction is 1 byte.
10 = Transaction is 2 bytes.
00 = Transaction is 4 bytes.
Other values are invalid and should not be required by the external peripheral!
Table 9-3 describes the various combinations of TSIZ, address and byte lanes for MOST/Graphis mode.
Table 9-3. Non-Muxed Aligned Data Transfers
Data lanes
Transfer
Size
TSIZ[1:2]
1 Byte
01
2 Bytes
4 Bytes
10
00
Addr[1:0]
AD[31:24]
AD[23:16]
AD[15:8]
AD[7:0]
00
Data
—
—
—
01
—
Data
—
—
10
—
—
Data
—
11
—
—
—
Data
00
Data
Data
—
—
10
—
—
Data
Data
00
Data
Data
Data
Data
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-7
LocalPlus Bus (External Bus Interface)
CS[x]
ADDR
Valid Address
OE
R/W
DATA (wr)
Valid write Data
ValidRread Data
DATA (rd)
ACK
TS
TSIZ[1:2]
NOTE:
1.
ACK can shorten the CS pulse width.
2.
TS is only available in Large Flash and MOST Graphics mode.
Figure 9-4. Timing Diagram—Non-MUXed Mode
MPC5200B User’s Manual, Rev. 3
9-8
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
PCI CLK
CS[x]
ADDR
Valid Address
OE
R/W
Valid Read Data
DATA (rd)
ACK
TS
NOTE:
1.
Burst Mode is only available for Large Flash and MOST Graphics mode.
2.
ACK is output and indicates the burst.
Figure 9-5. Timing Diagram—Burst Mode
In this mode, the peripheral address and data lines are limited to a total of 32 in Legacy Modes, to 40 or
48 in Large Flash or to 56 in MOST Graphics mode. They are driven/read simultaneously on the external
AD bus. A single dedicated R/W pin is driven to indicate read or write. An individually dedicated CS pin
is driven low while an external access is active.
Wait states are programmable and simply select how many PCI clocks the CS pin (and related signals)
remain asserted. Separate values are available for Read cycles versus Write Cycles. These values can be
combined to create extremely long (up to 16 bits) Write cycles. Byte lane swapping is separately
programmable between Reads versus Writes and can be used to perform Endian conversions. The 24-bit
data width is not supported.
Peripherals can be marked as read-only or write-only by setting a control bit in the appropriate LPC
register. Attempted accesses in violation of this setting are prevented and result in either a Bus Error and/or
an Interrupt as controlled by corresponding Enable bits. Each CS pin can be individually enabled/disabled
and the entire LPC module has a Master Enable bit. No software reset bit is provided or needed.
The non-multiplexed mode requires no external logic for interfacing to simple devices such as Flash ROM,
E2PROM or SRAM. It is faster than the multiplexed mode because data and address are provided in a
single tenure. The supported address space is limited by the 26 address lines.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-9
LocalPlus Bus (External Bus Interface)
9.4.2
MUXed Mode
In MUXed mode the addresses and data are multiplexed using dual tenure. First, the address is put on the shared
address/data bus and ALE is asserted. Then the data is driven when the chip select is asserted. Twelve different
modes of address and data sizes can be configured:
Table 9-4. MUXed Mode Options
Category
Address Size
Data Size
Memory Size
per Bank
Memory Size
Total
Legacy
8
8
256 Bytes
1 kBytes
Legacy
8
16
256 Bytes
1 kBytes
A0 not used.
Legacy
8
32
256 Bytes
1 kBytes
A0, A1 not used.
Legacy
16
8
64 kBytes
256 kBytes
Legacy
16
16
64 kBytes
256 kBytes
A0 not used.
Legacy
16
32
64 kBytes
256 kBytes
A0, A1 not used.
Legacy
24
8
16 MBytes
64 MBytes
Legacy
24
16
16 MBytes
64 MBytes
A0 not used.
Legacy
24
32
16 MBytes
64 MBytes
A0, A1 not used.
Legacy
25
8
32 MBytes
128 MBytes
Legacy
25
16
32 MBytes
128 MBytes
BOOT
Legacy
25
32
32 MBytes
128 MBytes
BOOT
Comments
NOTE
The 24-bit data width is not supported.
The total supported Memory space consists of four banks.
Bank select bits are written in a register by the e300 processor. They can be used as individual selects or
as encoded values. They are presented on the bus during the address tenure as additional upper address bits.
In this mode, an address tenure is generated that can be up to 25bits of active address. The additional
address bits drive:
• a TSIZE value (3 bits)
• a Bank Select value (2 bits)
An ALE signal is asserted (active lo) during this address tenure. ALE width is always one PCI bus clock.
The dedicated R/W output is also driven with ALE (and throughout the cycle). One clock after ALE
negates, the appropriate CS pin asserts (low) and the AD bus enters the data tenure. The CS pin and this
data tenure remain active until the programmed wait states expire, or the peripheral responds with an ACK
assertion. ACK polarity is active low, but can be programmed to be ignored. The data tenure can contain
up to the full 32-bit width. However, the data width is programmable to support dynamically bus-sized
transactions.
MPC5200B User’s Manual, Rev. 3
9-10
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
The MUXed mode requires external logic to latch the address during the address tenure and to decode bank
selects if they are encoded. This mode is slower than the non-MUXed mode because data and address are
multiplexed in time. The supported address space is limited by the 25 address lines. In MUXed mode,
LocalPlus can access up to 128 MBytes of data divided into four banks each of 32 MBytes maximum.
9.4.2.1
Address Tenure
The address is presented on the corresponding AD bus bits up to a maximum of 25bits (i.e., AD[24:0]).
Smaller devices (with address ranges at 8, 16, or 24 respectively) must use the corresponding AD bits,
beginning with AD[0]. AD[0] is the least significant address bit. Regardless of address size, the entire AD
bus is driven during the address phase.
The Bank Select bits appear on AD[26] (Bank Select most significant bit) and AD[25] (Bank Select least
significant bit). These bit values are pre-programmed into the corresponding LPC control register prior to
initiating an external transaction.
The TSIZ bits appear on AD[30] (TSIZ most significant bit) to AD[28] (TSIZ least significant bit). These
bits are calculated and driven by the LPC based on the internal Byte Lane enables on the IP bus.
NOTE
Only TSIZs of 1, 2, or 4 are supported.
TSIZ [0:2]/AD[30:28] are driven as follows:
001 = Transaction is 1 byte.
010 = Transaction is 2 bytes.
100 = Transaction is 4 bytes.
NOTE
Other values are invalid and should not be required by the external
peripheral!
Table 9-5 describes the various combinations of TSIZ, address and byte lanes for 32 bit wide data bus.
Table 9-5. Muxed Aligned Data Transfers
Transfer
Size
Data lanes
TSIZ[0:2]
1 Byte
2 Bytes
4 Bytes
001
010
100
AD[1:0]
AD[31:24]
AD[23:16]
AD[15:8]
AD[7:0]
00
Data
—
—
—
01
—
Data
—
—
10
—
—
Data
—
11
—
—
—
Data
00
Data
Data
—
—
10
—
—
Data
Data
00
Data
Data
Data
Data
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-11
LocalPlus Bus (External Bus Interface)
The ALE signal is active low and remains asserted for 1 external PCI bus clocks. When active any external
latch should be transparent.
AD[31] & AD[27] are unused and are driven low by the LPC during the address tenure, they are used as
data lines during the data phase in 32-bit modes.
9.4.2.2
Data Tenure
During Data Tenure, the following occurs:
• In the case of a write to the peripheral, the LPC drives the indicated AD data bits.
• In the case of a read, the indicated AD bits are tri-stated by the LPC.
NOTE
AD[0] is treated as the least significant data bit. Any unused data bits (as
indicated by the Data Size field in the associated control register) are driven
low by the LPC. Therefore, they should NOT be driven by the peripheral or
glue chip.
At the first PCI clock edge where the ACK input is detected as asserted, the LPC terminates the transaction
and releases the bus on the next PCI Bus clock. AD bus control reverts to the PCI Controller, which is then
responsible for driving default values on the bus. Obviously, any peripheral device must tri-state the AD
bus when it is not in use.
Figure 9-6 shows a MUXed transaction type timing diagram.
9.5
Configuration
The LPC supports several options in terms of modes, address and data sizes, speed, and configuration
which are described below.
9.5.1
Boot Configuration
After power-on reset (POR) the e300 processor accesses the local bus to fetch initial code sequences. Chip
Select Boot (CS Boot) is dedicated for this purpose. CS Boot and CS0 are physically the same pins. The
difference is that CS Boot is impacted by the reset configuration and is enabled after reset.
Several options are also available for boot code fetches. The boot configuration is determined during POR
using the reset_configuration word.
The following boot code configuration options are available, see Table 9-6.
• MUXed or non-MUXed mode.
— In MUXed mode Data bus can be 16- or 32-bits wide.
— In non-MUXed Legacy mode Data bus can be 8- or 16-bits wide.
— In non-MUXed MOST Graphics mode Data bus can be 32-bits wide.
— In non-MUXed Large Flash modes Data bus can be 8- or 16-bits wide.
• The number of wait states during boot can be 4 or 48 PCI bus clock cycles.
• The boot address/exception table can be located at 0x0000 0100 or 0xfff0 0100.
MPC5200B User’s Manual, Rev. 3
9-12
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
PCI CLK
AD[31,27] (wr)
Valid Wrtie Data
AD[30:28] (wr)
TSIZ[0:2] bits
Valid Wrtie Data
AD[26:25] (wr)
Bank[0:1] bits
Valid Wrtie Data
AD[24:0] (wr)
Address[7:31]
Valid Wrtie Data
Valid Read Data
AD[31:0] (rd)
ALE
TS
CSx
OE
RW
ACK
Address Tenure
Data Tenure
NOTE:
1.
ACK can shorten the CS pulse width.
2.
Address should be latched with the rising edge of ALE.
Figure 9-6. Timing Diagram—MUXed Mode
The PowerPC architecture compatible processor core requires 64-bit instruction fetches. During boot code
accesses from CS Boot space on-chip logic is provided to perform enough LocalPlus accesses to
accumulate 64-bit instructions to be given to the e300 processor. For example, before passing the resulting
64-bit instruction to the e300 processor, LocalPlus logic does either:
• 8 accesses to an 8-bit device
• 4 accesses to a 16-bit device
• 2 accesses to a 32-bit device
NOTE
The Boot space supports cached instruction reads and critical double word
first transactions.
The Boot space does NOT support an 8-bit wide MUXed mode
configuration during boot.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-13
LocalPlus Bus (External Bus Interface)
After boot, CS Boot space can be programmed to act as other MPC5200B Chip Select spaces (CS0-7).
This capability is described in the sections below.
9.5.2
Chip Selects Configuration
All Chip Selects CS0-7 have the same functionality. Only one CS can be active at any given time. Multiple
CS windows should not overlap. In the case that an address hit is located in multiple CS windows, only
one CS, the one with the highest priority, becomes active. The CS with the lowest number has the highest
priority (CS0 highest priority, CS7 lowest priority).
CS Boot and CS0 are identical with the exception of their control registers contained in the MPC5200B
MMAP register group, see Section 3.3.3.2, “Boot and Chip Select Addresses”. CS Boot and CS0 are
physically the same pins. The difference is that CS Boot is impacted by the reset configuration and is
enabled after reset, so boot is always performed only at CS Boot.
To change from CS Boot to CS0 the CS0 start and stop addresses must be configured and the disable of
CS Boot must occur together with the Enable of CS0 (see example).
ipbi->control_reg = (ipbi->control_reg & ~CSCTRL_BOOT_EN) | CSCTRL_CS0_EN;
Deadcycles from 0 to 3 can be added to any CS read access and will occur in addition to any cycles which
already exist. The configuration of Dead cycles are done by the Chip Select Deadcycle Control Register.
Burst Mode operations are supported on all CS and can be configured by the Chip Select Burst Control
Register.
The e300 processor can execute code from all CSs of the LP bus.
CS0-CS7 in MUXed mode:
• Supports 8-, 16- and 32-bit data reads and writes.
• Support of Dynamic bus sizing. This means read and write transactions greater than the defined
port size are possible (up to a maximum of 32 bits).
• The LPC Controller creates multiple transactions at the defined port size to satisfy the transaction
size requested up to a maximum of 32 bits. Transactions less than the defined port size are
supported only if the peripheral can decode the TSIZE[0:2] bits, which indicate the current
transaction size.
• 64-bit access is not supported. Internal logic is limited to 32-bits accesses.
• Support of Code execution
CS0-CS7 non-MUXed mode:
• In non-MUXed mode the data port size can be 8, 16 or 32bits.
• Dynamic Bus Sizing for read and write transactions are supported at the defined port sizes.
However, transactions that are less than the port size fail because no control signals exist to alert
the peripheral to the current transaction size. TSIZE[1:2] bits are available in all non-muxed modes
on separate pins, if the LPTZ bit is set in the GPS Port Configuration Register—MBAR + 0x0B00.
• Support of Burst access
MPC5200B User’s Manual, Rev. 3
9-14
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.5.3
Reset Configuration
The mode of the LocalPlus interface at boot is controlled by bits in the RST_CONFIG word described in
Chapter 4, “Resets and Reset Configuration”. The following 6 RST_CONFIG bits control boot device
operation from reset:
• BootType
• BootSize
• BootMostGraphics
• BootLargeFlash
• BootWait
• BootSwap
Table 9-6 describes possible boot settings.
Table 9-6. BOOT_CONFIG (RST_CONFIG) Options
Parameter
If Pulled Down (0)
If Pulled Up (1)
Notes
BootType
non-MUXed boot mode
MUXed boot mode
—
BootSize
non-MUXed type:
8-bit data
non-MUXed type:
16-bit data
—
24-bit address
16-bit address
MUXed type:
16-bit data
(25 bit address)
MUXed type:
32-bit data
(25 bit address)
—
—
BootMostGra
phics
—
MostGraphics boot mode.
LargeFlash
—
Large Flash boot mode
when active BootSize defines data size
(8/16)
BootWait
Minimum Wait states
4 pci_clk cycles
Maximum Wait states:
48 pci_clk cycles
The ACK input can shorten wait states,
if BootDevice supports it.
BootSwap
no Endian swapping applied to
read from Boot Device
Standard Endian swapping
performed on reads from Boot
Device
If swap indicated:
8-bit access = no swap
16-bit access = 2Byte swap
32-bit access = 4Byte swap
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-15
LocalPlus Bus (External Bus Interface)
9.6
DMA (BestComm) Interface (SCLPC)
The SCLPC interface provides a separate path from BestComm directly (on CommBus) to any peripheral.
The supported transactions are limited to 1, 2, 4, or 8 bytes only.
A single FIFO with a size of 512 bytes (32 x 128 bits) supports half duplex operation (Transmit or Receive)
only. If software configures a Transmit Packet, the Packet must be complete before a Receive operation
can be configured and started.
9.7
Programmer’s Model
Figure 9-7 through Figure 9-12 describe in detail the registers and bit meanings for configuring CS
operation. There are eight identical chip select configuration registers, one for each CS output. However,
the CS Boot ROM Configuration Register has active defaults for use by BOOTROM on CS0. All other
configuration registers power-up disabled and require software intervention before the corresponding CS
operates. The Chip Select Control Register is the enable register and the Chip Select Status Register serves
as a status register. For Burst Mode the Chip Select Burst Control Register exists and the configuration of
Dead cycles are done by the Chip Select Deadcycle Control Register.
NOTE
The address range registers for each CS reside in the MMAP register set
rather than in the LPC register set. See Section 3.3.3.2, “Boot and Chip
Select Addresses”.
9.7.1
Chip Select/LPC Registers
There are 12 32-bit Chip Select/LocalPlus (CS/LP) registers. These registers are located at an offset from
MBAR of 0x0300. Register addresses are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0300 + register address
The following registers are available:
• Chip Select 0/Boot Configuration Register (0x0300)
• Chip Select 1–7 Configuration Register (0x0304)
• Chip Select Control Register (0x0318)
• Chip Select Status Register (0x031C)
• Chip Select Burst Control Register (0x0328)
• Chip Select Deadcycle Control Register (0x032C)
MPC5200B User’s Manual, Rev. 3
9-16
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.1.1
Chip Select 0/Boot Configuration Register
Address MBAR + 0x0300
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WaitP
WaitX
W
Reset
0
0
0
0
0
0
0
0
cfg
cfg
cfg
cfg
cfg
cfg
cfg
cfg
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MX
Rsvd
AA
CE
WS
RS
WO
RO
cfg
1
1
1
0
0
0
1
R
AS
DS
Bank
WTyp
W
Reset
cfg
cfg
cfg
cfg
0
0
0
0
Figure 9-7. Chip Select 0/Boot Configuration Register
Table 9-7. Chip Select 0/Boot Configuration Register Field Descriptions (Sheet 1 of 3)
Bits
Name
Description
0:7
WaitP
Number of wait states to insert. Can be applied as a prescale to WaitX or used by itself, as specified
by WTyp bits below. Wait states control how many PCI clocks the corresponding CS pin remains
active.
8:15
WaitX
Base number of wait states to insert, or combined with WaitP as specified by WTyp bits below.
cfg operation—If rstcfg[11] (on pad_eth_03) is zero then 4 wait states are in effect, else 48 wait
states are in effect. Wait States equals the number of PCI clocks from CS assertion to when data
must be valid from boot device.
16
MX
MX bit specifies whether a transaction operates as multiplexed or non-multiplexed. A multiplexed
transaction presents address and data in different tenures. During the address tenure, ALE is
asserted. At the end of ALE, AD bus is switched to data tenure and CSx pin is asserted.
0 = Non-multiplexed
1 = Multiplexed
cfg operation—If rstcfg[14] on pad_eth_06 is low, boot operation is non-multiplexed (single
tenure), else boot operation is multiplexed (dual tenure).
17
—
Reserved
18
AA
ACK Active. This bit defines whether ALK input is active or not. If AA is 1, programmed wait states
can be overridden when/if the external device drives the ACK input low. If AA is 0, the ACK input is
ignored.
Wait states are still in effect. If no ACK is received, cycle terminates at end of wait state period.
Note: Bit must be set to 0, to use ACK as burst indication signal during a burst transaction.
19
CE
An individual Enable bit—allows CS operation for the corresponding CS pin. CE must be high to
allow operation. Chip Select Control Register ME bit must also be high, except when CS[0] is used
for boot ROM.
1 = Enable
0 = Disabled, register writes can occur but no external access is generated.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-17
LocalPlus Bus (External Bus Interface)
Table 9-7. Chip Select 0/Boot Configuration Register Field Descriptions (Sheet 2 of 3)
Bits
Name
Description
20:21
AS
Address Size field—defines size of peripheral Address bus (in bytes) and must be consistent with
physical connections.
00 = 8 bits
01 = 16 bits
10 = 24 bits
11 = > 25 bits
See documentation for Physical Connection requirements.
The combination of address size, data size, and transaction type (MX) must be consistent with the
peripheral physical connection. In case of a multiplexed transaction, the entire address is driven
regardless of address size field.
cfg operation—If rstcfg[13] on pad_eth_05 is low, then the address size for non-multiplexed boot
device is set to 24 bits (AS=10), else the boot device is treated as a 16 bit address (AS=01) device.
For multiplexed mode boot devices the maximum 25 bits of address is always driven. This rstcfg bit
more particularly affects the DS field below, and can be thought of as the “small” or “big” data size
config bit.
22:23
DS
Data Size field—represents the peripheral data bus size (in bytes):
00 =1Byte
01 = 2 Bytes
10 = 3 Bytes (Not Supported)
11 = 4Bytes
cfg operation—If rstcfg[13] on pad_eth_05 is low, then the data size for non-multiplexed boot
device is set to 8 bits (DS=00), else the boot device is treated as a 16 bit (DS=01) device. For
multiplexed mode boot device the selection is 16 bit data or 32 bit data respectively.
24:25
Bank
Bank bits—are reflected on external AD lines (AD[26:25]) during Address tenure of a multiplexed
transaction. Register bit 24 is the msb and appears on AD[26].
26:27
WTyp
Wait state Type bits—define the application of wait states contained in WaitP and WaitX fields, as
follows:
00 = WaitX is applied to read and write cycles (WaitP is ignored).
01 = WaitX is applied to Read cycles, WaitP is applied to Write cycles.
10 = WaitX is applied to Reads, WaitP/WaitX (16-bit value) is applied to Writes.
11 = WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes.
28
WS
Write Swap bit—If high, Endian byte swapping occurs during writes to a peripheral.
• For 8-bit peripherals, this bit has no effect.
• For 16-bit peripherals, byte swapping can occur.
• For 32-bit peripherals (possible in MUXed mode only) byte swap can occur.
1 = swap
0 = NO swap
2-byte swap is AB to BA, 4-byte swap is ABCD to DCBA.
Note: Transactions at less than the defined port size (i.e., data size) apply swap rules as above,
according to the current transaction size.
29
RS
Read Swap bit—Same as WS, but swapping is done when reading data from a peripheral.
1 = swap
0 = NO swap
cfg operation—If rstcfg[12] on pad_eth_04 is low, data from the boot device is Endian swapped
when read. This only has effect for boot devices configured as 16- or 32-bit data size.
MPC5200B User’s Manual, Rev. 3
9-18
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
Table 9-7. Chip Select 0/Boot Configuration Register Field Descriptions (Sheet 3 of 3)
Bits
Name
Description
30
WO
Write Only bit—If bit is high, the peripheral is treated as a write-only device. An attempted read
access results in a bus error (as dictated by Chip Select Control Register EBEE bit) and/or an
interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction is
presented to the peripheral.
A bus error means the internal cycle is terminated with a transfer error acknowledge (ips_xfr_err
assertion to IP bus, TEA assertion to XL bus).
31
RO
Read Only bit—If bit is high, the peripheral is treated as a read-only device. An attempted write
access results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or an
interrupt (as specified by Chip Select Control Register IE bit). In any case, no transaction is
presented to the peripheral.
NOTE: This bit is high from Reset, indicating Boot Device is Read-Only.
Note:
1. The reset values defined as cfg depends on the Reset Configuration.
2. Large Flash mode is used, if AS is set to 11 and DS is set to 00 or 01.
3. MOST/Graphics mode is used, if AS is set to 10 and DS is set to 11.
9.7.1.2
Chip Select 1–7 Configuration Register
Address MBAR + 0x0304, 0x0308, 0x030C, 0x310, 0x0314, 0x0320, 0x0324
0
1
2
R
R
W
Reset
4
5
6
7
8
9
10
11
WaitP
W
Reset
3
12
13
14
15
WaitX
0
0
0
0
0
0
0
0
cfg
cfg
cfg
cfg
cfg
cfg
cfg
cfg
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MX
Rsvd
AA
CE
WS
RS
WO
RO
cfg
1
1
1
0
0
0
1
AS
cfg
DS
cfg
cfg
Bank
cfg
0
WTyp
0
0
0
Figure 9-8. Chip Select 1–7 Configuration Register
Table 9-8. Chip Select 1–7 Configuration Register Field Descriptions (Sheet 1 of 3)
Bits
Name
Description
0:7
WaitP
Number of Wait States to insert. Can be applied as a prescale to Wait X or used by itself, as dictated
by the WTyp bits (see below). Wait States control how many PCI clocks the corresponding CS pin
remains active.
8:15
WaitX
The base number of wait states to insert, or combined with WaitP as dictated by the WTyp bits
below.
16
MX
MX bit specifies whether transaction operates as multiplexed or non-multiplexed. A multiplexed
transaction presents address and data in different tenures. During the address tenure, ALE is
asserted. At the end of ALE, AD bus is switched to data tenure and CSx pin is asserted.
0 = Non-multiplexed
1 = Multiplexed
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-19
LocalPlus Bus (External Bus Interface)
Table 9-8. Chip Select 1–7 Configuration Register Field Descriptions (Sheet 2 of 3)
Bits
Name
Description
17
—
Reserved
18
AA
ACK Active. This bit defines whether ALK input is active or not. If AA is 1, programmed wait states
can be overridden when/if the external device drives the ACK input low. If AA is 0, the ACK input is
ignored.
Wait states are still in effect. If no ACK is received, cycle terminates at end of wait state period.
Note: Bit must be set to 0, to use ACK as burst indication signal during a burst transaction.
19
CE
Chip Enable—bit allows CS operation for the corresponding CS pin. Must be high to allow operation.
Chip Select Control Register ME bit must also be high.
Enabled.
0 = Disabled, register writes can occur but no external access is generated.
20:21
AS
Address Size field—defines the peripheral address bus size in bytes, and must be consistent with
the physical connections.
00 = 8 bits
01 = 16 bits
10 = 24 bits
11 = > 25 bits
Note: The combination of address size, data size, and transaction type (MX) must be consistent
with the physical peripheral connection. In a multiplexed transaction, the entire address is
driven, regardless of the address size field.
22:23
DS
Data Size field—represents the peripheral data bus size (in bytes):
00 =1Byte
01 = 2 Bytes
10 = 3 Bytes (Not Supported)
11 = 4Bytes
24:25
Bank
Bank bits—are reflected on external AD lines (AD[26:25]) during address tenure of a multiplexed
transaction. Register bit 24 is the msb and appears on AD[26].
26:27
WTyp
Wait state Type bits—define application of wait states contained in WaitP and WaitX fields, as
follows:
00 = WaitX is applied to Read and Write cycles (WaitP is ignored)
01 = WaitX is applied to Read cycles, WaitP is applied to Write cycles
10 = WaitX is applied to Reads, WaitP/WaitX (16-bit value) is applied to Writes
11 = WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes
28
WS
Write Swap bit—If high, Endian byte swapping occurs during writes to a peripheral.
• For 8-bit peripherals, this bit has no effect.
• For 16-bit peripherals, byte swapping can occur.
• For 32-bit peripherals (possible in MUXed mode only) byte swap can occur.
1 = swap
0 = NO swap
2-byte swap is AB to BA, 4-byte swap is ABCD to DCBA.
Note: Transactions at less than the defined port size (i.e., data size) apply swap rules as above,
according to the current transaction size.
MPC5200B User’s Manual, Rev. 3
9-20
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
Table 9-8. Chip Select 1–7 Configuration Register Field Descriptions (Sheet 3 of 3)
Bits
Name
29
RS
Description
Read Swap bit—Same as WS, but swapping is done when reading data from a peripheral.
1 = swap
0 = NO swap
Note: Transactions at less than the defined port size (i.e., data size) apply swap rules as above,
according to the current transaction size.
30
WO
Write Only bit—If high peripheral is treated as a write-only device. An attempted Read access
results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or an interrupt
(as dictated by Chip Select Control Register IE bit). In any case, no transaction is presented to the
peripheral.
A bus error means the internal cycle is terminated with a transfer error acknowledge (ips_xfr_err
assertion to IP bus, TEA assertion to XL bus).
31
RO
Read Only bit—If high, peripheral is treated as a read-only device. An attempted Write access
results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or an interrupt (as
dictated by Chip Select Control Register IE bit). In any case, no transaction is presented to the
peripheral.
Note:
1. Large Flash mode is used, if AS is set to 11 and DS is set to 00 or 01.
2. MOST Graphics mode is used, if AS is set to 10 and DS is set to 11.
9.7.1.3
Chip Select Control Register
Address MBAR +
0x0318
0
1
2
R
4
5
6
Reserved
W
Reset:
3
8
9
10
ME
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 9-9. Chip Select Control Register
Table 9-9. Chip Select Control Register Field Descriptions
Bits
Name
Description
0:6
—
Reserved
7
ME
Master Enable bit—a global module enable bit. If this bit is low, register access can still occur, but
no external transactions are accepted. However, ME does not affect boot ROM operation on CS[0].
If software wishes to disable CS[0], it must write 0 to the Chip Select Boot ROM Configuration
Register enable bit (CE).
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-21
LocalPlus Bus (External Bus Interface)
9.7.1.4
Chip Select Status Register
Address MBAR + 0x031C
0
1
2
3
4
Reserved
8
9
10
11
12
13
14
15
ROerr
7
Rsvd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
W
Reset
6
WOerr
R
5
CSxerr
Reserved
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 9-10. Chip Select Status Register
Table 9-10. Chip Select Status Register Field Descriptions
Bits
Name
Description
0:1
—
2
WOerr
Write Only error—If 1, it indicates a Read access was attempted on a peripheral marked as
write-only.
This is a sticky bit and must be written with 1 to be cleared. This status bit is always active regardless
of bus error enable bit. The CS number that relates to the error is reflected in the CSxerr field.
3
ROerr
Read Only error—If 1, it indicates a Write access was attempted on a peripheral marked as
read-only.
This is a sticky bit and must be written with 1 to be cleared. This status bit is always active regardless
of bus error enable bit. The CS number that relates to the error is reflected in the CSxerr field.
4
—
5:7
CSxerr
8:31
—
Reserved
Reserved
Chip Select error—Indicates CS number associated with WOerr or ROerr.
Reserved
MPC5200B User’s Manual, Rev. 3
9-22
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.1.5
Chip Select Burst Control Register
Address MBAR + 0x0328
CW7 SLB7 Rsvd
W
6
CW6 SLB6 Rsvd
7
8
9
10
CW5 SLB5 Rsvd
11
12
13
14
CW4 SLB4 Rsvd
15
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CW3 SLB3 Rsvd
W
0
0
0
0
CW2 SLB2 Rsvd
0
0
0
0
CW1 SLB1 Rsvd
0
0
0
0
CW0 SLB0 Rsvd
0
0
0
BRE0
0
BRE1
0
BRE2
0
R
Reset
5
0
BRE3
Reset:
4
BRE4
R
3
BRE5
2
BRE6
1
BRE7
0
0
Figure 9-11. Chip Select Burst Control Register
Table 9-11. Chip Select Burst Control Register Field Descriptions (Sheet 1 of 3)
Bits
Name
Description
0
CW7
Chip Select 7 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
1
SLB7
Chip Select 7 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
2
—
3
BRE7
Chip Select 7 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
4
CW6
Chip Select 6 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
5
SLB6
Chip Select 6 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
6
—
7
BRE6
Chip Select 6 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
8
CW5
Chip Select 5 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-23
LocalPlus Bus (External Bus Interface)
Table 9-11. Chip Select Burst Control Register Field Descriptions (Sheet 2 of 3)
Bits
Name
Description
9
SLB5
Chip Select 5 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
10
—
11
BRE5
Chip Select 5 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
12
CW4
Chip Select 4 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
13
SLB4
Chip Select 4 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
14
—
15
BRE4
Chip Select 4 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
16
CW3
Chip Select 3 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
17
SLB3
Chip Select 3 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
18
—
19
BRE3
Chip Select 3 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
20
CW2
Chip Select 2 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
21
SLB2
Chip Select 2 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
22
—
23
BRE2
Chip Select 2 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
24
CW1
Chip Select 1 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
Reserved
Reserved
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
9-24
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
Table 9-11. Chip Select Burst Control Register Field Descriptions (Sheet 3 of 3)
Bits
Name
Description
25
SLB1
Chip Select 1 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
26
—
27
BRE1
Chip Select 1 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
28
CW0
Chip Select 0 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit
setting only applies in Large Flash or MOST Graphics Mode.
29
SLB0
Chip Select 0 Short/Long Burst, 0 for Short Burst only, 1 for Long Burst capable. Short burst is
8-bytes, used for Instruction fetches, and CDWF cache line bursts on XLB if cache wrap not capable.
Long Burst capable means that peripheral can do 32-byte burst which hardware will generate for
cache line aligned XLB bursts (and CDWF if peripheral tagged as cache wrap capable also).
This bit setting only applies in Large Flash or MOST Graphics Mode.
30
—
31
BRE0
Reserved
Reserved
Chip Select 0 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set
to enable any Bursting reads.
This bit setting only applies in Large Flash or MOST Graphics Mode.
Note:
1. CDWF is defined as critical double word first.
2. The bits for Chip Select 0 (CS0) control CS Boot too.
3. With a clock ratio 1:1:1 (66:66:66 MHz) it is not possible to burst in Large Flash mode.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-25
LocalPlus Bus (External Bus Interface)
9.7.1.6
Chip Select Deadcycle Control Register
Address MBAR + 0x032C
0
R
W
Reset
R
W
Reset
1
2
Reserved
3
DC7
4
5
6
Reserved
7
DC6
8
9
10
Reserved
11
DC5
12
13
14
Reserved
15
DC4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
0
0
DC3
1
Reserved
1
0
0
DC2
1
Reserved
1
0
0
DC1
1
Reserved
1
0
0
DC0
1
1
Figure 9-12. Chip Select Deadcycle Control Register
Table 9-12. Chip Select Deadcycle Control Register Field Descriptions
Bits
Name
0:1
—
2:3
DC7
4:5
—
6:7
DC6
8:9
—
10:11
DC5
12:13
—
14:15
DC4
16:17
—
18:19
DC3
20:21
—
22:23
DC2
24:25
—
Description
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 7 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 6 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 5 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 4 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 3 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 2 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
Reserved
MPC5200B User’s Manual, Rev. 3
9-26
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
Table 9-12. Chip Select Deadcycle Control Register Field Descriptions (continued)
Bits
Name
Description
26:27
DC1
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 1 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
28:29
—
30:31
DC0
Reserved
Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select 0 read
access and will occur in addition to any cycles which may already exist. These cycles are to provide
peripheral additional time to tri-state it's bus after a read operation. This is for all access types.
NOTE
Deadcycle counter is only used, if no arbitration to an other module (ATA
or PCI) of the shared local bus happens. If an arbitration happens the bus can
be driven within 4 IPB clocks by an other module.
9.7.2
SCLPC Registers
There are 6 32-bit BestComm Registers for the LocalPlus (SCLPC). These registers are located at an offset
from MBAR of 0x3C00. Register addresses are relative to this offset. Therefore, the actual register address
is: MBAR + 0x3C00 + register address
The following registers are available:
•
•
•
•
•
SCLPC Packet Size Register (0x3C00)
SCLPC Start Address Register (0x3C04)
SCLPC Control Register (0x3C08)
SCLPC Enable Register (0x3C0C)
SCLPC Bytes Done Status Register (0x3C14)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-27
LocalPlus Bus (External Bus Interface)
9.7.2.1
SCLPC Packet Size Register
Address MBAR + 0x3C00
0
1
2
3
4
5
6
8
9
10
11
12
13
14
15
0
W
Restart
R
Reset:
7
Reserved
Packet Size
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Packet Size
W
Reset
0
0
0
0
0
0
0
0
0
Figure 9-13. SCLPC Packet Size Register
Table 9-13. SCLPC Packet Size Register Field Descriptions
Bits
Name
Description
0:6
—
7
Restart
Once all registers have been programmed, software writes a 1 to this bit to begin a transfer.
It will auto-clear and always reads back as zero.
8:31
Packet Size
This 24-bit field represents the number of bytes SCLPC is to transact before going idle and
waiting for a Restart.
Note: The co-location of Restart bit and Packet_Size field allows Software to both Restart
a transaction AND change the Packet_Size in a single write. Maximum packet size is
16M-1 bytes.
Reserved
MPC5200B User’s Manual, Rev. 3
9-28
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.2.2
SCLPC Start Address Register
Address MBAR + 0x3C04
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Start Address
W
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Start Address
W
Reset
0
0
0
0
0
0
0
0
0
Figure 9-14. SCLPC Start Address Register
Table 9-14. SCLPC Start Address Register Field Descriptions
Bits
Name
Description
0:31
Start Address
Address of the first byte in the packet to be sent. This value must be aligned with the BPT
(Bytes Per Transaction) field, described below. This address will appear directly at the
peripheral and is completely independent of XLB address decoding logic.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-29
LocalPlus Bus (External Bus Interface)
9.7.2.3
SCLPC Control Register
Address MBAR + 0x3C08
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Flush
RWb
0
0
R
Reserved
CSX
Reserved
W
Reset:
0
16
0
17
0
18
0
19
0
20
0
21
0
22
0
23
0
24
0
25
0
26
0
27
0
28
0
29
30
31
R
Reserved
DAI
Reserved
BPT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-15. SCLPC Control Register
Table 9-15. SCLPC Control Register Field Descriptions
Bits
Name
Description
0:4
—
5:7
CSX
8:13
—
14
Flush
If set to 1, enables the assertion of SCLPC requestor at the completion of a *Read* Packet,
regardless of the actual state of the physical fifo ALarm. Requestor will de-assert once the
fifo goes empty. This is the fix for the familiar Stale Read Data fifo problem.
15
RWb
Read - Write bar. Controls direction of DMA transaction.
1 = SCLPC will read from the peripheral, i.e. Fifo Receive
Reserved
This field should be written with the Chip Select number associated with each DMA
transaction.
Note: LPC configuration registers associated with this CS also affect SCLPC transactions.
The two work together.
Reserved
0 = SCLPC will write to the peripheral, i.e. Fifo Transmit
16:22
—
23
DAI
24:27
—
28:31
BPT
Reserved
Disable Auto Increment. Normally, SCLPC and LPC will present sequential incrementing
addresses to the peripheral as the Packet proceeds. If the peripheral is operating as a single
address Fifo, then the DAI bit should be set to 1. When set, addresses to the peripheral will
be stuck at Start_Address for every transaction.
For DAI operation, the BPT field *MUST* be set to the port size of the peripheral.
Reserved
Bytes Per Transaction. Indicates number of bytes per transaction. The only valid entries in
this field are decimal/hex 1, 2, 4, or 8 bytes (i.e. binary 0001, 0010, 0100, 1000). BPT should
not be set to less than the peripheral port size, but certainly can be set to larger than the
peripheral port size. The higher the BPT value, the greater the throughput.
Note: Start_Address and Packet_Size values *must* be aligned/multiples of BPT. For DAI
operation, BPT must be set to the peripheral port size.
MPC5200B User’s Manual, Rev. 3
9-30
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.2.4
SCLPC Enable Register
Address MBAR + 0x3C0C
0
1
2
R
5
6
7
8
9
10
RC
11
12
13
14
Reserved
15
RF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AIE
NIE
0
0
R
Reserved
W
Reset
4
Reserved
W
Reset:
3
0
0
0
0
0
0
Reserved
0
0
0
0
ME
0
0
0
0
Figure 9-16. SCLPC Enable Register
Table 9-16. SCLPC Enable Register Field Descriptions
Bits
Name
Description
0:6
—
Reserved
7
RC
Reset Controller. This bit allows for a Software reset of the SCLPC state machine. Writing
a 1 to this bit will reset the SCLPC state machine. Reset will be maintained as long as this
bit is high. Software must write this bit low to release the reset and start operation.
Note:
1. Although RC does *not* reset this register interface, it does clear interrupt and interrupt
status conditions.
2. Never reset the SCLPC Controller during a transaction (tx or rx).
8:14
—
Reserved
15
RF
Reset Fifo. This is the Fifo software reset bit. Writing a 1 to this bit will reset the SCLPC Fifo.
The Fifo must not be in reset for normal operation. Software reset of the Fifo will clear the
fifo of data, reset its read/write pointers, but *not* disturb previously programmed Alarm and
Granularity settings.
Note: Good Practice would be for software to set and clear the RC and RF bits prior to
programming and starting a Packet.
16:21
—
Reserved
22
AIE
Abort Interrupt Enable. If set, and a fifo error occurs during packet transmission, a cpu
interrupt from SCLPC will be generated. In any case, the Packet will be terminated and an
Abort Status bit will be set.
Note: This bit does *not* affect the Requestor to BestComm in any way.
23
NIE
Normal Interrupt Enable. This bit, if set enables a cpu interrupt to occur at the end of a
normally terminated Packet. There is also a NT status bit which sets in any case.
Note: This bit does *not* affect the Requestor to BestComm in any way.
24:30
—
Reserved
31
ME
Master Enable. This bit must be set to 1 to allow a Restart to be generated to the SCLPC
state machine. Restart is achieved by writing 1 to Byte 0 of the Packet_Size register. This
ME bit must also be set for a Restart to occur.
Note: ME being low (inactive) will also clear Interrupt and Interrupt status. But it does *NOT*
affect the BestComm Requestor.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-31
LocalPlus Bus (External Bus Interface)
9.7.2.5
SCLPC Bytes Done Status Register
Address MBAR + 0x3C14
0
1
2
R
3
4
6
AT
Reserved
7
8
10
11
12
NT
Bytes Done
rwc
rwc
Read Only
13
14
15
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
Bytes Done
W
Read Only
Reset
9
Reserved
W
Reset
5
X
X
X
X
X
X
X
X
X
Note: X: Bit does not reset to a defined value.
Figure 9-17. SCLPC Bytes Done Status Register
Table 9-17. SCLPC Bytes Done Status Register Field Descriptions
Bits
Name
Description
0:2
—
Reserved
3
AT
Abort Termination. This bit will be set to 1 if the Packet has terminated abnormally (which is
only possible if a fifoError occurred).
Note: This bit is ANDed with the AIE bit above to generate a single CPU interrupt signal to
the core. This bit is sticky write to 1" for clearing the bit and clearing the interrupt.
Note: This bit (and any interrupt) is also cleared if; 1) RC bit is set, 2) ME bit is clear, or 3)
Restart occurs.
4:6
—
Reserved
7
NT
Normal Termination. This bit is set to 1 whenever a complete Packet has been transferred
successfully.
Note: This bit is ANDed with the NIE bit above to generate a single CPU interrupt signal to
the core. This bit is sticky write to 1 for clearing the bit and clearing the interrupt.
8:31
Bytes Done
Bytes Done is updated dynamically by the SCLPC state machine to represent the actual
number of bytes transmitted at a given point in time. At the normal conclusion of a Packet,
the bytes_done field should match the Packet_Size field.
MPC5200B User’s Manual, Rev. 3
9-32
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.3
SCLPC FIFO Registers
LPC uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction
change and flushes FIFO before changing directions. FIFO memory is 512Bytes (32 x 128).
LPC FIFO is controlled by six 32-bit registers. These registers are located at an offset from MBAR of
0x3C40. Register addresses are relative to this offset. Therefore, the actual register address is: MBAR +
0x3C40 + register address
Hyperlinks to the LPC FIFO registers are provided below:
• LPC Rx/Tx FIFO Data Word Register (0x3C40)
• LPC Rx/Tx FIFO Status Register (0x3C44)
• LPC Rx/Tx FIFO Control Register (0x3C48)
• LPC Rx/Tx FIFO Alarm Register (0x3C4C)
• LPC Rx/Tx FIFO Read Pointer Register (0x3C50)
• LPC Rx/Tx FIFO Write Pointer Register (0x3C54)
9.7.3.1
LPC Rx/Tx FIFO Data Word Register
LPC_rx/tx_fifo_data_word_register
Address MBAR + 0x3C14
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FIFO_Data_Word
W
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
R
FIFO_Data_Word
W
Reset
X
X
X
X
X
X
X
X
X
X
Note: X: Bit does not reset to a defined value.
Figure 9-18. LPC Rx/Tx FIFO Data Word Register
Table 9-18. LPC Rx/Tx FIFO Data Word Register Field Descriptions
Bits
Name
Description
0:31
FIFO_Data_Word
The FIFO data port. Reading from this location “pops” data from the FIFO, writing “pushes”
data into the FIFO. During normal operation the BestComm Controller pushes data here.
Note: ONLY full word access is allowed. If all byte enables are not asserted when accessing
this location, a FIFO error flag is generated.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-33
LocalPlus Bus (External Bus Interface)
9.7.3.2
LPC Rx/Tx FIFO Status Register
Address MBAR + 0x3C44
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Err
UF
OF
Full
HI
LO
Emty
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Table 9-19. LPC Rx/Tx FIFO Status Register
Table 9-20. LPC Rx/Tx FIFO Status Register Field Descriptions
Bits
Name
Description
0:8
—
Reserved
9
Err
Error—flag bit is essentially the logical OR of other flag bits and can be polled for detection of any
FIFO error. After clearing the offending condition, writing 1 to this bit clears flag.
10
UF
UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read beyond
empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
11
OF
OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
12
Full
FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
13
HI
High—FIFO requests attention, because high level alarm is asserted. To clear this condition, FIFO
must be read to a level below the setting in granularity bits.
14
LO
Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition, FIFO
must be written to a level in which the space remaining is less than the granularity bit setting.
15
Emty
16:31
—
FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
Reserved
MPC5200B User’s Manual, Rev. 3
9-34
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.3.3
LPC Rx/Tx FIFO Control Register
Address MBAR + 0x3C48
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
WFR
Reserved
GR
Reserved
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Table 9-21. LPC Rx/Tx FIFO Control Register
Table 9-22. LPC Rx/Tx FIFO Control Register Field Descriptions
Bits
Name
Description
0:1
—
2
WFR
3:4
—
Reserved
5:7
GR
Granularity—bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.
000 = FIFO waits to become completely full before stopping data request.
Reserved
When bit sets, FIFO Controller assumes next data write is End of Frame (EOF).
Note: This module does not support Framing. This bit should remain low.
001 = FIFO stops data request when only one long word of space remains.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-35
LocalPlus Bus (External Bus Interface)
9.7.3.4
LPC Rx/Tx FIFO Alarm Register
Address MBAR + 0x3C4C
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
9
Reserved
W
Reset:
8
0
0
0
0
Alarm
0
0
0
0
0
0
0
0
Table 9-23. LPC Rx/Tx FIFO Alarm Register
Table 9-24. LPC Rx/Tx FIFO Alarm Register Field Descriptions
Bits
Name
0:22
—
23:31
Alarm
9.7.3.5
Description
Reserved
User writes these bits to set low level “watermark”, which is the point where FIFO asserts request
for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32, alarm condition
occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not negate until high level
mark is reached, as specified by FIFO control register granularity bits.
LPC Rx/Tx FIFO Read Pointer Register
Address MBAR + 0x3C50
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
ReadPtr
0
0
0
0
0
0
0
0
Table 9-25. LPC Rx/Tx FIFO Read Pointer Register
Table 9-26. LPC Rx/Tx FIFO Read Pointer Register Field Descriptions
Bits
Name
0:22
—
23:31
ReadPtr
Description
Reserved
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. Value represents the Read address presented to the
FIFO RAM.
MPC5200B User’s Manual, Rev. 3
9-36
Freescale Semiconductor
LocalPlus Bus (External Bus Interface)
9.7.3.6
LPC Rx/Tx FIFO Write Pointer Register
Address MBAR + 0x3C54
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
WritePtr
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Table 9-27. LPC Rx/Tx FIFO Write Pointer Register
Table 9-28. LPC Rx/Tx FIFO Write Pointer Register Field Descriptions
Bits
Name
0:22
—
23:31
WritePtr
Description
Reserved
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. Value represents the Read address presented to the
FIFO RAM.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
9-37
LocalPlus Bus (External Bus Interface)
MPC5200B User’s Manual, Rev. 3
9-38
Freescale Semiconductor
Chapter 10
PCI Controller
10.1
Overview
The Peripheral Component Interface (PCI) Bus is a high-performance bus with multiplexed address and
data lines. It is especially suitable for high data-rate applications.
The MPC5200B PCI Controller module supports a 32-bit PCI initiator and target interface. As a target,
access to the internal XL bus is supported. As an initiator, the PCI controller is coupled directly to the XL
bus (as a slave) and available on the Communication Sub-System as a Multi-Channel DMA peripheral.
The 32-bit multiplexed address/data is shared with the ATA Controller and LocalPlus Controllers.
However, control signals are on separate pins and only one operation (PCI, ATA, or LocalPlus) can be
done at any given time.
The LocalPlus Large Flash and Most/Graphic interfaces are not compatible with any PCI operation. When
these interfaces are needed, the PCI internal controller must be disabled by setting bit 16 (PCI_DIS) of the
GPS Configuration register. See Section 7.3.2.1.1, “GPS Port Configuration Register.”
The MPC5200B contains PCI central resource functions such as the PCI Arbiter (see Section 10.5, “PCI
Arbiter”) and PCI reset control. The PCI bus clock is always sourced from the MPC5200B and either equal
to 1, 1/2 the frequency of the Slave bus clock (IP bus clock) or 1/4 the frequency of the XL Bus clock.
Even when the PCI internal controller is disabled, the PCI clock is sourced by the MPC5200B.
A PCI reset signal is provided and implemented as an open-drain pin. An external (on board) pull-up
resistor (e.g. 5.6 kOhm) is then required to ensure proper operation.
NOTE
If the PCI interface is NOT used (and internally disabled) the PCI control
pins must be terminated as indicated by the PCI Local Bus specification.
PCI control signals always require pull-up resistors to ensure that they
contain stable values when no agent is actively driving the bus. This
includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-1
PCI Controller
10.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Supports system clock: Slave (IP) bus (internal peripheral slave bus) to PCI bus frequency ratios
1:1, 2:1. Or the XL Bus to PCI bus frequency ratio 4:1 (e.g. PCI runs at 33 MHz while the XL Bus
bus runs at 132 MHz).
Compatible with PCI 2.2 specification
PCI initiator and target operation
Fully synchronous design
32-bit PCI Address/Data bus
PCI 2.2 Type 0 Configuration Space header
Supports the PCI 16/8 clock rule
PCI master Multi-Channel DMA or CPU access to PCI Bus
High transfer rates at 66Mhz PCI clock, 512 byte buffer
PCI to system bus address translation
Target response is medium DEVSEL generation
Initiator latency time-outs are NOT supported.
Automatic retry of target disconnects
Fast Back-to-Back transactions are NOT supported.
NOTE
The corresponding FC bit in the Configuration Status Register is fixed to ‘1’
indicating the opposite. Nonetheless no Fast Back-to-Back transaction is
supported.
MPC5200B User’s Manual, Rev. 3
10-2
Freescale Semiconductor
PCI Controller
10.1.2
Block Diagram
PCI
Arbiter
External REQ/GNT
Req/Gnt
PCI Controller Block
PCI
Controller
Config
CommBus
XL Bus
Slave Bus
Master
Bus Target
Master
Bus/
CommBus
Initiator
Config
Interface
External
PCI Bus
Target
Interface
Initiator
Interface
Figure 10-1. PCI Block Diagram
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-3
PCI Controller
10.2
PCI External Signals
Table 10-1. PCI External Signals
Signal
I/O
Definition
AD[31:0]
I/O
Multiplexed Address and Data Bus (Shared with ATA and LPC). AD31 is the most significant
bit while AD0 is the least significant as per the PCI specification. The entire PCI external bus
is little Endian ordered.
PCI_CBE[3:0]
I/O
Command/Bytes Enables
PCI_DEVSEL
I/O
Device Select
PCI_FRAME
I/O
Frame
PCI_IDSEL
I
Initialization Device Select
PCI_IRDY
I/O
Initiator Ready
PCI_PAR
I/O
Parity
PCI_CLK
O
PCI Clock
PCI_PERR
I/O
Parity Error
PCI_RST
O
PCI Reset
PCI_SERR
I/O
System Error
PCI_STOP
I/O
Stop
PCI_TRDY
I/O
Target Ready
For detailed description of the PCI bus signals, see the PCI Local Bus Specification, Revision 2.2.
10.2.1
PCI_AD[31:0] — Address/Data Bus
The PCI_AD[31:0] lines are a time multiplexed address data bus. The address is presented on the bus
during the address phase while the data is presented on the bus during one or more data phases.
10.2.2
PCI_CBE[3:0] — Command/Byte Enables
The PCI_CBE[3:0] lines are time multiplexed. The PCI command is presented during the address phase
and the byte enables are presented during the data phase.
10.2.3
PCI_DEVSEL — Device Select
The PCI_DEVSEL signal is asserted active low when MPC5200B decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.
10.2.4
PCI_FRAME — Frame
The PCI_FRAME signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is
deasserted when the initiator is ready to complete the final data phase.
MPC5200B User’s Manual, Rev. 3
10-4
Freescale Semiconductor
PCI Controller
10.2.5
PCI_IDSEL — Initialization Device Select
The PCI_IDSEL signal is asserted during a PCI Type 0 Configuration Cycle to address the PCI
Configuration header.
10.2.6
PCI_IRDY — Initiator Ready
The PCI_IRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
10.2.6.1
PCI_PAR — Parity
The PCI_PAR signal indicates the parity of data on the PCI_AD[31:0] and PCI_CBE[3:0] lines.
10.2.7
PCI_CLK — PCI Clock
The PCI_CLK signal is the clock for the internal PCI Controller and the external PCI system. The PCI
clock is also used as reference clock for the LocalPlus synchronous interfaces (Burst Flash, ATA). The
PCI_CLK is always sourced by the MPC5200B.
10.2.8
PCI_PERR — Parity Error
The PCI_PERR signal, if enabled, is asserted when a data phase parity error is detected.
10.2.9
PCI_RST — Reset
The PCI_RST signal is asserted active low by MPC5200B to reset the PCI bus. This signal is asserted after
MPC5200B reset and must be negated to enable usage of the PCI bus. An external shared pull-up resistor
is required on this pin.
10.2.10 PCI_SERR — System Error
The PCI_SERR signal, if enabled, is asserted by the MPC5200B only when an address phase parity error
is detected.
10.2.11 PCI_STOP — Stop
The PCI_STOP signal is asserted by the currently addressed target to indicate that it wishes to stop the
current transaction.
10.2.12 PCI_TRDY — Target Ready
The PCI_TRDY signal is asserted by the currently addressed target to indicate that it is ready to complete
the current data phase.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-5
PCI Controller
10.3
Registers
MPC5200B has several sets of registers that control and report status for the different interfaces to the PCI
controller: PCI Type 0 Configuration Space Registers, General Status/Control Registers, and
Communication Sub-System Interface Registers. All of these registers are accessible as offsets of MBAR
(the PCI interface is located starting at offset 0x0D00 relative to the MBAR register’s value, while the
BestComm interface starts at offset 0x3800). As an XL bus master, an external PCI bus master can access
MBAR space for register updates and the internal SRAM.
NOTE
PCI_RST is controlled by a bit in the register space and must first be cleared
before external PCI devices wake-up. In other words, an external PCI
master cannot load configuration software across the PCI bus until this bit
is cleared by internal means.
All registers are accessible at an offset of MBAR in the memory space. There are two module offsets for
PCI configuration space. One is allocated to the Communication Sub-System Interface registers and the
other to all other PCI Controller Registers including the standard Type 0 PCI Configuration Space.
Software reads from unimplemented registers return 0x00000000 and writes have no effect. See
Section 3.2, “Internal Register Memory Map” for module offsets and descriptions of module responses.
Table 10-2. PCI Register Map
Register
Offset
Mnemonic
Name
PCI Type 0 Configuration Registers
0x00
PCIIDR
Device ID/Vendor ID
0x04
PCISCR
Status/Command
0x08
PCICCRIR
Class Code/Revision ID
0x0C
PCICR1
Configuration 1Register
0x10
PCIBAR0
Base Address Register 0
0x14
PCIBAR1
Base Address Register 1
0x18
...
Reserved
0x24
0x28
PCICCPR
Cardbus CIS Pointer
0x2C
PCISID
Subsystem ID/Subsystem Vendor ID
0x30
PCIERBAR
Expansion ROM
0x34
PCICPR
0x3C
Capabilities Pointer
Reserved
0x38
PCICR2
Configuration 2 Register
0x40
...
Reserved
0x5C
MPC5200B User’s Manual, Rev. 3
10-6
Freescale Semiconductor
PCI Controller
Table 10-2. PCI Register Map (continued)
Register
Offset
Mnemonic
Name
General Control/Status Registers
0x60
PCIGSCR
Global Status/Control Register
0x64
PCITBATR0
Target Base Address Translation Register 0
0x68
PCITBATR1
Target Base Address Translation Register 1
0x6C
PCITCR
Target Control Register
0x70
PCIIW0BTAR
Initiator Window 0 Base/Translation Address Register
0x74
PCIIW1BTAR
Initiator Window 1 Base/Translation Address Register
0x78
PCIIW2BTAR
Initiator Window 2 Base/Translation Address Register
Reserved
0x7C
0x80
PCIIWCR
Initiator Window Configuration Register
0x84
PCIICR
Initiator Control Register
0x88
PCIISR
Initiator Status Register
0x8C
PCIARB
PCI Arbiter Register
0x90
...
Reserved
0xF4
0xF8
PCICAR
Configuration Address Register
Reserved
0xFC
Table 10-3. PCI Communication System Interface Register Map
Register
Offset
Mnemonic
Name
0x00
PCITPSR
Tx Packet Size
0x04
PCITSAR
Tx Start Address
0x08
PCITTCR
Tx Transaction Control Register
0x0C
PCITER
Tx Enables
0x10
PCITNAR
Tx Next Address
0x14
PCITLWR
Tx Last Word
0x18
PCITDCR
Tx Bytes Done Counts
0x1C
PCITSR
Tx Status
0x20
PCITPDCR
Tx Packets Done Counts
0x24
...
Reserved
0x3C
0x40
PCITFDR
Tx FIFO Data
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-7
PCI Controller
Table 10-3. PCI Communication System Interface Register Map (continued)
Register
Offset
Mnemonic
Name
0x44
PCITFSR
Tx FIFO Status
0x48
PCITFCR
Tx FIFO Control
0x4C
PCITFAR
Tx FIFO Alarm
0x50
PCITFRPR
Tx FIFO Read Pointer
0x54
PCITFWPR
Tx FIFO Write Pointer
0x58
...
Reserved
0x7C
0x80
PCIRPSR
Rx Packet Size
0x84
PCIRSAR
Rx Start Address
0x88
PCIRTCR
Rx Transaction Control Register
0x8C
PCIRER
Rx Enables
0x90
PCIRNAR
Rx Next Address
0x94
PCIRLWR
Rx Last Word
0x98
PCIRDCR
Rx Bytes Done Counts
0x9C
PCIRSR
Rx Status
0xA0
PCIRPDCR
Rx Packets Done Counts
0xA4
...
Reserved
0xBC
0xC0
PCIRFDR
Rx FIFO Data
0xC4
PCIRFSR
Rx FIFO Status
0xC8
PCIRFCR
Rx FIFO Control
0xCC
PCIRFAR
Rx FIFO Alarm
0xD0
PCIRFRPR
Rx FIFO Read Pointer
0xD4
PCIRFWPR
Rx FIFO Write Pointer
0xD8
...
Reserved
0xFC
MPC5200B User’s Manual, Rev. 3
10-8
Freescale Semiconductor
PCI Controller
10.3.1
PCI Controller Type 0 Configuration Space
MPC5200B supplies a type 0 PCI Configuration Space header. These registers are accessible as an offset
from MBAR (Section 3.2, “Internal Register Memory Map”) or through externally mastered PCI
Configuration Cycles.
NOTE
The internal PCI controller can discover itself (by means of connecting an
AD line [preferably AD24 to AD31]to the PCI _IDSEL input). It is
essential, when the PCI interface is used as a Target, to enable the internal
PCI controller to access via the external PCI bus its own PCI registers. This
is the only available way in order to clear any error flag RWC bit
(Read/Write/Clear bit).
Reg
Addr
PCI
DWord
Offset
Reg
0x100
0x00
PCIIDR
Device ID
Vendor ID
0x104
0x01
PCISCR
Status
Command
0x108
0x02
PCICCRIR
0x10C
0x03
PCICR1
0x110
0x04
PCIBAR0
BAR0
0x114
0x05
PCIBAR0
BAR1
0x118
0x06
...
...
0x124
0x09
0x128
0x0A
PCICCPR
0x12C
0x0B
PCISID
0x130
0x0C
Expansion ROM Base Address
0x134
0x0D
Reserved
0x138
0x0E
0x13C
0x0F
na
0x10
na
...
na
0x3F
[31:24]
[23:16]
[15:8]
[7:0]
Class Code
BIST
Revision ID
Header Type
Latency Timer
Cache Line Size
Reserved
CardBus CIS Pointer
Subsystem ID
Subsystem Vendor ID
Cap_Ptr
Reserved
PCICR2
Min_Gnt
Max_Lat
Int Pin
Int Line
Reserved
PCI Dword Reserved space (0x10–0x3F) can be accessed only from an external PCI Configuration access.
NOTE
A PCI Double Word (DWORD) is a 32 bit long word. A PowerPC Double
Word is instead a 64 bit word (according to the EABI rule) while a Word is
a 32 bit value. In the following PCI Configuration space a DWORD refers
always to a 32 bit word.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-9
PCI Controller
10.3.1.1
Device ID/ Vendor ID Registers PCIIDR(R)
MBAR + 0x0D00
0
1
2
3
4
5
6
7
R
8
9
10
11
12
13
14
15
25
26
27
28
29
30
31
Device ID
W
Reset
0x5809
16
17
18
19
20
21
22
23
R
24
Vendor ID
W
Reset
0x1057
Figure 10-2. Device ID/Vendor ID Registers PCIIDR(R)
Table 10-4. Device ID/Vendor ID Registers PCIIDR(R) Field Descriptions
Bits
Name
0:15
Device ID
This field is read-only and represents the PCI Device Id assigned to MPC5200B
Its value is: 0x5809.
16:31
Vendor ID
This field is read-only and represents the PCI Vendor Id assigned to MPC5200B
Its value is: 0x1057.
10.3.1.2
Description
Status/Command Registers PCISCR(R/RW/RWC)
MBAR + 0x0D04
0
1
2
3
4
5
6
R
PE
SE
MA
TR
TS
W
rwc
rwc
rwc
rwc
rwc
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
F
S
MW
Sp
B
M
0
0
0
0
0
0
DT
7
8
9
10
11
DP
FC
R
66M
C
12
13
14
15
Reserved
Reset
rwc
R
St
Reserved
V
PER
IO
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 10-3. Status/Command Registers PCISCR(R/RW/RWC)
Bits 31-27 and 24 are read-write-clear (RWC).
• Hardware can set RWC bits, but cannot clear them.
• Only PCI configuration cycles can clear RWC bits that are currently set by writing a 1 to the bit
location. Writing a 1 to a RWC bit that is currently a 0 or writing a 0 to any RWC bit has no effect.
MPC5200B User’s Manual, Rev. 3
10-10
Freescale Semiconductor
PCI Controller
Table 10-5. Status/Command Registers PCISCR (R/RW/RWC) Field Descriptions
Bits
Name
Description
0
Parity Error
Detected
(PE)
This bit is set when a parity error is detected, even if the Parity Error Response bit in the Command
Register (bit 6) is disabled. A CPU interrupt will be generated if the PCIGSCR[PEE] bit is set. This
register is read-write-clear (RWC) via PCI configuration cycles.
1
System Error
Signalled
(SE)
This bit is set whenever MPC5200B generates a PCI System Error on the SERR line. This register
is read-write-clear (RWC) via PCI configuration cycles.
2
Master Abort
Received
(MA)
This bit is set whenever MPC5200B is the PCI master and terminates a transaction (except for
Special Cycle) with a Master-Abort. This register is read-write-clear (RWC) via PCI configuration
cycles.
3
Target Abort
Received
(TR)
This bit is set whenever MPC5200B is the PCI master and a transaction is terminated by a Target
Abort from the currently-addressed target. This register is read-write-clear (RWC) via PCI
configuration cycles.
4
Target Abort
Signalled
(TS)
This bit is set whenever MPC5200B is the PCI target and it terminates a transaction with a Target
Abort. This register is read-write-clear (RWC) via PCI configuration cycles.
5:6
DEVSEL#
Timing
(DT)
Fixed to 01. These bits encode a medium DEVSEL timing. This defines the slowest DEVSEL timing
when MPC5200B is the PCI target (except configuration accesses).
7
Master Data
Parity
Error
(DP)
This bit applies only when MPC5200B is PCI master and is set only if the following conditions are
met:
• MPC5200B-as-master sets PERR itself during a read or detected it asserted by the target
during a write
• The Parity Error Response bit in the Command Register, bit 6, is set to 1
This register is read-write-clear (RWC) via PCI configuration cycles.
8
Fast
Back-to-Back
Capable
(FC)
Fixed to 1. The MPC5200B PCI controller does NOT support Fast Back-to-Back transactions.
9
Reserved
(R)
Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (User Defined Features) Supported bit.
1 = Supported User Defined Features
0 = Does not support UDF
10
66 MHz
Capable
(66M)
11
Capabilities
List
(C)
12:21
Reserved
22
Fast
Back-to-Back
Transfer Enable
(F)
23
SERR enable
(S)
Fixed to 1. This bit indicates that the PCI controller is 66 MHz capable.
Fixed to 0. This bit indicates that the PCI controller does not implement the New Capabilities List
Pointer Configuration Register in DWORD 13 of the Configuration Space.
These bits are reserved.
The MPC5200B PCI controller does NOT support Fast Back-to-Back transactions.
Setting this bit has no effect.
This bit is an enable bit for the SERR driver. A value of zero disables the SERR driver. A value of
1 enables the SERR driver. Note: Address parity errors are reported only if this bit and bit 6 are 1.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-11
PCI Controller
Table 10-5. Status/Command Registers PCISCR (R/RW/RWC) Field Descriptions (continued)
Bits
Name
Description
24
Address and
Data Stepping
(St)
Fixed to 0. This bit indicates that the PCI controller never uses address/data stepping. Initialization
software should write a 0 to this bit location.
25
Parity Error
Response
(PER)
This bit controls the device’s response to parity errors. When set and a parity error is detected, the
PCI controller asserts PERR. When the bit is “0”, the device sets its Detected Parity Error status
bit (bit 0) in the event of a parity error, but does not assert PERR.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles).
26
VGA Palette
Snoop Enable
(V)
Fixed to 0. This bit indicates that the PCI controller is not VGA compatible. Initialization software
should write a 0 to this bit location.
27
Memory Write
and Invalidate
Enable
(MW)
This bit is an enable for using the Memory Write and Invalidate command. When this bit is 1,
MPC5200B-as-master may generate the command. When it is 0, Memory Write must be used
instead. This bit is programmable (read/write from both the IP bus and PCI bus Configuration
cycles).
28
29
30
31
Special Cycle This bit is to determine whether or not to ignore PCI Special Cycles. Since MPC5200B-as-target
Monitor or Ignore does not recognize messages delivered via the Special Cycle operation, a value of 1 should never
(Sp)
be programmed to this register. This bit, however, is programmable (read/write from both the IP bus
and PCI bus Configuration cycles).
Bus Master
Enable
(B)
This bit indicates whether or not MPC5200B has the ability to serve as a master on the PCI bus. A
value of 1 indicates this ability is enabled. If MPC5200B is used as a master on the PCI bus (via
XL bus or CommBus), a 1 should be written to this bit during initialization. Even if set to 0, a
transaction initiated by an internal master (the core, BestComm) is allowed to take place. It is meant
to be read by configuration software.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles).
Memory Access This bit controls the PCI controller’s response to Memory Space accesses. A value of 0 disables
Control
the response. A value of 1 allows the controller to recognize a Memory access.
(M)
This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles).
IO access
Control
(IO)
Fixed to 0. This bit is not implemented because there is no MPC5200B IO type space accessible
from the PCI bus. The PCI base address registers are Memory address ranges only. Initialization
software should write a 0 to this bit location.
MPC5200B User’s Manual, Rev. 3
10-12
Freescale Semiconductor
PCI Controller
10.3.1.3
Revision ID/ Class Code Registers PCICCRIR(R)
MBAR + 0x0D08
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
25
26
27
28
29
30
31
Class Code
W
Reset
0x0680
16
17
R
18
19
20
21
22
23
24
Class Code (continued)
Revision ID
0x00
0x00
W
Reset
Figure 10-4. Revision ID/ Class Code Registers PCICCRIR(R)
Table 10-6. Revision ID/ Class Code Registers PCICCRIR(R) Field Descriptions
Bits
Name
Description
0:23
Class Code
This field is read-only and represents the PCI Class Code assigned to MPC5200B
Its value is: 0x068000. (Other bridge device)
24:31
Revision ID
This field is read-only and represents the PCI Revision Id for this version of MPC5200B. Its value
is: 0x00.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-13
PCI Controller
10.3.1.4
Configuration 1 Register PCICR1(R/RW)
MBAR + 0x0D0C
0
1
2
3
R
4
5
6
7
8
9
10
BIST
11
12
13
14
15
Header Type
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
Reset
Lat Timer[2:0]
Lat timer[7:3]
0
0
0
0
0
0
0
0
Reserved
0
0
0
Cache Line Size
0
0
0
0
0
Figure 10-5. Configuration 1 Register PCICR1(R/RW)
Table 10-7. Configuration 1 Register PCICR1(R/RW) Field Descriptions
Bits
0:7
Name
Built-In Self Test Fixed to 0x00. The PCI controller does not implement the Built-In Self Test register. Initialization
(BIST)
software should write a 0x00 to this register location.
8:15
Header Type
16:23
Latency Timer
28:31
Description
Fixed to 0x00. The PCI controller implements a Type 0 PCI Configuration Space Header.
Initialization software should write a 0x00 to this register location.
This register contains the latency timer value, in PCI clocks, used when MPC5200B is the PCI
master. The lower three bits of the register are hardwired low and the upper five bits are
programmable (read/write from both the IP bus and PCI bus Configuration cycles).
Note: The MPC5200B does NOT support initiator latency time-outs, the internal PCI Arbiter does
not support preemption of the internal masters XIPCI or SCPCI. The internal master is
granted until the transaction has been completed. The Latency Timer (LT) cannot terminate
any transfer.
Cache Line Size The four lower bits of this register are programmable (read/write from both the IP bus and PCI bus
Configuration cycles). The value programmed specifies the cacheline size in units of DWORDs.
MPC5200B User’s Manual, Rev. 3
10-14
Freescale Semiconductor
PCI Controller
10.3.1.5
Base Address Register 0 PCIBAR0(RW)
MBAR + 0x0D10
0
1
2
3
4
5
R
7
8
9
10
11
12
13
Base Address 0
W
Reset
6
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
pref
Reserved
IO/M
#
range
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-6. Base Address Register 0 PCIBAR0(RW)
Table 10-8. Base Address Register 0 PCIBAR0(RW) Field Descriptions
Bits
Name
Description
0:13
Base Address
Register 0
(BAR0)
MPC5200B PCI Base Address Register 0 (256Kbyte). Applies only when MPC5200B is target.
These bits are programmable (read/write from both the IP bus and PCI bus Configuration cycles).
This BAR register should be used to point at the internal MPC5200B register space (MBAR)
14:27
Reserved
28
prefetchable
access
(pref)
29:30
range
Fixed to 00. This register indicates that base address 0 is 32 bits wide and can be mapped
anywhere in 32-bit address space. Configuration software should write 00 to these bit locations.
31
IO or Memory
Space
(IO/M#)
Fixed to 0. This bit indicates that BAR0 is for memory space. Configuration software should write
a 0 to this bit location.
0 = Memory
These bits are reserved.
Fixed to 0. This bit indicates that the memory space defined by BAR0 is NOT prefetchable.
Configuration software should write a 0 to this bit location.
1 = I/O
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-15
PCI Controller
10.3.1.6
Base Address Register 1 PCIBAR1(RW)
MBAR + 0x0D14
0
R
W
Reset
1
2
3
4
5
6
7
Base
Address 1
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
pref
IO/M
#
range
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-7. Base Address Register 1 PCIBAR1(RW)
Table 10-9. Base Address Register 1 PCIBAR1(RW) Field Descriptions
Bits
Name
Description
0:1
Base Address
Register 1
(BAR1)
MPC5200B PCI Base Address Register 1 (1Gbyte). Applies only when MPC5200B is target. These
bits are programmable (read/write from both the IP bus and PCI bus Configuration cycles). This
BAR register shall be used to point at the local SDRAM/DDR Memory Space.
Note: The address ‘Window’ is much larger than the maximum theoretically supported physical
memory.
Note: This register should not point to the LocalPlus Memory Space. This is not supported.
2:27
Reserved
28
prefetchable
access
(pref)
Fixed to 1. This bit indicates that the memory space defined by BAR1 is prefetchable. Configuration
software should write a 1 to this bit location.
29:30
range
Fixed to 00. This register indicates that base address 1 is 32 bits wide and can be mapped
anywhere in 32-bit address space. Configuration software should write 00 to these bit locations.
31
IO or Memory
Space
(IO/M#)
Fixed to 0. This bit indicates that BAR1 is for memory space. Configuration software should write
a 0 to this bit location.
0 = Memory
These bits are reserved.
1 = I/O
MPC5200B User’s Manual, Rev. 3
10-16
Freescale Semiconductor
PCI Controller
10.3.1.7
CardBus CIS Pointer Register PCICCPR(RW)
MBAR + 0x0D28
This optional register contains the pointer to the Card Information Structure (CIS) for the CardBus card.
All 32 bits of the register are programmable by the Slave bus. It can only be read from the PCI Bus. Its
reset value is 0x00000000.
10.3.1.8
Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)—MBAR +
0x0D2C
The Subsystem Vendor ID register contains the 16-bit manufacturer identification number of the add-in
board or subsystem that contains this PCI device. The Subsystem ID register contains the 16-bit subsystem
identification number of the add-in board or subsystem that contains this PCI device. A value of zero in
these registers indicates there isn’t a Subsystem Vendor and Subsystem ID associated with the device. If
used, software must write to these registers before any PCI bus master reads them.
All 32 bits of the register are programmable by the Slave bus. They can only be read from the PCI Bus.
The reset value is 0x00000000.
10.3.1.9
Expansion ROM Base Address PCIERBAR(R)
MBAR + 0x0D30
Not implemented. Fixed to 0x00000000.
10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)
MBAR + 0x0D34
Not implemented. Fixed to 0x00000000.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-17
PCI Controller
10.3.1.11 Configuration 2 Register PCICR2 (R/RW)
MBAR + 0x0D3C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Maximum Latency
Minimum Grant
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Interrupt Pin
Interrupt Line
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-8. Configuration 2 Register PCICR2 (R/RW)
Table 10-10. Configuration 2 Register PCICR2 (R/RW) Field Descriptions
Bits
Name
Description
0:7
Maximum
Latency
(Max_Lat)
Specifies how often, in units of 1/4 microseconds, the PCI controller would like to have access to
the PCI bus as master. A value of zero indicates the device has no stringent requirement in this
area. The register is read/write to/from the Slave bus, but read only from the PCI bus.
Note: The MPC5200B does NOT support initiator latency time-outs, the internal PCI Arbiter does
not support preemption of the internal masters XIPCI or SCPCI. The internal master is
granted until the transaction has been completed. The Latency Timer (LT) cannot terminate
any transfer.
8:15
Minimum Grant
(Min_Gnt)
The value programmed to this register indicates how long the PCI controller as master would like
to retain PCI bus ownership whenever it initiates a transaction. The register is programmable from
the Slave bus, but read only from the PCI bus.
16:23
Interrupt Pin
Fixed to 0x00. Indicates that this device does NOT use an interrupt request pin.
24:31
Interrupt Line
Fixed to 0x00. The Interrupt Line register stores a value that identifies which input on a PCI
interrupt controller the function’s PCI interrupt request pin. Since no interrupt request pin is used,
as specified in the Interrupt Pin register, this register has no function.
10.3.2
General Control/Status Registers
The General Control/Status Registers primarily address the configurability of the XL bus Initiator and
Target Interfaces, though some also address global options which affect the Multi-Channel DMA interface
(BestComm). These registers are accessed primarily internally as offsets of MBAR, but can also be
accessed by an external PCI master if PCI base and Target base address registers are configured to access
the space. See Section 10.6.2, “Address Maps” on configuring address windows.
MPC5200B User’s Manual, Rev. 3
10-18
Freescale Semiconductor
PCI Controller
10.3.2.1
Global Status/Control Register PCIGSCR(RW)
MBAR + 0x0D60
0
1
2
3
4
5
R
W
Reset
8
9
10
11
12
13
14
15
ipg_clk to PCI_CLK
differential
PE
SE
rwc
rwc
rwc
0
0
0
0
0
x
x
x
0
0
0
0
0
x
x
x
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Rsvd
BME
PEE
SEE
0
0
0
0
W
R
7
BM
Rsvd
Reset
6
XL Bus_clk
to PCI_CLK
differential
Rsvd
Reserved
Reserved
0
0
0
0
0
0
PR
0
0
0
0
0
0
Figure 10-9. Global Status/Control Register PCIGSCR(RW)
Table 10-11. Global Status/Control Register PCIGSCR(RW) Field Descriptions
Bits
Name
Description
0
Reserved
1
Broken Master
Detected
(BM)
This bit is set when the PCI Arbiter detects a broken external PCI master.
Note: In case of broken master detection the external PCI request will be ignored until external
deassertion of PCI request or until a software reset (PCI Arbiter Softreset) or by Hardreset
is detected. After broken master detection (PCI bus idle for 16 clocks) the arbiter will ignore
any FRAME# assertion.
A CPU interrupt will be generated if the PCIGSCR[BME] bit is set. This is a RWC
(Read/WriteClear) bit: to clear it, software must write a ‘1’ at this position.
2
PERR
Detected
(PE)
This bit is set when the PCI Parity Error line, PERR, asserts (any device). A CPU interrupt will be
generated if the PCIGSCR[PEE] bit is set. This is a RWC (Read/WriteClear) bit: to clear it,
software must write a ‘1’ at this position.
3
SERR
Detected
(SE)
This bit is set when a PCI System Error line, SERR, asserts (any device). A CPU interrupt will be
generated if the PCIGSCR[SEE] bit is set. This is a RWC (Read/WriteClear) bit: to clear it,
software must write a ‘1’ at this position.
4
Reserved
Unused bit. Software should write zero to this register.
5:7
XL Bus_clk to
PCI_CLK
differential
(read only)
8:12
Reserved
Unused bits. Software should write zero to this register.
13:15
ipg_clk to
PCI_CLK
differential
(read only)
This bit field stores the Slave bus clock to the PCI clock divide ratio. This field is read-only and
the reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can read these bits
to determine a valid ratio. If the register contains a differential value that does not reflect the PLL
settings, the PCI controller could malfunction.
16
Reserved
Unused bit. Software should write zero to this register.
17
Broken Master
Interrupt Enable
(BME)
Unused bit. Software should write zero to this register.
This bit field stores the XL bus clock to the PCI clock divide ratio. This field is read-only and the
reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can read these bits to
determine a valid ratio. If the register contains a differential value that does not reflect the PLL
settings, the PCI controller could malfunction.
This bit enables CPU Interrupt generation when a broken Master is detected. When enabled,
software must clear the BM status bit to clear the interrupt condition.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-19
PCI Controller
Table 10-11. Global Status/Control Register PCIGSCR(RW) Field Descriptions (continued)
Bits
Name
18
Parity Error
Interrupt Enable
(PEE)
This bit enables CPU Interrupt generation when the PCI Parity Error signal, PERR, is sampled
asserted. When enabled and PERR asserts, software must clear the PE status bit to clear the
interrupt condition.
19
System Error
Interrupt Enable
(SEE)
This bit enables CPU Interrupt generation when a PCI System Error is detected on the SERR
line. When enabled and SERR asserts, software must clear the SE status bit to clear the interrupt
condition.
20:30
Reserved
31
PCI
Reset
(PR)
10.3.2.2
Description
Unused bits. Software should write zero to this register.
This bit controls the external PCI RST. When this bit is cleared, the external PCI RST deasserts.
Setting this bit does not reset the internal PCI controller. The application software must not initiate
PCI transactions while this bit is set. It is recommended that this bit be programmed last.
The reset value of the bit is 1 (PCI RST asserted).
Note: A global PCI reset should be asserted just by the MPC5200B controller. Any external
common reset controller signal will be ignored by the internal PCI controller.
Target Base Address Translation Register 0 PCITBATR0(RW)
MBAR + 0x0D64
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Base Address Translation 0
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
En
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-10. Target Base Address Translation Register 0 PCITBATR0(RW)
Table 10-12. Target Base Address Translation Register 0 PCITBATR0(RW) Field Descriptions
Bits
Name
Description
0:13
Base Address
Translation 0
This base address register corresponds to a hit on the BAR0 in MPC5200B PCI Type 0
Configuration space register from PCI space. When there is a hit on MPC5200B PCI BAR0
(MPC5200B as Target), the upper 14 bits of the external PCI address (256Kbyte boundary) are
written over by this register value to address some space in MPC5200B. In normal operation,
this value should be written during the initialization sequence only to point to the internal
Register space.
14:30
Reserved
Unused bits. Software should write zero to this register.
31
Enable 0
This bit enables a transaction in BAR0 space. If this bit is zero and a hit on MPC5200B PCIBAR0
occurs, the target interface gasket will abort the PCI transaction.
MPC5200B User’s Manual, Rev. 3
10-20
Freescale Semiconductor
PCI Controller
10.3.2.3
Target Base Address Translation Register 1 PCITBATR1(RW)
MBAR + 0x0D68
0
1
2
3
4
5
6
7
R Base Address
W Translation 1
Reset
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
En
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-11. Target Base Address Translation Register 1 PCITBATR1(RW)
Table 10-13. Target Base Address Translation Register 1 PCITBATR1(RW) Field Descriptions
Bits
Name
Description
0:1
Base Address
Translation 1
This base address register corresponds to a hit on the BAR1 in MPC5200B PCI Type 0
Configuration space register (PCI space). When there is a hit on MPC5200B PCI BAR1
(MPC5200B as Target), the upper 2 bits of the external PCI address (1Gbyte boundary) are
written over by this register value to address some 1Gbyte space in MPC5200B. This register can
be reprogrammed to move the window of MPC5200B address space accessed during a hit in
PCIBAR1. It should be written by software during initialization to point to the internal SDR/DDR
memory space.
Note: This register should not point to the LocalPlus Memory Space. This is not supported.
2:30
Reserved
Unused bits. Software should write zero to this register.
31
Enable 1
This bit enables a transaction in BAR1 space. If this bit is zero and a hit on MPC5200B PCI BAR1
occurs, the target interface gasket will abort the PCI transaction.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-21
PCI Controller
10.3.2.4
Target Control Register PCITCR(RW)
MBAR + 0x0D6C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
LD
Reserved
P
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
R
Reserved
WCD
Write Combine Timer [7:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-12. Target Control Register PCITCR(RW)
Table 10-14. Target Control Register PCITCR(RW) Field Descriptions
Bits
Name
Description
0:6
Reserved
7
Latrule
Disable
(LD)
8:14
Reserved
15
Prefetch Reads
(P)
16:22
Reserved
23
Write Combine
Disable
(WCD)
This control bit applies only when MPC5200 is Target. When set, it prevents the PCI Controller from
automatically combining write data to be sent out on the XL bus as a burst, if possible. Instead, data
is transferred as soon as possible on the XL bus as single-beat transactions.
Better target write performance is achieved when this bit cleared.
24:31
Write Combine
Timer (WCT)
This register contains the timer value, in PCI clocks, used when a partial burst has been buffered
in the target write data path and write data stops being transferred to local memory from the
external PCI device. Every time a sequential beat of write data is stored in the buffer, the counter
is reset with this value.
If partial burst data has been buffered, thereby activating the count-down counter, and this field is
reprogrammed to a value less than the current counter value, the counter will jump down to the new
write combine timer value. This way, software can force the write buffer to flush data to the XL bus
more quickly than when the counter was initialized.
The reset value of the write combine timer is 0x08. All 8 bits are programmable.
Unused bits. Software should write zero to this register.
This control bit applies only when MPC5200B is Target. When set, it prevents the PCI Controller
from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.
The bit must be set before the 15th PCI clock for the first transfer and before the 7th clock for other
transfers.
Unused bits. Software should write zero to this register.
This bit controls fetching a line from memory in anticipation of a request from the external master.
The target interface will continue to prefetch lines from memory as long as PCI_FRAME is asserted
and there is space to store the data in the target read buffer.
Note: This bit only applies to PCI reads in the address range for BAR 1 (prefetchable memory).
Note: Prefetching is performed in response to a PCI memory-read-multiple command even if this
bit is cleared.
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
10-22
Freescale Semiconductor
PCI Controller
10.3.2.5
Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)
MBAR + 0x0D70
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Window 0 Base Address
Window 0 Address Mask
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Window 0 Translation Address
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-13. Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)
Table 10-15. Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW) Field Descriptions
Bits
Name
Description
0:7
Window 0 Base
Address
One of three base address registers to determine an XL bus hit on PCI. At most, the upper byte
of the address is decoded. The Window 0 Address Mask register determines what bits of this
register to compare the XL bus address against to generate the hit.
Note: The smallest possible Window is a 16 MByte block.
8:15
Window 0 Address The Window 0 Address Mask Register masks the corresponding XL bus base address bit of the
Mask
base address for Window 0 (Window 0 Base Address) to instruct the address decode logic to
ignore or “don’t care” the bit. If the base address mask bit is set, the associated base address bit
of Window 0 is ignored when generating the PCI hit. Bit 16 masks bit 24, bit 17 masks bit 25, and
so on.
0 Corresponding address bit is used in address decode
1 Corresponding address bit is ignored in address decode
For XL Bus accesses to Window 0 address range, this byte also determines which upper 8 bits
of the XL Bus address to pass on for presentation as a PCI address. Any address bit used to
decode the XL Bus address, indicated by a “0”, will be translated. This provides a way to overlay
a PCI page address onto the XL Bus address. A “1” in the Address Mask byte indicates that the
XL Bus address bit will be passed to PCI unaltered.
16:23
Window 0
Translation
Address
For any translated bit (described above), the corresponding value here will be driven onto the PCI
address bus for the XL bus Window 0 address hit.
Note: The Window Translation operation can not be turned off. If a direct mapping from XL Bus
to PCI space is desired, program the same value to both the Window Base Address
Register and Window Translation Address Register.
24:31
Reserved
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-23
PCI Controller
10.3.2.6
Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW)
MBAR + 0x0D74
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Window 1 Base Address
Window 1 Address Mask
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Window 1 Translation Address
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-14. Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW)
10.3.2.7
Initiator Window 2 Base/Translation Address Register
PCIIW2BTAR (RW)
MBAR + 0x0D78
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Window 2 Base Address
Window 2 Address Mask
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Reserved
Window 2 Translation Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-15. Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW)
MPC5200B User’s Manual, Rev. 3
10-24
Freescale Semiconductor
PCI Controller
10.3.2.8
Initiator Window Configuration Register PCIIWCR(RW)
MBAR + 0x0D80
0
R
3
4
5
6
7
8
9
Window 0
Control
10
11
12
13
14
15
Window 1
Control
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Window 2
Control
Reserved
W
Reset
2
Reserved
W
Reset
1
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
Figure 10-16. Initiator Window Configuration Register PCIIWCR(RW)
Table 10-16. Initiator Window Configuration Register PCIIWCR(RW) Field Descriptions
Bits
Name
0:3
Reserved
4:7
Description
Reserved register. Write a zero to this register.
Window 0 Control Bit[3] - IO/M#.
[3:0]
0 = Window is mapped to PCI memory
1 = Window is mapped to PCI I/O
Bit[2:1] - PCI Read Command (PRC).
If bit[3] is programmed memory, “0”, then these bits are used to determine the type of PCI
memory command to issue. See <Cross Refs Helv 9>Table 10-63. If bit[3] is set to “1”, the value
of these bits are meaningless.
00 = PCI Memory Read
01 = PCI Memory Read Line
10 = PCI Memory Read Multiple
11 = Reserved
Note: A PCI write command is automatically detected and needs not to be explicitly configured.
No PCI Write and Invalidate command is allowed in any case with this interface.
Bit[0] - Enable.
This bit is set to indicate the address registers that control the XL Bus initiator interface access
to PCI initialized and will be used. The PCI Controller can begin to decode XL Bus PCI accesses.
0 = Do not decode XL Bus PCI accesses to Window
1 = Registers initialized - decode accesses to Window
8:11
Reserved
12:15
Window 1Control
[3:0]
16:19
Reserved
20:23
24:31
Reserved register. Write a zero to this register.
Bit[3] - IO/M#.
Bit[2:1] - PRC.
Bit[0] - Enable.
Reserved register. Write a zero to this register.
Window 0 Control Bit[3] - IO/M#.
[3:0]
Bit[2:1] - PRC.
Bit[0] - Enable.
Reserved
Reserved register. Write a zero to this register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-25
PCI Controller
10.3.2.9
Initiator Control Register PCIICR(RW)
MBAR + 0x0D84
0
1
2
3
4
5
6
7
REE
IAE
TAE
8
9
10
11
12
13
14
15
R
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
R
Reserved
Maximum Retries
W
Reset
0
0
0
0
0
0
0
0
1
1
1
1
1
Figure 10-17. Initiator Control Register PCIICR(RW)
Table 10-17. Initiator Control Register PCIICR(RW) Field Descriptions
Bits
Name
Description
0:4
Reserved
5
Retry Error
Enable
(RE)
This bit enables CPU Interrupt generation in the case of Retry Error termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software should poll
the status bits to prevent a possible lock-up condition.
6
Initiator Abort
Enable
(IAE)
This bit enables CPU Interrupt generation in the case of Initiator Abort termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software should poll
the status bits to prevent a possible lock-up condition.
7
Target Abort
Enable
(TAE)
This bit enables CPU Interrupt generation in the case of Target Abort termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software should poll
the status bits to prevent a possible lock-up condition.
8:23
Reserved
Unused bits. Software should write zero to this register.
24:31
Maximum
Retries
This bit field controls the maximum number of automatic PCI retries to permit per transaction. The
retry counter is reset at the beginning of each transaction (i.e. it is not cumulative). Setting the
Maximum Retries to 0x00 allows infinite automatic retry cycles.
A finite (0x01 to 0xff) Maximum Retries value will detect the maximum PCI retries and the next retry
will abort the transaction. For a Write transaction an interrupt will be generated, for a Read
transaction an interrupt and a TEA on the XL Bus will be generated.
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
10-26
Freescale Semiconductor
PCI Controller
10.3.2.10 Initiator Status Register PCIISR(RWC)
MBAR + 0x0D88
0
1
2
3
4
R
5
6
7
RE
IA
TA
rwc
rwc
rwc
8
9
10
Reserved
12
13
14
15
Reserved
W
Reset
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-18. Initiator Status Register PCIISR(RWC)
Table 10-18. Initiator Status Register PCIISR(RWC) Field Descriptions
Bits
Name
Description
0:4
Reserved
5
Retry
Error
(RE)
This flag is set if Max_Retries is set to a finite value (0x01 through 0xff) and the Target has
performed Max_Retries number of retry disconnects for a single transaction. A retry error would
generally indicate a broken or improperly accessed Target. A CPU interrupt will be generated if
PCIICR[RE] bit is set. This is a RWC (Read/WriteClear) bit: to clear it, software must write a ‘1’ at
this position.
6
Initiator Abort
(IA)
This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no Target
responded by asserting DEVSEL within the time allowed for subtractive decoding. A CPU interrupt
will be generated if the PCIICR[IAE] bit is set. This is a RWC (Read/WriteClear) bit: to clear it,
software must write a ‘1’ at this position.
7
Target Abort
(TA)
This flag bit is set if the addressed PCI Target has signalled an Abort. A CPU interrupt will be
generated if the PCIICR[TAE] bit is set. It is up to application software to query the Target’s status
register and determine the source of the error. This is a RWC (Read/WriteClear) bit: to clear it,
software must write a ‘1’ at this position.
8:31
Reserved
Unused bits. Software should write zero to this register.
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-27
PCI Controller
10.3.2.11 PCI Arbiter Register PCIARB(RW)
MBAR + 0x0D8C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ASR
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-19. PCI Arbiter Register PCIARB(RW)
Table 10-19. PCI Arbiter Register PCIARB(RW) Field Descriptions
Bits
Name
0:6
Reserved
7
PCI Arbiter Soft
Reset (ASR)
Description
Unused bits. Software should write zero to this register.
This bit puts the PCI Arbiter in a reset condition.
1 = reset the PCI Arbiter
0 = release the PCI Arbiter
Note: Resetting the PCI arbiter will disrupt any related transaction in progress and should be
reserved only for error conditions, or when it is known that no PCI or AD bus transactions
are in progress.
8:31
Reserved
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
10-28
Freescale Semiconductor
PCI Controller
10.3.2.12 Configuration Address Register PCICAR(RW)
MBAR + 0x0DF8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
E
Reserved
Bus Number
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Device Number
Function Number
dword
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-20. Configuration Address Register PCICAR (RW)
Table 10-20. Configuration Address Register PCICAR (RW) Field Descriptions
Bits
Name
Description
0
Enable
(E)
The enable flag that controls configuration space mapping. When enabled, subsequent access to
initiator window space defined as I/O in the PCIIWCR is translated into a PCI configuration access
using the Configuration Address Register information (<Cross Refs Helv 9>Section 10.6, <Cross
Refs Helv Italic 9>Application Information). When disabled, a read or write to the window is passed
through to the PCI bus as an I/O transaction using the.
1 = Enabled
0 = Disabled
1:7
Reserved
Unused bits. Software should write zero to this register.
8:15
Bus
Number
This register field is an encoded value used to select the target bus of the configuration access. For
target devices on the PCI bus connected to MPC5200B, this field should be set to 0x00.
16:20
Device
Number
This field is used to select a specific device on the target bus.
21:23
Function
Number
This field is used to select a specific function in the requested device. Single-function devices
should respond to function number 0b000.
24:29
dword
30:31
Reserved
This field is used to select the dword address offset in the configuration space of the target device.
Unused bits. Software should write zero to this register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-29
PCI Controller
10.3.3
Communication Sub-System Interface Registers
The Communication Sub-System/Multi-Channel DMA interface (also shortly referred to as SCPCI) has
separate control registers for transmit and receive operations.
10.3.3.1
Multi-Channel DMA Transmit Interface
PCI Tx is controlled by 14 ‘32-bit’ registers. These registers are located at an offset 0x3800 from MBAR.
Register addresses are relative to this offset.
10.3.3.1.1
Tx Packet Size PCITPSR(RW)
MBAR + 0x3800
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Packet_Size[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PacketSize[1:0]
Packet_Size[15:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 10-21. Tx Packet Size PCITPSR(RW)
Table 10-22. Tx Packet Size PCITPSR(RW) Field Descriptions
Bits
Name
Description
0:31
Packet_Size
User writes the number of bytes for transmit controller to send over PCI.The two low bits are
hardwired low; only 32-bit data transfers to the FIFO are allowed. Writing to this register also
completes a Restart Sequence as long as the Master Enable bit, PCITER[ME], is high and Reset
Controller bit, PCITER[RC], is low.
MPC5200B User’s Manual, Rev. 3
10-30
Freescale Semiconductor
PCI Controller
10.3.3.1.2
Tx Start Address PCITSAR(RW)
MBAR + 0x3804
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-21. Tx Start Address PCITSAR(RW)
Table 10-23. Tx Start Address PCITSAR(RW) Field Descriptions
Bits
Name
0:31
Start_Add
Description
User writes the PCI address to be presented for the first DWORD (32 bit) of a PCI packet. The
PCI Tx controller will track and calculate the necessary address for subsequent transactions
(addressing is assumed to be sequential from the start address).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-31
PCI Controller
10.3.3.1.3
Tx Transaction Control Register PCITTCR(RW)
MBAR + 0x3808
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
PCI_cmnd
Max_Retries
W
Reset
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
Max_Beats
Reserved
W
Reserved
DI
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-22. Tx Transaction Control Register PCITTCR(RW)
Table 10-24. Tx Transaction Control Register PCITTCR(RW) Field Descriptions
Bits
Name
Description
0:3
Reserved
Unused. Software should write zero to these bits.
4:7
PCI_cmd
The user writes this field with the desired PCI command to present during the address phase of
each PCI transaction. The default is Memory Write. This field is not checked for consistency and
if written to an illegal value, unpredictable results will occur. If not using the default value, the user
should write this register only once prior to any packet Restart.
8:15
Max_Retries
The user writes this field with the maximum number of retries to permit per packet. The retry
counter is reset when the packet completes normally or is terminated by a master abort, target
abort, or an abort due to exceeding the retry limit. A slow or malfunctioning Target might issue
infinite disconnects and therefore permanently tie up the PCI bus.
A finite (0x01 to 0xff) Max_Retries value will detect this condition and generate an interrupt.
Setting Max_Retries to 0x00 will not generate any interrupt.
16:20
Reserved
21:23
Max_Beats
24:26
Reserved
27
Word Transfer
(W)
28:30
Reserved
31
Disable address
Incrementing
(DI)
Unused bits. Software should write zero to these bits.
The user writes this register with the desired number of PCI data beats to attempt on each PCI
transaction. The default setting of 0 represents the maximum of eight beats per transaction. The
transmit controller will wait until sufficient bytes are in the Transmit FIFO to support the indicated
number of beats (NOTE: Each beat is four bytes). In the case that a packet is nearly complete and
less than the Max_Beats number of bytes remain to complete the packet, the Transmit Controller
will issue single-beat transactions automatically until the packet is finished.
Unused. Software should write zero to these bits.
The user writes this register to disable the two high byte enables of the PCI bus during SCPCI
initiated write transactions. The default setting is 0, enable all 4 byte enables.
Unused. Software should write zero to these bits.
The user writes this register to disable PCI address incrementing between transactions. The
default setting is 0, incrementing the address by 4 (4 byte data bus).
Note: This feature is recommended when an external FIFO (with a fixed address) must be written.
MPC5200B User’s Manual, Rev. 3
10-32
Freescale Semiconductor
PCI Controller
10.3.3.1.4
Tx Enables PCITER(RW)
MBAR + 0x380C
0
1
2
3
4
5
6
7
8
RC
RF
Rsvd
CM
BE
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
FEE
SE
RE
TAE
IAE
NE
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
ME
Reserved
W
Reset
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-23. Tx Enables PCITER(RW)
Table 10-25. Tx Enables PCITER(RW) Field Descriptions
Bits
Name
Description
0
Reset
Controller
(RC)
User writes this bit high to put Transmit Controller in a reset state. Other register bits are not
affected. This Reset is intended for recovery from an error condition or to reload the Start Address
when Continuous mode is selected. This Reset bit does not prohibit register access but it must be
negated in order to initiate a Restart sequence (i.e. writing the Packet_Size register). If it is used
to reload a Start Address then the Start_Add register must be written prior to asserting this Reset
bit.
Setting the Reset Controller bits in either PCITER or PCIRER can cause the PCI interface and the
PCI bus to hang if these bits are set while the PCI interface is currently executing a PCI transaction.
To terminate PCI data transfers across the PCI communication sub-system Tx and/or Rx
interface(s) safely, follow steps 1 through 5 in order.
1. Kill the DMA task associated with the appropriate channel (PCI Tx or PCI Rx) to stop the internal
transfer of data to or from the PCI FIFOs
2. Reprogram the Max_Beats field of the appropriate PCI interface register, PCITTCR or PCIRTCR, to 1
3. Wait for the FIFO to fill (Rx) or empty (Tx) by polling the FIFO status registers.
4. Assert Reset Controller bit for the appropriate interface.
5. Assert Reset FIFO bit for the appropriate interface.
1
Reset
FIFO
(RF)
The FIFO will be reset and flushed of any existing data when set high. The Reset Controller bit and
the Reset FIFO bit operate independently but clearly both must be low for normal operation.
2
Reserved
3
Continuous
mode
(CM)
User writes this bit high to activate Continuous mode. In Continuous mode the Start_Add value is
ignored at each packet restart and the PCI address is auto-incremented from one packet to the
next. Also, the Packets_Done status byte will become active, indicating how many packets have
been transmitted since the last Reset Controller condition. If the Continuous bit is low, software is
responsible for updating the Start_Add value at each packet Restart.
4
Bus error
Enable
(BE)
User writes this bit high to enable Bus Error indications. <Cross Refs Helv 9>Section 10.3.3.1.9,
<Cross Refs Helv Italic 9>Tx Status PCITSR(RWC) for Bus Error descriptions. Normally this bit will
be low (negated) since illegal Slave bus accesses are not destructive to register contents (although
it may indicate broken software). This bit does not affect interrupt generation.
5:6
Reserved
Unused. Software should write zero to these bits.
Unused bit. Software should write a zero to this bit.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-33
PCI Controller
Table 10-25. Tx Enables PCITER(RW) Field Descriptions (continued)
Bits
Name
Description
7
Master
Enable
(ME)
This is the Transmit Controller master enable signal. User must write it high to enable operation. It
can be toggled low to permit out-of-order register updates prior to generating a Restart sequence
(in which case transmission will begin when Master Enable is written back high), but it should not
be used as such in Continuous mode because it has the side effect of resetting the Packets_Done
status counter.
8:9
Reserved
Unused. Software should write zero to these bits.
10
FIFO Error
Enable
(FEE)
User writes this bit high to enable CPU Interrupt generation in the case of FIFO error termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
11
System error
Enable
(SE)
User writes this bit high to enable CPU Interrupt generation in the case of system error termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case someone should be polling the status bits to
prevent a possible lock-up condition.
12
Retry abort
Enable
(RE)
User writes this bit high to enable CPU Interrupt generation in the case of retry abort termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
13
Target Abort
Enable
(TAE)
User writes this bit high to enable CPU Interrupt generation in the case of target abort termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
14
Initiator Abort
Enable
(IAE)
User writes this bit high to enable CPU Interrupt generation in the case of initiator abort termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
15
Normal
termination
Enable (NE)
User writes this bit high to enable CPU Interrupt generation at the conclusion of a normally
terminated packet transmission. This may or may not be desirable depending on the nature of
program control by Multi-Channel DMA or the processor core.
16:31
Reserved
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
10-34
Freescale Semiconductor
PCI Controller
10.3.3.1.5
Tx Next Address PCITNAR(R)
MBAR + 0x3810
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Next_Address
W
Reset
0
0
0
0
0
0
0
16
17
18
19
20
21
22
R
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-24. Tx Next Address PCITNAR(R)
Table 10-26. Tx Next Address PCITNAR(R) Field Descriptions
Bits
Name
0:31
Next_Address
10.3.3.1.6
Description
This status register contains the next (unwritten) PCI address and is updated at the successful
completion of each PCI data beat. It represents a byte address and is updated with the
user-written Start_Add value whenever the Start_Add is reloaded. It is intended to be accurate
even in the case of abnormal terminations on the PCI bus.
Tx Last Word PCITLWR(R)
MBAR + 0x3814
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Last_Word
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Last_Word
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-25. Tx Last Word PCITLWR(R)
Table 10-27. Tx Last Word PCITLWR(R) Field Descriptions
Bits
Name
Description
0:31
Last_Word
This status register indicates the last 32-bit data fetched from the FIFO and is designed for the
case in which an abnormal PCI termination has corrupted the integrity of the FIFO data (for that
word).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-35
PCI Controller
10.3.3.1.7
Tx Bytes Done Counts PCITDCR(R)
MBAR + 0x3818
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Bytes_Done
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Bytes_Done
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-26. Tx Bytes Done Counts PCITDCR(R)
Table 10-28. Tx Bytes Done Counts PCITDCR(R) Field Descriptions
Bits
Name
Description
0:31
Bytes_Done
This status register indicates the number of bytes transmitted since the start of a packet. It is
updated at the end of each successful PCI data beat. For normally terminated packets the
Bytes_Done value and the Packet_Size values will be equal. If Continuous Mode is active the
Bytes_Done value will read zero at the end of a successful packet and the Packets_Done field will
be incremented.
10.3.3.1.8
Tx Packets Done Counts PCITPDCR(R)
MBAR + 0x3820
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Packets_Done
W
Reset
0
0
0
0
0
0
0
16
17
18
19
20
21
22
R
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Packets_Done
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-27. Tx Packets Done Counts PCITPDCR(R)
Table 10-29. Tx Packets Done Counts PCITPDCR(R) Field Descriptions
Bits
Name
Description
0:31
Packets_Done
This status register indicates the number of packets transmitted and is active only if continuous
mode is in effect. The counter is reset if the following occurs:
• Reset Controller bit, PCITER[RC], is asserted (normal way to restart continuous mode)
• Master Enable bit, PCITER[ME], becomes negated
Master enable can reset Packets_Done status without disturbing continuous mode addressing. At
any point in time, the total number of Bytes transmitted can be calculated as:
(Packets_Done x Packet_Size) + Bytes_Done
assuming Packet_Size is the same for all restart sequences
MPC5200B User’s Manual, Rev. 3
10-36
Freescale Semiconductor
PCI Controller
10.3.3.1.9
Tx Status PCITSR(RWC)
MBAR + 0x381C
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
NT
BE3
BE2
BE1
FE
SE
RE
TA
IA
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-28. Tx Status PCITSR(RWC)
Table 10-30. Tx Status PCITSR(RWC) Field Descriptions
Bits
Name
0:6
Reserved
7
Normal
Termination
(NT)
This flag is set when any packet terminates normally. It is NOT set for abnormally terminated packets.
Note: Flag does not require clearing, but does not clear until 1 is written, in which case 0 is read back
(i.e., negated). The following flag bits operate similarly.
8
Bus Error
type 3
(BE3)
This flag is set whenever a Slave bus transaction attempts to write to a Read-Only register. This flag
bit is set regardless of the Bus error Enable bit (BE). If software is polling this Byte and wishes to
disregard this error it must mask this bit out.
No register bit corruption occurs for this (or any other) bus error case.
9
Bus Error
type 2
(BE2)
This flag is set whenever a Slave bus transaction attempts to write to a Reserved register (an entire
32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus error Enable
bit (BE). If software is polling this Byte and wishes to disregard this error it must mask this bit out.
10
Bus Error
type 1
(BE1)
This flag is set whenever a Slave bus transaction attempts to read a Reserved register (an entire 32-bit
register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus error Enable bit (BE).
If software is polling this Byte and wishes to disregard this error it must mask this bit out.
11
FIFO Error
(FE)
This flag is set whenever the Transmit FIFO asserts its FIFO Error output. A CPU interrupt will be
generated if the FIFO Error Enable (FEE) bit is set. The source of the error must be determined by
reading the FIFO Error status register. Also, the error condition must be cleared at the FIFO prior to
clearing this Sticky bit or this flag will continue to assert.
12
13
Description
Unused. Software should write zero to these bits.
System Error This flag is set in response to the Transmit Controller entering an illegal state. A CPU interrupt will be
(SE)
generated if the System error Enable (SE) bit is set. In normal operation this should never occur. The
only recovery is to assert the Reset Controller bit, PCITER[RC], and clear this flag.
Retry Error
(RE)
This flag is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction has
performed retries in excess of the setting. A CPU interrupt will be generated if the Retry error Enable
(RE) bit is set. The retry counter is reset at the beginning of each transaction (i.e. it is not cumulative
throughout a packet) and would generally indicate a broken or improperly accessed Target.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-37
PCI Controller
Table 10-30. Tx Status PCITSR(RWC) Field Descriptions (continued)
Bits
Name
Description
14
Target Abort
(TA)
This flag bit is set if the PCI controller has issued a Target Abort (which means the addressed PCI
Target has signalled an Abort). A CPU interrupt will be generated if the Target Abort Enable (TAE) bit
is set. It is up to application software to query the Target’s status register and determine the source of
the error. The coherency of the Transmit FIFO data and the Transmit Controller’s status registers
(Next_Address, Bytes_Done, etc.) should remain valid.
15
Initiator Abort This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no Target
(IA)
responded but further status information can be read from the PCI Configuration interface. A CPU
interrupt will be generated if the Initiator Abort error Enable (IAE) bit is set. The coherency of the
Transmit FIFO data and the Transmit Controller’s status registers (Next_Address, Bytes_Done, etc.)
should remain valid.
16:31
Reserved
Unused. Software should write zero to these bits.
10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW)
MBAR + 0x3840
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
27
28
29
30
31
R
FIFO_Data_Word
W
Reset
Uninitialized random 16 bit value
16
17
18
19
20
21
22
23
24
25
26
R
FIFO_Data_Word
W
Reset
Uninitialized random 16 bit value
Figure 10-29. Tx FIFO Data Register PCITFDR(RW)
Table 10-31. Tx FIFO Data Register PCITFDR(RW) Field Descriptions
Bits
Name
Description
0:31
FIFO_Data_Word
This is the data port to the FIFO. Reading from this location will “pop” data from the FIFO,
writing data will “push” data into the FIFO. During normal operation the Multi-Channel DMA
controller will be pushing data here. The PCI controller will pop data for transmission from a
dedicated peripheral port, so the user program should not be reading here. At reset any
uninitialized random 32 bit value is read at this address. A FIFO reset must be always
performed before first accessing the FIFO.
Note: Only full 32-bit accesses are allowed. If all Byte enables are not asserted when
accessing this location, FIFO data will be corrupted.
MPC5200B User’s Manual, Rev. 3
10-38
Freescale Semiconductor
PCI Controller
10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC)
MBAR + 0x3844
0
1
2
3
4
5
6
7
8
R
9
10
11
12
RXW
UF
OF
FR
rwc
rwc
rwc
13
14
15
Full Alarm Empty
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-30. Tx FIFO Status Register PCITFSR(R/RWC)
Table 10-32. Tx FIFO Status Register PCITFSR(R/RWC) Field Descriptions
Bits
Name
Description
0:8
Reserved
9
Receive Wait
Condition
(RXW)
This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not enough room
in the FIFO to accept the data without causing overflow. This bit will cause the error outputs (fifoError,
ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in the FIFO Control register is set.
Resetting the FIFO will clear this condition and the flag bit is cleared by writing a one to its bit
position.
10
UnderFlow
(UF)
This flag bit indicates that the read pointer has surpassed the write pointer. In other words the FIFO
has been read beyond Empty. Resetting the FIFO will clear this condition and the flag bit is cleared
by writing a one to its bit position.
11
OverFlow
(OF)
This flag bit indicates that the write pointer has surpassed the read pointer. In other words the FIFO
has been written beyond Full. Resetting the FIFO will clear this condition and the flag bit is cleared
by writing a one to its bit position.
12
Frame Ready
(FR)
13
Full
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the state of
the FIFO.
14
Alarm
When the FIFO pointer is at or below the Alarm “watermark”, as written by the user according to the
Alarm and Control registers settings, this bit is set, automatically signalling to the DMA engine the
need to re-fill the FIFO. By writing a ‘1’ to this bit software can enforce a re-evaluation of the ‘alarm’
condition.
15
Empty
The FIFO is empty. This is not a sticky bit or error condition.
16:31
Reserved
Unused. Software should write zero to these bits.
The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for Data Framing applications, so this bit should be ignored.
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-39
PCI Controller
10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW)
MBAR + 0x3848
5
6
7
9
10
11
12
13
14
15
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
GR
W
Reset
8
OF_MASK
4
UF_MASK
3
RXW_MASK
2
FAE_MASK
1
IP_MASK
0
Reserved
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-31. Tx FIFO Control Register PCITFCR(RW)
Table 10-33. Tx FIFO Control Register PCITFCR(RW) Field Descriptions
Bits
Name
Description
0:4
Reserved
Unused. Software shall write zero to these bits. (R/W)
5:7
Granularity
(GR)
Granularity bits control high “watermark” point at which FIFO negates Alarm condition (i.e., request
for data). It represents the number of free Bytes, which is given by the granularity value multiplied
by 4.
Note: A granularity setting of zero should be avoided because it means the Alarm bit (and the
Requestor signal) will not negate until the FIFO is completely full. The Multi-Channel DMA
module may perform up to 2 additional data writes after the negation of a Requestor due to
its internal pipelining
Note: This field must be set to a value of 4 or higher. When the FIFO granularity is 0 - 3, read data
can be corrupted with no error indication when the PCI controller simultaneously writes to the
same location that the BestComm is reading from. The workaround is to use a FIFO
granularity of 4 or greater.
8
IP_MASK
Illegal Pointer Mask
When this bit is set, the FIFO controller masks the Status register’s IP bit from generating an error.
9
FAE_MASK
When this bit is set, the FIFO controller masks the Status Register’s FAE bit from generating an
error.
10
RXW_MASK
When this bit is set, the FIFO controller masks the Status Register’s RXW bit from generating an
error. (To help with backward compatibility, this bit is asserted at reset.)
11
UF_MASK
When this bit is set, the FIFO controller masks the Status Register’s UF bit from generating an error.
12
OF_MASK
When this bit is set, the FIFO controller masks the Status Register’s OF bit from generating an error.
13:15
Reserved
Unused. Software should write zero to these bits.
16:31
Reserved
Unused. Software should write zero to these bits. (R/W)
MPC5200B User’s Manual, Rev. 3
10-40
Freescale Semiconductor
PCI Controller
10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW)
MBAR + 0x384C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Alarm
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
0
0
0
Alarm
0
0
0
0
0
0
Figure 10-32. Tx FIFO Alarm Register PCITFAR(RW)
Table 10-34. Tx FIFO Alarm Register PCITFAR(RW) Field Descriptions
Bits
Name
0:19
Reserved
20:31
Alarm
Description
Unused. Software should write zero to these bits.
User writes these bits to set low level “watermark”, which is the point where FIFO asserts request
for Multi-Channel DMA controller data filling. Value is in Bytes. For example, with Alarm = 32, alarm
condition occurs when FIFO contains less than 32Bytes. Once asserted, alarm does not negate
until high level mark is reached, as specified by FIFO control register granularity (GR) bits.
Note: An Alarm setting less than the value of Max_Beats x 4 should be avoided. The transmit
operation waits for the data to be stored in the FIFO before transmission onto the PCI bus.
(e.g. A Max_setting of 0 represents eight beats (32-bits each) per transaction. The value of
Alarm is in bytes. Ex: the value programmed to the Alarm register should be at least 0x20 (32
bytes) for the Multi-Channel DMA to continue to write enough data to complete at least one
PCI burst.)
Note: TX PCI FIFO is 512 bytes deep.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-41
PCI Controller
10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW)
MBAR + 0x3850
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
9
Reserved
W
Reset
8
0
0
0
ReadPtr
0
0
0
0
0
0
0
0
Figure 10-33. Tx FIFO Read Pointer Register PCITFRPR(RW)
Table 10-35. Tx FIFO Read Pointer Register PCITFRPR(RW) Field Descriptions
Bits
Name
0:19
Reserved
20:31
ReadPtr
Description
Unused. Software should write zero to these bits.
This value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. The value represents the Read address presented to the
FIFO RAM.
10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW)
MBAR + 0x3854
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
WritePtr
0
0
0
0
0
0
0
0
Figure 10-34. Tx FIFO Write Pointer Register PCITFWPR(RW)
Table 10-36. Tx FIFO Write Pointer Register PCITFWPR(RW) Field Descriptions
Bits
Name
0:19
Reserved
20:31
WritePtr
Description
Unused bits. Software should write zero to these bits.
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. Value represents the Write address presented to the FIFO
RAM.
This marks the end of the PCI Multi-Channel DMA Transmit Interface description.
MPC5200B User’s Manual, Rev. 3
10-42
Freescale Semiconductor
PCI Controller
10.3.3.2
Multi-Channel DMA Receive Interface
PCI Rx is controlled by 13 32-bit registers. These registers are located at an offset from MBAR. Register
addresses are relative to this offset.
10.3.3.2.1
Rx Packet Size PCIRPSR(RW)
MBAR + 0x3880
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Packet_Size[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Packet_Siz[1:0
]
Packet_Size[15:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-35. Rx Packet Size PCIRPSR(RW)
Table 10-37. Rx Packet Size PCIRPSR(RW) Field Descriptions
Bits
Name
Description
0:31
Packet_Size
The user writes this register with the number of bytes for Receive Controller to fetch over PCI. The
two low bits are hardwired low; only 32-bit data transfers to the FIFO are allowed.
Writing to this register also completes a Restart Sequence as long as Master Enable bit,
PCIRER[ME], is high and Reset Controller bit, PCIRER[RC], is low.
10.3.3.2.2
Rx Start Address PCIRSAR(RW)
MBAR + 0x3884
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Start_Add
W
Reset
8
Start_Add
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 10-36. Rx Start Address PCIRSAR (RW)
Table 10-38. Rx Start Address PCIRSAR (RW) Field Descriptions
Bits
Name
Description
0:31
Start_Add
The user writes this register with the desired Starting Address for the current packet. This is the
address which will be first presented on the external PCI bus and then auto-incremented as
necessary. This register will not increment as the PCI packet proceeds.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-43
PCI Controller
10.3.3.2.3
Rx Transaction Control Register PCIRTCR(RW)
MBAR + 0x3888
0
R
3
4
5
6
7
8
9
10
PCI_cmnd
11
12
13
14
15
Max_Retries
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FB
R
0
0
R
Reserved
W
Reset
2
Reserved
W
Reset
1
0
0
0
Max_Beats
0
0
Reserved
0
0
0
W
0
0
Reserved
0
0
DI
0
0
Figure 10-37. Rx Transaction Control Register PCIRTCR(RW)
Table 10-39. Rx Transaction Control Register PCIRTCR(RW) Field Descriptions
Bits
Name
Description
0:3
Reserved
Unused. Software should write zero to these bits.
4:7
PCI_cmd
The user writes this field with the desired PCI command to present during the address phase of
each PCI transaction. The default is Memory Read Multiple. This field is not checked for
consistency and if written to an illegal value, unpredictable results will occur. If not using the default
value, the user should write this register only once prior to any packet Restart.
8:15
Max_Retries
The user writes this field with the maximum number of retries to permit “per packet”. The retry
counter is reset when the packet completes normally or is terminated by a master abort, target
abort, or an abort due to exceeding the retry limit. A slow or malfunctioning Target might issue
infinite disconnects and therefore permanently tie up the PCI bus.
A finite (0x01 to 0xff) Max_Retries value will detect this condition and generate an interrupt. Setting
Max_Retries to 0x00 will not generate any interrupt.
16:18
Reserved
Unused. Software should write zero to these bits.
19
Full Burst
(FB)
This is the Full Burst bit. If Full Burst is set, no check of the Receive Fifo emptiness is done and the
PCI transaction is immediately started when Packet_Size register is written (and SCPCI RX gains
the PCI bus).
The PCI transaction will continue with multiple data beats UNTIL THE FULL PACKET IS
TRANSFERRED (up to 4G bytes). The Full Burst operation avoids latency time-out and will not
relinquish the bus until all Packet Bytes are received.
Note: All FIFO checks (by scpci Rx) are disabled in this mode. It is up to the Multi-Channel DMA
to keep the Rx FIFO from being overrun by the continuous incoming PCI burst data.
Note: It is recommended to use the Full Burst mode only for transactions where more than 32
Bytes should be received.
Note: Max_Beats must be set to 0.
20
Reserved
Unused. Software should write zero to this bit.
21:23
Max_Beats
24:26
Reserved
The user writes this register with the desired number of PCI data beats to attempt on each PCI
transaction. The default setting of 0 represents the maximum of eight beats per transaction. The
receive controller will wait until sufficient space is in the Receive FIFO to support the indicated
number of beats (Note: Each beat is four bytes). In the case that a packet is nearly complete and
less than the Max_Beats number of bytes remain to complete the packet, the Receive Controller
will issue single-beat transactions automatically until the packet is finished.
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
10-44
Freescale Semiconductor
PCI Controller
Table 10-39. Rx Transaction Control Register PCIRTCR(RW) Field Descriptions (continued)
Bits
Name
27
Word Transfer
(W)
28:30
Reserved
31
Description
The user writes this register to disable the two high byte enables of the PCI bus during initiated
read transactions. The default setting is 0, enable all 4 byte enables.
Unused. Software should write zero to these bits.
Disable address The user writes this register to disable PCI address incrementing between transactions. The
Incrementing
default setting is 0, increment address by 4 (4 byte data bus).
(DI)
Note: This feature is recommended when reading from an external FIFO (having a fixed address).
10.3.3.2.4
Rx Enables PCIRER(RW)
MBAR + 0x388C
0
1
2
3
4
5
6
7
8
RC
RF
FE
CM
BE
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
FEE
SE
RE
TAE
IAE
NE
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
ME
Reserved
W
Reset
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-38. Rx Enables PCIRER (RW)
Table 10-40. Rx Enables PCIRER (RW) Field Descriptions
Bits
Name
Description
0
Reset
Controller
(RC)
User writes this bit high to put Receive Controller in a reset state. Note that other register bits are
not affected. This Reset is intended for recovery from an error condition or to reload the Start
Address when Continuous mode is selected. This Reset bit does not prohibit register access but it
must be negated in order to initiate a Restart sequence (i.e. writing the Packet_Size register). If it
is used to reload a Start Address then the Start_Add register must be written prior to asserting this
Reset bit.
1
Reset
FIFO
(RF)
The FIFO will be reset and flushed of any existing data when set high. The Reset Controller bit and
the Reset FIFO bit operate independently, but clearly both must be low for normal operation.
2
FE
Flush enable. This is an important bit which causes a flush signal to be generated to the Receive
FIFO Controller when the end of the current packet occurs. This Flush is necessary to insure that
the Multi-Channel DMA will get all data left in the Receive FIFO. FE is active high.
3
Continuous
mode
(CM)
User writes this bit high to activate Continuous mode. In Continuous mode the Start_Add value is
ignored at each packet restart and the PCI address is auto-incremented from one packet to the
next. Also, the Packets_Done status byte will become active, indicating how many packets have
been received since the last Reset Controller condition. If the Continuous bit is low, software is
responsible for updating the Start_Add value at each packet Restart.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-45
PCI Controller
Table 10-40. Rx Enables PCIRER (RW) Field Descriptions (continued)
Bits
Name
Description
4
Bus error
Enable
(BE)
User writes this bit high to enable Bus Error indications. Section 10.3.3.2.9, “Rx Status
PCIRSR(R/sw1)” for Bus Error descriptions. Normally this bit will be 0 since illegal Slave bus
accesses are not destructive to register contents, although it may indicate broken software. Note
that this bit does not affect interrupt generation.
5:6
Reserved
Unused. Software should write zero to these bits.
7
Master
Enable
(ME)
8:9
Reserved
Unused. Software should write zero to these bits.
10
FIFO Error
Enable
(FEE)
User writes this bit high to enable CPU Interrupt generation in the case of FIFO error termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
11
System error
Enable
(SE)
User writes this bit high to enable CPU Interrupt generation in the case of system error termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should be polling the status bits to prevent
a possible lock-up condition.
12
Retry abort
Enable
(RE)
User writes this bit high to enable CPU Interrupt generation in the case of retry abort termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case, software should poll the status bits to prevent a
possible lock-up condition.
13
Target Abort
Enable
(TAE)
User writes this bit high to enable CPU Interrupt generation in the case of target abort termination
of a packet transmission. It may be desirable to mask CPU interrupts in the case that Multi-Channel
DMA is controlling operation, but in such a case software should poll the status bits to prevent a
possible lock-up condition.
14
Initiator Abort
error
Enable
(IAE)
User writes this bit high to enable CPU Interrupt generation in the case of initiator abort error
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case that
Multi-Channel DMA is controlling operation, but in such a case software should poll the status bits
to prevent a possible lock-up condition.
15
Normal
termination
Enable (NE)
User writes this bit high to enable CPU Interrupt generation at the conclusion of a normally
terminated packet transmission. This may or may not be desirable depending on the nature of
program control by Multi-Channel DMA or the processor core.
16:31
Reserved
This is the Receive Controller master enable signal. User must write it high to enable operation. It
can be toggled low to permit out-of-order register updates prior to generating a Restart sequence
(in which case transmission will begin when Master Enable is written back high), but it should not
be used as such in Continuous mode because it has the side effect of resetting the Packets_Done
status counter.
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
10-46
Freescale Semiconductor
PCI Controller
10.3.3.2.5
Rx Next Address PCIRNAR(R)
MBAR + 0x3890
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-39. Rx Next Address PCIRNAR(R)
Table 10-41. Rx Next Address PCIRNAR(R) Field Descriptions
Bits
Name
Description
0:31
Next_Address
This status register contains the next (unread) PCI address and is updated at the successful
completion of each PCI data beat. It represents a Byte address and is updated with a user-written
Start_Add value when Start_Add is reloaded. This register is intended to be accurate even if an
abnormal PCI bus termination occurs.
10.3.3.2.6
Rx Last Word PCIRLWR(R)
MBAR + 0x3894
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Last_Word
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Last_Word
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-40. Rx Last Word PCIRLWR(R)
Table 10-42. Rx Last Word PCIRLWR(R) Field Descriptions
Bits
Name
Description
0:31
Last_Word
This status register indicates the last 32-bit data fetched from the FIFO and is designed for the
case in which an abnormal PCI termination has corrupted the integrity of the FIFO data (for that
word).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-47
PCI Controller
10.3.3.2.7
Rx Bytes Done Counts PCIRDCR(R)
MBAR + 0x3898
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Bytes_Done
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Bytes_Done
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-41. Rx Bytes Done Counts PCIRDCR(R)
Table 10-43. Rx Bytes Done Counts PCIRDCR(R) Field Descriptions
Bits
Name
Description
0:31
Bytes_Done
This status register indicates the number of Bytes received since the start of a packet. It is
updated at the end of each successful PCI data beat. For normally terminated packets, the
Bytes_Done value and the Packet_Size values are equal. If continuous mode is active, the
Bytes_Done value reads 0 at the end of a successful packet and the Packets_Done field
is incremented.
MPC5200B User’s Manual, Rev. 3
10-48
Freescale Semiconductor
PCI Controller
10.3.3.2.8
Rx Packets Done Counts PCIRPDCR(R)
MBAR + 0x38A0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Packets_Done
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Packets_Done
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-42. Rx Packets Done Counts PCIRPDCR(R)
Table 10-44. Rx Packets Done Counts PCIRPDCR(R) Field Descriptions
Bits
Name
Description
0:31
Packets_Done
This status register indicates the number of packets received. It is active only if continuous mode
is in effect. If the following occurs, the counter is reset:
• Reset Controller bit, PCIRER[RC], is asserted (normal way to restart continuous mode)
• Master Enable bit, PCIRER[ME], is negated
In this way, master enable can be used to reset Packets_Done status without disturbing
continuous mode addressing. At any point in time the total number of Bytes received can be
calculated as:
(Packets_Done x Packet_Size) + Bytes_Done
This assumes Packet_Size is the same for all restart sequences.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-49
PCI Controller
10.3.3.2.9
Rx Status PCIRSR(R/sw1)
MBAR + 0x389C
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
NT
BE3
BE2
BE1
FE
SE
RE
TA
IA
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
rwc
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-43. Rx Status PCIRSR (R/sw1)
Table 10-45. Rx Status PCIRSR (R/sw1) Field Descriptions
Bits
Name
Description
0:6
Reserved
7
Normal
Termination
(NT)
This flag is set when any packet terminates normally. It is not set in the case of an abnormally
terminated packet. It does not require clearing but will not clear until it is written to a one (in which
case it will now read back as zero, i.e. negated).
>ALL THE FOLLOWING FLAG BITS OPERATE SIMILARLY<
8
Bus Error
type 3
(BE3)
This flag is set whenever a Slave bus transaction attempts to write to a Read-Only register. This
flag bit is set regardless of the Bus error Enable bit (BE). If software is polling this Byte and wishes
to disregard this error it must mask this bit out. No corruption of the register bits occur for this (or
any other) Bus Error case.
9
Bus Error
type 2
(BE2)
This flag is set whenever a Slave bus transaction attempts to write to a Reserved register (an entire
32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus error Enable
bit (BE). If software is polling this Byte and wishes to disregard this error it must mask this bit out.
10
Bus Error
type 1
(BE1)
This flag is set whenever a Slave bus transaction attempts to read a Reserved register (an entire
32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus error Enable
bit (BE). If software is polling this Byte and wishes to disregard this error it must mask this bit out.
11
FIFO Error
(FE)
This flag is set whenever the Receive FIFO asserts its FIFO Error output. A CPU interrupt will be
generated if the FIFO Error Enable (FEE) bit is set. The source of the error must be determined by
reading the FIFO Error status register. Also, the error condition must be cleared at the FIFO prior
to clearing this Sticky bit or this flag will continue to assert.
12
System Error
(SE)
This flag is set in response to the Transmit Controller entering an illegal state. A CPU interrupt will
be generated if the System error Enable (SE) bit is set. In normal operation this should never occur.
The only recovery is to assert the Reset Controller bit, PCIRER[RC], and clear this flag.
13
Retry Error
(RE)
This flag is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction has
performed retries in excess of the setting. A CPU interrupt will be generated if the Retry error
Enable (RE) bit is set. The retry counter is reset at the beginning of each transaction (i.e. it is not
cumulative throughout a packet) and would generally indicate a broken or improperly accessed
Target.
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
10-50
Freescale Semiconductor
PCI Controller
Table 10-45. Rx Status PCIRSR (R/sw1) Field Descriptions (continued)
Bits
Name
Description
14
Target Abort
(TA)
This flag bit is set if the PCI controller has issued a Target Abort (which means the addressed PCI
Target has signalled an Abort). A CPU interrupt will be generated if the Target Abort Enable (TAE)
bit is set. It is up to application software to query the Target’s status register and determine the
source of the error. The coherency of the Receive FIFO data and the Receive Controller’s status
registers (Next_Address, Bytes_Done, etc.) should remain valid.
15
Initiator Abort
(IA)
This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no Target
responded but further status information can be read from the PCI Configuration interface. A CPU
interrupt will be generated if the Initiator Abort error Enable (IAE) bit is set. The coherency of the
Receive FIFO data and the Receive Controller’s status registers (Next_Address, Bytes_Done, etc.)
should remain valid.
16:31
Reserved
Unused. Software should write zero to these bits.
10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW)
MBAR + 0x38C0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
27
28
29
30
31
R
FIFO_Data_Word
W
Reset
Uninitailized random 16 bit value
16
17
18
19
20
21
22
23
24
25
26
R
FIFO_Data_Word
W
Reset
Uninitalized random 16 bit value
Figure 10-44. Rx FIFO Data Register PCIRFDR(RW)
Table 10-46. Rx FIFO Data Register PCIRFDR(RW) Field Descriptions
Bits
Name
Description
0:31
FIFO_Data_Word
FIFO data port—Reading from this location “pops” data from the FIFO; writing “pushes” data
into the FIFO. During normal operation the Multi-Channel DMA controller pops data here. The
receive controller pushes data. Therefore, user programs should not write here. At power on
reset an uninitialized random value is read at this register. A FIFO reset must be always
performed before first accessing the FIFO.
Note: Only full 32-bit accesses are allowed. If all Byte enables are not asserted when
accessing this location, FIFO data will be corrupted.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-51
PCI Controller
10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1)
MBAR + 0x38C4
0
1
2
3
4
5
6
7
8
R
9
10
11
12
13
RXW
UF
OF
FR
Full
rwc
rwc
rwc
14
15
Alarm Empty
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-45. Rx FIFO Status Register PCIRFSR(R/sw1)
Table 10-47. Rx FIFO Status Register PCIRFSR(R/sw1) Field Descriptions
Bits
Name
Description
0:8
Reserved
9
Receive Wait
Condition
(RXW)
This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not
enough room in the FIFO to accept the data without causing overflow. This bit will cause the
error outputs (fifoError, ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in
the FIFO Control register is set. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to its bit position.
10
UnderFlow
(UF)
This flag bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
11
OverFlow
(OF)
This flag bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
12
Frame Ready
(FR)
13
Full
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the
state of the FIFO.
14
Alarm
When the FIFO pointer is at or above the Alarm “watermark”, as written by the user
according to the Alarm and Control registers settings, the Alarm bit is asserted, thus
automatically signalling to the DMA engine that the FIFO needs to be ‘emptied’. By writing
a ‘1’ to this location software can enforce re-evaluation of the alarm condition.
15
Empty
The FIFO is empty. This is not a sticky bit or error condition.
16:31
Reserved
Unused byte. Software should write zero to these bits.
The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for Data Framing applications, so this bit should be ignored.
Unused. Software should write zero to these bits.
MPC5200B User’s Manual, Rev. 3
10-52
Freescale Semiconductor
PCI Controller
10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW)
MBAR + 0x38C8
5
6
7
9
10
11
12
13
14
15
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
GR
R
Reset
8
OF_MASK
4
UF_MASK
3
RXW_MASK
2
FAE_MASK
1
IP_MASK
0
Reserved
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 10-46. Rx FIFO Control Register PCIRFCR(RW)
Table 10-48. Rx FIFO Control Register PCIRFCR(RW) Field Descriptions
Bits
Name
Description
0:4
Reserved
Unused. Software shall write zero to these bits. (R/W)
5:7
Granularity
(GR)
Granularity bits control high “watermark” point at which FIFO negates Alarm condition (i.e., request
for data). It represents the number of free Bytes times 4.
Note: A granularity setting of zero should be avoided because it means the Alarm bit (and the
Requestor signal) will not negate until the FIFO is completely full. The Multi-Channel DMA
module may perform up to 2 additional data writes after the negation of a Requestor due to
its internal pipelining.
Note: This field must be set to a value of 4 or higher. When the FIFO granularity is 0 - 3, read data
can be corrupted with no error indication when the PCI controller simultaneously writes to the
same location that the BestComm is reading from. The workaround is to use a FIFO
granularity of 4 or greater.
8
IP_MASK
Illegal Pointer Mask
When this bit is set, the FIFO controller masks the Status register’s IP bit from generating an error.
9
FAE_MASK
When this bit is set, the FIFO controller masks the Status Register’s FAE bit from generating an
error.
10
RXW_MASK
When this bit is set, the FIFO controller masks the Status Register’s RXW bit from generating an
error. (To help with backward compatibility, this bit is asserted at reset.)
11
UF_MASK
When this bit is set, the FIFO controller masks the Status Register’s UF bit from generating an error.
12
OF_MASK
When this bit is set, the FIFO controller masks the Status Register’s OF bit from generating an error.
13:15
Reserved
Unused. Software should write zero to these bits.
16:31
Reserved
Unused. Software shall write zero to these bits. (R/W)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-53
PCI Controller
10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW)
MBAR + 0x38CC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Alarm
Reserved
Alarm
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-47. Rx FIFO Alarm Register PCIRFAR(RW)
Table 10-49. Rx FIFO Alarm Register PCIRFAR(RW) Field Descriptions
Bits
Name
0:19
Reserved
20:31
Alarm
[11:0]
Description
Unused. Software should write zero to these bits.
User writes these bits to set the low level watermark, which is the point at which the FIFO asserts
its request for data emptying to the Multi-Channel DMA controller. This value is in bytes. For
example, with Alarm = 32, the alarm condition will occur when the FIFO has 32 or less free bytes in
it. The alarm, once asserted, will not negate until the high level mark is reached, as specified by the
Granularity bits in the Rx FIFO Control Register.
Note: The PCI RX FIFO is 512 bytes deep.
MPC5200B User’s Manual, Rev. 3
10-54
Freescale Semiconductor
PCI Controller
10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW)
MBAR + 0x38D0
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
9
Reserved
W
Reset
8
0
0
0
ReadPtr
0
0
0
0
0
0
0
0
Figure 10-48. Rx FIFO Read Pointer Register PCIRFRPR(RW)
Table 10-50. Rx FIFO Read Pointer Register PCIRFRPR(RW) Field Descriptions
Bits
Name
0:19
Reserved
20:31
ReadPtr
Description
Unused. Software should write zero to these bits.
This value is maintained by the FIFO hardware and is not normally written. It can be adjusted in
special cases but will disrupt the integrity of the data flow. This value represents the Read address
being presented to the FIFO RAM.
10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR(RW)
MBAR + 0x38D4
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
RESET
8
Reserved
W
Reset
7
0
0
0
WritePtr
0
0
0
0
0
0
0
0
Figure 10-49. Rx FIFO Read Pointer Register PCIRFRPR(RW)
Table 10-51. Rx FIFO Read Pointer Register PCIRFRPR(RW) Field Descriptions
Bits
Name
12:19
Reserved
20:31
WritePtr
Description
Unused. Software should write zero to these bits.
This value is maintained by the FIFO hardware and is not normally written. It can be adjusted in
special cases but will of course disrupt the integrity of the data flow. This value represents the Write
address being presented to the FIFO RAM.
This marks the end of the PCI Multi-Channel DMA Receive Interface description.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-55
PCI Controller
10.4
Functional Description
The MPC5200B PCI module provides both master and target PCI bus interfaces as shown in Figure 10-1.
The internal PCI master, or initiator, interface is accessible by any XL bus master such as the processor
core and also provides a DMA interface (for BestComm) through the Communication Sub-System, which
can be accessed by the Multi-Channel DMA engine. The internal PCI target interface provides external
PCI masters access into two memory windows of MPC5200B address space. PCI arbitration is handled
external to this module, by the MPC5200B internal PCI arbiter.
NOTE
Only the internal PCI arbiter of the MPC5200B can be used as PCI arbiter
for the PCI bus. An external PCI arbiter cannot be used.
The registers, described in Section 10.3, “Registers,” control and provide information about these multiple
interfaces. An additional Configuration interface allows internal access through the Slave bus(also referred
to as IP bus) to the PCI Type 0 Configuration registers, which are accessible to both MPC5200B and
external masters through the PCI bus.
The following sections describe the operation of the PCI module.
10.4.1
PCI Bus Protocol
This section will provide a simple overview of the PCI bus protocol, including some details of MPC5200B
implementation. For details regarding PCI bus operation, refer to the PCI Local Bus Specification,
Revision 2.2.
10.4.1.1
PCI Bus Background
The PCI interface is synchronous and is best used for bursting data in large chunks. Its maximum
theoretical bandwidth approaches 266 Megabytes per second for the 32-bit implementation running at
66MHz. A system will contain one device that is responsible for configuring all other devices on the bus
upon reset. Each device has 256 bytes of configuration space that define individual requirements to the
system controller. These registers are read and written through a “configuration access” command. A PCI
transfer is started by the master and is directed toward a specific target. A provision is made for
broadcasting to several targets through the “special command.” Data is transferred through the use of
memory and IO read and write commands.
.
Table 10-52. PCI Command Encoding
C/BE[3:0]
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
Reserved
0101
Reserved
MPC5200B User’s Manual, Rev. 3
10-56
Freescale Semiconductor
PCI Controller
Table 10-52. PCI Command Encoding (continued)
10.4.1.2
C/BE[3:0]
Command Type
0110
Memory Read
0111
Memory Write
1000
Reserved
1001
Reserved
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
Dual Address Cycle
1110
Memory Read Line
1111
Memory Write and Invalidate
Basic Transfer Control
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one
or more data phases. Fundamentally, all PCI data transfers are controlled by three signals FRAME, IRDY,
and TRDY. An initiator asserts FRAME to indicate the beginning of a PCI bus transaction and negates
FRAME to indicate the end of a PCI bus transaction. An initiator negates IRDY to force wait cycles. A
target negates TRDY to force wait cycles.
The PCI bus is considered idle when both FRAME and IRDY are negated. The first clock cycle in which
FRAME is asserted indicates the beginning of the address phase. The address and bus command code are
transferred in that first cycle. The next cycle begins the first of one or more data phases. Data is transferred
between initiator and target in each cycle that both IRDY and TRDY are asserted. Wait cycles may be
inserted in a data phase by the initiator (by negating IRDY) or by the target (by negating TRDY).
Once an initiator has asserted IRDY, it cannot change IRDY or FRAME until the current data phase
completes regardless of the state of TRDY. Once a target has asserted TRDY or STOP, it cannot change
DEVSEL,TRDY, or STOP until the current data phase completes. In simpler terms, once an initiator or
target has committed to the data transfer, it cannot back out.
When the initiator intends to complete only one more data transfer (which could be immediately after the
address phase), FRAME is negated and IRDY is asserted (or kept asserted) indicating the initiator is ready.
After the target indicates the final data transfer (by asserting TRDY), the PCI bus may return to the idle
state (both FRAME and IRDY are negated).
NOTE
No Fast Back-to-Back transactions are supported by the MPC5200B.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-57
PCI Controller
10.4.1.3
PCI Transactions
The figures in this section show the basic “memory read” and “memory write” command transactions.
Figure 10-50 shows a PCI burst read transaction (2-beat). The signal FRAME is driven low to initiate the
transfer. Cycle 1 is the address phase with valid address information driven on the AD bus and a PCI
command driven on the C/BE bus. In cycle 2, the AD bus is in a turnaround cycle because of the read on
a muxed bus. The byte enables, which are active low, are driven onto the C/BE bus in this clock. Any
combination of byte enables can be asserted (none may be asserted). A target will respond to an address
phase by driving the DEVSEL signal. The specification allows for four types of decode operations. The
target can drive DEVSEL in 1, 2 or 3 clocks depending on whether the target is a fast, medium or slow
decode device. A single device is allowed to drive DEVSEL should another agent fail to respond by the
fourth clock. This is called “subtractive decoding” in PCI terminology.
A valid transfer occurs when both IRDY and TRDY are asserted. If either are negated during a data phase,
it is considered a wait state. The target asserts a wait state in cycles 3 and 5 of Figure 10-50. A master
indicates that the final data phase is to occur by negating FRAME. The final data phase occurs in cycle 6.
Another agent cannot start an access until cycle 8.
1
2
3
4
5
6
7
8
CLK
FRAME
AD
C/BE
A1
CMD
D1
D2
Byte Enables
IRDY
TRDY
(wait)
(wait)
DEVSEL
Address
Phase
Data Phase 1
Data Phase 2
Figure 10-50. PCI Read Terminated by Master
MPC5200B User’s Manual, Rev. 3
10-58
Freescale Semiconductor
PCI Controller
Figure 10-51 shows a write cycle which is terminated by the target. In this diagram the target responds as
a slow device, driving DEVSEL in cycle 4. The first data is transferred in cycle 4. The master inserts a
wait state at cycle 5. The target indicates that it can accept only one more transfer by asserting both TRDY
and STOP at the same time in cycle 5. The signal STOP must remain asserted until FRAME negates. The
final data phase does not have to transfer data. If STOP and IRDY are both asserted while TRDY is
negated, it is considered a target disconnect without a transfer. See the PCI specification for more details.
1
2
3
4
5
6
7
8
CLK
FRAME
AD
C/BE
A1
CMD
D2
D1
Byte Enables
IRDY
TRDY
(wait)
DEVSEL
STOP
Address
Phase
Data Phase 1
Data Phase 2
Figure 10-51. PCI Write Terminated by Target
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-59
PCI Controller
10.4.1.4
PCI Bus Commands
PCI supports a number of different commands. These commands are presented by the initiator on the
C/BE[3:0] lines during the address phase of a PCI transaction.
Table 10-53. PCI Bus Commands
C/BE[3:0]
PCI Bus
Command
MPC5200B
Supports
as Initiator
MPC5200B
Supports
as Target
Definition
0000
Interrupt
acknowledge
Yes
No
The interrupt acknowledge command is a read (implicitly
addressing an external interrupt controller). Only one device on the
PCI bus should respond to the interrupt acknowledge command.
0001
Special Cycle
Yes
No
The Special Cycle command provides a mechanism to broadcast
select messages to all devices on the PCI bus.
0010
I/O-read
Yes
No
The I/O-read command accesses agents mapped into the PCI I/O
space.
0011
I/O-write
Yes
No
The I/O-write command accesses agents mapped into the PCI I/O
space.
0100
Reserved
No
No
—
0101
Reserved
No
No
—
0110
Memory-read
Yes
Yes
The memory read command accesses agents mapped into PCI
memory space.
0111
Memory-write
Yes
Yes
The memory write command accesses agents mapped into PCI
memory space.
1000
Reserved
No
No
—
1001
Reserved
No
No
—
1010
Configuration
read
Yes
Yes
The configuration read command accesses the 256 byte
configuration space of a PCI agent.
1011
Configuration
write
Yes
Yes
The configuration read command accesses the 256 byte
configuration space of a PCI agent.
1100
Memory read
multiple
Yes
Yes
For MPC5200B, the memory read multiple command functions the
same as the memory read command. Cache line wrap is
implemented when XL Bus is the transaction initiator and it also
wraps.
1101
Dual address
cycle
No
No
The dual address cycle command is used to transfer a 64-bit
address (in two 32-bit address cycles) to 64-bit addressable
devices. MPC5200B device does not respond to this command.
MPC5200B User’s Manual, Rev. 3
10-60
Freescale Semiconductor
PCI Controller
Table 10-53. PCI Bus Commands (continued)
C/BE[3:0]
PCI Bus
Command
MPC5200B
Supports
as Initiator
MPC5200B
Supports
as Target
Definition
1110
Memory
read line
Yes
Yes
The memory read line command indicates that an initiator is
requesting the transfer of an entire cache line.For MPC5200B, the
memory read line functions the same as the memory read
command. Cache line wrap is not implemented.
1111
Memory write
and invalidate
Yes (DMA
access only)
Yes
The memory write and invalidate command indicates that an
initiator is transferring an entire cache line, and, if this data is in any
cacheable memory, that cache line needs to be invalidated. The
memory write and invalidate functions the same as the memory
write command. Cache line wrap is implemented.
Software must make sure that the cache line register and
max_beats register are set to the same value and the packet size
must be a multiple of the cache line size.
This instruction is supported only by the TX SCPCI initiator
interface and when the MPC5200B acts as a target.
Though MPC5200B supports many PCI commands as an initiator, the Communication Sub-System
Initiator interface is intended to use PCI Memory Read, and Memory Write commands.
10.4.1.5
Addressing
PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configuration
space. Address decoding on the PCI bus is performed by every device for every PCI transaction. Each
agent is responsible for decoding its own address. PCI supports two types of address decoding: positive
decoding and subtractive decoding. The address space which is accessed depends primarily on the type of
PCI command that is used.
10.4.1.5.1
Memory Space Addressing
For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits of the
address: linear incrementing(AD[1:0] = 0b00) and cache wrap mode (AD[1:0] = 0b10). The other two
AD[1:0] encodings (0b01 and 0b11) are reserved.
For linear incrementing mode, the memory address is encoded/decoded using AD[31:2]. Thereafter, the
address is incremented by 4 bytes after each data phase completes until the transaction is terminated or
completed (a 4 byte data width per data phase is implied). Note, the two low-order bits of the address are
still included in all the parity calculations.
MPC5200B supports both linear incrementing and cache wrap mode as an initiator. For memory
transactions, when an XL Bus burst transaction is wrapped, the cache wrap mode is automatically
generated. For zero-word-aligned bursts and single-beat transactions, MPC5200B drives AD[1:0] to 0b00.
As a target, the MPC5200B treats cache wrap mode as a reserved memory mode. MPC5200B will return
the first beat of data and then signal a disconnect without data on the second data phase.
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10.4.1.5.2
I/O Space Addressing
For PCI I/O accesses, all 32 address signals are used to provide an address with granularity of a single byte.
Once a target has claimed an I/O access, it must determine if it can complete the entire access as indicated
by the byte enable signals. If all the selected bytes are not in the address range of the target, the entire
access cannot complete. In this case, the target does not transfer any data, and terminates the transaction
with a target-abort.
Table 10-54. PCI I/O Space Byte Decoding
Access Size
AD[1:0]
C/BE[3:0]
Data
8-bit
00
xxx0
AD[7:0]
01
xx01
AD[15:8]
10
x011
AD[23:16]
11
0111
AD[31:24]
00
xxx0
AD[15:0]
01
xx01
AD[23:8]
10
x011
AD[31:16]
00
xxx0
AD[23:0]
01
xx01
AD[31:8]
00
xxx0
AD[31:0]
16-bit
24-bit
32-bit
10.4.1.5.3
Configuration Space Addressing and Transactions
PCI supports two types of configuration accesses. Their primary difference is the format of the address on
the AD[31:0] signals during the address phase. The two low-order bits of the address indicate the format
used for the configuration address phase: type 0 (AD[1:0] = 0b00) or type 1 (AD[1:0] = 0b01). Both
address formats identify a specific device and a specific configuration register for that device.
Type 0 configuration accesses are used to select a device on the local PCI bus. They do not propagate
beyond the local PCI bus and are either claimed by a local device or terminated with a master-abort. Type 1
configuration accesses are used to target a device on a subordinate bus through a PCI-to-PCI bridge.
Type 1 accesses are ignored by all targets except PCI-to-PCI bridges that pass the configuration request to
another PCI bus.
When the controller initiates a configuration access on the PCI bus, it places the configuration address
information on the AD bus and the configuration command on the C/BE[3:0] bus. A Type 0 configuration
transaction is indicated by setting AD[1:0] to 0b00 during the address phase. The bit pattern tells the
community of devices on the PCI bus that the bridge that “owns” that bus has already performed the bus
number comparison and verified that the request targets a device on its bus. Figure 10-52 shows the
contents of the AD bus during the address phase of the Type 0 configuration access.
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PCI Controller
Target configuration double word number
31
11 10
87
2 1 0
DW
Number
Function
Number
Reserved
0 0
Figure 10-52. Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction
Address bits [10:8] identify the target function and bits AD[7:2] select one of the 64 configuration dwords
within the target function’s configuration space. For Type 0 configuration transactions, the target device’s
IDSEL pin must be asserted. The upper 21 address lines are commonly used as IDSELs since they are not
used during the address phase of a type 0 configuration transaction.
If the target bus is a bus that is subordinate to the local PCI bus (bus 0), the configuration transaction is
still initiated on bus 0, but indicates that none of the devices on this bus are the target of the transaction.
Rather, only PCI-to-PCI bridges residing on the bus should pay attention to the transaction because it
targets a device on a bus further out in the hierarchy beyond a PCI-to-PCI bridge that is attached to the
local PCI bus (bus 0). This is accomplished by initiating a Type 1 configuration transaction (setting
AD[1:0] to 01b during the address phase). This pattern instructs all functions other than PCI-to-PCI
bridges that the transaction is not for any of them. Figure 10-53 illustrates the contents of the AD bus
during the address phase of the Type 1 configuration access.
Double word number in the device’s configuration space
31
24 23
Reserved
16 15
Bus
Number
11 10
Device
Number
Function
Number
8 7
2 1 0
DW
Number
0 1
Figure 10-53. Contents of the AD Bus During Address Phase of a Type 1 Configuration Transaction
During the address phase of a Type 1 configuration access, the information on the AD bus if formatted as
follows:
• AD[1:0] contain a 01b, identifying this as a Type 1 configuration access.
• AD[7:2] identifies one of 64 configuration dwords within the target devices’s configuration space.
• AD[10:8] identifies one of the eight functions within the target physical device.
• AD[15:11] identifies one of 32 physical devices. This field is used by the bridge to select which
device’s IDSEL line to assert.
• AD[23:16] identifies one of 256 PCI buses in the system.
• AD[31:24] are reserved and are cleared to zero.
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During a Type 1 configuration access, PCI devices ignore the state of their IDSEL inputs. When any
PCI-to-PCI bridge latches a Type 1 configuration access (command = configuration read or write and
AD[1:0] = 01b) on its primary side, it must determine whether the bus number field on the AD bus matches
the number of its secondary bus or if it’s within the range of its subordinate buses. If the bus number
matches, it should claim and pass the configuration access onto its secondary bus as a Type 0 configuration
access, decoding the device number to select one of the IDSEL lines. If the bus number isn’t equal to its
secondary bus, but is within the range of buses that are subordinate to the bridge, the bridge claims and
passes that access through as a Type 1 access.
10.4.1.5.4
Address Decoding
For positive address decoding, an address hits when the address on the address bus matches an assigned
address range. Multiple devices on the same PCI bus may use positive address decoding, though there can
not be any overlap in the assigned address ranges.
For subtractive address decoding, an address hits when the address on the address bus does not match any
address range for any of the PCI devices on the bus. Only one device on a PCI bus may use subtractive
address decoding, and its use is optional.
10.4.2
Initiator Arbitration
There are three possible internal initiator sources - CommBus Transmit, CommBus Receive, or the XL bus
(from Internal System Arbiter). Custom interface logic arbitrates and provides mux select control for these
sources to the PCI controller. Figure 10-54 illustrates the arbitration block connection.
PCI
request/grant
(to PCI Arbiter)
XL Bus
Arbiter
XL Bus
Initiator
PCI
Initiator
Arbiter
PCI Controller
External
PCI bus
tx_req
Multi-Channel DMA
Controller
Comm
Bus
Initiator
tx_gnt
rx_req
Initiator
Interface
rx_gnt
Figure 10-54. Initiator Arbitration Block Diagram
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10.4.2.1
Priority Scheme
The PCI Initiator arbiter uses the following fixed priority scheme.
1. XL bus Initiator
2. CommBus Transmit (Tx)
3. CommBus Receive (Rx) (lowest)
10.4.3
Configuration Interface
The PCI bus protocol requires the implementation of a standardized set of registers for most devices on
the PCI bus. MPC5200B implements a Type 0 Configuration register set or header. They are described in
Section 10.3.1, “PCI Controller Type 0 Configuration Space.” These registers are primarily intended to be
read or written by the PCI configuring master at initialization time through the PCI bus. MPC5200B
provides internal access to these registers through a Slave bus interface. As with most MPC5200B
registers, they are accessible by software in the address space at offsets of MBAR. Internal accesses to the
Type 0 Configuration header do not require PCI arbitration when they are accessed as offsets of MBAR
and are allowed to execute regardless of whether any write data is posted in the PCI Controller.
If MPC5200B is the configuring master, the Slave bus interface should be used to configure the PCI
Controller. An external master would configure the PCI controller through the external PCI bus.
More information on the standard PCI Configuration register can be found in the PCI 2.2 specification.
10.4.4
XL bus Initiator Interface
The XL bus Initiator Interface provides access to the PCI bus for XL bus masters, primarily the processor
core. This interface is accessed through three windows in MPC5200B address space set up by base address
and base address mask registers (Initiator Window 0 Base/Translation Address Register
PCIIW0BTAR(RW)). The base address registers must be enabled by setting their respective Enable bits in
the Initiator Window Configuration Register PCIIWCR(RW). Accesses to this area are translated into PCI
transactions on the PCI bus. See Section 10.6.2, Address Maps for examples on setting up address
windows.
The particular type of PCI transaction generated is determined by the PCI configuration bits associated
with the address window (PCIIWCR). For example, the user might set one window to do PCI memory read
multiple accesses, one window for PCI I/O accesses, and the other window to do non-prefetchable
(memory-mapped I/O) PCI memory accesses. Table 10-63 for command translation.
In addition to the configurable address window mapping logic, the register interface provides a
Configuration Address Register, which provides the ability to generate Configuration, Interrupt
Acknowledge and Special Cycles. External PCI devices should be configured through this interface.
Section 10.4.4.2, “Configuration Mechanism” for configuration, interrupt acknowledge, and special cycle
command support.
The PCI XL Bus Initiator interface supports all XL Bus transactions, including single-beat transfers and
bursts (32 bytes). Single-beat 64-bit data transactions are automatically translated into 2-beats burst
transfers on the PCI bus. Standard XL bus burst transactions are supported as well, however, buffering is
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implemented to boost performance during writes and avoid deadlock scenario for all reads and memory
writes. If the target for an XL bus read from PCI disconnects part way through the burst, MPC5200B may
have to handle a local memory access from an alternate PCI master before the disconnected transfer can
continue.
XL Bus initiator read requests are decoded into four types: PCI Memory, I/O, Configuration, and Interrupt
Acknowledge. The PCI Controller must first gain access to the PCI bus before acknowledging the XL Bus
read request. The specific timing of the address acknowledge is dependent upon the type of transfer.
When the XL bus requests burst data from PCI space, the data received from PCI is stored in a buffer until
all requested data has been latched. The PCI Controller does not terminate the address tenure of the XL
Bus transaction until all requested data is latched. This is because PCI targets are allowed to disconnect in
the middle of a transfer, and the XL bus requires burst transfers to be atomic. If the PCI target disconnects
in the middle of the data transfer and an alternate PCI master acquires the bus and initiates a local memory
access, the Controller retries the internal read transaction on the XL bus. The PCI Controller continues to
request mastership of the PCI bus until the original request is completed.
For example, if the XL bus initiates a burst read, and the PCI target disconnects after transferring the first
half of the burst, MPC5200B re-arbitrates for the PCI bus, and when granted, initiates a new transaction
with the address of the third beat of the burst (4-beat XL Bus bus bursts). If an alternate PCI master
requests data from local memory while the PCI Controller is waiting for the PCI bus grant, the PCI
controller retries the XL Bus bus transaction to allow the PCI-initiated transaction to complete and the read
buffer will be emptied.
PCI critical-word-first (CWF) burst operation (i.e. cache line wrap burst) is supported and the 2-bit cache
line wrap address mode is driven on the address bus when the XL Bus bus starts the burst at a
non-zero-word-first address. Note that this option is only provided as a means to support memory targets
that support cache-line wrap.
NOTE
A processor is not permitted to cache from any external memory targets
residing on the PCI bus. This was allowed previously in the PCI spec. 2.1.
The PCI spec. 2.2. took this requirements away.
XL bus writes are decoded into PCI memory, PCI I/O, PCI configuration, or special cycles. If the
transaction decodes into an I/O, configuration, or special cycle, the write is connected. The PCI controller
gains access to the PCI bus and successfully transfers the data before it asserts address acknowledge to the
XL bus. If the address maps to PCI memory space, the XL Bus address tenure is immediately
acknowledged and write data is posted.
A 32-byte buffer is used to post memory writes from XL Bus to PCI. Buffering minimizes the effect of the
slower PCI bus on the higher-speed XL bus. It may contain single-beat XL Bus write transactions or a
single burst. After the XL bus write data is latched internally, the bus is available for subsequent
transactions without having to wait for the write to the PCI target to complete. If a subsequent XL Bus
write request to the PCI bus comes in, the data transfer is delayed until all previous writes to the PCI bus
are completed. Only when the write buffer is empty can burst data from the XL bus be posted.
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10.4.4.1
Endian Translation
The PCI bus is inherently little endian in its byte ordering. The internal XLB bus, however, is big endian.
XLB bus transactions are limited to 1, 2, 3, 4, 5, 6, 7, 8, or 32 byte (burst) transactions within the data bus
byte lanes on any 32-bit address boundary for burst transfers. Table 10-55 shows the byte lane mapping
between the two buses.
Table 10-55. XLB bus to PCI Byte Lanes for Memory1 Transactions
XL bus
PCI Bus
Data Bus Byte Lanes
A
TSIZ
AD
BE
[29:31]
[0:2]
[3:0]
31:2
4
23:1
6
15:8
7:0
7
[2:0]
0
1
2
3
4
5
6
000
001
OP7
—
—
—
—
—
—
—
000
1110
—
—
—
OP7
001
001
—
OP7
—
—
—
—
—
—
000
1101
—
—
OP7
—
010
001
—
—
OP7
—
—
—
—
—
000
1011
—
OP7
—
—
011
001
—
—
—
OP7
—
—
—
—
000
0111
OP7
—
—
—
100
001
—
—
—
—
OP7
—
—
—
100
1110
—
—
—
OP7
101
001
—
—
—
—
—
OP7
—
—
100
1101
—
—
OP7
—
110
001
—
—
—
—
—
—
OP7
—
100
1011
—
OP7
—
—
111
001
—
—
—
—
—
—
—
OP7
100
0111
OP7
—
—
—
000
010
OP6
OP7
—
—
—
—
—
—
000
1100
—
—
OP7
OP6
001
010
—
OP6
OP7
—
—
—
—
—
000
1001
—
OP7
OP6
—
010
010
—
—
OP6
OP7
—
—
—
—
000
0011
OP7
OP6
—
—
011
010
—
—
—
OP6
OP7
—
—
—
000
0111
OP6
—
—
—
100
1110
—
—
—
OP7
100
010
—
—
—
—
OP6
OP7
—
—
100
1100
—
—
OP7
OP6
101
010
—
—
—
—
—
OP6
OP7
—
100
1001
—
OP7
OP6
—
110
010
—
—
—
—
—
—
OP6
OP7
100
0011
OP7
OP6
—
—
000
011
OP5
OP6
OP7
—
—
—
—
—
000
1000
—
OP7
OP6
OP5
001
011
—
OP5
OP6
OP7
—
—
—
—
000
0001
OP7
OP6
OP5
—
010
011
—
—
OP5
OP6
OP7
—
—
—
000
0011
OP6
OP5
—
—
100
1110
—
—
—
OP7
000
0111
OP5
—
—
—
100
1100
—
—
OP7
OP6
011
011
—
—
—
OP5
OP6
OP7
—
—
100
011
—
—
—
—
OP5
OP6
OP7
—
100
1000
—
OP7
OP6
OP5
101
011
—
—
—
—
—
OP5
OP6
OP7
00
0001
OP7
OP6
OP5
—
000
100
OP4
OP5
OP6
OP7
—
—
—
—
00
0000
OP7
OP6
OP5
OP4
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Table 10-55. XLB bus to PCI Byte Lanes for Memory1 Transactions (continued)
XL bus
Data Bus Byte Lanes
A
TSIZ
[29:31]
[0:2]
0
1
2
3
4
5
6
001
100
—
OP4
OP5
OP6
OP7
—
—
010
011
100
100
—
—
—
—
OP4
—
OP5
OP4
OP6
OP5
OP7
OP6
—
OP7
AD
BE
[3:0]
31:2
4
23:1
6
15:8
7:0
7
[2:0]
—
000
0001
OP6
OP5
OP4
—
100
1110
—
—
—
OP7
000
0011
OP5
OP4
—
—
100
1100
—
—
OP7
OP6
000
0111
OP4
—
—
—
100
1000
—
OP7
OP6
OP5
—
—
100
100
—
—
—
—
OP4
OP5
OP6
OP7
100
0000
OP7
OP6
OP5
OP4
000
101
OP3
OP4
OP5
OP6
OP7
—
—
—
000
0000
OP6
OP5
OP4
OP3
100
1110
—
—
—
OP7
000
0001
OP5
OP4
OP3
—
100
1100
—
—
OP7
OP6
000
0011
OP4
OP3
—
—
100
1000
—
OP7
OP6
OP5
000
0111
OP3
—
—
—
100
0000
OP7
OP6
OP5
OP4
000
0000
OP5
OP4
OP3
OP2
100
1100
—
—
OP7
OP6
000
0001
OP4
OP3
OP2
—
100
1000
—
OP7
OP6
OP5
000
0011
OP3
OP2
—
—
100
0000
OP7
OP6
OP5
OP4
000
0000
OP4
OP3
OP2
OP1
100
1000
—
OP7
OP6
OP5
000
0001
OP3
OP2
OP1
—
100
0000
OP7
OP6
OP5
OP4
000
0000
OP3
OP2
OP1
OP0
100
0000
OP7
OP6
OP5
OP4
001
010
011
000
001
010
000
001
000
1
PCI Bus
101
101
101
110
110
110
111
111
000
—
—
—
OP2
—
—
OP1
—
OP0
OP3
—
—
OP3
OP2
—
OP2
OP1
OP1
OP4
OP3
—
OP4
OP3
OP2
OP3
OP2
OP2
OP5
OP4
OP3
OP5
OP4
OP3
OP4
OP3
OP3
OP6
OP5
OP4
OP6
OP5
OP4
OP5
OP4
OP4
OP7
OP6
OP5
OP7
OP6
OP5
OP6
OP5
OP5
—
OP7
OP6
—
OP7
OP6
OP7
OP6
OP6
—
—
OP7
—
—
OP7
—
OP7
OP7
The byte lane translation will be similar for other types of transactions. However, the PCI address may be different as explained
in Section 10.4.1.5, “Addressing.”
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10.4.4.2
Configuration Mechanism
In order to support both Type 0 and Type 1 configuration transactions, MPC5200B provides the 32 bit
Configuration Address Register (CAR), located at module address 0x1F8. The register specifies the target
PCI bus, device, function, and configuration register to be accessed. A read or a write to the MPC5200B
window defined as PCI I/O space, in PCIIWCR, causes the host bridge to translate the access into a PCI
configuration cycle if the enable bit in the Configuration Address Register is set and the device number
does not equal 0b1_1111. For space to be defined as I/O space, the accessed space (one of the initiator
Windows) must be programmed as I/O, not memory. Section 10.3.2.8, “Initiator Window Configuration
Register PCIIWCR(RW).”
The format of the Configuration Address Register is shown in Section 10.3.2.12, “Configuration Address
Register PCICAR(RW).” When MPC5200B detects an access to an I/O Window, it checks the enable flag
and the device number in the Configuration Address Register. If the enable bit is set, and the device
number is not 0b1_1111, the MPC5200B performs a configuration cycle translation function and runs a
configuration read or configuration write transaction on the PCI bus. The device number 0b1_1111 is used
for performing interrupt acknowledge and Special Cycle transactions. See Section 10.4.4.2.3, “Interrupt
Acknowledge Transactions” and Section 10.4.4.2.4, “Special Cycle Transactions” for more information.
If the bus number corresponds to the local PCI bus (bus number = 0x00), a Type 0 configuration cycle
transaction is performed. If the bus number indicates a remote PCI bus, MPC5200B performs a Type 1
configuration cycle translation. If the enable bit is not set, the access to the Configuration Window is
passed through to the PCI bus as a I/O space transaction at the internal address (window translation
applies).
Note that the PCI data byte enables (C/BE[3:0]) are determined by the size access to the Window.
10.4.4.2.1
Type 0 Configuration Translation
Figure 10-55 shows the Type 0 translation function performed on the contents of the Configuration
Address Register to the AD[31:0] signals on the PCI bus during the address phase of the configuration
cycle (only applies when the Enable bit in the Configuration Address Register is set).
Reserved
Contents of Configuration Address Register
31 30
E
24 23
0000000
16 15
Bus Number
11 10
Device Number
Function Number
8 7
dword
2 1 0
00
AD[31:0] Signals During Address Phase
See Table 10-56
31
11 10
IDSEL (only one signal high)
Function Number/dword
2 1 0
00
Figure 10-55. Type 0 Configuration Translation
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For Type 0 configuration cycles, MPC5200B translates the device number field of the Configuration
Address Register into a unique IDSEL line shown in Table 10-56. (allows for 21 different devices).
Table 10-56. Type 0 Configuration
Device Number to IDSEL Translation
Device Number
IDSEL
Binary
Decimal
0b0_0000-0b0_1001
0-9
-
0b0_1010
10
AD31
0b0_1011
11
AD11
0b0_1100
12
AD12
0b0_1101
13
AD13
0b0_1110
14
AD14
0b0_1111
15
AD15
0b1_0000
16
AD16
0b1_0001
17
AD17
0b1_0010
18
AD18
0b1_0011
19
AD19
0b1_0100
20
AD20
0b1_0101
21
AD21
0b1_0110
22
AD22
0b1_0111
23
AD23
0b1_1000
24
AD24
0b1_1001
25
AD25
0b1_1010
26
AD26
0b1_1011
27
AD27
0b1_1100
28
AD28
0b1_1101
29
AD29
0b1_1110
30
AD30
0b1_1111
31
-
Note: Device numbers 0b0_0000 to 0b0_1001 are reserved.
Programming to these values and issuing a configuration
transaction will result in a PCI configuration cycle with
AD31-AD11 driven low.
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MPC5200B can issue PCI configuration transactions to itself. A Type 0 configuration initiated by
MPC5200B can access its own configuration space by asserting its IDSEL input signal. This is the only
way MPC5200B can clear its own status register bits (read-write-clear).
For Type 0 translations, the function number and dword fields are copied without modification onto the
AD[10:2] signals and AD[1:0] are driven low during the address phase.
10.4.4.2.2
Type 1 Configuration Translation
For Type 1 translations, the 30 high-order bits of the Configuration Address Register are copied without
modification onto the AD[31:2] signals during the address phase. The AD[1:0] signals are driven to 0b01
during the address phase to indicate a Type 1 configuration cycle.
10.4.4.2.3
Interrupt Acknowledge Transactions
When MPC5200B detects a read from an I/O-defined Window (Section 10.3.2.8, “Initiator Window
Configuration Register PCIIWCR(RW)”), it checks the enable flag, bus number, and the device number in
the Configuration Address Register (Section 10.3.2.12, “Configuration Address Register
PCICAR(RW)”). If the enable bit is set, the bus number corresponds to the local PCI bus (bus number =
0x00), and the device number is all 1’s (device number = 0b1_1111), then an interrupt acknowledge
transaction is initiated. If the bus number indicates a subordinate PCI bus (bus number != 0x00), a Type 1
configuration cycle is initiated, similar to any other configuration cycle for which the bus number does not
match. The function number and dword values are ignored.
The interrupt acknowledge command (0b0000) is driven on the C/BE[3:0] signals and the address bus is
driven with a stable pattern during the address phase, but a valid address is not driven. The address of the
target device during an interrupt acknowledge is implicit in the command type. Only the system interrupt
controller on the PCI bus should respond to the interrupt acknowledge and return the interrupt vector on
the data bus during the data phase. The size of the interrupt vector returned is indicated by the value driven
on the C/BE[3:0] signals.
10.4.4.2.4
Special Cycle Transactions
When the MPC5200B detects a write to an I/O-defined Window (Section 10.3.2.8, “Initiator Window
Configuration Register PCIIWCR(RW)”), it checks the enable flag, bus number, and the device number in
the Configuration Address Register (Section 10.3.2.12, “Configuration Address Register
PCICAR(RW)”). If the enable bit is set, the bus number corresponds to the local PCI bus (bus number =
0x00), and the device number is all 1’s (device number = 0b1_1111), then a Special Cycle transaction is
initiated. If the bus number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration
cycle is initiated, similar to any other configuration cycle for which the bus number does not match. The
function number and dword values are ignored.
The Special Cycle command (0b0001) is driven on the C/BE[3:0] signals and the address bus is driven
with a stable pattern during the address phase, but contains no valid address information. The Special
Cycle command contains no explicit destination address, but broadcast to all agents on the same bus
segment. Each receiving agent must determine whether the message is applicable to it. PCI agent will
never assert DEVSEL in response to a Special Cycle command. Master Abort is the normal termination
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for a Special Cycle and no errors are reported for this case of Master Abort termination. This command is
basically a broadcast to all agents, and interested agents accept the command and process the request.
NOTE
Special Cycle commands do not cross PCI-to-PCI bridges. If a master wants
to generate a Special Cycle command on a specific bus in the hierarchy that
is not its local bus, it must use a Type 1 configuration write command to do
so. Type 1 configuration write commands can traverse PCI-to-PCI bridges
in both directions for the purpose of generating Special Cycle commands on
any bus in the hierarchy and are restricted to a single data phase in length.
However, the master must know the specific bus on which it desires to
generate the Special Cycle command and cannot simply do a broadcast to
one bus and expect it to propagate to all buses.
During the data phase, AD[31:0] contain the Special Cycle message and an optional data field. The Special
Cycle message is encoded on the 16 least significant bits (AD[15:0]) and the optional data field is encoded
on the most significant bits (AD[31:16]). The Special Cycle message encodings are assigned by the PCI
SIG Steering Committee. The current list of defined encodings are provided in Table 10-57.
Table 10-57. Special Cycle Message Encodings
AD[15:0]
0x0000
SHUTDOWN
0x0001
HALT
0x0002
x86 architecture-specific
0x0003-0xFFFF
10.4.4.3
Message
reserved
Transaction Termination
If the PCI cycle Master Aborts, interface will return 0xFFFFFFFF as read data, but complete without error.
It will issue an interrupt to the internal interrupt controller if enabled.
For abnormal transaction termination during an XL bus-initiated transaction (unsupported transfer types,
retry limit reached, or target abort), an error is generated. It will issue an interrupt to the MPC5200B
Interrupt controller if such interrupts are enabled.
Transfers that cross the 32-bit boundary (greater than 4 bytes) to a PCI non-memory address range result
in a transfer error. The space is defined as non-memory if the IO/M# configuration bit associated with that
window is programmed “0”.
Table 10-58. Unsupported XL Bus Transfers
XL Bus Transaction
PCI Address Space
Burst (32-byte)
Nonmemory
> 4 byte Single Beat
Nonmemory
4 byte Single Beat at a[29:31] 001, 010, or 011
Nonmemory
3 byte Single Beat at a[29:31] 010 or 011
Nonmemory
2 byte Single Beat at a[29:31] 011
Nonmemory
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10.4.5
•
•
•
•
•
•
XL bus Target Interface
The target interface can issue target abort, target retry, and target disconnect terminations.
The target interface does NOT support fast back-to-back cycles.
No support of dual address cycles as a PCI target.
Target transactions are not snooped by the processor.
Medium device selection timing
Three 32-byte buffers enhance data throughput.
The XL Bus Target Interface provides access for external PCI masters to two windows of MPC5200B
address space. Target Base Address Translation Registers 0 and 1 allow the user to map PCI address hits
on MPC5200B PCI Base Address Registers to areas in the internal address space. All of these registers
must be enabled for this interface to operate.
Upon detection of a PCI address phase, the PCI controller decodes the address and bus command to
determine if the transaction is for local memory (BAR0 or BAR1hit). If the transaction falls within
MPC5200B PCI space (a PCI memory space only), the PCI Controller target interface asserts DEVSEL,
latches the address, decodes the PCI bus command, and forwards them to the internal control unit. On
writes, data is forwarded along with the byte enables to the internal gasket. On reads, four bytes of data
are provided to the PCI bus and the byte enables determine which byte lanes contain meaningful data. If
no byte enables are asserted, MPC5200B completes a read access with valid data and completes a write
access by discarding the data internally. All target transactions will be translated into XL bus master
transactions.
There are two address translation registers that must be initialized before data transfer can begin. These
address registers correspond to BAR0 and BAR1 in MPC5200B PCI Type 00h Configuration space
register (PCI space). When there is a hit on MPC5200B PCI base address ranges (0 or 1), the upper bits of
the address are written over by this register value to address some space in MPC5200B. One 256Kbyte
base address range (BAR0) maps to non-prefetchable local memory and one 1Gbyte range (BAR1)
targeted to prefetchable memory.
10.4.5.1
Reads from Local Memory
MPC5200B can provide continuous data to a PCI master using two 32-byte buffers. The PCI controller
bursts reads internally at each 32-byte PCI address boundary. The data is stored in the first 32-byte buffer
until either the PCI master flushes the data or the transaction terminates (FRAME deasserts). For
prefetchable memory (BAR1 space), the next line can be fetched from memory in anticipation of the next
PCI request (speculative read) and stored in the second buffer. Prefetching is performed for
BAR1-addressed transactions if the PCI command is a Memory-Read-Multiple or the prefetch bit is set in
the Target Control Register PCITCR(RW).
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10.4.5.2
Local Memory Writes
A 32-byte write buffer is implemented to improve data throughput. This allows a write operation to be
“posted”, that is to successfully complete even when the PCI internal controller is requesting access to the
local memory. In other words, data is latched while waiting for internal access to local memory to
complete. While PCI burst transactions are accepted, writes are sent out on the internal bus as single-beat.
NOTE
Before a read from XL Bus to PCI or PCI to XL Bus can complete, all
posted writes are flushed.
If the PCI controller aborts the transaction in the middle of PCI burst due to internal conflicts, the external
master recognizes some of the data as transferred. (Subsequent transfers of a burst will be aborted on PCI
bus). The external PCI master must query the “Target abort signalled” bit in the PCI Type 00h
configuration status register to determine if a target abort occurred.
10.4.5.3
Data Translation
The XL bus supports misaligned operations, however, it is strongly recommended that software attempt to
transfer contiguous code and data where possible. Non-contiguous transfers degrade performance.
PCI-to-XL Bus transaction data translation is shown in Table 10-59 and Table 10-60.
Table 10-59. Aligned PCI to XL Bus Transfers
PCI Bus
XL bus
Data Bus Byte Lanes
BE
[3:0]
AD[2:0]
1110
000
1101
000
1011
000
0111
000
1110
100
1101
100
1011
100
0111
100
1100
000
1001
000
0011
000
1100
100
1001
100
0011
100
1000
000
0001
000
1000
100
31:24
23:16
15:8
7:0
A[29:31]
0
OP3
OP3
OP3
6
100
OP3
OP3
OP3
111
OP3
OP3
OP2
OP2
OP3
OP2
001
OP2
OP3
OP2
010
OP3
OP3
000
OP2
OP2
OP3
OP2
OP3
100
OP2
101
OP2
OP3
OP2
110
OP3
OP2
OP2
OP1
OP3
OP2
OP1
000
000
OP1
7
OP3
110
OP3
OP3
5
101
OP3
OP3
4
OP3
011
OP3
3
OP3
010
OP3
2
OP3
001
OP3
OP3
000
1
OP3
OP2
OP1
OP2
OP3
OP1
OP2
100
OP3
OP3
OP1
OP2
OP3
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Table 10-59. Aligned PCI to XL Bus Transfers (continued)
PCI Bus
XL bus
Data Bus Byte Lanes
BE
[3:0]
AD[2:0]
0001
100
OP3
OP2
OP1
0000
000
OP3
OP2
OP1
OP0
000
0000
100
OP3
OP2
OP1
OP0
100
31:24
23:16
15:8
7:0
A[29:31]
0
1
2
3
4
101
OP0
OP1
OP2
5
6
7
OP1
OP2
OP3
OP1
OP2
OP3
6
7
OP3
OP0
Table 10-60. Non-contiguous PCI to XL Bus Transfers
(requires two XL Bus bus accesses)
PCI Bus
XL bus
Data Bus Byte Lanes
BE
[3:0]
AD[2:0]
1010
000
31:24
23:16
15:8
7:0
A[29:31]
0
OP3
OP2
000
1
100
OP3
OP2
3
4
5
OP2
010
1010
2
OP3
100
OP2
110
0110
000
OP3
OP2
000
OP3
OP2
011
0110
100
OP3
OP2
OP3
100
OP2
111
0101
000
OP3
OP2
OP3
001
OP2
011
0101
100
OP3
OP2
OP3
101
OP2
111
0010
000
OP3
OP2
OP1
000
OP3
OP1
010
0010
100
OP3
OP2
OP1
OP2
OP3
100
OP1
110
0100
000
OP3
OP2
OP1
000
OP2
OP1
OP2
011
0100
100
OP3
OP2
OP1
OP3
100
111
OP3
OP1
OP2
OP3
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10.4.5.4
Target Abort
A target abort will occur if the PCI address falls within a base address window (BAR0 or BAR1) that has
not been enabled. See Section 10.3.2.2, “Target Base Address Translation Register 0 PCITBATR0(RW)”
and Section 10.3.2.3, “Target Base Address Translation Register 1 PCITBATR1(RW).”
10.4.5.5
Latrule Disable
The latrule disable bit in the interface control register, Section 10.3.2.4, “Target Control Register
PCITCR(RW),” prevents the PCI controller from automatically disconnecting a target transaction due to
the PCI 16/8 clock rule. With this bit set, it is possible to hang the PCI bus if the internal bus does not
complete the data transfer.
10.4.6
Communication Sub-System Initiator Interface
This interface provides for high-speed, autonomous DMA transactions to PCI with the PCI Controller
operating as a standard Communication Sub-System peripheral. Full duplex operation is supported and
direct XL bus transactions can also be interleaved while CommBus transactions are in progress. Internal
arbitration will occur continuously to support transaction interleaving. (See Section 10.4.2, “Initiator
Arbitration.”) Multi-Channel DMA operation operates independently of the XL bus. Non-PCI transactions
on the XL bus will have 100% bandwidth available to them during PCI Multi-Channel DMA activities. In
general, this block will be used by functions in the Multi-Channel DMA API.
The Communication Sub-System Initiator Interface consists of Receive and Transmit FIFOs, integrated as
separate Multi-Channel DMA peripherals. Therefore, it is generally controlled by the Multi-Channel
DMA controller through a pre-described program loop. As with all Communication Sub-System
peripherals, it can be accessed and controlled directly through the Slave bus interface if desired, but this
path does not generally lend itself to high throughput.
The Transmit and Receive FIFOs are 512 bytes deep and support PCI bursts up to 8 beats, each beat being
a 32 bit word. The burst size is programmable. The general approach is to write a PCI command and
address to the control register along with the number of bytes to be transmitted (Packet_Size).
When transmitting data, the module will wait for the Transmit FIFO to fill at least to the minimum number
of bytes required to perform the programmed burst; then it begins transmitting the data onto the PCI bus.
Multi-Channel DMA must handle filling the Transmit FIFO to support the specified number of bytes.
Transmission will continue until the specified number of bytes have been sent.
When reading data, the module will check that enough space is available in the Receive FIFO and
immediately begin PCI read transactions. Multi-Channel DMA must handle emptying the Receive FIFO
to support the specified number of bytes. Transmission will continue until the specified number of bytes
have been received. To avoid stale data while receiving the last burst flushing of the RX FIFO can be
forced with the set of the flush bit FE. See Section 10.3.3.2.4, “Rx Enables PCIRER(RW).”
At this point, software must restart the procedure by at least re-writing the Packet_Size register. Each
transmission of the specified number of bytes is considered a “packet”. A new packet can be instructed to
continue at the last valid PCI address or software may choose to write a new starting address. The largest
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burst size is 8 PowerPC words and the largest Packet_Size is 4 Gbytes, so a packet will typically consist
of many PCI data bursts.
The Transmit Controller will wait until sufficient bytes are in the Transmit FIFO to support a full burst and
will continue in this mode until the entire packet is transmitted. Similarly, the Receive Controller will stall
until sufficient space is available in the Receive FIFO to support a full burst. If the packet is nearly done
and the number of bytes remaining to complete the packet is less than Max_beats, the remaining data will
be performed as single-beat PCI transactions.
10.4.6.1
Access Width
This Multi-Channel DMA module primarily performs 32-bit data accesses to and from PCI, even though
some signals are referred to in bytes. The two least significant bits of the PCITPSR and PCIRPSR value
are ignored. All PCI byte enables are enabled during these types of accesses. Additionally, the FIFOs
should only be accessed using 32-bit accesses.
The Communication Sub-System interface optionally supports 16 bit accesses on the PCI bus. Since reads
and writes to and from the FIFO require 32-bit accesses, using this option requires padding the remaining
16 bits of data.
10.4.6.2
Addressing
The Communication Sub-System Initiator interface does not use the addressing windows that are set up
for the XL bus Initiator Interface. Instead, the Tx Start Address register and Rx Start Address register are
used. Software programs these registers with the initial starting address for the packet. The module
contains an internal counter which will present the incremented PCI address at the beginning of each
successive burst for packet transfers.
10.4.6.3
Data Translation
The PCI bus is inherently little endian in its byte ordering. The Comm bus however is big endian.
Table 10-61 shows the byte lane mapping between the two buses. Since this interface only allows 32-bit
accesses, there is only one entry.
Table 10-61. Comm bus to PCI Byte Lanes for Memory1 Transactions
Comm bus
Transfer cAddress
[1:0]
long
1
00
PCI data bus
Data Bus
cByte
Enable
[3:0]
31:
24
23:
16
15:8
1111
OP0
OP1
OP2
Data Bus
7:0
PCI_
AD
[1:0]
BE
[3:0]
31:24
23:16
15:8
7:0
OP3
00
0000
OP3
OP2
OP1
OP0
The byte lane translation will be similar for other types of transactions. However, the PCI address may be different as
explained in Section 10.4.1.5, “Addressing.”
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10.4.6.4
Initialization
The following list is the recommended procedure for setting up either the Transmit or Receive controller.
1. Set the Start Address
2. Set the PCI command, Max_Retries, and Max_Beats
3. Set mode, Continuous or Non-continuous
4. Reset the FIFO
5. Set the FIFO Alarm and Granularity fields
6. Set the Master Enable bit (eventually enable the wanted interrupt in case of errors or even of a
normal termination)
7. Set the Reset Controller bit low
8. Setup the BestComm (eventually passing the parameters to the task if needed, enabling, if required,
the Task to interrupt the Core when finished, etc.)
9. Start the Task(s). It is not strictly necessary to start a PCI RX or TX task before starting the PCI to
transmit/receive as one will ‘wait’ for the other to fill the data in or out of the FIFO.
10. Write the Packet Size value to fire off the transfer
10.4.6.5
Restart and Reset
A Restart sequence (namely writing of the Packet Size register) is required whenever the controller ends
a packet transmission, either normally or abnormally. In non-continuous mode, a new Start_Add address
is generally required since this value is re-used as the start of the next packet once it is Restarted. In
Continuous mode, the Start_Add value is not reused. Instead, the next packet begins where the last one left
off, but a Restart sequence is still required to get this next packet started.
Writing a non-zero value to the Packet_Size register generates a Restart pulse to the controller. Depending
on the desired mode of operation other register accesses may be required, as described in the following
paragraphs.
If Continuous mode is not selected, operation is fairly straight forward. Upon packet termination, Restart
will not occur until Packet_Size is written with a non-zero value, even if the packet size is the same it must
be re-written. Master Enable bit was previously high and can remain so. Reset Controller bit was
previously low and can remain so. Toggling the Master Enable or Reset bit is unnecessary but would not
disrupt the transmit controller. If any other Control values, e.g. Start_Add, are to be changed they should
be written either prior to writing the Packet_Size value or written while the Master Enable bit is negated
and the Reset Controller bit is negated. The recommended approach is to write the control values in order
(Packet_Size must be last) and not toggle the Master Enable bit. The Reset bit should remain negated.
If Continuous mode is active, basic operation is still straight forward. A Restart is achieved by writing the
Packet_Size register to a non-zero value (just as before). However, the Master Enable and Reset bits must
not toggle in this case. If the Master Enable bit goes low the Packets_Done counter will be reset. If the
Reset bit goes high the Start_Add value will be re-loaded and subsequent transactions will begin at this
address. Therefore, the Master Enable bit can be used to reset the Packets_Done counter but without
disturbing the current PCI address. The Reset Controller bit will reset the counter and reload the Start_Add
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value into the transmit controller, thus achieving a total restart of a continuous mode sequence. In any
case, it is still required that the Packet_Size register be written to complete a Restart sequence.
The Master Enable bit, if negated, will prevent a Restart sequence but allows Control values to be updated
without order dependency. A side effect is to reset the Packets_Done counter and status, which is a concern
in continuous mode only.
The Reset bit (RC bit of the RX/TX Enables register, NOT the external PCI RESET line), if asserted, will
force a Reset of the controller. All continuous mode effects will be reset and the Start_Add value is
re-loaded. However, the Reset bit must be negated while the required write to the Packet_Size register is
accomplished. The Reset bit provides the only means to re-load the Start_Add value into the transmit
controller while Continuous mode is active. In either mode it provides a means to clear the transmit
controller in cases of abnormal termination. Note, a new Start_Add value must be written prior to setting
the Reset bit.
10.4.6.6
PCI Commands
The expected PCI commands are Memory Write for transmit and Memory Read for receive. These are
independent of cache or line size. This permits the number of data beats per transaction to be flexible. If
any requirements exist on number of data beats, then the software must carefully consider the possibilities.
If the Max_Beats setting does not divide properly into the Packet_Size setting then the packet will end up
with one or more single-beat transaction(s). Setting Max_Beats to 1 will force all transactions to be
single-beat but will affect throughput.
In normal operation, all PCI byte enables will be asserted for PCI transactions through this interface,
except if the 16-bit Word register bit is set in the Tx Transaction Control Register PCITTCR(RW) or Rx
Transaction Control Register PCIRTCR(RW), in which case BE[3:0] = 1100.
Configuration writes to an external target should be handled exclusively by the XL bus Initiator interface.
10.4.6.7
FIFO Considerations
Careful consideration must also be given to filling and counting bytes of the Transmit FIFO and emptying
and counting bytes of the Receive FIFO. This operation is expected to be accomplished through
Multi-Channel DMA which can also perform the register writes to the controller, including necessary
Restart sequences.
10.4.6.8
Alarms
The FIFO alarm registers allow software to control when the DMA fills or empties the appropriate FIFO.
10.4.6.9
Bus Errors
Since Bus Errors are particular to the module register set and that register set includes both Transmit and
Receive Controller and FIFO settings, the Bus Error status bits and Bus error Enable bit(s) are duplicated
in the Transmit and Receive register groupings. Clearing or setting one will clear or set the other. From a
software point of view, then, they can be treated separately or together, as desired.
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10.4.7
PCI - Supported Clock Ratios
MPC5200B supports the following XL Bus:IP:PCI clock ratios.
Table 10-62. XL Bus:IP:PCI Clock Ratios
10.4.8
XL Bus:IP:PCI
XL Bus
CLK
IP CLK
PCI CLK
4:4:2
132 MHz
132 MHz
66 MHz
4:4:1
132 MHz
132 MHz
33 MHz
4:2:2
132 MHz
66 MHz
66 MHz
4:2:1
132 MHz
66 MHz
33 MHz
2:2:2
66 MHz
66 MHz
66 MHz
2:2:1
66 MHz
66 MHz
33 MHz
2:1:1
66 MHz
33 MHz
33 MHz
Interrupts
10.4.8.1
PCI Bus Interrupts
MPC5200B does not generate interrupts on the PCI bus interrupt lines INTA - INTD.
10.4.8.2
Internal Interrupt
The PCI module is capable of generating 3 interrupts to MPC5200B interrupt controller in MPC5200B
SIU. Each interrupt can be enabled for a variety of conditions, mostly error conditions. For the XL bus
Initiator interface, the internal interrupt can be enabled for Retry errors, Target Aborts and Initiator
(Master) Aborts. See Section 10.3.2.9, “Initiator Control Register PCIICR(RW)” and Section 10.3.2.10,
“Initiator Status Register PCIISR(RWC)” for more information. For the Comm bus Initiator interface, an
internal interrupt can be enabled for FIFO errors and Normal Termination of a packet transfer for either
the Receive (rx) or Transmit (tx) interface. For more information, see the Enable and Status registers for
the Comm bus Transmit and Receive interfaces, Section 10.3.3.1, “Multi-Channel DMA Transmit
Interface” and Section 10.3.3.2, “Multi-Channel DMA Receive Interface.”
10.5
PCI Arbiter
The PCI Arbiter is a separate module, it is not part of the PCI Controller module. The 32-bit multiplexed
PCI A/D bus is shared with the ATA Controller and LocalPlus Controller. The on-chip arbiter (called PCI
Arbiter) controls the access to the AD bus for the different clients:
• PCI clients
— XIPCI (XL Bus-PCI interface)
— SCPCI (BestComm-PCI interface)
— external PCI
• non-PCI clients
— LPC (LocalPlus bus interface)
— SCLPC (BestComm LocalPlus bus interface)
— ATA
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One pair only of external PCI REQ#/GNT# signals is supported by the PCI Arbiter. By an external Priority
Encoder multiple external masters could be connected. The PCI bus clock is always sourced from the
MPC5200B.
The PCI Arbiter accepts inputs from the external PCI bus, XL bus, LocalPlus bus, and ATA. The
arbitration priority is fixed and it operates in a Round-Robin manner. The round-robin fairness algorithm
avoids the domination of the bus by high-priority masters and exclusion of low-priority masters.
The last PCI bus master to win arbitration is parked on the internal PCI bus until another master requests
the bus. For instance, if ATA was the last PCI bus requestor to be granted the bus, ATA does not have to
re-arbitrate for the bus if it is the next requestor.
NOTE
The XL bus arbitrator can be programmed to park the PCI module on the
XL bus. This should not be confused with the parking of the PCI requestors
on the internal PCI bus.
The PCI Arbiter runs independently. The programmability consists of a Soft Reset, which allows to reset
the PCI Arbiter, and one status bit to detect the Broken Master condition. and a corresponding enable bit
for the generation of a CPU interrupt for the Broken Master condition. All these register bits are located
in registers of the PCI Controller.
In case of broken master detection the external PCI REQ# will be disconnected internally and will be
re-connected after external deassertion of PCI REQ# or by software (Softreset) or by Hardreset. After
broken master detection (bus idle for 16 clocks) the arbiter will ignore any PCI FRAME# assertion.
The PCI Arbiter does not support preemption of the internal masters XIPCI or SCPCI. The internal master
is granted until the transaction has been completed. The Latency Timer (LT) cannot terminate any transfer.
10.6
Application Information
This section provides example usage of some of the features of the PCI module.
10.6.1
XL bus Initiated Transaction Mapping
The use of the PCI Configuration Address Register along with the initiator window registers provide many
possibilities for PCI command and address generation. Table 10-63 shows how the PCI Controller accepts
read and write requests from a XLB bus master and decodes them to different address ranges resulting in
the generation of memory, I/O, configuration, interrupt acknowledge and special cycles on the PCI bus.
The Window Registers are defined in Section 10.3.2.6, “Initiator Window 1 Base/Translation Address
Register PCIIW1BTAR(RW)” through Section 10.3.2.8, “Initiator Window Configuration Register
PCIIWCR(RW).”
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-81
PCI Controller
Table 10-63. Transaction Mapping: XL Bus -> PCI
Initiator Register Settings
XL bus Transaction
(XL Bus Slave Interface)
Cache Line Size
Register = 8
Initiator Window
Configuration bits
Configuration
Address
Register
IO/M#
PRC
En
device
number
==
b1_1111
PCI Transaction
Controller (XL Bus
Initiator Interface) ->
PCI Target
Single-Beat 1 -> 8 byte Read
x
0
b00
x
x
Memory Read
Burst Read (32 bytes)
x
0
b00
x
x
Memory Read
Single-Beat 1 -> 8 byte Read
x
0
b01
x
x
Memory Read
Burst Read
false
0
b01
x
x
Memory Read
Burst Read
true
0
b01
x
x
Memory Read Line
Single-Beat 1 -> 8 byte Read
x
0
b10
x
x
Memory Read Multiple
Burst Read
x
0
b10
x
x
Memory Read Multiple
Single-Beat 1 -> 8 byte, or Burst
Write
x
0
x
x
x
Memory Write
Single-Beat 1 -> 4 byte Read
x
1
x
0
x
I/O Read
Single-Beat 1 -> 4 byte Write
x
1
x
0
x
I/O Write
Single-Beat 1 -> 4 byte Read
x
1
x
1
false
Configuration Read
Single-Beat 1 -> 4 byte Write
x
1
x
1
false
Configuration Write
Single-Beat 1 -> 4 byte Read
x
1
x
1
true
Interrupt acknowledge
Single-Beat 1 -> 4 byte Write
x
1
x
1
true
Special Cycle
Note:
1. Dual Address Cycles and Memory Write and Invalidate Commands are not supported
2. x means “don’t care”
10.6.2
Address Maps
The address mapping in MPC5200B system is setup by software through a number of base address
registers. (Section 3.2, “Internal Register Memory Map” for more detail). The internal CPU writes the base
address value to module base address register MBAR. MBAR holds the base address for the 256 Kbyte
space allocated to internal registers.
10.6.2.1
10.6.2.1.1
Address Translation
Inbound Address Translation
The MPC5200B-as-Target occupies 2 memory target address windows on the PCI bus. The location is
determined by the values programmed to BAR0 and BAR1 of the PCI Type 00h Configuration space.
These inbound memory window sizes are fixed to one 256 Kbyte window (BAR0) and one 1 Gbyte
window (BAR1).
MPC5200B User’s Manual, Rev. 3
10-82
Freescale Semiconductor
PCI Controller
PCI inbound address translation allows address translation to any space in the MPC5200B space (4 Gbyte
of address space). The target base address translation registers TBATR0 and TBATR1 specify the location
of the inbound memory window. These registers are described in Section Section 10.4.3, Configuration
Interface. Address translation occurs for all enabled inbound transactions. If the enable bit of the Target
Base Address Translation Registers is cleared, MPC5200B aborts all PCI memory transactions to that base
address window.
Note, the PCI configuring master can program BAR0 to overlap BAR1. The default address translation
value is TBATR0 in that case. It is not recommended to program overlapping BAR0 and BAR1 or
overlapping TBATR0 and TBATR1. An overlap of TBATRs can cause data write-over of BAR0 data.
The Initiator Window Base Address Registers are used to decode XL bus addresses for PCI bus
transactions. The base address and base address mask values define the upper byte of address to decode.
The XL bus address space in MPC5200B dedicated to PCI transactions can be mapped to two 16-Mbyte
or larger address spaces in MPC5200B. In normal operation, software should not program either Target
Address Window Translation Register to address Initiator Window space. In that event,
MPC5200B-as-Target transaction would propagate through MPC5200B’s internal bus and request PCI bus
access as the PCI Initiator. The PCI arbiter could see the PCI bus as busy (target read transaction in
progress) and only a time-out would free the PCI bus.
MPC5200B
PCI Space (Memory View)
0
0
Inbound Translation
base address 0
Register Space
TBATR0 Address
Translation
1G
System Memory
1G
MPC5200B
BAR1
Not Recommended
Initiator
Window(s)
MPC5200B
memory
PCI Space
TBATR1 Address
Translation
Inbound Translation2G
base address 1
2G
MPC5200B
memory
Sdram Space
3G
3G
4G
4G
MPC5200B
BAR0
Figure 10-56. Inbound Address Map
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-83
PCI Controller
10.6.2.1.2
Outbound Address Translation
Figure 10-57 shows example XL Bus Initiator Window configurations. Overlapping the inbound memory
window (MPC5200B Memory) and the outbound translation window is not supported and can cause
unpredictable behavior.
This figure doesn’t show configuration mechanism.
0
MBAR
PCI Space (Memory View)
0
MPC5200B Space
Window 0
Translation
Window 0
XL Bus
Initiator
Windows
2G
Window 1
PCI Space (Configuration View)
0
Window 0
Register Space
1G
PCI Space (IO View)
0
1G
1G
1G
Not Recommended
Window 1
Translation
MPC5200B
memory
2G
2G
Window 1
2G
MPC5200B memory
Window 2
Not Recommended
Window 2
Translation
3G
3G
3G
3G
4G
4G
Window 2
4G
4G
Associated with PCI Prefetchable Memory
Associated with PCI I/O
Associated with PCI Non-Prefetchable Memory
Window 0 Base Address = 0x40
Window 0 Address Mask = 0x1F
Window 0 Translation Address = 0x00
Window 2 Base Address = 0x80
Window 2 Address Mask = 0x3F
Window 2 Translation Address = 0xC0
Window 1 Base Address = 0x70
Window 1 Address Mask = 0x0F
Window 1 Translation Address = 0x70
Figure 10-57. Outbound Address Map
MPC5200B User’s Manual, Rev. 3
10-84
Freescale Semiconductor
PCI Controller
10.6.2.1.3
Base Address Register Overview
Table 10-63 shows the available accessibility for all PCI associated base address and translation address
registers in MPC5200B.
Base Address
Register
Register Function
PCI Bus Configuration
Access
Processor
Access
Any XL bus Master
Access
BAR0
PCI Base Address Register 0
(256 Kbyte)
X
X
X
BAR1
PCI Base Address Register 1 (1
Gbyte)
X
X
X
TBATR0
Target Base Address
Translation Register 0
(256Kbyte)
X
X
TBATR1
Target Base Address
Translation Register 0 (1 Gbyte)
X
X
IMWBAR
Initiator Window
Base/Translation Address
Registers
X
X
10.6.3
XL bus Arbitration Priority
When the XL Bus Arbiter Master Priority Register (Section 16.2.1.1, “Arbiter Configuration Register
(R/W)”) is set to any configuration except all-master fair-share (all masters have the same priority), live
lock can occur on the shared PCI bus and the XL Bus, which results in system-wide live lock.
The only resolution that guarantees that this live lock scenario will not occur is to set all the XL Bus Arbiter
master priorities to be equal. Additionally, it is usually preferable that all master priorities are not set to
zero, as this can generate an interrupt by the XL Bus Arbiter, if enabled.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
10-85
PCI Controller
MPC5200B User’s Manual, Rev. 3
10-86
Freescale Semiconductor
Chapter 11
ATA Controller
11.1
Overview
The following sections are contained in this document:
• BestComm Key Features
— ATA Register Interface, includes:
— ATA Host Registers
— ATA FIFO Registers
— ATA Drive Registers
• ATA Host Controller Operation
• Signals and Connections
• ATA Interface Description
• ATA Bus Background
• ATA RESET/Power-Up
• ATA I/O Cable Specifications
The Advanced Technology Attachment (ATA) Controller provides full functional compatibility with
ATA-4 documentation, supporting Ultra-33. For more ATA Standards information, refer to American
National Standard for Information Technology—AT Attachment with Packet Interface Extension
(ATA/ATAPI-4).
A dedicated MPC5200B pin for ATA reset is not provided. An appropriate signal on the board should be
routed to the reset input on the ATA connector. If ATA reset is tied to HRESET or SRESET on MPC5200B
pins, they are asserted and internally held low for an appropriate period of time to satisfy ATA reset. An
MPC5200B GPIO may be used to drive ATA reset independently if special software control is needed.
Figure 11-1 shows the ATA Controller Interface.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-1
ATA Controller
PCI Handshake
ATA Host
Controller
Ultra DMA
Channel
BestComm
(higher priority)
IP bus
Rx/Tx FIFO
Interface
Multiword
DMA
Channel
ARB
IPBI
IPBI
Program
Registers
(Host/Driver)
Local Bus
PIO
Channel
Figure 11-1. ATA Controller Interface
11.2
11.2.1
BestComm Key Features
BestComm Read
1. microprocessor sets up descriptors in BestComm RAM and initiates a transfer.
2. BestComm hits on an ATA command FIFO space and writes a command (ATA drive register
address, transfer size) into FIFO.
3. ATA Controller reads data from the drive and puts data in FIFO.
4. As FIFO fills, BestComm is interrupted and moves data from FIFO to an internal destination.
11.2.2
BestComm Write
1. microprocessor sets up descriptors in BestComm RAM and initiates a transfer.
2. BestComm hits on an ATA command FIFO space and writes a command (ATA drive register
address, transfer size) into FIFO.
3. BestComm reads data from internal source and puts data in FIFO
4. ATA Controller transfers data from FIFO and writes to drive.
NOTE
Any DMA transfer, where source and destination are both on the local bus,
requires internal BestComm SRAM buffering.
MPC5200B User’s Manual, Rev. 3
11-2
Freescale Semiconductor
ATA Controller
11.3
ATA Register Interface
The IPBI module contains all software-programmable ATA Controller registers and the IPB glue logic
needed to read and write these registers. The IPBI registers are listed below. Unless otherwise noted, each
register is written and read from the same address.
11.3.1
ATA Host Registers
ATA is controlled by 10 32-bit registers. These registers are located at an offset from MBAR of 0x3A00.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x3A00 +
register address
Hyperlinks to the ATA Host registers are provided below:
• ATA Host Configuration Register (0x3A00)
• ATA Host Status Register (0x3A04)
• ATA PIO Timing 1 Register (0x3A08)
• ATA PIO Timing 2 Register (0x3A0C)
• ATA Multiword DMA Timing 1 Register (0x3A10)
• ATA Multiword DMA Timing 2 Register (0x3A14)
• ATA Ultra DMA Timing 1 Register (0x3A18)
• ATA Ultra DMA Timing 2 Register (0x3A1C)
• ATA Ultra DMA Timing 3 Register (0x3A20)
• ATA Ultra DMA Timing 4 Register (0x3A24)
• ATA Ultra DMA Timing 5 Register (0x3A28)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-3
ATA Controller
11.3.1.1
ATA Host Configuration Register
Address MBAR + 0x3A00
R
W
Reset
0
1
2
3
4
SMR
FR
0
0
0
0
0
16
17
18
19
20
5
6
7
IE
IORDY
0
0
0
0
0
0
0
21
22
23
24
25
26
0
0
Reserved
R
9
10
11
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
Reserved
Reserved
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 11-2. ATA Host Configuration Register
Table 11-1. ATA Host Configuration Register Field Descriptions
Bits
Name
Description
0
SMR
1
FR
FIFO Reset—bit can be used to reset FIFO when bit 0 of this register is set to reset the ATA state
machine. During normal ATA transaction, FIFO can be reset by setting ATA Drive Command
Register FR bit (see Table 11-30.)
2:5
—
Reserved
6
IE
Enables drive interrupt to pass to CPU in PIO modes.
7
IORDY
16:31
—
State Machine Reset—bit resets ATA state machine to IDLE state for PIO, DMA and UDMA
read/write.
Set by software when the drive supports IORDY. Required for PIO mode 3 and above.
Reserved
MPC5200B User’s Manual, Rev. 3
11-4
Freescale Semiconductor
ATA Controller
11.3.1.2
ATA Host Status Register
Address MBAR + 0x3A04
R
W
Reset
0
1
2
3
4
5
TIP
UREP
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
0
Reserved
6
8
9
10
RERR WERR
R
11
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
Reserved
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
Figure 11-3. ATA Host Status Register
Table 11-2. ATA Host Status Register Field Descriptions
Bits
Name
Description
0
TIP
Transaction in Progress—indicator bit MUST be polled by software before PIO access. System bus
(XL bus) locks up if PIO access is attempted while this bit is set. This bit is read-only.
1
UREP
UDMA Read Extended Pause—bit sets when drive stops strobing for an extended period without
initiating burst termination by negating DMARQ, during an UDMA read burst. Software may initiate
an Ultra DMA read burst termination, in this case by setting ATA Drive Device Command Register
HUT bit (see Table 11-30.).
2:5
—
6
RERR
Read Error—An un-implemented register read.
7
WERR
Write Error—An un-implemented register write.
8:31
—
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-5
ATA Controller
11.3.1.3
ATA PIO Timing 1 Register
Address MBAR + 0x3A08
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
pio_t2_8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
pio_t2_16
W
Reset
4
pio_t0
W
Reset
3
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
Figure 11-4. ATA PIO Timing 1 Register
Table 11-3. ATA PIO Timing 1 Register Field Descriptions
Bits
Name
0:7
pio_t0
8:15
pio_t2_8
PIO read/write pulse width for 8-bit transfers. Count value is based on system clock operating
frequency.
16:23
pio_t2_16
PIO read/write pulse width for 16-bit transfers. Count value is based on system clock operating
frequency.
24:31
—
11.3.1.4
Description
PIO cycle time count value is based on system clock operating frequency.
Reserved
ATA PIO Timing 2 Register
Address MBAR + 0x3A0C
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
pio_t1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
pio_ta
W
Reset
4
pio_t4
W
Reset
3
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
Figure 11-5. ATA PIO Timing 2 Register
Table 11-4. ATA PIO Timing 2 Register Field Descriptions
Bits
Name
Description
0:7
pio_t4
PIO write (DIOW) data hold time. Count value is based on system clock operating frequency.
8:15
pio_t1
Address valid to DIOR/DIOW setup. Count value is based on system clock operating frequency.
16:23
pio_ta
IORDY setup time. Count value is based on system clock operating frequency.
24:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
11-6
Freescale Semiconductor
ATA Controller
11.3.1.5
ATA Multiword DMA Timing 1 Register
Address MBAR + 0x3A10
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
dma_td
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
dma_tk
W
Reset
4
dma_t0
W
Reset
3
0
0
0
0
dma_tm
0
0
0
0
0
0
0
0
0
Figure 11-6. ATA Multiword DMA Timing 1 Register
Table 11-5. ATA Multiword DMA Timing 1 Register Field Descriptions
Bits
Name
Description
0:7
dma_t0
Multiword DMA cycle time. Count value is based on system clock operating frequency.
8:15
dma_td
Multiword DMA read/write (DIOR/DIOW) asserted pulse width. Count value is based on system
clock operating frequency.
16:23
dma_tk
Multiword DMA read/write (DIOR/DIOW) negated pulse width. Count value is based on system
clock operating frequency.
24:31
dma_tm
CS[0], CS[1] valid to DIOR/DIOW. Count value is based on system clock operating frequency.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-7
ATA Controller
11.3.1.6
ATA Multiword DMA Timing 2 Register
Address MBAR + 0x3A14
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
dma_tj
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
dma_tn
W
Reset
4
dma_th
W
Reset
3
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
Figure 11-7. ATA Multiword DMA Timing 2 Register
Table 11-6. ATA Multiword DMA Timing 2 Register Field Descriptions
Bits
Name
Description
0:7
dma_th
Multiword DMA write (DIOW) data hold time. Count value is based on system clock operating
frequency.
8:15
dma_tj
Multiword DMA read/write (DIOR/DIOW) asserted pulse width. Count value is based on system
clock operating frequency.
16:23
dma_tn
CS[0], CS[1] hold. Count value is based on system clock operating frequency.
24:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
11-8
Freescale Semiconductor
ATA Controller
11.3.1.7
ATA Ultra DMA Timing 1 Register
Address MBAR + 0x3A18
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
udma_tcyc
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
udma_tds
W
Reset
4
udma_t2cyc
W
Reset
3
0
0
0
0
0
udma_tdh
0
0
0
0
0
0
0
0
Figure 11-8. ATA Ultra DMA Timing 1 Register
Table 11-7. ATA Ultra DMA Timing 1 Register Field Descriptions
Bits
Name
Description
0:7
udma_t2cyc
Ultra DMA sustained average two cycle time. Count value is based on system clock operating
frequency.
8:15
udma_tcyc
Ultra DMA strobe edge to strobe edge cycle time. Count value is based on system clock operating
frequency.
16:23
udma_tds
Ultra DMA read data setup time. Count value is based on system clock operating frequency.
24:31
udma_tdh
Ultra DMA read data hold time. Count value is based on system clock operating frequency.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-9
ATA Controller
11.3.1.8
ATA Ultra DMA Timing 2 Register
Address MBAR + 0x3A1C
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
udma_tdvh
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
udma_tfs
W
Reset
4
udma_tdvs
W
Reset
3
0
0
0
0
0
udma_tli
0
0
0
0
0
0
0
0
Figure 11-9. ATA Ultra DMA Timing 2 Register
Table 11-8. ATA Ultra DMA Timing 2 Register Field Descriptions
Bits
Name
Description
0:7
udma_tdvs
Ultra DMA write data setup time. Count value is based on system clock operating frequency.
8:15
udma_tdvh
Ultra DMA write data hold time. Count value is based on system clock operating frequency.
16:23
udma_tfs
First strobe time during the initiation of ultra DMA data transfer. Count value is based on system
clock operating frequency.
24:31
udma_tli
Limited interlock time with a defined maximum, when drive or host are waiting for response from
each other. Count value is based on system clock operating frequency.
MPC5200B User’s Manual, Rev. 3
11-10
Freescale Semiconductor
ATA Controller
11.3.1.9
ATA Ultra DMA Timing 3 Register
Address MBAR + 0x3A20
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
udma_taz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
udma_tenv
W
Reset
4
udma_tmli
W
Reset
3
0
0
0
0
0
udma_tsri
0
0
0
0
0
0
0
0
Figure 11-10. ATA Ultra DMA Timing 3 Register
Table 11-9. ATA Ultra DMA Timing 3 Register Field Descriptions
Bits
Name
Description
0:7
udma_tmli
Limited interlock time with a defined minimum, when drive or host are waiting for response from
each other. Count value is based on system clock operating frequency.
8:15
udma_taz
Maximum time allowed for output drivers to release from being driven. Count value is based on
system clock operating frequency.
16:23
udma_tenv
Envelope time from DMACK to STOP and HDMARDY during data-out burst initiation. Count value
is based on system clock operating frequency.
24:31
udma_tsr
Strobe to DMARDY time. If DMARDY is negated before this long after strobe edge the recipient
receives no more than one additional data word. Count value is based on system clock operating
frequency.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-11
ATA Controller
11.3.1.10 ATA Ultra DMA Timing 4 Register
Address MBAR + 0x3A24
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
udma_trfs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
udma_trp
W
Reset
4
udma_tss
W
Reset
3
0
0
0
0
0
udma_tac
0
0
0
0
0
0
0
0
Figure 11-11. ATA Ultra DMA Timing 4 Register
Table 11-10. ATA Ultra DMA Timing 4 Register Field Descriptions
Bits
Name
Description
0:7
udma_tss
Time from strobe edge to negation of DMARQ (when drive terminates burst) or assertion of STOP
(when host terminates burst). Count value is based on system clock operating frequency.
8:15
udma_trfs
Ready-to-final-strobe time. No strobe edges are sent this long after negation of DMARDY. Count
value is based on system clock operating frequency.
16:23
udma_trp
Ready-to-pause time. The time that recipient waits to initiate pause after negating DMARDY.
Count value is based on system clock operating frequency.
24:31
udma_tack
Setup and hold times for DMACK before negation or assertion. Count value is based on system
clock operating frequency.
MPC5200B User’s Manual, Rev. 3
11-12
Freescale Semiconductor
ATA Controller
11.3.1.11 ATA Ultra DMA Timing 5 Register
Address MBAR + 0x3A28
0
1
2
R
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
udma_tzah
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-12. ATA Ultra DMA Timing 5 Register
Table 11-11. ATA Ultra DMA Timing 5 Register Field Descriptions
Bits
Name
Description
0:7
udma_tzah
Minimum delay time required for output drivers to assert or negate from release state. Count value
is based on system clock operating frequency.
8:31
—
Reserved
11.3.1.12 ATA Share Count Register
Address MBAR + 0x3A2C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
8
ata_share_cnt
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 11-13. ATA Share Count Register
Table 11-12. ATA Share Count Register Field Descriptions
Bits
Name
0:15
ata_share_cnt
16:31
—
Description
This 16-bit value controls the length of the “time slot” assigned to ATA transactions when PCI
arbiter provides a grant to the ATA device. This is in IPB clocks. The arbiter will maintain the grant
to ATA for (at least) the ata_share_cnt value. When this value has expired, ATA may be
interrupted (paused) by the arbiter, to service other pending requests for the AD bus.
Default value at reset is 128
Note: The maximal allowed setting is 0xFFFE.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-13
ATA Controller
11.3.2
ATA FIFO Registers
ATA uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction
change and flushes FIFO before changing directions. FIFO memory is 512Bytes (Four 8 x 128 memories).
ATA FIFO is controlled by 32-bit registers. These registers are located at an offset from MBAR of 0x3a00.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x3A00
+ register address
Hyperlinks to the ATA FIFO registers are provided below:
• ATA Rx/Tx FIFO Data Word Register (0x3A3C)
• ATA Rx/Tx FIFO Status Register (0x3A40)
• ATA Rx/Tx FIFO Control Register (0x3A44)
• ATA Rx/Tx FIFO Alarm Register (0x3A48)
• ATA Rx/Tx FIFO Read Pointer Register (0x3A4C)
• ATA Rx/Tx FIFO Write Pointer Register (0x3A50)
11.3.2.1
ATA Rx/Tx FIFO Data Word Register
Address MBAR + 0x3A3C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
R
FIFO_Data_Word
W
Reset
8
FIFO_Data_Word
W
Reset
7
0
0
0
0
0
0
0
0
0
0
Figure 11-14. ATA Rx/Tx FIFO Data Word Register
Table 11-13. ATA Rx/Tx FIFO Data Word Register Field Descriptions
Bits
Name
Description
0:31
FIFO_Data_Word
The FIFO data port. Reading from this location “pops” data from the FIFO, writing “pushes”
data into the FIFO. During normal operation the BestComm Controller pushes data here.
Note: ONLY full long-word access is allowed. If all byte enables are not asserted when
accessing this location, a FIFO error flag is generated.
MPC5200B User’s Manual, Rev. 3
11-14
Freescale Semiconductor
ATA Controller
11.3.2.2
ATA Rx/Tx FIFO Status Register
Address MBAR + 0x3A40
0
1
2
3
R
5
6
8
9
10
11
12
13
14
15
Err
UF
OF
Full
HI
LO
Emty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Reserved
W
Reset
4
0
0
0
0
0
0
0
0
0
Figure 11-15. ATA Rx/Tx FIFO Status Register
Table 11-14. ATA Rx/Tx FIFO Status Register Field Descriptions
Bits
Name
Description
0:8
—
Reserved
9
Err
Error—flag bit is essentially the logical OR of other flag bits and can be polled for detection of any
FIFO error. After clearing the offending condition, writing 1 to this bit clears flag.
10
UF
UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read beyond
empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
11
OF
OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
12
Full
FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
13
HI
High—FIFO requests attention, because high level alarm is asserted. To clear this condition, FIFO
must be read to a level below the setting in granularity bits.
14
LO
Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition, FIFO
must be written to a level in which the space remaining is less than the granularity bit setting.
15
Emty
16:31
—
FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-15
ATA Controller
11.3.2.3
ATA Rx/Tx FIFO Control Register
Address MBAR + 0x3A44
0
R
W
Reset
1
Reserved
2
3
WFR
4
5
Reserved
6
8
9
10
GR
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 11-16. ATA Rx/Tx FIFO Control Register
Table 11-15. ATA Rx/Tx FIFO Control Register Field Descriptions
Bits
Name
Description
0:1
—
2
WFR
3:4
—
Reserved
5:7
GR
Granularity—bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.
000 = FIFO waits to become completely full before stopping data request.
Reserved
Write End of Frame (EOF) This bit should remain low.
001 = FIFO stops data request when only one long word of space remains.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
11-16
Freescale Semiconductor
ATA Controller
11.3.2.4
ATA Rx/Tx FIFO Alarm Register
Address MBAR + 0x3A48
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
Alarm
0
0
0
0
0
0
0
0
Figure 11-17. ATA Rx/Tx FIFO Alarm Register
Table 11-16. ATA Rx/Tx FIFO Alarm Register Field Descriptions
Bits
Name
0:19
—
20:31
Alarm
11.3.2.5
Description
Reserved
User writes these bits to set low level “watermark”, which is the point where FIFO asserts request
for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32, alarm condition
occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not negate until high level
mark is reached, as specified by FIFO control register granularity bits.
ATA Rx/Tx FIFO Read Pointer Register
Address MBAR + 0x3A4C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
ReadPtr
0
0
0
0
0
0
0
0
Figure 11-18. ATA Rx/Tx FIFO Read Pointer Register
Table 11-17. ATA Rx/Tx FIFO Read Pointer Register Field Descriptions
Bits
Name
0:19
—
20:31
ReadPtr
Description
Reserved
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. Value represents the Read address presented to the
FIFO RAM.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-17
ATA Controller
11.3.2.6
ATA Rx/Tx FIFO Write Pointer Register
Address MBAR + 0x3A50
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
WritePtr
0
0
0
0
0
0
0
0
Figure 11-19. ATA Rx/Tx FIFO Write Pointer Register
Table 11-18. ATA Rx/Tx FIFO Write Pointer Register Field Descriptions
Bits
Name
0:19
—
20:31
WritePtr
Description
Reserved
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special
cases, but this disrupts data flow integrity. Value represents the Read address presented to the
FIFO RAM.
MPC5200B User’s Manual, Rev. 3
11-18
Freescale Semiconductor
ATA Controller
11.3.3
ATA Drive Registers
The ATA drive registers are physically located inside the drive controller on the ATA disk drive. The
MPC5200B ATA Host Controller provides access to these registers using the chip selects and address bits.
ATA Drive is controlled by 32-bit registers. These registers are located at an offset from MBAR of
0x3A00. Register addresses are relative to this offset. Therefore, the actual register address is: MBAR +
0x3A00 + register address
Hyperlinks to the ATA Drive registers are provided below:
• ATA Drive Device Control Register (0x3A5C), write-only
• ATA Drive Alternate Status Register (0x3A5C), read-only
• ATA Drive Data Register (0x3A60), R/W
• ATA Drive Features Register (0x3A64), write-only
• ATA Drive Error Register (0x3A64), read-only
• ATA Drive Sector Count Register (0x3A68), R/W
• ATA Drive Sector Number Register (0x3A6C), R/W
• ATA Drive Cylinder Low Register (0x3A70), R/W
• ATA Drive Cylinder High Register (0x3A74), R/W
• ATA Drive Device/Head Register (0x3A78), R/W
• ATA Drive Device Command Register (0x3A7C), write-only
• ATA Drive Device Status Register (0x3A7C), read-only
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-19
ATA Controller
11.3.3.1
ATA Drive Device Control Register
Address MBAR + 0x3A5C
0
1
R
3
4
Reserved
W
Reset
2
5
6
8
9
10
11
12
13
14
15
Reserved
SRST nIEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 11-20. ATA Drive Device Control Register
Table 11-19. ATA Drive Device Control Register Field Descriptions
Bits
Name
Description
0:4
—
5
SRST
Software Reset—Host controlled software reset bit. Drive executes software reset protocol when bit
is set to 1 by host.
6
nIEN
Interrupt Enable—Host controlled interrupt enable. INTRQ is enabled when this bit is cleared to 0.
Note: For MPC5200B ATA Host Controller, enabling INTRQ is mandatory for DMA/UDMA data
transfer modes.
7:31
—
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
11-20
Freescale Semiconductor
ATA Controller
11.3.3.2
ATA Drive Alternate Status Register
Address MBAR + 0x3A5C
R
0
1
BSY
DRDY
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
W
Reset
2
3
4
5
DRQ
Reserved
6
Rsvd
R
8
9
10
11
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
13
14
15
Reserved
Reserved
W
Reset
7
ERR
0
0
0
0
0
0
0
0
0
Figure 11-21. ATA Drive Alternate Status Register
Table 11-20. ATA Drive Alternate Status Register Field Descriptions
Bits
Name
0
BSY
1
DRDY
2:3
—
4
DRQ
5:6
—
7
ERR
8:31
—
11.3.3.3
Description
Drive Busy—Transactions internal to drive are in progress. Host must wait.
Drive Ready
Reserved
Set to 1 indicates drive is ready to transfer a word of data.
Reserved
Indicates an error during the execution of the previous command.
Reserved
ATA Drive Data Register
Address MBAR + 0x3A60
0
1
2
R
4
5
6
8
9
10
11
12
Data L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Data H
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-22. ATA Drive Data Register
Table 11-21. ATA Drive Data Register Field Descriptions
Bits
Name
Description
0:7
Data H
Upper byte of drive data (read/write)
8:15
Data L
Lower byte of drive data (read/write)
16:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-21
ATA Controller
11.3.3.4
ATA Drive Features Register
Address MBAR + 0x3A64
0
1
2
3
4
5
6
7
8
9
10
R
W
Reset
12
13
14
15
Reserved
Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
11
0
0
0
0
0
0
0
0
0
Figure 11-23. ATA Drive Features Register
Table 11-22. ATA Drive Features Register Field Descriptions
Bits
Name
0:7
Data
8:31
—
Description
Register content is command dependent. Contents become command parameters when the ATA
drive command register is written.
Reserved
MPC5200B User’s Manual, Rev. 3
11-22
Freescale Semiconductor
ATA Controller
11.3.3.5
ATA Drive Error Register
Address MBAR + 0x3A64
0
1
R
2
3
4
Data
5
6
ABRT
7
8
9
10
Data
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
12
Reserved
W
Reset
11
0
0
0
0
0
0
0
0
0
Figure 11-24. ATA Drive Error Register
Table 11-23. ATA Drive Error Register Field Descriptions
Bits
Name
Description
0:4
Data
Register content is command dependent. Contents become command parameters when the ATA
drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the ATA drive
status register. Register content is not valid when drive is in sleep mode.
5
ABRT
Bit is set to 1 to indicate requested command has been aborted, because command code or a
command parameter is invalid or some other error occurred.
0:7
Data
Register content is command dependent. Contents become command parameters when the ATA
drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the ATA drive
status register. Register content is not valid when drive is in sleep mode.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-23
ATA Controller
11.3.3.6
ATA Drive Sector Count Register
Address MBAR + 0x3A68
0
1
2
R
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Data
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-25. ATA Drive Sector Count Register
Table 11-24. ATA Drive Sector Count Register Field Descriptions
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most read/write commands, this register indicates the total
number of sectors requested for transfer.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and DMACK is
not asserted. If register is written when BSY and DRQ bits are set to 1, the result is indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
11.3.3.7
Reserved
ATA Drive Sector Number Register
Address MBAR + 0x3A6C
0
1
2
R
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Data
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-26. ATA Drive Sector Number Register
Table 11-25. ATA Drive Sector Number Register Field Descriptions
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most commands, this register indicates the data transfer
starting sector number for when CHS addressing is enabled. This register indicates part of the LBA
address when the LBA addressing is enabled.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and DMACK is
not asserted. If register is written when BSY and DRQ bits are set to 1, the result is indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
11-24
Freescale Semiconductor
ATA Controller
11.3.3.8
ATA Drive Cylinder Low Register
Address MBAR + 0x3A70
0
1
2
R
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Data
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-27. ATA Drive Cylinder Low Register
Table 11-26. ATA Drive Cylinder Low Register Field Descriptions
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most commands, this register indicates the data transfer
starting sector number for when CHS addressing is enabled. This register indicates part of the LBA
address when the LBA addressing is enabled.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and DMACK is
not asserted. If this register is written when BSY and DRQ bits are set to 1, the result is
indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-25
ATA Controller
11.3.3.9
ATA Drive Cylinder High Register
Address MBAR + 0x3A74
0
1
2
R
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
Data
W
Reset
3
0
0
0
0
0
0
0
0
0
Figure 11-28. ATA Drive Cylinder High Register
Table 11-27. ATA Drive Cylinder High Register Field Descriptions
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most commands, this register indicates the data transfer
starting sector number for when CHS addressing is enabled. This register indicates part of the LBA
address when the LBA addressing is enabled.
This register is written only when ATA drive status register bits BSY and DRQ equal 0 and DMACK
is not asserted. If this register is written when BSY and DRQ bits are set to 1, the result is
indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
11-26
Freescale Semiconductor
ATA Controller
11.3.3.10 ATA Drive Device/Head Register
Address MBAR + 0x3A78
0
R
W
Reset
1
Rsvd
2
3
4
5
Data Rsvd DEV
6
7
9
10
11
Data
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 11-29. ATA Drive Device/Head Register
Table 11-28. ATA Drive Device/Head Register Field Descriptions
Bits
Name
Description
0
—
1
Data
2
—
Reserved
3
—
Reserved
4:7
Data
8:31
—
Reserved
Bit is command dependent. In LBA addressing mode, this bit is set to 1 to indicate LBA addressing
is chosen for data transfer.
Bit content is command dependent. For most commands, this register indicates the data transfer
starting sector number for when CHS addressing is enabled. This register indicates part of the LBA
address when the LBA addressing is enabled.
This register is written only when ATA drive status register bits BSY and DRQ equal 0 and DMACK
is not asserted. If this register is written when BSY and DRQ bits are set to 1, the result is
indeterminate.
Register content is not valid when drive is in sleep mode.
Reserved
11.3.3.11 ATA Drive Device Command Register
Address MBAR + 0x3A7C
0
1
2
3
4
5
6
7
R
W
Reset
Data
9
10
11
12
Rsvd
HUT
FR
FE
IE
13
14
UDMA READ
15
WRITE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 11-30. ATA Drive Device Command Register
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-27
ATA Controller
Table 11-29. ATA Drive Device Command Register Field Descriptions
Bits
Name
Description
0:7
Data
8
—
9
HUT
Host UDMA burst Terminate—Software can terminate UDMA burst prematurely by setting this bit.
Bits 15 through 10 are unaffected and retain previous values.
10
FR
FIFO Reset—Hardware resets FIFO when the direction is switched from Tx to Rx. No hardware
reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling it for Tx. When
bit 10 is set, FIFO is being reset and bits 15, 14, 13, 12, 11, 9 and 8 are invalid.
11
FE
Enable FIFO flush in Rx mode—For all commands except DEVICE RESET, this register is written
only when the ATA drive status register bits BSY and DRQ equal 0 and DMACK is not asserted. If
this register is written when BSY or DRQ bits are set to 1, the result is indeterminate except for the
DEVICE RESET command.
Register content is not valid when drive is in sleep mode.
12
IE
Enables drive interrupt to pass to CPU in DMA/UDMA modes. Software writes to this register as
follows:
• FE (bit 11) and IE (bit 12)
• Clear IE and set FE if SDMA task loop count is the same as the data transfer requested from the
drive.
The following is a typical sequence if the BestComm task loop is a larger count than data request
programmed for the drive:
1. Start transaction with IE set and FE cleared.
2. Repeat until task loop count expires.
3. Start last transaction with IE clear and FE set.
• Controller issues flush at end.
• Task loop completes and interrupts CPU.
• CPU responds to SDMA interrupt instead of drive interrupt.
• UDMA (bit 13)—Set when UDMA protocol is selected for data transfer, cleared for DMA protocol.
• READ (bit 14)—Set when read command for DMA/UDMA protocols is written to drive command
register, cleared otherwise.
• WRITE (bit 15)—Set when write command for DMA/UDMA protocols is written to drive
command register, cleared otherwise.
MANDATORY—Be Aware: Drive interrupt must be enabled by clearing bit 1 of drive control register
for DMA/UDMA mode transfers.
13
UDAMA
14
READ
Bit is set when READ DMA command is issued.
15
WRITE
Bit is set when WRITE DMA command is issued.
16:31
—
Register contains the command code sent to the drive. When this register is written, command
execution begins immediately. Writing this register clears any pending interrupt condition.
Reserved
Bit is set when UDMA protocol is selected, cleared when multiword DMA protocol is selected.
Reserved
MPC5200B User’s Manual, Rev. 3
11-28
Freescale Semiconductor
ATA Controller
11.3.3.12 ATA Drive Device Status Register
Address MBAR + 0x3A7C
R
0
1
BSY
DRDY
2
3
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
Data
4
DRQ
W
Reset
5
6
Reserved
7
R
9
10
11
12
13
14
15
FR
FE
IE
UDMA
Read
Write
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Rsvd HUT
Reserved
W
Reset
8
ERR
0
0
0
0
0
0
0
0
0
Figure 11-31. ATA Drive Device Status Register
Table 11-30. ATA Drive Device Status Register Field Descriptions
Bits
Name
Description
0
BSY
1
DRDY
2:3
Data
Command dependent—Register is written only when ATA drive status register bits BSY and DRQ
equal 0 and DMACK is not asserted. If this register is written when BSY and DRQ bits are set to 1,
the result is indeterminate.
Register content is not valid when drive is in sleep mode.
4
DRQ
Indicates drive is ready to transfer a data word.
5:6
—
7
ERR
8
—
9
HUT
Host UDMA burst Terminate—Software can terminate UDMA burst prematurely by setting this bit.
Bits 15 through 10 are unaffected and retain previous values.
10
FR
FIFO Reset—Hardware resets FIFO when the direction is switched from Tx to Rx. No hardware
reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling it for Tx. When
bit 10 is set, FIFO is being reset and bits 15, 14, 13, 12, 11, 9 and 8 are invalid.
11
FE
Enable FIFO flush in Rx mode—For all commands except DEVICE RESET, this register is written
only when the ATA drive status register bits BSY and DRQ equal 0 and DMACK is not asserted. If
this register is written when BSY or DRQ bits are set to 1, the result is indeterminate except for the
DEVICE RESET command.
Register content is not valid when drive is in sleep mode.
Indicates drive is busy processing a command.
Indicates drive is ready to accept executable commands.
Reserved
Set to 1 indicates ATA drive error register bits are valid.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-29
ATA Controller
Table 11-30. ATA Drive Device Status Register Field Descriptions (continued)
Bits
Name
Description
12
IE
Enables drive interrupt to pass to CPU in DMA/UDMA modes. Software writes to this register as
follows:
• FE (bit 11) and IE (bit 12)
• Clear IE and set FE if SDMA task loop count is the same as the data transfer requested from the
drive.
The following is a typical sequence if the SDMA task loop is a larger count than data request
programmed for the drive:
1. Start transaction with IE set and FE cleared.
2. Repeat until task loop count expires.
3. Start last transaction with IE clear and FE set.
• Controller issues flush at end.
• Task loop completes and interrupts CPU.
• CPU responds to BestComm interrupt instead of drive interrupt.
• UDMA (bit 13)—Set when UDMA protocol is selected for data transfer, cleared for DMA protocol.
• READ (bit 14)—Set when read command for DMA/UDMA protocols is written to drive command
register, cleared otherwise.
• WRITE (bit 15)—Set when write command for DMA/UDMA protocols is written to drive
command register, cleared otherwise.
MANDATORY—Be Aware: Drive interrupt must be enabled by clearing bit 1 of drive control register
for DMA/UDMA mode transfers.
13
UDAMA
14
READ
Bit is set when READ DMA command is issued.
15
WRITE
Bit is set when WRITE DMA command is issued.
16:31
—
Bit is set when UDMA protocol is selected, cleared when multiword DMA protocol is selected.
Reserved
MPC5200B User’s Manual, Rev. 3
11-30
Freescale Semiconductor
ATA Controller
11.4
ATA Host Controller Operation
With the asynchronous ATA interface, an interface must be implemented that meets the timing
specifications, given an input clock from the processor that is not fixed among all applications. The
challenge is to meet the minimum ATA specifications while minimizing wasted time. Time is wasted
because of differences between the minimum specification and the number of clock-cycles, multiplied by
the clock-cycle period. This indicates the counter compare value depends on:
• The data transfer mode
• The clock frequency driving the ATA state machine (IPB clock)
• The minimum data transfer mode cycle-time passed in the INDENTIFY block from the drive to
the ATA Host Controller
Software requirements for setting up the Host Controller are as follows:
1. Write into ata_config register to enable (ata_config[7] == 1) support for IORDY for PIO modes
3 and 4.
2. Software determines ATA mode timing based on the operating clock frequency
ATA_mode_timing_spec + ipbi_clock_period – 1
Count = ------------------------------------------------------------------------------------------------------------------------------clock_period
This rounds up to the smallest integer number of clock counts that meet the minimum specification.
In the case of counters that control duration of a read strobe (pio_t2_8, pio_t2_16 and dma_td), the
added transceiver propagation delay must be taken into account so the read data meets setup time
to the rising edge of the strobe. Therefore:
ATA_mode_timing_spec + 2 × XCVR_PROP_DLY + clock_period – 1
Count = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------clock_period
udma_t2cyc is another special case. Unlike the name implies, this register does not control 2
UDMA timing cycles. Rather, it controls how long the host continues to accept data after it has
de-asserted HDMARDY–. According to the ATA-4 specification—if tSR is met, the host should
accept 0–1 more data words, or if tSR is exceeded, 0–2 more data words. A safe value to ensure
the host accepts these data words after HDMARDY– de-asserts is:
4 + t2CYC_sec[mode] + clock_period – 1
Count = -----------------------------------------------------------------------------------------------------------clock_period
3. Write the calculated count in the timing registers provided in the ATA host register memory map.
4. Write ATA drive registers per ATA-4 specification using Host Controller register memory map to
the setup drive for desired operation.
5. Read/Write to unimplemented registers or read of a write-only or vice versa errors set flag bits in
the ATA Host Controller status register. The status register is cleared by writing 1 to the flag bit set
to indicate an error.
6. Write ata_dma_mode register to indicate UDMA/DMA READ/WRITE operations for
UDMA/DMA data transfer modes.
7. Initiate and complete data transfers according to protocols described in ATA-4 specification.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-31
ATA Controller
ATA host hardware does data transfers per chosen protocol. Hardware also maintains proper handshaking
with the MPC5200B system.
The ATA state machine is a combination of several small state machines. The data transfers is initiated by
the software. The software chooses the mode of operation and sets up needed registers in the ATA Host
Controller IPBI module.
The ATA drive registers are also set up by the software through ATA IPBI module using PIO mode. The
ATA drive command and control block registers are mapped into ATA Host Controller register memory
map.
The software writes a command to be executed in the ATA drive command register. The command code is
decoded by the drive electronics. The software, at the same time indicates to the host if UDMA/DMA
protocol is used for READ/WRITE of the data. This is done by setting proper bits in the ata_dma_mode
register in the ATA IPBI module.
11.4.1
PIO State Machine
In the ATA-4 spec, 16 timing characteristics must be met for a PIO data or register access:
• 9 are driven by the ATA drive controller—2 (t1 and ta) are counted by the Host Controller for
checking/latching purposes.
• 7 are driven by the ATA Host Controller
To simplify Host Controller design, the following implementation is used:
• Counter—The counter used to count this timing spec (pio_<name>_counter). All non-zero
counters count down from an initial value to 1 (end)
• Start from—Where this counter is initialized.
• Activity at end—What activity to perform when counter reaches 1
• Dependencies—When counter reaches 0, what signals must be checked before counter is finished
(cleared to 0)
Table 11-31. PIO Timing Requirements
Counter
Start from
Activity at end
Dependencies
t0
t1
go to IDLE
t2=0, t2i=0, t4=0
t1 1
N/A (Use t1 instead)
—
—
t2
t1
Latch Read_Data
IORDY_reg=1
t2i
t2
—
—
N/A (Use t2 instead)
—
—
t3
write_enable=0
—
address_enable=0
—
t3
2
t4
t5
N/A (Timing controlled by drive controller)
—
—
t6
N/A (Timing controlled by drive controller)
—
—
t6z
N/A (Timing controlled by drive controller)
—
—
MPC5200B User’s Manual, Rev. 3
11-32
Freescale Semiconductor
ATA Controller
Table 11-31. PIO Timing Requirements (continued)
Counter
Start from
Activity at end
Dependencies
t9 3
N/A (Use t4 instead)
—
—
tA
t1
Check IORDY
IORDY=1
tB
N/A (Timing controlled by drive controller)
—
—
tC
N/A (Timing controlled by drive controller)
—
—
1
Since t1 and t1 are both minimum specs, and t1 <= t1 for PIO modes 0–2, and t1 >= t1 for PIO modes 3–4, t1 is used to
count both, by loading in an initial value that depends on the PIO mode being used. This is the responsibility of software.
2
Since t3 (WDATA setup time) is a minimum, and t3 <= t2 for all PIO modes, t2 is used to determine when to drive Write_Data
on DD.
3
Since t4 and t9 are both minimum specs, and t4 >= t9 for all PIO modes, t4 is used to count from DIOR/DIOW negate to
CS[1]FX/CS[3]FX/ADDR negate.
If ATA drive address space is accessed by CPU, the ATA IPBI module generates:
• a signal to enable the PIO mode state machine
• a wait state to the IPBI module to hold off any further IPBI module access
The PIO state machine indicates transfer is in progress to the IPBI module. This extends the transfer wait
to the IPBI module until the PIO transaction is complete.
11.4.2
DMA State Machine
The interface between the ATA Controller DMA channel and the rest of the system is through a standard
Type 1 BestComm FIFO interface. Table 11-32 shows the timing requirements specified in the ATA-4 spec
for multiword DMA data transfers.
Table 11-32. Multiword DMA Timing Requirements
Counter
Start from
Activity at end
Dependencies
TM
START (Negate CS0, CS1,
set DMA_In_Progress flag)
Assert DMACK,
Assert DIOR/DIOW,
Write Data ready
DMARQ asserted by drive
TE
N/A (Timing controlled
by drive controller)
—
—
TD
TM
Negate DIOR/DIOW,
Latch Read Data/Drive Write Data
DMARQ=1
TK
TD
Assert DIOR/DIOW
DMARQ=1
TH
TD
Ready for new write data
DMARQ=1
T0
TD
Begin next cycle
DMARQ=1
Start TJ, Start TN
DMARQ=0
TJ
T0
Negate DMACK,
Go to Idle
DMARQ Negated,
DMACK asserted, T0=0
TN
T0
Clear DMA_In_Progress flag.
Allow CS0, CS1 to be driven
DMARQ Negated,
DMACK asserted, T0=0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-33
ATA Controller
11.4.2.1
Software Requirements
Software calculates the appropriate values of TD and TK based on information reported for the cycle time
(T0) in the drive’s IDENTIFY DEVICE data and the operating clock frequency. Cycle time (T0) must be
greater than the sum of TD and TK.
11.5
Signals and Connections
Table 11-33. MPC5200B External Signals
Signal
I/O
DATA[15:0]
I/O
SA[2:0]
O
Address—3-bit address, when combined with the two chip-selects, CS1FX and CS3FX, is used
to address Control and Command Block Registers in an ATA drive controller (DA2, DA1 and DA0
on ATA cable, respectively).
CS[1]FX
O
Chip select connected to CS[0] on ATA cable.
CS[3]FX
O
Chip select connected to CS[1] on ATA cable.
IOW
O
I/O Write—Active low signal that denotes a WRITE transaction (DIOW on ATA cable).
IOR
O
I/O Read—Active low signal that denotes a READ transaction (DIOR on ATA cable).
DACK
O
DMA Acknowledge (DMACK on ATA cable).
INTRQ
O
ATA interrupt.
ATA_ISOLATION
O
ATA Write Enable to allow sharing of the ATA DD bus with PCI Bus.
IOCHRDY
I
I/O Channel Ready (IORDY pin on ATA cable)
DRQ
I
RESET
1
NC
Description
Data—16-bit Data Bus (DD pins on ATA cable).
DMA Request (DMARQ pin on ATA cable)
1
Reset—Handled at the board level
NC = No connection
NOTE
The ATA_ISOLATION output is an active high signal to control external
ATA transceiver devices and to isolate the ATA bus from the Local Plus
(shared) bus. The ATA_ISOLATION pin is driven low immediately after the
positive edge of HRESET for 4 PCI_CLK cycles.
This note is only a warning about the behavior of this pin.
Normally, the ATA_ISOLATION pin is used to control an isolation buffer
between the LocalPlus Bus and the ATA bus. Even though this glitch will
cause the ATA Isolation Buffer to drive the LocalPlus Bus for four PCI
Clock Cycles, the LocalPlus Bus cannot initiate a bus cycle for
approximately 10 cycles after the positive edge of HRESET. Therefore, bus
conflict will not occur.
MPC5200B User’s Manual, Rev. 3
11-34
Freescale Semiconductor
ATA Controller
Cable
System Board
See Notes
MPC5200
ATA Controller
Pin1
N/A–GPIO Optional
RESET
GND
DD[15:0]
33 Ohms
ATA_DATA[15:0]
82 Ohms
ATA_DRQ
22 Ohms
ATA_IOW
22 Ohms
ATA_IOR
82 Ohms
ATA_IOCHRDY
DMACK
GND
INTRQ
Reserved
22 Ohms
ATA_DACK
82 Ohms
ATA_INTRQ
DA[1]
PDIAG
22 Ohms
ATA_SA[1]
DA[0]
DA[2]
CS[0]
CS[1]
DASP
GND
22 Ohms
22 Ohms
22 Ohms
22 Ohms
ATA_SA[0]
ATA_SA[2]
ATA_CS[1]FX(CS[4])
ATA_CS[3]FX(CS[5])
GND
KEY
DMARQ
GND
DIOW:STOP
GND
DIOR:HDMARDY:HSTROBE
GND
IORDY:DDMARDY:DSTROBE
CSEL
Pin 40
Note: On system board:
1. All outgoing signals need 3.3V to 5V level shifters.
2. All incoming signals need 5V to 3.3V level shifters or 5V
tolerant input buffers on MPC5200B ATA signals.
LEGEND
Bidirectional
Output
Input
Figure 11-32. Connections—Controller Cable, System Board, MPC5200B
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-35
ATA Controller
11.6
ATA Interface Description
Pin#
Cable
I/O
System Board
I/O
MPC5200B
1
RESET
O
RESET:Reset
—
N/A—GPIO optional
2
GND
—
—
—
—
3–18
DD[15:0]
3,5,7,9,11,13,15,17→DD[7:0]
18,16,14,12,10,8,6,4→DD[15:8]
I/O
DD[0:15]
I/O
ATA_DATA[15:0]
19
GND
—
—
—
—
20
KEY
—
No Signal:Alignment key
—
—
2
DMARQ
I
DMARQ:DMA Request
I
ATA_DRQ
22
GND
—
—
—
—
23
DIOW:STOP
O
DIOW
O
ATA_IOW
24
GND
—
—
—
—
25
DIOR:HDMARDY:HSTROBE
O
DIOR
O
ATA_IOR
26
GND
—
—
—
—
27
IORDY:DDMARDY:DSTROBE
I
IORDY
I
ATA_IOCHRDY
28
CSEL
—
NC
—
—
29
DMACK
O
DMACK
O
ATA_DACK
30
GND
—
—
—
—
31
INTRQ
I
INTRQ
I
ATA_INTRQ
32
Reserved
—
—
—
—
33
DA[1]
O
DA[1]:Address Bus Bit1
O
ATA_SA[1]
34
PDIAG
—
NC
—
—
35
DA[0]
O
DA[0]:Address Bus Bit0
O
ATA_SA[0]
36
DA[2]
O
DA[2]:Address Bus Bit2
O
ATA_SA[2]
37
CS[0]
O
CS[1]FX:Chip Select 0
O
ATA_CS[1]FX(CS[4])
38
CS[1]
O
CS[3]FX:Chip Select 1
O
ATA_CS[3]FX(CS[5])
39
DASP
—
NC
—
—
40
GND
—
—
—
—
Table 11-34. ATA Controller External Connections
NOTE
MPC5200B provides the ATA_ISOLATION output signal. This signal is
shared with the A22 output of the LocalPlus Most/Graphics mode.
The ATA_ISOLATION is not a signal defined by the ATA Standard. It is provided to support an external
ATA transceiver. ATA_ISOLATION is an active high signal to control external transceiver devices and to
‘isolate’ the ATA bus from the LocalPlus (shared) bus.
MPC5200B User’s Manual, Rev. 3
11-36
Freescale Semiconductor
ATA Controller
It can force the transceiver direction -> MPC5200 disk drive. Only during an ATA read is this signal
allowed to go low, forcing transceiver direction disk drive ->MPC5200B.
The ATA_ISOLATION should be connected to the Direction input of the transceiver.
• High = Write to drive
• Low = Read from drive
HOST
DEVICE
CS[0], CS[1]
Chip Select to select Command Block registers.
DA[2:0]
Address to access drive registers or data ports.
DD[15:0]
DIOR:HDMARDY:HSTROBE
8-, 16-bit data interface.
DIORÆAsserted by host to read drive registers or data ports.
HDMARDYÆHost ready to receive UDMA data in bursts. Negated to pause.
HSTROBEÆHost signal for UDMA data out bursts. Data latched in drive registers from DD[15:0]
on both edges of HSTROBE. Host stops generating HSTROBE edges to pause.
DIOW:STOP
DIOWÆAsserted by host to write drive registers or data ports. Negated by host before initiation of UDMA.
STOPÆNegated by host before UDMA burst. Assertion by host signals termination of UDMA.
DMACK
Host response to DMARQ by drive to initiate DMA transfers.
DMARQ
Asserted by drive for DMA data transfers from/to host. For multiword DMA, data direction is
controlled by DIOR and DIOW. MARQ is negated by drive when DMACK is received from
host.drivere-asserts DMARQ for more DMA transfers.
INTRQ
INTRQ used by selected drive to interrupt host. If (nIEN bit == 0 && drive is selected),
INTRQ must be enabled through tri-state and must be driven asserted or negated.
If (nIEN == 1 || drive is not selected), INTRQ = 1'bz.
When INTRQ asserted, drive must negate it within 400ns of negation of DIOR that reads
STATUS register or within 400ns of negation of DIOW that writes the COMMAND register.
When drive is selected by writing to Device/Head register and interrupt is pending, INTRQ
must be asserted within 400ns of negation of DIOW that writes the Device/Head register.
When drive is de-selected by writing to Device/Head register and interrupt is pending, INTRQ
must be negated within 400ns of negation of DIOW that writes the Device/Head register.
IORDY:DDMARDY:DSTROBE
IORDY is negated by drive to extend host transfer cycle (read or write) for PIO modes 3 and above.
DDMARDYÆdrive ready to receive UDMA data out bursts. Negated to pause.
DSTROBEÆdrive signal from UDMA data in bursts. Data latched in host registers from
DD[15:0] on both edges of DSTROBE. Drive stops generating DSTROBE edges to pause.
PDIAG:CBLID
PDIAGÆis asserted by drive 1 to indicate to drive 0 that it has completed diagnostics.
CBLIDÆHost may sample CBLID after Power-ON or hardware reset is completed for all drives on
the cable, to detect presence or absence of 80 conductor cable. If CBLID is detected as connected
to ground then 80-conductor cable is present.
If drive 1 is present, Host should issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE
and use returned data to determine if drive is compliant with ATA-3 or subsequent standards.
Drives compliant with ATA-3 or above, release PDIAG no later than after the first command
following a Power-ON or hardware reset sequence.
RESET
CSEL
RESET used by host to reset drive.
CSEL negated, drive address is 0
CSEL asserted, drive address is 1
Figure 11-33. Pin Description—ATA Interface
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
11-37
ATA Controller
11.7
ATA Bus Background
11.7.1
Terminology
The most popular interface used in modern hard disks is the Integrated Drive Electronics (IDE) interface,
also known by various other names such as: ATA, EIDE, ATA-2, Fast ATA, Ultra ATA, etc.
• Western Digital ® used the term IDE when they first integrated the drive controller logic board on
the disk drive.
• Quantum ® and Seagate ® used the term ATA (Advanced Technology Attachment) or
AT-Attachment, because it has a 16-bit data interface like original AT machines.
ATA is the interface name adopted by the American National Standards Institute (ANSI). Thus far, ANSI
has published ATA, ATA-2, ATA-3 and ATA-4 interfaces. More work is underway for ATA-5 and future
extensions of the ATA interface. Table 11-35 summarizes the different ATA standards.
MPC5200B is compliant with the latest officially published ANSI ATA-4 interface.
Table 11-35. ATA Standards
Interface
Standard
Standard
Type
PIO Modes
IDE/ATA
ANSI
0,1,2
Single word—0,1,2
Multiword—0
—
ATA-2
ANSI
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2
Block transfers, logical block addressing, improved
identify drive command
FAST ATA
Marketing
0,1,2,3
Single word—0,1,2
Multiword 0,1
Same as ATA-2
Fast ATA-2
Marketing
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2
Same as ATA-2
ATA-3
Unofficial
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2
Same as ATA-2, plus improved reliability, SMART
Ultra ATA
Unofficial
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2,3
Same as ATA-3
ATAPI
ANSI
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2
Support for non-hard-disk devices CD-ROM, Tape
drives, etc.
EIDE
Marketing
0,1,2,3,4
Single word—0,1,2
Multiword—0,1,2
Same as ATA-2, plus ATAPI and dual host adapters
ATA-4
ANSI
0,1,2,3,4
Multiword—0,1,2
Ultra DMA—0,1,2
Same as ATA-3, Single word DMA retired
DMA Modes
Special Features or Enhancements introduced
Relative to IDE/ATA
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11.7.2
ATA Modes
Table 11-36. ATA Physical Level Modes
Mode
Cycle Time (ns)
Transfer Rate (MB/s)
Standard
PIO mode 0
600
3.3
ATA
PIO mode 1
383
5.2
ATA
PIO mode 2
240
8.3
ATA
PIO mode 3
180
11.1
ATA-2 (IORDY required)
PIO mode 4
120
16.7
ATA-2 (IORDY required)
DMA mode 0 (Multiword)
480
4.2
ATA
DMA mode 1 (Multiword)
150
13.3
ATA-2
DMA mode 2 (Multiword)
120
16.7
ATA-2
Ultra DMA mode 0
114
16.7
ATA-4
Ultra DMA mode 1
75
25
ATA-4
Ultra DMA mode 2
55
33
ATA-4
11.7.3
ATA Addressing
In the ATA interface, there are two aspects of addressing that are present: register addressing and sector
addressing. These are discussed in the next sections.
11.7.3.1
ATA Register Addressing
The address used to reference an ATA drive register. This is the actual address (CS[1]FX, CS[3]FX,
DA[2:0]) present on the physical ATA interface. Table 11-37 gives details.
Table 11-37. ATA Register Address/Chip Select Decoding
Address
Function
READ (DIOR)
WRITE (DIOW)
System
Address
CS[1]FX
—
1
1
x
x
x
Data bus high impedance
Not used
03F0–03F3
1
0
0
x
x
Data bus high impedance
Not used
03F4–03F5
1
0
1
0
x
Data bus high impedance
Not used
03F6
1
0
1
1
0
Alternate status
Device control
03F7
1
0
1
1
1
Obsolete
Not used
CS[3]FX
DA[2]
DA[1]
DA[0]
Control Block Registers
Command Block Registers
01F0
0
1
0
0
0
Data
Data
01F1
0
1
0
0
1
Error register
Features
01F2
0
1
0
1
0
Sector count
Sector count
01F3
0
1
0
1
1
Sector number
Sector number
1
1
LBA bits 0–71
01F3
0
1
0
1
LBA bits 0–7
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Table 11-37. ATA Register Address/Chip Select Decoding (continued)
Address
1
Function
WRITE (DIOW)
READ (DIOR)
System
Address
CS[1]FX
01F4
0
CS[3]FX
DA[2]
DA[1]
DA[0]
Control Block Registers
1
1
0
0
Cylinder low
Cylinder low
1
01F4
0
1
1
0
0
LBA bits 8–15
01F5
0
1
1
0
1
Cylinder high
LBA bits 8–151
Cylinder high
1
01F5
0
1
1
0
1
LBA bits 16–23
LBA bits 16–231
01F6
0
1
1
1
0
Drive/head
Drive/head
1
01F6
0
1
1
1
0
LBA bits 24–27
LBA bits 24–271
01F7
0
1
1
1
1
Status
Command
—
0
0
x
x
x
Invalid address
Invalid address
LBA mode register mapping—system addresses are for a single channel, accommodating two drives only.
11.7.3.2
Drive Interrupt
A pending drive interrupt is cleared by the following actions:
• Read of status (not the alternate status) register
• Write to command register
11.7.3.3
Sector Addressing
Sector addressing is the address used to reference data on the drive. It is the address used by the low-level
drivers to access a particular piece of data and to place it into one or more ATA registers as part of a
command block. To understand the data addressing, it is necessary to understand the physical organization
of data in a drive, as presented in Figure 11-1. Each drive contains a number of disks, each with one or two
heads (one head per surface). Each disk is divided into concentric tracks that are then divided into a number
of sectors. A sector is the smallest unit of data that can be written or read by a drive. The collections of
tracks that can be accessed by the heads at a single position is called a cylinder. Therefore, a sector can be
uniquely identified by a sector number, a head number and a cylinder number. From this addressing
scheme there are two ways to address an individual sector: physical addressing and logical block
addressing, which are described in the next two sections.
NOTE
LBA mode is only available in ATA-2 or later specifications.
A block mode exists (not to be confused with logical block addressing), in
which sectors are grouped into a unit, called a block, for purposes of data
transfer. The number of sectors is set with SET MULTIPLE MODE
command and is used by the READ MULTIPLE and WRITE MULTIPLE
commands. When specifying sectors within a block, either CHS or LBA
mode may be used.
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11.7.3.4
Physical/Logical Addressing Modes
Addressing is done by referencing the sector, head and cylinder for a particular sector. Using a physical
addressing mode, there are two mappings available:
• Natural—Sector, head and cylinder numbers represent actual physical sectors, heads and cylinders
on the drive.
• Logical—Sector, head and cylinder numbers map to different physical sectors, heads and cylinders
on the drive.
Most modern hard disks usually have 2, 3 or 4 platters. All platters are connected together on a common
spindle to spin as a single assembly. Each platter has two surfaces and two heads to access each surface.
The platter is a collection of concentric circles called tracks, to store data. Each track is subdivided into
sectors. Each sector can hold 540Bytes of information, with 512Bytes being used for data and 28Bytes
being used for error correction code (ECC). A set of tracks under each head at the same track position is
called a cylinder. So to get to the disk read/write data point, a cylinder address, a head address and a sector
address is needed. Hence the basic addressing mode is called cylinder head sector (CHS) addressing.
In this mode, the address is written into the ATA registers as follows:
• Cylinder→{Cylinder High (0x01F5), Cylinder Low (0x01F4)}
• Head→Drive/Head (0x01F6)
• Sector→Sector Number (0x01F3)
To most efficiently use the drive for data storage, the physical geometry is translated into logical geometry
by the hard disk manufacturers. The BIOS or overlay software from the disk manufacturer translates the
logical geometry to physical geometry to get to the physical location of the data written/read on/from the
disk.
The CHS method is limited to 1024 cylinders, 16 heads and 63 sectors. This limits the hard disk
recognition to a maximum of 504MBytes. This limit is increased for larger disks by enhancing the CHS
translation. BIOS limits cylinder size to 1024 (10bits allocated), but allows the number of heads to be 256
(8bits allocated). Therefore, a 3.1GByte hard disk with 6136 cylinders and 16 heads is translated by
dividing the cylinders by 8 (6136 ÷ 8 = 767). The number of heads is then multiplied by the same number
(16 x 8 = 128). This fits well within the limits set by the BIOS and a larger disk is recognized for its true
size (767 x 128 x 63 x 512 = 3.1GBytes).
Another form of addressing is called logical block addressing (LBA). This uses 28bits in the ATA standard
to address a particular sector on a hard disk. A sum total of sectors on a drive is available and each unique
sector is addressed using LBA.
Mapping from physical organization to logical block numbers is done using the following formula:
LBA→(Cylinder# x HeadCount + Head#) x SectorCount + Sector# –1
In this mode, the address is written in the ATA Registers as follows:
LBA→{LBA[0:7](0x01F3), LBA[8:15](0x01F4), LBA[16:23](0x01F5), LBA[24:27]
(0x01F6)}
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ATA Controller
GAP1
VFO Sync
Sync
GAP1
Sync
Cylinder
Header
Cylinder
Header
Write Splice
Head Sector
GAP2
Head Sector
Sync
VFO Sync
512 Bytes data
CRC
512 Bytes data
ECC
GAP3
Soft-Sector Format
GAP3
ECC
CRC
Hard-Sector Format
Figure 11-34. ATA Sector Format
11.7.4
ATA Transactions
ATA Transactions are divided into three types:
• PIO Mode
• Multiword DMA
• Ultra DMA
11.7.4.1
PIO Mode Transactions
PIO mode transactions are the simplest transaction available on the ATA interface. They essentially consist
of single word accesses across the ATA interface. There are currently 6 PIO modes available, which are
summarized in Table 11-36. Timing and sequence information are given in the MPC5200B data sheet.
Three classes of ATA commands use PIO Mode:
•
•
•
Class 1—PIO Read
Class 2—PIO Write
Class Non-Data Command
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11.7.4.1.1
Class 1—PIO Read
Figure 11-35 shows the PIO Read process.
• PIO Single sector read [identify drive, read buffer, read sector(s)]
• Interrupt is generated after each sector is read into the sector buffer:
1.
2.
3.
4.
5.
6.
7.
8.
9.
HOST: Write to ATA control/command block registers to setup for data read.
HOST: Write to ATA command register to execute read command.
HOST: Poll drive to see if it is ready.
DRIVE: Read sector from physical medium to sector buffer.
DRIVE: Interrupt HOST when done.
HOST: Read ATA control/command block registers to get status
DRIVE: Clear interrupt after reading status register.
HOST: Read ATA data register 256 times to get all 512Bytes from sector buffer.
Repeat steps 4–8 for multiple sectors.
— PIO Block mode read [read multiple]
— Interrupt is generated after each block is read into sector buffer:
1.
2.
3.
4.
5.
6.
7.
8.
HOST: Write to ATA control/command block registers to setup for data read.
HOST: Write to ATA command register to execute read command.
HOST: Poll drive to see if it is ready.
DRIVE: Read block of sectors from physical medium to sector buffer.
DRIVE: Interrupt HOST when done.
HOST: Read ATA control/command block registers to get status.
DRIVE: Clear interrupt after reading status register.
HOST: Read ATA data register to get all sectors from sector buffer.
Host
Set Up
Register
Block
Drive
Send
Command
Read
Status
Read
Sector
Read
Sector
Buffer
Read
Status
Read
Sector
Buffer
Read
Sector
DRDY
BSY
DRQ
INTRQ
Figure 11-35. Timing Diagram—PIO Read Command (Class 1)
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11.7.4.1.2
Class 2—PIO Write
The PIO single sector write command [format, write buffer, write sector(s)] is as follows:
1. HOST: Write to ATA control/command block registers to setup for data write.
2. HOST: Write to ATA command register to execute write command.
3. HOST: Poll drive to see if it is ready.
4. HOST: Write ATA data register 256 times to get all 512Bytes into sector buffer.
5. DRIVE: When sector buffer is filled, write sector to physical medium.
6. DRIVE: Interrupt HOST when done.
7. HOST: Read ATA control/command block registers to get status.
8. DRIVE: Clear interrupt after reading status register.
9. Repeat steps 4–8 for multiple sector writes.
The PIO block mode write command (write multiple) is as follows:
1. HOST: Write to ATA control/command block registers to set up for data write.
2. HOST: Write to ATA command register to execute write command.
3. HOST: Poll drive to see if it is ready.
4. HOST: Write ATA data register 256 times to get all sectors into sector buffer.
5. DRIVE: When sector buffer is filled, write sector to physical medium.
6. DRIVE: Interrupt HOST when done.
7. HOST: Read ATA control/command block registers to get status.
8. DRIVE: Clear interrupt after reading status register.
Figure 11-36 shows the PIO Write process.
Host
Drive
Set Up
Register
Block
Send
Command
Write
Sector
Buffer
Read
Status
Write
Sector
Write
Sector
Buffer
Read
Status
Write
Sector
DRDY
BSY
DRQ
INTRQ
Figure 11-36. Timing Diagram—PIO Write Command (Class 2)
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11.7.4.1.3
Class 3—Non-Data Command
The Non-Data Command is as follows:
1. HOST: Write to ATA control/command block registers to setup for data read.
2. HOST: Write to ATA command register to execute read command.
3. DRIVE: Execute command.
Figure 11-37 shows the Non-Data Command.
Host
Set Up
Register
Block
Drive
Set Up
Register
Block
Send
Command
Execute
Command
Send
Command
Execute
Command
DRDY
BSY
DRQ
INTRQ
Figure 11-37. Timing Diagram—Non-Data Command (Class 3)
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11.7.4.2
DMA Protocol
The DMA protocol has the following commands:
• READ DMA
• WRITE DMA
The Host selects the multiword DMA protocol as follows:
1. Write 00100b to upper 5 bits ([7:3]) of sector count register to select multiword DMA protocol.
Write desired mode value to lower 3 bits ([2:0]) of sector count register to set multiword DMA
transfer mode (mode 0=000b, mode 1=001b, etc.).
2. Write sub-command code 0x03 to features register to set transfer mode, based on value in sector
count register.
3. Write command code 0xEF to command register to execute SET FEATURES command. This sets
the data transfer protocol to multiword DMA with desired mode.
Data transfers into DMA differ from a PIO transfer in that:
• Data is transferred using the DMA channel.
• A single interrupt is issued at command completion.
The Host initializes the DMA channel prior to issuing DMA mode commands. The drive asserts an
interrupt when data transfer is complete. The DMA command protocol is as follows:
1. HOST: Read status or alternate status register until BSY and DRQ are both 0. (ATA-4, 41, 48).
2. HOST: Write device/head register with appropriate DEV bit value to select drive. (ATA-4, 45).
3. HOST: Wait 400 ns, read status or alternate status register until BSY & DRQ are set to 0. The
required drive is then assured to be selected.
4. HOST: Write required command parameters to the features, sector count, sector number, cylinder
high, cylinder low, and device/head registers. (ATA-4, chapter 7).
5. HOST: Write command code to command register for drive to start processing command using
parameters from the command block registers. (ATA-4, 41).
6. DRIVE: If no drive error exists, set BSY=1 and begin processing command.
7. HOST: Wait 400ns, read status or alternate status register to ensure valid contents.
8. DRIVE: Set BSY=1 or BSY=0 && DRQ=1.
9. DRIVE: Assert DMARQ when ready, transfer data per multiword DMA timing or ultra DMA
protocol.
10. HOST: Assert DMACK, negate CS [0] and CS [1] when ready to transfer data per multiword DMA
timing or ultra DMA protocol. Transfers are 16-bit wide from the data port. DMA data out
(drive→host) transfers are processed by a series of reads to the data port. Each read transfers the
data that follows the previous read. DMA in data (host→drive) transfers are processed by a series
of writes to this port. Each write transfers the data that follows the previous write. Results are
indeterminate if data port is written during a DMA data out or data port is read during a DMA data
in transfers.
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11. DRIVE: Negate DMARQ when transfer is complete.
12. DRIVE: Set error status in error register if error exists.
13. DRIVE: Clear BSY and DRQ.
14. DRIVE: Assert INTRQ if Host has enabled nIEN (set to 0) in command control register. This
register is written by the host to enable interrupt from the drive by clearing nIEN bit to 0. INTRQ
is in a high impedance state if nIEN bit is set to 1.
When host sets command control register bit SRST to 1, software can reset selected drive. However, the
command control register must be written while DMACK is not asserted. Bit 0 must be cleared to 0.
1. HOST: To clear pending interrupt, read status register (regardless of nIEN status).
2. DRIVE: If enabled by nIEN (nIEN = 0), negate INTRQ.
3. DMA command completes.
Table 11-38. DMA Command Parameters
Parameters Used (Registers)
DMA
Command
Command
Code
READ DMA
WRITE DMA
Features
Sector
Count
Sector
Number/LBA
Cylinder
HI/LO/LBA
Device/Head/LBA
C8h
Yes
Yes
Yes
Yes
D/H Both
CAh
Yes
Yes
Yes
Yes
D/H Both
Figure 11-38 shows the DMA command protocol flow diagram.
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ATA Controller
START
Drive: Assert DMARQ when
ready to transfer data
Host: Read Status or
Alternate Status register
Host:
BSY = 0 &
DRQ = 0
Host: Assert DMACK when
ready to transfer data
No
Yes
Drive:
Transfer
Done
Host: Write Device/Head
register to select drive
No
Yes
Host: Read Status or
Alternate Status register
Drive:
Error
No
Yes
Host:
BSY = 0 &
DRQ = 0
No
Drive: Set Error Status
Yes
Drive: Clear BSY = 0 and DRQ = 0
Write Control/Command block
registers to setup data transfer
No
Write Command Code
to Command register
Yes
Drive: Set BSY = 1 and
begin command execution
Drive: Assert INTRQ
Host: Read Status Register
Drive:
Error
Drive:
nIEN = 0
Host: Read Status Register
Yes
Drive: Negate INTRQ
No
END
Drive: Set BSY = 1, or
BSY = 0 & DRQ = 1
Figure 11-38. Flow Diagram—DMA Command Protocol
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11.7.4.3
Multiword DMA Transactions
Multiword DMA transactions differ from PIO mode transactions in three ways:
1. Data transfers are done using a drive DMA and a host DMA (optional).
2. Handshaking is done with DMARQ and DMACK, no address is necessary.
3. Interrupts do not occur after every sector for multi-sector transfers
11.7.4.3.1
Class 4—DMA Command
Figure 11-39 shows the DMA timing diagram. The DMA command (Read DMA, Write DMA) is as
follows:
1. HOST: Set up HOST DMA (in ATA Host Controller or system DMA).
2. HOST: Write to ATA control/command block registers to setup drive DMA.
3. HOST: Write to ATA control/command block registers to set up data read/write.
4. HOST: Write to ATA command register to execute the read/write command.
5. DRIVE: Assert DMARQ.
6. HOST: When DMARQ is asserted, assert DMACK.
7. DRIVE: Read sector from physical medium to sector buffer.
8. DRIVE: Transfer data to HOST using DMA handshaking.
9. Repeat steps 7–8 as needed for multiple sectors.
10. DRIVE: De-assert DMARQ.
11. HOST: De-assert DMACK.
12. DRIVE: Interrupt HOST.
13. HOST: Stop HOST DMA.
14. HOST: Read ATA control/command block registers to get status.
15. DRIVE: Clear interrupt after reading status register.
Host
Set Up
DMA
Drive
DRDY
BSY
Set Up
Command
/Registers
Carry out DMA
Read
Sector
Reset
DMA
Reset
Status
Read
Sector
UNDEFINED
UNDEFINED
IEN
Figure 11-39. Timing Diagram—DMA Command (Class 4)
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11.7.4.4
Ultra DMA Protocol
The Ultra DMA protocol has the following commands:
• READ DMA
• WRITE DMA
The host selects the Ultra DMA protocol as follows:
• Write 01000b to upper 5 bits ([7:3]) of sector count register to select ultra DMA protocol. Write
desired mode value to lower 3 bits ([2:0]) of sector count register to set ultra DMA transfer mode
(mode 0=000b, mode 1=001b, etc.).
• Write sub-command code 03h to features register to set transfer mode based on value in sector
count register.
• Write command code EFh to command register to execute SET FEATURES command, which sets
the data transfer protocol to ultra DMA with desired mode.
When enabled, the ultra DMA protocol is used instead of the multiword DMA protocol.
NOTE
Ultra DMA mode 2 (UDMA2) requires that the ip bus clock speed is at least
66MHz.
Table 11-39 lists the redefined ultra DMA protocol signal lines. These lines provide new functions during
the ultra DMA mode. At termination of an ultra DMA burst, the host negates DMACK and the lines revert
to the definitions used for non-ultra DMA transfers.
Table 11-39. Redefinition of Signal Lines for Ultra DMA Protocol
Non-Ultra DMA Modes
Ultra DMA Modes
DIOR
HDMARDY
Host DMA ready during Ultra DMA data in bursts
HSTROBE
Host data strobe during Ultra DMA data out bursts
DDMARDY
Drive DMA ready during Ultra DMA data out bursts
DSTROBE
Drive data strobe during Ultra DMA data in bursts
IORDY
DIOW
STOP
Description
Host stop ultra DMA bursts
Both the host and drive do a CRC function during an ultra DMA burst:
• The host sends CRC data to the drive.
• The drive does a CRC data comparison.
If the CRC comparison fails, the error register ERR bit is set. The drive always reports the first error that
occurs.
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11.8
ATA RESET/Power-Up
11.8.1
Hardware Reset
The host asserts RESET for a minimum of 25µs after power has stabilized within system specified
tolerance. A signal assertion less than 20ns is not recognized by the drive.
The host should not do the following:
• set the device control register bit SRST to 1 to enable the drive for software reset
• issue a DEVICE RESET command while the status register BSY bit is set to 1.
NOTE
Hardware reset is a board requirement, not an MPC5200B function unless
GPIO is used.
11.8.2
Software Reset
The host sets the device control register bit SRST to 1. Any subsequent setting and clearing of the SRST
bit must be at least 5µs apart.
Figure 11-40 shows the Reset timing diagram. Table 11-40 gives timing characteristics.
tM
RESET
tN
Can set BSY=0 if Drive 1 not present
BSY
Drive 0
tP
tR Drive 0
Can assert DASP to indicate
active if Drive 1 not present
DASP
Control
Registers
tN
BSY
Drive 1
tP
tQ
PDIAG
tS
tR Drive 1
DASP
Figure 11-40. Timing Diagram—Reset Timing
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Table 11-40. Reset Timing Characteristics
Name
Min/Max
Timing
tM
Reset pulse width
Min
25µs
tN
Reset negated to BSY active setup
Max
400ns
tP
Reset negated to DASP inactive setup
Max
1ms
tQ
DASP active to PDIAG active setup
Max
30s
tR
Drive 0—Reset negated to DASP active setup
Max
450ms
Drive 1—Reset negated to DASP active setup
Max
400ms
DASP active to PDIAG inactive setup
Max
30.5s
tS
11.9
PIO Timing Parameter
ATA I/O Cable Specifications
For reference, the standard ATA cable specifications affects stem integrity and should not exceed 18inches
or 0.46m. Total cable capacitance should not exceed 35pF.
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Chapter 12
Universal Serial Bus (USB)
12.1
Overview
The following sections are contained in this document:
• Section 12.2, “Data Transfer Types”
• Section 12.4, “Host Control (HC) Operational Registers”, includes:
— Section 12.4.2, “Control and Status Partition”
— Section 12.4.3, “Memory Pointer Partition”
— Section 12.4.4, “Frame Counter Partition”
— Section 12.4.5, “Root Hub Partition”
The Universal Serial Bus (USB) is an external bus standard that supports data transfer rates of 12Mbps.
Figure 12-1 shows the four main areas of a USB system, which are:
• Client software/USB driver—software implemented
• Host Controller Driver (HCD)—software implemented
• Host Controller (HC)—hardware implemented
• USB device—hardware implemented
Client Software
USB Driver
Software
Host Controller Driver
Scope of OHCI
Host Controller
Hardware
USB Device
Figure 12-1. USB Focus Areas
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-1
Universal Serial Bus (USB)
The Open Host Controller Interface (OHCI) is a register-level description of a HC for the Universal Serial
Bus (USB). OHCI specifies the interface between and the fundamental HCD operation and the HC.
The HCD and HC work in tandem to transfer data between client software and a USB device. Data is
translated from shared-memory data structures at the client software end, to USB signal protocols at the
USB device end, and vice-versa.
12.2
Data Transfer Types
Four data transfer types are defined in the USB. Each type is optimized to match the service requirements
between client software and the USB device. These types are:
• Interrupt Transfers—Small data transfers used to communicate information from the USB
device to the client software. The HCD polls the USB device by issuing tokens to the device at a
periodic interval sufficient for the requirements of the device.
• Isochronous Transfers—Periodic data transfers with a constant data rate. Data transfers are
correlated in time between the sender and receiver.
• Control Transfers—Non-periodic data transfers used to communicate
configuration/command/status type information between client software and the USB device.
• Bulk Transfers—Non-periodic data transfers used to communicate large amounts of information
between client software and the USB device.
In OpenHCI the data transfer types are classified into two categories: periodic and nonperiodic. Periodic
transfers are interrupt and isochronous since they are scheduled to run at periodic intervals. Non-periodic
transfers are control and bulk since they are not scheduled to run at any specific time, but rather on a
time-available basis.
12.3
12.3.1
Host Controller Interface
Communication Channels
There are two communication channels between the HC and HCD.
1. The first channel uses a set of operational registers located on the HC. The HC is the target for all
communication on this channel. The operational registers contain control, status, and list pointer
registers. Within the operational register set is a pointer to a location in shared memory named the
HC Communications Area (HCCA).
2. The HCCA is the second communication channel. The HC is the master for all communication on
this channel. The HCCA contains the head pointers to the interrupt endpoint descriptor lists, the
head pointer to the done queue, and status information associated with start-of-frame processing.
MPC5200B User’s Manual, Rev. 3
12-2
Freescale Semiconductor
Universal Serial Bus (USB)
Device Enumeration
OpenHCI
Operational
Registers
Host Controller Communications Area
Mode
Interrupt 0
HCCA
Interrupt 1
Status
Interrupt 2
Event
Frame Int
. . .
Interrupt 31
. . .
Ratio
Control
Bulk
. . .
Done
Device Register in
Memory Space
Shared RAM
Figure 12-2. Communication Channels
NOTE
The Open Host Controller Interface (OHCI) specification describes the Host
Controller Communication Area (HCCA), which is located in memory (as
opposed to the USB module register). The start address (base address) of
that memory area is defined by the USB controller register HC
Communication Register.
The HCCA includes the “virtual” registers HccaFrameNumber and
HccaPad1. The offsets shall be 0x80 (for HccaFrameNumber) and 0x82 (for
HccaPad1).
In the USB module of the MPC5200B these two “virtual” registers are
swapped. The HccaFrameNumber is a copy of the Frame Number field at
the USB HC Timing Reference Register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-3
Universal Serial Bus (USB)
12.3.2
Data Structures
The basic building blocks for communication across the interface are the endpoint descriptor (ED) and
transfer descriptor (TD).
The HCD assigns an endpoint descriptor to each endpoint in the system. The endpoint descriptor contains
the information necessary for the HC to communicate with the endpoint. The fields include the maximum
packet size, the endpoint address, the speed of the endpoint, and the direction of data flow. Endpoint
descriptors are linked in a list.
A queue of transfer descriptors is linked to the endpoint descriptor for the specific endpoint. The transfer
descriptor contains the information necessary to describe the data packets to be transferred. The fields
include data toggle information, shared memory buffer location, and completion status codes. Each
transfer descriptor contains information that describes one or more data packets. The data buffer for each
transfer descriptor ranges in size from 0 to 8192 Bytes with a maximum of one physical page crossing.
Transfer descriptors are linked in a queue; the first one queued is the first one processed.
Each data transfer type has its own linked list of endpoint descriptors to be processed. Figure 12-3 shows
the data structure relationship.
Head Ptr
ED
ED
ED
ED
TD
TD
TD
TD
TD
TD
TD
Figure 12-3. Typical List Structure
The head pointers to the bulk and control endpoint descriptor lists are maintained within the operational
registers in the HC. The HCD initializes these pointers prior to the HC gaining access to them. Should
these pointers need to be updated, the HCD may need to stop the HC from processing the specific list,
update the pointer, then re-enable the HC.
The head pointers to the interrupt endpoint descriptor lists are maintained within the HCCA. There is no
separate head pointer for isochronous transfers. The first isochronous endpoint descriptor simply links to
the last interrupt endpoint descriptor. There are 32 interrupt head pointers. The head pointer used for a
particular frame is determined by using the last five bits of the frame counter as an offset into the interrupt
array within the HCCA.
The interrupt endpoint descriptors are organized into a tree structure with the head pointers being the leaf
nodes. The desired interrupt endpoint polling rate is achieved by scheduling the endpoint descriptor at the
appropriate depth in the tree. The higher the polling rate, the closer to the root of the tree the endpoint
descriptor is placed. Figure 12-4 shows the interrupt endpoint structure. The Interrupt endpoint descriptor
MPC5200B User’s Manual, Rev. 3
12-4
Freescale Semiconductor
Universal Serial Bus (USB)
placeholder indicates where zero or more endpoint descriptors may be queued. The numbers on the left are
the index into the HCCA interrupt head pointer array.
Interrupt
Headpointers
0
16
8
24
4
20
12
28
2
18
10
26
6
22
14
30
1
17
9
25
5
21
13
29
3
19
11
27
7
23
15
31
Interrupt
Endpoint
Descriptor
Placeholder
32 16
8
4
2
1
Endpoint Poll Interval (ms)
Figure 12-4. Interrupt ED Structure
Figure 12-5 shows a sample interrupt endpoint schedule. The schedule shows:
•
•
•
•
•
•
Two endpoint descriptors at a 1ms poll interval
Two endpoint descriptors at a 2ms poll interval
One endpoint descriptor at a 4ms poll interval
Two endpoint descriptors at an 8ms poll interval
Two endpoint descriptors at a 16ms poll interval
Two endpoint descriptors at a 32ms poll interval.
NOTE
Unused interrupt endpoint placeholders are bypassed and the link is
connected to the next available endpoint in the hierarchy.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-5
Universal Serial Bus (USB)
Interrupt
Headpointers
0
16
8
24
4
20
12
28
2
18
10
26
6
22
14
30
1
17
9
25
5
21
13
29
3
19
11
27
7
23
15
31
Interrupt
Endpoint
Descriptor
32 16
8
4
2
1
Endpoint Poll Interval (ms)
Figure 12-5. Sample Interrupt Endpoint Schedule
12.4
Host Control (HC) Operational Registers
Host Control contains a set of on-chip operational registers which are mapped into a non-cacheable portion
of the system addressable space. These registers are used by the HCD. According to the function of these
registers, they are divided into four partitions, specifically for control and status, memory pointer, frame
counter and root hub. All of the registers should be read and written as 32-bit words.
Reserved bits may be allocated in future releases of this specification. To ensure interoperability, the HCD
that does not use a reserved field should not assume the reserved field contains 0. In addition, HCD should
always preserve the reserved field value(s).
When a R/ W register is modified, the HCD should first read the register and modify the bits desired. Then,
HCD should write the register with the reserved bits still containing the read value. Alternatively, HCD
can maintain an in-memory copy of previously written values that can be modified and written to the HC
register. When a write to the set/clear register is written, bits written to reserved fields should be 0.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Universal Serial Bus (USB)
12.4.1
Programming Note
Programmers should observe the following notes:
1. The CDM 48MHz Fractional Divider Configuration Register must be initialized before you can
access any USB registers. If this register is not initialized, every USB register access will cause a
machine check interrupt.
For Example: If the SYS_XTAL_IN frequency is 33 MHz and the RST_CFG6 pin is low
(multiplier 16), than the four phase divide ratios must be set to 0x5,fractional counter divide ration
of fsystem /11. 33 MHz * 16 / 11 = 48 MHz (USB frequency)
2. The GPS Port Configuration Register must be initialized to communicate over the muxed USB
port. It configures USB for Differential or SE0 mode, the port to be used for USB2 and if the
IrDA/USB 48 MHz clock is generated internally or externally.
12.4.2
Control and Status Partition
This HC partition uses 6 32-bit registers. These registers are located at an offset from MBAR of 0x1000.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x1000 +
register address
The following registers are available:
• USB HC Revision Register (0x1000)
• USB HC Control Register (0x1004)
• USB HC Command Status Register (0x1008)
• USB HC Interrupt Status Register (0x100C)
• USB HC Interrupt Enable Register (0x1010)
• USB HC Interrupt Disable Register (0x1014)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-7
Universal Serial Bus (USB)
12.4.2.1
USB HC Revision Register
Address MBAR + 0x1000
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
0
REV
0
0
0
0
0
0
1
Figure 12-6. USB HC Revision Register
Table 12-1. USB HC Revision Register Field Descriptions
Bits
Name
0:23
–
24:31
REV
Description
Reserved
Revision—a read-only field containing the BCD representation of the HCI specification version
implemented by this HC. For example, a value of 11h corresponds to version 1.1. All HC
implementations compliant with this specification have a value of 10h.
MPC5200B User’s Manual, Rev. 3
12-8
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.2.2
USB HC Control Register
The HC Control register defines HC operating modes. Except for HostController FunctionalState and
RemoteWakeUpConnected, most fields in this register are modified only by the HCD.
Address MBAR + 0x1004
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BLE
CLE
IE
PLE
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
RWE RWC
0
0
0
0
IR
0
HCFS
0
0
CBSR
0
0
Figure 12-7. USB HC Control Register
Table 12-2. USB HC Control Register Field Descriptions
Bits
Name
Description
0:20
—
21
RWE
RemoteWakeUpEnable—HCD uses bit to enable or disable the remote WakeUp feature on
detection of upstream resume signaling.
When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote WakeUp is
signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt.
22
RWC
RemoteWakeUpConnected—bit indicates whether HC supports remote WakeUp signaling. If
remote WakeUp is supported and used by the system it is the responsibility of system firmware to
set this bit during BOOT UP.
HC clears bit on a hardware reset, but does not alter it on a software reset. Host system remote
WakeUp signaling is host-bus-specific and not described in this specification.
23
IR
InterruptRouting—bit determines routing of interrupts generated by events registered in
HcInterruptStatus.
The IR Bit is ignored by the MPC5200B. It is here to maintain OHCI compliancy. The interrupt from
the USB module is routed to the interrupt controller in the SIU where it can be routed to the SMI or
NORMAL interrupt.
24:25
HCFS
HostControllerFunctionalState—a USB field:
00 USBRESET
01 USBRESUME
10 USBOPERATIONAL
11 USBSUSPEND
Transition to USBOPERATIONAL from another state causes SOF generation to begin 1ms later.
HCD may determine if HC has begun sending SOFs by reading the StartofFrame field of
HcInterruptStatus. This field may be changed by HC, only when in the USBSUSPEND state. HC
may move from the USBSUSPEND state to the USBRESUME state after detecting resume
signaling from a downstream port. HC enters USBSUSPEND after a software reset, whereas it
enters USBRESET after a hardware reset. A hardware reset also resets the Root Hub and asserts
subsequent reset signaling to downstream ports.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-9
Universal Serial Bus (USB)
Table 12-2. USB HC Control Register Field Descriptions (continued)
Bits
Name
26
BLE
BulkListEnable—setting bit enables Bulk list processing in next Frame.
• If cleared by HCD, Bulk list processing does not occur after next SOF. HC checks this bit
whenever it determines to process the list. When disabled, HCD may modify the list.
• If HcBulkCurrentED points to an ED to be removed, HCD advances pointer by updating
HcBulkCurrentED before re-enabling list processing.
27
CLE
ControlListEnable—setting bit enables Control list processing in next Frame.
• If cleared by HCD, Control list processing does not occur after next SOF. HC checks this bit
whenever it determines to process the list. When disabled, HCD may modify the list.
• If HcControlCurrentED points to an ED to be removed, HCD advances pointer by updating
HcControlCurrentED before re-enabling list processing.
28
IE
IsochronousEnable—HCD uses bit to enable/disable isochronous EDs processing. While
processing the periodic list in a Frame, HC checks bit status when it finds an Isochronous ED (F=1).
• If set (enabled), HC continues processing the EDs.
• If cleared (disabled), HC halts periodic list processing, which now contains only isochronous
EDs, and begins processing Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame, not the current Frame.
29
PLE
PeriodicListEnable—setting bit enables periodic list processing in next Frame. If cleared by HCD,
periodic list processing does not occur after the next SOF. HC checks this bit prior to starting list
processing.
30:31
CBSR
ControlBulkServiceRatio—field specifies the service ratio between Control and Bulk EDs. Before
processing non-periodic lists, HC compares the ratio specified with its internal count on how many
non-empty Control EDs have been processed, in determining whether to continue serving another
Control ED or switching to Bulk EDs. When crossing the frame boundary, the internal count is
retained. In case of reset, HCD is responsible for restoring this value.
CBSR=Number of Control EDs Over Bulk EDs Served
0 1:1
1 2:1
2 3:1
3 4:1
12.4.2.3
Description
USB HC Command Status Register
HC uses the HC Command Status register to receive (Rx) commands issued by HCD. It reflects the current
HC status. To HCD, it appears to be a write-to-set register. HC ensures bits written as 1 are set in the
register, while bits written as 0 remain unchanged in the register. HCD may issue multiple distinct
commands to HC without concern for corrupting previously issued commands. HCD has normal read
access to all bits.
The SchedulingOverrunCount field indicates the number of frames in which HC detects scheduling
overrun errors. This occurs when the Periodic list does not complete before EOF. When a scheduling
overrun error is detected, HC increments the counter and sets SchedulingOverrun field in
HcInterruptStatus register.
MPC5200B User’s Manual, Rev. 3
12-10
Freescale Semiconductor
Universal Serial Bus (USB)
Address MBAR + 0x1008
0
1
2
3
4
5
R
8
9
10
11
12
13
14
15
SOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OCR
BLF
CLF
HCR
0
0
0
0
R
Reserved
W
Reset
7
Reserved
W
Reset
6
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-8. USB HC Command Status Register
Table 12-3. USB HC Command Status Register Field Descriptions
Bits
Name
Description
0:13
—
14:15
SOC
16:27
—
28
OCR
OwnershipChangeRequest—OS HCD sets this bit to request an HC change of control. When set,
HC sets the OwnershipChange field in HcInterruptStatus. After changeover, this bit is cleared and
remains clear until the next OS HCD request.
29
BLF
BulkListFilled—bit indicates whether there are Bulk List TDs. HCD sets this bit when it adds a TD
to a Bulk List ED. When HC begins processing the Bulk List head, it checks BF.
• If BLF is 0, HC does not start Bulk List processing.
• If BLF is 1, HC starts Bulk List processing and sets BF to 0.
• If HC finds a Bulk List TD, HC sets BLF to 1, causing Bulk List processing to continue.
• If HC does not find a Bulk List TD and HCD does not set BLF, then BLF remains 0 when HC
completes processing and Bulk List processing stops.
30
CLF
ControlListFilled—bit indicates whether there are Control List TDs. HCD sets this bit when it adds
a TD to a Control List ED. When HC begins processing the Control List head, it checks CLF.
• If CLF is 0, HC does not start Control List processing.
• If CF is 1, HC starts Control List processing and sets CLF to 0.
• If HC finds a Control List TD, CLF is set to 1, causing Control List processing to continue.
• If HC does not find a Control List TD and HCD does not set CLF, then CLF remains 0 when HC
completes processing and Control List processing stops.
31
HCR
HostControllerReset—HCD sets bit to initiate a software reset of HC. Regardless of the HC
functional state, it moves to the USBSUSPEND state in which most of the operational registers are
reset except those stated otherwise. For example, HcControl Interrupt Routing field and no Host bus
access is allowed.
On completion of the reset operation, HC clears this bit. Completion must be within 10ms. When
set, this bit should not cause a root hub reset and no subsequent reset signaling should be asserted
to downstream ports.
Reserved
SchedulingOverrunCount—bits are incremented on each scheduling overrun error. SOC is
initialized to 00 and wraps at 11. SOC increments when a scheduling overrun is detected, even if
SchedulingOverrun in HcInterruptStatus has already been set. HCD uses SOC to monitor any
persistent scheduling problems.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-11
Universal Serial Bus (USB)
12.4.2.4
USB HC Interrupt Status Register
This register provides status on various events that cause hardware interrupts. When an event occurs, HC
sets the corresponding register bit. When a bit is set, a hardware interrupt is generated, if the interrupt is
enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set. HCD may clear specific
bits in this register by writing 1 to bit positions to be cleared. HCD may not set any of these bits. HC never
clears the bit.
Address MBAR + 0x100C
R
W
Reset
0
1
2
3
Rsvd
OC
5
6
7
8
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
R
Reserved
0
0
9
10
11
12
13
14
15
0
0
0
0
0
0
0
25
26
27
28
29
30
31
RHSC
FNO
UE
RD
SF
WDH
SO
0
0
0
0
0
0
0
Reserved
W
Reset
4
0
0
0
0
0
0
0
Figure 12-9. USB HC Interrupt Status Register
Table 12-4. USB HC Interrupt Status Register Field Descriptions
Bits
Name
Description
0
—
Reserved
1
OC
OwnershipChange—HC sets this bit when HCD sets the HcCommandStatus
OwnershipChangeRequest field. This event, when unmasked, always generate an immediate System
Management Interrupt (SMI).
When the SMI pin is not implemented, the OC bit is tied to 0.
2:24
—
Reserved
25
RHSC
26
FNO
FrameNumberOverflow—bit is set when HcFmNumber msb (bit 15) changes value (from 0 to 1, or
from 1 to 0) and after HccaFrameNumber is updated.
27
UE
UnrecoverableError—bit is set when HC detects a system error not related to USB. HC should not
proceed with processing or signaling prior to the system error being corrected. HCD clears this bit
after HC is reset.
28
RD
ResumeDetected—bit is set when HC detects a USB device asserting a resume signal. It is the
transition from no resume signaling to resume signaling that causes this bit to be set. This bit is not
set when HCD sets the USBRESUME state.
29
SF
StartofFrame—bit is set by HC at each start of a frame and after updating the HccaFrameNumber.
HC also generates an SOF token at the same time.
30
WDH
WritebackDoneHead—bit is set immediately after HC writes HcDoneHead to HccaDoneHead.
Further HccaDoneHead updates do not occur until this bit is cleared. HCD should only clear this bit
after saving HccaDoneHead contents.
31
SO
RootHubStatusChange—bit is set when HcRhStatus content or content of any
HcRhPortStatus[Number of Downstream Port] changes.
SchedulingOverrun—bit is set when USB schedule for the current Frame overruns and after an
HccaFrameNumber update. A scheduling overrun also causes the HcCommandStatus SOC to
increment.
MPC5200B User’s Manual, Rev. 3
12-12
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.2.5
USB HC Interrupt Enable Register
Each enable bit in the HC Interrupt Enable register corresponds to an associated interrupt bit in the
HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a
hardware interrupt. When:
1. Abit is set in the HcInterruptStatus register, and
2. The corresponding bit is set in the HcInterruptEnable register, and
3. The MasterInterruptEnable bit is set, then
4. Ahardware interrupt is requested on the host bus.
Writing 1 to a bit in this register sets the corresponding bit, whereas writing 0 to a bit in this register leaves
the corresponding bit unchanged. On read, the current value of this register is returned.
Address MBAR + 0x1010
R
W
Reset
0
1
2
3
MIE
OC
5
6
7
8
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
R
Reserved
0
9
10
11
12
13
14
15
0
0
0
0
0
0
0
25
26
27
28
29
30
31
RHSC
FNO
UE
RD
SF
WDH
SO
0
0
0
0
0
0
0
Reserved
W
Reset
4
0
0
0
0
0
0
0
0
Figure 12-10. USB HC Interrupt Enable Register
Table 12-5. USB HC Interrupt Enable Register Field Descriptions
Bits
Name
Description
0
MIE
Master Interrupt Enable—used by HCD.
0 Writing to this bit is ignored by HC.
1 Writing to this bit enables interrupt generation, due to events specified in other bits of this register.
1
OC
OwnershipChange
0 Writing to this bit is ignored by HC.
1 Writing to this bit enables interrupt generation, due to ownership.
2:24
—
Reserved
25
RHSC
RootHubStatusChange
0 Ignore
1 Enable interrupt generation due to root hub status change.
26
FNO
FrameNumberOverflow
0 Ignore
1 Enable interrupt generation due to frame number overflow.
27
UE
UnrecoverableError
0 Ignore
1 Enable interrupt generation due to unrecoverable error.
28
RD
ResumeDetected
0 Ignore
1 Enable interrupt generation due to resume detect.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-13
Universal Serial Bus (USB)
Table 12-5. USB HC Interrupt Enable Register Field Descriptions (continued)
Bits
Name
29
SF
30
WDH
31
SO
12.4.2.6
Description
StartofFrame
0 Ignore
1 Enable interrupt generation due to start of frame.
WritebackDoneHead
0 Ignore
1 Enable interrupt generation due to HcDoneHead writeback.
SchedulingOverrun
0 Ignore
1 Enable interrupt generation due to scheduling overrun.
USB HC Interrupt Disable Register
Each disable bit in the HC Interrupt Disable register corresponds to an associated interrupt bit in the
HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register.
Thus, writing a ‘1’ to a bit in this register clears the corresponding bit in the HcInterruptEnable register,
whereas writing a ‘0’ to a bit in this register leaves the corresponding bit in the HcInterruptEnable register
unchanged. On read, the current value of the HcInterruptEnable register is returned.
Address MBAR + 0x1014
R
W
Reset
0
1
2
3
MIE
OC
5
6
7
8
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
Reserved
W
0
0
9
10
11
12
13
14
15
0
0
0
0
0
0
0
25
26
27
28
29
30
31
RHSC
FNO
UE
RD
SF
WDH
SO
0
0
0
0
0
0
0
Reserved
R
Reset
4
0
0
0
0
0
0
0
Figure 12-11. USB HC Interrupt Disable Register
Table 12-6. USB HC Interrupt Disable Register Field Descriptions
Bits
Name
Description
0
MIE
Master Interrupt Enable—bit is set after a hardware or software reset.
0 Written to this bit is ignored by HC.
1 Written to this bit disables interrupt generation, due to events specified in other bits of this register.
1
OC
OwnershipChange
0 Ignore
1 Disable interrupt generation due to Ownership Change
2:24
—
Reserved
25
RHSC
RootHubStatusChange
0 Ignore
1 Disable interrupt generation due to root hub status change.
26
FNO
FrameNumberOverflow
0 Ignore
1 Disable interrupt generation due to frame number overflow.
MPC5200B User’s Manual, Rev. 3
12-14
Freescale Semiconductor
Universal Serial Bus (USB)
Table 12-6. USB HC Interrupt Disable Register Field Descriptions (continued)
Bits
Name
Description
27
UE
UnrecoverableError
0 Ignore
1 Disable interrupt generation due to unrecoverable error.
28
RD
ResumeDetected
0 Ignore
1 Disable interrupt generation due to resume detect.
29
SF
StartofFrame
0 Ignore
1 Disable interrupt generation due to start of frame.
30
WDH
31
SO
WritebackDoneHead
0 Ignore
1 Disable interrupt generation due to HcDoneHead writeback.
SchedulingOverrun
0 Ignore
1 Disable interrupt generation due to scheduling overrun.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-15
Universal Serial Bus (USB)
12.4.3
Memory Pointer Partition
This HC partition uses 7 32-bit registers. These registers are located at an offset from MBAR of 0x1018.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x1018 +
register address
The following registers are available:
• USB HC HCCA Register (0x1018)
• USB HC Period Current Endpoint Descriptor Register (0x101C)
• USB HC Control Head Endpoint Descriptor Register (0x1020)
• USB HC Control Current Endpoint Descriptor Register (0x1024)
• USB HC Bulk Head Endpoint Descriptor Register (0x1028)
• USB HC Bulk Current Endpoint Descriptor Register (0x102C)
• USB HC Done Head Register (0x1030)
12.4.3.1
USB HC HCCA Register
The HC HCCA register contains the physical address of the Host Controller Communication Area. HCD
determines alignment restrictions by writing all 1s to HcHCCA and reading the HcHCCA content.
Alignment is evaluated by examining the number of 0s in the lower order bits. Minimum alignment is
256Bytes. Bits 0 through 7 must always return 0 when read. This area holds control structures and the
interrupt table, which are accessed by both the HC and HCD.
Address MBAR + 0x1018
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Reserved
HCCA
W
Reset
9
HCCA
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-12. USB HC HCCA Register
Table 12-7. USB HC HCCA Register Field Descriptions
Bits
Name
0:23
HCCA
24:31
—
Description
Host Controller Communication Area—base address.
Reserved
MPC5200B User’s Manual, Rev. 3
12-16
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.3.2
USB HC Period Current Endpoint Descriptor Register
The HC Period Current Endpoint Descriptor (ED) register contains the physical address of the current
isochronous or interrupt endpoint descriptor.
Address MBAR + 0x101C
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PCED
W
Reset
9
PCED
W
Reset
8
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
Figure 12-13. USB HC Period Current Endpoint Descriptor Register
Table 12-8. USB HC Period Current Endpoint Descriptor Register Field Descriptions
Bits
Name
Description
0:27
PCED
PeriodCurrentED—HC uses this field to point to the head of one of the Periodic lists, which is
processed in the current Frame. HC updates register content after a periodic ED is processed. HCD
may read the content in determining which ED is currently being processed at the time of reading.
28:31
—
12.4.3.3
Reserved
USB HC Control Head Endpoint Descriptor Register
The HC Control Head Endpoint Descriptor register contains the physical address of the first endpoint
descriptor of the Control list.
Address MBAR + 0x1020
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CHED
W
Reset
9
CHED
W
Reset
8
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
Figure 12-14. USB HC Control Head Endpoint Descriptor Register
Table 12-9. USB HC Control Head Endpoint Descriptor Register Field Descriptions
Bits
Name
Description
0:27
CHED
ControlHeadED—HC traverses the control list starting with the HcControlHeadED pointer. Content
is loaded from HCCA during HC initialization.
28:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-17
Universal Serial Bus (USB)
12.4.3.4
USB HC Control Current Endpoint Descriptor Register
The HC Control Current Endpoint Descriptor register contains the physical address of the current control
list endpoint descriptor.
Address MBAR + 0x1024
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
CCED
W
Reset
9
CCED
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-15. USB HC Control Current Endpoint Descriptor Register
Table 12-10. USB HC Control Current Endpoint Descriptor Register Field Descriptions
Bits
Name
Description
0:27
CCED
ControlCurrentED—pointer is advanced to next ED after serving the present one. HC continues
processing the list from where it left off in the last frame. When it reaches the control list end, HC
checks the HcCommandStatus ControlListFilled.
• If set, CCED copies HcControlHeadED content to HcControlCurrentED and clears bit.
• If not set, it does nothing.
HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared. When
set, HCD only reads the instantaneous value of this register. Initially, this is set to 0 to indicate the end
of the Control List.
28:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
12-18
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.3.5
USB HC Bulk Head Endpoint Descriptor Register
The HC Head Endpoint Descriptor register contains the physical address of the first bulk list endpoint
descriptor.
Address MBAR + 0x1028
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
BHED
W
Reset
9
BHED
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-16. USB HC Bulk Head Endpoint Descriptor Register
Table 12-11. USB HC Bulk Head Endpoint Descriptor Register Field Descriptions
Bits
Name
0:27
BHED
28:31
—
Description
BulkHeadED—HC traverses the Bulk List starting with the HcBulkHeadED pointer. The content is
loaded from HCCA during the HC initialization.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-19
Universal Serial Bus (USB)
12.4.3.6
USB HC Bulk Current Endpoint Descriptor Register
The HC Bulk Current Endpoint Descriptor register contains the physical address of the current endpoint
of the bulk list. The bulk list is served in a round-robin fashion, therefore endpoints are ordered according
to their insertion into the list.
Address MBAR + 0x102C
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BCED
W
Reset
9
BCED
W
Reset
8
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
Figure 12-17. USB HC Bulk Current Endpoint Descriptor Register
Table 12-12. USB HC Bulk Current Endpoint Descriptor Register Field Descriptions
Bits
Name
Description
0:27
BHED
BulkCurrentED—advances to the next ED after HC has served the present ED.
HC continues processing the list from where it left off in the last Frame. When it reaches the end of the
Bulk List, HC checks the HcCommandStatus BulkListFilled.
• If set, BHED copies HcBulkHeadED content to HcBulkCurrentED and clears bit.
• If not set, it does nothing.
HCD is only allowed to modify this register when HcControl BulkListEnable is cleared. When set, HCD
only reads the instantaneous value of this register. This is initially set to 0 to indicate the end of the Bulk
List.
28:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
12-20
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.3.7
USB HC Done Head Register
The HC Done Head register contains the physical address of the last completed transfer descriptor that was
added to the done queue. In normal operation, HCD does not need to read this register as its content is
periodically written to the HCCA.
Address MBAR + 0x1030
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
DH
W
Reset
9
DH
W
Reset
8
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
Figure 12-18. USB HC Done Head Register
Table 12-13. USB HC Done Head Register Field Descriptions
Bits
Name
Description
0:27
DH
DoneHead—When a TD is complete, HC writes the HcDoneHead content to the TD NextTD field. HC
then overwrites the HcDoneHead content with the TD address. This is set to 0 when HC writes the
register content to HCCA. HcInterruptStatus WritebackDoneHead is also set.
28:31
—
Reserved
12.4.4
Frame Counter Partition
This HC partition uses 5 32-bit registers. These registers are located at an offset from MBAR of 0x1034.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x1034 +
register address
The following registers are available:
• USB HC Frame Interval Register Field Descriptions (0x1034)
• USB HC Frame Remaining Register (0x1038)
• USB HC Frame Number Register (0x103C)
• USB HC Periodic Start Register (0x1040)
• USB HC LS Threshold Register (0x1044)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-21
Universal Serial Bus (USB)
12.4.4.1
USB HC Frame Interval Register
The HC Frame Interval register contains a 14-bit value that indicates:
• The bit-time interval in a Frame. For example, between two consecutive SOFs.
• A 15-bit value that indicates the full speed maximum packet size the HC may transmit or receive
without causing scheduling overruns.
HCD may carry out minor adjustment on the frame interval by writing a new value over the present one
at each SOF. This provides the programmability necessary for the HC to synchronize with an external
clocking resource and to adjust any unknown local clock offset.
Address MBAR + 0x1034
0
R
W
Reset
R
W
Reset
1
2
3
4
5
6
7
FIT
8
9
10
11
12
13
14
15
FSMPS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
Reserved
0
0
FI
0
0
0
0
0
0
0
0
Figure 12-19. USB HC Frame Interval Register
Table 12-14. USB HC Frame Interval Register Field Descriptions
Bits
Name
Description
0
FIT
1:15
FSMPS
16:17
—
Reserved
18:31
FI
FrameInterval—specifies the bit-time interval between two consecutive SOFs. Nominally, this value is
set to 11,999. HCD should store the field’s current value before resetting HC. Setting the
HcCommandStatus HostControllerReset field causes the HC to reset this field to its nominal value.
HCD may choose to restore the stored value when the reset sequence completes.
FrameIntervalToggle—HCD toggles this bit when it loads a new value to the frame interval.
FSLargestDataPacket—specifies a value that is loaded into the largest data packet counter at the
beginning of each frame. The counter value represents the largest amount of data in bits that the HC
can send or received in a single transaction at any given time without causing scheduling overrun.
HCD calculates this field value.
MPC5200B User’s Manual, Rev. 3
12-22
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.4.2
USB HC Frame Remaining Register
This register is a 14-bit count-down counter containing the remaining current Frame bit-time.
Address MBAR + 0x1038
0
R
W
Reset
R
W
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
FRT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
Reserved
0
FR
0
0
0
0
0
0
0
0
0
Figure 12-20. USB HC Frame Remaining Register
Table 12-15. USB HC Frame Remaining Register Field Descriptions
Bits
Name
Description
0
FRT
1:17
—
Reserved
18:31
FR
FrameRemaining—is a counter that is decremented at each bit-time. When it reaches 0, it is reset by
loading the FrameInterval value specified in HcFmInterval at the next bit-time boundary.
When entering the USBOPERATIONAL state, HC reloads the content with the HcFmInterval
Frame Interval and uses the updated value from the next SOF.
FrameRemainingToggle—bit is loaded from the HcFmInterval FrameIntervalToggle field when
FrameRemaining reaches 0. HCD uses this bit for synchronization between FrameInterval and
FrameRemaining.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-23
Universal Serial Bus (USB)
12.4.4.3
USB HC Frame Number Register
The HC Frame Number register is a 16-bit counter. It provides a timing reference among events happening
in the HC and HCD. The HC driver may use the 16-bit value specified in this register and generate a 32-bit
frame number without requiring frequent access to the register.
Address MBAR + 0x103C
0
1
2
3
4
5
6
R
8
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
FN
W
Reset
9
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 12-21. USB HC Frame Number Register
Table 12-16. USB HC Frame Number Register Field Descriptions
Bits
Name
Description
16:31
FN
FrameNumber—is incremented when HcFmRemaining is re-loaded. FN rolls over to 0 after ffff.
When entering the USBOPERATIONAL state, this is automatically incremented. Content is written to
HCCA after HC has incremented the FN at each frame boundary and sent a SOF, but before HC reads
the first ED in that frame. After writing to HCCA, HC sets the HcInterruptStatus StartofFrame.
0:15
—
Reserved
MPC5200B User’s Manual, Rev. 3
12-24
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.4.4
USB HC Periodic Start Register
This register has a 14-bit programmable value that determines when is the earliest time HC should start
processing the periodic list.
Address MBAR + 0x1040
0
1
2
3
4
5
6
R
R
W
Reset
8
9
10
11
12
13
14
15
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
Reserved
0
0
PS
0
0
0
0
0
0
0
0
Figure 12-22. USB HC Periodic Start Register
Table 12-17. USB HC Periodic Start Register Field Descriptions
Bits
Name
Description
0:17
—
Reserved
18:31
PS
PeriodicStart—field is cleared after a hardware reset. PS is then set by HCD during HC initialization.
PS value is calculated roughly as 10% off from HcFmInterval. A typical value is 3E67.
When HcFmRemaining reaches the value specified, processing of periodic lists has priority over
Control/Bulk processing. HC then starts processing the Interrupt list after completing the current
Control or Bulk transaction in progress.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-25
Universal Serial Bus (USB)
12.4.4.5
USB HC LS Threshold Register
This register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a
maximum 8-Byte LS packet before EOF. Neither the HC nor HCD are allowed to change this value.
Address MBAR + 0x1044
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
R
Reserved
W
Reset
0
0
0
LST
0
0
0
0
0
0
0
0
Figure 12-23. USB HC LS Threshold Register
Table 12-18. USB HC LS Threshold Register Field Descriptions
Bits
Name
0:19
—
20:31
LST
Description
Reserved
LSThreshold—field contains a value which is compared to the FrameRemaining field prior to initiating
a low speed transaction. The transaction is started only if FrameRemaining is greater than or equal
to this field. HCD calculates this value with the consideration of transmission and setup overhead.
MPC5200B User’s Manual, Rev. 3
12-26
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.5
Root Hub Partition
This HC partition uses 5 32-bit registers. These registers are located at an offset from MBAR of 0x1048.
Register addresses are relative to this offset. Therefore, the actual register address is: MBAR + 0x1048 +
register address
The following registers are available:
• USB HC Rh Descriptor A Register (0x1048)
• USB HC Rh Descriptor B Register Field Descriptions (0x104C)
• USB HC Rh Status Register Field Descriptions (0x1050)
• USB HC Rh Port1 Status Register (0x1054)
• USB HC Rh Port2 Status Register (0x1058)
All registers included in this partition are dedicated to the USB root hub, which is an integral part of the
HC though still a functionally separate entity. HCD emulates USBD access to the root hub via a register
interface. HCD maintains many USB-defined hub features which are not required to be supported in
hardware. For example, the hub’s device, configuration, interface, and endpoint descriptors are maintained
only in the HCD and some class descriptor static fields. HCD also maintains and decodes the root hub
device address as well as other trivial operations better suited to software than hardware.
The root hub register interface is otherwise developed to maintain similarity of bit organization and
operation to typical hubs which are found in the system. Each register is read and written as a 32-bit word.
These registers are only written during initialization to correspond with the system implementation.
• HcRhDescriptorA and HcRhDescriptorB registers should be implemented such that they are
writeable regardless of the HC USB state.
• HcRhStatus and HcRhPortStatus must be writeable during the USBOPERATIONAL state.
NOTE
IS denotes an implementation-specific reset value for that field.
12.4.5.1
USB HC Rh Descriptor A Register
This register is the first of two registers describing the root hub characteristics. Reset values are
implementation-specific. The HCD emulates the following hub class descriptor fields:
• Descriptor length (11)
• Descriptor type (TBD)
• Hub controller current (0)
All other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-27
Universal Serial Bus (USB)
Address MBAR + 0x1048
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
0
R
Reserved
W
Reset
4
POTPGT
W
Reset
3
0
0
NOCP OCPM
0
1
0
DT
0
NPS PSM
1
0
NDP
0
0
0
0
0
Figure 12-24. USB HC Rh Descriptor A Register
Table 12-19. USB HC Rh Descriptor A Register Field Descriptions
Bits
Name
Description
0:7
POTPGT
8:18
—
19
NOCP
NoOverCurrentProtection—describes how the Root Hub port overcurrent status is reported. When
NOCP is cleared, OCPM specifies global or per-port reporting.
0 Overcurrent status is reported collectively for all downstream ports.
1 No overcurrent protection supported.
20
OCPM
OverCurrentProtectionMode—describes how the Root Hub port overcurrent status is reported.
At reset, OCPM should reflect the same mode as PowerSwitchingMode. OCPM is valid only if
NoOverCurrentProtection is cleared.
0 Overcurrent status is reported collectively for all downstream ports.
1 Overcurrent status is reported on a per-port basis.
21
DT
DeviceType—specifies Root Hub is not a compound device. Root Hub is not permitted to be a
compound device. DT should always read/write 0.
22
NPS
NoPowerSwitching—specifies whether power switching is supported or ports are always powered.
NPS is implementation specific. When this bit is cleared, PSM specifies global or per-port switching.
0 Ports are power switched.
1 Ports are always powered on when HC is powered on.
23
PSM
PowerSwitchingMode—specifies how the root hub port power switching is controlled. PSM is
implementation-specific and is only valid if the NoPowerSwitching field is cleared.
0 All ports are powered at the same time.
1 Each port is powered individually. This mode lets port power be controlled by either the global
switch or per-port switching.
• If PortPowerControlMask bit is set, port responds only to port power commands
(Set/ClearPor tPower).
• If port mask is cleared, port is controlled only by the global power switch
(Set/ClearGlobalPower).
24:31
NDP
NumberDownstreamPorts—specifies the number of downstream ports supported by the Root Hub.
NDP is implementation-specific.
• Minimum number of ports is 1.
• Maximum number of ports (supported by OpenHCI) is 15.
PowerOnToPowerGoodTime—specifies the duration HCD must wait before accessing a Root Hub
powered-on port. POTPGT is implementation-specific.
The time unit is 2ms. Duration is calculated as POTPGT x 2ms.
Reserved
MPC5200B User’s Manual, Rev. 3
12-28
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.5.2
USB HC Rh Descriptor B Register
This register is the second of two registers describing the Root Hub characteristics. These fields are written
during initialization to correspond with the system implementation. Reset values are
implementation-specific.
Address MBAR + 0x104C
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
DR
W
Reset
9
PPCM
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 12-25. USB HC Rh Descriptor B Register
Table 12-20. USB HC Rh Descriptor B Register Field Descriptions
Bits
Name
0:15
PPCM
16:31
DR
Description
PortPowerControlMask—each bit indicates whether a port is affected by a global power control
command when PSM is set.
• When set, port power state is only affected by per-port power control (Set/ClearPortPower).
• When cleared, port is controlled by the global power switch (Set/ClearGlobalPower).
If device is configured to Global Switching Mode (PSM=0), this field is not valid.
bit 0—Reserved
bit 1—Ganged-power mask on Port #1
bit 2—Ganged-power mask on Port #2
…
bit15—Ganged-power mask on Port #15
NDeviceRemovable—each bit is dedicated to a Root Hub port. When cleared, the attached device is
removable. When set, the attached device is not removable.
bit 0—Reserved
bit 1—Device attached to Port #1
bit 2—Device attached to Port #2
…
bit15—Device attached to Port #15
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-29
Universal Serial Bus (USB)
12.4.5.3
USB HC Rh Status Register
This register is divided into two parts. The lower 16 bits of a 32-bit word represents the hub status field;
the upper word represents the hub status change field. Reserved bits should always be written 0.
Address MBAR + 0x1050
0
R
W
Reset
R
W
Reset
1
2
3
4
5
6
CRWE
7
8
9
10
11
12
13
Reserved
14
15
OCIC
LPSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OCI
LPS
0
0
Reserved
DRWE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-26. USB HC Rh Status Register
Table 12-21. USB HC Rh Status Register Field Descriptions
Bits
Name
Description
0
CRWE
1:13
—
14
OCIC
OverCurrentIndicatorChange—is set by hardware when a change occurs to the OCI field of this
register.
• Writing 1 causes HCD to clear this bit.
• Writing 0 has no effect.
15
LPSC
LocalPowerStatusChange (read)—Root Hub does not support the local power status feature. Thus,
this bit is always read as 0.
SetGlobalPower (write)
• In global power mode (PSM=0), LPSC is written to 1 to turn on power to all ports (clear
PortPowerStatus).
• In per-port power mode, LPSC sets PortPowerStatus only on ports whose PPCM bit is not set.
Writing 0 has no effect.
16
DRWE
DeviceRemoteWakeUpEnable (write)—enables a ConnectStatusChange bit as a resume event,
causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
interrupt.
0 ConnectStatusChange is not a remote WakeUp event.
1 ConnectStatusChange is a remote WakeUp event.
SetRemoteWakeUpEnable (read).
1 Sets DRWE.
0 Has no effect.
17:29
—
ClearRemoteWakeUpEnable (write)
• Writing 1 clears DRWE.
• Writing 0 has no effect.
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
12-30
Freescale Semiconductor
Universal Serial Bus (USB)
Table 12-21. USB HC Rh Status Register Field Descriptions
Bits
Name
30
OCI
OverCurrentIndicator—reports overcurrent conditions when global reporting is implemented.
When set, an overcurrent condition exists.
When cleared, all power operations are normal.
If per-port overcurrent protection is implemented this bit is always 0.
31
LPS
LocalPowerStatus—Root Hub does not support the local power status feature. This bit is always read
as 0 (write) ClearGlobalPower.
In global power mode (PSM=0), bit is written to 1 to turn off power to all ports (clear
PortPowerStatus).
In per-port power mode, bit clears PortPowerStatus only on ports whose PPCM bit is not set.
Writing 0 has no effect.
12.4.5.4
Description
USB HC Rh Port1 Status Register
This register is controls and reports port events on a per-port basis. The Number of Downstream Ports
(NDP) represents the number of HcRhPortStatus registers that are implemented in hardware. The lower
16-bits is used to reflect the port status; the upper 16-bits reflects the status change bits. MPC5200B has
NDP = 2, therefore, HcRhPort1Status (MBAR + 1054) and HcRhPort2Status (MBAR + 1058).
Some status bits are implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status change is postponed until
the transaction completes. Reserved bits should always be written 0.
Address MBAR + 0x1054
0
1
2
3
4
R
7
8
9
10
11
PRSC
12
13
14
OCIC PSSC PESC
15
CSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PRS
POCI
PSS
PES
CCS
0
0
0
0
0
R
Reserved
W
Reset
6
Reserved
W
Reset
5
0
0
0
0
LSDA PPS
0
0
0
0
Reserved
0
0
0
Figure 12-27. USB HC Rh Port1 Status Register
Table 12-22. USB HC Rh Port1 Status Register Field Descriptions (Sheet 1 of 4)
Bits
Name
0:10
—
11
PRSC
Description
Reserved
PortResetStatusChange—bit is set at the end of the 10ms port reset signal.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 Port reset not complete
1 Port reset complete
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-31
Universal Serial Bus (USB)
Table 12-22. USB HC Rh Port1 Status Register Field Descriptions (Sheet 2 of 4)
Bits
Name
Description
12
OCIC
PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 No change in POCI
1 POCI has changed
13
PSSC
PortSuspendStatusChange—bit is set when the full resume sequence completes. Sequence includes
a 20s resume pulse, LS EOP, and 3ms resychronization delay.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 Resume not complete
1 Resume complete
14
PESC
PortEnableStatusChange—bit is set when hardware events cause the PES bit to be cleared.
Changes from HCD writes do not set this bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 No change in PES
1 Change in PES
15
CSC
16:21
—
22
LSDA
ConnectStatusChange—bit is set whenever a connect or disconnect event occurs.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
If CCS is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is
set to force the driver to re-evaluate the connection status since these writes should not occur if the
port is disconnected.
0 No change in CCS
1 Change in CCS
If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to notify the system
that the device is attached.
Reserved
LowSpeedDeviceAttached (read)—bit indicates the speed of the device attached to this port.
0 Full speed device attached
1 Low speed device attached
This field is valid only when CurrentConnectStatus is set.
ClearPortPower (write)
• Writing 1 causes HC to clear the PortPowerStatus bit.
• Writing 0 has no effect.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Universal Serial Bus (USB)
Table 12-22. USB HC Rh Port1 Status Register Field Descriptions (Sheet 3 of 4)
Bits
Name
Description
23
PPS
PortPowerStatus (read)—bit reflects the port power status, regardless of the type of power switching
implemented.
If an overcurrent condition is detected, this bit is cleared. HCD sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power
control switches are enabled is determined by PowerSwitchingMode and
PortPortControlMask[NDP].
In global switching mode (PSM=0), only Set/ClearGlobalPower controls this bit.
In per-port power switching (PSM=1), if the PortPowerControlMask[NDP] bit for the port is set, only
Set/ClearPortPower commands are enabled.
If the mask is not set, only Set/ClearGlobalPower commands are enabled.
If port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and
PortResetStatus should be reset.
0 Port power is off
1 Port power is on
SetPortPower (write)
• Writing causes HC to set the PortPowerStatus bit.
• Writing 0 has no effect.
If power switching is not supported, this bit always reads ‘1b’.
24:26
—
27
PRS
PortResetStatus (read)—When this bit is set by a write to SetPortReset, port reset signaling is
asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit
cannot be set if CurrentConnectStatus is cleared.
0 Port reset signal is not active
1 Port reset signal is active
SetPortReset (write)
• Writing 1 causes HC to set port reset signaling.
• Writing 0 has no effect.
If CurrentConnectStatus is cleared, a write does not set PortResetStatus. Instead, it sets
ConnectStatusChange. This notifies the driver that an attempt was made to reset a disconnected
port.
28
POCI
PortOverCurrentIndicator (read)—bit is only valid when root hub is configured in such a way that
overcurrent conditions are reported on a per-port basis.
If per-port overcurrent reporting is not supported, this bit is set to 0.
If cleared, all power operations are normal for this port.
If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal
0 No overcurrent condition.
1 Overcurrent condition detected.
ClearSuspendStatus (write)
• Writing 1 causes HC to initiate a resume.
• Writing 0 has no effect.
A resume is initiated only if PSS is set.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-33
Universal Serial Bus (USB)
Table 12-22. USB HC Rh Port1 Status Register Field Descriptions (Sheet 4 of 4)
Bits
Name
Description
29
PSS
PortSuspendStatus (read)—bit indicates port is suspended or in resume sequence. It is set by a
SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume
interval.
This bit cannot be set if CCS. This bit is cleared when:
• PortResetStatusChange is set at the end of the port reset, or
• when HC is placed in the USBRESUME state.
If an upstream resume is in progress, it should propagate to the HC.
0 Port is not suspended
1 Port is suspended
SetPortSuspend (write)
• Writing 1 causes HC to set PSS bit.
• Writing 0 has no effect.
If CurrentConnectStatus is cleared, this write does not set PSS. Instead it sets
ConnectStatusChange. This notifies the driver an attempt was made to suspend a disconnected port.
30
PES
PortEnableStatus (read)—indicates whether the port is enabled or disabled.
The Root Hub may clear this bit when the following conditions are detected:
• An overcurrent condition
• Disconnect event
• Switched-off power
• Operational bus error (such as babble)
This change causes PESC to be set. HCD sets this bit by writing SetPortEnable and clears it by
writing ClearPortEnable.
PES cannot be set when CurrentConnectStatus is cleared. If not already set, PES is set at the
completion of a port reset when ResetStatusChange is set or port suspend when
SuspendStatusChange is set.
0 Port is disabled
1 Port is enabled
SetPortEnable (write)—HCD sets PES by writing 1. Writing 0 has no effect.
If CCS is cleared, this write does not set PES, but instead sets CSC. This notifies the driver that an
attempt was made to enable a disconnected port.
31
CCS
CurrentConnectStatus (read)—reflects current state of downstream port.
0 No device connected
1 Device connected
ClearPortEnable (write)—HCD writes 1 to this bit to clear PortEnableStatus bit. Writing 0 has no
effect. CCS is not affected by any write.
Note: This bit is always read ‘1b’ when the attached device is non-removable
(DeviceRemovable[NDP]).
MPC5200B User’s Manual, Rev. 3
12-34
Freescale Semiconductor
Universal Serial Bus (USB)
12.4.5.5
USB HC Rh Port2 Status Register
This register is controls and reports port events on a per-port basis. The Number of Downstream Ports
(NDP) represents the number of HcRhPortStatus registers that are implemented in hardware. The lower
word is used to reflect the port status; the upper word reflects the status change bits. MPC5200B has
NDP = 2, therefore, HcRhPort1Status (MBAR + 1054) and HcRhPort2Status (MBAR + 1058).
Some status bits are implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status change is postponed until
the transaction completes. Reserved bits should always be written 0.
Address MBAR + 0x1058
0
1
2
3
4
R
7
8
9
10
11
PRSC
12
13
14
OCIC PSSC PESC
15
CSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PRS
POCI
PSS
PES
CCS
0
0
0
0
0
R
Reserved
W
Reset
6
Reserved
W
Reset
5
0
0
0
0
LSDA PPS
0
0
0
0
Reserved
0
0
0
Figure 12-28. USB HC Rh Port2 Status Register
Table 12-23. USB HC Rh Port2 Status Register Field Descriptions (Sheet 1 of 4)
Bits
Name
Description
0:10
—
11
PRSC
PortResetStatusChange—bit is set at the end of the 10ms port reset signal.
• Writing 1 clears this bit.
• Writing 0 has no effect.
0 Port reset not complete
1 Port reset complete
12
OCIC
PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit.
• Writing 1 clears this bit.
• Writing 0 has no effect.
0 No change in POCI
1 POCI has changed
13
PSSC
PortSuspendStatusChange—bit is set when the full resume sequence completes. Sequence includes
a 20s resume pulse, LS EOP, and 3ms resychronization delay.
• Writing 1 clears this bit.
• Writing 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 Resume not complete
1 Resume complete
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-35
Universal Serial Bus (USB)
Table 12-23. USB HC Rh Port2 Status Register Field Descriptions (Sheet 2 of 4)
Bits
Name
Description
14
PESC
15
CSC
16:21
—
22
LSDA
LowSpeedDeviceAttached (read)—bit indicates the speed of the device attached to this port.
0 Full speed device attached
1 Low speed device attached
This field is valid only when CurrentConnectStatus is set.
ClearPortPower (write)
• Writing 1 causes HC to clear the PortPowerStatus bit.
• Writing 0 has no effect.
23
PPS
PortPowerStatus (read)—bit reflects the port power status, regardless of the type of power switching
implemented.
If an overcurrent condition is detected, this bit is cleared. HCD sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power
control switches are enabled is determined by PowerSwitchingMode and
PortPortControlMask[NDP].
In global switching mode (PSM=0), only Set/ClearGlobalPower controls this bit.
In per-port power switching (PSM=1), if the PortPowerControlMask[NDP] bit for the port is set, only
Set/ClearPortPower commands are enabled.
If the mask is not set, only Set/ClearGlobalPower commands are enabled.
If port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and
PortResetStatus should be reset.
0 Port power is off
1 Port power is on
SetPortPower (write)
• Writing causes HCD to set the PortPowerStatus bit.
• Writing 0 has no effect.
If power switching is not supported, this bit always reads ‘1b’.
24:26
—
PortEnableStatusChange—bit is set when hardware events cause the PES bit to be cleared.
• Writing 1clears this bit.
• Writing 0 has no effect.
0 No change in PES
1 Change in PES
ConnectStatusChange—bit is set whenever a connect or disconnect event occurs.
• Writing 1 clears this bit.
• Writing 0 has no effect.
If CCS is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is
set to force the driver to re-evaluate the connection status since these writes should not occur if the
port is disconnected.
0 No change in CCS
1 Change in CCS
If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to notify the system
that the device is attached.
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
12-36
Freescale Semiconductor
Universal Serial Bus (USB)
Table 12-23. USB HC Rh Port2 Status Register Field Descriptions (Sheet 3 of 4)
Bits
Name
Description
27
PRS
PortResetStatus (read)—When this bit is set by a write to SetPortReset, port reset signaling is
asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit
cannot be set if CurrentConnectStatus is cleared.
0 Port reset signal is not active
1 Port reset signal is active
SetPortReset (write)
• Writing 1 causes HCD to set port reset signaling.
• Writing 0 has no effect.
If CurrentConnectStatus is cleared, a write does not set PortResetStatus. Instead, it sets
ConnectStatusChange. This notifies the driver that an attempt was made to reset a disconnected
port.
28
POCI
PortOverCurrentIndicator (read)—bit is only valid when root hub is configured in such a way that
overcurrent conditions are reported on a per-port basis.
If per-port overcurrent reporting is not supported, this bit is set to 0.
If cleared, all power operations are normal for this port.
If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal
0 No overcurrent condition.
1 Overcurrent condition detected.
ClearSuspendStatus (write)
• Writing 1 causes HC to initiate a resume.
• Writing 0 has no effect.
A resume is initiated only if PSS is set.
29
PSS
PortSuspendStatus (read)—bit indicates port is suspended or in resume sequence. It is set by a
SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume
interval.
This bit cannot be set if CCS. This bit is cleared when:
• PortResetStatusChange is set at the end of the port reset, or
• when HC is placed in the USBRESUME state.
If an upstream resume is in progress, it should propagate to the HC.
0 Port is not suspended
1 Port is suspended
SetPortSuspend (write)
• Writing 1 causes HCD to set PSS bit.
• Writing 0 has no effect.
If CurrentConnectStatus is cleared, this write does not set PSS. Instead it sets
ConnectStatusChange. This notifies the driver an attempt was made to suspend a disconnected port.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
12-37
Universal Serial Bus (USB)
Table 12-23. USB HC Rh Port2 Status Register Field Descriptions (Sheet 4 of 4)
Bits
Name
Description
30
PES
PortEnableStatus (read)—indicates whether the port is enabled or disabled.
The Root Hub may clear this bit when the following conditions are detected:
• An overcurrent condition
• Disconnect event
• Switched-off power
• Operational bus error (such as babble)
This change causes PESC to be set. HCD sets this bit by writing SetPortEnable and clears it by
writing ClearPortEnable.
PES cannot be set when CurrentConnectStatus is cleared. If not already set, PES is set at the
completion of a port reset when ResetStatusChange is set or port suspend when
SuspendStatusChange is set.
0 Port is disabled
1 Port is enabled
SetPortEnable (write)—HCD sets PES by writing 1. Writing 0 has no effect.
If CCS is cleared, this write does not set PES, but instead sets CSC. This notifies the driver that an
attempt was made to enable a disconnected port.
31
CCS
CurrentConnectStatus (read)—reflects current state of downstream port.
0 No device connected
1 Device connected
ClearPortEnable (write)—HCD writes 1 to this bit to clear PortEnableStatus bit. Writing 0 has no
effect. CCS is not affected by any write.
Note: This bit is always read ‘1b’ when the attached device is non-removable
(DeviceRemovable[NDP]).
MPC5200B User’s Manual, Rev. 3
12-38
Freescale Semiconductor
Chapter 13
BestComm
13.1
Overview
The following sections are contained in this document:
• Section 13.2, “BestComm Functional Description”
• Section 13.15, “BestComm DMA Registers”
• Section 13.16, “On-Chip SRAM”
BestComm provides an efficient, integrated approach to gathering and manipulating data sets from a broad
range of communication interfaces. The DMA controller reduces the workload on the microprocessor,
allowing it to continue execution of system software. The DMA microcode engine is tailored to efficiently
transfer data across the internal bus architecture to memory and peripheral devices.
The DMA controller processes microcode tasks that are stored in local memory (SRAM 16 kBytes). A task
is a sequence of instructions, referred to as descriptors, that specifies a series of data movements or
manipulations. The DMA controller steps through the descriptors and executes the specified function in a
similar fashion to a CPU executing a program.
For the MPC5200B, BestComm consists of SDMA and the following peripheral interfaces:
• 10/100 Fast Ethernet Controller (FEC)
• I2C
• PCI
• ATA
• LocalPlus
• PSC—Peripheral Serial Controller (implementing a different mix of functionalities such as SPI,
UART, CODEC 8-16-32 bits, AC97 controller, I2S, IrDA controller)
Many of the peripherals’ port pins serve multiple functions, allowing flexibility in optimizing the system
to meet a specific set of integration requirements. For a description of the pin multiplexing scheme and
supported functions, refer to Chapter 2, “Signal Descriptions”.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-1
BestComm
Other peripheral functions are included in MPC5200B, but are not directly supported by BestComm.
These peripherals include:
• A separate Serial Peripheral Interface (SPI), which:
— Supports a 6.25MHz rate as a master
— Supports a 12.5MHz rate as a slave
• USB Host/Hub controller
• MSCAN controller
• General Purposes Timers
13.2
BestComm Functional Description
The BestComm I/O subsystem consists of the following:
• A BestComm DMA Controller
• An on-chip 16 kBytes SRAM
• A set of peripheral interface modules with DMA controllable:
— Transmit (Tx)
— Receive (Rx)
The BestComm unit provides an interrupt control and data movement interface. The Interface is on a
separate peripheral bus to several on-chip peripheral functions. This independent control of data
movement leaves the e300 core free to concentrate on higher level activities, which increases overall
system performance.
BestComm DMA can control data movement on the following peripherals and interfaces:
• PCI bus
• ATA Controller
• Ethernet
• PSC
• I2C
• IrDA
• LP bus interface
NOTE
It is possible for the BESTComm DMA to produce misaligned word
addresses on its Slave and Comm bus. These accesses occur due to incorrect
program code executed by the BestComm unit. Any misaligned access will
be incorrectly processed on the internal SRAM bus and the Comm bus.
The work around is to avoid using misaligned accesses. That is, BestComm
program code must be written such that misaligned word accesses will not
occur.
BestComm DMA performs general purpose DMA transfers. Most data transactions are between the
peripheral/interface (typically a FIFO) and the system SDRAM.
MPC5200B User’s Manual, Rev. 3
13-2
Freescale Semiconductor
BestComm
BestComm allows up to 16 tasks to run simultaneously under the control of up to 32 DMA hardware
requestors, user selectable from a possible 64 DMA request sources.
A hardware logic unit capable of basic logic operations (boolean arbitrary operations, shift, byte swap)
plus some precoded CRC (CRC-16, CRC-CCITT, CRC-32, Internet Checksum) is also integrated in the
SDMA engine.
BestComm uses internal buffers to prefetch reads and post writes such that bursting is used whenever
possible. This optimizes both internal and external bus activity.
Speculative reads from system SDRAM may also be enabled to increase performance.
FIFO interfaces are implemented between the DMA and each peripheral/interface. As FIFOs are filled or
emptied, automatic requests are made to the DMA unit. Based on programmable water mark levels (called
ALARM and GRANULARITY level), the DMA unit moves data to and from the FIFOs. This method
insures uninterrupted data movement at the given peripheral/interface rate.
13.3
•
•
•
•
•
•
•
•
•
•
•
•
13.4
Features Summary
A programmatic, deterministic capability for managing bus resources while servicing many data
streams with individual latency and processing requirements.
Single cycle access of peripheral and memory data.
Support for up to 16 simultaneously enabled tasks (channels).
Support for up to 32 separate DMA requestors at a time, user selectable from a possible 64 DMA
request sources.
Support for operations with up to 12 sources, or 11 sources and 1 destination.
Simultaneous 32-bit reads and writes.
Checksum generation.
Endian conversion.
Chaining/Scatter-gather capability.
Support for packet-based I/O protocols (limitation might be dictated by performance when too
much control is implemented within the task).
External DMA Request.
External DMA breakpoint.
Descriptors
The DMA controller interprets a series of descriptors that specifies a sequence of data movements and
manipulations. A collection of these descriptors is much like a program. The two types of descriptors are
Loop Control Descriptors (LCDs) and Data Routing Descriptors (DRDs). These descriptors allow a
“for”-loop programming style for the SDMA engine.
The LCDs specify the index variables (memory pointers, byte counters, etc.) along with the termination
and increment values, while the DRDs specify the nature of the operation to perform.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-3
BestComm
13.5
Tasks
A task is a microcode program that embodies a desired function. An example could be to gather an ethernet
frame, store it in memory and interrupt the processor when done. The multi-channel DMA supports sixteen
simultaneously enabled tasks. By dynamically swapping task pointers in the task table, an unlimited
number of tasks could be supported.
13.6
Memory Map/ Register Definitions
Memory organization is described in the register array pointed to by the Task Base Address Register
(TaskBAR).
The TaskBAR identifies a location for a table of pointers to multi-channel DMA tasks (Task TABLE or
Entry Table).
Each task has an entry (8 long words) that contains information about the microcode’s location (start
address and stop address) in memory as well as pointers to the variable table to be used in the task, the
Function Descriptor Table for the logic functions used within the task, the Context Save area used during
task switch/swap and some specific flags to enable performance affecting modes such as speculative reads,
prefetch enable, readline and combined write.
A task’s code should always be loaded into SRAM as the SDMA engine can fetch its descriptors from this
internal memory with one cycle access per instruction. It is not recommended to place the code in SDRAM
as there will then be a few overhead clocks which are needed to load the SDMA instruction unit.
13.7
Task Table (Entry Table)
The Task Table (or Entry Table) is a memory region containing pointers to each SDMA task. A Task Table
Base Address Register (taskBAR) sets the location of the Task Table itself. Each entry in the Task Table
contains pointers to the task’s first descriptor, last descriptor, Variable Table, and other task-specific
information.
13.8
Task Descriptor Table
Each Task Descriptor Table is a memory region containing the descriptors that comprise the task. The
pointers in the Task Table define the beginning and end of each Task Descriptor Table.
13.9
Variable Table
Each task has a private 32-word Variable Table, where a word is four bytes (32 bits). According to the
application requirements, the user initializes some of the words in the Variable Table as follows. The first
24 words are for pointers, counter values and initial data. The DMA Engine manipulates these variables
as it executes loops. The next 8 words hold words-aligned, two-byte (“short word” or 16 bit word)
increment variables.
MPC5200B User’s Manual, Rev. 3
13-4
Freescale Semiconductor
BestComm
13.10 Function Descriptor Table
An area of 256 bytes divided in 4 groups of 64 bytes. Each group can represent a set of 16 different Logic
Functions belonging to a single execution unit. Every function is encoded with a single word (32 bits).
The implemented SDMA engine uses only one out of four potential Execution Units, execution unit 3, so
all the functions needed by the task will be encoded in the third group (starting at offset 0xC0 from the
start address of the Function Descriptor Table). The other words are reserved and must be written to ‘0’ to
maintain memory alignment.
For space optimization, tasks which use the same logic functions could share a single Function Descriptor
Table avoiding the redundancy of re-writing the same table many times in SRAM.
13.11 Context Save Area
This is an area allocated for each task to allow the SDMA engine to save vital data (such as index values,
etc.) during a task switch operation to allow later restoration.
The context save area should never be used or modified by the user as it is managed directly by the SDMA
engine.
13.12 External DMA Request
BestComm supports 64 user selectable request sources. 32 of them are controllable via GPIO pins, see
SDMA Request MuxControl Register. This GPIO group is split up into two different kind of GPIO’s, 24
simple and 8 simple interrupt GPIO’s. The differences are:
• Simple GPIO’s: The external request event must be kept asserted until the first, intended data
transaction is executed.
• Simple interrupt GPIO’s: The external request event can be deasserted before the first, intended
data transaction has started. Additionally, the external request can generate an interrupt for the e300
core.
The GPIO, which is intended to generate a DMA request, must be enabled and set up as input, in both cases
(see Section 7.3, “General Purpose I/O (GPIO)”).
NOTE
MPC5200B doesn’t support external DMA Acknowledge.
13.13 External DMA Breakpoint
The SDMA engine can be halted if the Enable Breakpoint (EB) and the Enable External Breakpoint (E)
bits of the SDMA Debug Module Control Register are set and the 603e e300 core hits an Instruction
Address Breakpoint or a Data Address Breakpoint.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-5
BestComm
13.14 BestComm XLB Address Snooping
BestComm prefetches data from the XLB into 4 32-Byte wide Read Line Buffers. A buffer will be
invalidated, if the BestComm XLB Address Snooping (BSDIS) is enabled, see Chapter 16, “XLB
Arbiter”, and a write operation on the XLB to the prefetched data address happens. No invalidation of the
buffer will happen if the BSDIS bit is set. BestComm will still use the old prefetched data.
13.15 BestComm DMA Registers
A register overview is provided in Section 3.2, “Internal Register Memory Map”.
13.15.1 Register Descriptions
Hyperlinks to the BestComm DMA registers are provided below:
• SDMA Task Bar Register (0x1200)
• SDMA Current Pointer Register (0x1204)
• SDMA End Pointer Register (0x1208)
• SDMA Variable Pointer Register (0x120C)
• SDMA Interrupt Vector, PTD Control Register Field Descriptions (0x1210)
• SDMA Interrupt Pending Register (0x1214)
• SDMA Interrupt Mask Register (0x1218)
• SDMA Task Control 0 and 1 Registers (0x121C)
• SDMA Task Control 2 and 3 Registers (0x1220)
• SDMA Task Control 4 and 5 Registers (0x1224)
• SDMA Task Control 6 and 7 Registers (0x1228)
• SDMA Task Control 8 and 9 Registers (0x122C)
• SDMA Task Control A and B Registers (0x1230)
• SDMA Task Control C and D Registers (0x1234)
• SDMA Task Control E and F Registers (0x1238)
• SDMA Initiator Priority 0, 1, 2, and 3 Registers (0x123C)
• SDMA Initiator Priority 4, 5, 6, and 7 Registers (0x1240)
• SDMA Initiator Priority 8, 9, 10, and 11 Registers (0x1244)
• SDMA Initiator Priority 12, 13, 14, and 15 Registers (0x1248)
• SDMA Initiator Priority 16, 17, 18, and 19 Registers (0x124C)
• SDMA Initiator Priority 20, 21, 22, and 23 Registers (0x1250)
• SDMA Initiator Priority 24, 25, 26, and 27 Registers (0x1254)
• SDMA Initiator Priority 28, 29, 30, and 31 Registers (0x1258)
• SDMA Request MuxControl (0x125C)
• SDMA Task Size 0/1 Field Descriptions (0x1260)
• SDMA Task Size 0/1 Field Descriptions (0x1264)
MPC5200B User’s Manual, Rev. 3
13-6
Freescale Semiconductor
BestComm
•
•
•
•
SDMA Debug Module Comparator 1, Value1 Register (0x1270)
SDMA Debug Module Comparator 2, Value2 Register (0x1274)
SDMA Debug Module Control Register (0x1278)
SDMA Debug Module Status Register (0x127C)
13.15.1.1 SDMA Task Bar Register
Address MBAR + 0x1200
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
taskBar
W
Reset
9
taskBar
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-1. SDMA Task Bar Register
Table 13-1. SDMA Task Bar Register Field Description
Bit
Name
0:31
taskBar
Description
TaskBAR is the pointer to the base address of the Task Table (Entry Table)
13.15.1.2 SDMA Current Pointer Register
Address MBAR + 0x1204
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
CurrentPointer
W
Reset
8
CurrentPointer
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 13-2. SDMA Current Pointer Register
Table 13-2. SDMA Current Pointer Register Field Description
Bit
Name
0:31
CurrentPointer
Description
CurrentPointer contains the address of the currently executing DMA descriptor.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-7
BestComm
13.15.1.3 SDMA End Pointer Register
Address MBAR + 0x1208
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
EndPointer
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
EndPointer
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-3. SDMA End Pointer Register
Table 13-3. SDMA End Pointer Register Field Descriptions
Bit
Name
0:31
endPointer
Description
EndPointer contains the address of the last descriptor in the currently executing SDMA task.
13.15.1.4 SDMA Variable Pointer Register
Address MBAR + 0x120C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
VariablePointer
W
Reset
8
VariablePointer
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 13-4. SDMA Variable Pointer Register
Table 13-4. SDMA Variable Pointer Register Field Descriptions
Bit
Name
0:31
variablePointer
Description
VariablePointer contains the starting address of the variable table for the currently executing
task.
MPC5200B User’s Manual, Rev. 3
13-8
Freescale Semiconductor
BestComm
13.15.1.5 SDMA Interrupt Vector, PTD Control Register
Address MBAR + 0x1210
0
1
R
R
W
Reset
3
4
Vector A[7:6]
W
Reset
2
5
6
7
8
9
INA[3:0]
10
11
12
13
Vector B[7:6]
14
15
INB[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
T/I
TEA
HE
0
0
0
Reserved
0
0
0
0
0
0
0
PE
0
0
0
0
0
0
Figure 13-5. SDMA Interrupt Vector, PTD Control Register
Table 13-5. SDMA Interrupt Vector, PTD Control Register Field Descriptions
Bit
Name
Description
0:7
IntVect1
The Interrupt Vector register is used during interrupt acknowledge read cycles. The high order four
bits are programmed by the user, and the low order four bits are decoded from either the current
task number or execution unit. If any task interrupts are asserted, Interrupt Vector 1 is driven
during the interrupt acknowledge cycle. If the task interrupts are negated and the execution unit
interrupts are asserted, Interrupt Vector 2 is driven during the interrupt acknowledge cycle. The
registers are set to the uninitialized vector $0F by system reset.
The interrupt A number is prioritized with IPR[15] the highest and IPR[0] the lowest. If all interrupt
mask bits are set, then INA[3:0] = 1111 is read from this location.
The interrupt B number is prioritized with the dbgInterrupt as the highest and euInterrupt[0] the
lowest. If all interrupt mask bits are set, then INB[3:0] = 1111 is read from this location.
8:15
IntVect2
See above
16
T/I
17
TEA
TEA: If set to ‘1’ a TEA received by BestComm will be ignored and the task will NOT be halted.
TEA indication can still trigger an interrupt if the proper mask bit is cleared in the Interrupt Mask
Register and the TEA status bit plus the TASK number of the task which received the TEA are still
updated in the Interrupt Pending Register.
18
HE
HE = 1; allows smartDMA higher task number same request priority to block current task, and
allow arbitration.
HE = 0; disables higher task number from blocking. This bit is cleared by reset.
19:30
—
Reserved
31
PE
Prefetch Disable: set to ‘1’ to disable prefetch. Set to ‘0’ to enable prefetch on CommBus
T/I: Task/Iniator priority. Set to ‘1’ to switch to “TASK priority” control; set to ‘0’ to revert to
INITIATOR (Requestor) Priority mode.
The priority level of either the TASK or the initiator is set in the register IPR0 through IPR31
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-9
BestComm
13.15.1.6 SDMA Interrupt Pending Register
Address MBAR + 0x1214
0
R
W
Reset
1
2
3
Rsvd
DBG
4
TEA
5
6
8
9
10
Etn[3:0]
11
12
13
14
15
EU[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TASK[15:0]
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 13-6. SDMA Interrupt Pending Register
Table 13-6. SDMA Interrupt Pending Register Field Descriptions
Bit
Name
Description
0
DBG
1:2
—
3
TEA
4:7
Etn[3:0]
Error Task Number: when a TEA is received by the currently executing task its
corresponding number is indicated here. If the TEA bit of the PtdControl register
is set then the task will not be halted. If the TEA Msk bit in the Mask register is
set then no interrupt to the core will be generated.
8:15
EU[7-0]
Execution Unit: only EU3 is valid for MPC5200B
16:31
TASK[15:0]
Debug
Reserved
A TEA has been received by the currently running task. The corresponding
task number is written in the Error Task Number field
Each bit corresponds to an interrupt source defined by the task number or execution unit. This
register contains a registered copy of the interrupt signal that the interrupting source generates.
The corresponding bit in the register reflects the state of the interrupt signal even if the
corresponding mask bit is set. An interrupt is masked by setting the corresponding bit in the
IntMask register. A bit is cleared by writing 1 to that bit location. Writing 0 has no effect. At system
reset, all bits are initialized to logic 0.
0 The corresponding interrupt source is not pending.
1 The corresponding interrupt source is pending.
MPC5200B User’s Manual, Rev. 3
13-10
Freescale Semiconductor
BestComm
13.15.1.7 SDMA Interrupt Mask Register
Address MBAR + 0x1218
0
R
W
Reset
1
DBG
2
3
Reserved
4
TEA
Msk
5
6
8
9
10
Reserved
11
12
13
14
15
EU[7:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
R
TASK[15:0]
W
Reset
7
1
1
1
1
1
1
1
1
1
Figure 13-7. SDMA Interrupt Mask Register
Table 13-7. SDMA Interrupt Mask Register Field Descriptions
Bit
Name
0
DBG
1:2
—
3
TEA Msk
4:7
—
8:15
EU[x]
16:31
TASK[15:0]
Description
Debug: set to ‘1’ to mask the “debug” interrupt (see the SDMA Debug Control Register)
Reserved
TEA Mask: set to ‘1’ to mask the TEA. If set to ‘1’ and a TEA is received in the currently executing
Task an interrupt is generated.
Reserved
Execution Unit: Only EU3 is present in MPC5200B
Each bit corresponds to an interrupt source defined by the task number or execution unit.
An interrupt is masked by setting the corresponding bit. At system reset, all bits are initialized to
logic 1.
0 The corresponding interrupt source is not masked.
1 The corresponding interrupt source is masked (no interrupt is generated).
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-11
BestComm
13.15.1.8 SDMA Task Control 0 Register
SDMA Task Control 1 Register
Address MBAR + 0x121C, 0x121E
R
W
Reset
0
1
2
3
4
5
En
Val
Alw
Init
0
0
0
0
0
0
0
16
17
18
19
20
21
22
7
8
9
10
11
Auto
Start
High
En
Hold
Rsvd
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
IN[4:0]
R
12
13
14
15
AS [3:0]
TCR1 (same as for TCR0)
W
Reset
6
0
0
0
0
0
0
0
0
0
0
Figure 13-8. SDMA Task Control 0 and 1 Registers
Table 13-8. SDMA Task Control 0 and 1 Register Field Descriptions
Bit
Name
Description
0
EN
Each of the sixteen tasks has an associated task control register. Only one register is shown. At
system reset, all bits are initialized to logic zeros.
Enable =Task Enable
0 Disabled
1 Enabled
This bit can be set or cleared by the programmer at any time when a task is enabled or disabled.
This bit is also set by the PTD logic if the auto-restart bit is set and the task completes.
1
Val
Valid—Initiator Number is Valid
0 Initiator is not valid
1 Initiator is valid
This bit is set by the engine logic when it obtains the requestor value from the first DRD that is
parsed. This bit is cleared by the logic when the task completes. At system reset, this bit is cleared.
2
Alw Init
Always Init—Decode of the always initiator
0 The always initiator is not being used
1 The always initiator is being used
This bit is a status bit only and is set and cleared by writing the initiator number into the Task
Control Register.
3:7
IN[4:0]
InitNum[4:0]—Initiator number from task descriptor
These bits are registered when the SDMA engine has parsed the first DRD to obtain the requestor
number. These bits are cleared by system reset. These bits can be written by the programmer
when the Hold Init Num bit is set or being set and the task is not enabled.
At system reset, these bits are cleared.
8
Auto Start
Auto-Start—Task Start
0Task will not restart within program control
1 Task will restart at end of task automatically.
This bit can be set or cleared by the programmer at any time. This bit is also cleared if the SDMA
engine encounters an error in the task. At system reset, this bit is cleared.
MPC5200B User’s Manual, Rev. 3
13-12
Freescale Semiconductor
BestComm
Table 13-8. SDMA Task Control 0 and 1 Register Field Descriptions (continued)
Bit
Name
Description
9
High En
High-Enable—High Priority Task Enable
0 Normal task enable control
1 High priority task enable control
This bit can be set or cleared by the programmer at any time. This bit enables the SDMA to give
priority to the enabled task function over running a task. At system reset, this bit is cleared.
10
Hold
Hold Init Num- Hold initiator number
0 Allow the SDMA engine to update initiator number for task
1 Keep current initiator number.
This bit allows the initiator number to be set by the programmer and held for the complete task.
The SDMA can not overwrite the programmed initiator except for the use of the always initiator
which is contained in a separate control bit.
11
—
12-15
AS[3:0]
16:31
TCR1
Reserved
ASNum[3:0]—Auto-Start Task Number
These four bits contain the task number which will be auto-started when the Auto-Start control bit
is set. At system reset, these bits are cleared.
Task control register for task 1. Same bit layout as for TCR0
13.15.1.9 SDMA Task Control 2 Register
SDMA Task Control 3 Register
Address MBAR + 0x1220,
0x1222
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCR3
W
Reset
9
TCR2
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-9. SDMA Task Control 2 and 3 Registers
Table 13-9. SDMA Task Control 2 and 3 Register Field Descriptions
Bit
Name
Description
0:15
TCR2
Task control register for task 2. Same bit layout as for TCR0
16:31
TCR3
Task control register for task 3. Same bit layout as for TCR0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-13
BestComm
13.15.1.10 SDMA Task Control 4 Register
SDMA Task Control 5 Register
Address MBAR + 0x1224, 0x1226
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCR5
W
Reset
9
TCR4
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-10. SDMA Task Control 4 and 5 Registers
Table 13-10. SDMA Task Control 4 and 5 Register Field Descriptions
Bit
Name
Description
0:15
TCR4
Task control register for task 4. Same bit layout as for TCR0
16:31
TCR5
Task control register for task 5. Same bit layout as for TCR0
13.15.1.11 SDMA Task Control 6 Register
SDMA Task Control 7 Register
Address MBAR + 0x1228, 0x122A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TCR6
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCR7
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-11. SDMA Task Control 6 and 7 Registers
Table 13-11. SDMA Task Control 6 and 7 Register Field Descriptions
Bit
Name
Description
0:15
TCR6
Task control register for task 6. Same bit layout as for TCR0
16:31
TCR7
Task control register for task 7. Same bit layout as for TCR0
MPC5200B User’s Manual, Rev. 3
13-14
Freescale Semiconductor
BestComm
13.15.1.12 SDMA Task Control 8 Register
SDMA Task Control 9 Register
Address MBAR + 0x122C, 0x122E
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCR9
W
Reset
9
TCR8
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-12. SDMA Task Control 8 and 9 Registers
Table 13-12. SDMA Task Control 8 and 9 Register Field Descriptions
Bit
Name
Description
0:15
TCR8
Task control register for task 8. Same bit layout as for TCR0
16:31
TCR9
Task control register for task 9. Same bit layout as for TCR0
13.15.1.13 SDMA Task Control A Register
SDMA Task Control B Register
Address MBAR + 0x1230, 0x1232
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCRB
W
Reset
9
TCRA
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-13. SDMA Task Control A and B Registers
Table 13-13. SDMA Task Control A and B Register Field Description
Bit
Name
Description
0:15
TCRA
Task control register for task 10. Same bit layout as for TCR0
16:31
TCRB
Task control register for task 11. Same bit layout as for TCR0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-15
BestComm
13.15.1.14 SDMA Task Control C Register
SDMA Task Control D Register
Address MBAR + 0x1234, 0x1236
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCRD
W
Reset
9
TCRC
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-14. SDMA Task Control C and D Registers
Table 13-14. SDMA Task Control C and D Register Field Descriptions
Bit
Name
Description
0:15
TCRC
Task control register for task 12. Same bit layout as for TCR0
16:31
TCRD
Task control register for task 13. Same bit layout as for TCR0
13.15.1.15 SDMA Task Control E Register
SDMA Task Control F Register
Address MBAR + 0x1238, 0x123A
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
TCRF
W
Reset
9
TCRE
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-15. SDMA Task Control E and F Registers
Table 13-15. SDMA Task Control E and F Registers
Bit
Name
Description
0:15
TCRE
Task control register for task 14. Same bit layout as for TCR0
16:31
TCRF
Task control register for task 15. Same bit layout as for TCR0
MPC5200B User’s Manual, Rev. 3
13-16
Freescale Semiconductor
BestComm
13.15.1.16 SDMA Initiator Priority 0 Register
SDMA Initiator Priority 1 Register
SDMA Initiator Priority 2 Register
SDMA Initiator Priority 3 Register
Address MBAR + 0x123C, 0x123D, 0x128E, 0x123F
0
R
W
Reset
1
IPR0
Hold
2
4
5
Reserved
6
7
8
9
10
11
Prior [2:0]
12
13
14
15
IPR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR2
W
Reset
3
0
0
0
0
IPR3
0
0
0
0
0
0
0
0
0
Figure 13-16. SDMA Initiator Priority 0, 1, 2, and 3 Registers
Table 13-16. SDMA Initiator Priority 0, 1, 2, and 3 Register Field Descriptions
Bit
Name
Description
Each of the thirty-two initiators has an associated priority level. Only one register is shown. All bits are set to ‘0 at reset.
0
IPR0 Hold
Hold—Keep current priority of initiator
0 = Allow higher priority initiator to block current initiator
1 = Hold current initiator priority level
This bit can be set or cleared by the programmer at any time. This bit allows the current initiator
to hold priority until the initiator has negated or the task has finished. When this bit is cleared, an
initiator with a higher priority will block the current initiator and force arbitration. At system reset,
this bit is cleared.
1:4
—
Reserved
5:7
Prior[2:0]
8:15
IPR1
Initiator Priority register for initiator 1 (or Task1 if PtdControl[16]=1).
Same bit layout as IPR0
16:23
IPR2
Initiator Priority register for initiator 2.(or Task2 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR3
Initiator Priority register for initiator 3.(or Task3 if PtdControl[16]=1)
Same bit layout as IPR0
InitPrior[2:0]—Initiator/Task priority level.
These bits can be set by the programmer at any time. These bits control the priority of the
requestor/task which will be serviced next depending on the setting of the T/I bit in the PtdControl
register.
The highest priority is level 7. The lower priority is level 0. If more than one initiator/task contains
the same priority then the order of the task within the Task table (task 7 highest to task 0 lowest)
will set the priority.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-17
BestComm
13.15.1.17 SDMA Initiator Priority 4 Register
SDMA Initiator Priority 5 Register
SDMA Initiator Priority 6 Register
SDMA Initiator Priority 7 Register
Address MBAR + 0x1240, 0x1241, 0x1242, 0x1243
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR6
W
Reset
4
IPR4
W
Reset
3
0
0
0
0
IPR7
0
0
0
0
0
0
0
0
0
Figure 13-17. SDMA Initiator Priority 4, 5, 6, and 7 Registers
Table 13-17. SDMA Initiator Priority 4, 5, 6, and 7 Register Field Descriptions
Bit
Name
Description
0:7
IPR4
Initiator Priority register for initiator 4 (or Task4 if PtdControl[16]=1)
Same bit layout as IPR0
8:15
IPR5
Initiator Priority register for initiator 5 (or Task5 if PtdControl[16]=1)
Same bit layout as IPR0
16:23
IPR6
Initiator Priority register for initiator 6 (or Task6 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR7
Initiator Priority register for initiator 7 (or Task7 if PtdControl[16]=1)
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
13-18
Freescale Semiconductor
BestComm
13.15.1.18 SDMA Initiator Priority 8 Register
SDMA Initiator Priority 9 Register
SDMA Initiator Priority 10 Register
SDMA Initiator Priority 11 Register
Address MBAR + 0x1244, 0x1245, 0x1246, 0x1247
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR10
W
Reset
4
IPR8
W
Reset
3
0
0
0
0
IPR11
0
0
0
0
0
0
0
0
0
Figure 13-18. SDMA Initiator Priority 8, 9, 10, and 11 Registers
Table 13-18. SDMA Initiator Priority 8, 9, 10, and 11 Register Field Descriptions
Bit
Name
Description
0:7
IPR8
Initiator Priority register for initiator 8 (or Task8 if PtdControl[16]=1)
Same bit layout as IPR0
8:15
IPR9
Initiator Priority register for initiator 9 (or Task9 if PtdControl[16]=1)
Same bit layout as IPR0
16:23
IPR10
Initiator Priority register for initiator 10 (or Task10 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR11
Initiator Priority register for initiator 11 (or Task11 if PtdControl[16]=1)
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-19
BestComm
13.15.1.19 SDMA Initiator Priority 12 Register
SDMA Initiator Priority 13 Register
SDMA Initiator Priority 14 Register
SDMA Initiator Priority 15 Register
Address MBAR + 0x1248, 0x1249, 0x124A, 0x124B
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR14
W
Reset
4
IPR12
W
Reset
3
0
0
0
0
IPR15
0
0
0
0
0
0
0
0
0
Figure 13-19. SDMA Initiator Priority 12, 13, 14, and 15 Registers
Table 13-19. SDMA Initiator Priority 12, 13, 14, and 15 Register Field Descriptions
Bit
Name
Description
0:7
IPR12
Initiator Priority register for initiator 12 (or Task12 if PtdControl[16]=1)
Same bit layout as IPR0
8:15
IPR13
Initiator Priority register for initiator 13 (or Task13 if PtdControl[16]=1)
Same bit layout as IPR0
16:23
IPR14
Initiator Priority register for initiator 14 (or Task14 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR15
Initiator Priority register for initiator 15 (or Task15 if PtdControl[16]=1)
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
13-20
Freescale Semiconductor
BestComm
13.15.1.20 SDMA Initiator Priority 16 Register
SDMA Initiator Priority 17 Register
SDMA Initiator Priority 18 Register
SDMA Initiator Priority 19 Register
Address MBAR + 0x124C, 0x124D, 0x124E, 0x124F
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR18
W
Reset
4
IPR16
W
Reset
3
0
0
0
0
IPR19
0
0
0
0
0
0
0
0
0
Figure 13-20. SDMA Initiator Priority 16, 17, 18, and 19 Registers
Table 13-20. SDMA Initiator Priority 16, 17, 18, and 19 Register Field Descriptions
Bit
Name
Description
0:7
IPR16
Initiator Priority register for initiator 16.
Same bit layout as IPR0
8:15
IPR17
Initiator Priority register for initiator 17.
Same bit layout as IPR0
16:23
IPR18
Initiator Priority register for initiator 18.
Same bit layout as IPR0
24:31
IPR19
Initiator Priority register for initiator 19.
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-21
BestComm
13.15.1.21 SDMA Initiator Priority 20 Register
SDMA Initiator Priority 21 Register
SDMA Initiator Priority 22 Register
SDMA Initiator Priority 23 Register
Address MBAR + 0x1250, 0x1251, 0x1252, 0x1253
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR22
W
Reset
4
IPR20
W
Reset
3
0
0
0
0
IPR23
0
0
0
0
0
0
0
0
0
Figure 13-21. SDMA Initiator Priority 20, 21, 22, and 23 Registers
Table 13-21. SDMA Initiator Priority 20, 21, 22, and 23 Register Field Descriptions
Bit
Name
Description
0:7
IPR20
Initiator Priority register for initiator 20.
Same bit layout as IPR0
8:15
IPR21
Initiator Priority register for initiator 21.
Same bit layout as IPR0
16:23
IPR22
Initiator Priority register for initiator 22.
Same bit layout as IPR0
24:31
IPR23
Initiator Priority register for initiator 23.
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
13-22
Freescale Semiconductor
BestComm
13.15.1.22 SDMA Initiator Priority 24 Register
SDMA Initiator Priority 25 Register
SDMA Initiator Priority 26 Register
SDMA Initiator Priority 27 Register
Address MBAR + 0x1254, 0x1255, 0x1256, 0x1257
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR25
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR26
W
Reset
4
IPR24
W
Reset
3
0
0
0
0
IPR27
0
0
0
0
0
0
0
0
0
Figure 13-22. SDMA Initiator Priority 24, 25, 26, and 27 Registers
Table 13-22. SDMA Initiator Priority 24, 25, 26, and 27 Register Field Descriptions
Bit
Name
Description
0:7
IPR24
Initiator Priority register for initiator 24.
Same bit layout as IPR0
8:15
IPR25
Initiator Priority register for initiator 25.
Same bit layout as IPR0
16:23
IPR26
Initiator Priority register for initiator 26.
Same bit layout as IPR0
24:31
IPR27
Initiator Priority register for initiator 27.
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-23
BestComm
13.15.1.23 SDMA Initiator Priority 28 Register
SDMA Initiator Priority 29 Register
SDMA Initiator Priority 30 Register
SDMA Initiator Priority 31 Register
Address MBAR + 0x1258, 0x1259, 0x125A, 0x125B
0
1
2
R
5
6
7
8
9
10
11
12
13
14
15
IPR29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
IPR30
W
Reset
4
IPR28
W
Reset
3
0
0
0
0
IPR31
0
0
0
0
0
0
0
0
0
Figure 13-23. SDMA Initiator Priority 28, 29, 30, and 31 Registers
Table 13-23. SDMA Initiator Priority 28, 29, 30, and 31 Register Field Descriptions
Bit
Name
Description
0:7
IPR28
Initiator Priority register for initiator 28.
Same bit layout as IPR0
8:15
IPR29
Initiator Priority register for initiator 29.
Same bit layout as IPR0
16:23
IPR30
Initiator Priority register for initiator 30.
Same bit layout as IPR0
24:31
IPR31
Initiator Priority register for initiator 31.
Same bit layout as IPR0
MPC5200B User’s Manual, Rev. 3
13-24
Freescale Semiconductor
BestComm
13.15.1.24 SDMA Requestor MuxControl
Address MBAR + 0x125C
0
R
W
Reset
R
W
Reset
1
Req31
2
3
Req30
4
5
Req29
6
7
8
Req28
9
10
Req27
11
Req26
12
13
14
Req25
15
Req24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Req23
0
Req22
0
0
0
Req21
0
0
Req20
0
0
Req19
0
0
Req18
0
Req17
0
0
0
Req16
0
0
Figure 13-24. SDMA Request MuxControl
Table 13-24. SDMA Request MuxControl Field Descriptions
Bit
Name
Description
0:1
Req31
00
01
10
11
Requestor (RESERVED)
GPIO_PSC2_3
GPIO_IRDA_1
Always Requestor 31
2:3
Req30
00
01
10
11
Requestor (RESERVED)
GPIO_PSC2_2
GPIO_IRDA_0
Always Requestor 30
4:5
Req29
00
01
10
11
Requestor (RESERVED)
GPIO_PSC2_1
GPIO_ETH_3
Always Requestor 29
6:7
Req28
00
01
10
11
Requestor (RESERVED)
GPIO_PSC2_0
GPIO_ETH_2
Always Requestor 28
8:9
Req27
00
01
10
11
Requestor (RESERVED)
GPIO_PSC1_3
GPIO_ETH_1
Always Requestor 27
10:11
Req26
00
01
10
11
Requestor IrDA TX (PSC_6)
GPIO_PSC1_2
GPIO_ETH_0
Always Requestor 26
12:13
Req25
00
01
10
11
Requestor IrDA RX (PSC_6)
GPIO_PSC1_1
GPIO_USB_3
Always Requestor 25
14:15
Req24
00
01
10
11
Requestor I2C1_TX
GPIO_PSC1_0
GPIO_USB_2
Always Requestor 24
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-25
BestComm
Table 13-24. SDMA Request MuxControl Field Descriptions (continued)
Bit
Name
Description
16:17
Req23
00
01
10
11
Requestor I2C1_RX
GPIO_SINT_7
GPIO_USB_1
Always Requestor 23
18:19
Req22
00
01
10
11
Requestor I2C2_TX
GPIO_SINT_6
GPIO_USB_0
Always Requestor 22
20:21
Req21
00
01
10
11
Requestor I2C2_RX
GPIO_SINT_5
GPIO_PSC3_5
Always Requestor 21
22:23
Req20
00
01
10
11
Requestor PSC4_TX
GPIO_SINT_4
GPIO_PSC3_4
Always Requestor 20
24:25
Req19
00
01
10
11
Requestor PSC4_RX
GPIO_SINT_3
GPIO_PSC3_3
Always Requestor 19
26:27
Req18
00
01
10
11
Requestor PSC5_TX
GPIO_SINT_2
GPIO_PSC3_2
Always Requestor 18
28:29
Req17
00
01
10
11
Requestor PSC5_RX
GPIO_SINT_1
GPIO_PSC3_1
Always Requestor 17
30:31
Req16
00
01
10
11
Requestor LP
GPIO_SINT_0
GPIO_PSC3_0
Always Requestor 16
MPC5200B User’s Manual, Rev. 3
13-26
Freescale Semiconductor
BestComm
The remaining 16 requestors are fixed as follows:
Table 13-25. FIxed Requestors Table
Requestor
Peripheral
REQ15
(RESERVED)
REQ14
PSC1_TX
REQ13
PSC1_RX
REQ12
PSC2_TX
REQ11
PSC2_RX
REQ10
PSC3_TX
REQ9
PSC3_RX
REQ8
PCI TX
REQ7
PCI RX
REQ6
ATA TX
REQ5
ATA RX
REQ4
FEC TX
REQ3
FEC RX
REQ2
(RESERVED)
REQ1
(RESERVED)
REQ0
ALWAYS
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-27
BestComm
13.15.1.25 SDMA Task Size0
SDMA Task Size 1
Address MBAR + 0x1260, 0x1264
Bits
R
W
0,4,8,12,
16,20,24,28
1,5,9,13,
17,21,25,29
2,6,10,14,
18,22,26,30
3,7,1115
19,23,27,31
srcSize[1]
srcSize[0]
dstSize[1]
dstSize[0]
Reset
At reset all Bits are set to 0
Figure 13-25. SDMA Task Size 0/1
Table 13-26. SDMA Task Size 0/1 Field Descriptions
Bit
Name
Description
srcSize[1:0]
Each of the 16 tasks can be programmed to use the source and destination sizes contained in one
of the Task Size Registers. The task size information is used by the SDMA module to determine
the source and destination transfer size of the operands. When the size contained the task
descriptor is set to 2’b11 then the size field from the Task Size Control register is selected.
srcSize[1:0]—source size
00 Word (32 bit)
01 Byte
10 Word
11 Word
destSize[1:0]—destination size
00 Word (32 bit)
01 Byte
10 Word
11 Word
13.15.1.25.1 SDMA Task 0 and Task Size 1 Map
Offset
Register Name
Byte 0
Byte 1
Byte 2
Byte 3
Access
0x1260
Task Size 0
TS[0:1]
TS[2:3]
TS[4:5]
TS[5:7]
R/W
0x1264
Task Size 1
TS[8:9]
TS[10:11]
TS[12:13]
TS[14:15]
R/W
Figure 13-26. SDMA Task Size Map
See Figure 13-33 for details. Each task has 4 bits allocated (2 for source and 2 for destination size).
MPC5200B User’s Manual, Rev. 3
13-28
Freescale Semiconductor
BestComm
13.15.1.26 SDMA Reserved Register 1
Address MBAR + 0x1268
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
res1
W
Reset
9
res1
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-27. SDMA Reserved Register 1
Table 13-27. SDMA Reserved Register 1 Field Descriptions
Bit
Name
0:31
res1
Description
Reserved
13.15.1.27 SDMA Reserved Register 2
Address MBAR + 0x126C
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
res2
W
Reset
9
res2
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-28. SDMA Reserved Register 2
Table 13-28. SDMA Reserved Register 2 Field Descriptions
Bit
Name
0:31
res2
Description
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-29
BestComm
13.15.1.28 SDMA Debug Module Comparator 1, Value1 Register
Address MBAR + 0x1270
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Value1
W
Reset
9
Value1
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-29. SDMA Debug Module Comparator 1, Value1 Register
Table 13-29. SDMA Debug Module Comparator 1, Value1 Register Field Descriptions
Bit
Name
0:31
Value1
Description
Debug Module Comparator 1 Value.
13.15.1.29 SDMA Debug Module Comparator 2, Value2 Register
Address MBAR + 0x1274
0
1
2
3
4
5
6
7
R
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Value2
W
Reset
9
Value2
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-30. SDMA Debug Module Comparator 2, Value2 Register
Table 13-30. SDMA Debug Module Comparator 2, Value2 Register Field Descriptions
Bit
Name
0:31
Value2
Description
Debug Module Comparator 2 Value.
MPC5200B User’s Manual, Rev. 3
13-30
Freescale Semiconductor
BestComm
13.15.1.30 SDMA Debug Module Control Register
Address MBAR + 0x1278
0
1
2
3
4
5
6
7
R
R
W
Reset
9
10
11
12
13
14
15
Block Tasks
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AA
B
E
I
B
0
0
0
0
0
Comparator
Type 1
0
0
Comparator
Type 2
0
0
0
and/
or
0
0
EU breakpoints
0
0
0
0
Figure 13-31. SDMA Debug Module Control Register
Table 13-31. SDMA Debug Module Control Register Field Descriptions
Bit
Name
Description
0:15
Block Tasks
Specify for each of tasks 15-0, whether to block that task with detection of a breakpoint (bit 0 halts
TASK 15, bit 1 halts TASK 14, etc)
0 Do not block task
1 Block the task
16
AA
AutoArm—specifies whether or not the triggered bit dbgStatusReg[16] will be automatically reset
to 0 following the saving of context for a breakpoint. This bit is set to 0 at reset.
0 Triggered bit will not be automatically reset
1 Triggered bit will be automatically reset
17
B
18:20
Comparator
Type 1
Comparator 1 type—These bits specify the type of data that has been loaded into comparator 1;
refer to Table 13-32 for the bit encoding.
21:23
Comparator
Type 2
Comparator 2 type—These bits specify the type of data that has been loaded into comparator 2;
refer to Table 13-33 for the bit encoding.
24
and / or
AND/OR—This specifies what type of operation is to be used with the comparators. This bit is set
to 0 at reset.
0 Indicates an OR’ing of the comparators
1 Indicates an AND’ing of the comparators
25:28
EU breakpoints
euBreakpoint: These bits indicate that a breakpoint has occurred in one of the four execution units.
Each execution unit has one bit dedicated to it. A 1 in any of these bits indicates that the
associated execution unit has issued breakpoint. These bits are sticky and must be overwritten to
continue. These bits are cleared to zero at reset. See Table 13-35 for the bit encoding.
MPC5200B has integrated only EU3
29
E
Breakpoint—This bit specifies whether or not to take a breakpoint. This bit is set to 0 at reset.
0 Disable breakpoints
1 Enable breakpoints
Enable External Breakpoint.
0 Do not enable external breakpoint to cause a halt condition
1 Allow external breakpoint to cause a halt condition
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-31
BestComm
Table 13-31. SDMA Debug Module Control Register Field Descriptions (continued)
Bit
Name
30
I
31
EB
Description
Enable Internal Breakpoint
0 Do not enable internal breakpoint to cause a halt condition
1 Allow internal breakpoint to cause a halt condition
Enable Breakpoint (this bit must be always set to allow any kind of breakpoint to halt the task)
0 Disable breakpoint
1 Enable breakpoint
Table 13-32. Comparator 1 Type Bit Encoding
Encoding
Comparator Type 1
000
uninitialized
001
write address
010
read address
011
current pointer
100
task #
101
reserved
110
reserved
111
reserved
Table 13-33. Comparator 2 Type Bit Encoding
Encoding
Comparator Type 2
000
uninitialized
001
write address
010
read address
011
current pointer
100
task #
101
counter value
110
reserved
111
reserved
NOTE
The reserved encodings are set to 0 indicating an uninitialized state.
Table 13-34. EU Breakpoint Encoding
Reset
EU3
EU2
EU1
EU0
0
0
0
0
It must be noted that even if a breakpoint is issued at a specific address the SDMA engine will halt ONLY
at a “data aligned” boundary (for instance, if the task moves 32 bits of data per transaction and a breakpoint
is set at address 0x02 then the task will be halted at offset 0x04).
MPC5200B User’s Manual, Rev. 3
13-32
Freescale Semiconductor
BestComm
13.15.1.31 SDMA Debug Module Status Register
Address MBAR + 0x127C
0
1
2
3
4
5
R
8
9
10
11
12
13
14
15
I
E
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
R
dbgStatusReg[15:0]
W
Reset
7
Reserved
W
Reset
6
0
0
0
0
0
0
0
0
0
0
Figure 13-32. SDMA Debug Module Status Register
Table 13-35. SDMA Debug Module Status Register Field Descriptions
Bit
Name
0:12
Reserved
13
I
Interrupt—This bit indicates whether or not an interrupt has been taken. This bit is set to 0 at
reset. It can be written by the user or the SDMA engine.
0 No Interrupt
1 Interrupt taken
14
E
External Breakpoint—This bit indicates detection of an external breakpoint. Status bit is sticky
and requires a one (1) to be written to it to clear it. The writing of a zero (0) to this bit has no
effect. This bit is set to zero (0) at reset.
0 No external breakpoint detected
1 External breakpoint detected
15
T
Triggered (dbgStatusReg[16])—This bit indicates that a SmartDMA breakpoint has occurred
with the current settings. Status bit is sticky and requires a one (1) to be written to it to clear it.
The writing of a zero (0) to this bit has no effect. This bit is set to zero (0) at reset.
0 Armed or normal operation
1 Triggered or debug mode
16:31
Description
Reserved
dbgStatusReg[15:0] dbgTaskBlock (dbgStatusReg[15:0])—Each bit corresponds to one of the 16 task numbers.
The value of the register bit reflects the debug state of the task number. A bit is cleared by
writing a one to that bit location; writing a zero (0) has no effect. At system reset, all bits are
initialized to logic zeros (0).
0 Unblocked or normal operation
1 Blocked, task has been blocked due to a breakpoint
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-33
BestComm
13.16 On-Chip SRAM
MPC5200B contains 16KBytes of on-chip SRAM. This memory is directly accessible by the BestComm
DMA unit. It is used primarily as storage for task table and buffer descriptors used by BestComm DMA
to move peripheral data to and from SDRAM or other locations. These descriptors must be downloaded to
the SRAM at boot.
This SRAM resides in the MPC5200B internal register space and is also accessible by the processor core.
As such it can be used for other purposes, such as scratch pad storage. The 16kBytes SRAM starts at
location MBAR + 0x8000.
13.17 Programming Model
The SDMA engine expects the programmer to initialize several things in memory including the Task Table
and the Variable Table(s). These are described and illustrated in the following sub-sections. The various
descriptors used in each task are also described below.
13.17.1 Task Table
The programmer must initialize the taskBAR register in the IPB Interface Module (offset 0x1200). The
Task Table (sometime also referred to as Entry Table), whose format is shown in Figure 13-33, should
reside at the address specified by taskBAR.
The Task Table base address must be aligned to a 512-byte boundary. There are sixteen tasks, each of
which has its own unique Task Descriptor Table (TDT) start pointer, TDT end pointer, Variable Table
pointer, control information, and status information. The TDT start pointer is a 32-bit value that points to
the first descriptor, an LCD, of that particular task. The remaining descriptors (LCDs and DRDs) should
consecutively follow the first one in memory, except in special branching cases. The TDT end pointer is a
32-bit value that points to the last descriptor, which must be a DRD, of that particular task.
The 32-bit Variable Table pointer points to the top of the 32-word (128 byte) memory space where this
task’s Variable Table resides. The Variable Table format is explained later in more detail.
The control information is located in the fourth word of each task’s Task Table information as shown in
Figure 13-33. Bits 0 through 23 contain the base address for this task’s function descriptors. Control bits
24 through 31 are for precise increment, not resetting the error code, whether to pack data, integer mode,
complex data mode, to enable speculative reads and whether bursting is allowed on reads and writes.
The fifth and sixth word of the task table are reserved.
The seventh word is a pointer to the Context Save Area where important data is saved and later restored
in case of a task switch.
The last word is used by the SDMA engine in conjunction with Literal Initialization of LCD (to save
variable usage). The user should not modify the values stored there.
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Freescale Semiconductor
BestComm
0
1 1
4 5
4 5
1 2
9 0
3
1
Task Descriptor Start Pointer
Task Descriptor End Pointer
Variable Table Pointer
Function Descriptor Base Address
R P E P I S C R
S I
P W L
V
R
Task 0
Reserved
Reserved
Base Address for Context Save Space
Literal
Base 0
Reserved
Literal
Base 1
Reserved
....................
Task Descriptor Start Pointer
Task Descriptor End Pointer
Variable Table Pointer
Function Descriptor Base Address
R P E P I S C R
S I
P W L
V
R
Task n
Reserved
Reserved
Base Address for Context Save Space
Literal
Base 0
Reserved
Literal
Base 1
Reserved
Note: For each task, the start pointer, end pointer, and variable table pointer are 32-bit values. For the task control
bits, bits 0 through 23 are for the Function Descriptor Base Address, and bits 24 through 31 are:
RSV = Reserved,
PI = Precise Increment,
E = do not reset error code if ‘1’
P = Pack data if ‘1’
I = Integer mode if ‘1’ (else fractional)
SPR = speculative enable
CW = Combined Write Enable if ‘1’
RL = Read Line Buffer Enable if ‘1’ speculative Reads if ‘1’
Figure 13-33. Task Table
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-35
BestComm
Table 13-36. Behavior of Task Table Control Bits
Control Function
Precise Increment
No Error Code Reset
Pack
Integer Mode
Speculative Reads
Combined Write Enable
Read Line Buffer Enable
Value
Meaning
0
Increments are allowed at any time the SDMA can do it
1
Only increment at the end of an iteration
0
Reserved
1
Reserved
0
Do not pack data
1
Pack data
0
Fractional data representation
1
Integer data representation
0
Disabled
1
Enabled
0
Do not enable combined writes
1
Enable combined writes
0
Do not enable line reads
1
Enable line reads
13.17.1.1 Integer Mode
This input signal is only valid if the pack signal is negated (set to ‘0’). This signal indicates if the SDMA
engine should operate in integer mode or fractional mode. During integer mode, the engine sign-extends
read data and the it reads the write size amount of data starting from the MSB position and drives it to the
proper destination byte lanes as indicated by the write address.
During fractional mode, the engine zero-extends read data and the ADS reads the write size amount of data
starting from the LSB position and drives it to the proper write byte lanes as indicated by the write address.
13.17.1.2 Pack
This input signal indicates that packing or unpacking of data should occur if the read size does not equal
the write size. The pack signal has precedence over the integerMode signal.
This signal indicates to the SmartDMA that it should pack data when the source size does not match the
destination size. When this signal is asserted, the SmartDMA should pack data, and the integerMode signal
is ignored. Otherwise, the SmartDMA should not pack data. Packing data refers to the case where the
SmartDMA will wait for a full word of data before passing the data to one of the memory interfaces.
13.17.2 Variable Table
Table 13-37 shows the Variable Table format to which each task must adhere. The Variable Table pointer
that is located in the Task Table in Figure 13-33 points to the first location in this 32-word (128-byte)
memory space.
If restoring, and the Variable Table has been modified, then the new Variable Table pointer is located at the
end of the context save space for the corresponding task. The Variable Table for each task must be aligned
MPC5200B User’s Manual, Rev. 3
13-36
Freescale Semiconductor
BestComm
to a 16-byte boundary (to aid in address calculation). Before executing a particular task, that task’s Variable
Table must be initialized with the appropriate data. Specifically, any constants, initial values, and
increment values must be written to the Variable Table before executing the corresponding task.
Variables may be loaded into words 0 through 23.Increment values 0 through 7 may be loaded into words
24 through 31, respectively.
Any of the eight increment values may be used as normal Loop-Index Variables or Constants if they are
not needed as increment values. All of these variables and increment values may be used to initialize
loop-index registers. However, only variables 0 through 31 may be written by the ADS. At this time, if
variables 24 through 31 are written, it is assumed that these variables should be treated as normal
Loop-Index Variables or Constants and not as increment values. Also, note that Variable Tables may
overlap if sharing the last eight variables with another task’s Variable Table is desired. In addition, if a task
does not use the last 16 variables, another Variable Table could start immediately after that task’s increment
values, so as to not waste memory.
Table 13-37. Variable Table per Task
#
Hex
Offset
0
00
Loop-Index Variable or Constant 0
1
04
Loop-Index Variable or Constant 1
2
08
Loop-Index Variable or Constant 2
3
0c
Loop-Index Variable or Constant 3
4
10
Loop-Index Variable or Constant 4
5
14
Loop-Index Variable or Constant 5
6
18
Loop-Index Variable or Constant 6
7
1c
Loop-Index Variable or Constant 7
8
20
Loop-Index Variable or Constant 8
9
24
Loop-Index Variable or Constant 9
10
28
Loop-Index Variable or Constant 10
11
2c
Loop-Index Variable or Constant 11
12
30
Loop-Index Variable or Constant 12
13
34
Loop-Index Variable or Constant 13
14
38
Loop-Index Variable or Constant 14
15
3c
Loop-Index Variable or Constant 15
16
40
Loop-Index Variable or Constant 16
17
44
Loop-Index Variable or Constant 17
18
48
Loop-Index Variable or Constant 18
19
4c
Loop-Index Variable or Constant 19
20
50
Loop-Index Variable or Constant 20
21
54
Loop-Index Variable or Constant 21
22
58
Loop-Index Variable or Constant 22
23
5c
Loop-Index Variable or Constant 23
Contents
Comments
These twenty-four words (32 bits)
are used for constant operands to
the EUs, for initialization values, or
for a place to write results straight
to a variable in this table. These are
typically preloaded by the CPU
unless you are writing directly to a
variable.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
13-37
BestComm
Table 13-37. Variable Table per Task (continued)
#
Hex
Offset
24
60
Compare Type[31:29], Reserved[28:16], Increment Variable 0[15:0]
25
64
Compare Type[31:29], Reserved[28:16], Increment Variable 1[15:0]
26
68
Compare Type[31:29], Reserved[28:16], Increment Variable 2[15:0]
27
6c
Compare Type[31:29], Reserved[28:16], Increment Variable 3[15:0]
28
70
Compare Type[31:29], Reserved[28:16], Increment Variable 4[15:0]
29
74
Compare Type[31:29], Reserved[28:16], Increment Variable 5[15:0]
30
78
Compare Type[31:29], Reserved[28:16], Increment Variable 6[15:0]
31
7c
Compare Type[31:29], Reserved[28:16], Increment Variable 7[15:0]
Contents
Comments
Variables 24–31 may be increment
variables of the format shown to
the left. Any of these variables may
be used as normal Loop-Index
Variables or Constants (like
variables 0–23) instead.
When the user writes a program, or when the assembler converts the user’s programs, the SDMA engine
will use the initialization variables and constants that the user or processor should have loaded into the
Variable Table. The initial index variables in the LCD tells the engine to allocate space for the resulting
variables in the loop registers. The space will be allocated consecutively, so the user knows with which
register each variable will be associated. This is important when the user’s program tries to reference one
of these previously allocated variables. Also, the eight increment variables in positions 24 through 31 of
Table 13-37 are preloaded by the processor, as programmed by the user.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Chapter 14
Fast Ethernet Controller (FEC)
14.1
Overview
The fast Ethernet controller (FEC) is an Ethernet MAC plus two 1 Kbyte FIFOs that work under the control
of the processor and BestComm DMA engine to support 10/100 Mbps Ethernet/802.3 networks.
Figure 14-1 shows a block diagram.
A brief introduction and overview of the major functional blocks aid in understanding and programming
the FEC.
The FEC is controlled by writing through the system interface (SIF) module into control registers located
in each block. The control/status register (CSR) block provides global control and interrupt handling
registers. User programming of the CSR is the primary focus of this chapter.
The RISC based Ethernet controller provides the following functions:
• Initialization
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
The FIFO controller is the focal point of all data flow in the FEC. The FIFO is divided into a transmit and
receive FIFO of 1Kbyte each. Transmit data flows from the CommBus into the transmit FIFO and through
the transmit block to the physical layer device (PHY). Receive data flows from the PHY to the receive
block and is pulled out of the FIFO by BestComm. BestComm data transfers are interrupt driven. Interrupt
driven data movement from the processor is not supported.
The bus controller decides which block is to be the T-bus master for each cycle. All the blocks receive their
control information over the T-bus and provide status information over this same internal bus.
The media independent interface (MII) block provides a serial channel for control/status communication
with the external physical layer device (transceiver or PHY). The serial channel consists of the MDC
(clock) and MDIO (bidirectional data I/O) lines of the MII interface.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assistance from the
BestComm unit). Internal to these blocks are clock domain boundaries between the system clock and the
network clocks supplied by the PHY.
The management information base (MIB) block maintains the counters for a variety of network events and
statistics. The counters support the RMON (RFC 1757) Ethernet statistics group and some of the IEEE
802.3 counters.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-1
Fast Ethernet Controller (FEC)
The FEC supports several standard MAC-PHY interfaces to connect to an external Ethernet transceiver.
One is the 10/100 Mbps MII (18-wire) interface. Another is the 10-Mbps only 7-Wire interface, which uses
a subset of the MII pins.
CLK/CNTL
CommBus
IP Bus
Interrupt
FEC
SIF
tbus_addr
tbus
Requests
Bus
Controller
tbus_addr
CSR
tbusd_addr
FIFO Controller
Tx FIFO (1KByte)
Rx FIFO (1KByte)
RISC
Controller
(RISC +
Microcode)
T-bus
MIB
Counters
MII
MDO
MDEN
Transmit
Receive
MDI
I/O
Pad
MDIO
TX_EN
TXD[3:0]
TX_ER
MDC
TX_CLK
CRS,COL
RX_CLK
RX_DV
RXD[3:0]
RX_ER
MII/7-Wire Data
Option
Figure 14-1. Block Diagram—FEC
MPC5200B User’s Manual, Rev. 3
14-2
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.1.1
Features
The FEC incorporates several features/design goals that are key to its use:
• Support for different Ethernet physical interfaces:
— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface (industry standard)
• IEEE 802.3 full-duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200 Mbps throughput) with a minimum system clock rate of
50 MHz.
• Support for half-duplex operation (100 Mbps throughput) with a minimum system clock rate of
25 MHz.
• Large (1 Kbyte) on-chip transmit and receive FIFOs to support a variety of bus latencies.
• Retransmission from transmit FIFO following a collision (no processor bus utilization).
• Automatic internal flushing of the Rx FIFO for runts (collision fragments) and address recognition
rejects (no processor bus utilization).
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
14.2
Modes of Operation
The primary operational modes are described in this section.
14.2.1
Full- and Half-Duplex Operation
This is determined by the X_CNTRL register FDEN bit. Full-duplex mode is intended for use on point to
point links between switches or end node to switch. Half-duplex mode is used in connections between an
end node and a repeater or between repeaters.
Full-duplex flow control is an option that may be enabled in full-duplex mode.
14.2.2
10Mbps and 100Mbps MII Interface Operation
The MAC-PHY interface operates in MII mode by asserting the R_CNTRL register MII_MODE bit. MII
is the media independent interface defined by the 802.3 standard for 10/100 Mbps operation.
Speed of operation is determined by the TX_CLK and RX_CLK pins, which are driven by the transceiver.
The transceiver either auto-negotiates the speed or it may be controlled by software using the serial
management interface (MDC/MDIO pins) to the transceiver.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-3
Fast Ethernet Controller (FEC)
14.2.3
10Mbps 7-Wire Interface Operation
If the external transceiver supports 10 Mbps only and uses a 7-wire style interface then deassert the
R_CNTRL register MII_MODE bit in the R_CNTRL register. This style of interface is not defined by the
802.3 standard, but instead is an industry standard.
14.2.4
Address Recognition Options
The options supported are promiscuous, broadcast reject, individual address hash or exact match and
multicast hash match. Refer to the R_CNTRL register for address recognition programming.
14.2.5
Internal Loopback
Internal loopback mode is selected using the R_CNTRL register LOOP bit.
14.3
I/O Signal Overview
This section defines the FEC-to-chip pin I/O. The FEC network interface supports multiple options. One
is the MII option that requires 18 I/O pins and supports both data and an out-of-band serial management
interface to the PHY (transceiver) device. The MII option supports both 10 and 100 Mbps Ethernet rates.
The second is referred to as the 7-wire interface and supports only 10 Mbps Ethernet data. The 7-wire
interface uses a subset of the MII signals.
Table 14-1 shows the network interface signals and lists 18 signals, all of which are used for the 10/100
MII interface.
NOTE
The MDIO pin is bidirectional and corresponds to the FEC block MDI,
MDO and MDIO pins. The 7-wire interface option uses a subset of these
signals.
Table 14-1. Signal Properties
Signal Name
Chip Pin
Function
Reset State
tx_en
ETH0
MII—transmit data valid output
7-wire—transmit data valid output
0
tdata[0]
ETH1
MII—transmit data bit 0 output
7-wire—transmit data output
—
tdata[1]
ETH2
MII—transmit data bit 1 output
—
tdata[2]
ETH3
MII—transmit data bit 2 output
—
tdata[3]
ETH4
MII—transmit data bit 3 output
—
tx_er
ETH5
MII—transmit error output
0
mdc
ETH6
MII—management clock output
0
mdi
mdo
md_en
ETH7
MII—management data bidirect
Hi-Z (input)
MPC5200B User’s Manual, Rev. 3
14-4
Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-1. Signal Properties (continued)
14.3.1
14.3.1.1
Signal Name
Chip Pin
Function
Reset State
rx_dv
ETH8
MII—Rx data valid input
7-wire—rena input
—
rx_clk
ETH9
MII—Rx clock input
7-wire—Rx clock input
—
col
ETH10
MII—collision input
10 Mbps 7-wire—collision input
—
tx_clk
ETH11
MII—transmit clock input
7-wire—transmit clock input
—
rdata[0]
ETH12
MII—Rx data bit 0 input
7-wire—Rx data input
—
rdata[1]
ETH13
MII—Rx data bit 1 input
—
rdata[2]
ETH14
MII—Rx data bit 2 input
—
rdata[3 ]
ETH15
MII—Rx data bit 3 input
—
rx_er
ETH16
MII—Rx error input
—
crs
ETH17
MII—carrier sense input
—
Detailed Signal Descriptions
MII Ethernet MAC-PHY Interface
This section gives a detailed description of the Media-Independent Interface (MII). An overview of the
MII is presented followed by a description of the MII signals. Two different types of MII frames are
described. A brief MII management function overview is given.
The MII interface has 18 signals. Tx and Rx functions require 7 signals each:
• 4 data signals
• 1 delimiter
• 1 error
• 1 clock
Media status is indicated by 2 signals:
• 1 signal indicates a carrier is present.
• 1 signal indicates a collision occurred.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-5
Fast Ethernet Controller (FEC)
Management interface is provided by 2 signals.
MII signals are described below.
Tx_CLK
A continuous clock that provides a timing reference for Tx_EN, TxD, and Tx_ER. The
frequency of Tx_CLK is 25% of the transmit data rate, ± 100 ppm. Duty cycle shall be
35%-65% inclusive.
Rx_CLK
A continuous clock that provides a timing reference for Rx_DV, RxD, and Rx_ER. The
frequency of Rx_CLK is 25% of the receive data rate, with a duty cycle between 35% and
65%.
Tx_EN
Assertion of this signal indicates valid nibbles are being presented on the MII. This signal
is asserted with the first nibble of preamble and is negated prior to the first Tx_CLK
following the final nibble of the frame.
TxD
TxD[0:3] represent a nibble of data when Tx_EN is asserted and have no meaning when
Tx_EN is de-asserted. Table 14-2 summarizes the permissible encoding of TxD.
Tx_ER
Rx_DV
RxD
Rx_ER
CRS
COL
MDC
MDIO
Assertion of this signal for one or more clock cycles while Tx_EN is asserted causes PHY
to transmit one or more illegal symbols. Asserting Tx_ER has no affect when operating at
10 Mbps or when Tx_EN is de-asserted This signal transitions synchronously with respect
to Tx_CLK.
When this signal is asserted, PHY is indicating a valid nibble is present on the MII. This
signal remains asserted from the first recovered nibble of the frame through the last nibble.
Assertion of Rx_DV must start no later than the SFD, and exclude any EOF.
RxD[0:3] represents a nibble of data to be transferred from the PHY to the MAC when
Rx_DV is asserted. A completely formed SFD must be passed across the MII. When
Rx_DV is not asserted, RxD has no meaning. There is an exception to this which is
explained later. Table 14-3 summarizes the permissible encoding of RxD.
When Rx_ER and Rx_DV are asserted, the PHY has detected an error in the current frame.
When Rx_DV is not asserted, Rx_ER shall have no affect. This signal transitions
synchronously with Rx_CLK.
Signal is asserted when Tx or Rx medium is not idle. If a collision occurs, CRS remains
asserted through the duration of the collision. This signal is not required to transition
synchronously with Tx_CLK or Rx_CLK.
Signal is asserted on a collision detection and remains asserted while the collision persists.
The signal behavior is not specified when in full-duplex mode. This signal is not required
to transition synchronously with Tx_CLK or Rx_CLK.
Signal provides a timing reference to the PHY for data transfers on the MDIO signal. MDC
is aperiodic and has no maximum high or low times. The minimum high and low times is
160 ns with the minimum period being 400 ns.
Signal transfers control/status information between the PHY and MAC. It transitions
synchronously to MDC. The MDIO pin is a bidirectional pin. The internal FEC signals that
connect to this pad are: MDI (data in), MDO (data out), and MD_EN (direction control,
high for output).
MPC5200B User’s Manual, Rev. 3
14-6
Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-2 lists the interpretation of possible encodings for Tx_EN and Tx_ER.
Table 14-2. MII: Valid Encoding of TxD, Tx_EN and Tx_ER
TX_EN
TX_ER
TXD
Indication
0
0
0000 through 1111
Normal inter-frame
0
1
0000 through 1111
Reserved
1
0
0000 through 1111
Normal data transmission
1
1
0000 through 1111
Transmit error propagation
A false carrier condition occurs if the PHY detects a bad start-of-stream delimiter. This condition signals
the MII by asserting Rx_ER and placing 1110 on RxD. Rx_DV must also be de-asserted. Valid Rx_DV,
Rx_ER and RxD[3:0] encodings are shown in Table 14-3.
Table 14-3. MII: Valid Encoding of RxD, Rx_ER and Rx_DV
14.3.1.2
RX_DV
RX_ER
RXD
Indication
0
0
0000 through 1111
Normal inter-frame
0
1
0000
Normal inter-frame
0
1
0001 through 1101
Reserved
0
1
1110
False Carrier
0
1
1111
Reserved
1
0
0000 through 1111
Normal data reception
1
1
0000 through 1111
Data reception with errors
MII Management Frame Structure
A transceiver management frame transmitted on the MII management interface uses the MDIO and MDC
pins. A transaction or frame on this serial interface has the following format:
<preamble><st><op><phyad><regad><ta><data><idle>
Table 14-4. MMI Format Definitions
Name
<preamble>
Description
Optional—consists of a sequence of 32 continuous logic 1s.
<st>
Start of frame—indicated by a <01> pattern.
<op>
Operation code:
Read instruction is <10>
Write instruction is <01>
<phyad>
A 5-bit field that lists up to 32 PHYs be addressed. The first address bit transmitted is the msb of the
address.
<regad>
A 5-bit field that lets 32 registers be addressed within each PHY. The first register bit transmitted is
the msb of the address.
<ta>
A 2-bit field that provides spacing between the register address field and the data field to avoid
contention on the MDIO signal during a read operation.
<data>
Data field is 16 bits wide. Data bit 15 is first bit transmitted and received.
<idle>
During idle condition, MDIO is in the high impedance state.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-7
Fast Ethernet Controller (FEC)
14.3.1.2.1
MII Management Register Set
The MII management register set located in the PHY may consist of a basic register set and an extended
register set as defined in Table 14-5.
Table 14-5. MII Management Register Set
14.4
Register Address
Register Name
Basic/Extended
0
Control
B
1
Status
B
2:3
PHY Identifier
E
4
Auto-Negotiation Advertisement
E
5
AN Link Partner Ability
E
6
AN Expansion
E
7
AN Next Page Transmit
E
8:15
Reserved
E
16:31
Vendor Specific
E
FEC Memory Map and Registers
The FEC device is programmed by a combination of control/status registers (CSRs) and BestComm task
loops. Since the FEC software model is BestComm-based, there is no similarity with existing CPM-based
products’ coding.
The CSRs are used for mode control, interrupts and extraction of status information. BestComm tasks are
used to pass data buffers and related buffer or frame information between the hardware and software.
All access via microprocessor to and from the registers must be 32-bit accesses. There is no support for
accesses other than 32-bit. All access via BestComm to and from the registers may be byte, word or
longword (32-bit) accesses. Top Level Module Memory Map
The FEC implementation requires a 2KByte memory map space. This is divided into two sections of 512
Bytes and an additional 1KBytes of reserved space. The first 512 Bytes is used for Control and Status
Registers. The second contains event/statistic counters held in the MIB block. Table 14-6 defines the top
level memory map.
Table 14-6. Module Memory Map
Address
Function
000–1FF
Control/Status Registers
200–3FF
MIB Block Counters, see Table 14-8
400–7FF
Reserved
MPC5200B User’s Manual, Rev. 3
14-8
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.1
Control and Status (CSR) Memory Map
Table 14-7. CSR Counters
Address
Mnemonic
000
FEC_ID
FEC_ID Register
004
IEVENT
Interrupt Event Register
008
IMASK
Interrupt Enable Register
00C
Name
Reserved
010
R_DES_ACTIVE
Receive Ring Updated Flag
014
X_DES_ACTIVE
Transmit Ring Updated Flag
018-020
024
Reserved
ECNTRL
028-03C
Reserved
040
MII_DATA
044
MII_SPEED
04C-060
064
Ethernet Control Register
MII Data Register
MII Speed Register
Reserved
MIB_CONTROL
068-080
MIB Control/Status Register
Reserved
084
R_CNTRL
Receive Control Register
088
R_HASH
Receive Hash
08C-0C0
0C4
Reserved
X_CNTRL
0C8-0E0
Transmit Control Register
Reserved
0E4
PADDR1
Physical Address Low
0E8
PADDR2
Physical Address High+ Type Field
0EC
OP_PAUSE
0F0-114
Opcode + Pause Duration
Reserved
118
IADDR1
Upper 32 bits of individual Hash Table
11C
IADDR2
Lower 32 bits of individual Hash Table
120
GADDR1
Upper 32 bits of Group Hash Table
124
GADDR2
Lower 32 bits of Group Hash Table
128-140
144
Reserved
X_WMRK
148-180
Transmit FIFO Watermark
Reserved
184
RFIFO_DATA
Receive FIFO Data
188
RFIFO_STATUS
Receive FIFO Status
18C
RFIFO_CONTROL
Receive FIFO Control
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-9
Fast Ethernet Controller (FEC)
Table 14-7. CSR Counters (continued)
Address
Mnemonic
Name
190
RFIFO_LRF_PTR
Receive FIFO Last Read Frame Pointer
194
RFIFO_LWF_PTR
Receive FIFO Last Write Frame Pointer
198
RFIFO_ALARM
Receive FIFO Alarm Pointer
19C
RFIFO_RDPTR
Receive FIFO Read Pointer
1A0
RFIFO_WRPTR
Receive FIFO Write Pointer
1A4
TFIFO_DATA
1A8
TFIFO_STATUS
Transmit FIFO Status
1AC
TFIFO_CONTROL
Transmit FIFO Control
1B0
TFIFO_LRF_PTR
Transmit FIFO Last Read Frame Pointer
1B4
TFIFO_LWF_PTR
Transmit FIFO Last Write Frame Pointer
1B8
TFIFO_ALARM
Transmit FIFO Alarm Pointer
1BC
TFIFO_RDPTR
Transmit FIFO Read Pointer
1C0
TFIFO_WRPTR
Transmit FIFO Write Pointer
1C4
RESET_CNTRL
Reset Control
1C8
XMIT_FSM
Transmit FSM
Transmit FIFO Data
1CC-1FF
14.4.2
MIB Block Counters Memory Map
Table 14-8 defines the MIB Counters memory map which defines the MIB RAM space locations where
hardware-maintained counters reside. These fall in the 3200-33FF address range. Counters are divided into
two groups.
1. RMON counters—are included which cover Ethernet statistics counters defined in RFC 1757. In
addition to Ethernet statistics group counters, a counter is included to count truncated frames as
FEC only supports frame lengths up to 2047bytes. RMON counters are implemented
independently for Tx and Rx, to ensure accurate network statistics when operating in full-duplex
mode.
2. IEEE counters—are included which support the mandatory and recommended counter packages
defined in Section 5 of ANSI/IEEE Standard 802.3 (1998 edition). FEC supports IEEE Basic
Package objects, but does not require MIB block counters. In addition, some recommended
package objects supported do not require MIB counters. Counters for Tx and Rx full-duplex flow
control frames are included.
MPC5200B User’s Manual, Rev. 3
14-10
Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-8. MIB Counters
Address
Mnemonic
Description
200
RMON_T_DROP
204
RMON_T_PACKETS
208
RMON_T_BC_PKT
RMON Tx Broadcast Packets
20C
RMON_T_MC_PKT
RMON Tx Multicast Packets
210
RMON_T_CRC_ALIGN
RMON Tx Packets with CRC/Align error
214
RMON_T_UNDERSIZE
RMON Tx Packets less than 64bytes, good CRC
218
RMON_T_OVERSIZE
21C
RMON_T_FRAG
220
RMON_T_JAB
RMONTxPackets greater than MAX_FL bytes, bad CRC
224
RMON_T_COL
RMON Tx collision count
228
RMON_T_P64
RMON Tx 64Byte packets
22C
RMON_T_P65TO127
RMON Tx 65 to 127Byte packets
230
RMON_T_P128TO255
RMON Tx 128 to 255Byte packets
234
RMON_T_P256TO511
RMON Tx 256 to 511Byte packets
238
RMON_T_P512TO1023
RMON Tx 512 to 1023Byte packets
23C
RMON_T_P1024TO2047
RMON Tx 1024 to 2047Byte packets
240
RMON_T_P_GTE2048
244
RMON_T_OCTETS
248
IEEE_T_DROP
24C
IEEE_T_FRAME_OK
250
IEEE_T_1COL
Frames Transmitted with Single Collision
254
IEEE_T_MCOL
Frames Transmitted with Multiple Collisions
258
IEEE_T_DEF
Frames Transmitted after Deferral Delay
25c
IEEE_T_LCOL
Frames Transmitted with Late Collision
260
IEEE_T_EXCOL
264
IEEE_T_MACERR
Frames Transmitted with Tx FIFO Underrun
268
IEEE_T_CSERR
Frames Transmitted with Carrier Sense Error
26C
IEEE_T_SQE
270
T_FDXFC
274
IEEE_T_OCTETS_OK
278–27C
rsvd
280
RMON_R_DROP
284
RMON_R_PACKETS
288
RMON_R_BC_PKT
RMON Rx Broadcast Packets
28C
RMON_R_MC_PKT
RMON Rx Multicast Packets
Count of Frames Not Correctly Counted
RMON Tx Packet Count
RMON Tx Packets greater than MAX_FL bytes, good CRC
RMON Tx Packets less than 64bytes, bad CRC
RMON Tx packets with greater than 2048Bytes
RMON Tx Octets
Count of Frames Not Counted Correctly
Frames Transmitted OK
Frames Transmitted with Excessive Collisions
Frames Transmitted with SQE Error
Flow Control Pause Frames Transmitted
Octet Count for Frames Transmitted w/o Error
Reserved
Count of frames Not Counted Correctly
RMON Rx Packet Count
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-11
Fast Ethernet Controller (FEC)
Table 14-8. MIB Counters (continued)
Address
Mnemonic
Description
290
RMON_R_CRC_ALIGN
RMON Rx Packets with CRC/Align error
294
RMON_R_UNDERSIZE
RMON Rx Packets less than 64Bytes, good CRC
298
RMON_R_OVERSIZE
29C
RMON_R_FRAG
2A0
RMON_R_JAB
2A4
RMON_R_RESVD_0
2A8
RMON_R_P64
2AC
RMON_R_P65TO127
RMON Rx 65 to 127Byte packets
2B0
RMON_R_P128TO255
RMON Rx 128 to 255Byte packets
2B4
RMON_R_P256TO511
RMON Rx 256 to 511Byte packets
2B8
RMON_R_P512TO1023
RMON Rx 512 to 1023Byte packets
2BC
RMON_R_P1024TO2047
RMON Rx 1024 to 2047Byte packets
2C0
RMON_R_P_GTE2048
2C4
RMON_R_OCTETS
2C8
IEEE_R_DROP
2CC
IEEE_R_FRAME_OK
2D0
IEEE_R_CRC
2D4
IEEE_R_ALIGN
2D8
IEEE_R_MACERR
2DC
R_FDXFC
2E0
IEEE_R_OCTETS_OK
2E4–2FC
rsvd
Reserved
300–3FF
rsvd
Reserved
RMON Rx Packets greater than MAX_FL bytes, good CRC
RMON Rx Packets less than 64Bytes, bad CRC
RMONRxPackets greater than MAX_FL bytes, bad CRC
Reserved
RMON Rx 64Byte packets
RMON Rx packets with greater than 2048Bytes
RMON Rx Octets
Count of frames not counted correctly
Frames received OK
Frames received with CRC error
Frames received with alignment error
Rx FIFO overflow count
Flow Control Pause frames received
Octet count for frames received without error
MPC5200B User’s Manual, Rev. 3
14-12
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3
FEC Registers
The FEC uses 37 32-bit registers. These registers are located at an offset from MBAR of 0x3000. Register
addresses are relative to this offset. Therefore, the actual register address is MBAR + 0x3000 + register
address.
Hyperlinks to the FEC registers are provided below:
• FEC ID Register (0x3000)
• FEC Interrupt Event Register (0x3004)
• FEC Interrupt Enable Register (0x3008)
• FEC Rx Descriptor Active Register (0x3010)
• FEC Tx Descriptor Active Register (0x3014)
• FEC Ethernet Control Register (0x3024)
• FEC MII Management Frame Register (0x3040)
• FEC MII Speed Control Register (0x3044)
• FEC MIB Control Register (0x3064)
• FEC Receive Control Register (0x3084)
• FEC Hash Register (0x3088)
• FEC Tx Control Register (0x30C4)
• FEC Physical Address Low Register (0x30E4)
• FEC Physical Address High Register (0x30E8)
• FEC Opcode/Pause Duration Register (0x30EC)
• FEC Descriptor Individual Address 1 Register (0x3118)
• FEC Descriptor Individual Address 2 Register (0x311C)
• FEC Descriptor Group Address 1 Register (0x3120)
• FEC Descriptor Group Address 2 Register (0x3124)
• FEC Tx FIFO Watermark Register (0x3144)
• FEC Rx FIFO Data Register FEC Tx FIFO Data Register (0x3184)
• FEC Rx FIFO Status Register FEC Tx FIFO Status Register (0x31A4)
• FEC Rx FIFO Control Register FEC Tx FIFO Control Register (0x3188)
• FEC Rx/Tx FIFO Status Register (0x31A8)
• FEC Rx/Tx FIFO Control Register (0x318C)
• FEC Rx/Tx FIFO Last Read Frame Pointer Register (0x3190)
• FEC Rx/Tx FIFO Last Write Frame Pointer Register (0x3194)
• FEC Rx/Tx FIFO Alarm Pointer Register (0x3198)
• FEC Rx/Tx FIFO Alarm Pointer Register (0x31B8)
• FEC Rx/Tx FIFO Read Pointer Register (0x319C)
• FEC Rx/Tx FIFO Write Pointer Register (0x31A0)
• FEC Reset Control Register (0x31C4)
• FEC Transmit FSM Register (0x31C8)
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-13
Fast Ethernet Controller (FEC)
14.4.3.1
FEC ID Register
The read-only FEC ID Register (FEC_ID) identifies the FEC block and revision.
Address MBAR + 0x3000
0
1
2
3
4
5
6
7
R
8
9
10
11
12
13
14
15
FEC_ID
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
Reset
DMA FIFO
Reserved
W
0
0
0
0
0
0
FEC_REV
Rsvd
0
0
0
0
0
0
0
Figure 14-2. FEC ID Register
Table 14-9. FEC ID Register Field Descriptions
Bits
Name
0:15
FEC_ID
16:20
—
21
DMA
DMA function is included in the FEC
0 FEC does not include DMA (BestComm is the DMA engine)
22
FIFO
FIFO function included in the FEC
1 FEC does include a FIFO
24:31
FEC_REV
14.4.3.2
Description
Value identifying the FEC
Reserved
Value identifies the FEC revision
FEC Interrupt Event Register
When an event occurs that sets a bit in the IEVENT register, an interrupt is generated if the corresponding
bit in the interrupt enable register (IMASK) is also set. The IEVENT register bit is cleared if 1 is written
to that bit position. A 0 write has no effect. A hardware reset clears this register.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts and
internal error interrupts. Interrupts that may occur in normal operation are:
• GRA
• TFINT
• MII
Interrupts resulting from errors/problems detected in the network or transceiver are:
• HBERR
• BABR
• BABT
• LATE_COL
• COL_RETRY_LIM
MPC5200B User’s Manual, Rev. 3
14-14
Freescale Semiconductor
Fast Ethernet Controller (FEC)
Interrupts resulting from FIFO errors are:
• XFIFO_UN
• XFIFO_ERROR
• RFIFO_ERROR
Some error interrupts are independently counted in the MIB block counters. Software may choose to mask
these interrupts, since the errors are visible to network management via the MIB counters.
• HBERR – IEEE_T_SQE
• BABR – RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
• BABT – RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
• LATE_COL – IEEE_T_LCOL
• COL_RETRY_LIM – IEEE_T_EXCOL
• XFIFO_UN – IEEE_T_MACERR
Address MBAR + 0x3004
10
11
12
13
14
15
MII
Rsvd
RFIFO_
ERROR
9
XFIFO_
ERROR
8
XFIFO_UN
7
COL_
RETRY_LIM
6
LATE_COL
5
TFINT
4
GRA
3
BABT
2
BABR
1
HBERR
0
Rsvd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
W
Reset
Reserved
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 14-3. FEC Interrupt Event Register
Table 14-10. FEC Interrupt Event Register Field Descriptions
Bits
Name
Description
0
HBERR
Heartbeat Error— interrupt bit indicates HBC is set in the X_CNTRL register and COL input
was not asserted within the heartbeat window following a transmission.
1
BABR
Babbling Receive Error—bit indicates frame was received with a length in excess of
R_CNTRL.MAX_FL bytes.
2
BABT
Babbling Transmit Error—bit indicates transmitted frame length exceeded
R_CNTRL.MAX_FL bytes. This condition is usually caused by a frame that is too long being
placed into the transmit data buffer(s).
Truncation does not occur.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-15
Fast Ethernet Controller (FEC)
Table 14-10. FEC Interrupt Event Register Field Descriptions (continued)
Bits
Name
Description
3
GRA
Graceful Stop Complete—interrupt bit is asserted for one of three reasons.
1 A graceful stop initiated by setting X_CNTRL.GTS bit is complete.
2 A graceful stop initiated by setting X_CNTRL.FC_PAUSE bit is complete.
3 A graceful stop initiated by reception of a valid full duplex flow control “pause” frame is
complete. Refer to “Full-Duplex Flow Control” section of the Ethernet Operation chapter.
A graceful stop means the transmitter is put into a pause state after completion of the frame
currently being transmitted.
4
TFINT
5
—
Reserved
6
—
Reserved
7
—
Reserved
8
MII
MII Interrupt—bit indicates MII completed the data transfer requested.
9
—
Reserved
10
LATE_COL
11
COL_RETRY_LIM
Collision Retry Limit—bit indicates a collision occurred on each of 16 successive attempts to
transmit the frame. The frame is discarded without being transmitted and transmission of the
next frame begins.
Only occurs in half-duplex mode.
12
XFIFO_UN
Transmit FIFO Underrun—bit indicates the transmit FIFO became empty before the complete
frame was transmitted. A bad CRC is appended to the frame fragment and remainder of
frame is discarded.
13
XFIFO_ERROR
Transmit FIFO Error—indicates an error occurred within the transmit FIFO. When
XFIFO_ERROR bit is set, ECNTRL.ETHER_EN is cleared, halting FEC frame processing.
When this occurs, software must ensure both the FIFO Controller and BestComm are
soft-reset.
14
RFIFO_ERROR
Receive FIFO Error—indicates error occurred within the RX FIFO. When RFIFO_ERROR bit
is set, ECNTRL.ETHER_EN is cleared, halting FEC frame processing. When this occurs,
software must ensure both the FIFO Controller and BestComm are soft-reset.
15:31
—
Transmit frame interrupt. This bit indicates that a frame has been transmitted.
Late Collision bit indicates a collision occurred beyond the collision window (slot time) in
half-duplex mode. The frame is truncated with a bad CRC. Remainder of the frame is
discarded.
Reserved.
MPC5200B User’s Manual, Rev. 3
14-16
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.3
FEC Interrupt Enable Register
The IMASK register provides control over the interrupt events allowed to generate an interrupt. All
implemented bits in this CSR are R/W. This register is cleared by a hardware reset. If corresponding bits
in both the IEVENT and IMASK registers are set, the interrupt is signalled to the CPU. The interrupt signal
remains asserted until 1 is written to the IEVENT bit (write 1 to clear) or a 0 is written to the IMASK bit.
Address MBAR + 0x3008
11
12
13
14
15
Rsvd
RFERREN
10
XFERREN
9
XFUNEN
8
CRLEN
7
LCEN
6
MIIEN
5
TFIEN
4
GRAEN
3
BTEN
2
BREN
1
HBEEN
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Reserved
Rsvd
W
Reset
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 14-4. FEC Interrupt Enable Register
Table 14-11. FEC Interrupt Enable Register Field Descriptions
Bits
Name
Description
0
HBEEN
1
BREN
Babbling Receiver Interrupt Enable
2
BTEN
Babbling Transmitter Interrupt Enable
3
GRAEN
4
TFIEN
5
—
Reserved
6
—
Reserved
7
—
Reserved
8
MIIEN
9
—
10
LCEN
Late Collision Enable
11
CRLEN
Late Collision Enable
12
XFUNEN
13
XFERREN
Transmit FIFO Error Enable
14
RFERREN
Receive FIFO Error Enable
15:31
—
Heartbeat Error Interrupt Enable
Graceful Stop Interrupt Enable
Transmit Frame Interrupt Enable
MII Interrupt Enable
Reserved
Transmit FIFO Underrun Enable
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-17
Fast Ethernet Controller (FEC)
14.4.3.4
FEC Rx Descriptor Active Register
The FEC descriptor active register is a command register which should be written by the user to indicate
that the receive descriptor ring has been updated (empty receive buffers have been produced by the driver
with the E bit set).
Whenever the register is written the R_DES_ACTIVE bit is set. This is independent of the data actually
written by the user. When set, the FEC will poll the receive descriptor ring and process receive frames
(provided ETHER_EN is also set). Once the FEC polls a receive descriptor whose ownership bit is not set,
then the FEC will clear the R_DES_ACTIVE bit and cease receive descriptor ring polling until the user
sets the bit again, signifying additional descriptors have been placed into the receive descriptor ring.
The R_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN.
Address MBAR + 0x3010
1
2
3
4
5
6
R
W
Reserved
Reset
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
R_DES_ACTIVE
0
0
0
0
0
0
0
0
0
0
Figure 14-5. FEC Rx Descriptor Active Register
Table 14-12. FEC Rx Descriptor Active Register Field Descriptions
Bits
Name
0:6
—
7
R_DES_ACTIVE
8:31
—
Description
Reserved
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “ready” descriptors remain in the receive ring.
Reserved
MPC5200B User’s Manual, Rev. 3
14-18
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.5
FEC Tx Descriptor Active Register
The FEC descriptor active register is a command register which should be written by the user to indicate
that the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with
the R bit set in the buffer descriptor).
Whenever the register is written the X_DES_ACTIVE bit is set. This is independent of the data actually
written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit frames
(provided ETHER_EN is also set). Once the FEC polls a transmit descriptor whose ownership bit is not
set, then the FEC will clear the X_DES_ACTIVE bit and cease transmit descriptor ring polling until the
sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring.
The X_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN.
Address MBAR + 0x3014
1
2
3
4
5
6
R
W
Reserved
Reset
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
X_DES_ACTIVE
0
0
0
0
0
0
0
0
0
0
Figure 14-6. FEC Tx Descriptor Active Register
Table 14-13. FEC Tx Descriptor Active Register Field Descriptions
Bits
Name
0:6
—
7
X_DES_ACTIVE
8:31
—
Description
Reserved
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “ready” descriptors remain in the transmit ring.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-19
Fast Ethernet Controller (FEC)
14.4.3.6
FEC Ethernet Control Register
The ECNTRL register is a read/write user register that can enable/disable the FEC. Some fields may be
altered by hardware.
Address MBAR + 0x3024
1
2
3
4
R
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESET
Reserved
ETHER_EN
Reset
6
FEC_OE
W TAG0 TAG1 TAG2 TAG3 Rsvd
5
TESTMD
0
0
0
0
0
0
0
0
0
0
R
W
Reset
Reserved
0
0
0
0
0
0
0
Figure 14-7. FEC Ethernet Control Register
Table 14-14. FEC Ethernet Control Register Field Descriptions
Bits
Name
Description
0:3
TAG[0:3]
This field allows programming and reading the TBUS tag bits. This field is used for debug/test
only, and is implemented in two separate 4-bit registers. The tags_in register is written to when
a write to this register takes place. This field (tags_in) resets to 1111. During a write cycle to any
FEC register other than ECNTRL the tags_in value is driven onto the tbus data bus tag field.
During a read cycle the tbus tag field bits is latched and saved in the tags_out register. When
the ECNTRL register is read the value from tags_out shows in the TAG field.
4
—
5
TESTMD
6:28
—
29
FEC_OE
30
ETHER_EN
Ethernet Enable—When this bit is set, FEC is enabled and Rx/Tx can occur. When bit is
cleared, Rx stops immediately; Tx stops after a bad CRC is appended to any frame currently
being transmitted. The ETHER_EN bit is altered by hardware under the following conditions:
• If ECNTRL.RESET is written to 1 by software, ETHER_EN is cleared.
• If error conditions causing the IEVENT.EBERR, XFIFO_ERROR or RFIFO_ERROR bits to
set occur ETHER_EN is cleared.
31
RESET
Ethernet Controller Reset—When this bit is set, the equivalent of a hardware reset is done, but
it is local to the FEC. ETHER_EN is cleared and all other FEC registers take their reset values.
Also, any Tx/Rx currently in progress is abruptly aborted. This bit is automatically cleared by
hardware during the reset sequence. The reset sequence takes approximately 8 clock cycles
after RESET is written with 1.
Reserved
Test Mode—used for manufacturing test only. TESTMD resets to 0. This bit forces the bus
controller to ignore all bus requests except the one from the SIF.
Reserved
FEC Output Enable—It is a spare bit and has no affect on internal operation.
MPC5200B User’s Manual, Rev. 3
14-20
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.7
FEC MII Management Frame Register
This MII_DATA register does not reset to a defined value. The MII_DATA register is used to communicate
with the attached MII compatible PHY device(s), providing read/write access to the MII registers.
Writing to the MII_DATA register causes a management frame to be sourced unless the MII_SPEED
register has been programmed to 0. When writing to MII_DATA when MII_SPEED = 0, if the
MII_SPEED register is then written to a non-zero value, an MII frame is generated with the data previously
written to the MII_DATA register. This let MII_DATA and MII_SPEED be programmed in either order if
MII_SPEED is currently 0.
Address MBAR + 0x3040
0
R
2
ST
W
Reset
1
3
4
5
OP
6
7
9
10
PA
11
12
13
14
RA
15
TA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
DATA
W
Reset
8
X
X
X
X
X
X
X
X
X
Note: X: Bit does not reset to a defined value.
Figure 14-8. FEC MII Management Frame Register
Table 14-15. FEC MII Management Frame Register Field Descriptions
Bits
Name
Description
0:1
ST
Start of Frame Delimiter—bits must be programmed to 01 for a valid MII management frame.
2:3
OP
Operation Code—field must be programmed to 10 (read) or 01 (write) to generate a valid MII
management frame.
• A value of 11 causes a “read” frame operation.
• A value of 00 causes a “write” frame operation. However, these frames are not MII compliant.
4:8
PA
PHY Address—specifies 1 of up to 32 attached PHY devices.
9:13
RA
Register Address—specifies 1 of up to 32 registers within the specified PHY device.
14:15
TA
TurnAround—must be programmed to 10 to generate a valid MII management frame.
16:31
DATA
Management Frame Data—used for data written to or read from PHY register.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-21
Fast Ethernet Controller (FEC)
To do a read or write operation the MII management interface writes to the MII_DATA register. To
generate a valid read or write management frame:
• the ST field must be written with a 01
• the OP field must be written with either:
— 01 (management register write frame), or
— 10 (management register read frame), and
• the TA field must be written with a 10
If other patterns are written to these fields, a frame is generated, but it does not comply to the IEEE 802.3
MII definition:
• OP field = 1x produces a “read” frame operation, while
• OP field = 0x produces a “write” frame operation.
To generate an IEEE 802.3 compliant MII management interface write frame (write to a PHY register), the
user must write the following to the MII_DATA register:
{01 01 PHYAD REGAD 10 DATA}
Writing this pattern causes control logic to shift out the data in the MII_DATA register following a
preamble generated by the control state machine. During this time, the MII_DATA register contents are
altered as the contents are serially shifted, and is unpredictable if read by the user. When the write
management frame operation is complete, the MII_DATAIO_COMPL interrupt is generated. At this time
the MII_DATA register contents match the original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write the
following to the MII_DATA register (DATA field content is don’t care):
{01 10 PHYAD REGAD 10 XXXX}
Writing this pattern causes control logic to shift out data in the MII_DATA register following a preamble
generated by the control state machine. During this time, the MII_DATA register contents are altered as
the contents are serially shifted, and is unpredictable if read by the user. When the read management frame
operation is complete, the MII_DATAIO_COMPL interrupt is generated. At this time the MII_DATA
register contents matches the original value written, except for the DATA field whose contents have been
replaced by the value read from the PHY register.
If the MII_DATA register is written while frame generation is in progress, frame contents are altered.
Software should use the MII_STATUS register and/or the MII_DATAIO_COMPL interrupt to avoid
writing to the MII_DATA register while frame generation is in process.
MPC5200B User’s Manual, Rev. 3
14-22
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.8
FEC MII Speed Control Register
The MII_SPEED register provides MII clock (MDC pin) frequency control. This allows dropping the MII
management frame preamble and provides observability (intended for manufacturing test) of an internal
counter used in generating an MDC clock signal.
Address MBAR + 0x3044
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DIS_
PREAMBLE
0
R
W
Reset
8
Reserved
W
Reset
7
Reserved
0
0
0
0
0
0
0
0
0
MII_SPEED
0
0
0
0
Rsvd
0
0
0
Figure 14-9. FEC MII Speed Control Register
Table 14-16. FEC MII Speed Control Register Field Descriptions
Bits
Name
Description
0:23
—
24
DIS_PREAMBLE
Asserting this bit causes preamble (32 1s) to not be prepended to the MII management
frame. The MII standard allows the preamble to be dropped, if not required by the attached
PHY device(s).
Reserved
25:30
MII_SPEED
Controls the frequency of the MII management interface clock (MDC) relative to ipb_clk. A 0
value in this field “turns off” the MDC and leaves it in low voltage state. Any non-zero value
results in the MDC frequency of
1/(MII_SPEED*2) of the ipb_clk frequency.
The MII_SPEED field must be programmed with a value to provide an MDC frequency of less
than or equal to 2.5 MHz to be compliant with the IEEE MII characteristic. The MII_SPEED
must be set to a non-zero value in order to source a read or write management frame. After
the management frame is complete, the MII_SPEED register may optionally be set to 0 to
turn off the MDC. The MDC generated has a 50% duty cycle except when MII_SPEED is
changed during operation (change takes affect following either a rising or falling edge of
MDC).
If the ipb_clk is 25MHz, programming MII_SPEED field to 0x5 results in a MDC frequency of
25MHz * 1/(5*2) = 2.5 MHz. Table 14-17 shows MII_SPEED optimum values as a function of
the ipb_clk frequency.
31
—
Reserved
Table 14-17. Programming Examples for MII_SPEED Register
ipb_clk Frequency
MII_SPEED (Field in Register)
MDC Frequency
25MHz
$5
2.5MHz
33MHz
$7
2.36MHz
40MHz
$8
2.5MHz
50MHz
$A
2.5MHz
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-23
Fast Ethernet Controller (FEC)
14.4.3.9
FEC MIB Control Register
The MIB_CONTROL register is a read/write register used to provide control of and to observe the state
of the MIB block. This register is accessed by user software if there is a need to disable the MIB block
operation. For example, to clear all MIB counters in RAM the user should disable the MIB block, clear all
MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1.
Address MBAR + 0x3064
Reset
2
3
4
5
6
8
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
Reserved
R
Reserved
W
Reset
7
MIB_IDLE
W
1
MIB_DISABLE
R
0
0
0
0
0
0
0
0
0
0
Figure 14-10. FEC MIB Control Register
Table 14-18. FEC MIB Control Register Field Descriptions
Bits
Name
Description
0
MIB_DISABLE
A read/write control bit. If set, MIB logic halts and MIB counters do not update.
1
MIB_IDLE
A read-only status bit. If set, MIB block is not currently updating MIB counters.
2:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
14-24
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.10 FEC Receive Control Register
The R_CNTRL register is user programmable. It controls the operational mode of the receive block and
should be written only when ETHER_EN = 0 (initialization time).
Address MBAR + 0x3084
0
1
R
3
4
5
6
7
8
9
Reserved
10
12
13
14
15
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FCE
PROM
MII_MODE
MAX_FL
DRT
LOOP
0
0
0
0
0
1
R
W
Reset
11
BC_REJ
W
Reset
2
Reserved
0
0
0
0
0
0
0
0
0
0
Figure 14-11. FEC Receive Control Register
Table 14-19. FEC Receive Control Register Field Descriptions
Bits
Name
Description
0:4
—
5:15
MAX_FL
16:25
—
26
FCE
Flow Control Enable—If asserted, the receiver detects PAUSE frames. On PAUSE frame detection,
transmitter stops transmitting data frames for a given duration.
27
BC_REJ
Broadcast Frame Reject—If asserted, frames with DA (destination address) = FFFF_FFFF_FFFF
are rejected, unless PROM bit is set. If both BC_REJ and PROM = 1, frames with broadcast DA are
accepted and M (MISS) bit is set in the Rx buffer descriptor.
28
PROM
Promiscuous mode—All frames are accepted regardless of address matching.
29
MII_MODE
Selects External Interface Mode—controls the interface mode for Tx/Rx blocks.
• Setting bit to 1 selects MII mode.
• Setting bit to 0 selects 7wire mode (used only for serial 10Mbps).
30
DRT
Reserved
Maximum Frame Length—User R/W field. Resets to decimal 1518. The length is measured starting
at DA and includes CRC at End Of Frame (EOF). Tx frames longer than MAX_FL causes the BABT
interrupt to occur. Rx Frames longer than MAX_FL causes BABR interrupt to occur and sets the
EOF Receive Frame Status Word LG bit. The recommended user programmed default value is
1518, or if VLAN Tags are supported, 1522.
Reserved
Disable Receive on Transmit
0 = Rx path operates independently of Tx
(use for full-duplex or to monitor Tx activity in half-duplex mode).
1 = Disable frames reception while transmitting
(normally used for half-duplex mode).
31
LOOP
Internal Loopback—If set, transmitted frames are looped back internal to the device and transmit
output signals are not asserted. The system clock is substituted for TX_CLK when LOOP is
asserted. DRT must be set to 0 when asserting LOOP.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-25
Fast Ethernet Controller (FEC)
14.4.3.11 FEC Hash Register
The read-only R_HASH register provides address recognition information from the Rx block about the
frame currently being received. These bits provide information used in the address recognition subroutine.
Address MBAR + 0x3088
R
0
1
2
3
4
5
6
7
8
9
10
FCE_DC
MULTI
CAST
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
HASH
11
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
Reserved
W
Reset
R
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
Figure 14-12. FEC Hash Register
Table 14-20. FEC Hash Register Field Descriptions
Bits
Name
0
FCE_DC
1
MULTICAST
2:7
HASH
8:31
—
Description
This is a read-only view of the R_CNTRL register FCE bit.
Set if current Rx frame contained a multi-cast destination address, indicating DA LSB was set.
Cleared if current Rx frame does not correspond to a multi-cast address.
Corresponds to “hash” value of current Rx frame’s destination address. Hash value is a 6-bit field
extracted from least significant portion of CRC register.
Reserved
MPC5200B User’s Manual, Rev. 3
14-26
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.12 FEC Tx Control Register
This X_CNTRL register is read/write and is written to configure the transmit block. This register is cleared
at system reset. Bits 29:30 should be modified only when ETHER_EN = 0.
Address MBAR + 0x30C4
0
1
2
3
4
5
6
R
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RFC_PAUSE
TFC_PAUSE
W
Reset
7
0
0
R
W
Reset
Reserved
0
0
0
0
0
0
0
0
0
0
0
FDEN HBC
0
0
GTS
0
Figure 14-13. FEC Tx Control Register
Table 14-21. FEC Tx Control Register Field Descriptions
Bits
Name
Description
0:26
—
27
RFC_PAUSE
This read-only status bit is asserted when a full-duplex flow control pause frame is received. The
transmitter is paused for the duration defined in this pause frame. Bit automatically clears when
the pause duration is complete.
28
TFC_PAUSE
Assert to transmit a PAUSE frame. When this bit is set, the MAC stops transmission of data
frames after the current transmission is complete. At this time, the INTR_EVENT register GRA
interrupt is asserted. With transmission of data frames stopped, the MAC transmits a MAC
Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data
frames.
Note: If the transmitter is paused due to user assertion of GTS or reception of a PAUSE frame,
MAC may still transmit a MAC Control PAUSE frame.
29
FDEN
Full Duplex Enable—If set, frames are transmitted independent of Carrier Sense and Collision
inputs.
This bit should only be modified when ETHER_EN is deasserted.
30
HBC
Heartbeat Control—If set, the heartbeat check is done following End Of Transmission (EOT)
and the Event Status Register HB bit is set if the collision input does not assert within the
heartbeat window.
This bit should only be modified when ETHER_EN is deasserted.
31
GTS
Graceful Transmit Stop—When this bit is set, the MAC stops transmission after any frame that
is currently being transmitted is complete and the INTR_EVENT register GRA interrupt is
asserted.
If frame transmission is not currently underway, the GRA interrupt is immediately asserted.
Once transmission completes, a “restart” can be done by clearing the GTS bit. The next frame
in the transmit FIFO is then transmitted.
If an early collision occurs during transmission when GTS = 1, transmission stops after the
collision. The frame is transmitted again once GTS is cleared.
Note: Old frames may exist in the transmit FIFO and be transmitted when GTS is reasserted.
To avoid this, deassert ETHER_EN after the GRA interrupt.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-27
Fast Ethernet Controller (FEC)
14.4.3.13 FEC Physical Address Low Register
The PADDR1 register is written by the user. This register contains the lower 32bits (Bytes 0,1,2,3) of the
48-bit address used in the address recognition process to compare with the destination address (DA) field
of receive frames with an individual DA. In addition, this register is used in Bytes0:3 of the 6-Byte source
address field when transmitting PAUSE frames. This register is not reset and must be initialized.
Address MBAR + 0x30E4
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
PADDR1
W
Reset
8
PADDR1
W
Reset
7
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-14. FEC Physical Address Low Register
Table 14-22. FEC Physical Address Low Register Field Descriptions
Bits
Name
0:31
PADDR1
Description
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address
used for an exact match, and the Source Address field in PAUSE frames.
MPC5200B User’s Manual, Rev. 3
14-28
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.14 FEC Physical Address High Register
The PADDR2 register is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the
48-bit address used in the address recognition process to compare with the destination address (DA) field
of receive frames with an individual DA. In addition, this register is used in Bytes 4 and 5 of the 6-Byte
source address field when transmitting PAUSE frames. Bits 16:31 of XMIT.PADDR2 contain a constant
type field (hex 8808) used for transmission of PAUSE frames. This register is not reset and bits 0:15 must
be initialized.
Address MBAR + 0x30E8
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
PADDR2
W
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
1
0
0
0
R
TYPE
W
Reset
1
0
0
0
1
0
0
0
0
Note: X: Bit is not reset and must be initialized.
Figure 14-15. FEC Physical Address High Register
Table 14-23. FEC Physical Address High Register Field Descriptions
Bits
Name
Description
0:15
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for an exact match,
and the Source Address field in PAUSE frames.
16:31
TYPE
These 16 bits are a constant value, hex 8808.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-29
Fast Ethernet Controller (FEC)
14.4.3.15 FEC Opcode/Pause Duration Register
The OP_PAUSE register is read/write accessible. This register contains the 16-bit opcode, and 16-bit
pause duration fields used in transmission of a PAUSE frame. The opcode field is a constant value, hex
0001. When another node detects a PAUSE frame, that node pauses transmission for the duration specified
in the pause duration field. This register is not reset and bits 16:31 must be initialized.
Address MBAR + 0x30EC
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
OPCODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
PAUSE_DUR
W
Reset
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-16. FEC Opcode/Pause Duration Register
Table 14-24. FEC Opcode/Pause Duration Register Field Descriptions
Bits
Name
0:15
OPCODE
16:31
PAUSE_DUR
Description
Opcode field used in PAUSE frames. Bits are a constant value, hex 0001.
Pause Duration field used in PAUSE frames.
MPC5200B User’s Manual, Rev. 3
14-30
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.16 FEC Descriptor Individual Address 1 Register
The IADDR1 register is written by the user. This register contains the upper 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA field
of receive frames with an individual DA. This register is not reset and must be initialized.
Address MBAR + 0x3118
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
IADDR1
W
Reset
8
IADDR1
W
Reset
7
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-17. FEC Descriptor Individual Address 1 Register
Table 14-25. FEC Descriptor Individual Address 1 Register Field Descriptions
Bits
Name
Description
0:31
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames
with a unicast address.
• Bit 31 contains hash index bit 63.
• Bit 0 contains hash index bit 32.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-31
Fast Ethernet Controller (FEC)
14.4.3.17 FEC Descriptor Individual Address 2 Register
The IADDR2 register is written by the user. This register contains the lower 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA field
of receive frames with an individual DA. This register is not reset and must be initialized.
Address MBAR + 0x311C
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
IADDR2
W
Reset
8
IADDR2
W
Reset
7
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-18. FEC Descriptor Individual Address 2 Register
Table 14-26. FEC Descriptor Individual Address 2 Register Field Descriptions
Bits
Name
Description
0:31
IADDR2
The lower 32bits of the 64-bit hash table used in the address recognition process for receive frames
with a unicast address.
• Bit 31 contains hash index bit 31.
• Bit 0 contains hash index bit 0.
MPC5200B User’s Manual, Rev. 3
14-32
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.18 FEC Descriptor Group Address 1 Register
The GADDR1 register is written by the user. This register contains the upper 32bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register must be
initialized.
Address MBAR + 0x3120
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
GADDR1
W
Reset
8
GADDR1
W
Reset
7
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-19. FEC Descriptor Group Address 1 Register
Table 14-27. FEC Descriptor Group Address 1 Register Field Descriptions
Bits
Name
0:31
GADDR1
Description
The GADDR1 register contains the upper 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address.
• Bit 31 contains hash index bit 63.
• Bit 0 contains hash index bit 32.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-33
Fast Ethernet Controller (FEC)
14.4.3.19 FEC Descriptor Group Address 2 Register
The GADDR2 register is written by the user. The GADDR2 register contains the lower 32bits of the 64-bit
hash table used in the address recognition process for receive frames with a multicast address. This register
must be initialized.
Address MBAR + 0x3124
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
X
X
X
X
X
X
R
GADDR2
W
Reset
8
GADDR2
W
Reset
7
X
X
X
X
X
X
X
X
X
Note: X: Bit is not reset and must be initialized.
Figure 14-20. FEC Descriptor Group Address 2 Register
Table 14-28. FEC Descriptor Group Address 2 Register Field Descriptions
Bits
Name
0:31
GADDR2
Description
The GADDR2 register contains the lower 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address.
• Bit 31 contains hash index bit 31.
• Bit 0 contains hash index bit 0.
MPC5200B User’s Manual, Rev. 3
14-34
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.3.20 FEC Tx FIFO Watermark Register
The X_WMRK register is a user programmable 4-bit read/write register that controls the amount of data
required in the transmit FIFO before transmission of a frame can begin. This lets the user minimize
transmit latency (X_WMRK = 0000) or allows for larger bus access latency (X_WMRK = 1111) due to
contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO
underrun due to contention for the system bus. The X_WMRK register resets to 0.
NOTE
This register value may need to be customized by software for specific FEC
applications to be compatible with specific FIFO/system bus access latency
requirements.
Address MBAR + 0x3144
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Reserved
W
Reset
0
0
0
0
0
0
0
X_WMRK
0
0
0
0
0
0
0
0
0
Figure 14-21. FEC Tx FIFO Watermark Register
Table 14-29. FEC Tx FIFO Watermark Register Field Descriptions
Bits
Name
0:28
—
28:31
X_WMRK
Description
Reserved
Transmit FIFO Watermark—Frame transmission begins:
• If the number of bytes selected by this field are written into the transmit FIFO, or
• if an EOF is written to the FIFO, or
• if the FIFO is full before the selected number of bytes are written.
Options are:
0000 64Bytes written to FIFO
0001 128Bytes written to FIFO
0010 192Bytes written to FIFO
0011 256Bytes written to FIFO
0100 320Bytes written to FIFO
0101 384Bytes written to FIFO
0110 448Bytes written to FIFO
0111 512Bytes written to FIFO
1000 576Bytes written to FIFO
1001 640Bytes written to FIFO
1010 704Bytes written to FIFO
1011 768Bytes written to FIFO
1100 832Bytes written to FIFO
1101 896Bytes written to FIFO
1110 960Bytes written to FIFO
1111 1024Bytes written to FIFO
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-35
Fast Ethernet Controller (FEC)
14.4.4
FIFO Interface
The programming interface to the FIFO allows access to Data, Status, Control, Last Write Pointer, Last
Read Pointer, Alarm, Read and Write Pointers for Transmit and Receive configurations. The FIFO can be
accessed by byte, word, or longword, but all accesses must be aligned with the most significant byte (big
endian) of the data port. BestComm supports byte, word or longword accesses. The processor supports
longword access only. All register name access is longword aligned
.
Table 14-30. FIFO Interface Register Map
Address
byte0
byte1
byte2
byte3
0x184
Data
Data
Data
Data
0x188
Stat
Stat
0x18C
Ctl
Description
Receive FIFO Data
Receive FIFO Status
Receive FIFO Control
0x190
LRF
LRF
Receive Last Read Frame Pointer
0x194
LWF
LWF
Receive Last Write Frame Pointer
0x198
Alarm
Alarm
Receive (High/Low) Alarm Pointer
0x19C
Read
Read
Receive FIFO Read Pointer
0x1A0
Write
Write
Receive FIFO Write Pointer
Data
Data
Transmit FIFO Data
0x1A4
Data
Data
0x1A8
Stat
Stat
0x1AC
Ctl
Transmit FIFO Status
Transmit FIFO Control
0x1B0
LRF
LRF
Transmit Last Read Frame Pointer
0x1B4
LWF
LWF
Transmit Last Write Frame Pointer
0x1B8
Alarm
Alarm
Transmit (High/Low) Alarm Pointer
0x1BC
Read
Read
Transmit FIFO Read Pointer
0x1C0
Write
Write
Transmit FIFO Write Pointer
MPC5200B User’s Manual, Rev. 3
14-36
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.4.1
FEC Rx FIFO Data Register
FEC Tx FIFO Data Register
The RFIFO_DATA (MBAR + 0x3184) and TFIFO_DATA (MBAR + 0x31A4) registers are the main
interface port for the transmit and receive FIFO. Data which is to be buffered in the FIFO, or has been
buffered in the FIFO, is accessed through this register.
14.4.4.2
FEC Rx FIFO Status Register
FEC Tx FIFO Status Register
The RFIFO_STATUS and TFIFO_STATUS registers contain bits which provide information about the
status of the FIFO controller. The bits marked sticky are cleared by writing a “1” to their positions.
Address MBAR + 0x3188, 0x31A8
R
W
Reset
0
1
2
3
4
5
6
IP
TXW
0
0
0
0
0
0
0
16
17
18
19
20
21
22
8
9
10
11
FAE
RXW
UF
OF
0
0
0
0
23
24
25
0
Frame[0:3]
TYPE TYPE
[1]
[0[
R
12
13
14
15
FR
Full
0
0
0
1
1
26
27
28
29
30
31
0
0
0
0
1
1
Alarm Empty
Reserved
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 14-22. FEC Rx/Tx FIFO Status Register
Table 14-31. FEC Rx/Tx FIFO Status Register Field Descriptions
Bits
Name
Description
0:3
—
4:7
Frame[0:3]
8
—
9
Error
FIFO Error – Sticky, Write To Clear.
This bit signifies that an error has occurred in the FIFO controller. Errors can be caused by
underflow, overflow, or pointers being out of bounds. This bit will remain set until this bit of the FIFO
status register has been written with a 1.
10
UF
UF FIFO Underflow – Sticky, Write To Clear
This bit signifies the read pointer has surpassed the write pointer. This bit will remain set until this
bit of the FIFO status register has been written with a 1.
11
OF
OF FIFO Overflow – Sticky, Write To Clear
This bit signifies the write pointer has surpassed the read pointer. This bit will remain set until this
bit of the FIFO status register has been written with a 1.
Reserved
Frame Indicator – READ ONLY
This bus provides a frame status indicator for non-DMA applications.
Frame[0] = A frame boundary has occurred on the [31:24] byte of the data bus.
Frame[1] = A frame boundary has occurred on the [23:16] byte of the data bus.
Frame[2] = A frame boundary has occurred on the [15:8] byte of the data bus.
Frame[3] = A frame boundary has occurred on the [7:0] byte of the data bus.
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-37
Fast Ethernet Controller (FEC)
Table 14-31. FEC Rx/Tx FIFO Status Register Field Descriptions (continued)
Bits
Name
Description
12
FR
FR Frame Ready – Read Only
The FIFO has requested attention because there is framed data ready. All complete frames must
be read from the FIFO to clear this alarm. This alarm will only be asserted while in frame mode.
13
Full
Full Alarm – Read Only
The FIFO has requested attention because it is full. The FIFO must be read to clear this alarm.
14
Alarm
FIFO Alarm – Read Only
The FIFO has requested attention because it has determined an alarm condition. The specific alarm
condition detected is dependent upon the FIFO direction (Transmit or Receive); if it is a Transmit
FIFO, then the FIFO alarm output pin provides indication of a low level, asserting when there is less
than alarm bytes of data remaining in the FIFO, and deasserting when there are less than 4*
granularity free bytes remaining. When the FIFO is configured to Receive, the FIFO alarm provides
high level indication, asserting when there are less than alarm bytes free in the FIFO, and
deasserting when there are less than granularity bytes of data remaining. This signal can be cleared
by reading or writing (as appropriate) the FIFO, or manipulating the FIFO pointers.
15
Empty
Empty – Read Only
The FIFO has requested attention because it is empty. The FIFO must be written to clear this alarm.
16:31
—
Reserved
MPC5200B User’s Manual, Rev. 3
14-38
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.4.3
FEC Rx FIFO Control Register
FEC Tx FIFO Control Register
The RFIFO_CONTROL and TFIFO_CONTROL registers provide programmability of many FIFO
behaviors, from last transfer granularity to frame operation. Last transfer granularity allows the user to
control when the FIFO controller stops requesting data transfers through the FIFO alarm. When the alarm
is configured as a Receive FIFO, the granularity value is the GR[2:0] value. When the alarm is configured
as a Transmit FIFO, the granularity value is four times the GR[2:0] value, or the pipeline depth. The frame
bit of the control register provides a capability to enable and control the FIFO controller’s ability to view
data on a packetized basis. The FIFO controller also has the programmable capability to not request
attention after it has received a complete frame until Ethernet has reported completion of transmission.
Frame mode supersedes the FIFO granularity bits, through the assertion of a hardware signal to
BestComm.
Address MBAR + 0x318C, 0x31AC
2
4
5
6
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
IP
FAE RXW UF
OF
TXW
MASK MASK MASK MASK MASK MASK
GR[2:0]
R
Reserved
Reserved
W
Reset
7
0
W Shadow WFR[1:0]
Reset
3
FRAME
1
COMP
0
R
0
0
0
0
0
0
0
0
0
Figure 14-23. FEC Rx/Tx FIFO Control Register
Table 14-32. FEC Rx/Tx FIFO Control Register Field Descriptions
Bits
Name
Description
0
—
1:2
WFR[1:0]
3
COMP
COMP Re-enable Requests on Frame Transmission Completion.
When this bit is set, the FIFO controller will not request attention between receiving the last data
of the frame from the BestComm until the peripheral acknowledges transmission of the frame.
4
FRAME
Frame Mode Enable.
When this bit is set, the FIFO controller monitors frame done information from the peripheral or
BestComm. Setting this bit also enables the other frame control bits in this register, as well as
other frame functions. This bit must be set to use frame functions.
5:7
GR[2:0]
Last Transfer Granularity.
These bits define the deassertion point for the “high” service request and also define the
deassertion point for the “low” service request. A “high” service request is deasserted when there
are less than GR[2:0] data bytes remaining in the FIFO. A “low” service request is deasserted
when there are less than (4 * GR[2:0]) free bytes remaining in the FIFO.
Reserved
Write Frame
01 The FIFO controller assumes the next write to its data port is the next to last write.
10 The FIFO controller assumes the next write to its data port is status / control information.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-39
Fast Ethernet Controller (FEC)
14.4.4.4
FEC Rx FIFO Last Read Frame Pointer Register
FEC Tx FIFO Last Read Frame Pointer Register
The RFIFO_LRF_PTR and TFIFO_LRF_PTR are a FIFO-maintained pointer which indicates the location
of the start of the most recently read frame, or the start of the frame currently in transmission. The LRFP
updates on FIFO read data accesses to a frame boundary. The LRFP can be read and written for debug
purposes. For the frame retransmit function, the LRFP indicates which point to begin retransmission of the
data frame. The LRFP carries validity information, however, there are no safeguards to prevent
retransmitting data which has been overwritten. When FRAME is not set, then this pointer has no meaning.
Address MBAR + 0x3190, 0x31B0
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
LRFP[9:0]
0
0
0
0
0
0
0
0
Figure 14-24. FEC Rx/Tx FIFO Last Read Frame Pointer Register
Table 14-33. FEC Rx/Tx FIFO Last Read Frame Pointer Register Field Descriptions
Bits
Name
0:21
—
22:31
LRFP[9:0]
Description
Reserved
LRFP Last Read Frame Pointer.
This pointer indicates the start of the last data frame read from the FIFO by the peripheral.
MPC5200B User’s Manual, Rev. 3
14-40
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.4.5
FEC Rx FIFO Last Write Frame Pointer Register
FEC Tx FIFO Last Write Frame Pointer Register
The RFIFO_LWF_PTR and TFIFO_LWF_PTR are a FIFO maintained pointer which indicates the
location of the start of the last frame written into the FIFO. The LWFP updates on FIFO write data accesses
which create a frame boundary, whether that be by setting the WFC control bit or by feeding a frame bit
in on the appropriate bus. The LWFP can be read and written for debug purposes. For the frame discard
function, the LWFP divides the valid data region of the FIFO (the area in-between the read and write
pointers) into framed and unframed data. Data between the LWFP and write pointer constitutes an
incomplete frame, while data between the read pointer and the LWFP has been received as whole frames.
When FRAME is not set, then this pointer has no meaning.
Address MBAR + 0x3194, 0x31B4
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
LRFP[9:0]
0
0
0
0
0
0
0
0
Figure 14-25. FEC Rx/Tx FIFO Last Write Frame Pointer Register
Table 14-34. FEC Rx/Tx FIFO Last Write Frame Pointer Register Field Descriptions
Bits
Name
0:21
—
22:31
LWFP[9:0]
Description
Reserved
LRFP Last WriteFrame Pointer.
This pointer indicates the start of the last data frame written into the FIFO by the peripheral.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-41
Fast Ethernet Controller (FEC)
14.4.4.6
FEC Rx FIFO Alarm Pointer Register
FEC Tx FIFO Alarm Pointer Register
RFIFO_ALARM and TFIFO_ALARM include pointer which provide high/low level alarm information
to the user integration logic and the BestComm interface. A low level alarm reports lack of data; a high
level alarm reports lack of space. The alarm pointer is interpreted depending on the state of the FIFO
transmit input pin: if FIFO transmit = “1”, then the alarm is represented in terms of data bytes, if FIFO
Transmit = “0”, the alarm is represented in terms of free bytes. This programmable alarm can warn the
system when the FIFO is almost full of data (FIFO Transmit = “0”), or when the FIFO is almost out of data
(FIFO Transmit = “1”). This register is programmed to the upper limit for the number of bytes in the FIFO
of data, when FIFO transmit is negated, or space, when FIFO transmit is asserted, before an internal alarm
is set. Any time the amount of data or space in the FIFO is above the indicated amount, the alarm will be
set. The alarm is cleared when there is less data or space than is defined as the FIFO granularity or pipeline
depth. The number of bits in the alarm pointer register will vary with the address space of the FIFO
memory, and the alarm pointer is initialized to zero.
Address MBAR + 0x3198, 0x31B8
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
Alarm[9:0]
0
0
0
0
0
0
0
0
Figure 14-26. FEC Rx/Tx FIFO Alarm Pointer Register
Table 14-35. FEC Rx/Tx FIFO Alarm Pointer Register Field Descriptions
Bits
Name
0:21
—
22:31
Alarm[9:0]
Description
Reserved
Alarm Pointer.
This pointer indicates the point at (or below) which to assert the FIFO alarm signal. This value is
compared with data or free bytes, depending upon the state of FIFO Transmit (FIFO Transmit = “1”,
alarm measures data bytes).
MPC5200B User’s Manual, Rev. 3
14-42
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.4.7
FEC Rx FIFO Read Pointer Register
FEC Tx FIFO Read Pointer Register
The RFIFO_RDPTR and TFIFO_RDPTR are a FIFO-maintained pointer which point to the next FIFO
location to be read. The read pointer can be both read and written.
Address MBAR + 0x319C, 0x31BC
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
READ[9:0]
0
0
0
0
0
0
0
0
Figure 14-27. FEC Rx/Tx FIFO Read Pointer Register
Table 14-36. FEC Rx/Tx FIFO Read Pointer Register Field Descriptions
Bits
Name
0:21
—
22:31
READ[9:0]
Description
Reserved
Read Pointer.
This pointer indicates the next location to be read by the FIFO controller.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-43
Fast Ethernet Controller (FEC)
14.4.4.8
FEC Rx FIFO Write Pointer Register
FEC Tx FIFO Writer Pointer Register
The RFIFO_WRPTR and TFIFO_WRPTR are a FIFO-maintained pointer which point to the next FIFO
location to be written. The write pointer can be both read and written.
Address MBAR + 0x31A0, 0x31C0
0
1
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
Reserved
W
Reset
8
Reserved
W
Reset
7
0
0
0
0
WRITE[9:0]
0
0
0
0
0
0
0
0
Figure 14-28. FEC Rx/Tx FIFO Write Pointer Register
Table 14-37. FEC Rx/Tx FIFO Write Pointer Register Field Descriptions
Bits
Name
0:21
—
22:31
WRITE[9:0]
Description
Reserved
WRITE Pointer.
This pointer indicates the next location to be written by the FIFO controller.
MPC5200B User’s Manual, Rev. 3
14-44
Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.4.4.9
FEC Reset Control Register
The RESET_CNTRL register allows reset of the FIFO controllers.
Address MBAR + 0x31C4
0
1
R
3
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
RCTL RCTL
[1]
[0]
Reserved
W
Reset
2
0
0
0
0
0
0
0
0
0
Figure 14-29. FEC Reset Control Register
Table 14-38. FEC Reset Control Register Field Descriptions
Bits
Name
Description
0:5
—
6
RCTL[1]
0 Do not Reset FIFO controllers.
1 Reset FIFO controllers.
7
RCTL[0]
0 Disable fec_enable as a reset to FIFO controllers.
1 Enable fec_enable as a reset to FIFO controllers.
8:31
—
Reserved
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-45
Fast Ethernet Controller (FEC)
14.4.4.10 FEC Transmit FSM Register
The transmit finite state machine register (XMIT_FSM) controls operation of appending CRC. Typical use
is enabled and CRC is appended.
Address MBAR + 0x31C8
0
1
R
3
4
5
6
8
9
10
11
12
13
14
15
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
Reserved
W
Reset
7
XFSM XFSM
[1]
[0]
Reserved
W
Reset
2
0
0
0
0
0
0
0
0
0
Figure 14-30. FEC Transmit FSM Register
Table 14-39. FEC Transmit FSM Register Field Descriptions
Bits
Name
0:5
—
6
XFSM[1]
0 Do not append CRC.
1 Append CRC (typical use).
7
XFSM[0]
0 Disable CRC FSM.
1 Enable CRC FSM (typical use is enabled).
8:31
—
14.5
Description
Reserved
Reserved
Initialization Sequence
This section describes which registers are hardware reset, which are reset by the FEC and what locations
the user must initialize prior to enabling the FEC.
14.5.1
Hardware Controlled Initialization
Some registers in the FEC are reset by internal logic. Specifically those registers are control logic that
generate interrupts, cause outputs to be asserted and, in general, configuration control bits.
Other registers are reset when the ETHER_EN bit is not asserted (i.e., cleared). To halt operation
ETHER_EN is deasserted by either a hard reset or by software. By deasserting ETHER_EN configuration
control registers such as X_CNTRL and R_CNTRL are not reset, but the entire data path is reset.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-40 shows the effect deasserting ETHER_EN has on Ethernet MAC operation and registers.
Table 14-40. ETHER_EN De-Assertion Affect on FEC
14.5.2
Register/Machine
Reset Value
XMIT block
Transmission Aborted (bad CRC appended)
RECV block
Receive activity aborted
Tx/Rx FIFO
Reset control logic dependent on reset_cntrl
User Initialization (Prior to Asserting ETHER_EN)
The user needs to initialize portions of the FEC prior to setting the ETHER_EN bit. The exact values
depend on the particular application; the sequence of writing the registers is not important. Ethernet MAC
registers requiring initialization are defined in Table 14-41.
Table 14-41. User Initialization (Before ETHER_EN)
Description
Initialize IMASK
Clear IEVENT (write FFFF_FFFF)
X_WMRK (optional)
IADDR2/IADDR1
GADDR1/GADDR2
PADDR1/PADDR2
OP_PAUSE (only needed for FDX flow control)
R_CNTRL
X_CNTRL
MII_SPEED (optional)
Clear MIB_RAM (locations 200–2FC)
14.5.2.1
Microcontroller Initialization
In the FEC the descriptor control RISC initializes some registers after ETHER_EN is asserted. After the
microcontroller initialization sequence is complete, hardware is ready for operation.
Table 14-42 shows RISC initialization operations common to the FEC.
Table 14-42. Microcontroller Initialization (FEC)
Description
Initialize BackOff random number seed
Activate Receiver
Activate Transmit
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-47
Fast Ethernet Controller (FEC)
14.5.3
Frame Control/Status Words
In the FEC transmit frame control words and receive frame status words cross the following the end of
frame data. These words are marked with a type value of 10 and have the following formats.
14.5.3.1
Receive Frame Status Word
Figure 14-31 below defines the format for the receive frame status word.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
(Last)
0
0
0
BC
MC
LG
NO
0
CR
OV
TR
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
FRAME_LENGTH
Figure 14-31. Receive Frame Status Word Format
Bits 31-28, 26-25, 19 and 15-11—Reserved
Table 14-43. Receive Frame Status Word Format Field Descriptions
Bits
Name
0:3
—
Reserved
4
L
Last in Frame, written by the FEC
The buffer is not the last in a frame.
The buffer is the last in a frame.
5:7
Description
Reserved
8
BC
Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF)
9
MC
Will be set if the DA is multicast and not BC
10
LG
Rx Frame Length Violation, written by the FEC.
A frame length greater than R_CNTRL.MAX_FL was recognized. This bit is valid only if the L-bit
is set. The receive data is not altered in any way unless the length exceeds 2047 bytes.
11
NO
Rx Non-octet Aligned Frame, written by the FEC.
A frame that contained a number of bits not divisible by 8 was received and the CRC check that
occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is
set. If this bit is set the CR bit will not be set.
12
Reserved
13
CR
Rx CRC Error, written by the FEC.
This frame contains a CRC error and is an integral number of octets in length. This bit is valid
only if the L-bit is set.
14
OV
Overrun, written by the FEC.
A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M,
LG, NO, SH, CR, and CL lose their normal meaning and will be zero. This bit is valid only if the
L-bit is set.
15
TR
Rx Frame Truncated
Will be set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set the
frame should be discarded and the other error bits should be ignored as they may be incorrect.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-43. Receive Frame Status Word Format Field Descriptions (continued)
Bits
Name
Description
16:20
21:31
14.5.3.2
Reserved
FRAME_
LENGTH
Length of Received Frame
Transmit Frame Control Word
The only requirement for this control word is to have the TC and ABC bits valid. The TC bit defines
whether the transmit block should append the CRC (TC = 1) or not (TC = 0) for the current frame. The
ABC bit defines whether the transmit block should append a bad CRC (ABC = 1), independent of the TC
value. Refer to Figure 14-32 below for the format of the transmit frame control word.
0
16
1
2
17
18
3
4
19
20
5
6
TC
ABC
21
22
7
8
9
0
11
12
13
14
15
23
24
25
26
27
28
29
30
31
Figure 14-32. Transmit Frame Control Word Format
Bits 31-27, 24-0—Reserved
Table 14-44. Transmit Frame Control Word Format Field Descriptions
Bits
Name
0:4
—
Reserved
5
TC
Transmit CRC, written by user
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
6
ABC
7:31
Description
Append Bad CRC, written by user
0 No affect
1 Transmit the CRC sequence inverted after the last data bye (regardless of TC value).
Reserved
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-49
Fast Ethernet Controller (FEC)
14.5.4
Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by the MII_MODE bit in the R_CNTRL register. In MII
mode (R_CNTRL.MII_MODE = 1) there are 18 signals defined by the 802.3 standard and supported by
the FEC. These are shown in Table 14-1.
The 7-Wire serial interface (R_CNTRL.MII_MODE = 0) operates in what is generally referred to as the
“AMD” mode.
The Ethernet transmitter is designed to work with almost no intervention from software. Once
ETHER_EN is asserted and data appears in the transmit FIFO the Ethernet MAC is able to transmit onto
the network.
When the transmit FIFO fills to the watermark (defined by the X_WMRK register), the MAC transmit
logic will assert TX_EN and start transmitting the preamble sequence, the start frame delimiter, and then
the frame information from the FIFO. However, the controller defers the transmission if the network is
busy (carrier sense is asserted). Before transmitting, the controller waits for carrier sense to become
inactive, then determines if carrier sense stays inactive for 60 bit times. If so, then the transmission begins
after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive).
If a collision occurs during transmission of the frame (half-duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The
transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved
from system memory in case of a collision. This improves bus utilization and latency in case immediate
retransmission is necessary.
When all the frame data has been transmitted, the FCS (32-bit CRC) bytes are appended if the TC bit is
set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC
will be appended to the frame data regardless of the TC bit value. Following the transmission of the CRC,
the Ethernet controller writes the frame status information to the MIB block. Short frames are
automatically padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of
frame buffer = 1).
The FEC frame interrupts may be generated as determined by the settings in the IMASK register.
Transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, XFIFO_UN and
XFIFO_ERROR. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be
asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (Graceful Transmit Stop) bit in the X_CNTRL register. When the GTS
is set the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame either finishes or terminates with a collision. After the transmitter has
stopped the GRA (Graceful Stop Complete) interrupt is asserted. If GTS is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
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Freescale Semiconductor
Fast Ethernet Controller (FEC)
14.5.5
FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking and maximum frame length checking.
When the driver enables the FEC receiver by asserting ETHER_EN it will immediately start processing
receive frames. When RX_DV asserts, the receiver will first check for a valid PA/SFD header. If the
PA/SFD is valid it will be stripped and the frame will be processed by the receiver. If a valid PA/SFD is
not found the frame will be ignored.
In 7-wire serial mode, the first 16 bit times of RX_D0 following assertion of RX_DV (RENA) are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1s and 0s. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the
data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is
detected, the PA/SFD sequence is complete.
In MII mode the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA.
If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified
to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which
indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, SH, CR, OV and TR status bits, and the frame length.
The Ethernet controller receives serial data LSB first.
14.5.6
Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual (unicast), group
(multicast) or broadcast (all-ones group address). The difference between an individual address and a
group address is determined by the I/G bit in the destination address field. A flowchart for address
recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running on the
microcontroller. The flowchart shown in Figure 14-33 illustrates the address recognition decisions made
by the receive block, while Figure 14-34 illustrates the decisions made by the microcontroller.
If the DA is a broadcast address and broadcast reject (R_CNTRL.BC_REJ) is deasserted, then the frame
will be accepted unconditionally as shown in Figure 14-33. Otherwise, if the DA in not a broadcast address
the microcontroller runs the address recognition subroutine as shown in Figure 14-34.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-51
Fast Ethernet Controller (FEC)
Accept/Reject
Frame
True
Broadcast Addr
?
False
Receive
Address
Recognition
False
Receive Frame
Set BC bit in RCV BD
True
AR_HM_B = 0
?
BC_REJ = 1
?
False
True
Receive Frame
Set MC bit in RCV BD if multicast
AR_EM_B = 0
?
True
False
Pause Frame True
?
False
Reject Frame
Flush from FIFO
PROM = 1
?
True
Receive Frame
Set M (Miss) bit in Rcv BD
Set MC bit in Rcv BD if multicast
Set BC bit in Rcv BD if broadcast
False
Reject Frame
Flush from FIFO
Receive Frame
NOTES:
BC_REJ - field in R_CNTRL register (BroadCast REJect)
Check Address - microcode Address Recognition subroutine; returns AR_HM_B and AR_EM_B
AR_EM_B - bit in RECV.AR_DONE register (address recognition exact match bar)
AR_HM_B - bit in RECV.AR_DONE register (address recognition hash match bar)
PROM - field in R_CNTRL register (PROMiscous mode)
Pause Frame - valid PAUSE frame received
Figure 14-33. Ethernet Address Recognition—Receive Block Decisions
If the DA is a group (multicast) address and flow control is disabled the microcontroller will perform a
group hash table lookup using the 64-entry hash table programmed in GADDR1 and GADDR2. If a hash
match occurs AR_HM_B (address recognition hash match bar) is set to 0 and the receiver accepts the
frame. If flow control is enabled the microcontroller will do an exact address match check between the DA
and the designated PAUSE DA in registers XMIT.FDXFC_DA1 and XMIT.FDXFC_DA2. In the case
where a PAUSE DA exact match occurs AR_EM_B (address recognition exact match bar) is set to 0. If
the receive block determines that the received frame is a valid PAUSE frame the frame will be rejected.
Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or
the unicast physical address.
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Fast Ethernet Controller (FEC)
Receive Address
Recognition
Group
False
True
FCE
?
False
Individual
I/G Address
?
False
Pause Address
?
Hash Search
Group Table
Match
?
False
ar_em_b = 1
ar_hm_b = 1
Exact Match
?
True
Hash Search
Individual Table
ar_em_b = 0
ar_hm_b = 1
ar_em_b = 0
ar_hm_b = 1
True
True
True
Match
?
False
ar_em_b = 1
ar_hm_b = 0
ar_em_b = 1
ar_hm_b = 0
ar_em_b = 1
ar_hm_b = 1
NOTES:
FCE - field in R_CNTRL register (Flow Control Enable)
AR_EM_B - bit in RECV.AR_DONE register (address recognition exact match bar)
AR_HM_B - bit in RECV.AR_DONE register (address recognition hash match bar)
I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
Figure 14-34. Ethernet Address Recognition—Microcode Decisions
If the DA is the individual (unicast) address the microcontroller performs an individual exact match
comparison between the DA and 48-bit physical address that the user programs in the PADDR1 and
PADDR2 registers. If an exact match occurs AR_EM_B is set to 0; otherwise, the microcontroller does an
individual hash table lookup using the 64-entry hash table programmed in registers IADDR1 and
IADDR2. In the case of an individual hash match AR_HM_B is set to 0. Again, the receiver will accept
or reject the frame based on PAUSE frame detection, shown in Figure 14-33.
If neither a hash match (group or individual) nor an exact match (group or individual) occur both
AR_HM_B and AR_EM_B are set to 1. In this case, if promiscuous mode is enabled
(R_CNTRL.PROM = 1), then the frame will be accepted and the MISS bit in the receive buffer descriptor
is set; otherwise, the frame will be rejected and the MISS bit will be cleared.
Similarly, if the DA is a broadcast address, broadcast reject (R_CNTRL.BC_REJ) is asserted and
promiscuous mode is enabled. Then the frame will be accepted and the MISS bit in the receive buffer
descriptor is set; otherwise, the frame will be rejected and the MISS bit will be cleared.
In general, when a frame is rejected it is flushed from the FIFO.
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-53
Fast Ethernet Controller (FEC)
The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit
destination address is mapped into one of 64 bits which are represented by 64 bits stored in GADDR1,2
(group address hash match) or IADDR1,2 (individual address hash match). This mapping is performed by
passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the 6 most significant
bits of the CRC-encoded result to generate a number between 0 and 63. The MSB of the CRC result selects
GADDR1 (MSB = 1) or GADDR2 (MSB = 0). The least significant 5 bits of the hash result select the bit
within the selected register. If the CRC generator selects a bit that is set in the hash table, the frame is
accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group addresses are received,
the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory.
Those that do reach memory must be further filtered by the processor to determine if they truly contain
one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
The hash table registers must be initialized by the user. The user may compute the hash for a particular
address in software. The CRC32 polynomial to use in computing the hash is:
X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1
A table of example Destination Addresses and corresponding hash values is included below for reference.
Table 14-45. Destination Address to 6-Bit Hash (Sheet 1 of 3)
48-Bit DA
6-Bit Hash (in hex)
Hash Decimal Value
65:ff:ff:ff:ff:ff
0x0
0
55:ff:ff:ff:ff:ff
0x1
1
15:ff:ff:ff:ff:ff
0x2
2
35:ff:ff:ff:ff:ff
0x3
3
b5:ff:ff:ff:ff:ff
0x4
4
95:ff:ff:ff:ff:ff
0x5
5
d5:ff:ff:ff:ff:ff
0x6
6
f5:ff:ff:ff:ff:ff
0x7
7
db:ff:ff:ff:ff:ff
0x8
8
fb:ff:ff:ff:ff:ff
0x9
9
bb:ff:ff:ff:ff:ff
0xa
10
8b:ff:ff:ff:ff:ff
0xb
11
0b:ff:ff:ff:ff:ff
0xc
12
3b:ff:ff:ff:ff:ff
0xd
13
7b:ff:ff:ff:ff:ff
0xe
14
5b:ff:ff:ff:ff:ff
0xf
15
27:ff:ff:ff:ff:ff
0x10
16
07:ff:ff:ff:ff:ff
0x11
17
57:ff:ff:ff:ff:ff
0x12
18
77:ff:ff:ff:ff:ff
0x13
19
MPC5200B User’s Manual, Rev. 3
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Freescale Semiconductor
Fast Ethernet Controller (FEC)
Table 14-45. Destination Address to 6-Bit Hash (Sheet 2 of 3)
48-Bit DA
6-Bit Hash (in hex)
Hash Decimal Value
f7:ff:ff:ff:ff:ff
0x14
20
c7:ff:ff:ff:ff:ff
0x15
21
97:ff:ff:ff:ff:ff
0x16
22
a7:ff:ff:ff:ff:ff
0x17
23
99:ff:ff:ff:ff:ff
0x18
24
b9:ff:ff:ff:ff:ff
0x19
25
f9:ff:ff:ff:ff:ff
0x1a
26
c9:ff:ff:ff:ff:ff
0x1b
27
59:ff:ff:ff:ff:ff
0x1c
28
79:ff:ff:ff:ff:ff
0x1d
29
29:ff:ff:ff:ff:ff
0x1e
30
19:ff:ff:ff:ff:ff
0x1f
31
d1:ff:ff:ff:ff:ff
0x20
32
f1:ff:ff:ff:ff:ff
0x21
33
b1:ff:ff:ff:ff:ff
0x22
34
91:ff:ff:ff:ff:ff
0x23
35
11:ff:ff:ff:ff:ff
0x24
36
31:ff:ff:ff:ff:ff
0x25
37
71:ff:ff:ff:ff:ff
0x26
38
51:ff:ff:ff:ff:ff
0x27
39
7f:ff:ff:ff:ff:ff
0x28
40
4f:ff:ff:ff:ff:ff
0x29
41
1f:ff:ff:ff:ff:ff
0x2a
42
3f:ff:ff:ff:ff:ff
0x2b
43
bf:ff:ff:ff:ff:ff
0x2c
44
9f:ff:ff:ff:ff:ff
0x2d
45
df:ff:ff:ff:ff:ff
0x2e
46
ef:ff:ff:ff:ff:ff
0x2f
47
93:ff:ff:ff:ff:ff
0x30
48
b3:ff:ff:ff:ff:ff
0x31
49
f3:ff:ff:ff:ff:ff
0x32
50
d3:ff:ff:ff:ff:ff
0x33
51
53:ff:ff:ff:ff:ff
0x34
52
73:ff:ff:ff:ff:ff
0x35
53
23:ff:ff:ff:ff:ff
0x36
54
13:ff:ff:ff:ff:ff
0x37
55
3d:ff:ff:ff:ff:ff
0x38
56
0d:ff:ff:ff:ff:ff
0x39
57
5d:ff:ff:ff:ff:ff
0x3a
58
7d:ff:ff:ff:ff:ff
0x3b
59
MPC5200B User’s Manual, Rev. 3
Freescale Semiconductor
14-55
Fast Ethernet Controller (FEC)
Table 14-45. Destination Address to 6-Bit Hash (Sheet 3 of 3)
14.5.7
48-Bit DA
6-Bit Hash (in hex)
Hash Decimal Value
fd:ff:ff:ff:ff:ff
0x3c
60
dd:ff:ff:ff:ff:ff
0x3d
61
9d:ff:ff:ff:ff:ff
0x3e
62
bd:ff:ff:ff:ff:ff
0x3f
63
Full-Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames.
Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (X_CNTRL.FDEN asserted)
and flow control enable (R_CNTRL.FCE) must be asserted. The FEC detects a pause frame when the
fields of the incoming frame match the pause frame specifications as shown in the table below. In addition,
the receive status associated with the frame should indicate that the frame is valid
Table 14-46. PAUSE Frame Field Specification
48-Bit Destination
Address
0180_c200_0001
or Physical Address
48-bit Source Address
any
16-bit type
8808
16-bit opcode
0001
16-bit PAUSE duration
0000 to ffff
Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs
an address recognition subroutine to detect the specified pause frame destination address, while the
receiver detects the type and opcode pause frame fields. On detection of a pause frame, graceful transmit
stop is asserted by the FEC internally. When transmission has paused, the GRA (Graceful Stop complete)
interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the
transmit backoff timer hardware which is used for tracking the appropriate collision backoff time in
half-duplex mode. The pause timer increments once every slot time until PAUSE_DURATION slot times
have expired. On PAUSE_DURATION expiration, graceful transmit stop is deasserted allowing MAC
data frame transmission to resume. Note that the receive flow control pause (X_CNTRL.RFC_PAUSE)
status bit is asserted while the transmitter is paused due to reception of a pause frame.
To transmit a pause frame the FEC must operate in full-duplex mode and the user must assert flow control
pause (X_CNTRL.TFC_PAUSE). On assertion of transmit flow control pause (X_CNTRL.TFC_PAUSE)
the transmitter asserts graceful transmit stop internally. When the transmission of data frames stops the
GRA (Graceful Stop complete) interrupt asserts. Following GRA assertion the Pause frame is transmitted.
On completion of pause frame transmission flow control pause (X_CNTRL.TFC_PAUSE) and graceful
transmit stop are deasserted internally.
MPC5200B User’s Manual, Rev. 3
14-56
Freescale Semiconductor
Fast Ethernet Controller (FEC)
During pause frame transmission the transmit hardware places data into the transmit data stream from the
registers shown in the table below.
Table 14-47. Transmit Pause Frame Registers
PAUSE FRame Fields
FEC Register
Register Contents
48-bit destination address
{FDXFC_DA1[0:31], FDXFC_DA2[0:15]}
0180_c200_0001
48-bit Source Address
{PADDR1[0:31], PADDR2[0:15]}
physical address
16-bit type
PADDR2[16:31]
8808
16-bit opcode
OP_PAUSE[0:15]
0001
16-bit PAUSE duration
OP_PAUSE[16:31]
0000 to ffff
The user must specify the desired pause duration in the OP_PAUSE register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit
flow control pause (X_CNTRL.TFC_PAUSE) still may be asserted and will cause the transmission of a
single pause frame. In this case the GRA interrupt will not be asserted.
14.5.8
Inter-Packet Gap Time
The minimum inter packet gap time for back-to-back transmission is 96 bit times. After completing a
transmission or after the backoff algorithm completes the transmitter waits for carrier sense to be negated
before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense
is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times it
will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an
inter-packet gap between receive frames is less than 28 bit times the following frame may be discarded by
the receiver.
14.5.9
Collision Handling
If a collision occurs during frame transmission the Ethernet controller will continue the transmission for
at least 32 bit times, transmitting a JAM pattern consisting of 32 one’s. If the collision occurs during the
preamble sequence the JAM pattern will be sent after the end of the preamble sequence.
If a collision occurs within 64 byte times the retry process is initiated.