Keysight W6600A Series LPDDR4 BGA Interposers

Keysight W6600A Series
LPDDR4 BGA Interposers
Data Sheet
02 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Table of Contents
Introduction................................................................................................................... 3
LPDDR4 BGA Interposer and Cabling Selection Guide............................................... 4
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s,
CA Channel A, Partial DQ........................................................................................ 5
Software........................................................................................................................ 12
Configuration Guide and Ordering Information........................................................... 23
Related Products........................................................................................................... 24
Related Literature......................................................................................................... 24
Introduction
The Keysight Technologies, Inc. W6600A Series LPDDR4 BGA interposers enable probing of embedded
memory LPDDR4 DRAM from the ball grid array with Keysight U4164A logic analyzers.
The W6600A Series LPDDR4 BGA interposers are designed to take full advantage of quad sample state
mode on U4164A modules with Option 02G, requiring only a single probe point for up to four samples at two
different thresholds. W6600A Series BGA interposers are designed to capture data rates in excess of
3.2 Gb/s.
The LPDDR4 BGA interposer advantage
Features
Direct connection to the LPDDR4 BGA balls using a riser
LPDDR4 200-ball DRAM at data rates up to and including
3.2 Gb/s with W6601A
LPDDR4, decode, functional compliance and performance
analysis using optional software tools
APS (advanced probe pettings) to enable DQ (data) capture
over 1866 Mb/s
Leaded or lead-free solder supported
Contract manufactures available for those without the
in-house expertise or facilities for soldering BGAs
Flexible “wings” with ZIF connectors
Benefits
Eliminates reflections from mid-bus probing methods. Also
eliminates design time, prototype builds, and trace routing
required to design in alternative probing methods
Accelerates navigation and insight of information captured
in the logic analyzer trace via multiple different graphs and
views of condensed analysis of LPDDR4 traces
Provides larger eyes to logic analyzer for accurate signal
capture via internal logic analyzer comparator compensation
Works easily with all solder finishes. Designed to tolerate
lead-free soldering temperature profiles
Eliminates the need to develop BGA soldering expertise
Ensures reliable connection to the ZIF probes. Enables
placement of the probe cables around adjacent components.
Minimizes the torque to the balls of the BGA
04 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6600A Series LPDDR4 BGA Interposer Selection Guide
Memory family
LPDDR4
Package
–– 200-ball
–– 0.8 mm x 0.65 mm pitch
–– JEDEC MO-311 footprint
variation xx-x with
maximum DRAM package
size of 10 mm x 15 mm
can fit on top of W6601A
without an additional
(optional) riser or socket
to provide clearance for
the RC components
Data rates
Signal coverage
Use model
In excess of
3200 Mb/s
Command address:
–– All Channel A CA for Bank 0
and Bank 1
–– No Channel B CA
Control: RESET
–– Channel A CKE0, CKE1, ODT,
CS0, CS1, CK_A
–– No Channel B control
Data:
–– DQ0_A, DQ7_A, DMI0_A,
DQSt_A, DQ15_A, DQ8_A,
DQ9_A, DMI1_A
–– DQ0_B, DQ1_B, DQ2_B,
DQ3_B, DQ4_B, DQ7_B,
DMI0_B
–– DQ8_B, DQ9_B, DQ10_B,
DQ11_B, DQ12_B, DMI1_B
Debug and functional
validation for LPDDR4
200-ball DRAM
configured as single
channel system
Keysight BGA
interposer
W6601A
05 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
LPDDR4 200-ball DRAM are dual x16 channel devices. They can be used as two single x16
channel devices or as a single x32 device.
The W6601A LPDDR4 200-ball BGA interposer is designed to satisfy functional debug and
validation for LPDDR4 200-ball chip down systems using the DRAM as a single, 32-bit channel.
If the DRAM is used as two channels, then the W6601A will only provide visibility to the logic
analyzer for the CA and commands for Bank 0 and Bank 1 from Channel A.
Figure 1. Top view of W6601A LPDDR4 200-ball BGA interposer with DRAM installed.
W6601A wings are designed to connect using one U4208A and one U4209A 61 pin ZIF probe/
cables into a single U4164A logic analyzer.
Routing and cabling for the signals is single touch probing and is compatible with both Quad
Sample State mode and Quarter Channel Timing modes of the U4164A logic analyzer. The
exception is that Reset and CKE1 are NOT visible in Quarter Channel Timing mode, as those
signals route into pods (3 and 7) and those pods loose the CK inputs when in Quarter Channel
Timing mode. Quad Sample State mode is available only with Option -02G of the U4164A.
Quarter Channel Timing mode is available in both Options -01G and -02G.
Software configurations for Quad Sample Timing mode and Quarter Channel Timing mode will
be different as the labeling for Read /Write separation and rising /falling edges are not required
in Timing modes.
At speeds under 2500 Mb/s, the W6601A can be used with dual-clock edge clocking and
Dual-Sample mode instead of Quad Sample mode. Even in this reduced speed mode, it is
recommended that the W6601A be used with a U4164A as the U4164A is the only LA with dual
thresholds for Read/Write separation in Dual Sample mode.
Not all DQ are visible to the LA. This is due to routing limitations (even using single touch
probing and the denser 61 pin ZIF). Refer to the W6601A pinout for the signals probed.
The U4208A connects to the left side of the W6601A and the U4209A connects to the right
wing.
Notice: The U4208A and U4209A connect into the U4164A differently when used for the
W6601A than they do for the W4640A Series DDR4 BGA interposers.
06 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Technical characteristics
Figure 2. W6601A signals probed at 200-ball footprint and signal distribution through U4208A and U4209A ZIF probe/cables into the U4164A logic
analyzer. Hardware connections are identical for all three W6601A default software configurations.
–– DQ and DQS highlighted in
‘green’ are probed.
–– CK and CKE highlighted in
‘yellow’ are probed.
–– CA and ODT highlighted in
‘indigo’ are probed.
Figure 3. Signals routed from W6601A into logic analyzer.
07 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Signal access
All signals, including power and ground signals, are passed between the system and memory
chip.
LPDDR4 signal group logic analyzer signal access
Command/Address:
–– All Channel A CA for Bank 0 and Bank 1
–– No Channel B CA
Control and other signals:
–– All for Channel A Bank 0 and Bank 1
–– No Channel B control signals
Data:
–– All except DQS0_c_A, DQS1_c_A, DQ1_A, DQ6_A, DQ14_A, DQ9_A, DQ2_A, DQ5_A,
DQ13_A, DQ10_A, DQ3_A, DQ4_A, DQ12_A, DQ11_A, DQ2_B, DQ5_B, DQ13_B, DQ10_B,
DQ1_B, DQ6_B, DQ14_B, DQ9_B
Power:
–– DDR4 device power is not monitored by the logic analyzer
–– Passed through the interposer through vias
W6601A series Interposers include separate ground, 1.1 V (VDD2/VDDQ), and 1.8 V (VDD1)
planes. For additional installation information, refer to the W6600A Series installation guide at
http://literature.cdn.keysight.com/litweb/pdf/W6600-97000.pdf.
08 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Dimensional drawings
Figure 4a. W6601A top view.
Figure 4b. W6601A side view.
09 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Dimensional drawings (Continued)
0.591”
0.394”
Note: 0.067” thick
Figure 4c. LPDDR4 200-ball riser.
10 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Images
Figure 5. Top view of W6601A.
Figure 6. Bottom view of W6601A.
11 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ
(Continued)
Connecting the U4208A and U4209A probe cables to a U4164A logic
analyzer
In a W6601A interposer setup, you connect the U4208A and U4209A probe cable pods to
U4164A logic analyzer pods per the mapping shown in the Table 1. (Hardware connections are
valid for all three default software configurations.)
Table 1. Pod mapping
U4209A cable pods
Pod A
Pod B
U4208A cable pods
Pod A
Pod B
U4164A inputs
Pod 7
Pod 1
U4164A inputs
Pod 3
Pod 5
Figure 7. Connections between U4208A and U4209A probe cables and logic analyzer pods.
Note: U4208A and U4209A connect to the ZIF wings with the ZIF connector door closing
against the top side of the wing.
12 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software
Default configurations for the W6600A Series interposers are included in the standard B4661A
memory analysis software package. The Keysight B4661A memory analysis software provides
four standard software features and four licensed memory analysis options.
B4661A standard software features
–– Default configurations for DDR and LPDDR probing solutions for Keysight logic analyzers.
There are three default SW configurations for the W6601A:
–– 10 GHz Timing mode
–– State mode under 2500 Mb/s (double edge clocking)
–– State mode over 2500 Mb/s (single edge clocking)
–– DDR setup assistant
–– DDR eye finder/eye scan
–– DDR configuration creator
The Keysight B4661A memory analysis software offers a suite of viewers and tools that include
the industry’s first protocol compliance violation testing capability across speed changes, a
condensed traffic overview for rapid navigation to areas of interest in the logic analyzer trace,
powerful performance analysis graphics, and DDR and LPDDR decoders. With the B4661A
memory analysis software and a Keysight logic analyzer 1, users can monitor DDR3/4 or
LPDDR2/3/4 systems to debug, improve performance, and validate protocol compliance.
Powerful traffic overviews, multiple viewing choices, and real-time compliance violation
triggering help identify elusive DDR/LPDDR system violations.
B4661A software options
–– DDR decoder with physical address trigger tool
–– LPDDR decoder with physical address trigger tool for LPDDR/2/3
–– DDR and LPDDR compliance violation analysis toolset
–– Post-process compliance violation analysis
–– Real-time compliance violation analysis
–– DDR3/4 and LPDDR2/3/4 performance analysis
DDR eye finder and eye scan software
DDR eye scan results of LPDDR4 signals gives you qualitative insight for all signals relative to
each other. LPDDR4 signals are scanned in groups (Clock, CS#, ADD&Command, READ DQ/
DQS, and WRITE DQ/DQS).
Figure 8. Eyescan of CS# shows large clean eyes.
13 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Figure 9. CA eye scans also show large open eyes. Light traffic shows up as incomplete lines in the CA
scans.
14 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Figure 10. Read eye scans show the DQ traces are floating high when not preparing for a burst. Then the
DQ and DQS are driven low prior to the burst. Note that the signal swing during the burst is only 400 mV to
10 mV. (Not unusual for LPDDR4, actually, this is a large swing for LPDDR4.)
15 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Write signal trace eye scans
Figure 11. The LPDDR4 system has two DQS pulses for the Write preamble (per the LPDDR4 specification).
No data is transferred during the Preamble. It is not unusual for the preamble pulse(s) to be shorter than
the DQS pulses (edges that drive DQ transfer).
16 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Optional software
Accelerate LPDDR4 analysis and debug using the B4661A memory analysis software with the
W6601A LPDDR4 200-ball BGA interposer, U4208A and U4209A ZIF probe/cables, and U4164A
logic analyzer.
Figure 12. B4661A Option -4FP/TP/NP transaction decode, memory access overview graph and details
window.
Figure 13. The memory analysis window is the B4661A -4FP/NP/TP option (performance analysis). All tabs
in the Memory Analysis Window are dockable and can be moved around for user viewing preference.
17 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Benefits of the B4661A performance analysis transaction decoder and traffic overview:
–– Condensed view of all command activity in the trace
–– Including details of rank/bank, row, Col, BA, physical ADD, and clock frequency
–– Enables rapid navigation of the trace
–– Click, scroll, or jump to commands of interest
–– Pan/zoom on chart of command activity
–– Place or jump to markers (markers are global across all windows/views)
–– Users can rapidly notice variations in charts of the command activity that either make
sense or do not
Figure 14. Traffic overview with graph. Notice that when you zoom in on the traffic overview graph you can see individual commands. In this trace,
when all Ranks is selected, you only see one color (yellow) for Rank 0 as it is a single rank trace capture.
Figure 15. Zoom into details of command activity using Traffic Overview graph.
Figure 16. Details tab available using B4661A -4FP/NP/TP performance analysis option.
18 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
The Details tab provides additional information on commands:
DDR/LPDDR DRAM banks must be activated (opening a “page” or “row”) prior to any Read/
Write activity to that bank/row. When the memory controller needs to access a different row
address on the bank, a Precharge is issued to “close” the “page”.
The all associated Activates, Reads, Writes, and Precharges are displayed together on the left
side of the Details tab. This is important information for debug and performance optimization of
a system. (Page violations can result in corrupt data, and extra opening and closing of pages,
which takes time and slows system performance.)
On the left side of the Details tab, you will see the data associated with any Read or Write
command selected.
When the Refresh rate falls below the 100%
bar (indicating too few Refresh):
–– Red dots indicate the locations
–– Too few Refresh = risk of data corruption
Figure 17. Refresh rate window.
Refresh rate overview
The refresh rate overview is an industry first. Analyzing a rolling 32 ms (adjustable) window of
refresh activity to provide a percentage result for the minimum number of Refreshes required
(also adjustable). This new analysis view is particularly suited to viewing the unique LPDDR4
refresh window. Deep traces, usually 128 M or deeper are required for meaningful refresh rate
displays.
The Memory Access Overview allows the user to select different X & Y variables to view the
entire Memory space accessed in the trace and to pan and zoom around the address space.
Time on the X and either BA:ROW or Row:BA are particularly insightful for highlighting “hot
spots” of excessive activates to a particular Blank/Row address at a specific time. This can help
users determine if particular memory tests or stimulus are possibly stressing Row Hammer.
(Row hammer is a situation where internal Rows on any specific bank inside the DRAM are
victims of cross talk from surrounding Rows in the bank.)
Figure 18. In Memory Access Overview set for Time Vs. RowAdd:BA, the system under test was steping through row addresses to individual banks. In
this view, users can zoom in and re-draw to see more detail for a specific time.
19 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Line charts
Total data rate
Read data rate
Write data rate
% utilization
Figure 19. Performance analysis overview. B4661A Option -4FP/NP/TP provides data rate performance and percent utilization analysis and graphs.
Figure 20. Clock frequency overview is provided in B4661A Option -4FP/NP/TP.
Clock frequency overview is very interesting to users with systems that are changing frequency.
LPDDR systems can be aggressive at changing clock frequencies to conserve power.
DDR and LPDDR compliance violation analysis tool (B4661A-3FP/TP/NP)
The DDR and LPDDR compliance violation analysis toolset provides two tools under one
license: post-process and real-time compliance violation tools. Both compliance tools cover
DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4.
Key features of both the post-process and real-time compliance violation tools:
–– Test compliance violations across speed changes using the post-process compliance
violation tool
–– Identify DDR/2/3/4 or LPDDR/2/3/4 state machine, protocol compliance, and protocol
level bus cycle timing violations using either post-process or real-time tools
–– Save time with automated real-time DDR2/3/4 or LPDDR2/3/4 protocol compliance
measurements and trace captures using the real-time compliance violation analysis tool
–– Edit parameters of the DDR/LPDDR standard preset tests easily using the enhanced
parameter editing interface for both post-process and real-time tools
20 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Figure 21. LPDDR4 post process compliance tests from B4661A Option -3FP/TP/NP.
21 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Figure 22. Example LPDDR4 parameter with speed changes, READ16 to PRECHARGE (same bank).
The B4661A Option -3FP/TP/NP, post process compliance tool scans the logic analyzer trace capture,
calculates the different speed bins, and runs compliance tests on each speed bin.
22 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Software (Continued)
Figure 23. B4661A Option -2FP/TP/NP, LPDDR4 decode, viewed in Listing window.
The B4661A-2FP/TP/NP option offers a traditional LPDDR decoder for the LA listing window.
Benefits include:
–– Complete decode of LPDDR commands with data associated to specific Reads and Writes
–– Fastest display of decode (page aware)
–– Users can scroll through the listing (or waveform) while computing large traces with the
performance software
23 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Configuration Guide and Ordering Information
W6601A includes
–– LPDDR4 200-ball, 2 wing BGA interposer
–– 200-ball riser for devices under test that have components surrounding the LPDDR4
200-ball DRAM where the surrounding components are too close to install the W6601A
without the riser. Riser includes a ground plane. Riser orientation is critical for proper
operation
W6601A requires
–– Qty (1) U4208A 61-pin ZIF probe/cable to connect between the left wing of the W6601A
and compatible logic analyzer
–– Qty (1) U4209A 61-pin ZIF probe/cable to connect between the right wing of the W6601A
and compatible logic analyzer
–– Qty (1) U4164A logic analyzer module in a chassis with a host controller
Optional for W6601A
–– 200-ball riser for devices under test that have components surrounding the LPDDR4
200-ball DRAM, where the surrounding components are too close to install the W6601A
without the riser. Riser includes a ground plane. Riser orientation is critical for proper
operation
–– The 200-ball riser may be replaced with an optional 200-ball grypper socket
(sold separately): http://www.hsiotech.com/products/released-products/
engineering-products/grypper-family
Recommended configuration
Item
W6601A LPDDR4 200-ball BGA interposer
U4208A 61-pin ZIF probe/cable to connect between the left wing of the W6601A and
compatible logic analyzer
U4209A 61-pin ZIF probe/cable to connect between the right wing of the W6601A and
compatible logic analyzer
U4164A logic analyzer module
M9502A 2 slot chassis
M9536A embedded controller
B4661A Option -2FP/TP/NP LPDDR decoder
B4661A Option -3FP/TP/NP compliance analysis
B4661A Option -4FP/TP/NP performance analysis
Quantity
1
1
1
1
1
1
1
1
1
24 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
Related Products
Item
Modular logic analyzers
U4164A
Description
36-channel, up to 4 Gb/s state, quad state mode, up to 10 GHz timing,
memory depth up to 400 M, AXIe-based logic analyzer module allowing three
modules to merge into one time base
Logic analyzer ZIF probe/cables
U4208A
U4208A probe/cable, 61-pin ZIF, from left wing, no RC, 160-pin direct
connect to logic analyzer front panel connector
U4208A
U4209A probe/cable, 61-pin ZIF, from right wing, no RC, 160-pin direct
connect to logic analyzer front panel connector
Software
Logic and protocol analyzer Required – not licensed; acts as the base software platform
software
B4661A memory analysis
Required – unlicensed base software
Licensed options recommended: Options -2FP/TP/NP, -3FP/TP/NP, and
-4FP/TP/NP
Related Literature
Publication title
W6600 Series LPDDR4 DRAM BGA Interposers - Installation Guide
Probing Solutions for Logic Analyzers - Data Sheet
Infiniium 90000 X-Series Oscilloscopes - Data Sheet
Capture Highest DDR3 Data Rates Using Advanced Probe Settings on Logic Analyzers
- Technical Brief
B4661A Memory Analysis Software for Logic Analyzers - Data Sheet
U4164A Logic Analyzer Module - Data Sheet
Publication number
W6600-97000
5968-4632E
5990-5271EN
5991-0799EN
5992-0984EN
5992-1057EN
25 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
www.axiestandard.org
AdvancedTCA® Extensions for Instrumentation and Test (AXIe) is an
open standard that extends the AdvancedTCA for general purpose and
semiconductor test. Keysight is a founding member of the AXIe consortium.
ATCA®, AdvancedTCA®, and the ATCA logo are registered US trademarks of
the PCI Industrial Computer Manufacturers Group.
www.lxistandard.org
LAN eXtensions for Instruments puts the power of Ethernet and the
Web inside your test systems. Keysight is a founding member of the LXI
consortium.
www.pxisa.org
PCI eXtensions for Instrumentation (PXI) modular instrumentation delivers a
rugged, PC-based high-performance measurement and automation system.
26 | Keysight | W6600A Series LPDDR4 BGA Interposers - Data Sheet
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Published in USA, March 15, 2016
5992-1461EN
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