AM4096 – Angular magnetic encoder IC

AM4096 – Angular magnetic encoder IC
Data sheet
AM4096D02_02
th
Issue 2, 10 March 2010
AM4096 – Angular magnetic encoder IC
Features
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Contactless angular position encoding over
360°
12 bit absolute encoder
Output options:
 Incremental
 Serial SSI
 Serial two wire interface (TWI)
 UVW commutation output
 Linear voltage
 Tacho
 Analogue sinusoidal
Presetable zero position
High speed operation to 60,000 rpm
Power save mode for low current
consumption
5 V or 3 V power supply
Integrated EEPROM
SMD package SSOP28
RoHS compliant (lead free)
Applications
Non-contact position or velocity measurements:

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Motor motion control and commutation
Robotics
Camera positioning
Various encoder applications
Battery powered devices
Other demanding high resolution
applications
General description
The AM4096 uses Hall sensor technology for
sensing the magnetic field. A circular array of
sensors detects the perpendicular component of
the magnetic field. The signals are summed then
amplified. Sine and cosine signals are generated
when the magnet rotates. The sine and cosine
signals are factory calibrated for optimum
performance.
From the sine and cosine values the angular
position is calculated with a fast 12 bit interpolator.
The calculated position is then output in various
digital and analogue formats.
An inbuilt voltage regulator ensures stable
conditions for the core of the chip and a more
flexible power supply voltage. All inputs and
outputs are related to the external supply voltage.
Fig. 1: AM4096 with magnet
The AM4096 has many different setting options
which are defined by the contents of internal
registers. The zero position can be also set with an
external pin. The settings of the chip are stored in
an integrated EEPROM.
The registers and the EEPROM can be accessed
through a serial two wire interface TWI.
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Index
Features ............................................................................................................................................................... 1
Applications .......................................................................................................................................................... 1
General description .............................................................................................................................................. 1
Index ..................................................................................................................................................................... 2
Block diagram....................................................................................................................................................... 3
Pin description ...................................................................................................................................................... 3
Absolute maximum ratings ................................................................................................................................... 5
Operating range conditions .................................................................................................................................. 5
AM4096 programming.......................................................................................................................................... 6
Memory address space ........................................................................................................................................ 7
3/5V operation mode ............................................................................................................................................ 9
Outputs direction .................................................................................................................................................. 9
Sinusoidal analogue outputs for filtering .............................................................................................................. 9
Sinusoidal differential analogue outputs ............................................................................................................ 10
AGC .................................................................................................................................................................... 10
Interpolator ......................................................................................................................................................... 10
Zeroing ............................................................................................................................................................... 11
Incremental output.............................................................................................................................................. 11
Binary synchronous serial output SSI ................................................................................................................ 12
Two wire interface (TWI) output ......................................................................................................................... 13
Tacho output ...................................................................................................................................................... 13
UVW output ........................................................................................................................................................ 14
Linear voltage output.......................................................................................................................................... 14
Hysteresis ........................................................................................................................................................... 16
Nonlinearity ........................................................................................................................................................ 16
Power save mode............................................................................................................................................... 17
Recommended magnet ...................................................................................................................................... 18
Magnet quality and the nonlinearity error .......................................................................................................... 19
Magnet position .................................................................................................................................................. 20
Mounting instructions ......................................................................................................................................... 20
Application scheme ............................................................................................................................................ 21
Ordering information .......................................................................................................................................... 22
RMK4 sample kit ................................................................................................................................................ 23
Document issues ................................................................................................................................................ 24
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Vdda
Vddd
Block diagram
Vext
LDO
Analogue part
LDO
Digital part
Hall array
&
front end
amplifier
B
Sin
Cos
Agnd
EEPROM
32 x16
SSI
Differential
amplifier
Analog
differential
12 bit
interpolator
UVW
10 bit
DA converter
RefP
RefN
A
B
Ri
Clock
Data
Incremental
Sin positive
Sin negative
Cos positive
Cos negative
U
V
W
Linear
voltage
Vout
Tacho
Tout
TWI
SDA
SCL
Registers
AM4096
Zero
Fig. 2: AM4096 block diagram
Pin description
Name
Pin description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Data
Ri
B
A
W/NCos
V/PSin
U/NSin
Td/PCos
Error
Cos
Sin
Vddd
Vext
Vdda
Vss
Agnd
Mag
RefN
RefP
Vout/Tout
PSM
Zero
SDA
SCL
NC
NC
NC
Clock
SSI data output
Incremental output Ri
Incremental output B
Incremental output A
Commutation output W/Cosine negative output
Commutation output V/Sine positive output
Commutation output U/Sine negative output
Tacho direction output/Cosine positive output
Analogue error or amplitude output
Cosine analogue output for filtering
Sine analogue output for filtering
Digital power supply 3.0/3.3V
Power supply input 5V
Analogue power supply 3.0/3.3V
Power supply 0V
Analogue reference voltage
Output, that indicates magnet presence
Lower reference input for voltage output
Upper reference input for voltage output
Linear voltage output/Tacho output
Power save mode input
Zeroing input
TWI serial interface data line
TWI serial interface clock line
Factory test
Factory test
Factory test
SSI clock input
© 2010 RLS
1
Data
Ri
B
A
W/NCos
V/PSin
U/NSin
Td/PCos
Error
Cos
Sin
Vddd
Clock
nc
AM4096
RLSXXXX
Pin nr.
nc
nc
SCL
SDA
Zero
PSM
Vout/Tout
RefP
RefN
Mag
Vext
Agnd
Vdda
Vss
Fig. 3: Pin description for AM4096
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Data sheet
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Issue 2, 10 March 2010
Some pins have more than one function. The function of those pins can be selected over the two wire serial
interface and stored in the chip. All digital input pins all have a pull-down resistor except PSM pin.
Pin 1 (Data) is a digital output for serial SSI communication.
Pin 2 (Ri) is the quadrature incremental reference mark output.
Pin 3 (B) is the quadrature incremental output B.
Pin 4 (A) is the quadrature incremental output A.
Pin 5 (W/NCos) is the commutation digital output W or analogue differential buffered Cosine negative output.
Pin 6 (V/PSin) is the commutation digital output V or analogue differential buffered Sine positive output.
Pin 7 (U/NSin) is the commutation digital output U or analogue differential buffered Sine negative output.
Pin 8 (Td/PCos) is the tacho direction digital output or analogue differential buffered Cosine positive output.
Pin 9 (Error) is the analogue output signal. It can monitor the axial misalignment between the AM4096 and
the magnet or it can monitor the signal amplitude.
Pin 10 (Cos) is the single-ended cosine analogue output for filtering.
Pin 11 (Sin) is the single-ended sine analogue output for filtering.
Pin 12 (Vddd) is the pin for filtering the power supply of the digital part of the chip. The power supply voltage
is selectable between 3 V and 3.3 V.
Pin 13 (Vext) is the external power supply pin (3 V to 5.5 V).
Pin 14 (Vdda) is the pin for filtering the power supply of the analogue part of the chip. The power supply
voltage is selectable between 3 V and 3.3 V.
Pin 15 (Vss) is the power supply pin 0 V.
Pin 16 (Agnd) is the pin for filtering analogue reference voltage (1.55 V).
Pin 17 (Mag) is the digital output for monitoring the magnet presence. If the output is high than the magnet
distance is OK. If the distance is too small or too large, then the output voltage is low.
Pin 18 (RefN) is the reference voltage input for defining the minimum output value of the linear voltage output.
Pin 19 (RefP) is the reference voltage input for defining the maximum output value of the linear voltage
output.
Pin 20 (Vout/Tout) is the linear voltage output or tacho output.
Pin 21 (PSM) is the digital input pin for power save mode operation. The input is floating and it must have
defined input. When the input is low, the power save mode is inactive.
Pin 22 (Zero) is the digital input for zeroing the output position with internal 10k pull-down resistor. The
zeroing is done at transition from low to high.
Pin 23 (SDA) is the data line for the two wire serial interface (TWI).
Pin 24 (SCL) is the clock line for the two wire serial interface (TWI).
Pins 25, 26 and 27 are test pins and must be left unconnected.
Pin 28 (Clock) is the digital clock input for SSI communication with internal 10k pull-down resistor.
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Absolute maximum ratings
Ambient temperature TA = 22 °C unless otherwise noted.
Parameter
Supply voltage
Input pin voltage
Input current (latch-up immunity)
Electrostatic discharge
Operating junction temperature
Storage temperature range
Symbol
Vext
Vin
Iscr
ESD
Tj
Tst
Min.
-0.3
-0.3
-100
-40
-40
Max.
5.5
5.5
100
2
140
150
Unit
V
V
mA
kV
°C
°C
Note
*
* Human Body Model
Operating range conditions
Parameter
General
Temperature range
Temperature range for EEPROM write
Supply voltage
Supply current
Power-up time
Interpolator delay
Sensors delay
Filtering delay
Oscillator
Oscillator frequency
Oscillator frequency temperature drift
fosc power supply dependence
Digital outputs
Saturation voltage hi (Vext-Vout)
Saturation voltage lo
Rise time
Fall time
Digital inputs
Threshold voltage hi
Threshold voltage lo
Hysteresis
Symbol
Min.
Typ.
TO
TOE
Vext
Idd
tp
tdi
tds
tdf
-40
-40
3
*
125
115
5
26
1.5
0.7
10
20
fosc
TCosc
VCosc
8
Vshi
Vslo
tr
tf
137
124
4
3
Vthi
Vtlo
Vthys
0.39
0.30
0.08
10
-0.006
3
0.5
0.38
0.12
Max.
5.5
30
2
12
Unit
°C
°C
V
mA
ms
µs
µs
µs
Note
*
**
MHz
%/K
%/V
***
490
339
12
9
mV
mV
ns
ns
Iload= 2mA
Iloa = 2mA
Cload= 15+3pF
Cload= 15+3pF
0.59
0.45
0.15
Vext
Vext
Vext
* When in power-save mode the average supply current is significantly reduced.
** Typical time delay is calculated for filter capacitors 10 nF.
*** Due to internal supply regulator only 3 V or 3.3 V is possible.
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
AM4096 programming
The AM4096 can be programmed over the two-wire serial interface (TWI) which is compatible with I2C
protocol with a 400 kbps bit-rate speed.
The TWI protocol allows the to interconnect up to 128 individually addressable devices using only two bidirectional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to
implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus
have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol.
Vext
Device 1
Device 2
......
Device n
R1 R2
SDA
SCL
Fig. 4: TWI bus interconnection
The TWI bus is a multi-master bus where one or more devices, capable of taking control of the bus, can be
connected. Only Master devices can drive both the SCL and SDA lines while a Slave device is only allowed to
issue data on the SDA line. Data transfer is always initiated by a Bus Master device. A high to low transition
on the SDA line while SCL is high is defined to be a START condition (or a repeated start condition).
Fig. 5: TWI Address and Data Packet Format
A START condition is always followed by the (unique) 7-bit slave addresses and then by a Data Direction bit.
The Slave device addressed now acknowledges to the Master by holding SDA low for one clock cycle. If the
Master does not receive any acknowledge the transfer is terminated. Depending of the Data Direction bit, the
Master or Slave now transmits 8-bit of data on the SDA line. The receiving device then acknowledges the
data. Multiple bytes can be transferred in one direction before a repeated START or a STOP condition is
issued by the Master. The transfer is terminated when the Master issues a STOP condition. A STOP condition
is defined by a low to high transition on the SDA line while the SCL is high. If a Slave device cannot handle
incoming data until it has performed some other function, it can hold SCL low to force the Master into a waitstate. All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an
acknowledge bit. During a data transfer, the master generates the clock and the START and STOP
conditions, while the receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is
signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA
line high, a NACK is signaled.
The AM4096 has a default slave address of 00h. This address can be changed for each device. The
functionality of the device can be programmed on the addresses between 0 and 55 with 16 bit long words.
Address
00 – 31
32 – 35
40 – 41
48 – 55
© 2010 RLS
Functionality
Read/Write EEPROM
Read registers for reading the output data
Write registers for factory tests
Read/Write registers with settings
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Data sheet
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Issue 2, 10 March 2010
The AM4096 device acts as a slave and supports two modes:
1) Master transmits to slave. This mode is used to write to the AM4096 address space. The 16 bit data word
is divided into two 8 bit data frames. The ACK acknowledges are provided by the slave.
ACK
8 BIT MSB DATA
8 BIT LSB DATA
STOP
8 BIT MEM. ADDRESS
ACK
ACK
ACK
WRITE
START
7 BIT SLAVE ADDRESS
Fig.6: Write data packet
After the EEPROM write packet (memory address 00h – 1Fh) the slave device can not be addressed for a
time of 10 ms. In this time the slave is performing the internal EEPROM write process. If the device is
addressed, no ACK is returned.
2) Combined format mode is used to read the AM4096 address space. If the EEPROM address space is
addressed (00h – 1Fh), then the slave uses clock stretching during the internal EEPROM read time (minimum
20 µs).
ACK
8 BIT MSB DATA
8 BIT LSB DATA
STOP
ACK
ACK
7 BIT SLAVE ADDRESS
READ
8 BIT MEM. ADDRESS
SR
ACK
ACK
WRITE
START
7 BIT SLAVE ADDRESS
Fig. 7: EEPROM read data packet, with clock stretching
If the R or R/W registers are addressed, then the device response is immediate. After the two DATA packets
the ACK is not verified.
ACK
8 BIT MSB DATA
STOP
ACK
ACK
7 BIT SLAVE ADDRESS
READ
SR
8 BIT MEM. ADDRESS
ACK
ACK
WRITE
START
7 BIT SLAVE ADDRESS
8 BIT LSB DATA
Fig.8: Register read data packet
R
R/W
R/W
R/W
R
REGISTERS
R
R
EEPROM
R/W
Memory address space
ADR
0
1
2
3
4
5
6
7
8
9
10
…
28
29
30
31
32
33
34
35
…
40
41
…
48
49
50
51
52
53
54
55
15
Pdint
Abridis
Dact
14
AGCdis
Bufsel
13
Monsel
12
Slowint
Sign
11
10
Pdtr
8
Reg35
7
-
6
5
4
3
Addr
2
1
0
Zin
Nfil
SSIcfg
Dac
9
Pdie
-
-
Hist
Daa
Sth
UVW
Res
Factory settings data.
This part of EEPROM is locked.
Free EEPROM space
Device identification number. This part of EEPROM is locked.
SRCH
SRCH
Weh
Wel
AGCgain
Rpos
Apos
-
Tho
Thof
Not available
Only for testing. For normal operation must be zeros.
Pdint
Abridis
Dact
AGCdis
Bufsel
Dac
Monsel
Slowint
Sign
Nfil
SSIcfg
Pdtr
Pdie
Not available
Reg35
-
Addr
Zin
-
-
Daa
Sth
Hist
UVW
Res
Factory settings data.
Those registers are locked.
AM4096 has EEPROM and registers with 16 bit word organization. AM4096 operates according to the
contents in registers. When the chip is powered-on the EEPROM contents from address 0 to 7 is copied to
the registers from 48 to 55. This is also done with every change in the EEPROM. Registers from 48 to 51 can
be accessed for fast non-permanent setting changes. Registers from 32 to 35 can be used for fast readings of
the measured data.
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Description of parameters:
Parameter
Length
Description
Logic
Note
Pdint
1
Interpolator power
0= on, 1= off
Interpolator power can be switched
off, if only analogue outputs are used.
AGCdis
1
AGC disable
0= AGC on, 1= AGC off
Slowint
1
Interpolator delay
0= on, 1= off
Pdtr
2
Pdie
Reg35
Adr
1
1
7
Abridis
1
00= 1:128, 01= 1:256,
10= 1:512, 11= 1:1024
0= disabled, 1= enabled
0= 3V, 1= 3.3V
From 0 to 127
0= enabled,
1= disabled
Bufsel
1
Monsel
1
Sign
1
Zin
Nfil
12
8
Daa
1
Hist
7
Internal power down
rate
Internal power down
Regulator voltage
Device address
Enabling A B Ri
outputs
Selects the output
on pins U/NSin,
V/PSin, W/NCos,
Td/PCos
Selects the output
on Error pin
Selects the output
direction
Zero position data
Test parameters
Output position
selection
Digital hysteresis
value in LSB at 12
bit resolution
Select the output on
Vout/Tout pin
Dact
1
Dac
2
SSIcfg
2
Sth
3
UVW
3
Res
3
SRCH
1
Rpos
Apos
12
12
Weh
1
Wel
1
Thof
1
Tacho overflow info
Tho
10
Tacho output data
© 2010 RLS
Linear voltage
period selection
SSI settings
Tacho measuring
range
UVW number of
periods/turn
Interpolation factor
rate
Output position data
valid
Relative position inf.
Absolute position inf.
Magnet too far
status
Magnet too close
status
0= UVW, Tacho
direction
1=Sinusoidal differential
It must always be set to 1. Currently it
is not allowed to use value 0.
See power save mode description.
See power save mode description.
Default address is set to 0.
Incremental output can be disabled if
not used.
Interpolator may not work properly
when sinusoidal differential analogue
outputs are on.
0= error signal,
1= amplitude level signal
0= positive, 1= negative
0= 0°, 4095= 360°
0= relative, 1= absolute
Must be zeros
Absolute position is not affected by
zeroing while relative position is.
From 0 to 127
0= position data on
Vout/Tout pin
1= tacho data on
Vout/Tout pin
00= 360°, 01= 180°,
10= 90°, 11= 45°
See SSI description.
See table in tacho output description.
000= 1, 001=2, 010= 3,
011= 4, ..., 111= 8
000= 4096, 001= 2048,
... 110= 64, 111= 32
0= valid data,
1= data not valid yet
0= 0°, 4095= 360°
0= 0°, 4095= 360°
0= magnet distance ok,
1= magnet is too far
0= magnet distance ok,
1= magnet is too close
0= speed in range,
1= speed out of range
0= 0, 1023= full
measuring range
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Data sheet
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Issue 2, 10 March 2010
3/5V operation mode
The AM4096 can operate with power supply voltage from 3 V to 5.5 V. The outputs and inputs are supplied
with the external voltage. The core of the chip is always powered with the regulated voltage from the LDO
voltage regulator. The voltage of the regulator can be selected with the “Reg35” parameter between 3 V and
3.3 V. When the external power supply is from 3 V to 3.3 V the regulator voltage should be set to 3 V. When
the external power supply voltage is from 3.3 V to 5.5 V the regulator voltage should be set to 3.3 V.
Outputs direction
Fig. 9: CW rotation
The direction of the outputs can be changed by changing the “Sign” parameter. The arrow in Fig. 9 shows
clockwise (CW) rotation of the magnet. The picture is a top view of the magnet placed above the AM4096.
Sinusoidal analogue outputs for filtering
Agnd is an internally generated reference voltage. It is used as a zero level for the analogue signals, the
voltage is typically 1.55 V. Pins 10 and 11 are unbuffered sinusoidal analogue outputs used for filtering and
for testing purposes.
Unbuffered sinusoidal outputs:
Symb.
Min
Rn
3
Typ
Max
Unit
kΩ
2
Analogue output [V]
Parameter
Internal serial
impedance
Fig. 10 shows the timing diagram for CW rotation
of the recommended magnet.
Sinusoidal outputs produce one period of sine and
cosine signal per turn with phase difference of 90°.
Each signal has the same amplitude and minimum
offset with respect to Agnd.
AGC controls the amplitude of the signals within
20%. AGC can be disabled if “AGCdis” parameter
is set to 1.
2
A
Sine
Agnd
Cosine
1
0
0
90
180
Magnet rotation [°]
270
360
Fig. 10: Timing diagram for analogue output
Sinusoidal signal parameters:
Parameter
Amplitude
Vref voltage
Max. frequency
Symbol
A
VVref
fMax
Min.
0.5
Typ.
0.83
1.55
1000
Max.
1.1
Unit
V
V
Hz
Note
*
* Amplitude = 1/2 of peak to peak value.
© 2010 RLS
9/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Sinusoidal differential analogue outputs
Sinusoidal signals can be output as sinusoidal differential signals when the “BufSel” parameter is set to 1. The
interpolator may not work properly when the differential analogue outputs are on. If analogue outputs are not
needed then the “BufSel” parameter should be set to 0.
Analogue differential output [V]
3
Sine +
Cosine -
2
A
1
Pin name
“W/NCos”
“V/PSin”
“U/NSin”
Td/PCos
Cosine +
Sine -
0
0
90
180
Magnet rotation [°]
270
Pin function
Cosine negative
Sine positive
Sine negative
Cosine positive
360
Fig. 11: Timing diagram for differential analogue output
Parameter
Amplitude
Amplitude difference
Phase difference
Sine offset
Cosine offset
Max. frequency
Symbol
A
dA
dPh
Soffs
Coffs
fMax
Min.
1
89.8
-5
-5
Typ.
1.66
0
90
0
0
1000
Max.
2.2
0.5
90.2
5
5
Unit
V
%
°
mV
mV
Hz
Note
*
* Amplitude = 1/2 of peak to peak value of the difference between the positive and negative signal. The distance to the magnet
and the temperature are within tolerances. To prevent saturation of the signals, the amplitude must never exceed 2.2 V.
AGC
Automatic gain control is enabled when the “AGCdis” parameter is set to 0. If the magnetic signal is changing
the AGC is able to control the output signal amplitude in range between 0.8V and 1V. When the amplitude is
less than 0.8 V, the gain is increased. When the amplitude is more than 1V, the gain is decreased. The AGC
gain has 16 levels and the range is from 0.5 to 2. Level 8 is at normal magnetic conditions.
Interpolator
When the magnet is rotated for 360° the sensors generates two perfect sinusoidal signals with phase
difference of 90°. The interpolator is using those sinusoidal signals to calculate the current angle position and
the angle position is output in various output formats. The calculation is performed is less than 1µs. The
interpolation rates is selectable from 64 to 4096.
© 2010 RLS
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Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Interpolation rates:
“Res” value
000
001
010
011
100
101
110
111
Interpolation rate
4096
2048
1024
512
256
128
64
32
Resolution
0.0879°
0.1758°
0.3516°
0.7031°
1.4062°
2.8125°
5.625°
11.25°
Max. input freq.
500 Hz
1000 Hz
1000 Hz
1000 Hz
1000 Hz
1000 Hz
1000 Hz
1000 Hz
Zeroing
The output angle position data can be zeroed at any angle with resolution of 0.0879°. The relative output
position is a difference between absolute position and data in zero register. The value in zero register can be
changed by writing a desired value with TWI interface or with using a “Zero” input pin. With low to high
transition of a signal on “Zero” pin the current absolute value is stored in zero register. When zeroing the
relative position the chip must not be in power-save mode as the EEPROM is not accessible.
Incremental output
There are three signals for the incremental output: A, B and Ri. Signals A and B are quadrature signals,
shifted by 90°, and signal Ri is a reference mark. The reference mark signal is produced once per revolution.
The width of the Ri pulse is 1/4 of the quadrature signal period and it is synchronized with the A and B
signals. The position of the reference mark is at zero.
Fig. 12 shows the timing diagram of A, B and Ri signals with CW rotation of the magnet and positive counting
direction. B leads A for CW rotation. The counting direction can be changed by programming the EEPROM
with the “Sign” parameter.
tTD
B
A
Ri
Pos.
CPR= Number of counts per revolution
Fig. 12: Timing diagram for incremental output
The transition distance (tTD) is the time between two output position changes. The transition distance time is
limited by the interpolator and the limitation is dependent on the output resolution. The counter must be able
to detect the minimum transition distance to avoid missing pulses.
© 2010 RLS
11/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Binary synchronous serial output SSI
Serial output data is available in up to 12 bit natural binary code through the SSI protocol. With positive
counting direction and the CW magnet rotation, the value of the output data increases.
Parameter
Clock period
Clock high
Clock low
Monoflop time
1
2
Symbol
tCL
tCHI
tCLO
tm
Min.
0.25
0.1
0.1
15
Typ.
19
Max.
2 x tm
tm
tm
25
Unit
µs
µs
µs
µs
tCL
tCLO
Note
3
tCHI
4
Clock
tm
Data
MSB
MSB-1 MSB-2
D4
D3
D2
D1
D0
Fig. 13: SSI timing diagram with monoflop timeout
The controller interrogates the AM4096 for its positional value by sending a pulse train to the Clock input. The
Clock signal must always start from high. The first high/low transition (point 1) stores the current position data
in a parallel/serial converter and the monoflop is triggered. With each transition of Clock signal (high/low or
low/high) the monoflop is retriggered. At the first low/high transition (point 2) the most significant bit (MSB) of
the binary code is transmitted through the Data pin to the controller. At each subsequent low/high transition of
the Clock the next bit is transmitted to the controller. While reading the data the tCHI and tCLO must be less
than tmMin to keep the monoflop set. After the least significant bit (LSB) is output (point 3) the Data goes to
low. The controller must wait longer than tmMax before it can read updated position data. At this point the
monoflop time expires and the Data output goes to high (point 4).
SSICfg
00
01
10
11
Descripion
no ring register operation
ring register operation data length according to the resolution, data is not refreshed
no ring register operation
ring register operation data length according to the resolution, data is refreshed
If the number of clocks is more than the data length than the behaviour of the SSI can be as defined with the
SSIcfg parameter. If the “SSIref” parameter is set to 00 then the data is output only once (Fig. 14).
Fig. 14: SSI single read, SSIref is set to 00
To enlarge the reliability of reading the controller can read the same data more than once. The “SSIref”
parameter must be set to “10” and the controller must continue sending the Clock pulses after the data is read
without waiting for Tm (Fig. 15). The same data will be output again and between the two outputs one logic
zero will be output. The length of the data is depended of the resolution settings.
© 2010 RLS
12/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Clock
Data
D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
Data
Data
Fig. 15: SSI multi-read of the same position data, “SSIref” is set to 10
To speed-up the position reading of AM4096 the controller can constantly read the data. The “SSIref”
parameter must be set to “11” and the controller must continue sending the Clock pulses after the data is read
without waiting for Tm (Fig. 16). Each data will be output as fresh position information and between the two
outputs one logic zero will be output. The length of the data is depended of the resolution settings.
Clock
Data
D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
Data
New data
Fig. 16: SSI fast position read, SSIref is set to 11
Two wire interface (TWI) output
The output data can be read with the TWI interface which is described in the beginning of the data sheet. The
available data are relative position, absolute position, magnet out of range and tacho output.
Data
Relative position
Absolute position
Magnet too far
Magnet too close
Tacho overflow
Tacho out
Symbol
Rpos
Apos
Weh
Wel
Thof
Tho
Adress
32
33
34
34
35
35
Position
<11:0>
<11:0>
<14>
<13>
<10>
<9:0>
Tacho output
The tacho output provides information of the current rotating speed. The rotating speed is calculated and
output on the “Vout/Tout” pin when the “Dact” parameter is set to 1. The speed information is also available in
the registers on address 35. The measuring range can be selected with the “Sth” parameter. The update time
depends on the “Sth” parameter and selected resolution (“Res”).
“Sth”
value
000
001
010
011
100
101
110
111
Measuring
range [Hz]
2048
1024
512
256
128
64
32
16
Measuring
range [rpm]
122880
61440
30720
15360
7680
3840
1920
960
Update time
[ms]
0.125*4096/Res
0.25*4096/Res
0.5*4096/Res
1*4096/Res
2*4096/Res
4*4096/Res
8*4096/Res
16*4096/Res
The “Vout/Tout” pin is an output from the 10 bit DA converter. The DA converter output voltage range is
defined by the voltages on the “RefN” and “RefP” pins. See the linear voltage output description for detailed
description of DA converter properties.
© 2010 RLS
13/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
UVW output
UVW outputs can be output as digital signals when the “BufSel” parameter is set to 0. The number of pole
pairs can be selected with “UVW” parameter. The number of signal periods (P) equals number of pole pairs.
The timing diagram shows the signals when the position data is increasing. The U signal always starts at zero
position regardless the signal period length. The resolution should be set to 4096 to ensure accurate
transitions of the signals.
U
V
W
P/3
P/3
P/3
P
Fig. 17: UVW timing diagram for CW magnet rotation
“Uvw”
value
000
001
010
011
100
101
110
111
Number of pole
pairs
1
2
3
4
5
6
7
8
Signal period
length [°]
360
180
120
90
72
60
51,4
45
Pin name
“U/NSin”
“V/PSin”
“W/NCos”
Pin function
U
V
W
Linear voltage output
The digital relative angular position information is converted into linear voltage with a 10 bit DA converter. The
linear output voltage is a sawtooth shape and lies within thresholds defined with the two external pins RefP
and RefN. The number of periods per revolution can be selected with the “Dac” parameter. The interpolator
resolution setting should be more than 10 bit.
5
5
RefP
t
u
Vo
2
0
90
180
Angle [°]
270
360
Fig. 18: One period per revolution (“Dac”= 0 0)
© 2010 RLS
t
2
1
RefN
0
3
Vo
u
3
1
RefP
4
Voltage [V]
Voltage [V]
4
0
RefN
0
90
180
Angle [°]
270
360
Fig. 19: Two periods per revolution (“Dac”= 0 1)
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Data sheet
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Issue 2, 10 March 2010
5
5
RefP
2
0
90
3
2
1
RefN
0
Vout
Voltage [V]
3
1
RefP
4
Vou
t
Voltage [V]
4
180
Angle [°]
270
RefN
0
360
Fig. 20: Four periods per revolution (“Dac”= 1 0)
0
90
180
Angle [°]
270
360
Fig. 21: Eight periods per revolution (“Dac”= 1 1)
Terminology:
RELATIVE ACCURACY: For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the
maximum deviation in LSBs, from a straight line passing through the actual endpoints of the DAC transfer
function.
OFFSET ERROR: This is a measure of the offset error of the DAC and the output ampli fier. It is the difference
between the output and the RefN voltage when the digital input value is 0. The units are in LSB.
GAIN ERROR: This is a measure of the span error of the DAC (including any error in the gain of the buffer
amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed in LSB.
1
Gain error
VrefP
Actual
Voltage output
DA output error [LSB]
0,5
0
-0,5
Ideal
Offset error
-1
0
256
512
768
1024
VrefN
Position code
Position code
0
Fig. 22: Typical relative accuracy plot of the DAC
1024
Fig. 23: Offset and Gain error of the DAC
DAC reference inputs characteristics:
Parameter
RefN internal pull down resistor
RefP internal pull up resistor
VRefN input range
VRefP input range
VRefN default value
VRefP default value
Min.
Typ.
4.4 kΩ
4.4 kΩ
Vss
Vext/2
Max.
Note
Vext/2
Vext
7.4 % (Vext)
92.7 % (Vext)
if RefN pin is not connected
if RefP pin is not connected
DAC voltage output characteristics:
Parameter
Minimum output voltage
Maximum output voltage
Output impedance
© 2010 RLS
Min.
Typ.
0V
Vext-10 mV
42 Ω
Max.
Note
Unloaded output
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Data sheet
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Issue 2, 10 March 2010
DAC characteristics:
Parameter
Min.
Typ.
Resolution
Relative accuracy
Offset error
Gain error
Max.
Units
bit
LSB
LSB
LSB
10
±2
10
5
Note
Hysteresis
Hysteresis is the difference of the output position at the same magnet position when rotating direction is
changed. Hysteresis can be separated into static and dynamic. Static hysteresis is independent of rotational
speed, whilst dynamic hysteresis is directly related. The AM4096 uses an electrical and digital hysteresis
(static) when converting analogue signals to digital. The hysteresis must always be larger than the peak noise
to assure a stable digital output. Electrical hysteresis is set to 0.17°. Digital hysteresis can be set with the
“Hist” parameter from 0 to 127 units. By default the digital hysteresis is set to 0. Each unit equals 360°/4096.
Dynamic hysteresis is caused by filter delay. Analogue signals are filtered with an RC filter (2kΩ, 10nF). The
delay of such filter is 20 µs.
Output
Hysteresis
3
2
1
Magnet
position
0
0
1
2
3
Fig. 24: Hysteresis
Parameter
Electrical hysteresis
Digital hysteresis
Symbol
Hyste
Hystd
Min.
0.14
0
Typ.
0.17
0
Max.
0.21
11.16
Unit
deg
deg
Note
*
* Measured at slow movement to avoid delay caused by filtering.
Nonlinearity
Nonlinearity is defined as the difference between the actual angular position of the magnet and the angular
position output from the AM4096. There are different types of nonlinearity.
Differential nonlinearity is the difference between the measured position step and the ideal position step.
The position step is the output position difference between any two neighbouring output positions, while the
ideal position step is 360° divided by the resolution. Differential nonlinearity is mainly caused by noise.
Differential nonlinearity is always less than one position step because there is a system that prevents missing
codes. Fig. 25 shows a typical differential nonlinearity plot of the AM4096 with 12 bit resolution, 10 nF filtering
and default parameters.
Integral nonlinearity is the total position error of the AM4096 output. Integral nonlinearity includes all position
errors but does not include the quantisation error. Integral nonlinearity is minimised during production to better
than ±0.2°. Fig. 26 shows a typical integral nonlinearity plot of the AM4096 with 12 bit resolution, a perfectly
aligned magnet, 10 nF filtering and default parameters. Integral nonlinearity can increase if the default
parameters are changed.
© 2010 RLS
16/25
0,1
0,5
0,08
0,4
0,06
0,3
Integral nonlinearity [°]
Differential nonlinearity [°]
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
0,04
0,02
0
-0,02
-0,04
0,2
0,1
0
-0,1
-0,2
-0,3
-0,06
-0,4
-0,08
-0,5
-0,1
0
0
45
90
135
180
225
270
315
45
90
135
180
225
270
315
360
Angle position [°]
360
Angle position [°]
Fig. 26: Typical integral nonlinearity at optimal
parameters
Fig. 25: Typical differential nonlinearity
Power save mode
The AM4096 can operate in power save mode to minimise current consumption when position data update
rate is not critical. Two types of power save mode are available, externally triggered and autonomous power
save mode. It is recommended that when power save mode is used, the internal voltage regulator is not used
and the voltage supply is 3.3 V.
Externally triggered power save mode can be done with “PSM” pin. While the “PSM” pin is high, the chip is
operating in stand-by mode with no current consumption. When the “PSM” pin is switched to low the chip
starts to operate normally and after 6ms the correct position data is available. When the position data is no
longer needed, the chip can be put to sleep again.
Autonomous power save mode can be activated with “Pdie” parameter. If ”Pdie” is set to 1 then the chip starts
to sleep with periodically 1ms wake-up time. The length of sleep time can be selected with “Pdtr” parameter.
“PSM” pin *
Low
High
Operation
AM4096 operates normally
AM4096 sleeps
Note
**
* PSM pin is the only digital input that does not have internally pull-down resistor and it must not be left open.
** No communication with the chip is available.
“Pdie” value
0
1
Operation
AM4096 operates normally
AM4096 cyclically awakes according to the “Pdtr” parameter
Note
*
* When autonomous power save mode is selected, the “PSM” pin should be low
“Pdtr” value
00
01
10
11
“Pdee” value
0
1
Active time
0.94
0.94
0.94
0.94
Inactive time
120
240
480
960
Available outputs
All outputs are available
Only SSI and TWI outputs are available
Units
ms
ms
ms
ms
Note
Note
*
**
* After PSM is switched from high to low it takes 6 ms before output information is usable.
** SSI and TWI data is available all the time. Position information is updated according to the “Pdtr” parameter.
© 2010 RLS
17/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Recommended magnet
The AM4096 can be supplied with a pre-selected magnet to ensure that optimum performance is achieved.
Alternatively, magnets can be sourced from other suppliers but they must conform to the following guidelines.
To select a suitable magnet it is important to know the properties of the sensors. Hall Sensors are only
sensitive to the perpendicular component of the magnetic flux density (B). The AM4096 has a Hall sensor
array arranged in a circle with 1 mm radius. The sensors are located on the surface of the silicon. The
nominal distance between the sensors and the magnet surface is 1.6 mm.
Magnets must be cylindrical in shape and diametrically polarized. The main criterion for magnet selection is
the modulation of the perpendicular component of magnetic flux density at the location of the sensors (Bn)
and a low offset of magnet modulation.
Fig. 27: Distribution of the perpendicular component of B
Fig. 28: Distribution of Bn and its modulation if the magnet is rotated through 360°
Parameter
Amplitude of Bn modulation
Offset of Bn modulation
Symbol
BnAmpl
BnOffset
Min.
Typ.
50
Max.
Unit
mT
mT
Note
*
**
* Typical value of BnAmpl will give an analogue signal output with amplitude of 0.68 V. The amplitude of the signal is proportional
to the BnAmpl. 1 Tesla equals 10,000 Gauss.
** Bad quality magnets offset the Bn modulation which results in increased integral nonlinearity when the magnet is not aligned
correctly with respect to the chip.
-1
1
We recommend that a magnet with the following parameters is used to provide the necessary modulation:
Parameter
Diameter
Length
Material
Material remanence
Temperature coefficient
Curie temperature
Typ.
4
4
Sm2Co17
1.05
-0.03
720
Unit
mm
mm
Note
*
T
% / °C
°C
* Rare earth material magnets SmCo are recommended; however, NdFeB magnets can be used but they have different
characteristics.
© 2010 RLS
18/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Magnet quality and the nonlinearity error
Each AM4096 is optimized during the production to give best performance with an ideal magnet when
perfectly aligned.
An ideal magnet would have the polarization border exactly in the middle of the magnet. If the polarization is
not exactly in the middle of the magnet then the modulation of the magnetic field has an offset.
N
S
N
S
Fig. 29: Ideally polarized magnet and not ideally polarized magnet
The offset represents a mean value of Bn when the magnet is rotated trough 360° and Bn is measured at
1.6mm distance from the magnet surface and at 1 mm radius.
Offset will cause larger than normal integral nonlinearity errors if the sensors center placement is not in the
center of the magnet rotation. Fig. 30 shows an additional integral nonlinearity error caused by misalignment
of the AM4096 for ideal and recommended magnets. Total integral nonlinearity is the summation of integral
nonlinearity and the additional integral nonlinearity error caused by magnet displacement.
Additional integral nonlinearity [°]
2,5
2
Recommended
magnet
1,5
1
Ideal magnet
0,5
0
-0,5
-0,25
0
0,25
0,5
Radial displacement [mm]
Fig. 30: Additional integral nonlinearity error caused by magnet displacement
It is important that magnetic materials are not close to the magnet because they can increase the integral
nonlinearity. They should ideally be at least 3 centimetres away from the chip. The magnet should be
mounted in a non-magnetic carrier.
© 2010 RLS
19/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Magnet position
Magnet must be positioned above the AM4096 in the centre of hall sensor array. The centre of the sensor
array is not in the centre of the AM4096.
Magnet
N
S
Silicon
surface
h
a
z
b
PCB
Fig. 31: AM4096 and the magnet with dimensions
Parameter
Distance sensors – chip surface
Distance PCB plane– chip surface
Distance chip surface – magnet
Distance PCB plane – magnet
Symbol
a
b
h
z
Min.
Typ.
0.75
1.86
1.00
2.86
0.50
2.36
Max.
1.50
3.36
Unit
mm
mm
mm
mm
Note
*
*
* For typical 40 µm copper thickness of PCB
Mounting instructions
*
0.15
0.2
Recommended
magnet
S
2.86 ±0.5
N
0.56 ±0.2
II*
II*
Fig. 32: Mounting instructions
© 2010 RLS
20/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
13
100n
2.2µ
100n
2.2µ
100n
2.2µ
Vdd
23
24
19
RefP
18
RefN
22
Zero
21
PSM
Vdd
47k
47k
Vdd
Application scheme
SDA
SCL
1
28
Vext
Data
Clock
4
3
2
AM4096
14 Vdda
A
B
Ri
7
6
5
U
V
W
20
12 Vddd
Sin
11
Agnd
16
100n
10n
Cos
10
Vout
Vss
15
10n
23
24
21 PSM
AM4096
Vdd= 3.3V
100n
13
10µ
14
12
1
28
Vdd
47k
47k
Vdd
Fig. 33: Typical application scheme
SDA
SCL
Data
Clock
Vext
Vdda
Vddd
Agnd Sin
16
100n
11
10n
Cos
10
10n
Vss
15
Fig. 34: Application scheme for autonomous power save mode
© 2010 RLS
21/25
Data sheet
AM4096D02_02
th
Issue 2, 10 March 2010
Ordering information
1. Angular Magnetic encoder IC
Part number
AM4096PT
Description
AM4096 Angular Magnetic Encoder IC with default functionality
Output options:
- SSI
- Incremental
- Linear voltage
- UVW
- TWI
Programmable:
- Differential buffered Sine/Cosine
- Tacho
SSOP28 plastic package
Delivered in tubes (48 units per tube)
NOTE: Order quantity must be a multiple of 48 (one tube).
Can be delivered in reels (special order)
Magnet must be ordered separately! The Angular Magnetic Encoder IC part number does not include a magnet.
2. Magnet
Part Number
Description
RMM44A3C00
Diametrically polarized magnet
Dimensions: ∅ 4 mm x 4 mm
3. Sample Kits
Part Number
Description
RMK4
AM4096 Angular Magnetic Encoder IC, on a PCB with all necessary
components and a magnet, delivered in an antistatic box
Output options: SSI, Incremental, Linear voltage, UVW, TWI
Programmable: Differential buffered Sine/Cosine, Tacho
4. Interfaces
Part Number
UPRGAM4096
Description
The UPRGAM4096 is a programming interface for use with
AM4096 rotary magnetic encoder chip and RMK4 evaluation
board. It connects simply to a computer via a USB port.
The package includes USB 2.0 A-B mini cable and a ribbon cable
with the appropriate connector for the RMK4 board
© 2010 RLS
22/25
Data sheet
AM4096D02_02
th
Issue 2, 10 March 2010
RMK4 sample kit
AM4096 on a PCB with all necessary components and a magnet, delivered in an antistatic box. RMK4 has all
outputs available, by default it is configured for 5 V supply voltage and with 12 bit resolution.
Fig. 35: RMK4 installation drawing
Fig. 36: RMK4 with schematic
Jumper configuration:
J1, J2: Bridges for voltage regulators, opened
by default.
J3:
© 2010 RLS
PSM connection to Vss. To use PSM
pin function, J3 must be opened. J3 is
closed by default.
23/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
Head office
RLS merilna tehnika d.o.o.
Poslovna cona Žeje pri Komendi
Pod vrbami 2
SI-1218 Komenda
T +386 1 5272100
F +386 1 5272129
E mail@rls.si
www.rls.si
Document issues
Document
issues
1
2
Date
Changes
19. 11. 2009
10. 3. 2010
New document
Page 12: SSI data added
Page 22: UPRGAM4096 ordering information added
Page 23: New RMK4 image
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24/25
Data sheet
AM4096D02_02
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Issue 2, 10 March 2010
RLS merilna tehnika d.o.o. has made considerable effort to ensure the content of this document is correct at the date of
publication but makes no warranties or representations regarding the content. RLS merilna tehnika d.o.o. excludes liability,
howsoever arising, for any inaccuracies in this document.
© 2010 RLS
25/25
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