CS47L15 - Cirrus Logic

CS47L15 - Cirrus Logic
CS47L15
Smart Codec with Low-Power Audio DSP
• Earpiece, speaker, and digital (pulse-density modulation,
PDM) output interfaces
Features
• 150 MIPS, 150 MMAC audio-signal processor
— Two-way stereo PDM interface
— Low-power, always-on voice trigger capability
• Three full digital-audio interfaces
— Speaker protection algorithm support
— Standard sample rates from 8 to 192 kHz
— Event loggers with time-stamp and interrupt functions
— Multichannel support on AIF1 and AIF2
• Programmable wideband audio processing
• Self-boot capability from external non-volatile memory
— Transmit-path noise reduction and echo cancelation
• Flexible clocking, derived from MCLKn or AIFn
• Integrated multichannel 24-bit hi-fi audio hub codec
— 98-dB signal-to-noise ratio (SNR) mic input (48 kHz)
• Low-power frequency-locked loops (FLLs) support
reference clocks down to 32 kHz
— 127-dB SNR headphone playback (48 kHz)
• Advanced accessory detection functions
— Low-power analog input modes
• Configurable functions on up to 15 general-purpose
input/output (GPIO) pins
• Up to four analog or four digital microphone (DMIC) inputs
— Speaker-monitoring input path (analog or digital)
• Stereo headphone/earpiece/line output driver: 30 mW
into 32- load at 0.1% total harmonic distortion + noise
(THD+N)
• Small WLCSP package, 0.4-mm ball array
Applications
• Smartphones, tablets, and wearable technology
IN1BLN
IN1BLP
IN1ALN/DMICCLK
IN1ALP/DMICDAT
IN1BRN
IN1BRP
IN1ARN
IN1ARP
IN2N
IN2P
SPKRXDAT
Input
Select
AIFnBCLK
AIFnLRCLK
MICDET2/
HPOUTFB2
MICDET1/
HPOUTFB1
JACKDET2
JACKDET1
HPOUTR
Five-band equal izer (EQ)
Dynamic range control (DRC)
Low-pass/high-pass filter (LHPF)
Automatic sample -rate detection
DAC
EPOUTP
EPOUTN
SYSCLK
2 x FLL
AIF1TXDAT
AIF1RXDAT
AIF1BCLK
AIF1LRCLK
Digital Audio
Interface AIF1
Preliminary Product Information
Digital Audio
Interface AIF2
Digital Audio
Interface AIF3
SPKOUTP
SPKOUTN
PDM
Driver
AEC (Echo Cancelation)
Loop-Back
DSPCLK
IRQ
http://www.cirrus.com
SUBGND
DAC
Tone generator
Noise generator
PWM signal generator
Haptic control signal generator
Digital PDM
Interface
Clocking
Control
SPKVDD
SPKGNDP
SPKGNDN
Programmable DSP
Always-on signal processing
TX noise reduction
Acoustic-echo cancelation
Speaker protection
Digital Mic
Interface
ADC
Input
Select
DCVDD
DBVDD
DGND
CPVDD
CPGND
CPC2B
CPVOUT2P
CPVOUT1N
CPC2A
CP1OUT1P
CPVOUT2N
HPOUTL
Digital Core
ADC
MCLK1
MCLK2
RESET
DAC
ADC
General
Purpose
Switch
SPKCLK
SPKTXDAT
GPSWP
GPSWN
Control Interfaces (SPI, I2C)
Master Interface (SPI)
MSTRBOOT
Reference
Generator
External Accessory
Detect
CS47L15
SPIMISO/SCLK
SPIMOSI/SDA
SPISCLK
SPISS
AVDD
AGND
VREFC
Charge Pump
AIF3TXDAT
AIF3RXDAT
AIF3BCLK
AIF3LRCLK
MICBIAS
Generator
AIF2TXDAT
AIF2RXDAT
AIF2BCLK
AIF2LRCLK
MICBIAS1A
MICBIAS1B
MICBIAS1C
CPC1A
CP11B
MICVDD
— Karaoke algorithm support
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product.
Copyright  Cirrus Logic, Inc. 2016
(All Rights Reserved)
DS1137PP1
NOV '16
CS47L15
Description
The CS47L15 is a highly integrated, low-power audio hub for smartphones, tablets, and other portable audio devices
including wearable technology. It combines an advanced DSP feature set with a flexible, high-performance audio hub
codec. The CS47L15 combines a programmable DSP core with a variety of power-efficient fixed-function audio
processors. An SPI master interface is provided, for autonomous boot-up and configuration using an external non-volatile
memory—enabling the CS47L15 to be used independently of a host processor.
The DSP core supports advanced audio processing functions such as wideband noise reduction, acoustic-echo
cancelation (AEC), speech enhancement, karaoke, and many more. Low-power analog and digital interfaces provide
flexible support for always-on voice applications and speaker-protection algorithms implemented on the programmable
DSP core. The DSP core is integrated within a fully flexible, all-digital mixing and routing engine with sample-rate
converters, for wide use-case flexibility. Support for third-party DSP programming provides far-reaching opportunities for
product differentiation.
Three digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial
interface formats. Automatic sample-rate detection enables seamless wideband/narrowband voice-call handover. The
DACs and output paths provide full support for high definition audio throughout the entire signal chain.
The stereo headphone driver provides ground-referenced output, with noise levels as low as 0.45 VRMS for hi-fi quality
line or headphone output. The CS47L15 also features a mono bridge-tied load (BTL) earpiece output, mono 2.5-W Class D
speaker driver, two channels of stereo PDM output, and an IEC-60958-3–compatible S/PDIF transmitter. A signal
generator for controlling haptics devices is included; vibe actuators can connect directly to the Class D speaker output, or
via an external driver on the PDM output interface.
The CS47L15 supports up to five analog inputs, and up to four PDM digital inputs. As many as four analog microphone
connections can be supported; a separate analog input channel is provided for use in speaker-protection applications.
Microphone activity detection with interrupt is available. A smart accessory interface supports most standard 3.5-mm
accessories. Impedance sensing and measurement is provided for external accessory and push-button detection
(Android™ headset specification compliant).
The CS47L15 supports SPI™ and I2C interface modes for control-register access. The CS47L15 can also be configured
as SPI master, enabling autonomous boot-up and configuration without dependency on a host processor. Two integrated
FLLs support a wide range of system-clock frequencies. The device is powered from 1.8- and 1.2-V supplies. Separate
MICVDD input can be supported, for microphone operation above 1.8 V. An additional supply is required for the Class D
speaker drivers (typically direct connection to 4.2-V battery). The power, clocking, and output driver architectures are
designed to maximize battery life in voice, music, and standby modes. Low-power (25 W) Sleep Mode is supported, with
configurable wake-up events.
2
DS1137PP1
CS47L15
Table of Contents
1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 WLCSP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-1. Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . 10
Table 3-4. Analog Input Signal Level—IN1Axx, IN1Bxx, IN2x . . . . . . . 10
Table 3-5. Analog Input Pin Characteristics . . . . . . . . . . . . . . . . . . . . . 10
Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs) 10
Table 3-7. Digital Input Signal Level—DMICDAT, SPKRXDAT . . . . . . 11
Table 3-8. Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3-9. Input/Output Path Characteristics . . . . . . . . . . . . . . . . . . . . 11
Table 3-10. Digital Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3-11. Miscellaneous Characteristics . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-12. Device Reset Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3-13. System Clock and Frequency-Locked Loop (FLL) . . . . . . 17
Table 3-14. Digital Microphone (DMIC) Interface Timing . . . . . . . . . . . 18
Table 3-15. Digital Speaker (PDM) Interface Timing . . . . . . . . . . . . . . 18
Table 3-16. Digital Audio Interface—Master Mode . . . . . . . . . . . . . . . . 19
Table 3-17. Digital Audio Interface—Slave Mode . . . . . . . . . . . . . . . . . 20
Table 3-18. Digital Audio Interface Timing—TDM Mode . . . . . . . . . . . 20
Table 3-19. Control Interface Timing—Two-Wire (I2C) Mode . . . . . . . . 21
Table 3-20. Control Interface Timing—Four-Wire (SPI) Mode . . . . . . . 22
Table 3-21. Master Interface Timing—SPI Master . . . . . . . . . . . . . . . . 23
Table 3-22. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3-23. Typical Power Consumption . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3-24. Typical Signal Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Input Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Digital Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 DSP Firmware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5 DSP Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.6 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.7 Digital Audio Interface Control . . . . . . . . . . . . . . . . . . . . . . 111
4.8 Output Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.9 External Accessory Detection . . . . . . . . . . . . . . . . . . . . . . 133
4.10 Low Power Sleep Configuration . . . . . . . . . . . . . . . . . . . . 149
4.11 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.13 Clocking and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 173
4.14 Control Interface and Master-Boot Interface . . . . . . . . . . 195
4.15 Control-Write Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . 202
4.16 Charge Pumps, Regulators, and Voltage Reference . . . . 210
4.17 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
4.18 Thermal, Short-Circuit, and Timer-Controlled Protection . 214
4.19 Power-Up, Resets, and Device ID . . . . . . . . . . . . . . . . . . 215
5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.1 Recommended External Components . . . . . . . . . . . . . . . . 218
5.2 Resets Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
5.3 Output-Signal Drive-Strength Control . . . . . . . . . . . . . . . . . 228
5.4 Digital Audio Interface Clocking Configurations . . . . . . . . . 229
5.5 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . 233
6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
8 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
DS1137PP1
CS47L15
1 Pin Descriptions
1 Pin Descriptions
1.1 WLCSP Pinout
A1
A3
A5
A9
A11
A13
A15
A4
A6
A8
A10
A12
A14
JACKDET2
JACKDET1
EPOUTN
EPOUTP
HPOUTR
HPOUTL
CPVOUT2N
B2
B4
B6
B8
B10
B12
B14
B1
B3
B5
B7
B9
B11
B13
MICDET2/
HPOUTFB2
MICDET1/
HPOUTFB1
MICBIAS1C
GPSWN
GPSWP
CPVOUT2P
CPC2B
C1
C3
C5
C7
C9
C11
C13
C15
C2
C4
C6
C8
C10
C12
C14
MICVDD
SUBGND
MICBIAS1B
MICBIAS1A
CPC2A
CPGND
CPVDD
D2
D4
D6
D8
D10
D12
D14
D1
D3
D5
D7
D9
D11
D13
AVDD
AGND
VREFC
IN1ALP/
DMICDAT
SPKRXDAT/
GPIO15
CPC1A
CPVOUT1P
E1
E3
E5
E7
E9
E11
E13
E15
E2
E4
E6
E8
E10
E12
E14
IN1ARN
IN1BLN
IN1ARP
IN1ALN/
DMICCLK
AIF1TXDAT/
GPIO1
CPVOUT1N
CPC1B
F2
F4
F6
F8
F10
F12
F14
F1
F3
F5
F7
F9
F11
F13
IN1BRN
IN1BRP
IN1BLP
AIF1BCLK/
GPIO3
AIF2RXDAT/
GPIO6
AIF1LRCLK/
GPIO4
AIF1RXDAT/
GPIO2
G1
G3
G5
G7
G9
G11
G13
G15
G2
G4
G6
G8
G10
G12
G14
IN2P
IN2N
AIF2LRCLK/
GPIO8
AIF3LRCLK/
GPIO12
AIF3RXDAT/
GPIO10
AIF2BCLK/
GPIO7
AIF2TXDAT/
GPIO5
H2
I1
A7
A2
H4
H6
H8
H10
H12
H14
H1
H3
H5
H7
H9
H11
H13
SPKGNDP
RESET
MSTRBOOT
SPISCLK
SPIMISO/
SCLK
SPIMOSI/SDA
AIF3TXDAT/
GPIO9
J1
J3
J5
J7
J9
J11
J13
J15
J2
J4
J6
J8
J10
J12
J14
SPKOUTP
SPKVDD
SPKTXDAT/
GPIO13
DGND
SPKCLK/
GPIO14
MCLK1
AIF3BCLK/
GPIO11
K2
K4
K6
K8
K10
K12
K14
K1
K3
K5
K7
K9
K11
K13
SPKGNDN
SPKOUTN
IRQ
SPISS
DCVDD
DBVDD
MCLK2
Analog I/O
Digital I/O
Power
Figure 1-1. Top-Down (Through-Package) View—70-Ball WLCSP Package
4
DS1137PP1
CS47L15
1.2 Pin Descriptions
1.2 Pin Descriptions
Table 1-1 describes each pin on the CS47L15. All digital output pins are CMOS outputs, unless otherwise stated.
Table 1-1. Pin Descriptions
PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain.
Pin Name
Pin #
Power
Supply
I/O
Pin Description
Digital Pad
State at Reset 1
Attributes
Analog I/O
CPC1A
D11
—
O
Charge pump fly-back capacitor 1 pin
—
—
CPC1B
E14
—
O
Charge pump fly-back capacitor 1 pin
—
—
CPC2A
C10
—
O
Charge pump fly-back capacitor 2 pin
—
—
CPC2B
B13
—
O
Charge pump fly-back capacitor 2 pin
—
—
CPVOUT1N
E12
—
O
Charge pump negative output 1 decoupling pin
—
Output
CPVOUT1P
D13
—
O
Charge pump positive output 1 decoupling pin
—
Output
CPVOUT2N
A14
—
O
Charge pump negative output 2 decoupling pin
—
Output
CPVOUT2P
B11
—
O
Charge pump positive output 2 decoupling pin
—
Output
EPOUTN
A6
—
O
Earpiece negative output
—
Output
EPOUTP
A8
—
O
Earpiece positive output
—
Output
GPSWN
B7
—
I/O
General-purpose bidirectional switch contact
—
—
GPSWP
B9
—
I/O
General-purpose bidirectional switch contact
—
—
HPOUTL
A12
—
O
Left headphone output
—
Output
HPOUTR
A10
—
O
Right headphone output
—
Output
IN1ALN/
DMICCLK
E8
MICVDD or
MICBIASnx [2]
I/O
Left-channel negative differential mic/line input /DMIC
clock output
PD/H
IN1ALN input
IN1ALP/
DMICDAT
D7
MICVDD or
MICBIASnx [2]
I
Left-channel single-ended mic/line input/left-channel
positive differential mic/line input/DMIC data input
PD/H
IN1ALP input
IN1ARN
E2
MICVDD
I
Right-channel negative differential mic/line input
—
Input
IN1ARP
E6
MICVDD
I
Right-channel single-ended mic/line input/
right-channel positive differential mic/line input
—
Input
IN1BLN
E4
MICVDD
I
Left-channel negative differential mic/line input. Also
suitable for connection to external accessory
interfaces.
—
Input
IN1BLP
F5
MICVDD
I
Left-channel single-ended mic/line input/left-channel
positive differential mic/line input. Also suitable for
connection to external accessory interfaces.
—
Input
IN1BRN
F1
MICVDD
I
Right-channel negative differential mic/line input. Also
suitable for connection to external accessory
interfaces.
—
Input
IN1BRP
F3
MICVDD
I
Right-channel single-ended mic/line input/
right-channel positive differential mic/line input. Also
suitable for connection to external accessory
interfaces.
—
Input
IN2N
G4
MICVDD
I
Negative differential analog input
—
Input
IN2P
G2
MICVDD
I
Positive differential analog input
—
Input
JACKDET1
A4
AVDD
I
Jack detect input 1
—
Input
JACKDET2
A2
AVDD
I
Jack detect input 2
—
Input
MICBIAS1A
C8
—
O
Microphone bias 1A
—
Output
MICBIAS1B
C6
—
O
Microphone bias 1B
—
Output
MICBIAS1C
B5
—
O
Microphone bias 1C
—
Output
MICDET1/
HPOUTFB1
B3
—
I
Microphone and accessory sense input 1/HPOUTL
and HPOUTR ground feedback pin 1
—
Input
MICDET2/
HPOUTFB2
B1
—
I
Microphone and accessory sense input 2/HPOUTL
and HPOUTR ground feedback pin 2
—
Input
5
DS1137PP1
CS47L15
1.2 Pin Descriptions
Table 1-1. Pin Descriptions (Cont.)
PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain.
Pin #
Power
Supply
I/O
K3
—
O
Speaker negative output
SPKOUTP
J2
—
O
Speaker positive output
—
Output
VREFC
D5
—
O
Band-gap reference external capacitor connection
—
Output
AIF1BCLK/
GPIO3
F7
DBVDD
I/O
Audio interface 1 bit clock/GPIO
PU/PD/K/H/ GPIO3 input with
Z/C/OD
bus-keeper
AIF1LRCLK/
GPIO4
F11
DBVDD
I/O
Audio interface 1 left/right clock/GPIO
PU/PD/K/H/ GPIO4 input with
Z/C/OD
bus-keeper
AIF1RXDAT/
GPIO2
F13
DBVDD
I/O
Audio interface 1 RX digital audio data/GPIO
PU/PD/K/H/ GPIO2 input with
C/OD
bus-keeper
AIF1TXDAT/
GPIO1
E10
DBVDD
I/O
Audio interface 1 TX digital audio data/GPIO
PU/PD/K/H/ GPIO1 input with
Z/C/OD
bus-keeper
AIF2BCLK/
GPIO7
G12
DBVDD
I/O
Audio interface 2 bit clock/GPIO
PU/PD/K/H/ GPIO7 input with
Z/C/OD
bus-keeper
AIF2LRCLK/
GPIO8
G6
DBVDD
I/O
Audio interface 2 left/right clock/GPIO
PU/PD/K/H/ GPIO8 input with
Z/C/OD
bus-keeper
AIF2RXDAT/
GPIO6
F9
DBVDD
I/O
Audio interface 2 RX digital audio data/GPIO
PU/PD/K/H/ GPIO6 input with
C/OD
bus-keeper
AIF2TXDAT/
GPIO5
G14
DBVDD
I/O
Audio interface 2 TX digital audio data/GPIO. If the
JTAG interface is configured, this pin provides the TDI
input connection.
PU/PD/K/H/ GPIO5 input with
Z/C/OD
bus-keeper
AIF3BCLK/
GPIO11
J14
DBVDD
I/O
Audio interface 3 bit clock/GPIO. If the JTAG interface
is configured, this pin provides the TCK input
connection.
PU/PD/K/H/
Z/C/OD
GPIO11 input
with bus-keeper
AIF3LRCLK/
GPIO12
G8
DBVDD
I/O
Audio interface 3 left/right clock/GPIO. If the JTAG
interface is configured, this pin provides the TDO
output connection.
PU/PD/K/H/
Z/C/OD
GPIO12 input
with bus-keeper
AIF3RXDAT/
GPIO10
G10
DBVDD
I/O
Audio interface 3 RX digital audio data/GPIO. If the
JTAG interface is configured, this pin provides the
TMS input connection.
PU/PD/K/H/
C/OD
GPIO10 input
with bus-keeper
AIF3TXDAT/
GPIO9
H13
DBVDD
I/O
Audio interface 3 TX digital audio data/GPIO. If the
JTAG interface is configured, this pin provides the
TRST input connection.
PU/PD/K/H/ GPIO9 input with
Z/C/OD
bus-keeper
K5
DBVDD
O
Interrupt request output (default is active low). The pin
configuration is selectable CMOS or open drain.
Pin Name
SPKOUTN
Pin Description
Digital Pad
State at Reset 1
Attributes
—
Output
Digital I/O
IRQ
C/OD
Output
MCLK1
J12
DBVDD
I
Master clock 1
H
Input
MCLK2
K13
DBVDD
I
Master clock 2
H
Input
MSTRBOOT
H5
DBVDD
I
Master boot mode select
PD/H
Input
RESET
H3
DBVDD
I
Digital reset input (active low)
SPIMISO/
SCLK
H9
DBVDD
I/O
Control interface (SPI) Master In Slave Out data/I2C
clock input. SPIMISO is high impedance if SPISS is
not asserted.
PD/H/C
Input
SPIMOSI/SDA
H11
DBVDD
I/O
Control interface (SPI) Master Out Slave In data/I2C
data input and output.
H/C/OD
Input
SPISCLK
H7
DBVDD
I/O
Control interface (SPI) clock
H/C
Input
SPISS
K7
DBVDD
I/O
Control interface (SPI) slave select (SS)
H/C
Input
output/GPIO/I2C
PU/PD/K/H Input with pull-up
SPKCLK/
GPIO14
J10
DBVDD
I/O
Digital speaker (PDM) clock
clock
input. GPIO output is selectable CMOS or open drain;
SPKCLK output is CMOS.
PU/PD/K/H/
C/OD
GPIO14 input
with bus-keeper
SPKRXDAT/
GPIO15
D9
DBVDD
I/O
Digital speaker (PDM) data input/GPIO/I2C data input
and output. GPIO output is selectable CMOS or open
drain.
PU/PD/K/H/
C/OD
GPIO15 input
with bus-keeper
6
DS1137PP1
CS47L15
1.2 Pin Descriptions
Table 1-1. Pin Descriptions (Cont.)
PU = Pull-up, PD = Pull-down, K = Bus keeper, H = Hysteresis on CMOS input, Z = Hi-Z (High impedance), C = CMOS, OD = Open drain.
Pin Name
SPKTXDAT/
GPIO13
Pin #
Power
Supply
I/O
Pin Description
Digital Pad
State at Reset 1
Attributes
J6
DBVDD
I/O
Digital speaker (PDM) data output/GPIO. GPIO
output is selectable CMOS or open drain; SPKTXDAT
output is CMOS.
PU/PD/K/H/
C/OD
GPIO13 input
with bus-keeper
Supply
AGND
D3
—
—
Analog ground (return path for AVDD and MICVDD)
—
—
AVDD
D1
—
—
Analog supply
—
—
CPGND
C12
—
—
Charge pump ground (return path for CPVDD)
—
—
CPVDD
C14
—
—
Supply for charge pump
—
—
DBVDD
K11
—
—
Digital buffer (I/O) supply
—
—
DCVDD
K9
—
—
Digital core supply
—
—
DGND
J8
—
—
Digital ground (return path for DCVDD and DBVDD)
—
—
MICVDD
C2
—
—
Microphone bias supply (input to MICBIAS regulator)
—
—
3
SPKGNDN
K1
—
—
Speaker driver ground (return path for SPKVDD)
—
—
SPKGNDP
H1
—
—
Speaker driver ground (return path for SPKVDD) 3
—
—
SPKVDD
J4
—
—
Speaker driver supply
—
—
SUBGND
C4
—
—
Substrate ground
—
—
1.Note that the default conditions described are not valid if modified by the boot sequence or by a wake-up control sequence.
2.The analog input functions on these pins are referenced to the MICVDD power domain. The digital input/output functions are referenced to the
MICVDD or MICBIAS1 power domain, as selected by the IN1_DMIC_SUP field.
3. Separate P/N ground connections are provided for the Class D speaker output, which provides flexible support for current monitoring and
output-protection circuits. If this option is not used, these ground connections should be tied together on the PCB.
7
DS1137PP1
CS47L15
2 Typical Connection Diagram
2 Typical Connection Diagram
AGND
CPGND
DGND
SUBGND
1.2 V
DCVDD
4.2 V
2.2 F
VREFC
SPISS
1.8 V
SPISCLK
Control Interface/
Master SPI Interface
SPIMOSI/SDA
2.2 F
SPIMISO/SCLK
SPKVDD
Master Boot Select
MSTRBOOT
CPVDD
AVDD
DBVDD
MICVDD
MCLK1
MCLK2
Master Clocks
4.7F
Reset Control
RESET
4.7 F
1.0 F
0.1 F
CS47L15
1.0 F
IRQ
GPSWP
AIF1LRCLK
CPC1A
AIF1RXDAT
2.2 F
CPVOUT1N
CPC2A
AIF2RXDAT
CPC2B
AIF2TXDAT
CPVOUT2P
AIF3BCLK
CPVOUT2N
AIF3LRCLK
2.2 F
4.7 F
4.7 F
AIF3RXDAT
AIF3TXDAT
JACKDET1
Jack Detect Inputs
JACKDET2
MICBIAS1A
VDD
CHAN
GND
Stereo Digital
Microphone
Connection
2.2 F
CPVOUT1P
AIF2LRCLK
Audio Interface 3
1.0 F
CPC1B
AIF1TXDAT
AIF2BCLK
Audio Interface 2
The CS47L15 supports up to 15 GPIO pins.
These are shared with the primary functions shown.
GPSWN
AIF1BCLK
Audio Interface 1
Interrupt Output
VDD
CHAN
GND
HPOUTL
DMIC
DMIC
DAT
CLK
Headphone
HPOUTR
MICDET1/HPOUTFB1
(Note: HPOUTFB ground
connection close to headset jack )
IN1ALP/DMICDAT
DAT
CLK
IN1ALN/DMICCLK
IN1ARP
IN1ARN
EPOUTN
EPOUTP
Earpiece
Speaker
MICBIAS1B
MICDET2/HPOUTFB2
2.2 k
1 F
Pseudodifferential
Microphone
Connection
1 F
IN1BLP
SPKOUTN
SPKOUTP
IN1BLN
SPKGNDN
IN1BRP
IN1BRN
SPKGNDP
MICDET1/HPOUTFB1
IN2N
0.1
(1%, 100ppm/°C)
IN2P
(Note: Speaker-monitoring connections and
components are shown. If these connections are not
used, the SPKGNDx pins connect directly to GND)
Analog and Digital Inputs
Bias/Supplies for
Microphones and External
Accessory Detection
Loudspeaker
MICBIAS1A
SPKCLK
MICBIAS1B
SPKTXDAT
MICBIAS1C
SPKRXDAT
Digital Speaker
(PDM) Interface
Figure 2-1. Typical Connection Diagram
8
DS1137PP1
CS47L15
3 Characteristics and Specifications
3 Characteristics and Specifications
Table 3-1 defines parameters as they are characterized in this section.
Table 3-1. Parameter Definitions
Parameter
Channel separation
Common-mode rejection
ratio (CMRR)
Dynamic range (DR)
Power-supply rejection
ratio (PSRR)
Signal-to-noise ratio
(SNR)
Total harmonic distortion
(THD)
Total harmonic distortion
plus noise (THD+N)
Definition
Left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to
maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active
channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured
at the output of the associated idle channel.
The ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that
results from it.
A measure of the difference between the maximum full scale output signal and the sum of all harmonic distortion
products plus noise, with a low-level input signal applied. Typically, an input signal level 60 dB below full scale is
used.
The ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured
under quiescent signal path conditions.
A measure of the difference in level between the maximum full scale output signal and the output with no input signal
applied.
The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth 1 relative to the RMS
amplitude of the fundamental (i.e., test frequency) output.
The ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth 1 relative to the
RMS amplitude of the fundamental (i.e., test frequency) output.
1.All performance measurements are specified with a 20-kHz low-pass brick-wall filter and, where noted, an A-weighted filter. The low-pass filter
removes out-of-band noise.
Table 3-2. Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.
Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified.
Parameter
Symbol
Minimum
Maximum
DCVDD
–0.3 V
1.6 V
CPVDD
–0.3 V
2.5 V
DBVDD, AVDD, MICVDD
–0.3 V
5.0 V
SPKVDD
–0.3 V
6.0 V
Voltage range digital inputs
—
SUBGND – 0.3 V
DBVDD + 0.3 V
SUBGND – 0.3 V
MICVDD + 0.3 V
Voltage range analog inputs
IN1Axx, IN2xx
SUBGND – 0.9 V
MICVDD + 0.3 V
IN1Bxx
SUBGND – 0.3 V
SUBGND + 0.3 V
HPOUTFBn 1
MICDETn 1
SUBGND – 0.3 V
MICVDD + 0.3 V
JACKDET1
CPVOUT2N – 0.3 V [3]
AVDD + 0.3 V
SUBGND – 0.3 V
JACKDET2 [2], GPSWP, GPSWN
MICVDD + 0.3 V
Ground
AGND, DGND, CPGND,
SUBGND – 0.3 V
SUBGND + 0.3 V
SPKGNDN, SPKGNDP
–40ºC
+85ºC
Operating temperature range
TA
Operating junction temperature
TJ
–40ºC
+125ºC
Storage temperature after soldering
—
–65ºC
+150ºC
ESD-sensitive device. The CS47L15 is manufactured on a CMOS process. It is therefore generically susceptible to damage from
excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is qualified
to current JEDEC ESD standards.
Supply voltages
1.The HPOUTFBn and MICDETn functions share common pins. The absolute maximum rating varies according to the applicable function of each pin.
2.If AVDD > MICVDD the maximum JACKDET2 voltage is AVDD + 0.3 V.
3.CPVOUT2N is an internal supply, generated by the CS47L15 charge pump (CP). Its voltage can vary between CPGND and –CPVDD.
9
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-3. Recommended Operating Conditions
Parameter
Digital supply range 1,2
Charge pump supply range
Speaker supply range
Analog supply range
Mic bias supply
Ground 4
Core and FLL
I/O
CPVDD
Power supply rise time 5,6
Operating temperature range
Symbol
DCVDD [3]
DBVDD
CPVDD
SPKVDD
AVDD
MICVDD
DGND, AGND, CPGND, SPKGNDN,
SPKGNDP, SUBGND
DCVDD
All other supplies
TA
Minimum
1.14
1.71
1.71
2.4
1.71
1.71
—
Typical
1.2
—
1.8
—
1.8
1.8
0
Maximum
1.26
3.6
1.89
5.5
1.89
3.6
—
Units
V
V
V
V
V
V
V
100
100
–40
—
—
—
2000
—
85
s
s
ºC
1.When powering-up the CS47L15, the DBVDD and AVDD supplies must be enabled before DCVDD. The DCVDD domain must not be powered if
DBVDD or AVDD is not present. There are no power-down sequencing requirements; the supplies may be disabled in any order.
2.When powering-up the CS47L15, RESET must be deasserted (high) before DCVDD is applied. RESET must be held high until at least 10 ms after
DCVDD is applied.
3.Sleep mode is supported for when DCVDD is below the limits noted, provided that AVDD and DBVDD are present.
4.The impedance between DGND, AGND, and SUBGND must not exceed 0.1 .
The impedance between SPKGNDN, SPKGNDP, and SUBGND must not exceed 0.2 .
5.If the DCVDD rise time exceeds 2 ms, RESET must be asserted (low) during the rise and held asserted until after DCVDD is within the recommended
operating limits. This requirement takes precedence over Note 2 above.
6.The specified minimum power supply rise times assume a minimum decoupling capacitance of 100 nF per pin. However, Cirrus Logic strongly
advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. The specified
minimum power supply rise times also assume a maximum PCB inductance of 10 nH between decoupling capacitor and pin.
Table 3-4. Analog Input Signal Level—IN1Axx, IN1Bxx, IN2x
Test conditions (unless specified otherwise): AVDD = 1.8V, sinusoid input signal; with the exception of the conditions noted, the following electrical
characteristics are valid across the full range of recommended operating conditions.
Parameter
Minimum Typical Maximum
Maximum input signal level (IN1Axx, IN1Bxx) 1, 2
Single-ended configuration, 0 dB PGA gain
—
0.5
—
—
–6
—
Differential configuration 3, 0 dB PGA gain
—
1
—
—
0
—
Maximum input signal level (IN2x) 4
Differential configuration
—
0.1
—
—
–20
—
Note: The maximum and full-scale input signal levels change in proportion with AVDD.
Units
VRMS
dBV
VRMS
dBV
VRMS
dBV
1.The maximum input signal level (before clipping occurs) is also the full-scale input signal level (0 dBFS) at the IN1 ADC outputs.
2.If Low-Power Mode is enabled, the maximum input signal level is reduced by 6 dB. The maximum input signal level corresponds to –6 dBFS at the
IN1 ADC output in this case.
3.A 1.0VRMS differential signal equates to 0.5VRMS/–6dBV per input.
4.The maximum input signal level (before clipping occurs) corresponds to –6 dBFS at the IN2 ADC output.
Table 3-5. Analog Input Pin Characteristics
Test conditions (unless specified otherwise): TA = +25ºC; with the exception of the condition noted, the following electrical characteristics are valid across
the full range of recommended operating conditions.
Input resistance (IN1x)
Input resistance (IN2x)
Input capacitance
Parameter
Minimum
Single-ended PGA input, All PGA gain settings
9
Differential PGA input, All PGA gain settings
18
—
—
Typical
10
21
17
—
Maximum
—
—
—
5
Units
k
k
k
pF
Typical
0
31
1
Maximum
—
—
—
Units
dB
dB
dB
Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs)
The following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter1
Minimum programmable gain
Maximum programmable gain
Programmable gain step size
Minimum
—
—
Guaranteed monotonic
—
1.Note that PGA control is provided for the IN1x analog input channels only.
10
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-7. Digital Input Signal Level—DMICDAT, SPKRXDAT
The following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter
Full-scale input level 1
0 dBFS digital core input, 0 dB gain
Minimum
—
Typical
–6
Max
—
Units
dBFS
1. The digital input signal level is measured in dBFS, where 0 dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The
FSR is defined as the amplitude of a 1-kHz sine wave whose positive and negative peaks are represented by the maximum and minimum
digital codes respectively—this is the largest 1-kHz sine wave that can fit in the digital output range without clipping.
Table 3-8. Output Characteristics
The following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter
Minimum
Line/headphone/earpiece Load resistance
Normal operation, Single-Ended Mode
6
output driver (HPOUTL,
Normal operation, Differential (BTL) Mode
15
HPOUTR)
Device survival with load applied indefinitely
0
Load capacitance
Single-Ended Mode
—
Differential (BTL) Mode
—
Earpiece output driver
Load resistance
Normal operation
15
(EPOUTP+EPOUTN)
Device survival with load applied indefinitely
0
Load capacitance
—
Speaker output driver
Load resistance
Normal operation
4
(SPKOUTP+SPKOUTN)
Device survival with load applied indefinitely
0
Load capacitance
—
0 dBFS digital core output, 0 dB gain
—
Digital speaker output
Full-scale output level 1
(SPKTXDAT)
Typical
—
—
—
—
—
—
—
—
—
—
—
–6
Max
—
—
—
500
200
—
—
200
—
—
200
—
Units



pF
pF


pF


pF
dBFS
1.The digital output signal level is measured in dBFS, where 0 dBFS is a signal level equal to the full-scale range (FSR) of the PDM output.
The FSR is defined as the amplitude of a 1-kHz sine wave whose positive and negative peaks are represented by the maximum and
minimum digital codes respectively—this is the largest 1-kHz sine wave that can fit in the digital output range without clipping.
Table 3-9. Input/Output Path Characteristics
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.
Parameter
Line/headphone/earpiece output DC offset at Load
driver (HPOUTL, HPOUTR)
Min Typ Max Units
Single-ended mode —
50
—
V
Differential (BTL) mode —
75
—
V
—
75
—
V
Earpiece output driver
(EPOUTP+EPOUTN)
Speaker output driver
(SPKOUTP+SPKOUTN)
DC offset at Load
Analog input paths (IN1xL,
IN1xR) to ADC (Differential
Input Mode)
48 kHz sample rate
16 kHz sample rate (wideband voice)
THD, defined in Table 3-1
–1 dBV input
THD+N, defined in Table 3-1
–1 dBV input
Channel separation (L/R), defined in Table 3-1
100 Hz to 10 kHz
Input-referred noise floor
A-weighted, PGA gain = +20 dB
CMRR, defined in Table 3-1
PGA gain = +30 dB
PGA gain = 0 dB
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
11
DC offset at Load
SPKVDD leakage current
SNR (A-weighted), defined in Table 3-1
—
—
90
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300 —
V
1
—
A
98
—
dB
104 —
dB
–87 —
dB
–88 –80
dB
109 —
dB
2.7 — VRMS
79
—
dB
70
—
dB
93
—
dB
77
—
dB
98
—
dB
90
—
dB
98
—
dB
83
—
dB
100 —
dB
95
—
dB
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-9. Input/Output Path Characteristics (Cont.)
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.
Analog input paths (IN1xL,
IN1xR) to ADC (Single-Ended
Input Mode)
Parameter
SNR (A-weighted), defined in Table 3-1
48-kHz sample rate
16-kHz sample rate (wideband voice)
THD, defined in Table 3-1
–7dBV input
THD+N, defined in Table 3-1
–7dBV input
Channel separation (L/R), defined in Table 3-1
100 Hz to 10 kHz
Input-referred noise floor
A-weighted, PGA gain = +20 dB
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Analog input path (IN2) to ADC SNR (A-weighted), defined in Table 3-1
48 kHz sample rate
(Differential Input Mode)
THD, defined in Table 3-1
–21 dBV input
THD+N, defined in Table 3-1
–21 dBV input
Input-referred noise floor
A-weighted
CMRR, defined in Table 3-1
PSRR (DBVDD, CPVDD, AVDD),
defined in Table 3-1
PSRR (MICVDD), defined in Table 3-1
PSRR (DCVDD), defined in Table 3-1
PSRR (SPKVDD), defined in Table 3-1
DAC to line output (HPOUTL,
HPOUTR; Load = 10 k,
50 pF)
12
Full-scale output signal level
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
0 dBFS input
SNR, defined in Table 3-1
A-weighted, output signal = 1 VRMS
Dynamic range, defined in Table 3-1
A-weighted, –60 dBFS input
THD, defined in Table 3-1
0 dBFS input
THD+N, defined in Table 3-1
0 dBFS input
Channel separation (L/R), defined in Table 3-1
100 Hz to 10 kHz
Output noise floor
A-weighted
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Min
85
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
105
—
—
—
—
—
—
—
—
—
—
—
—
Typ Max Units
97
—
dB
102 —
dB
–86 —
dB
–85 –78
dB
107 —
dB
4
— VRMS
77
—
dB
52
—
dB
100 —
dB
90
—
dB
96
—
dB
74
—
dB
100 —
dB
80
—
dB
70
—
dB
–65 —
dB
–63 —
dB
28
— VRMS
60
—
dB
70
—
dB
50
—
dB
50
—
dB
71
—
dB
83
—
dB
50
—
dB
50
—
dB
50
—
dB
50
—
dB
1
— VRMS
dBV
0
—
127 —
dB
114 —
dB
–94 —
dB
–92 –85
dB
105 —
dB
0.45 — VRMS
124 —
dB
80
—
dB
110 —
dB
105 —
dB
126 —
dB
90
—
dB
110 —
dB
100 —
dB
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-9. Input/Output Path Characteristics (Cont.)
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.
DAC to headphone output
(HPOUTL, HPOUTR;
RL = 32 )
DAC to headphone output
(HPOUTL, HPOUTR;
RL = 16 )
DAC to earpiece output
(EPOUTP+EPOUTN,
RL = 32  BTL)
13
Parameter
Maximum output power
0.1% THD+N
SNR, defined in Table 3-1
A-weighted, output signal = 1 VRMS
Dynamic range, defined in Table 3-1
A-weighted, –60 dBFS input
THD, defined in Table 3-1
PO = 25 mW
THD+N, defined in Table 3-1
PO = 25 mW
THD, defined in Table 3-1
PO = 20 mW
THD+N, defined in Table 3-1
PO = 20 mW
THD, defined in Table 3-1
PO = 2 mW
THD+N, defined in Table 3-1
PO = 2 mW
Channel separation (L/R), defined in Table 3-1
100 Hz to 10 kHz
Output noise floor
A-weighted
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Maximum output power
0.1% THD+N
SNR, defined in Table 3-1
A-weighted, output signal = 1 VRMS
Dynamic range, defined in Table 3-1
A-weighted, –60 dBFS input
THD, defined in Table 3-1
PO = 25 mW
THD+N, defined in Table 3-1
PO = 25 mW
THD, defined in Table 3-1
PO = 20 mW
THD+N, defined in Table 3-1
PO = 20 mW
THD, defined in Table 3-1
PO = 2 mW
THD+N, defined in Table 3-1
PO = 2 mW
Channel separation (L/R), defined in Table 3-1
100 Hz to 10 kHz
Output noise floor
A-weighted
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Maximum output power
0.1% THD+N
SNR, defined in Table 3-1
A-weighted, output signal = 1.41 VRMS
Dynamic range, defined in Table 3-1
A-weighted, –60 dBFS input
THD, defined in Table 3-1
PO = 75 mW
THD+N, defined in Table 3-1
PO = 75 mW
THD, defined in Table 3-1
PO = 5 mW
THD+N, defined in Table 3-1
PO = 5 mW
Output noise floor
A-weighted
PSRR (DBVDD, CPVDD, AVDD),
100 mV (peak-peak) 217 Hz
defined in Table 3-1
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Min
—
—
105
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
105
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
105
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ Max Units
30
—
mW
127 —
dB
115 —
dB
–94 —
dB
–92 —
dB
–92 —
dB
–90 –85
dB
–92 —
dB
–90 —
dB
102 —
dB
0.45 — VRMS
124 —
dB
80
—
dB
124 —
dB
110 —
dB
126 —
dB
90
—
dB
110 —
dB
100 —
dB
40
—
mW
127 —
dB
114 —
dB
–90 —
dB
–88 —
dB
–90 —
dB
–88 –80
dB
–88 —
dB
–86 —
dB
100 —
dB
0.45 — VRMS
124 —
dB
80
—
dB
124 —
dB
110 —
dB
126 —
dB
90
—
dB
110 —
dB
100 —
dB
96
—
mW
128 —
dB
118 —
dB
–92 —
dB
–88 —
dB
–88 —
dB
–86 —
dB
0.60 — VRMS
85
—
dB
85
—
dB
124 —
dB
110 —
dB
126 —
dB
86
—
dB
110 —
dB
105 —
dB
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-9. Input/Output Path Characteristics (Cont.)
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.
DAC to earpiece output
(EPOUTP+EPOUTN,
RL = 16  BTL)
Parameter
Maximum output power
SNR, defined in Table 3-1
Dynamic range, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
Output noise floor
PSRR (DBVDD, CPVDD, AVDD),
defined in Table 3-1
PSRR (MICVDD), defined in Table 3-1
PSRR (DCVDD), defined in Table 3-1
PSRR (SPKVDD), defined in Table 3-1
DAC to speaker output
(SPKOUTP+SPKOUTN,
Load = 8 , 22 H, BTL)
Maximum output power
SNR, defined in Table 3-1
Dynamic range, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
Output noise floor
PSRR (DBVDD, CPVDD, AVDD),
defined in Table 3-1
PSRR (MICVDD), defined in Table 3-1
PSRR (DCVDD), defined in Table 3-1
PSRR (SPKVDD), defined in Table 3-1
DAC to speaker output
(SPKOUTP+SPKOUTN,
Load = 4 , 15 H, BTL)
Maximum output power
SNR, defined in Table 3-1
Dynamic range, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
THD, defined in Table 3-1
THD+N, defined in Table 3-1
Output noise floor
PSRR (DBVDD, CPVDD, AVDD),
defined in Table 3-1
PSRR (MICVDD), defined in Table 3-1
PSRR (DCVDD), defined in Table 3-1
PSRR (SPKVDD), defined in Table 3-1
14
0.1% THD+N
A-weighted, output signal = 1.41 VRMS
A-weighted, –60 dBFS input
PO = 75 mW
PO = 75 mW
PO = 5 mW
PO = 5 mW
A-weighted
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
SPKVDD = 5.0 V, 1% THD+N
SPKVDD = 4.2 V, 1% THD+N
SPKVDD = 3.6 V, 1% THD+N
A-weighted, output signal = 2.83 VRMS
A-weighted, –60 dBFS input
PO = 1.0 W
PO = 1.0 W
PO = 0.5 W
PO = 0.5 W
A-weighted
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
SPKVDD = 5.0 V, 1% THD+N
SPKVDD = 4.2 V, 1% THD+N
SPKVDD = 3.6 V, 1% THD+N
A-weighted, output signal = 2.83 VRMS
A-weighted, –60 dBFS input
PO = 1.0 W
PO = 1.0 W
PO = 0.5 W
PO = 0.5 W
A-weighted
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Min
—
—
105
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ Max Units
108 —
mW
128 —
dB
118 —
dB
–89 —
dB
–87 —
dB
–90 —
dB
–88 —
dB
0.60 — VRMS
85
—
dB
85
—
dB
124 —
dB
110 —
dB
126 —
dB
86
—
dB
108 —
dB
110 —
dB
1.4 —
W
1.0 —
W
0.7 —
W
—
90
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
127 —
dB
100 —
dB
–40 —
dB
–40 —
dB
–61 —
dB
–60 –50
dB
1.3 — VRMS
110 —
dB
90
—
dB
124 —
dB
110 —
dB
125 —
dB
105 —
dB
125 —
dB
105 —
dB
2.5 —
W
1.8 —
W
1.3 —
W
127 —
dB
100 —
dB
–40 —
dB
–40 —
dB
–61 —
dB
–60 —
dB
1.3 — VRMS
110 —
dB
90
—
dB
124 —
dB
110 —
dB
125 —
dB
105 —
dB
125 —
dB
105 —
dB
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-10. Digital Input/Output
The following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter
Digital I/O (except
DMICDAT and
DMICCLK) 1,3
DMIC I/O
(DMICDAT and
DMICCLK) 2,3
GPIOn
Minimum
VDBVDD = 1.71–1.98 V 0.75 DBVDD
VDBVDD = 2.5 V ±10% 0.8 DBVDD
VDBVDD = 3.3 V ±10% 0.7 DBVDD
—
Input LOW level
VDBVDD = 1.71–1.98 V
VDBVDD = 2.5 V ±10%
—
VDBVDD = 3.3 V ±10%
—
VDBVDD = 1.71–1.98 V 0.75 DBVDD
Output HIGH level
VDBVDD = 2.5 V ±10% 0.65 DBVDD
(IOH = 1 mA)
VDBVDD = 3.3 V ±10% 0.7 DBVDD
VDBVDD = 1.71–1.98 V
—
Output LOW level
VDBVDD = 2.5 V ±10%
—
(IOL = 1mA)
VDBVDD = 3.3 V ±10%
—
Input capacitance
—
Input leakage
–1
Pull-up/pull-down resistance (where applicable)
RESET pin
35
All other pins
25
DMICDAT input HIGH Level
0.65  VSUP
DMICDAT input LOW Level
—
DMICCLK output HIGH Level
IOH = 1 mA
0.8  VSUP
—
DMICCLK output LOW Level
IOL = –1 mA
Input capacitance
—
Input leakage
–1
Clock output frequency
GPIO pin as OPCLK or FLL output
—
Input HIGH level
Typical
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25
—
—
Maximum
—
—
—
0.3 DBVDD
0.25 DBVDD
0.2 DBVDD
—
—
—
0.25 DBVDD
0.3 DBVDD
0.15 DBVDD
5
1
55
50
—
0.35  VSUP
—
0.2  VSUP
1
50
Units
V
V
V
V
V
V
V
V
V
V
V
V
pF
A
k
k
V
V
V
V
pF
A
MHz
1.Digital I/O is referenced to DBVDD.
2.DMICDAT and DMICCLK are referenced to a selectable supply, VSUP, according to the IN1_DMIC_SUP field.
3.Note that digital input pins should not be left unconnected or floating.
15
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-11. Miscellaneous Characteristics
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.
Parameter
Minimum Bias Voltage 2
Maximum Bias Voltage
Bias Voltage output step size
Bias Voltage accuracy
Regulator Mode (MICB1_BYPASS = 0), VMICVDD – VMICBIAS >200 mV
Bias Current 3
Bypass Mode (MICBn_BYPASS = 1)
Output Noise Density
Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,
Load current = 1 mA, Measured at 1 kHz
Integrated noise voltage
Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,
Load current = 1 mA, 100 Hz to 7 kHz, A-weighted
PSRR (DBVDD, CPVDD, AVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (MICVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (DCVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
PSRR (SPKVDD), defined in Table 3-1
100 mV (peak-peak) 217 Hz
100 mV (peak-peak) 10 kHz
Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 0
Load capacitance 3
Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 1
Output discharge resistance
MICBnx_ENA = 0, MICBnx_DISCH = 1
Switch closed, I = 1 mA
General-purpose Switch resistance
Switch open
switch 4
External
Headphone detection load impedance range:
HPD_IMPEDANCE_RANGE = 01
Accessory
Detection via HPOUTL (HPD_SENSE_SEL = 100) or
HPD_IMPEDANCE_RANGE = 10
Detect
HPOUTR (HPD_SENSE_SEL = 101)
HPD_IMPEDANCE_RANGE = 11
Headphone detection load impedance range:
Detection via MICDETn or JACKDETn pins
HPD_IMPEDANCE_RANGE = 01
Headphone detection accuracy:
(HPD_DACVAL, HPD_SENSE_SEL = 100 or 101)
HPD_IMPEDANCE_RANGE = 10
HPD_IMPEDANCE_RANGE = 11
Headphone detection accuracy (HPD_LVL, HPD_SENSE_SEL = 0XX or 11X)
for MICD1_LVL[0] = 1
Microphone impedance detection range:
for MICD1_LVL[1] = 1
(MICD1_ADC_MODE = 0, 2.2 k ±2% MICBIAS resistor. 5
for MICD1_LVL[2] = 1
for MICD1_LVL[3] = 1
for MICD1_LVL[8] = 1
Jack-detection input threshold voltage
Detection on JACKDET1, Jack insertion
(JACKDETn)
Detection on JACKDET1, Jack removal
Detection on JACKDET2, Jack insertion
Detection on JACKDET2, Jack removal
Pull-up resistance (JACKDETn)
Frequency-Lock Output frequency
FLL output as SYSCLK source
ed Loop (FLL1)
FLL output as DSPCLK source
Lock Time
FREF = 32 kHz, FOUT (DSPCLK source) = 147.456 MHz
FREF = 12 MHz, FOUT (DSPCLK source) = 147.456 MHz
Microphone bias
(MICBIAS1A,
MICBIAS1B,
MICBIAS1C) 1
RESET pin input RESET input pulse width 6
Min Typ
—
1.5
—
2.8
—
0.1
–5% —
—
—
—
—
—
50
Max
—
—
—
+5%
2.4
5.0
—
Units
V
V
V
V
mA
mA
nV/Hz
—
5
—
VRMS
—
—
—
—
—
—
—
—
—
0.1
—
—
—
0
90
1
400
100
80
82
44
100
80
100
80
—
1.0
2
25
100
—
—
—
—
—
—
—
—
—
—
—
—
50
10
—
40
—
90
1000
10
6000
dB
dB
dB
dB
dB
dB
dB
dB
pF
F
k

M


k

–10
–5
–10
–20
0
110
210
360
1
—
—
—
—
—
90
135
—
—
1
—
—
—
—
—
—
—
—
—
0.9
1.65
0.27
0.9
1
—
—
10
1
—
+10
+5
+10
+20
70
180
290
680
30
—
—
—
—
—
98.3
150
—
—
—
%
%
%
%




k
V
V
V
V
M
MHz
MHz
ms
ms
s
1.No capacitor on MICBIAS1x. In Regulator Mode, it is required that VMICVDD – VMICBIAS > 200 mV.
2.Regulator Mode (MICB1_BYPASS = 0), Load current  1.0 mA.
3.Bias current and load capacitance specifications are for the sum of all enabled MICBIAS1x outputs.
4.The GPSWN pin voltage must not exceed GPSWP + 0.3 V. See Table 3-2 for voltage limits applicable to the GPSWP and GPSWN pins.
5.These characteristics assume no other component is connected to MICDETn.
6.To trigger a hardware reset, the RESET input must be asserted for longer than this duration.
16
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-12. Device Reset Thresholds
The following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter
Symbol
Minimum
Typical
Maximum
Units
VAVDD
—
—
1.66
V
VAVDD rising
VAVDD falling
1.06
—
1.44
V
VDCVDD
—
—
1.04
V
DCVDD reset threshold
VDCVDD rising
VDCVDD falling
0.40
—
0.72
V
VDBVDD
—
—
1.66
V
DBVDD reset threshold
VDBVDD rising
VDBVDD falling
1.06
—
1.44
V
Note: The reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured
outside the voltage ranges defined in Table 3-3.
AVDD reset threshold
Table 3-13. System Clock and Frequency-Locked Loop (FLL)
The following timing information is valid across the full range of recommended operating conditions.
Parameter
Minimum
MCLK as input to FLL, FLL1_REFCLK_DIV = 00
74
MCLK as input to FLL, FLL1_REFCLK_DIV = 01
37
MCLK as input to FLL, FLL1_REFCLK_DIV = 10
18
MCLK as input to FLL, FLL1_REFCLK_DIV = 11
12.5
MCLK as direct SYSCLK source
40
MCLK duty cycle
MCLK as input to FLL
80:20
MCLK as direct SYSCLK source
60:40
Frequency-locked FLL input frequency
FLL1_REFCLK_DIV = 00
0.032
loop (FLL1)
FLL1_REFCLK_DIV = 01
0.064
FLL1_REFCLK_DIV = 11
0.128
FLL1_REFCLK_DIV = 11
0.256
FLL synchronizer input
FLL1_SYNCCLK_DIV = 00
0.032
frequency
FLL1_SYNCCLK_DIV = 01
0.064
FLL1_SYNCCLK_DIV = 10
0.128
FLL1_SYNCCLK_DIV = 11
0.256
Internal clocking
SYSCLK frequency
SYSCLK_FREQ = 000, SYSCLK_FRAC = 0
–1%
SYSCLK_FREQ = 000, SYSCLK_FRAC = 1
–1%
SYSCLK_FREQ = 001, SYSCLK_FRAC = 0
–1%
SYSCLK_FREQ = 001, SYSCLK_FRAC = 1
–1%
SYSCLK_FREQ = 010, SYSCLK_FRAC = 0
–1%
SYSCLK_FREQ = 010, SYSCLK_FRAC = 1
–1%
SYSCLK_FREQ = 011, SYSCLK_FRAC = 0
–1%
SYSCLK_FREQ = 011, SYSCLK_FRAC = 1
–1%
–1%
SYSCLK_FREQ = 100, SYSCLK_FRAC = 0
–1%
SYSCLK_FREQ = 100, SYSCLK_FRAC = 1
DSPCLK frequency
5
Master clock
timing (MCLK1,
MCLK2) 1
MCLK cycle time
Typical
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6.144
5.6448
12.288
11.2896
24.576
22.5792
49.152
45.1584
98.304
90.3168
—
Maximum
—
—
—
—
—
20:80
40:60
13.5
27
54
80
13.5
27
54
80
+1%
+1%
+1%
+1%
+1%
+1%
+1%
+1%
+1%
+1%
150
Units
ns
ns
ns
ns
ns
%
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.If MCLK1 or MCLK2 is selected as a source for SYSCLK (either directly or via the FLL), the frequency must be within 1% of the SYSCLK_FREQ
setting.
17
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-14. Digital Microphone (DMIC) Interface Timing
The following timing information is valid across the full range of recommended operating conditions.
Parameter 1,2
Symbol
Minimum
Typical Maximum Units
DMICCLK cycle time
tCY
160
163
1432
ns
DMICCLK duty cycle
—
45
—
55
%
DMICCLK rise/fall time (25-pF load, 1.8-V supply)
tr, tf
5
—
30
ns
DMICDAT (Left) setup time to falling DMICCLK edge
tLSU
15
—
—
ns
DMICDAT (Left) hold time from falling DMICCLK edge
tLH
0
—
—
ns
DMICDAT (Right) setup time to rising DMICCLK edge
tRSU
15
—
—
ns
DMICDAT (Right) hold time from rising DMICCLK edge
tRH
0
—
—
ns
Note: The voltage reference for the IN1 interface is selectable, using the IN1_DMIC_SUP field—the interface is referenced to MICVDD or
MICBIAS1.
1.DMIC interface timing
tCY
DMICCLK
(output)
VOH
VOL
tr
tf
tRSU t RH
DMICDAT
(input)
tLSU
(right data)
t LH
VIH
VIL
(left data)
2.If the SPKRXDAT pin is configured for digital input, the SPKRXDAT timing requirements (with respect to SPKCLK) are the same as the DMICDAT
timing requirements (with respect to DMICCLK).
Table 3-15. Digital Speaker (PDM) Interface Timing
The following timing information is valid across the full range of recommended operating conditions.
Mode A 1
Mode B 2
Parameter
SPKCLK cycle time
SPKCLK duty cycle
SPKCLK rise/fall time (25-pF load)
SPKTXDAT set-up time to SPKCLK rising edge (left channel)
SPKTXDAT hold time from SPKCLK rising edge (left channel)
SPKTXDAT set-up time to SPKCLK falling edge (right channel)
SPKTXDAT hold time from SPKCLK falling edge (right channel)
SPKCLK cycle time
SPKCLK duty cycle
SPKCLK rise/fall time (25-pF load)
SPKTXDAT enable from SPKCLK rising edge (right channel)
SPKTXDAT disable to SPKCLK falling edge (right channel)
SPKTXDAT enable from SPKCLK falling edge (left channel)
SPKTXDAT disable to SPKCLK rising edge (left channel)
Symbol
tCY
—
tr, tf
tLSU
tLH
tRSU
tRH
tCY
—
tr, tf
tREN
tRDIS
tLEN
tLDIS
Minimum
160
45
2
30
30
30
30
160
45
2
—
—
—
—
1.Digital speaker (PDM) interface timing—Mode A
Maximum
358
55
8
—
—
—
—
358
55
8
15
5
15
5
Units
ns
%
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
tCY
SPKCLK
(output)
SPKTXDAT
(output)
18
Typical
163
—
—
—
—
—
—
163
—
—
—
—
—
—
V OH
V OL
tr
tf
t LH
t RH
(left data)
(right data )
t LSU
t RSU
V OH
VOL
DS1137PP1
CS47L15
3 Characteristics and Specifications
2.Digital speaker (PDM) interface timing—Mode B
tCY
SPKCLK
(output)
VOH
V OL
tr
SPKTXDAT
(output)
tf
tLEN
t REN
(left data)
VOH
V OL
(right data)
tLDIS
tRDIS
Table 3-16. Digital Audio Interface—Master Mode
Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); BCLK slew (10% to 90%) = 3.7–5.6 ns; with the exception of the conditions
noted, the following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter 1
AIFnBCLK cycle time
AIFnBCLK pulse width high
AIFnBCLK pulse width low
AIFnLRCLK propagation delay from BCLK falling edge 2
AIFnTXDAT propagation delay from BCLK falling edge
AIFnRXDAT setup time to BCLK rising edge
AIFnRXDAT hold time from BCLK rising edge
Master Mode,
AIFnLRCLK setup time to BCLK rising edge
Slave LRCLK
AIFnLRCLK hold time from BCLK rising edge
Note: The descriptions above assume noninverted polarity of AIFnBCLK.
Master Mode
Symbol
tBCY
tBCH
tBCL
tLRD
tDD
tDSU
tDH
tLRSU
tLRH
Minimum
40
18
18
0
0
11
0
14
0
1.Digital audio interface timing—Master Mode. Note that BCLK and LRCLK outputs
can be inverted if required; the figure shows the default, noninverted polarity.
Typical
—
—
—
—
—
—
—
—
—
Maximum
—
—
—
8.3
5
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
t BCY
BCLK
(output)
tBCH
LRCLK
(output)
TXDAT
(output)
tBCL
tLRD
tDD
RXDAT
(input)
tDH
t DSU
2.The timing of the AIFnLRCLK signal is selectable. If the LRCLK advance option is enabled, the LRCLK transition is timed relative to the preceding
BCLK edge. Under the required condition that BCLK is inverted in this case, the LRCLK transition is still timed relative to the falling BCLK edge.
19
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-17. Digital Audio Interface—Slave Mode
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
Parameter 1,2
AIFnBCLK cycle time
AIFnBCLK pulse width high
BCLK as direct SYSCLK source
All other conditions
AIFnBCLK pulse width low
BCLK as direct SYSCLK source
All other conditions
CLOAD = 15 pF (output pins), AIFnLRCLK set-up time to BCLK rising edge
BCLK slew (10%–90%) = 3 ns AIFnLRCLK hold time from BCLK rising edge
AIFnTXDAT propagation delay from BCLK falling edge
AIFnRXDAT set-up time to BCLK rising edge
AIFnRXDAT hold time from BCLK rising edge
Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge
CLOAD = 25 pF (output pins), AIFnLRCLK set-up time to BCLK rising edge
BCLK slew (10%–90%) = 6 ns AIFnLRCLK hold time from BCLK rising edge
AIFnTXDAT propagation delay from BCLK falling edge
AIFnRXDAT set-up time to BCLK rising edge
AIFnRXDAT hold time from BCLK rising edge
Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge
Note: The descriptions above assume noninverted polarity of AIFnBCLK.
1.Digital audio interface timing—Slave Mode. Note that BCLK and LRCLK inputs can
be inverted if required; the figure shows the default, noninverted polarity.
Symbol
tBCY
tBCH
tBCH
tBCL
tBCL
tLRSU
tLRH
tDD
tDSU
tDH
tLRD
tLRSU
tLRH
tDD
tDSU
tDH
tLRD
Min Typ Max Units
40 —
—
ns
16 —
—
ns
14 —
—
ns
16 —
—
ns
14 —
—
ns
7
—
—
ns
0
—
—
ns
0
— 12.2 ns
2
—
ns
0
—
ns
— — 14.8 ns
7
—
ns
0
—
ns
0
— 14.2 ns
2
—
ns
0
—
ns
— — 15.9 ns
tBCY
BCLK
(input)
LRCLK
(input)
TXDAT
(output)
tBCH
t BCL
tLRH
tLRSU
tDD
RXDAT
(input)
tDSU
t DH
2.If AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK (either directly or via the FLL), the frequency must be within 1% of the SYSCLK_
FREQ setting.
Table 3-18. Digital Audio Interface Timing—TDM Mode
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
Parameter 1
Min
Typ
Max
Units
AIFnTXDAT enable time from BCLK falling edge
0
—
—
ns
Master Mode—CLOAD (AIFnTXDAT) = 15 to
25 pF. BCLK slew (10%–90%) = 3.7ns to 5.6 ns. AIFnTXDAT disable time from BCLK falling edge
—
—
6
ns
Slave Mode—CLOAD (AIFnTXDAT) = 15 pF).
AIFnTXDAT enable time from BCLK falling edge
2
—
—
ns
BCLK slew (10%–90%) = 3 ns
AIFnTXDAT disable time from BCLK falling edge
—
—
12.2
ns
Slave Mode—CLOAD (AIFnTXDAT) = 25 pF).
AIFnTXDAT enable time from BCLK falling edge
2
—
—
ns
BCLK slew (10%–90%) = 6 ns
AIFnTXDAT disable time from BCLK falling edge
—
—
14.2
ns
Note: If TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt to drive the AIFnTXDAT pin
simultaneously. To support this requirement, the AIFnTXDAT pins can be configured to be tristated when not outputting data.
1.Digital audio interface timing—TDM Mode.
The timing of the AIFnTXDAT tristating at the
start and end of the data transmission is
shown.
BCLK
TXDAT
AIFnTXDAT undriven (tristate)
AIFnTXDAT valid (codec output)
AIFnTXDAT enable time
20
AIFnTXDAT valid
AIFnTXDAT undriven (tristate)
AIFnTXDAT disable time
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-19. Control Interface Timing—Two-Wire (I2C) Mode
The following timing information is valid across the full range of recommended operating conditions.
Parameter 1
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA, SCLK Rise Time (10%–90%)
SCLK frequency > 1.7MHz
SCLK frequency > 1MHz
SCLK frequency  1MHz
SCLK frequency > 1.7MHz
SCLK frequency > 1MHz
SCLK frequency  1MHz
SDA, SCLK Fall Time (90%–10%)
Setup Time (Stop Condition)
SDA Setup Time (data input)
SDA Hold Time (data input)
SDA Valid Time (data/ACK output)
SCLK slew (90%–10%) = 20ns, CLOAD (SDA) = 15 pF
SCLK slew (90%–10%) = 60ns, CLOAD (SDA) = 100 pF
SCLK slew (90%–10%) = 160ns, CLOAD (SDA) = 400 pF
SCLK slew (90%–10%) = 200ns, CLOAD (SDA) = 550 pF
Pulse width of spikes that are suppressed
1.Control interface
timing—I2C Mode
START
t1
Symbol
—
t1
t2
t3
t4
t6
t6
t6
t7
t7
t7
t8
t5
t9
t10
t10
t10
t10
tps
t2
Min
—
160
100
160
160
—
—
—
—
—
—
160
40
0
—
—
—
—
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3400
—
—
—
—
80
160
2000
60
160
200
—
—
—
40
130
190
220
25
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STOP
t6
SCLK
(input)
t4
t7
t3
t8
SDA
t5
21
t9
t10
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-20. Control Interface Timing—Four-Wire (SPI) Mode
The following timing information is valid across the full range of recommended operating conditions.
Parameter 1, 2
SS falling edge to SCLK rising edge
SCLK falling edge to SS rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
MOSI to SCLK set-up time
MOSI to SCLK hold time
SCLK falling edge to MISO transition
SYSCLK disabled (SYSCLK_ENA = 0)
SYSCLK_ENA = 1, SYSCLK_FREQ = 000
SYSCLK_ENA = 1, SYSCLK_FREQ > 000
SCLK slew (90%–10%) = 5 ns, CLOAD (MISO) = 25 pF
1.Control interface timing—SPI Mode (write
cycle)
tSSU
Symbol
Min
Typ
Max
Units
tSSU
2.6
—
—
ns
tSHO
tSCY
tSCY
tSCY
tSCL
tSCH
tDSU
tDHO
tDL
0
38.4
76.8
38.4
15.3
15.3
1.5
1.7
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSHO
SS
(input)
tSCY
SCLK
(input)
tSCH
MOSI
(input)
tSCL
tDSU
tDHO
2.Control interface timing—SPI Mode (read
cycle)
SS
(input)
SCLK
(input)
MISO
(output)
tDL
22
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-21. Master Interface Timing—SPI Master
The following timing information is valid across the full range of recommended operating conditions.
Parameter 1
Symbol
Min
Typ
Max
Units
SS falling edge to SCLK rising edge
tSSU
13.88
—
—
ns
SCLK falling edge to SS rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SCLK falling edge to MOSI transition
MISO to SCLK set-up time
MISO to SCLK hold time
tSHO
tSCY
tSCL
tSCH
tDL
tDSU
tDHO
0
27.77
13.88
13.88
0
5
5
—
—
—
—
—
—
—
—
—
—
—
8.88
—
—
ns
ns
ns
ns
ns
ns
ns
SCLK slew (90%–10%) = 5 ns, CLOAD (MOSI) = 25 pF
1.Master interface timing—SPI read cycle
tSHO
tSSU
SS
(output)
tSCY
SCLK
(output)
tSCH
tSCL
MOSI
(output)
tDL
MISO
(input)
23
tDSU
tDHO
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-22. JTAG Interface Timing
Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); TCK slew (20%–80%) = 5 ns; with the exception of the conditions noted,
the following electrical characteristics are valid across the full range of recommended operating conditions.
Parameter 1
TCK cycle time
TCK pulse width high
TCK pulse width low
TMS setup time to TCK rising edge
TMS hold time from TCK rising edge
TDI setup time to TCK rising edge
TDI hold time from TCK rising edge
TDO propagation delay from TCK falling edge
TRST setup time to TCK rising edge
TRST hold time from TCK rising edge
TRST pulse width low
Symbol
TCCY
TCCH
TCCL
TMSU
TMH
TDSU
TDH
TDD
TRSU
TRH
—
1.JTAG Interface timing
Minimum
50
20
20
1
2
1
2
0
3
3
20
Typical
—
—
—
—
—
—
—
—
—
—
—
Maximum
—
—
—
—
—
—
—
17
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCCY
TCK
(input)
TRST
(input)
t CCH
t CCL
t RSU
tRH
TMS
(input)
TDI
(input)
TDO
(output)
24
tMSU
tMH
tDSU
t DH
t DD
DS1137PP1
CS47L15
3 Characteristics and Specifications
Table 3-23. Typical Power Consumption
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
Fs = 48 kHz; 24-bit audio data, I2S Slave Mode; SYSCLK = 24.576 MHz (direct MCLK1 input).
Operating Configuration
Headphone playback—AIF1 to DAC to
Quiescent
HPOUT (stereo), 32- load.
1-kHz sine wave, PO = 0.1 mW
Earpiece playback—AIF1 to DAC to EPOUT,
Quiescent
32- load (BTL).
1-kHz sine wave, PO = 30 mW
Speaker playback—AIF1 to DAC to SPKOUT,
Quiescent
8-, 22-H load.
1-kHz sine wave, PO = 700 mW
Stereo line record—Analog line to ADC to
1-kHz sine wave, –1 dBFS output
AIF1
Sleep Mode
Accessory detect enabled (JD1_ENA = 1)
Typical
I1.2V (mA)
0.78
0.87
0.59
0.62
0.61
0.66
1.11
Typical
I1.8V (mA)
0.92
3.6
0.94
61.68
1.18
1.18
2.22
Typical
I2.5V (mA)
0.001
0.001
0.001
0.001
0.001
0.001
0.001
Typical
I4.2V (mA)
0.00
0.00
0.00
0.00
0.13
187
0.00
PTOT
(mW)
2.59
7.6
2.40
112
3.40
790
5.33
0.000
0.014
0.000
0.000
0.025
Table 3-24. Typical Signal Latency
Test conditions (unless specified otherwise): DBVDD = CPVDD = AVDD = 1.8 V, DCVDD = 1.2 V; MICVDD = 2.5 V; SPKVDD = 4.2 V; TA = +25ºC;
Fs = 48 kHz; 24-bit audio data, I2S Slave Mode; SYSCLK = 24.576 MHz (direct MCLK1 input).
AIF to DAC path
Operating Configuration
Digital input (AIFn) to analog output (HPOUT).
ADC to AIF path
Analog input (INn) to digital output (AIFn).2
48 kHz input, 48 kHz output, Synchronous
44.1 kHz input, 44.1 kHz output, Synchronous
16 kHz input, 16 kHz output, Synchronous
8 kHz input, 8 kHz output, Synchronous
8 kHz input, 48 kHz output, Isochronous 1
16 kHz input, 48 kHz output, Isochronous 1
48 kHz input, 48 kHz output, Synchronous
44.1 kHz input, 44.1 kHz output, Synchronous
16 kHz input, 16 kHz output, Synchronous
8 kHz input, 8 kHz output, Synchronous
8 kHz input, 48 kHz output, Isochronous 1
16 kHz input, 48 kHz output, Isochronous 1
Latency (s)
332
358
550
1076
1717
1041
219
234
654
1323
1802
994
1.Signal is routed via the ISRC function in the isochronous cases only.
2.Digital core high-pass filter is included in the signal path
DS1137PP1
25
CS47L15
4 Functional Description
4 Functional Description
The CS47L15 is a highly integrated, low-power audio hub codec for mobile telephony, media players and wearable
technology devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and
cost-effective package. It also provides exceptional levels of performance and signal-processing capability, suitable for a
wide variety of mobile and handheld applications.
4.1 Overview
AVDD
AGND
VREFC
Reference
Generator
AIFnBCLK
AIFnLRCLK
2 x FLL
MICDET2/
HPOUTFB2
MICDET1/
HPOUTFB1
JACKDET2
JACKDET1
HPOUTR
Five-band equal izer (EQ)
Dynamic range control (DRC)
Low-pass/high-pass filter (LHPF)
Automatic sample -rate detection
DAC
EPOUTP
EPOUTN
SYSCLK
AEC (Echo Cancelation)
Loop-Back
DSPCLK
Digital Audio
Interface AIF1
Digital Audio
Interface AIF2
Digital Audio
Interface AIF3
SPKOUTP
SPKOUTN
PDM
Driver
Tone generator
Noise generator
PWM signal generator
Haptic control signal generator
Digital PDM
Interface
Clocking
Control
SUBGND
DAC
Digital Mic
Interface
ADC
MCLK1
MCLK2
SPKVDD
SPKGNDP
SPKGNDN
Programmable DSP
Always-on signal processing
TX noise reduction
Acoustic -echo cancelation
Speaker protection
AIF3TXDAT
AIF3RXDAT
AIF3BCLK
AIF3LRCLK
Input
Select
DCVDD
DBVDD
DGND
CPVDD
CPGND
CPVOUT2P
CPC2B
CPC2A
CPVOUT1N
CP1OUT1P
CP11B
CPVOUT2N
HPOUTL
Digital Core
AIF2TXDAT
AIF2RXDAT
AIF2BCLK
AIF2LRCLK
IN2N
IN2P
SPKRXDAT
IRQ
DAC
ADC
AIF1TXDAT
AIF1RXDAT
AIF1BCLK
AIF1LRCLK
Input
Select
External Accessory
Detect
CS47L15
ADC
IN1BLN
IN1BLP
IN1ALN/DMICCLK
IN1ALP/DMICDAT
IN1BRN
IN1BRP
IN1ARN
IN1ARP
RESET
Charge Pump
General
Purpose
Switch
SPKCLK
SPKTXDAT
GPSWP
GPSWN
Control Interfaces (SPI, I2C)
Master Interface (SPI)
MSTRBOOT
MICBIAS
Generator
SPIMISO/SCLK
SPIMOSI/SDA
SPISCLK
SPISS
MICBIAS1A
MICBIAS1B
MICBIAS1C
CPC1A
MICVDD
The CS47L15 block diagram is shown in Fig. 4-1.
Figure 4-1. CS47L15 Block Diagram
The CS47L15 digital core provides a flexible capability for signal-processing algorithms, including transmit (TX) path noise
reduction, acoustic-echo cancelation (AEC), and other programmable filters. Low-power analog and digital interfaces
provide additional support for always-on voice applications and speaker-protection algorithms implemented on the DSP
core. The DSP is supported by integrated general-purpose timers and event-logger functions. The DSP is ideally suited
to the Cirrus Logic® SoundClear® suite of audio processing algorithms, such as the SoundClear Control always-on voice
control software.
The CS47L15 digital core supports audio enhancements, such as dynamic range control (DRC) and multiband
compression (MBC). Highly flexible digital mixing, including stereo full-duplex isochronous sample-rate conversion,
provides use-case flexibility across a broad range of system architectures. A signal generator for controlling haptics vibe
actuators is included.
26
DS1137PP1
CS47L15
4.1 Overview
The CS47L15 provides multiple digital audio interfaces to provide independent isochronous connections to different
processors (e.g., application processor, baseband processor, and wireless transceiver). The DACs and output paths
support high definition audio throughout the entire signal chain, enabling studio-quality playback without loss of detail or
bandwidth.
A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the
digital audio interface. Two frequency-locked loop (FLL) circuits provide additional flexibility for system clocking, including
low-power always-on operation. Seamless switching between clock sources is supported, and free-running modes are
also available.
Unused circuitry can be disabled under software control to save power; low leakage currents enable extended standby/off
time in portable battery-powered applications. The CS47L15 always-on circuitry can be used in conjunction with the Apps
Processor to wake up the device following a headphone jack-detection event.
An SPI master interface is incorporated, enabling autonomous boot-up and configuration using an external non-volatile
memory (e.g., EEPROM or flash memory). Versatile GPIO functionality is provided, including support for external
accessory/push-button detection inputs. The CS47L15 also provides comprehensive interrupt functions, with status
reporting.
4.1.1
Hi-Fi Audio Codec
The CS47L15 is a high-performance, low-power audio codec that uses a simple analog architecture. Three ADCs are
incorporated, with multiplexers to support up to five analog inputs. Three DACs are incorporated, with two being switchable
between the headphone and BTL-earpiece analog output paths.
Five analog inputs are provided (multiplexed into three input channels), supporting single-ended or differential input
modes. As many as four analog microphone connections can be supported; a separate analog input channel is provided
for use in speaker-protection applications. In differential input mode, SNR performance of 104 dB is supported (16 kHz
sample rate, i.e., wideband voice mode). The ADC input paths can be bypassed, supporting up to four channels of digital
(e.g., DMIC) input.
The analog outputs comprise a stereo headphone amplifier with ground-referenced output (30-mW per channel, 127 dB
SNR), a mono (BTL) earpiece driver, and a mono Class D speaker driver capable of delivering 2.5 W into a 4- load.
The CS47L15 output drivers are designed to support a range of different system architectures. Each output path supports
independent signal mixing, equalization, filtering, and gain controls. This allows each signal path to be individually tailored
for the load characteristics. All outputs have integrated pop and click suppression features.
The headphone and earpiece output drivers are ground-referenced, powered from an integrated charge pump, enabling
high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop
feedback is incorporated, providing rejection of noise on the ground connections. Full support for high definition audio is
provided throughout the entire signal chain from the digital audio interfaces through to the analog output.
The Class D speaker driver delivers excellent power efficiency. Speaker protection software is supported within the DSP
core, enabling maximum audio output without risk of damage to the external speaker. High PSRR, low leakage and
optimized supply voltage ranges enable powering from switching regulators or directly from the battery. Battery current
consumption is minimized across a wide variety of voice communication and multimedia playback use cases.
The CS47L15 is cost optimized for a wide range of mobile applications, and incorporates a mono Class D power amplifier.
For applications requiring more than one channel of power amplification (or when using the integrated Class D path to
drive a haptics actuator), the PDM output channels can be used to drive external PDM-input speaker drivers. The PDM
outputs can ease layout and electromagnetic compatibility by avoiding the need to run the Class D speaker output over a
long distance and across interconnects.
4.1.2
Digital Audio Core
The CS47L15 uses a core architecture based on all-digital signal routing, making digital audio effects available on all signal
paths, regardless of whether the source data input is analog or digital. The digital mixing desk allows different audio effects
to be applied simultaneously on many independent paths, while supporting a variety of sample rates. A soft mute/unmute
control ensures smooth transitions between use cases without interruption to other audio streams.
DS1137PP1
27
CS47L15
4.1 Overview
The CS47L15 digital core provides an extensive capability for programmable signal-processing algorithms. The
SoundClear suite of software algorithms enable advanced audio features, such as transmit (TX) path noise reduction,
AEC, wind-noise reduction, speech enhancement, karaoke, and other programmable filters. The DSP core is supported
by peripheral timer and event logging functions, which provide additional capability for signal-processing applications.
Audio enhancements such as DRC and MBC are also supported.
The CS47L15 is ideal for mobile telephony, providing enhanced voice communication quality for both near-end and far-end
users in a wide variety of applications. The SoundClear Control voice command recognition software is supported, for
low-power always-on features. Speaker Protection software is available, using analog or digital input paths to support
current monitoring in the speaker output—this allows the Class D output to be optimized for the operational limits of the
speaker, and enables maximum audio output while ensuring the loudspeakers are fully protected from damage.
The digital audio core incorporates a highly flexible digital mixing capability, including mixing between audio interfaces.
The CS47L15 performs multichannel full-duplex isochronous sample-rate conversion, providing use-case flexibility across
a broad range of system architectures. Automatic sample-rate detection is provided, enabling seamless wideband/
narrowband voice call handover.
DRC functions are available for optimizing audio signal levels. In playback modes, the DRC can be used to maximize
loudness, while limiting the signal level to avoid distortion, clipping, or battery droop, for high-power output drivers such as
speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable.
The five-band parametric EQ functions can be used to compensate for the frequency characteristics of the output
transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and
low-pass filters are also available for general filtering applications, such as removal of wind and other low-frequency noise.
4.1.3
Digital Interfaces
Three serial digital audio interfaces (AIFs) each support PCM, TDM, and I2S data formats for compatibility with most
industry-standard chipsets. AIF1 supports six input/output channels; AIF2 supports four input/output channels; AIF3
supports two input/output channels. Bidirectional operation at sample rates up to 192 kHz is supported.
Four digital PDM input channels are available (two stereo interfaces). The IN1 digital input path is suitable for use with
digital microphones, powered from the integrated MICBIAS power-supply regulator. Two PDM output channels are also
available (one stereo interface); these are typically used for external power amplifiers. The IN2 digital input (SPKRXDAT)
is synchronized to the PDM output interface, creating a bidirectional audio interface suitable for speaker-protection
algorithms, using digital feedback from the external amplifier.
An IEC-60958-3–compatible S/PDIF transmitter is incorporated, enabling stereo S/PDIF output on a GPIO pin. Standard
S/PDIF sample rates of 32–192 kHz are supported.
Control register access and high bandwidth data transfer are supported by a slave SPI/I2C control interface. The slave
interface operates up to 26 MHz in SPI Mode, or up to 3.4 MHz in I2C Mode. The CS47L15 also supports an SPI master
interface that can be used to download firmware and register-configuration data from an external non-volatile memory
(e.g., EEPROM or flash memory).
4.1.4
Other Features
The CS47L15 supports autonomous boot-up and configuration from an external non-volatile memory. This enables the
device to self-boot to an application-specific configuration and to be used independently of a host processor. The interface
to the external memory is supported via the CS47L15 control interface, operating in SPI Master Mode.
The CS47L15 incorporates two 1-kHz tone generators that can be used for beep functions through any of the audio signal
paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential
signals, or for test scenarios.
A white-noise generator is provided that can be routed within the digital core. The noise generator can provide comfort
noise in cases where silence (digital mute) is not desirable.
Two pulse-width modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be
modulated by an audio source or can be set to a fixed value using a control register setting. The PWM signal generators
can be output directly on a GPIO pin.
28
DS1137PP1
CS47L15
4.2 Input Signal Path
The CS47L15 supports up to 15 GPIO pins, offering a range of input/output functions for interfacing, for detection of
external hardware, and for providing logic outputs to other devices. The GPIOs are multiplexed with other functions.
Comprehensive interrupt functionality is also provided for monitoring internal and external event conditions.
A signal generator for controlling haptics devices is included, compatible with both eccentric rotating mass (ERM) and
linear resonant actuator (LRA) haptics devices. The haptics signal generator is highly configurable and can execute
programmable drive event profiles, including reverse drive control. An external vibe actuator can be driven directly by the
Class D speaker output.
A smart accessory interface is included, supporting most standard 3.5-mm accessories. Jack detection, accessory
sensing, and impedance measurement is provided, for external accessory and push-button detection. Accessory detection
can be used as a wake-up trigger from low-power standby. Microphone activity detection with interrupt is also available.
System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the audio interfaces (configured in
Slave Mode), can be used to provide a clock reference. The CS47L15 also provides two integrated FLL circuits for clock
frequency conversion and stability. The flexible clocking architecture supports low-power always-on operation, with
reference frequencies down to 32 kHz. Seamless switching between clock sources is supported; free-running FLL modes
are also available.
The CS47L15 can be powered from 1.8- and 1.2-V external supplies. Separate MICVDD input can be supported (up to
3.6 V), for microphone operation above 1.8 V. A separate supply (4.2 V) is typically required for the Class D speaker
driver.
4.2 Input Signal Path
The CS47L15 provides flexible input channels, supporting up to five analog inputs or up to four digital inputs. Selectable
combinations of analog (mic or line) and digital inputs are multiplexed into two stereo input signal paths.
The IN1 signal paths support high performance analog and digital input modes. The analog paths support single-ended
and differential input, programmable gain control, and are digitized using a high performance sigma-delta ADCs. The IN1
analog input paths can be configured for low-power operation, ideal for always-on applications. The digital paths connect
directly to external digital microphones; the two-wire digital interface incorporates a dedicated clock source and supports
stereo microphone operation.
The IN2 signal paths can be configured for analog or digital input modes. Mono analog (differential) input is supported; the
analog configuration is optimized for low power operation and is ideally suited as an input path for speaker-protection
applications. Stereo digital input can also be supported on the SPKRXDAT pin; the respective data input is synchronized
with the digital speaker (PDM) output interface—these signal paths provide a bidirectional interface to an external speaker
driver.
The microphone bias (MICBIAS) generator provides a low-noise reference for biasing electret condenser microphones
(ECMs) or for use as a low-noise supply for MEMS microphones and digital microphones. Switchable outputs from the
MICBIAS generator allows three separate reference/supply outputs to be independently controlled.
Digital volume control is available on all inputs (analog and digital), with programmable ramp control for smooth, glitch-free
operation. A configurable signal-detect function is available on each input signal path.
The IN1 and IN2 signal paths and control fields are shown in Fig. 4-2.
DS1137PP1
29
CS47L15
4.2 Input Signal Path
IN1BLP
-
IN1BLN
IN1 L_SRC
00 = Differential IN1ALP – IN1ALN
01 = Single -ended IN1ALP (non -inverting)
10 = Differential IN1BLP – IN1BLN
11 = Single -ended IN1BLP (non -inverting)
IN1ALN/DMICCLK
Digital Core
IN_HPF_ CUT
IN1_MODE
ADC
IN1L input
+
IN1ALP/DMICDAT
IN1L _PGA _VOL [6:0 ]
IN1BRP
IN1L_ HPF
IN1 R_SRC
00 = Differential IN1ARP – IN1ARN
01 = Single -ended IN1ARP (non -inverting)
10 = Differential IN1BRP – IN1BRN
11 = Single -ended IN1BRP (non -inverting)
-
IN1BRN
IN_VD_RAMP
IN_VI_RAMP
IN1ARN
IN1L_ VOL
IN1L_ MUTE
IN1 L_ENA
ADC
IN1R input
+
IN1ARP
IN1R_PGA _VOL
DAT
IN1R_HPF
IN1 R_ ENA
Digital Mic
Interface
CLK
IN1R_VOL
IN1R_MUTE
IN1 _OSR
IN1 _DMIC_SUP
IN2_MODE
IN2N
ADC
IN2P
IN2L input
+
IN2L_ HPF
IN2L_ VOL
IN2L_ MUTE
IN2 L_ENA
SPKRXDAT
DAT
CLK
Digital Mic
Interface
IN2 _OSR
IN2R input
IN2R_HPF
IN2R_VOL
IN2R_MUTE
IN2 R_ ENA
SPKCLK timing signal from PDM output path
Figure 4-2. Input Signal Paths
4.2.1
Analog Microphone Input
Up to four analog microphones can be connected to the CS47L15, in single-ended or differential configuration. The input
configuration and pin selection for the IN1 signal paths is controlled using IN1x_SRC, as described in Section 4.2.7.
Note:
The IN2 analog input path is optimized for supporting speaker-protection applications. It is not suitable for
connection to microphones.
The CS47L15 includes external accessory-detection circuits that can report the presence of a microphone and the status
of a hook switch or other push buttons. When using this function, it is recommended to use the IN1BLP or IN1BRP analog
microphone input paths to ensure best immunity to electrical transients arising from the push buttons.
For single-ended input, the microphone signal is connected to the noninverting input of the PGAs (IN1xP). The inverting
inputs of the PGAs are connected to an internal reference in this configuration.
For differential input, the noninverted microphone signal is connected to the noninverting input of the PGAs (IN1xP), while
the inverted (or noisy ground) signal is connected to the inverting input pins (IN1xN).
30
DS1137PP1
CS47L15
4.2 Input Signal Path
Note:
Pseudodifferential connection is also possible—this is similar to the configuration shown in Fig. 4-4, but the GND
connection is directly to the microphone (and IN1xN capacitor), instead of via a resistor. This is the recommended
configuration if the external accessory detection functions on the CS47L15 are used. The IN1x_SRC field settings
are the same for pseudodifferential connection as for differential.
The gain of the IN1 signal path PGAs is controlled via register settings, as defined in Section 4.2.7. Note that the input
impedance of the analog input paths is fixed across all PGA gain settings.
The ECM analog input configurations are shown in Fig. 4-3 and Fig. 4-4. The integrated MICBIAS generator provides a
low noise reference for biasing the ECMs.
MICBIAS
MICBIAS
IN1xP
IN1xP
+
PGA
–
ECM
IN1xN
+
PGA
–
ECM
To ADC
IN1xN
To ADC
GND
VREF
VREF
GND
Figure 4-3. Single-Ended ECM Input
Figure 4-4. Differential ECM Input
Analog MEMS microphones can be connected to the CS47L15 in a similar manner to the ECM configurations. Typical
configurations are shown in Fig. 4-5 and Fig. 4-6. In this configuration, the integrated MICBIAS generator provides a
low-noise power supply for the microphones.
MICBIAS
MICBIAS
VDD
MEMS
Mic
IN1xP
IN1xP
OUT
GND
IN1xN
+
PGA
–
GND
VREF
Figure 4-5. Single-Ended MEMS Input
Note:
4.2.2
To ADC
MEMS
Mic
VDD
OUT-P
OUT-N
GND
GND
IN1xN
+
PGA
–
To ADC
VREF
Figure 4-6. Differential MEMS Input
It is also possible to use the MICVDD pin (instead of MICBIAS) as a reference or power supply for external
microphones; the MICBIAS outputs are preferred because they offer better noise performance and independent
enable/disable control.
Analog Line Input
Line input signals can be connected to the CS47L15 in a similar manner to the mic inputs.
Single-ended and differential configurations are supported on the IN1 pins, using the IN1x_SRC bits as described in
Section 4.2.7. The IN1 analog line input configurations are shown in Fig. 4-7 and Fig. 4-8. Note that the microphone bias
(MICBIAS) is not used for line input connections.
The gain of the IN1 signal path PGAs is controlled via register settings, as defined in Section 4.2.7. Note that the input
impedance of the analog input paths is fixed across all PGA gain settings.
DS1137PP1
31
CS47L15
4.2 Input Signal Path
IN1xP
IN1xP
Line
Line
IN1xN
+
PGA
–
To ADC
IN1xN
+
PGA
–
To ADC
GND
VREF
VREF
Figure 4-7. Single-Ended Line Input
Figure 4-8. Differential Line Input
The IN2 analog input path supports differential connection only, as shown in Fig. 4-2. The IN2 analog line input
configuration is shown in Fig. 4-9. The gain of the IN2 signal path PGA is fixed at 14 dB.
Note that IN2 analog input supports ground-referenced input signals only. Input capacitors must not be used on the IN2x
pins.
IN2P
Line
IN2N
+
PGA
–
To ADC
VREF
Figure 4-9. Differential Line Input
4.2.3
Analog Input—Speaker Current Monitoring
The IN2 analog input path is optimized for supporting speaker-protection applications. In these applications, the IN2 pins
are used to provide feedback from current-monitoring connections on the Class D speaker outputs. Speaker-protection
software, running on the integrated DSP core, enables the operational limits to be continually optimized for the particular
loudspeaker and the prevailing conditions.
Typical connections for speaker-protection applications, including the analog feedback path to the IN2 pins, are shown in
Fig. 4-10.
32
DS1137PP1
CS47L15
4.2 Input Signal Path
CS47L15
SPKOUTP
SPKOUTN
IN2P
IN2N
SPKGNDP
SPKGNDN
0.1
(1%, 100ppm/°C)
Figure 4-10. Speaker Current Monitoring Connection
See Section 4.8 for the details of the Class D speaker output.
4.2.4
Digital Input
The CS47L15 input signal paths support up to four channels of digital input—the IN1 and IN2 paths each support two
digital input channels. Digital operation on input paths IN1 and IN2 is selected using INn_MODE, as described in
Section 4.2.7.
The IN1 (DMICDAT) and IN2 (SPKRXDAT) digital paths are described in Section 4.2.4.1 and Section 4.2.4.2 respectively.
4.2.4.1 IN1 Digital Input (DMICDAT)
The IN1 digital input path is designed to support digital microphone (DMIC) operation. In DMIC mode, two channels of
audio data are multiplexed on the DMICDAT pin. If a DMIC input path is enabled, the CS47L15 outputs a clock signal on
the DMICCLK pin—this is the timing reference for the DMICDAT input. The DMICCLK frequency is controlled by the IN1_
OSR field, as described in Table 4-1 and Table 4-4.
Note that, if the 384- or 768-kHz DMICCLK frequency is selected for the DMIC input path, the maximum valid input path
sample rate (all input paths) is restricted as described in Table 4-1.
The system clock, SYSCLK, must be present and enabled when using the DMICDAT input channels; see Section 4.13 for
details regarding SYSCLK and the associated registers.
The DMICCLK frequencies in Table 4-1 assume that the SYSCLK frequency is a multiple of 6.144 MHz (SYSCLK_
FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the DMICCLK frequencies are
scaled accordingly.
Table 4-1. DMICCLK Frequency
Condition
IN1_OSR = 010
IN1_OSR = 011
IN1_OSR = 100
IN1_OSR = 101
IN1_OSR = 110
DMICCLK Frequency
384 kHz
768 kHz
1.536 MHz
3.072 MHz
6.144 MHz
Valid Sample Rates
Up to 48 kHz
Up to 96 kHz
Up to 192 kHz
Up to 192 kHz
Up to 192 kHz
Signal Passband
Up to 4 kHz
Up to 8 kHz
Up to 20 kHz
Up to 20 kHz
Up to 96 kHz
The voltage reference for the IN1 DMIC interface is selectable, using IN1_DMIC_SUP—the interface is referenced to
MICVDD or MICBIAS1. The voltage reference selection should be set equal to the power supply of the respective
microphones.
A pair of digital microphones is connected as shown in Fig. 4-11. The microphones must be configured to ensure that the
left mic transmits a data bit when DMICCLK is high and the right mic transmits a data bit when DMICCLK is low. The
CS47L15 samples the DMIC data at the end of each DMICCLK phase. Each microphone must tristate its data output when
the other microphone is transmitting.
DS1137PP1
33
CS47L15
4.2 Input Signal Path
Note that the CS47L15 provides an integrated pull-down resistor on the DMICDAT pin. This provides a flexible capability
for interfacing with other devices.
MICVDD or MICBIAS1x
DMICCLK
Digital
Microphone
Interface
DMICDAT
VDD
VDD
CLK DATA
VDD
Digital Mic
The DMIC inputs are referenced to
MICVDD or MICBIAS1.
CLK DATA
Digital Mic
The supply for each digital microphone
should provide the same voltage as the
applicable reference.
CHAN
CHAN
AGND
Figure 4-11. DMIC Input
Two DMIC channels are interleaved on DMICDAT. The DMIC interface timing is shown in Fig. 4-12. Each microphone
must tristate its data output when the other microphone is transmitting. See Table 3-14 for a detailed timing specification
of the DMIC interface.
DMICCLK pin
Hi-Z
Left mic output
1
2
Right mic output
DMICDAT pin
(Left and right channels interleaved)
1
1
2
1
2
1
2
2
1
2
Figure 4-12. DMIC Interface Timing
4.2.4.2 IN2 Digital Input (SPKRXDAT)
The IN2 digital input path forms part of a bidirectional interface for external speaker drivers. If the IN2 path is configured
for digital input, two channels of audio data are multiplexed on the SPKRXDAT pin. A timing reference signal is provided
on the SPKCLK pin, which is common to the input (SPKRXDAT) and output (SPKTXDAT) paths of the digital speaker
(PDM) interface.
The SPKCLK frequency is controlled using the OUT5_OSR field, as described in Table 4-55. The input signal timing is
controlled by the IN2_OSR field—this field must be configured for the same frequency as the OUT5_OSR field.
34
DS1137PP1
CS47L15
4.2 Input Signal Path
The system clock, SYSCLK, must be present and enabled when using the SPKRXDAT input channels; see Section 4.13
for details regarding SYSCLK and the associated registers.
The SPKCLK frequencies in Table 4-2 assume that the SYSCLK frequency is a multiple of 6.144 MHz (SYSCLK_
FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the SPKCLK frequencies are
scaled accordingly.
Table 4-2. SPKCLK Frequency
Condition
SPKCLK Frequency
Valid Sample Rates
Signal Passband
IN2_OSR = 101
3.072 MHz
Up to 192 kHz
Up to 20 kHz
IN2_OSR = 110
6.144 MHz
Up to 192 kHz
Up to 96 kHz
Note: The SPKCLK frequency is controlled by the OUT5_OSR field (see Table 4-55). The descriptions shown here assume that
the IN2_OSR and OUT5_OSR fields are configured for the same frequency.
The voltage reference for the IN2 digital input is DBVDD—this is the same voltage reference as the output pins of the digital
speaker (PDM) interface.
Typical connections for an external speaker driver, incorporating the IN2 digital input (SPKRXDAT) path, are shown in
Fig. 4-13. The left channel data is received when SPKCLK is high and the right channel data is received when SPKCLK
is low. The CS47L15 samples the data at the end of each SPKCLK phase.
Note that the CS47L15 provides integrated pull-up and pull-down resistors on the SPKRXDAT pin. This provides a flexible
capability for interfacing with other devices.
CS47L15
SPKCLK
SPKTXDAT
Speaker Driver
SPKRXDAT
Figure 4-13. Digital Speaker (PDM) Connection with Feedback
The IN2 digital interface timing is similar to the DMIC timing shown in Fig. 4-12, with two audio channels interleaved on
SPKRXDAT. See Table 3-14 for a detailed timing specification of the SPKRXDAT digital input.
4.2.5
Input Signal Path Enable
The input signal paths are enabled using the bits described in Table 4-3. The respective bits must be enabled for analog
or digital input on the respective input paths.
The input signal paths are muted by default. It is recommended that deselecting the mute should be the final step of the
path enable control sequence. Similarly, the mute should be selected as the first step of the path-disable control sequence.
The input signal path mute functions are controlled using the bits described in Table 4-6.
The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. See Section 4.13 for
details of the system clocks.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input signal
paths and associated ADCs. If the frequency is too low, an attempt to enable an input signal path fails. Note that active
signal paths are not affected under such circumstances.
The status bits in Register R769 indicate the status of each of the input signal paths. If an underclocked error condition
occurs, these bits indicate which input signal paths have been enabled.
DS1137PP1
35
CS47L15
4.2 Input Signal Path
Table 4-3. Input Signal Path Enable
Register Address
R768 (0x0300)
Input_Enables
R769 (0x0301)
Input_Enables_Status
4.2.6
Bit
3
Label
IN2L_ENA
Default
0
2
IN2R_ENA
0
1
IN1L_ENA
0
0
IN1R_ENA
0
3
IN2L_ENA_STS
0
2
IN2R_ENA_STS
0
1
IN1L_ENA_STS
0
0
IN1R_ENA_STS
0
Description
Input Path 2 (left) enable
0 = Disabled
1 = Enabled
Input Path 2 (right) enable
0 = Disabled
1 = Enabled
Input Path 1 (left) enable
0 = Disabled
1 = Enabled
Input Path 1 (right) enable
0 = Disabled
1 = Enabled
Input Path 2 (left) enable status
0 = Disabled
1 = Enabled
Input Path 2 (right) enable status
0 = Disabled
1 = Enabled
Input Path 1 (left) enable status
0 = Disabled
1 = Enabled
Input Path 1 (right) enable status
0 = Disabled
1 = Enabled
Input Signal Path Sample-Rate Control
The input signal paths may be selected as input to the digital mixers or signal-processing functions within the CS47L15
digital core. The sample rate for the input signal paths is configured using IN_RATE; see Table 4-24.
Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is configured for
a different sample rate.
4.2.7
Input Signal Path Configuration
The CS47L15 supports up to five analog inputs or up to four digital inputs. Selectable combinations of analog (mic or line)
and digital inputs are multiplexed into two stereo input signal paths, as illustrated in Fig. 4-2.
•
Input path IN1 can be configured for single-ended, differential, or digital operation. The analog input configuration
and pin selection is controlled using the IN1x_SRC bits; digital input mode is selected by setting IN1_MODE.
If digital input is selected, the IN1_DMICCLK_SRC field must be 00. Under default conditions, this field is locked
and cannot be written. To change the value of this field, the user key must be set before writing to IN1_DMICCLK_
SRC. It is recommended to clear the user key after writing to IN1_DMICCLK_SRC. See Table 4-105 for details of
the user key control register.
•
Input path IN2 can be configured for differential or digital operation. The analog mode supports mono, differential
connection only; stereo digital input is selected by setting IN2_MODE.
If analog input is selected (IN2_MODE=0), the IN2L_LP_MODE bit must be set. If digital input is selected (IN2_
MODE=1), the IN2L_LP_MODE must be cleared.
A configurable high-pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off
frequency is selected using IN_HPF_CUT. The filter can be enabled on each path independently using the INnx_HPF bits.
The IN1 analog input paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0 dB to
+31 dB in 1-dB steps. Note that these PGAs do not provide pop suppression functions; it is recommended that the gain
should not be adjusted while the respective signal path is enabled. The analog input PGA gain is controlled using IN1L_
PGA_VOL and IN1R_PGA_VOL.
36
DS1137PP1
CS47L15
4.2 Input Signal Path
The IN1 analog input paths can be configured for low-power operation, ideal for always-on applications. If the IN1 signal
path is configured for analog input, low-power operation can be selected as described in Section 4.2.7.1.
The IN2 analog input path supports mono input only. The IN2 analog input PGA gain is fixed at 14 dB.
If the IN1 input signal path is configured for digital (DMIC) input, the voltage reference for the DMICDAT/DMICCLK pins is
selectable using IN1_DMIC_SUP; the interface is referenced to MICVDD or MICBIAS1. The voltage reference selection
controls the digital logic thresholds for the DMICDAT/DMICCLK pins (see Table 3-10)—it should be set equal to the
applicable power supply of the respective microphones.
If the IN1 input signal path is configured for digital input, the DMICCLK frequency can be configured using the IN1_OSR
field.
If the IN2 input signal path is configured for digital input, the interface clocking frequency is configured using the IN2_OSR
field. The IN2_OSR field must select the same frequency as the OUT5_OSR bit (see Table 4-55).
The input signal paths are configured using the fields described in Table 4-4.
Table 4-4. Input Signal Path Configuration
Register Address
R780 (0x030C)
HPF_Control
R784 (0x0310)
IN1L_Control
R785 (0x0311)
ADC_Digital_
Volume_1L
R786 (0x0312)
DMIC1L_Control
R788 (0x0314)
IN1R_Control
R789 (0x0315)
ADC_Digital_
Volume_1R
DS1137PP1
Bit
2:0
Label
IN_HPF_
CUT[2:0]
Default
Description
010 Input Path HPF Select. Controls the cut-off frequency of the input path HPF circuits.
000 = 2.5 Hz
010 = 10 Hz
100 = 40 Hz
001 = 5 Hz
011 = 20 Hz
All other codes are reserved
15 IN1L_HPF
0
Input Path 1 (Left) HPF Enable
0 = Disabled
1 = Enabled
12:11 IN1_DMIC_
00
Input Path 1 DMIC Reference Select (sets the DMICDAT and DMICCLK logic levels)
SUP[1:0]
00 = MICVDD
All other codes are reserved
01 = MICBIAS1
10 IN1_MODE
0
Input Path 1 Mode
0 = Analog input
1 = Digital input
7:1 IN1L_PGA_ 0x40 Input Path 1 (Left) PGA Volume (applicable to analog inputs only)
VOL[6:0]
0x60 to 0x7F = Reserved
0x00 to 0x3F = Reserved
0x42 = 2 dB
… (1-dB steps)
0x40 = 0 dB
0x5F = 31 dB
0x41 = 1 dB
14:13 IN1L_
00
Input Path 1 (Left) Source
SRC[1:0]
00 = Differential (IN1ALP–IN1ALN)
10 = Differential (IN1BP–IN1BN)
01 = Single-ended (IN1ALP)
11 = Single-ended (IN1BP)
10:8 IN1_
101 Input Path 1 Oversample Rate Control
OSR[2:0]
If analog input is selected, this field must be set to 101 (default).
If digital input is selected, this field controls the DMICCLK frequency.
010 = 384 kHz
100 = 1.536 MHz
110 = 6.144 MHz
011 = 768 kHz
101 = 3.072 MHz
All other codes are reserved
15 IN1R_HPF
0
Input Path 1 (Right) HPF Enable
0 = Disabled
1 = Enabled
12:11 IN1_
01
Input Path 1 DMIC Clock Source
DMICCLK_
00 = DMICCLK1
SRC[1:0]
All other codes are reserved.
If digital input is selected, this field must be 00. Under default conditions, this field is locked
and cannot be written. To change the value of this field, the user key must be set before
writing to IN1_DMICCLK_SRC.
7:1 IN1R_PGA_ 0x40 Input Path 1 (Right) PGA Volume (applicable to analog inputs only)
VOL[6:0]
0x00 to 0x3F = Reserved
0x42 = 2 dB
0x60 to 0x7F = Reserved
0x40 = 0 dB
… (1-dB steps)
0x41 = 1 dB
0x5F = 31 dB
14:13 IN1R_
00
Input Path 1 (Right) Source
SRC[1:0]
00 = Differential (IN1ARP–IN1ARN)
10 = Differential (IN1BRP–IN1BRN)
01 = Single-ended (IN1ARP)
11 = Single-ended (IN1BRP)
37
CS47L15
4.2 Input Signal Path
Table 4-4. Input Signal Path Configuration (Cont.)
Register Address
R792 (0x0318)
IN2L_Control
R793 (0x0319)
ADC_Digital_
Volume_2L
R794 (0x031A)
DMIC2L_Control
R796 (0x031C)
IN2R_Control
Bit
15
Label
IN2L_HPF
10
IN2_MODE
11
IN2L_LP_
MODE
10:8 IN2_
OSR[2:0]
15
IN2R_HPF
Default
Description
0
Input Path 2 (Left) HPF Enable
0 = Disabled
1 = Enabled
0
Input Path 2 Mode
0 = Analog input
1 = Digital input
1
Input Path 2 (Left) control
If IN2_MODE = 0 (analog input), the IN2L_LP_MODE bit must be set.
If IN2_MODE = 1 (digital input), the IN2L_LP_MODE bit must be cleared.
101 Input Path 2 Oversample Rate Control
If analog input is selected, this field must be set to 101 (default).
If digital input is selected, this field must be set to the same frequency as OUT5_OSR.
101 = 3.072 MHz
All other codes are reserved
110 = 6.144 MHz
0
Input Path 2 (Right) HPF Enable
0 = Disabled
1 = Enabled
4.2.7.1 IN1 Low-Power Mode Configuration
The IN1 input path supports low-power operation for analog input configurations. Note that, although the IN1L and IN1R
signal paths can be enabled/disabled independently, the selection of Low-Power Mode is common to both channels.
The required register settings for selecting/deselecting Low-Power Mode are described in Table 4-5.
Table 4-5. IN1 Low-Power Mode Control Sequences
IN1 Low-Power Configuration
• Write 100 to address 0x312, bits [10:8]
• Write 001 to address 0x3A8, bits [13:11]
• Write 11 to address 0x3C4, bits [1:0]
4.2.8
IN1 Normal (High-Performance) Configuration
• Write 101 to address 0x312, bits [10:8]
• Write 100 to address 0x3A8, bits [13:11]
• Write 00 to address 0x3C4, bits [1:0]
Input Signal Path Digital Volume Control
A digital volume control is provided on each input signal path, providing –64 dB to +31.5 dB gain control in 0.5-dB steps.
An independent mute control is also provided for each input signal path.
Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a
programmable rate. For increasing gain (or unmute), the rate is controlled by IN_VI_RAMP. For decreasing gain (or mute),
the rate is controlled by IN_VD_RAMP.
Note:
The IN_VI_RAMP and IN_VD_RAMP fields should not be changed while a volume ramp is in progress.
The IN_VU bits control the loading of the input signal path digital volume and mute controls. When IN_VU is cleared, the
digital volume and mute settings are loaded into the respective control register, but do not change the signal path gain.
The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes
it possible to update the gain of multiple signal paths simultaneously.
Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in
0.125-dB steps. This allows a very high degree of gain control and smooth volume ramping under all operating conditions.
Note:
The 0 dBFS level of the IN1/IN2 digital input paths is not equal to the 0 dBFS level of the CS47L15 digital core.
The maximum digital input signal level is –6 dBFS (see Table 3-7). Under 0 dB gain conditions, a –6 dBFS input
signal corresponds to a 0 dBFS input to the CS47L15 digital core functions.
The digital volume control registers are described in Table 4-6 and Table 4-7.
38
DS1137PP1
CS47L15
4.2 Input Signal Path
Table 4-6. Input Signal Path Digital Volume Control
Register Address
R777 (0x0309)
Input_Volume_
Ramp
R785 (0x0311)
ADC_Digital_
Volume_1L
Bit
6:4
Label
IN_VD_RAMP[2:0]
Default
010
2:0
IN_VI_RAMP[2:0]
010
9
IN_VU
8
IN1L_MUTE
7:0
R789 (0x0315)
ADC_Digital_
Volume_1R
R793 (0x0319)
ADC_Digital_
Volume_2L
IN_VU
8
IN1R_MUTE
IN_VU
8
IN2L_MUTE
See
Footnote 1
1
0x80
See
Footnote 1
1
IN2L_VOL[7:0]
9
IN_VU
8
IN2R_MUTE
7:0
0x80
IN1R_VOL[7:0]
9
7:0
R797 (0x031D)
ADC_Digital_
Volume_2R
IN1L_VOL[7:0]
9
7:0
See
Footnote 1
1
0x80
See
Footnote 1
1
IN2R_VOL[7:0]
0x80
Description
Input Volume Decreasing Ramp Rate (seconds/6 dB)
This field should not be changed while a volume ramp is in progress.
000 = 0 ms
011 = 2 ms
110 = 15 ms
001 = 0.5 ms
100 = 4 ms
111 = 30 ms
010 = 1 ms
101 = 8 ms
Input Volume Increasing Ramp Rate (seconds/6 dB)
This field should not be changed while a volume ramp is in progress.
000 = 0 ms
011 = 2 ms
110 = 15 ms
001 = 0.5 ms
100 = 4 ms
111 = 30 ms
010 = 1 ms
101 = 8 ms
Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input
Signal Paths Volume and Mute settings to be updated simultaneously
Input Path 1 (Left) Digital Mute
0 = Unmute
1 = Mute
Input Path 1 (Left) Digital Volume (see Table 4-7 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
… (0.5-dB steps)
0x01 = –63.5dB
0xBF = +31.5 dB
… (0.5-dB steps)
Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input
Signal Paths Volume and Mute settings to be updated simultaneously
Input Path 1 (Right) Digital Mute
0 = Unmute
1 = Mute
Input Path 1 (Right) Digital Volume (see Table 4-7 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input
Signal Paths Volume and Mute settings to be updated simultaneously
Input Path 2 (Left) Digital Mute
0 = Unmute
1 = Mute
Input Path 2 (Left) Digital Volume (see Table 4-7 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input
Signal Paths Volume and Mute settings to be updated simultaneously
Input Path 2 (Right) Digital Mute
0 = Unmute
1 = Mute
Input Path 2 (Right) Digital Volume (see Table 4-7 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
1. Default is not applicable to these write-only bits
Table 4-7 lists the input signal path digital volume settings.
DS1137PP1
39
CS47L15
4.2 Input Signal Path
Table 4-7. Input Signal Path Digital Volume Range
Input Volume
Register
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
40
Volume (dB)
–64.0
–63.5
–63.0
–62.5
–62.0
–61.5
–61.0
–60.5
–60.0
–59.5
–59.0
–58.5
–58.0
–57.5
–57.0
–56.5
–56.0
–55.5
–55.0
–54.5
–54.0
–53.5
–53.0
–52.5
–52.0
–51.5
–51.0
–50.5
–50.0
–49.5
–49.0
–48.5
–48.0
–47.5
–47.0
–46.5
–46.0
–45.5
–45.0
–44.5
–44.0
–43.5
–43.0
–42.5
–42.0
–41.5
–41.0
–40.5
–40.0
Input Volume
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
Volume (dB)
–39.5
–39.0
–38.5
–38.0
–37.5
–37.0
–36.5
–36.0
–35.5
–35.0
–34.5
–34.0
–33.5
–33.0
–32.5
–32.0
–31.5
–31.0
–30.5
–30.0
–29.5
–29.0
–28.5
–28.0
–27.5
–27.0
–26.5
–26.0
–25.5
–25.0
–24.5
–24.0
–23.5
–23.0
–22.5
–22.0
–21.5
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–17.5
–17.0
–16.5
–16.0
–15.5
Input Volume
Register
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
Volume (dB)
–15.0
–14.5
–14.0
–13.5
–13.0
–12.5
–12.0
–11.5
–11.0
–10.5
–10.0
–9.5
–9.0
–8.5
–8.0
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
Input Volume
Register
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0–0xFF
Volume (dB)
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
Reserved
DS1137PP1
CS47L15
4.2 Input Signal Path
4.2.9
Input Signal Path Signal-Detect Control
The CS47L15 provides a digital signal-detect function for the input signal path. This enables system actions to be triggered
by signal detection and allows the device to remain in a low-power state until a valid audio signal is detected. A mute
function is integrated with the signal-detect circuit, ensuring the respective digital audio path remains at zero until the
detection threshold level is reached. Signal detection is also indicated via the interrupt controller.
The signal-detect function is supported on input paths IN1 and IN2 in analog and digital configurations (digital input is
selected by setting the respective INn_MODE bit). Note that the valid operating conditions for this function vary, depending
on the applicable signal-path configuration.
•
The signal-detect function is supported on analog input paths for sample rates up to 16 kHz.
•
The signal-detect function is supported on digital input paths for sample rates up to 48 kHz.
For each input path, the signal-detect function is enabled by setting the respective INnx_SIG_DET_ENA bit. The detection
threshold level is set using IN_SIG_DET_THR—this applies to all input paths.
If the signal-detect function is enabled, the respective input channel is muted if the signal level is below the configured
threshold. If the input signal exceeds the threshold level, the respective channel is immediately unmuted.
If the input signal falls below the threshold level, the mute is applied. To prevent erroneous behavior, a time delay is applied
before muting the input signal—the channel is only muted if the signal level remains below the threshold level for longer
than the hold time. The hold time is set using IN_SIG_DET_HOLD.
Note that the signal-level detection is performed in the digital domain, after the ADC, PGA, digital mute and digital volume
controls—the respective input channel must be enabled and unmuted when using the signal-detect function.
The signal-detect function is an input to the interrupt control circuit and can be used to trigger an interrupt event; see
Section 4.12. Note that the respective interrupt event represents the logic OR of the signal detection on all input channels
and does not provide indication of which input channel caused the interrupt. To avoid multiple interrupts, the signal-detect
interrupt can be reasserted only after all input channels have fallen below the trigger threshold level.
The input path signal-detection control registers are described in Table 4-8.
Table 4-8. Input Signal Path Signal-Detect Control
Register Address
R786 (0x0312)
DMIC1L_Control
Bit
15
Label
IN1L_SIG_DET_
ENA
R790 (0x0316)
DMIC1R_Control
15
IN1R_SIG_DET_
ENA
R794 (0x031A)
DMIC2L_Control
15
IN2L_SIG_DET_
ENA
R798 (0x031E)
DMIC2R_Control
15
IN2R_SIG_DET_
ENA
R832 (0x0340)
Signal_Detect_Globals
8:4
IN_SIG_DET_
THR[4:0]
3:0
IN_SIG_DET_
HOLD[3:0]
DS1137PP1
Default
Description
0
Input Path 1 (Left) Signal-Detect Enable
0 = Disabled
1 = Enabled
0
Input Path 1 (Right) Signal-Detect Enable
0 = Disabled
1 = Enabled
0
Input Path 2 (Left) Signal-Detect Enable
0 = Disabled
1 = Enabled
0
Input Path 2 (Right) Signal-Detect Enable
0 = Disabled
1 = Enabled
0x00 Input Signal Path Signal-Detect Threshold
0x05 = –54.2 dB
0x0A = –72.2 dB
0x00 = –30.1 dB
0x0B = –74.7 dB
0x01 = –36.1 dB
0x06 = –56.7 dB
0x07 = –60.2 dB
0x0C = –78.3 dB
0x02 = –42.1 dB
0x08 = –66.2 dB
0x0D = –80.8 dB
0x03 = –48.2 dB
0x04 = –50.7 dB
0x09 = –68.7 dB
All other codes are reserved
0001 Input Signal Path Signal-Detect Hold Time (delay before signal detect indication
is deasserted)
0000 = Reserved
... (4-ms steps)
1100 = 96–100 ms
0001 = 4–8 ms
1001 = 36–40 ms
1101 = 192–196 ms
0010 = 8–12 ms
1010 = 40–44 ms
1110 = 384–388 ms
0011 = 12–16 ms
1011 = 48–52 ms
1111 = 768–772 ms
41
CS47L15
4.3 Digital Core
4.2.10 Digital Input (DMICDAT/SPKRXDAT) Pin Configuration
DMIC operation on the IN1 input path is selected using IN1_MODE, as described in Table 4-4. If DMIC is selected, the
DMICCLK and DMICDAT pins are configured as digital output and input, respectively.
The CS47L15 provides an integrated pull-down resistor on the DMICDAT pin; this provides a flexible capability for
interfacing with other devices. The DMICDAT pull-down resistor can be configured using the DMICDAT1_PD bit, as
described in Table 4-9. Note that, if the IN1 DMIC input path is disabled, the pull-down is disabled on the DMICDAT pin.
Table 4-9. DMIC Interface Pull-Down Control
Register Address
R840 (0x0348)
Dig_Mic_Pad_Ctrl
Bit
0
Label
DMICDAT1_PD
Default
0
Description
DMICDAT1 Pull-Down Control
0 = Disabled
1 = Enabled
The SPKRXDAT function is implemented on the SPKRXDAT/GPIO15 pin, which must be configured for digital audio input
function when required. See Section 4.11 to configure the pin for SPKRXDAT operation.
Integrated pull-up and pull-down resistors can be enabled on the SPKRXDAT pin. This is provided as part of the GPIO
functionality, and provides a flexible capability for interfacing with other devices. The pull-up and pull-down resistors can
be configured independently using the fields described in Table 4-72.
If the pull-up and pull-down resistors are both enabled, the CS47L15 provides a bus keeper function on the SPKRXDAT
pin. The bus-keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated).
4.3 Digital Core
The CS47L15 digital core provides extensive mixing and processing capabilities for multiple signal paths. The
configuration is highly flexible, and virtually every conceivable input/output connection can be supported between the
available processing blocks.
The digital core provides parametric equalization (EQ) functions, DRC, low-/high-pass filters (LHPF), and programmable
DSP capability. The DSP can support functions such as wind-noise, side-tone, or other programmable filters, also dynamic
range control and compression, or virtual surround sound and other audio enhancements.
The CS47L15 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided
to allow digital audio to be routed between input (ADC/DMIC) paths, output (DAC) paths, and digital audio interfaces
(AIF1–AIF3) operating at different sample rates.
The DSP functions are highly programmable, using application-specific control sequences. Note that the DSP
configuration data is lost whenever the DCVDD power domain is removed; the DSP configuration data must be
downloaded to the CS47L15 each time the device is powered up.
The procedure for configuring the CS47L15 DSP functions is tailored to each customer’s application; please contact your
Cirrus Logic representative for more details.
The digital core incorporates a S/PDIF transmitter that can provide a stereo S/PDIF output on a GPIO pin. Standard
sample rates of 32–192 kHz can be supported. The CS47L15 incorporates a tone generator that can be used for beep
functions through any of the audio signal paths. A white-noise generator is incorporated, to provide comfort noise in cases
where silence (digital mute) is not desirable.
A haptic signal generator is provided, for use with external haptic devices (e.g., mechanical vibration actuators). Two
pulse-width modulation (PWM) signal generators are also provided; the PWM waveforms can be modulated by an audio
source within the digital core, and can be output on a GPIO pin.
An overview of the digital-core mixing and signal-processing functions is provided in Fig. 4-14.
The control registers associated with the digital-core signal paths are shown in Fig. 4-15 through Fig. 4-29. The full list of
digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are provided in
Table 4-10.
42
DS1137PP1
CS47L15
4.3 Digital Core
Silence (mute)
DSP1
AEC1 Loopback
AEC2 Loopback
DSP1 Channel 1
+
DSP1 Channel 2
IN1L signal path
DSP1 Channel 3
DSP Core
IN1R signal path
DSP1 Channel 4
IN2L signal path
+
DSP1 Channel 5
IN2R signal path
DSP1 Channel 6
ISRC2
ISRC1
ISRCn INT1
OUT5
OUT1
OUT4
ISRCn INT2
ISRCn INT3
ISRCn DEC1
Isochronous
Sample Rate
Converter (ISRC)
ISRCn INT4
+
Class D
Speaker
Output
Path
+
OUTnL output
Stereo
Output
Paths
OUT4 output
ISRCn DEC2
+
ISRCn DEC3
OUTnR output
ISRCn DEC4
PWM2
PWM1
+
PWM
(GPIO pin)
+
S/PDIF
(GPIO pin)
LHPF
+
EQ
+
+
EQn
+
+
DRCn
Left
Noise Generator
AIFn TX.. output
+
Tone Generator 1
AIFn TX.. output
etc...
DRC
Tone Generator
AIFn TX2 output
Haptic Output
DRC2
DRC1
White Noise
Generator
AIFn TX1 output
LHPFn
EQ4
EQ3
EQ2
EQ1
+
Haptic Signal
Generator
AIF3
AIF2
AIF1
LHPF4
LHPF3
LHPF2
LHPF1
AIFn RX1
DRCn
Right
AIF1 = 6 input , 6 output
AIF2 = 4 input , 4 output
AIF3 = 2 input , 2 output
AIFn RX2
AIFn RX..
AIFn RX..
Tone Generator 2
Figure 4-14. Digital Core
DS1137PP1
43
CS47L15
4.3 Digital Core
4.3.1
Digital-Core Mixers
The CS47L15 provides an extensive digital mixing capability. The digital-core mixing and signal-processing blocks are
shown in Fig. 4-14. A four-input digital mixer is associated with many of these functions, as shown. The digital mixer circuit
is identical in each instance, providing up to four selectable input sources, with independent volume control on each input.
The control registers associated with the digital-core signal paths are shown in Fig. 4-15–Fig. 4-29. The full list of digital
mixer control registers (R1600–R2936) is provided in Section 6.
Further description of the associated control registers is provided throughout Section 4.3. Generic register field definitions
are provided in Table 4-10.
The digital mixer input sources are selected using the associated x_SRCn fields; the volume control is implemented via
the associated x_VOLn fields.
The ISRC and DSP auxiliary input functions support selectable input sources, but do not incorporate any digital mixing.
The respective input source (x_SRCn) fields are identical to those of the digital mixers.
The x_SRCn fields select the input sources for the respective mixer or signal-processing block. Note that the selected input
sources must be configured for the same sample rate as the blocks to which they are connected. Sample-rate conversion
functions are available to support flexible interconnectivity; see Section 4.3.14.
A status bit is associated with each configurable input source. If an underclocked error condition occurs, these bits indicate
which signal paths have been enabled.
The generic register field definition for the digital mixers is provided in Table 4-10.
Table 4-10. Digital-Core Mixer Control Registers
Register Address
R1600 (0x0640)
to
R2936 (0x0B78)
44
Bit
Label
Default
Description
15 x_STSn
0
[Digital Core function] input n status
Valid for every digital
0 = Disabled
core function input
1 = Enabled
(digital mixers, DSP aux
inputs, and ISRC
inputs).
7:1 x_VOLn
0x40 [Digital Core mixer] input n volume. (–32 dB to +16 dB in 1-dB steps)
... (1-dB steps)
0x50 = +16 dB
Valid for every digital
0x00 to 0x20 = –32 dB
mixer input.
0x21 = –31 dB
0x40 = 0 dB
0x51 to 0x7F = +16 dB
0x22 = –30 dB
... (1-dB steps)
7:0 x_SRCn
0x00 [Digital Core function] input n source select
0x6B = DSP1 Channel 4
Valid for every digital
0x2A = AIF2 RX3
0x00 = Silence (mute)
core function input
0x6C = DSP1 Channel 5
0x04 = Tone generator 1 0x2B = AIF2 RX4
(digital mixers, DSP aux
0x6D = DSP1 Channel 6
0x05 = Tone generator 2 0x30 = AIF3 RX1
inputs, and ISRC
0xA0 = ISRC1 INT1
0x31 = AIF3 RX2
0x06 = Haptic generator
inputs).
0xA1 = ISRC1 INT2
0x08 = AEC Loop-Back 1 0x50 = EQ1
0xA2 = ISRC1 INT3
0x09 = AEC Loop-Back 2 0x51 = EQ2
0xA3 = ISRC1 INT4
0x52 = EQ3
0x0D = Noise generator
0xA4 = ISRC1 DEC1
0x53 = EQ4
0x10 = IN1L signal path
0xA5 = ISRC1 DEC2
0x58 = DRC1 Left
0x11 = IN1R signal path
0xA6 = ISRC1 DEC3
0x59 = DRC1 Right
0x12 = IN2L signal path
0xA7 = ISRC1 DEC4
0x5A = DRC2 Left
0x13 = IN2R signal path
0xA8 = ISRC2 INT1
0x5B = DRC2 Right
0x20 = AIF1 RX1
0xA9 = ISRC2 INT2
0x60 = LHPF1
0x21 = AIF1 RX2
0xAA = ISRC2 INT3
0x61 = LHPF2
0x22 = AIF1 RX3
0xAB = ISRC2 INT4
0x62 = LHPF3
0x23 = AIF1 RX4
0xAC = ISRC2 DEC1
0x63 = LHPF4
0x24 = AIF1 RX5
0x68 = DSP1 Channel 1 0xAD = ISRC2 DEC2
0x25 = AIF1 RX6
0x69 = DSP1 Channel 2 0xAE = ISRC2 DEC3
0x28 = AIF2 RX1
0x6A = DSP1 Channel 3 0xAF = ISRC2 DEC4
0x29 = AIF2 RX2
DS1137PP1
CS47L15
4.3 Digital Core
4.3.2
Digital-Core Inputs
The digital core comprises multiple input paths, as shown in Fig. 4-15. Any of these inputs may be selected as a source
to the digital mixers or signal-processing functions within the CS47L15 digital core.
Note that the outputs from other blocks within the digital core may also be selected as input to the digital mixers or
signal-processing functions within the CS47L15 digital core. Those input sources, which are not shown in Fig. 4-15, are
described separately throughout Section 4.3.
The hexadecimal numbers in Fig. 4-15 indicate the corresponding x_SRCn setting for selection of that signal as an input
to another digital-core function.
The sample rate for the input signal paths is configured by using the applicable IN_RATE or AIFn_RATE field; see
Table 4-24. Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is
configured for a different sample rate.
Silence (mute) (0x00)
AEC1 Loopback (0x08)
AEC2 Loopback (0x09)
IN1L signal path (0x10)
IN1R signal path (0x11)
IN2L signal path (0x12)
IN2R signal path (0x13)
AIF1 RX1 (0x20)
AIF1 RX2 (0x21)
AIF1 RX3 (0x22)
AIF1 RX4 (0x23)
AIF1 RX5 (0x24)
AIF1 RX6 (0x25)
AIF2 RX1 (0x28)
AIF2 RX2 (0x29)
AIF2 RX3 (0x2A)
AIF2 RX4 (0x2B)
AIF3 RX1 (0x30)
AIF3 RX2 (0x31)
Figure 4-15. Digital-Core Inputs
4.3.3
Digital-Core Output Mixers
The digital core comprises multiple output paths. The output paths associated with AIF1–AIF3 are shown in Fig. 4-16. The
output paths associated with OUT1, OUT4, and OUT5 are shown in Fig. 4-17.
A four-input mixer is associated with each output. The four input sources are selectable in each case, and independent
volume control is provided for each path.
The AIF1–AIF3 output mixer control fields (see Fig. 4-16) are located at register addresses R1792–R1935
(0x0700–0x078F). The OUT1, OUT4, and OUT5 output mixer control fields (see Fig. 4-17) are located at addresses
R1664–R1743 (0x0680–0x06CF).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be
configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are
available to support flexible interconnectivity; see Section 4.3.14.
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4.3 Digital Core
The sample rate for the output signal paths is configured using the applicable OUT_RATE or AIFn_RATE fields; see
Table 4-24. Note that sample-rate conversion is required when routing the output signal paths to any signal chain that is
configured for a different sample rate.
The OUT_RATE or AIFn_RATE fields must not be changed if any of the respective x_SRCn fields is nonzero. The
associated x_SRCn fields must be cleared before writing new values to OUT_RATE or AIFn_RATE. A minimum delay of
125 s must be allowed between clearing the x_SRCn fields and writing to the associated OUT_RATE or AIFn_RATE
fields. See Table 4-24 for details.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output
mixer paths. If the frequency is too low, an attempt to enable an output mixer path fails. Note that active signal paths are
not affected under such circumstances.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
…
AIF1TXnMIX_SRC1
AIF1TXnMIX_VOL1
…
AIF1TXnMIX_SRC2
AIF1TXnMIX_VOL2
…
AIF1TXnMIX_SRC3
AIF1TXnMIX_VOL3
…
AIF1TXnMIX_SRC4
AIF1TXnMIX_VOL4
+
AIF1 TXn
CS47L15 supports six AIF1 output mixers, i.e., n = 1–6
…
AIF2TXnMIX_SRC1
AIF2TXnMIX_VOL1
…
AIF2TXnMIX_SRC2
AIF2TXnMIX_VOL2
…
AIF2TXnMIX_SRC3
AIF2TXnMIX_VOL3
…
AIF2TXnMIX_SRC4
AIF2TXnMIX_VOL4
+
AIF2 TXn
CS47L15 supports four AIF2 output mixers, i.e., n = 1–4
…
AIF3TXnMIX_SRC1
AIF3TXnMIX_VOL1
…
AIF3TXnMIX_SRC2
AIF3TXnMIX_VOL2
…
AIF3TXnMIX_SRC3
AIF3TXnMIX_VOL3
…
AIF3TXnMIX_SRC4
AIF3TXnMIX_VOL4
+
AIF3 TXn
CS47L15 supports two AIF3 output mixers, i.e., n = 1 or 2
Figure 4-16. Digital-Core AIF Outputs
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4.3 Digital Core
…
OUTnLMIX_SRC1
OUTnLMIX_VOL1
…
OUTnLMIX_SRC2
OUTnLMIX_VOL2
…
OUTnLMIX_SRC3
OUTnLMIX_VOL3
…
OUTnLMIX_SRC4
OUTnLMIX_VOL4
…
OUTnRMIX_SRC1
OUTnRMIX_VOL1
…
OUTnRMIX_SRC2
OUTnRMIX_VOL2
…
OUTnRMIX_SRC3
OUTnRMIX_VOL3
…
OUTnRMIX_SRC4
OUTnRMIX_VOL4
+
+
OUTn Left
OUTn Right
CS47L15 supports two stereo output mixer pairs, i.e., n = 1 or 5
…
OUT4LMIX_SRC1
OUT4LMIX_VOL1
…
OUT4LMIX_SRC2
OUT4LMIX_VOL2
…
OUT4LMIX_SRC3
OUT4LMIX_VOL3
…
OUT4LMIX_SRC4
OUT4LMIX_VOL4
+
OUT4 Left
CS47L15 supports one mono output mixer
Figure 4-17. Digital-Core OUTn Outputs
4.3.4
Five-Band Parametric Equalizer (EQ)
The digital core provides four EQ processing blocks as shown in Fig. 4-18. A four-input mixer is associated with each EQ.
The four input sources are selectable in each case, and independent volume control is provided for each path. Each EQ
block supports one output.
The EQ provides selective control of five frequency bands as follows:
•
The low-frequency band (Band 1) filter can be configured as a peak filter or as a shelving filter. If configured as a
shelving filter, it provides adjustable gain below the Band 1 cut-off frequency. As a peak filter, it provides adjustable
gain within a defined frequency band that is centered on the Band 1 frequency.
•
The midfrequency bands (Band 2–Band 4) filters are peak filters that provide adjustable gain around the respective
center frequency.
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•
The high-frequency band (Band 5) filter is a shelving filter that provides adjustable gain above the Band 5 cut-off
frequency.
…
EQnMIX_SRC1
EQnMIX_VOL1
…
EQnMIX_SRC2
EQnMIX_VOL2
…
EQnMIX_SRC3
EQnMIX_VOL3
…
EQnMIX_SRC4
EQnMIX_VOL4
+
EQ
Five-band equalizer
EQ1 (0x50)
EQ2 (0x51)
EQ3 (0x52)
EQ4 (0x53)
CS47L15 supports four EQ blocks, i.e., n = 1–4
Figure 4-18. Digital-Core EQ Blocks
The EQ1–EQ4 mixer control fields (see Fig. 4-18) are located at register addresses R2176–R2207 (0x0880–0x089F).
The full list of digital-mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the respective EQ processing blocks. Note that the selected input sources
must be configured for the same sample rate as the EQ to which they are connected. Sample-rate conversion functions
are available to support flexible interconnectivity; see Section 4.3.14.
The hexadecimal numbers in Fig. 4-18 indicate the corresponding x_SRCn setting for selection of that signal as an input
to another digital-core function.
The sample rate for the EQ function is configured using FX_RATE; see Table 4-24. Note that the EQ, DRC, and LHPF
functions must be configured for the same sample rate. Sample-rate conversion is required when routing the EQ signal
paths to any signal chain that is configured for a different sample rate.
The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields
must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing
the x_SRCn fields and writing to FX_RATE. See Table 4-24 for details.
The cut-off or center frequencies for the five-band EQ are set by using the coefficients held in the registers identified in
Table 4-11. These coefficients are derived using tools provided in Cirrus Logic’s WISCE™ evaluation-board control
software; please contact your Cirrus Logic representative for details.
Table 4-11. EQ Coefficient Registers
EQ
EQ1
EQ2
EQ3
EQ4
Register Addresses
R3602 (0x0E10) to R3620 (0x0E24)
R3624 (0x0E28) to R3642 (0x0E3A)
R3646 (0x0E3E) to R3664 (0x0E53)
R3668 (0x0E54) to R3686 (0x0E66)
The control registers associated with the EQ functions are described in Table 4-12.
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Table 4-12. EQ Enable and Gain Control
Register Address
R3585 (0x0E01)
FX_Ctrl2
Bit
Label
15:4 FX_STS[11:0]
R3600 (0x0E10)
EQ1_1
15:11
10:6
5:1
0
R3601 (0x0E11)
EQ1_2
15:11 EQ1_B4_GAIN[4:0]
10:6 EQ1_B5_GAIN[4:0]
0
EQ1_B1_MODE
EQ1_B1_GAIN[4:0]
EQ1_B2_GAIN[4:0]
EQ1_B3_GAIN[4:0]
EQ1_ENA
R3602 (0x0E12) to 15:0 EQ1_B1_*
R3620 (0x0E24)
EQ1_B2_*
EQ1_B3_*
EQ1_B4_*
EQ1_B5_*
R3622 (0x0E26)
15:11 EQ2_B1_GAIN[4:0]
EQ2_1
10:6 EQ2_B2_GAIN[4:0]
5:1
0
R3623 (0x0E27)
EQ2_2
EQ2_B3_GAIN[4:0]
EQ2_ENA
15:11 EQ2_B4_GAIN[4:0]
10:6 EQ2_B5_GAIN[4:0]
0
EQ2_B1_MODE
R3624 (0x0E28) to 15:0 EQ2_B1_*
R3642 (0x0E3A)
EQ2_B2_*
EQ2_B3_*
EQ2_B4_*
EQ2_B5_*
R3644 (0x0E3C)
15:11 EQ3_B1_GAIN[4:0]
10:6 EQ3_B2_GAIN[4:0]
EQ3_1
5:1 EQ3_B3_GAIN[4:0]
0
EQ3_ENA
R3645 (0x0E3D)
EQ3_2
DS1137PP1
15:11 EQ3_B4_GAIN[4:0]
10:6 EQ3_B5_GAIN[4:0]
0
EQ3_B1_MODE
Default
Description
0x00 LHPF, DRC, EQ Enable Status. Indicates the status of each of the respective
signal-processing functions. Each bit is coded as follows:
0 = Disabled
1 = Enabled
[11] = EQ4
[7] = DRC2 (Right)
[3] = LHPF4
[10] = EQ3
[6] = DRC2 (Left)
[2] = LHPF3
[9] = EQ2
[5] = DRC1 (Right)
[1] = LHPF2
[8] = EQ1
[4] = DRC1 (Left)
[0] = LHPF1
0x0C EQ1 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0x0C EQ1 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0x0C EQ1 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0
EQ1 Enable
0 = Disabled
1 = Enabled
0x0C EQ1 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0x0C EQ1 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0
EQ1 Band 1 Mode
0 = Shelving filter
1 = Peak filter
—
EQ1 Frequency Coefficients. Refer to WISCE evaluation board control software for
the derivation of these field values.
0x0C
0x0C
0x0C
0
0x0C
0x0C
0
—
0x0C
0x0C
0x0C
0
0x0C
0x0C
0
EQ2 Band 1 Gain 1
–12 dB to +12 dB in 1-dB steps
EQ2 Band 2 Gain 1
–12 dB to +12 dB in 1-dB steps
EQ2 Band 3 Gain 1
–12 dB to +12 dB in 1-dB steps
EQ2 Enable
0 = Disabled
1 = Enabled
EQ2 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ2 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ2 Band 1 Mode
0 = Shelving filter
1 = Peak filter
EQ2 Frequency Coefficients. Refer to WISCE evaluation board control software for
the derivation of these field values.
EQ3 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ3 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ3 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ3 Enable
0 = Disabled
1 = Enabled
EQ3 Band 4 Gain1 (–12 dB to +12 dB in 1-dB steps)
EQ3 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ3 Band 1 Mode
0 = Shelving filter
1 = Peak filter
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4.3 Digital Core
Table 4-12. EQ Enable and Gain Control (Cont.)
Register Address Bit
Label
Default
Description
R3646 (0x0E3E) to 15:0 EQ3_B1_*
—
EQ3 Frequency Coefficients. Refer to WISCE evaluation board control software for
the derivation of these field values.
R3664 (0x0E50)
EQ3_B2_*
EQ3_B3_*
EQ3_B4_*
EQ3_B5_*
R3666 (0x0E52)
15:11 EQ4_B1_GAIN[4:0] 0x0C EQ4 Band 1 Gain 1 (–12 dB to +12 dB in 1-dB steps)
10:6 EQ4_B2_GAIN[4:0] 0x0C EQ4 Band 2 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ4_1
5:1 EQ4_B3_GAIN[4:0] 0x0C EQ4 Band 3 Gain 1 (–12 dB to +12 dB in 1-dB steps)
0
EQ4_ENA
0
EQ4 Enable
0 = Disabled
1 = Enabled
R3667 (0x0E53)
15:11 EQ4_B4_GAIN[4:0] 0x0C EQ4 Band 4 Gain 1 (–12 dB to +12 dB in 1-dB steps)
EQ4_2
10:6 EQ4_B5_GAIN[4:0] 0x0C EQ4 Band 5 Gain 1 (–12 dB to +12 dB in 1-dB steps
0
EQ4_B1_MODE
0
EQ4 Band 1 Mode
0 = Shelving filter
1 = Peak filter
R3668 (0x0E54) to 15:0 EQ4_B1_*
—
EQ4 Frequency Coefficients
R3686 (0x0E66)
EQ4_B2_*
Refer to WISCE evaluation board control software for the derivation of these field
values.
EQ4_B3_*
EQ4_B4_*
EQ4_B5_*
1.See Table 4-13 for gain range.
Table 4-13 lists the EQ gain control settings.
Table 4-13. EQ Gain-Control Range
EQ Gain Setting Gain (dB) EQ Gain Setting Gain (dB)
00000
–12
01101
+1
00001
–11
01110
+2
00010
–10
01111
+3
00011
–9
10000
+4
00100
–8
10001
+5
00101
–7
10010
+6
00110
–6
10011
+7
00111
–5
10100
+8
01000
–4
10101
+9
01001
–3
10110
+10
01010
–2
10111
+11
01011
–1
11000
+12
01100
0
11001–11111 Reserved
The CS47L15 automatically checks to confirm whether the SYSCLK frequency is high enough to support the commanded
EQ and digital mixing functions. If an attempt is made to enable an EQ signal path, and there are insufficient SYSCLK
cycles to support it, the attempt does not succeed. Note that any signal paths that are already active are not affected under
such circumstances.
The FX_STS field in register R3585 indicates the status of each of the EQ, DRC, and LHPF signal paths. If an
underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
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4.3 Digital Core
4.3.5
Dynamic Range Control (DRC)
The digital core provides two stereo DRC processing blocks, as shown in Fig. 4-19. A four-input mixer is associated with
each DRC input channel. The input sources are selectable in each case, and independent volume control is provided for
each path. The stereo DRC blocks support two outputs each.
The function of the DRC is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a
wide range, for example, when recording from microphones built into a handheld system or to restrict the dynamic range
of an output signal path.
To improve intelligibility in the presence of loud impulsive noises, the DRC can apply compression and automatic level
control to the signal path. It incorporates anticlip and quick-release features for handling transients.
The DRC also incorporates a noise-gate function that provides additional attenuation of very low-level input signals. This
means that the signal path is quiet when no signal is present, giving an improvement in background noise level under these
conditions.
A signal-detect function is provided within the DRC; this can be used to detect the presence of an audio signal and to
trigger other events. It can also be used as an interrupt event or to trigger the control-write sequencer. Note that DRC
triggering of the control-write sequencer is supported for DRC1 only.
…
DRCnLMIX_SRC1
DRCnLMIX_VOL1
…
DRCnLMIX_SRC2
DRCnLMIX_VOL2
…
DRCnLMIX_SRC3
DRCnLMIX_VOL3
…
DRCnLMIX_SRC4
DRCnLMIX_VOL4
…
DRCnRMIX_SRC1
DRCnRMIX_VOL1
…
DRCnRMIX_SRC2
DRCnRMIX_VOL2
…
DRCnRMIX_SRC3
DRCnRMIX_VOL3
…
DRCnRMIX_SRC4
DRCnRMIX_VOL4
+
DRC
Dynamic Range
Controller
+
DRC
Dynamic Range
Controller
DRC1 Left (0x58)
DRC2 Left (0x5A)
DRC1 Right (0x59)
DRC2 Right (0x5B)
CS47L15 supports two stereo DRC blocks, i.e., n = 1 or 2
Figure 4-19. Dynamic Range Control (DRC) Block
The DRC1 and DRC2 mixer control fields (see Fig. 4-19) are located at register addresses R2240–R2271
(0x08C0–0x08DF).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the respective DRC processing blocks. Note that the selected input sources
must be configured for the same sample rate as the DRC to which they are connected. Sample-rate conversion functions
are available to support flexible interconnectivity; see Section 4.3.14.
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The hexadecimal numbers in Fig. 4-19 indicate the corresponding x_SRCn setting for selection of that signal as an input
to another digital-core function.
The sample rate for the DRC function is configured using FX_RATE; see Table 4-24. Note that the EQ, DRC, and LHPF
functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the DRC
signal paths to any signal chain that is configured for a different sample rate.
The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields
must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing
the x_SRCn fields and writing to FX_RATE. See Table 4-24 for details.
The DRC functions are enabled using the control registers described in Table 4-14.
Table 4-14. DRC Enable
Register Address
R3712 (0x0E80)
DRC1_ctrl1
R3720 (0x0E88)
DRC2_ctrl1
Bit
1
Label
DRC1L_ENA
Default
0
0
DRC1R_ENA
0
1
DRC2L_ENA
0
0
DRC2R_ENA
0
Description
DRC1 (left) enable
0 = Disabled
1 = Enabled
DRC1 (right) enable
0 = Disabled
1 = Enabled
DRC2 (left) enable
0 = Disabled
1 = Enabled
DRC2 (right) enable
0 = Disabled
1 = Enabled
The following description of the DRC is applicable to each of the DRCs. The associated control fields are described in
Table 4-16 and Table 4-17 for DRC1 and DRC2 respectively.
4.3.5.1 DRC Compression, Expansion, and Limiting
The DRC supports two different compression regions, separated by a knee at a specific input amplitude. In the region
above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope
DRCn_LO_COMP applies. Note that n identifies the applicable DRC 1 or 2.
The DRC also supports a noise-gate region, where low-level input signals are heavily attenuated. This function can be
enabled or disabled according to the application requirements. The DRC response in this region is defined by the
expansion slope DRCn_NG_EXP.
For additional attenuation of signals in the noise-gate region, an additional knee can be defined (shown as Knee 2 in
Fig. 4-20). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the
DRCn_LO_COMP and DRCn_NG_EXP regions.
The overall DRC compression characteristic in steady state (i.e., where the input amplitude is near constant) is shown in
Fig. 4-20.
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4.3 Digital Core
DRCn Output Amplitude (dB)
(Y0)
Knee 1
DRCn_KNEE_OP
Knee 2
C
DR
P
OM
C
_
LO
n_
OMP
HI_C
_
n
C
DR
DR
Cn
_N
G
_E
XP
DRCn_KNEE2_OP
DRCn_KNEE2_IP
DRCn_KNEE_IP
0dB
DRCn Input Amplitude (dB)
Figure 4-20. DRC Response Characteristic
The slope of the DRC response is determined by DRCn_HI_COMP and DRCn_LO_COMP. A slope of 1 indicates constant
gain in this region. A slope less than 1 represents compression (i.e., a change in input amplitude produces only a smaller
change in output amplitude). A slope of 0 indicates that the target output amplitude is the same across a range of input
amplitudes; this is infinite compression.
When the noise gate is enabled, the DRC response in this region is determined by DRCn_NG_EXP. A slope of 1 indicates
constant gain in this region. A slope greater than 1 represents expansion (i.e., a change in input amplitude produces a
larger change in output amplitude).
When the DRCn_KNEE2_OP knee is enabled (Knee 2 in Fig. 4-20), this introduces the vertical line in the response pattern
shown, resulting in infinitely steep attenuation at this point in the response.
The DRC parameters are listed in Table 4-15.
Table 4-15. DRC Response Parameters
Parameters
1
2
3
4
5
6
7
Parameter
DRCn_KNEE_IP
DRCn_KNEE_OP
DRCn_HI_COMP
DRCn_LO_COMP
DRCn_KNEE2_IP
DRCn_NG_EXP
DRCn_KNEE2_OP
Description
Input level at Knee 1 (dB)
Output level at Knee 2 (dB)
Compression ratio above Knee 1
Compression ratio below Knee 1
Input level at Knee 2 (dB)
Expansion ratio below Knee 2
Output level at Knee 2 (dB)
The noise gate is enabled by setting DRCn_NG_ENA. When the noise gate is not enabled, Parameters 5–7 (see
Table 4-15) are ignored, and the DRCn_LO_COMP slope applies to all input signal levels below Knee 1.
The DRCn_KNEE2_OP knee is enabled by setting DRCn_KNEE2_OP_ENA. If this bit is not set, Parameter 7 is ignored
and the Knee 2 position always coincides with the low end of the DRCn_LO_COMP region.
The Knee 1 point in Fig. 4-20 is determined by DRCn_KNEE_IP and DRCn_KNEE_OP.
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Parameter Y0, the output level for a 0 dB input, is not specified directly but can be calculated from the other parameters
using Eq. 4-1.
Y0
=
DRCn_KNEE_OP
–  DRCn_KNEE_IP  DRCn_HI_COMP 
Equation 4-1. DRC Compression Calculation
4.3.5.2 Gain Limits
The minimum and maximum gain applied by the DRC is set by DRCn_MINGAIN, DRCn_MAXGAIN, and DRCn_NG_
MINGAIN. These limits can be used to alter the DRC response from that shown in Fig. 4-20. If the range between
maximum and minimum gain is reduced, the extent of the dynamic range control is reduced.
The minimum gain in the compression regions of the DRC response is set by DRCn_MINGAIN. The minimum gain in the
noise-gate region is set by DRCn_NG_MINGAIN. The minimum gain limit prevents excessive attenuation of the signal
path.
The maximum gain limit set by DRCn_MAXGAIN prevents quiet signals (or silence) from being excessively amplified.
4.3.5.3 Dynamic Characteristics
The dynamic behavior determines how quickly the DRC responds to changing signal levels. Note that the DRC responds
to the average (RMS) signal amplitude over a period of time.
The DRCn_ATK determines how quickly the DRC gain decreases when the signal amplitude is high. The DRCn_DCY
determines how quickly the DRC gain increases when the signal amplitude is low.
These fields are described in Table 4-16 and Table 4-17. The register defaults are suitable for general-purpose
microphone use.
4.3.5.4 Anticlip Control
The DRC includes an anticlip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses
a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing
the gain attack rate when required. The anticlip feature is enabled using the DRCn_ANTICLIP bit.
Note that the feed-forward processing increases the latency in the input signal path.
Note that the anticlip feature operates entirely in the digital domain. It cannot be used to prevent signal clipping in the
analog domain nor in the source signal. Analog clipping can only be prevented by reducing the analog signal gain or by
adjusting the source signal.
4.3.5.5 Quick Release Control
The DRC includes a quick-release feature to handle short transient peaks that are not related to the intended source
signal. For example, in handheld microphone recording, transient signal peaks sometimes occur due to user handling, key
presses or accidental tapping against the microphone. The quick-release feature ensures that these transients do not
cause the intended signal to be masked by the longer time constant of DRCn_DCY.
The quick-release feature is enabled by setting the DRCn_QR bit. When this bit is enabled, the DRC measures the crest
factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a transient peak that may not be related
to the intended source signal. If the crest factor exceeds the level set by DRCn_QR_THR, the normal decay rate (DRCn_
DCY) is ignored and a faster decay rate (DRCn_QR_DCY) is used instead.
4.3.5.6 Signal Activity Detect
The DRC incorporates a configurable signal-detect function, allowing the signal level at the DRC input to be monitored
and to be used to trigger other events. This can be used to detect the presence of a microphone signal on an ADC or DMIC
channel, or can be used to detect an audio signal received over the digital audio interface.
54
DS1137PP1
CS47L15
4.3 Digital Core
The DRC signal-detect function is enabled by setting DRCn_SIG_DET. Note that the respective DRCn must also be
enabled. The detection threshold is either a peak level (crest factor) or an RMS level, depending on DRCn_SIG_DET_
MODE. When peak level is selected, the threshold is determined by DRCn_SIG_DET_PK, which defines the applicable
crest factor (peak-to-RMS ratio) threshold. If RMS level is selected, the threshold is set using DRCn_SIG_DET_RMS.
The DRC signal-detect function is an input to the interrupt control circuit and can be used to trigger an interrupt event; see
Section 4.12.
The control-write sequencer can be triggered by the DRC1 signal-detect function. This is enabled by setting DRC1_
WSEQ_SIG_DET_ENA. See Section 4.15.
Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available
on DRC1 only.
4.3.5.7 DRC Register Controls
The DRC1 control registers are described in Table 4-16.
Table 4-16. DRC1 Control Registers
Register Address Bit
Label
R3585 (0x0E01)
15:4 FX_STS[11:0]
FX_Ctrl2
R3712 (0x0E80)
DRC1_ctrl1
DS1137PP1
Default
Description
0x00 LHPF, DRC, EQ enable status. Indicates the status of each of the respective
signal-processing functions. Each bit is coded as follows:
0 = Disabled
1 = Enabled
[11] = EQ4
[7] = DRC2 (Right)
[3] = LHPF4
[10] = EQ3
[6] = DRC2 (Left)
[2] = LHPF3
[9] = EQ2
[5] = DRC1 (Right)
[1] = LHPF2
[8] = EQ1
[4] = DRC1 (Left)
[0] = LHPF1
15:11 DRC1_SIG_
0x00 DRC1 Signal-Detect RMS Threshold. RMS signal level for signal-detect to be indicated
DET_RMS[4:0]
when DRC1_SIG_DET_MODE = 1.
0x00 = –30 dB
…. (1.5-dB steps)
0x1F = –76.5 dB
0x01 = –31.5 dB
0x1E = –75 dB
10:9 DRC1_SIG_
00
DRC1 Signal-Detect Peak Threshold. This is the Peak/RMS ratio, or Crest Factor, level
DET_PK[1:0]
for signal-detect to be indicated when DRC1_SIG_DET_MODE = 0.
00 = 12 dB
10 = 24 dB
01 = 18 dB
11 = 30 dB
8
DRC1_NG_ENA
0
DRC1 Noise-Gate Enable
0 = Disabled
1 = Enabled
7
DRC1_SIG_
0
DRC1 Signal-Detect Mode
DET_MODE
0 = Peak threshold mode
1 = RMS threshold mode
6
DRC1_SIG_DET
0
DRC1 Signal-Detect Enable
0 = Disabled
1 = Enabled
5
DRC1_KNEE2_
0
DRC1 KNEE2_OP Enable
OP_ENA
0 = Disabled
1 = Enabled
4
DRC1_QR
1
DRC1 Quick-release Enable
0 = Disabled
1 = Enabled
3
DRC1_ANTICLIP
1
DRC1 Anticlip Enable
0 = Disabled
1 = Enabled
2
DRC1_WSEQ_
0
DRC1 Signal-Detect Write Sequencer Select
SIG_DET_ENA
0 = Disabled
1 = Enabled
55
CS47L15
4.3 Digital Core
Table 4-16. DRC1 Control Registers (Cont.)
Register Address Bit
Label
R3713 (0x0E81)
12:9 DRC1_ATK[3:0]
DRC1_ctrl2
R3714 (0x0E82)
DRC1_ctrl3
8:5
DRC1_DCY[3:0]
4:2
DRC1_
MINGAIN[2:0]
1:0
DRC1_
MAXGAIN[1:0]
15:12 DRC1_NG_
MINGAIN[3:0]
11:10 DRC1_NG_
EXP[1:0]
R3715 (0x0E83)
DRC1_ctrl4
R3716 (0x0E84)
DRC1_ctrl5
56
9:8
DRC1_QR_
THR[1:0]
7:6
DRC1_QR_
DCY[1:0]
5:3
DRC1_HI_
COMP[2:0]
2:0
DRC1_LO_
COMP[2:0]
10:5 DRC1_KNEE_
IP[5:0]
4:0
DRC1_KNEE_
OP[4:0]
9:5
DRC1_KNEE2_
IP[4:0]
4:0
DRC1_KNEE2_
OP[4:0]
Default
Description
0100 DRC1 Gain attack rate (seconds/6 dB)
0000 = Reserved
0101 = 2.9 ms
1010 = 92.8 ms
0110 = 5.8 ms
1011 = 185.6 ms
0001 = 181 s
0010 = 363 s
0111 = 11.6 ms
1100 to 1111 = Reserved
0011 = 726 s
1000 = 23.2 ms
0100 = 1.45 ms
1001 = 46.4 ms
1001 DRC1 Gain decay rate (seconds/6 dB)
0000 = 1.45 ms
0101 = 46.5 ms
1010 = 1.49 s
1011 = 2.97 s
0001 = 2.9 ms
0110 = 93 ms
0111 = 186 ms
1100 to 1111 = Reserved
0010 = 5.8 ms
0011 = 11.6 ms
1000 = 372 ms
0100 = 23.25 ms
1001 = 743 ms
100 DRC1 Minimum gain to attenuate audio signals
000 = 0 dB
011 = –24 dB
11X = Reserved
001 = –12 dB
100 = –36 dB
010 = –18 dB
101 = Reserved
11
DRC1 Maximum gain to boost audio signals (dB)
00 = 12 dB
10 = 24 dB
01 = 18 dB
11 = 36 dB
0000 DRC1 Minimum gain to attenuate audio signals when the Noise Gate is active.
0101 = –6 dB
1010 = 24 dB
0000 = –36 dB
0110 = 0 dB
1011 = 30 dB
0001 = –30 dB
0010 = –24 dB
0111 = 6 dB
1100 = 36 dB
1000 = 12 dB
1101 to 1111 = Reserved
0011 = –18 dB
0100 = –12 dB
1001 = 18 dB
00
DRC1 Noise-Gate slope
00 = 1 (no expansion)
10 = 4
01 = 2
11 = 8
00
DRC1 Quick-release threshold (crest factor in dB)
00 = 12 dB
10 = 24 dB
01 = 18 dB
11 = 30 dB
00
DRC1 Quick-release decay rate (seconds/6 dB)
00 = 0.725 ms
10 = 5.8 ms
01 = 1.45 ms
11 = Reserved
011 DRC1 Compressor slope (upper region)
000 = 1 (no compression) 011 = 1/8
110 = Reserved
001 = 1/2
100 = 1/16
111 = Reserved
010 = 1/4
101 = 0
000 DRC1 Compressor slope (lower region)
000 = 1 (no compression) 011 = 1/8
11X = Reserved
001 = 1/2
100 = 0
010 = 1/4
101 = Reserved
0x00 DRC1 Input signal level at the compressor knee.
0x00 = 0 dB
0x02 = –1.5 dB
0x3C = –45 dB
0x01 = –0.75 dB
… (–0.75-dB steps)
0x3D–-0x3F = Reserved
0x00 DRC1 Output signal at the compressor knee.
0x00 = 0 dB
0x02 = –1.5 dB
0x1E = –22.5 dB
0x01 = –0.75 dB
… (–0.75 dB steps)
0x1F = Reserved
0x00 DRC1 Input signal level at the noise-gate threshold Knee 2.
0x00 = –36 dB
0x02 = –39 dB
0x1E = –81 dB
0x01 = –37.5 dB
… (-1.5-dB steps)
0x1F = –82.5 dB
Applicable if DRC1_NG_ENA = 1.
0x00 DRC1 Output signal at the noise-gate threshold Knee 2.
0x00 = –30 dB
0x02 = –33 dB
0x1E = –75 dB
0x01 = –31.5 dB
… (–1.5dB steps)
0x1F = –76.5 dB
Applicable only if DRC1_KNEE2_OP_ENA = 1.
DS1137PP1
CS47L15
4.3 Digital Core
The DRC2 control registers are described in Table 4-17.
Table 4-17. DRC2 Control Registers
Register Address Bit
Label
R3585 (0x0E01)
15:4 FX_STS[11:0]
FX_Ctrl2
R3720 (0x0E88)
DRC2_ctrl1
R3721 (0x0E89)
DRC2_ctrl2
DS1137PP1
Default
Description
0x00 LHPF, DRC, EQ Enable Status. Indicates the status of each of the respective
signal-processing functions. Each bit is coded as follows:
0 = Disabled
1 = Enabled
[11] = EQ4
[7] = DRC2 (Right)
[3] = LHPF4
[10] = EQ3
[6] = DRC2 (Left)
[2] = LHPF3
[9] = EQ2
[5] = DRC1 (Right)
[1] = LHPF2
[8] = EQ1
[4] = DRC1 (Left)
[0] = LHPF1
15:11 DRC2_SIG_
0x00 DRC2 Signal-Detect RMS Threshold. This is the RMS signal level for signal-detect to be
DET_RMS[4:0]
indicated when DRC2_SIG_DET_MODE = 1.
0x00 = –30 dB
…. (1.5-dB steps)
0x1F = –76.5 dB
0x01 = –31.5 dB
0x1E = –75 dB
10:9 DRC2_SIG_
00
DRC2 Signal-Detect Peak Threshold. Peak/RMS ratio, or Crest Factor, level for
DET_PK[1:0]
signal-detect to be indicated when DRC2_SIG_DET_MODE = 0.
00 = 12 dB
10 = 24 dB
01 = 18 dB
11 = 30 dB
8
DRC2_NG_
0
DRC2 Noise-Gate Enable
ENA
0 = Disabled
1 = Enabled
7
DRC2_SIG_
0
DRC2 Signal-Detect Mode
DET_MODE
0 = Peak threshold mode
1 = RMS threshold mode
6
DRC2_SIG_
0
DRC2 Signal-Detect Enable
DET
0 = Disabled
1 = Enabled
5
DRC2_
0
DRC2 KNEE2_OP Enable
KNEE2_OP_
0 = Disabled
ENA
1 = Enabled
4
DRC2_QR
1
DRC2 Quick-release Enable
0 = Disabled
1 = Enabled
3
DRC2_
1
DRC2 Anticlip Enable
ANTICLIP
0 = Disabled
1 = Enabled
12:9 DRC2_
0100 DRC2 Gain attack rate (seconds/6 dB)
ATK[3:0]
0000 = Reserved
0101 = 2.9 ms
1010 = 92.8 ms
1011 = 185.6 ms
0001 = 181 s
0110 = 5.8 ms
1100 to 1111 = Reserved
0010 = 363 s
0111 = 11.6 ms
1000 = 23.2 ms
0011 = 726 s
1001 = 46.4 ms
0100 = 1.45 ms
8:5 DRC2_
1001 DRC2 Gain decay rate (seconds/6 dB)
DCY[3:0]
1010 = 1.49 s
0000 = 1.45 ms
0101 = 46.5 ms
1011 = 2.97 s
0110 = 93 ms
0001 = 2.9 ms
1100 to 1111 = Reserved
0111 = 186 ms
0010 = 5.8 ms
1000 = 372 ms
0011 = 11.6 ms
1001 = 743 ms
0100 = 23.25 ms
4:2 DRC2_
100 DRC2 Minimum gain to attenuate audio signals
MINGAIN[2:0]
000 = 0 dB
011 = –24 dB
11X = Reserved
001 = –12 dB (default)
100 = –36 dB
010 = –18 dB
101 = Reserved
1:0 DRC2_
11
DRC2 Maximum gain to boost audio signals (dB)
MAXGAIN[1:0]
10 = 24 dB
00 = 12 dB
01 = 18 dB
11 = 36 dB
57
CS47L15
4.3 Digital Core
Table 4-17. DRC2 Control Registers (Cont.)
Register Address Bit
Label
R3722 (0x0E8A) 15:12 DRC2_NG_
MINGAIN[3:0]
DRC2_ctrl3
R3723 (0x0E8B)
DRC2_ctrl4
R3724 (0x0E8C)
DRC2_ctrl5
Default
Description
0000 DRC2 Minimum gain to attenuate audio signals when the Noise Gate is active.
0000 = –36 dB
0101 = –6 dB
1010 = 24 dB
0110 = 0 dB
1011 = 30 dB
0001 = –30 dB
0010 = –24 dB
0111 = 6 dB
1100 = 36 dB
0011 = –18 dB
1000 = 12 dB
1101 to 1111 = Reserved
0100 = –12 dB
1001 = 18 dB
11:10 DRC2_NG_
00
DRC2 Noise-Gate slope
EXP[1:0]
00 = 1 (no expansion)
01 = 2
10 = 4
11 = 8
9:8 DRC2_QR_
00
DRC2 Quick-release threshold (crest factor in dB)
THR[1:0]
00 = 12 dB
01 = 18 dB
10 = 24 dB
11 = 30 dB
7:6 DRC2_QR_
00
DRC2 Quick-release decay rate (seconds/6 dB)
DCY[1:0]
00 = 0.725 ms
01 = 1.45 ms
10 = 5.8 ms
11 = Reserved
5:3 DRC2_HI_
011 DRC2 Compressor slope (upper region)
COMP[2:0]
011 = 1/8
110–111 = Reserved
000 = 1 (no compression)
100 = 1/16
001 = 1/2
010 = 1/4
101 = 0
2:0 DRC2_LO_
000 DRC2 Compressor slope (lower region)
COMP[2:0]
000 = 1 (no compression)
010 = 1/4
100 = 0
001 = 1/2
011 = 1/8
101–11X = Reserved
10:5 DRC2_KNEE_
0x00 DRC2 Input signal level at the compressor knee.
IP[5:0]
0x00 = 0 dB
0x02 = –1.5 dB
0x3C = –45 dB
0x01 = –0.75 dB
… (–0.75-dB steps)
0x3D–-0x3F = Reserved
4:0 DRC2_KNEE_
0x00 DRC2 Output signal at the compressor knee.
OP[4:0]
0x00 = 0 dB
0x02 = –1.5 dB
0x1E = –22.5 dB
0x01 = –0.75 dB
… (–0.75 dB steps)
0x1F = Reserved
9:5 DRC2_
0x00 DRC2 Input signal level at the noise-gate threshold Knee 2.
KNEE2_IP[4:0]
0x00 = –36 dB
0x02 = –39 dB
0x1E = –81 dB
0x01 = –37.5 dB
… (-1.5-dB steps)
0x1F = –82.5 dB
Applicable only if DRC2_NG_ENA = 1.
4:0 DRC2_
0x00 DRC2 Output signal at the noise-gate threshold Knee 2.
KNEE2_
0x00 = –30 dB
0x02 = –33 dB
0x1E = –75 dB
OP[4:0]
0x01 = –31.5 dB
… (–1.5dB steps)
0x1F = –76.5 dB
Applicable only if DRC2_KNEE2_OP_ENA = 1.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the
commanded DRC and digital mixing functions. If the frequency is too low, an attempt to enable a DRC signal path fails.
Note that active signal paths are not affected under such circumstances.
The FX_STS field in register R3585 indicates the status of each of the EQ, DRC, and LHPF signal paths. If an
underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
58
DS1137PP1
CS47L15
4.3 Digital Core
4.3.6
Low-/High-Pass Digital Filter (LHPF)
The digital core provides four LHPF processing blocks as shown in Fig. 4-21. A four-input mixer is associated with each
filter. The four input sources are selectable in each case, and independent volume control is provided for each path. Each
LHPF block supports one output.
The LHPF /HPF can be used to remove unwanted out-of-band noise from a signal path. Each filter can be configured either
as a low-pass filter (LPF) or a high-pass filter (HPF).
…
LHPFnMIX_SRC1
LHPFnMIX_VOL1
…
LHPFnMIX_SRC2
LHPFnMIX_VOL2
…
LHPFnMIX_SRC3
LHPFnMIX_VOL3
…
LHPFnMIX_SRC4
LHPFnMIX_VOL4
+
LHPF
Low-Pass filter (LPF) /
High-Pass filter (HPF)
LHPF1 (0x60)
LHPF2 (0x61)
LHPF3 (0x62)
LHPF4 (0x63)
CS47L15 supports four LHPF blocks, i.e., n = 1–4
Figure 4-21. Digital-Core LPF/HPF Blocks
The LHPF1–LHPF4 mixer control fields, shown in Fig. 4-21, are located at register addresses R2304–R2335
(0x0900–0x091F).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the respective LHPF processing blocks. Note that the selected input
sources must be configured for the same sample rate as the LHPF to which they are connected. Sample-rate conversion
functions are available to support flexible interconnectivity; see Section 4.3.14.
The hexadecimal numbers in Fig. 4-21 indicate the corresponding x_SRCn setting for selection of that signal as an input
to another digital-core function.
The sample rate for the LHPF function is configured using FX_RATE; see Table 4-24. Note that the EQ, DRC, and LHPF
functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the LHPF
signal paths to any signal chain that is configured for a different sample rate.
The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields
must be cleared before writing a new value to FX_RATE. A minimum delay of 125 s must be allowed between clearing
the x_SRCn fields and writing to FX_RATE. See Table 4-24 for details.
The control registers associated with the LHPF functions are described in Table 4-18.
The cut-off frequencies for the LHPF blocks are set using the coefficients held in registers R3777, R3781, R3785, and
R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus
Logic’s WISCE evaluation board control software; please contact your Cirrus Logic representative for details.
DS1137PP1
59
CS47L15
4.3 Digital Core
Table 4-18. Low-Pass Filter/High-Pass Filter
Register Address Bit
Label
R3585 (0x0E01)
15:4 FX_STS[11:0]
FX_Ctrl2
R3776 (0x0EC0)
HPLPF1_1
R3777 (0x0EC1)
HPLPF1_2
R3780 (0x0EC4)
HPLPF2_1
R3781 (0x0EC5)
HPLPF2_2
R3784 (0x0EC8)
HPLPF3_1
R3785 (0x0EC9)
HPLPF3_2
R3788 (0x0ECC)
HPLPF4_1
R3789 (0x0ECD)
HPLPF4_2
1
LHPF1_MODE
0
LHPF1_ENA
15:0 LHPF1_COEFF[15:0]
1
LHPF2_MODE
0
LHPF2_ENA
15:0 LHPF2_COEFF[15:0]
1
LHPF3_MODE
0
LHPF3_ENA
15:0 LHPF3_COEFF[15:0]
1
LHPF4_MODE
0
LHPF4_ENA
15:0 LHPF4_COEFF[15:0]
Default
Description
0x00 LHPF, DRC, EQ Enable Status. Indicates the status of the respective
signal-processing functions. Each bit is coded as follows:
0 = Disabled
1 = Enabled
[11] = EQ4
[7] = DRC2 (Right)
[3] = LHPF4
[10] = EQ3
[6] = DRC2 (Left)
[2] = LHPF3
[9] = EQ2
[5] = DRC1 (Right)
[1] = LHPF2
[8] = EQ1
[4] = DRC1 (Left)
[0] = LHPF1
0
Low-/High-Pass Filter 1 Mode
0 = Low Pass
1 = High Pass
0
Low-/High-Pass Filter 1 Enable
0 = Disabled
1 = Enabled
0x0000 Low-/High-Pass Filter 1 Frequency Coefficient
Refer to WISCE evaluation board control software for the derivation of this field
value.
0
Low-/High-Pass Filter 2 Mode
0 = Low Pass
1 = High Pass
0
Low-/High-Pass Filter 2 Enable
0 = Disabled
1 = Enabled
0x0000 Low-/High-Pass Filter 2 Frequency Coefficient
Refer to WISCE evaluation board control software for the derivation of this field
value.
0
Low-/High-Pass Filter 3 Mode
0 = Low Pass
1 = High Pass
0
Low-/High-Pass Filter 3 Enable
0 = Disabled
1 = Enabled
0x0000 Low-/High-Pass Filter 3 Frequency Coefficient
Refer to WISCE evaluation board control software for the derivation of this field
value.
0
Low-/High-Pass Filter 4 Mode
0 = Low Pass
1 = High Pass
0
Low-/High-Pass Filter 4 Enable
0 = Disabled
1 = Enabled
0x0000 Low-/High-Pass Filter 4 Frequency Coefficient
Refer to WISCE evaluation board control software for the derivation of this field
value.
The CS47L15 performs automatic checks to confirm whether the SYSCLK frequency is high enough to support the
commanded LHPF and digital mixing functions. If the frequency is too low, an attempt to enable an LHPF signal path fails.
Note that active signal paths are not affected under such circumstances.
The FX_STS field in register R3585 indicates the status of each of the EQ, DRC, and LHPF signal paths. If an
underclocked error condition occurs, this field indicates which EQ, DRC, or LHPF signal paths have been enabled.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
60
DS1137PP1
CS47L15
4.3 Digital Core
4.3.7
Digital-Core DSP
The digital core provides one programmable DSP processing block as shown in Fig. 4-22. The DSP block supports eight
inputs (Left, Right, Aux1, Aux2, … Aux6). A four-input mixer is associated with the left and right inputs, providing further
expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is
provided for left and right input mixer channels. The DSP block supports six outputs.
The functionality of the DSP processing block is not fixed, and a wide range of audio enhancements algorithms may be
performed. The procedure for configuring the CS47L15 DSP functions is tailored to each customer’s application; please
contact your Cirrus Logic representative for details.
For details of the DSP firmware requirements relating to clocking, register access, and code execution, refer to
Section 4.4.3.
…
DSP1LMIX_SRC1
DSP1LMIX_VOL1
…
DSP1LMIX_SRC2
DSP1LMIX_VOL2
…
DSP1LMIX_SRC3
…
DSP1LMIX_SRC4
+
DSP1 Channel 1 (0x68)
DSP1LMIX_VOL3
DSP1 Channel 2 (0x69)
DSP1LMIX_VOL4
DSP1 Channel 3 (0x6A)
DSP
DSP1 Channel 4 (0x6B)
…
DSP1RMIX_SRC4
DSP1RMIX_VOL4
…
DSP1AUX6_SRC
DSP1RMIX_VOL3
…
DSP1AUX5_SRC
…
DSP1RMIX_SRC3
DSP1 Channel 6 (0x6D)
+
…
DSP1AUX4_SRC
DSP1RMIX_VOL2
…
DSP1AUX3_SRC
…
DSP1RMIX_SRC2
DSP1 Channel 5 (0x6C)
…
DSP1AUX2_SRC
DSP1RMIX_VOL1
…
DSP1AUX1_SRC
…
DSP1RMIX_SRC1
Figure 4-22. Digital-Core DSP Block
The DSP mixer input control fields (see Fig. 4-22) are located at register addresses R2368–R2424 (0x0940–0x0978).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the DSP processing block. Note that the selected input sources must be
configured for the same sample rate as the DSP. Sample-rate conversion functions are available to support flexible
interconnectivity; see Section 4.3.14.
The hexadecimal numbers in Fig. 4-22 indicate the corresponding x_SRCn setting for selection of that signal as an input
to another digital-core function.
DS1137PP1
61
CS47L15
4.3 Digital Core
The sample rate for the DSP functions is configured using the DSP1_RATE field; see Table 4-24. Sample-rate conversion
is required when routing the DSP signal paths to any signal chain that is configured for a different sample rate.
The DSP1_RATE field must not be changed if any of the respective x_SRCn fields is nonzero. The associated x_SRCn
fields must be cleared before writing new values to DSP1_RATE. A minimum delay of 125 s must be allowed between
clearing the x_SRCn fields and writing to the DSP1_RATE field. See Table 4-24 for details.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the required
DSP mixing functions. If the frequency is too low, an attempt to enable a DSP mixer path fails. Note that active signal paths
are not affected under such circumstances.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
4.3.8
S/PDIF Output Generator
The CS47L15 incorporates an IEC-60958-3–compatible S/PDIF output generator, as shown in Fig. 4-23; this provides a
stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full control over the S/PDIF validity bits and channel
status information.
The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume control is provided
for each path. The *TX1 and *TX2 fields control Channels A and B (respectively) of the S/PDIF output.
The S/PDIF signal can be output directly on a GPIO pin. See Section 4.11 to configure a GPIO pin for this function.
Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal-processing functions within the
CS47L15 digital core.
…
SPDIF1TX1_SRC
Channel A
SPDIF1TX1_VOL
S/PDIF
Channel B SPD1_ENA
SPD1_RATE
…
SPDIF1TX2_SRC
GPIO
(GPn_FN = 0x04C)
SPDIF1TX2_VOL
Figure 4-23. Digital-Core S/PDIF Output Generator
The S/PDIF input control fields (see Fig. 4-23) are located at register addresses R2048–R2057 (0x0800–0x0809).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the two S/PDIF channels. Note that the selected input sources must be
synchronized to the SYSCLK clocking domain, and configured for the same sample rate as the S/PDIF generator.
Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.14.
The sample rate of the S/PDIF generator is configured using SPD1_RATE; see Table 4-24. The S/PDIF transmitter
supports sample rates in the range 32–192 kHz. Note that sample-rate conversion is required when linking the S/PDIF
generator to any signal chain that is configured for a different sample rate.
The SPD1_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn
fields must be cleared before writing a new value to SPD1_RATE. A minimum delay of 125 s must be allowed between
clearing the x_SRCn fields and writing to SPD1_RATE. See Table 4-24 for details.
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The S/PDIF generator is enabled by setting SPD1_ENA, as described in Table 4-19.
The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit width can be
accommodated. The validity bits and the channel status bits in the S/PDIF data are configured using the corresponding
fields in registers R1474 (0x5C2) to R1477 (0x5C5).
Refer to the S/PDIF specification (IEC 60958-3 Digital Audio Interface - Consumer) for full details of the S/PDIF protocol
and configuration parameters.
Table 4-19. S/PDIF Output Generator Control
Register Address
R1474 (0x05C2)
SPD1_TX_Control
Bit
13
12
0
15:8
7:6
5:3
2
1
0
R1476 (0x05C4)
15:12
SPD1_TX_
11:8
Channel_Status_2 7:4
3:0
R1477 (0x05C5)
11:8
SPD1_TX_
7:5
Channel_Status_3
4
3:2
1:0
R1475 (0x05C3)
SPD1_TX_
Channel_Status_1
Label
SPD1_VAL2
SPD1_VAL1
SPD1_ENA
Default
0
0
0
SPD1_CATCODE[7:0]
SPD1_CHSTMODE[1:0]
SPD1_PREEMPH[2:0]
SPD1_NOCOPY
SPD1_NOAUDIO
SPD1_PRO
SPD1_FREQ[3:0]
SPD1_CHNUM2[3:0]
SPD1_CHNUM1[3:0]
SPD1_SRCNUM[3:0]
SPD1_ORGSAMP[3:0]
SPD1_TXWL[2:0]
SPD1_MAXWL
SPD1_SC31_30[1:0]
SPD1_CLKACU[1:0]
0x00
00
000
0
0
0
0000
1011
0000
0001
0000
000
0
00
00
Description
S/PDIF Validity (Subframe B)
S/PDIF Validity (Subframe A)
S/PDIF Generator Enable
0 = Disabled
1 = Enabled
S/PDIF Category code
S/PDIF Channel Status mode
S/PDIF Preemphasis mode
S/PDIF Copyright status
S/PDIF Audio/nonaudio indication
S/PDIF Consumer Mode/Professional Mode
S/PDIF Indicated sample frequency
S/PDIF Channel number (Subframe B)
S/PDIF Channel number (Subframe A)
S/PDIF Source number
S/PDIF Original sample frequency
S/PDIF Audio sample word length
S/PDIF Maximum audio sample word length
S/PDIF Channel Status [31:30]
Transmitted Clock accuracy
The CS47L15 automatically checks to confirm whether the SYSCLK frequency is high enough to support the digital mixer
paths. If an attempt is made to enable the S/PDIF generator, and there are insufficient SYSCLK cycles to support it, the
attempt does not succeed. Note that any active signal paths are unaffected under such circumstances.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
4.3.9
Tone Generator
The CS47L15 incorporates a tone generator that can be used for beep functions through any of the audio signal paths.
The tone generator provides two 1-kHz outputs, with configurable phase relationship, offering flexibility to create
differential signals or test scenarios.
1-kHz
Tone Generator
Tone Generator 1 (0x04)
Tone Generator 2 (0x05)
TONE1_ENA
TONE2_ENA
TONE_OFFSET
TONE_RATE
TONE1_OVD
TONE1_LVL
TONE2_OVD
TONE2_LVL
Figure 4-24. Digital-Core Tone Generator
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4.3 Digital Core
The tone generator outputs can be selected as input to any of the digital mixers or signal-processing functions within the
CS47L15 digital core. The hexadecimal numbers in Fig. 4-24 indicate the corresponding x_SRCn setting for selection of
that signal as an input to another digital-core function.
The sample rate for the tone generator is configured using TONE_RATE. See Table 4-24. Note that sample-rate
conversion is required when routing the tone generator outputs to any signal chain that is configured for a different sample
rate.
The tone generator outputs are enabled by setting the TONE1_ENA and TONE2_ENA bits as described in Table 4-20.
The phase relationship is configured using TONE_OFFSET.
The tone generator outputs can also provide a configurable DC signal level, for use as a test signal. The DC output is
selected using the TONEn_OVD bits, and the DC signal amplitude is configured using the TONEn_LVL fields, as
described in Table 4-20.
Table 4-20. Tone Generator Control
Register Address Bit
Label
Default
Description
R32 (0x0020)
9:8 TONE_
00
Tone Generator Phase Offset. Sets the phase of Tone Generator 2 relative to Tone
OFFSET[1:0]
Generator 1
Tone_Generator_1
00 = 0 degrees (in phase)
01 = 90 degrees ahead
10 = 180 degrees ahead
11 = 270 degrees ahead
5 TONE2_
0
Tone Generator 2 Override
OVD
0 = Disabled (1-kHz tone output)
1 = Enabled (DC signal output)
The DC signal level, when selected, is configured using TONE2_LVL[23:0]
4 TONE1_
0
Tone Generator 1 Override
OVD
0 = Disabled (1-kHz tone output)
1 = Enabled (DC signal output)
The DC signal level, when selected, is configured using TONE1_LVL[23:0]
1 TONE2_ENA
0
Tone Generator 2 Enable
0 = Disabled
1 = Enabled
0 TONE1_ENA
0
Tone Generator 1 Enable
0 = Disabled
1 = Enabled
R33 (0x0021)
15:0 TONE1_
0x1000 Tone Generator 1 DC output level
LVL[23:8]
Tone_Generator_2
TONE1_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits
[19:0] contain the fractional portion.
The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1).
R34 (0x0022)
7:0 TONE1_
0x00 Tone Generator 1 DC output level
LVL[7:0]
Tone_Generator_3
TONE1_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits
[19:0] contain the fractional portion.
The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1).
R35 (0x0023)
15:0 TONE2_
0x1000 Tone Generator 2 DC output level
LVL[23:8]
Tone_Generator_4
TONE2_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits
[19:0] contain the fractional portion.
The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1).
R36 (0x0024)
7:0 TONE2_
0x00 Tone Generator 2 DC output level
LVL[7:0]
Tone_Generator_5
TONE2_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits
[19:0] contain the fractional portion.
The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1).
4.3.10 Noise Generator
The CS47L15 incorporates a white-noise generator that can be routed within the digital core. The main purpose of the
noise generator is to provide comfort noise in cases where silence (digital mute) is not desirable.
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4.3 Digital Core
White Noise
Generator
Noise Generator (0x0D)
NOISE_GEN_ENA
NOISE_GEN_GAIN
NOISE_GEN_RATE
Figure 4-25. Digital-Core Noise Generator
The noise generator can be selected as input to any of the digital mixers or signal-processing functions within the CS47L15
digital core. The hexadecimal number (0x0D) in Fig. 4-25 indicates the corresponding x_SRCn setting for selection of the
noise generator as an input to another digital-core function.
The sample rate for the noise generator is configured using the NOISE_GEN_RATE field. See Table 4-24. Note that
sample-rate conversion is required when routing the noise generator output to any signal chain that is configured for a
different sample rate.
The noise generator is enabled by setting NOISE_GEN_ENA, described in Table 4-21. The signal level is configured using
NOISE_GEN_GAIN.
Table 4-21. Noise Generator Control
Register Address
R160 (0x00A0)
Comfort_Noise_
Generator
Bit
5
Label
NOISE_GEN_
ENA
Default
0
4:0
NOISE_GEN_
GAIN[4:0]
0x00
Description
Noise Generator Enable
0 = Disabled
1 = Enabled
Noise generator signal level
0x00 = –114 dBFS
…(6-dB steps)
All other codes are reserved
0x01 = –108 dBFS
0x11 = –6 dBFS
0x02 = –102 dBFS
0x12 = 0 dBFS
4.3.11 Haptic Signal Generator
The CS47L15 incorporates a signal generator for use with haptic devices (e.g., mechanical vibration actuators). The haptic
signal generator is compatible with both eccentric rotating mass (ERM) and linear resonant actuator (LRA) haptic devices.
The haptic signal generator is highly configurable, and includes the capability to execute a programmable event profile
comprising three distinct operating phases.
The resonant frequency of the haptic signal output (for LRA devices) is selectable, providing support for many different
actuator components.
The haptic signal generator is a digital signal generator, which is incorporated within the digital core of the CS47L15. The
haptic signal may be routed, via one of the digital-core output mixers, to a Class D speaker output for connection to the
external haptic device, as shown in Fig. 4-26. Note that the digital PDM output paths may also be used for haptic signal
output.
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4.3 Digital Core
Digital Core Output Mixer
Haptic Signal
Generator
Haptic Output
(0x06)
HAP_ACT
HAP_CTRL
ONESHOT_TRIG
LRA_FREQ
HAP_RATE
Output
Volume
+
DAC
Class D Speaker
Driver
DAC
OUTnxMIX_SRCn
OUTnxMIX_VOLn
Haptic
Device
Figure 4-26. Digital-Core Haptic Signal Generator
The hexadecimal number (0x06) in Fig. 4-26 indicates the corresponding x_SRCn setting for selection of the haptic signal
generator as an input to another digital-core function.
The haptic signal generator is selected as input to one of the digital-core output mixers by setting the x_SRCn field of the
applicable output mixer to 0x06.
The sample rate for the haptic signal generator is configured using the HAP_RATE field. See Table 4-22. Note that
sample-rate conversion is required when routing the haptic signal generator output to any signal chain that is configured
for a different sample rate.
The haptic signal generator is configured for an ERM or LRA actuator using the HAP_ACT bit. The required resonant
frequency is configured using the LRA_FREQ field. Note that the resonant frequency is only applicable to LRA actuators.
The signal generator can be enabled in continuous mode or configured for one-shot mode using the HAP_CTRL field, as
described in Table 4-22. In one-shot mode, the output is triggered by writing to the ONESHOT_TRIG bit.
In one-shot mode, the signal generator profile comprises the distinct phases (1, 2, 3). The duration and intensity of each
output phase is programmable.
In continuous mode, the signal intensity is controlled using the PHASE2_INTENSITY field only.
In the case of an ERM actuator (HAP_ACT = 0), the haptic output is a DC signal level, which may be positive or negative,
as selected by the x_INTENSITY fields.
For an LRA actuator (HAP_ACT = 1), the haptic output is an AC signal; selecting a negative signal level corresponds to a
180° phase inversion. In some applications, phase inversion may be desirable during the final phase, to halt the physical
motion of the haptic device.
Table 4-22. Haptic Signal Generator Control
Register Address Bit
Label
R144 (0x0090)
4 ONESHOT_
TRIG
Haptics_Control_1
3:2 HAP_CTRL[1:0]
1
HAP_ACT
R145 (0x0091)
14:0 LRA_
FREQ[14:0]
Haptics_Control_2
66
Default
Description
0
Haptic One-Shot Trigger. Writing 1 starts the one-shot profile (i.e., Phase 1, Phase 2,
Phase 3)
00
Haptic Signal Generator Control
00 = Disabled
10 = One-Shot
01 = Continuous
11 = Reserved
0
Haptic Actuator Select
0 = Eccentric rotating mass (ERM)
1 = Linear resonant actuator (LRA)
0x7FFF Haptic Resonant Frequency. Selects the haptic signal frequency (LRA actuator only,
HAP_ACT = 1)
Haptic Frequency (Hz) = System Clock/(2 x (LRA_FREQ+1)), where System Clock =
6.144 MHz or 5.6448 MHz, derived by division from SYSCLK.
Valid for haptic frequency in the range 100–250 Hz
For 6.144-MHz System Clock:
For 5.6448-MHz System Clock:
0x77FF = 100 Hz
0x6E3F = 100 Hz
0x4491 = 175 Hz
0x3EFF = 175 Hz
0x2FFF = 250 Hz
0x2C18 = 250 Hz
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4.3 Digital Core
Table 4-22. Haptic Signal Generator Control (Cont.)
Register Address Bit
Label
R146 (0x0092)
7:0 PHASE1_
INTENSITY[7:0]
Haptics_phase_1_
intensity
Default
Description
0x00
Haptic Output Level (Phase 1). Selects the signal intensity of Phase 1 in one-shot
mode.
Coded as 2’s complement. Range is ± Full Scale (FS).
For ERM actuator, this selects the DC signal level for the haptic output.
For LRA actuator, this selects the AC peak amplitude; negative values correspond to a
180° phase shift.
R147 (0x0093)
8:0 PHASE1_
0x000 Haptic Output Duration (Phase 1). Selects the duration of Phase 1 in one-shot mode.
DURATION[8:0]
Haptics_Control_
0x000 = 0 ms
0x002 = 1.25 ms
0x1FF = 319.375 ms
phase_1_duration
0x001 = 0.625 ms
… (0.625-ms steps)
R148 (0x0094)
7:0 PHASE2_
0x00
Haptic Output Level (Phase 2)
INTENSITY[7:0]
Haptics_phase_2_
Selects the signal intensity in Continuous mode or Phase 2 of one-shot mode.
intensity
Coded as 2’s complement. Range is ± Full Scale (FS).
For ERM actuator, this selects the DC signal level for the haptic output.
For LRA actuator, this selects the AC peak amplitude; negative values correspond to a
180° phase shift.
R149 (0x0095)
10:0 PHASE2_
0x000 Haptic Output Duration (Phase 2). Selects the duration of Phase 2 in one-shot mode.
DURATION[10:0]
Haptics_phase_2_
0x000 = 0 ms
0x002 = 1.25 ms
0x7FF = 1279.375 ms
duration
0x001 = 0.625 ms
… (0.625-ms steps)
R150 (0x0096)
7:0 PHASE3_
0x00
Haptic Output Level (Phase 3). Selects the signal intensity of Phase 3 in one-shot
INTENSITY[7:0]
mode.
Haptics_phase_3_
intensity
Coded as 2’s complement. Range is ± Full Scale (FS).
For ERM actuator, this selects the DC signal level for the haptic output.
For LRA actuator, this selects the AC peak amplitude; negative values correspond to a
180° phase shift.
R151 (0x0097)
8:0 PHASE3_
0x000 Haptic Output Duration (Phase 3). Selects the duration of Phase 3 in one-shot mode.
DURATION[8:0]
Haptics_phase_3_
0x000 = 0 ms
0x002 = 1.25 ms
0x1FF = 319.375 ms
duration
0x001 = 0.625 ms
… (0.625-ms steps)
R152 (0x0098)
0 ONESHOT_STS
0
Haptic One-Shot status
Haptics_Status
0 = One-Shot event not in progress
1 = One-Shot event in progress
4.3.12 PWM Generator
The CS47L15 incorporates two PWM signal generators as shown in Fig. 4-27. The duty cycle of each PWM signal can be
modulated by an audio source, or can be set to a fixed value using a control register setting.
A four-input mixer is associated with each PWM generator. The four input sources are selectable in each case, and
independent volume control is provided for each path.
PWM signal generators can be output directly on a GPIO pin. See Section 4.11 to configure a GPIO pin for this function.
Note that the PWM signal generators cannot be selected as input to the digital mixers or signal-processing functions within
the CS47L15 digital core.
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4.3 Digital Core
When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer .
When PWMn_OVD = 1, the PWM duty cycle is set by PWMn _LVL.
PWM sample rate and clocking frequency are selected using PWM _RATE and PWM_CLK_SEL.
…
PWM1MIX_SRC1
PWM1MIX_VOL1
…
PWM1MIX_SRC2
PWM1MIX_VOL2
…
PWM1MIX_SRC3
PWM1MIX_VOL3
…
PWM1MIX_SRC4
PWM1MIX_VOL4
+
PWM1
PWM1_ENA
PWM1_OVD
PWM1_LVL
GPIO
(GPn_FN = 0x048)
PWM_RATE
PWM_CLK_SEL
…
PWM2MIX_SRC1
PWM2MIX_VOL1
…
PWM2MIX_SRC2
PWM2MIX_VOL2
…
PWM2MIX_SRC3
PWM2MIX_VOL3
…
PWM2MIX_SRC4
PWM2MIX_VOL4
+
PWM2
PWM2_ENA
PWM2_OVD
PWM2_LVL
GPIO
(GPn_FN = 0x049)
Figure 4-27. Digital-Core PWM Generator
The PWM1 and PWM2 mixer control fields (see Fig. 4-27) are located at register addresses R1600–R1615
(0x0640–0x064F).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be
configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are
available to support flexible interconnectivity; see Section 4.3.14.
The PWM sample rate (cycle time) is configured using PWM_RATE. See Table 4-24. Note that sample-rate conversion is
required when linking the PWM generators to any signal chain that is configured for a different sample rate.
The PWM_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn
fields must be cleared before writing a new value to PWM_RATE. A minimum delay of 125 s must be allowed between
clearing the x_SRCn fields and writing to PWM_RATE. See Table 4-24 for details.
The PWM generators are enabled by setting PWM1_ENA and PWM2_ENA, respectively, as described in Table 4-23.
Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path;
a 4-input mixer is associated with each PWM generator, as shown in Fig. 4-27.
When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the
duty cycle ratio is configurable using the PWMn_LVL fields.
The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, the highest available
setting should be used. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK.
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Table 4-23. PWM Generator Control
Register Address Bit
Label
R48 (0x0030)
10:8 PWM_CLK_
SEL[2:0]
PWM_Drive_1
Default
000
5
PWM2_OVD
0
4
PWM1_OVD
0
1
PWM2_ENA
0
0
PWM1_ENA
0
R49 (0x0031)
PWM_Drive_2
9:0
PWM1_LVL[9:0]
0x100
R50 (0x0032)
PWM_Drive_3
9:0
PWM2_LVL[9:0]
0x100
Description
PWM Clock Select
000 = 6.144 MHz (5.6448 MHz)
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
All other codes are reserved.
The frequencies in brackets apply for 44.1 kHz–related sample rates only.
PWM_CLK_SEL controls the resolution of the PWM generator; higher settings
correspond to higher resolution.
The PWM Clock must be less than or equal to SYSCLK.
PWM2 Generator Override
0 = Disabled (PWM duty cycle is controlled by audio source)
1 = Enabled (PWM duty cycle is controlled by PWM2_LVL).
PWM1 Generator Override
0 = Disabled (PWM1 duty cycle is controlled by audio source)
1 = Enabled (PWM1 duty cycle is controlled by PWM1_LVL).
PWM2 Generator Enable
0 = Disabled
1 = Enabled
PWM1 Generator Enable
0 = Disabled
1 = Enabled
PWM1 Override Level. Sets the PWM1 duty cycle when PWM1_OVD = 1.
Coded as 2’s complement.
0x000 = 50% duty cycle
0x200 = 0% duty cycle
PWM2 Override Level. Sets the PWM2 duty cycle when PWM2_OVD = 1.
Coded as 2’s complement.
0x000 = 50% duty cycle
0x200 = 0% duty cycle
The CS47L15 automatically checks to confirm that the SYSCLK frequency is high enough to support the digital mixer
paths. If an attempt is made to enable a PWM signal mixer path, without sufficient SYSCLK cycles to support it, the attempt
fails. Note that any signal paths that are already active are not affected under such circumstances.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
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4.3 Digital Core
4.3.13 Sample-Rate Control
The CS47L15 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided
to allow digital audio to be routed between interfaces operating at different sample rates.
The master clock reference for the audio signal paths is SYSCLK, as described in Section 4.13. Every digital signal path
must be synchronized to SYSCLK.
Up to three different sample rates may be in use at any time on the CS47L15; all of these sample rates must be
synchronized to SYSCLK.
Sample-rate conversion is required when routing any audio path between digital functions that are configured for different
sample rates.
There are two isochronous sample-rate converters: ISRC1 and ISRC2. Each ISRC supports two-way, four-channel
conversion paths between sample rates on the SYSCLK domain. The ISRCs are described in Section 4.3.14.
The sample rate of different blocks within the CS47L15 digital core are controlled as shown in Fig. 4-28. The x_RATE fields
select the applicable sample rate for each respective group of digital functions.
The x_RATE fields must not be changed if any of the x_SRCn fields associated with the respective functions is nonzero.
The associated x_SRCn fields must be cleared before writing new values to the x_RATE fields. A minimum delay of 125 s
must be allowed between clearing the x_SRCn fields and writing to the associated x_RATE fields. See Table 4-24 for
details.
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4.3 Digital Core
Silence (mute)
DSP1 – DSP1_RATE
AEC1 Loopback
AEC2 Loopback
DSP1 Channel 1
+
OUT_RATE
DSP1 Channel 2
IN1L signal path
DSP1 Channel 3
DSP Core
IN1R signal path
DSP1 Channel 4
IN2L signal path
+
DSP1 Channel 5
IN2R signal path
DSP1 Channel 6
IN_RATE
ISRC2
ISRC1
ISRCn INT1
OUT_RATE
OUT5
OUT1
OUT4
ISRCn INT2
ISRCn INT3
Isochronous
Sample Rate
Converter (ISRC)
ISRCn DEC1
ISRCn INT4
+
Class D
Speaker
Output
Path
+
OUTnL output
Stereo
Output
Paths
OUT4 output
ISRCn DEC2
+
ISRCn DEC3
OUTnR output
ISRCn DEC4
ISRCn_FSL
ISRCn_FSH
PWM_RATE
PWM2
PWM1
+
PWM
FX_RATE
LHPF4
LHPF3
LHPF2
LHPF1
(GPIO pin)
+
LHPF
SPD1_RATE
S/PDIF
(GPIO pin)
HAP_RATE
Haptic Signal
Generator
AIF3 – AIF3_RATE
AIF2 – AIF2_RATE
AIF1 – AIF1_RATE
+
+
EQ4
EQ3
EQ2
EQ1
+
EQ
+
EQn
DRC2
DRC1
+
+
DRCn
Left
Noise Generator
AIFn TX.. output
TONE_RATE
Tone Generator 1
+
AIFn TX.. output
etc...
DRC
Tone Generator
AIFn TX2 output
Haptic Output
NOISE_GEN_RATE
White Noise
Generator
AIFn TX1 output
LHPFn
AIFn RX1
DRCn
Right
AIF1 = 6 input , 6 output
AIF2 = 4 input , 4 output
AIF3 = 2 input , 2 output
AIFn RX2
AIFn RX..
AIFn RX..
Tone Generator 2
Figure 4-28. Digital-Core Sample-Rate Control
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The input signal paths may be selected as input to the digital mixers or signal-processing functions. The sample rate for
the input signal paths is configured using the IN_RATE field.
The output signal paths are derived from the respective output mixers. The sample rate for the output signal paths is
configured using OUT_RATE. The sample rate of the AEC loop-back path is also set by OUT_RATE.
The AIFn RX inputs may be selected as input to the digital mixers or signal-processing functions. The AIFn TX outputs are
derived from the respective output mixers. The sample rates for digital audio interfaces (AIF1–AIF3) are configured using
the AIFn_RATE fields (where n identifies the applicable AIF 1, 2, or 3) respectively.
The EQ, DRC, and LHPF functions can be enabled in any signal path within the digital core. The sample rate for these
functions is configured using FX_RATE. Note that the EQ, DRC, and LHPF functions must all be configured for the same
sample rate.
The DSP functions can be enabled in any signal path within the digital core. The applicable sample rate is configured using
the DSP1_RATE field.
The S/PDIF transmitter can be enabled on a GPIO pin. Stereo inputs to this function can be configured from any of the
digital-core inputs, mixers, or signal-processing functions. The sample rate of the S/PDIF transmitter is configured using
SPD1_RATE.
The tone generators and noise generator can be selected as input to any of the digital mixers or signal-processing
functions. The sample rates for these sources are configured using the TONE_RATE and NOISE_GEN_RATE fields,
respectively.
The haptic signal generator can be used to control an external vibe actuator, which can be driven directly by the Class D
speaker output. The sample rate for the haptic signal generator is configured using HAP_RATE.
The PWM signal generators can be modulated by an audio source, derived from the associated signal mixers. The sample
rate (cycle time) for the PWM signal generators is configured using PWM_RATE.
The sample-rate control registers are described in Table 4-24. Refer to the field descriptions for details of the valid
selections in each case. The control registers associated with the ISRCs are described in Table 4-25.
Note that 32-bit register addressing is used from R12888 (0x3000) upwards; 16-bit format is used otherwise. The registers
noted in Table 4-24 contain a mixture of 16-bit and 32-bit register addresses.
Table 4-24. Digital-Core Sample-Rate Control
Register Address Bit
Label
R32 (0x0020)
14:11 TONE_RATE[3:0]
Tone_Generator_1
R48 (0x0030)
PWM_Drive_1
14:11 PWM_RATE[3:0]
R144 (0x0090)
14:11 HAP_RATE[3:0]
Haptics_Control_1
72
Default
Description
0000 Tone Generator Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
0000 PWM Frequency (sample rate)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
All PWMnMIX_SRCm fields must be cleared before changing PWM_RATE.
0000 Haptic Signal Generator Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
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4.3 Digital Core
Table 4-24. Digital-Core Sample-Rate Control (Cont.)
Register Address Bit
Label
R160 (0x00A0)
14:11 NOISE_GEN_
RATE[3:0]
Comfort_Noise_
Generator
R776 (0x0308)
Input_Rate
14:11 IN_RATE[3:0]
R1032 (0x0408)
Output_Rate_1
14:11 OUT_RATE[3:0]
R1283 (0x0503)
AIF1_Rate_Ctrl
R1347 (0x0543)
AIF2_Rate_Ctrl
R1411 (0x0583)
AIF3_Rate_Ctrl
14:11 AIF1_RATE[3:0]
R1474 (0x05C2)
SPD1_TX_Control
14:11 AIF2_RATE[3:0]
14:11 AIF3_RATE[3:0]
7:4
SPD1_RATE[3:0]
R3584 (0x0E00)
FX_Ctrl1
14:11 FX_RATE[3:0]
R1048064 (0x0F_
FE00)
DSP1_Config_1
14:11 DSP1_RATE[3:0]
Default
Description
0000 Noise Generator Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
0000 Input Signal Paths Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
If 384 kHz/768 kHz DMIC rate is selected (IN1_OSR = 01X), the input paths
sample rate is valid up to 48 kHz/96 kHz respectively.
0000 Output Signal Paths Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
All OUTnxMIX_SRCm fields must be cleared before changing OUT_RATE.
0000 AIFn Audio Interface Sample Rate
0000 = SAMPLE_RATE_1
0000 0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
0000 All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
All AIFnTXMIX_SRCm fields must be cleared before changing AIFn_RATE.
0000 S/PDIF Transmitter Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 32–192 kHz.
All SPDIF1TXn_SRC fields must be cleared before changing SPD1_RATE.
0000 FX Sample Rate (EQ, LHPF, DRC)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
All EQnMIX_SRCm, DRCnxMIX_SRCm, and LHPFnMIX_SRCm fields must be
cleared before changing FX_RATE.
0000 DSP1 Sample Rate
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8–192 kHz.
All DSP1xMIX_SRCm fields must be cleared before changing DSP1_RATE.
4.3.14 Isochronous Sample-Rate Converter (ISRC)
The CS47L15 supports multiple signal paths through the digital core. The ISRCs provide sample-rate conversion between
synchronized sample rates on the SYSCLK clock domain.
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There are two ISRCs on the CS47L15. Each ISRC provides four signal paths between two different sample rates, as
shown in Fig. 4-29. The sample rates associated with each ISRC can each be set equal to SAMPLE_RATE_1, SAMPLE_
RATE_2, or SAMPLE_RATE_3. See Section 4.13 for details of the sample-rate control registers.
Each ISRC supports sample rates in the range 8–192 kHz. The higher of the sample rates associated with each ISRC
must be an integer multiple of the lower sample rate; all possible integer ratios are supported (i.e., up to 24).
Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where
n identifies the applicable ISRC 1 or 2). Note that, in each case, the higher of the two sample rates must be selected by
ISRCn_FSH.
The ISRCn_FSL and ISRCn_FSH fields must not be changed if any of the respective x_SRCn fields is nonzero. The
associated x_SRCn fields must be cleared before writing new values to ISRCn_FSL or ISRCn_FSH. A minimum delay of
125 s must be allowed between clearing the x_SRCn fields and writing to the associated ISRCn_FSL or ISRCn_FSH
fields. See Table 4-25 for details.
The ISRC signal paths are enabled using the ISRCn_INTm_ENA and ISRCn_DECm_ENA bits, as follows:
•
The ISRCn interpolation paths (increasing sample rate) are enabled by setting the ISRCn_INTm_ENA bits, (where
m identifies the applicable channel).
•
The ISRCn decimation paths (decreasing sample rate) are enabled by setting the ISRCn_DECm_ENA bits.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the
commanded ISRC and digital mixing functions. If the frequency is too low, an attempt to enable an ISRC signal path fails.
Note that active signal paths are not affected under such circumstances.
The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error
condition occurs, these bits indicate which mixers have been enabled.
The ISRC signal paths and control registers are shown in Fig. 4-29.
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4.3 Digital Core
ISRC provides sample-rate conversions between synchronized sample rates on SYSCLK clock domain .
ISRCn_FSL identifies the lower of the two sample rates.
ISRCn_FSH identifies the higher of the two sample rates.
ISRCn_FSL
ISRCn_FSH
…
ISRCnINT1_SRC
ISRCn_INT1_ENA
ISRC1 INT1 (A0h)
ISRC2 INT1 (A8h)
…
ISRCnINT2_SRC
ISRCn_INT2_ENA
ISRC1 INT2 (A1h)
ISRC2 INT2 (A9h)
…
ISRCnINT3_SRC
ISRCn_INT3_ENA
ISRC1 INT3 (A2h)
ISRC2 INT3 (AAh)
…
ISRCnINT4_SRC
ISRCn_INT4_ENA
ISRC1 INT4 (A3h)
ISRC2 INT4 (ABh)
ISRC1 DEC1 (A4h)
ISRC2 DEC1 (ACh)
ISRCn_DEC1_ENA
…
ISRCnDEC1_SRC
ISRC1 DEC2 (A5h)
ISRC2 DEC2 (ADh)
ISRCn_DEC2_ENA
…
ISRCnDEC2_SRC
ISRC1 DEC3 (A6h)
ISRC2 DEC3 (AEh)
ISRCn_DEC3_ENA
…
ISRCnDEC3_SRC
ISRC1 DEC4 (A7h)
ISRC2 DEC4 (AFh)
ISRCn_DEC4_ENA
…
ISRCnDEC4_SRC
CS47L15 supports two ISRC blocks, i.e., n = 1 or 2
Figure 4-29. Isochronous Sample-Rate Converters (ISRCs)
The ISRC input control fields (see Fig. 4-29) are located at register addresses R2816–R2936 (0x0B00–0x0B78).
The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are
provided in Table 4-10.
The x_SRC fields select the input sources for the respective ISRC processing blocks. Note that the selected input sources
must be configured for the same sample rate as the ISRC to which they are connected.
The hexadecimal numbers in Fig. 4-29 indicate the corresponding x_SRC setting for selection of that signal as an input to
another digital-core function.
The register bits associated with the ISRCs are described in Table 4-25.
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Table 4-25. Digital-Core ISRC Control
Register Address Bit
Label
R3824 (0x0EF0)
14:11 ISRC1_FSH[3:0]
ISRC1_CTRL_1
R3825 (0x0EF1)
ISRC1_CTRL_2
R3826 (0x0EF2)
ISRC1_CTRL_3
R3827 (0x0EF3)
ISRC2_CTRL_1
76
14:11 ISRC1_FSL[3:0]
Default
0000
0000
15
ISRC1_INT1_ENA
0
14
ISRC1_INT2_ENA
0
13
ISRC1_INT3_ENA
0
12
ISRC1_INT4_ENA
0
9
ISRC1_DEC1_
ENA
0
8
ISRC1_DEC2_
ENA
0
7
ISRC1_DEC3_
ENA
0
6
ISRC1_DEC4_
ENA
0
14:11 ISRC2_FSH[3:0]
0000
Description
ISRC1 High Sample Rate (Sets the higher of the ISRC1 sample rates)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8 kHz to 192 kHz.
All ISRC1_DECn_SRC fields must be cleared before changing ISRC1_FSH.
ISRC1 Low Sample Rate (Sets the lower of the ISRC1 sample rates)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8 kHz to 192 kHz.
All ISRC1_INTn_SRC fields must be cleared before changing ISRC1_FSL.
ISRC1 INT1 Enable (Interpolation Channel 1 path from ISRC1_FSL rate to
ISRC1_FSH rate)
0 = Disabled
1 = Enabled
ISRC1 INT2 Enable (Interpolation Channel 2 path from ISRC1_FSL rate to
ISRC1_FSH rate)
0 = Disabled
1 = Enabled
ISRC1 INT3 Enable (Interpolation Channel 3 path from ISRC1_FSL rate to
ISRC1_FSH rate)
0 = Disabled
1 = Enabled
ISRC1 INT4 Enable (Interpolation Channel 4 path from ISRC1_FSL rate to
ISRC1_FSH rate)
0 = Disabled
1 = Enabled
ISRC1 DEC1 Enable (Decimation Channel 1 path from ISRC1_FSH rate to
ISRC1_FSL rate)
0 = Disabled
1 = Enabled
ISRC1 DEC2 Enable (Decimation Channel 2 path from ISRC1_FSH rate to
ISRC1_FSL rate)
0 = Disabled
1 = Enabled
ISRC1 DEC3 Enable (Decimation Channel 3 path from ISRC1_FSH rate to
ISRC1_FSL rate)
0 = Disabled
1 = Enabled
ISRC1 DEC4 Enable (Decimation Channel 4 path from ISRC1_FSH rate to
ISRC1_FSL rate)
0 = Disabled
1 = Enabled
ISRC2 High Sample Rate (Sets the higher of the ISRC2 sample rates)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8 kHz to 192 kHz.
All ISRC2_DECn_SRC fields must be cleared before changing ISRC2_FSH.
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4.4 DSP Firmware Control
Table 4-25. Digital-Core ISRC Control (Cont.)
Register Address Bit
Label
R3828 (0x0EF4)
14:11 ISRC2_FSL[3:0]
ISRC2_CTRL_2
R3829 (0x0EF5)
ISRC2_CTRL_3
Default
0000
15
ISRC2_INT1_ENA
0
14
ISRC2_INT2_ENA
0
13
ISRC2_INT3_ENA
0
12
ISRC2_INT4_ENA
0
9
ISRC2_DEC1_
ENA
0
8
ISRC2_DEC2_
ENA
0
7
ISRC2_DEC3_
ENA
0
6
ISRC2_DEC4_
ENA
0
Description
ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates)
0000 = SAMPLE_RATE_1
0001 = SAMPLE_RATE_2
0010 = SAMPLE_RATE_3
All other codes are reserved.
The selected sample rate is valid in the range 8 kHz to 192 kHz.
All ISRC2_INTn_SRC fields must be cleared before changing ISRC2_FSL.
ISRC2 INT1 Enable (Interpolation Channel 1 path from ISRC2_FSL rate to
ISRC2_FSH rate)
0 = Disabled
1 = Enabled
ISRC2 INT2 Enable (Interpolation Channel 2 path from ISRC2_FSL rate to
ISRC2_FSH rate)
0 = Disabled
1 = Enabled
ISRC2 INT3 Enable (Interpolation Channel 3 path from ISRC2_FSL rate to
ISRC2_FSH rate)
0 = Disabled
1 = Enabled
ISRC2 INT4 Enable (Interpolation Channel 4 path from ISRC2_FSL rate to
ISRC2_FSH rate)
0 = Disabled
1 = Enabled
ISRC2 DEC1 Enable (Decimation Channel 1 path from ISRC2_FSH rate to
ISRC2_FSL rate)
0 = Disabled
1 = Enabled
ISRC2 DEC2 Enable (Decimation Channel 2 path from ISRC2_FSH rate to
ISRC2_FSL rate)
0 = Disabled
1 = Enabled
ISRC2 DEC3 Enable (Decimation Channel 3 path from ISRC2_FSH rate to
ISRC2_FSL rate)
0 = Disabled
1 = Enabled
ISRC2 DEC4 Enable (Decimation Channel 4 path from ISRC2_FSH rate to
ISRC2_FSL rate)
0 = Disabled
1 = Enabled
4.4 DSP Firmware Control
The CS47L15 digital core incorporates one programmable digital signal processing (DSP) block, capable of running a wide
range of audio-enhancement functions. Different firmware configurations can be loaded onto the DSP, enabling the
CS47L15 to be customized for specific application requirements. Full read/write access to the device register map is
supported from the DSP core.
Examples of the DSP functions include multiband compressor (MBC), and the SoundClear™ suite of audio processing
algorithms. The DSP can be clocked at up to 150MHz, corresponding to 150 MIPS.
DSP firmware can be configured using software packages provided by Cirrus Logic. A software programming guide can
also be provided to assist users in developing their own software algorithms—please contact your Cirrus Logic
representative for further information.
To use the programmable DSP, the required firmware configuration must first be loaded onto the device by writing the
appropriate files to the CS47L15 register map. The firmware configuration comprises program, data, and coefficient
content. In some cases, the coefficient content must be derived using tools provided in the WISCE evaluation board control
software.
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Details of the DSP firmware memory registers are provided in Section 4.4.1. Note that the WISCE evaluation board control
software provides support for easy loading of program, data, and coefficient content onto the CS47L15. Please contact
your Cirrus Logic representative for more details of the WISCE evaluation board control software.
After loading the DSP firmware, the DSP functions must be enabled using the associated control fields.
The audio signal paths to and from the DSP processing block are configured as described in Section 4.3. Note that the
DSP firmware must be loaded and enabled before audio signal paths can be enabled.
4.4.1
DSP Firmware Memory and Register Mapping
The DSP firmware memory is programmed by writing to the registers referenced in Table 4-26. Note that clocking is not
required for access to the firmware registers by the host processor.
The CS47L15 program, data, and coefficient register memory space is described in Table 4-26. The full register map
listing is provided in Section 6.
The program firmware parameters are formatted as 40-bit words. For this reason, 3 x 32-bit register addresses are
required for every 2 x 40-bit words.
Table 4-26. DSP Program, Data, and Coefficient Registers
DSP Number
Description
DSP1
Program memory
X-Data memory
Y-Data memory
Coefficient memory
Register Address
0x08_0000–0x08_8FFE
0x0A_0000–0x0A_9FFE
0x0C_0000–0x0C_1FFE
0x0E_0000–0x0E_1FFE
Number of Registers
18432
20480
4096
4096
DSP Memory Size
12k x 40-bit words
20k x 24-bit words
4k x 24-bit words
4k x 24-bit words
The X-memory on the DSP supports read/write access to all register fields throughout the device, including the codec
control registers, and the other firmware-memory regions of DSP core itself. Access to the register address space is
supported using a number of register windows within the X-memory on the DSP.
Note that the register window space is additional to the X-data memory size described in Table 4-26.
Addresses 0xC000 to 0xDFFF in X-memory map directly to addresses 0x0000 to 0x1FFF in the device register space.
This fixed register window contains primarily the codec control registers; it also includes the virtual DSP control registers
(described in Section 4.4.7). Each X-memory address within this window maps onto one 16-bit register in the codec
memory space.
Four movable register windows are also provided, starting at X-memory addresses 0xF000, 0xF400, 0xF800, and 0xFC00
respectively. Each window represents 1024 addresses in the X-memory space. The start address, within the
corresponding device register space, for each window is configured using DSP1_EXT_[A/B/C/D]_PAGE (where A defines
the first window, B defines the second window, etc.).
Two mapping modes are supported and are selected using the DSP1_EXT_[A/B/C/D]_PSIZE16 bits for the respective
window. In 16-Bit Mode, each address within the window maps onto one 16-bit register in the device memory space; the
window equates to 1024 x 16-bit registers. In 32-Bit Mode, each address within the window maps onto two 16-bit registers
in the device memory space; the window equates to 1024 x 32-bit registers.
Note that the X-memory is only 24-bits wide; as a result, the upper 8 bits of the odd-numbered register addresses are not
mapped, and cannot be accessed, in 32-Bit Mode.
The DSP1_EXT_[A/B/C/D]_PAGE fields are defined with an LSB = 512. Accordingly, the base address of each window
must be aligned with 512-word boundaries. Note that the base addresses are entirely independent of each other; for
example, overlapping windows are permissible if required, and there is no requirement for the A/B/C/D windows to be at
incremental locations.
The register map window functions are shown in Fig. 4-30. Further information on the definition and usage of the DSP
firmware memories is provided in the software programming guide; contact your Cirrus Logic representative if required.
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Page D Base Address
0xFFFF
Register
Window D
Page C Base Address
0xFC00
0xF800
0xF400
Register
Window C
Register
Window B
Page B Base Address
Register
Window A
0xF000
Internal DSP Control
Page A Base Address
0xE000
Write Sequencer, DSP Peripherals, and DSP Firmware Address Space
4.4 DSP Firmware Control
Moveable
Register
Window D
Moveable
Register
Window C
Moveable
Register
Window B
Moveable
Register
Window A
Virtual DSP Ctrl
0x3000
0xD000
16-bits
CODEC Register
Address Space
0x2000
0xC000
X Data Memory
0x0000
24-bits
DSP X-Memory Map
0x0000
Fixed codec
Register Window
16-bits
Audio Hub Register Map
Figure 4-30. X-Data Memory Map
Note that the full CS47L15 register space is shown here as 16-bit width. (SPI/I2C register access uses 32-bit data width
at 0x3000 and above.) However, the window base address fields (DSP1_EXT_[A/B/C/D]_PAGE) are referenced to 16-bit
width, and 16-bit register mapping is shown. Hence, the device register map is shown here entirely as 16-bit width for ease
of explanation.
The control registers associated with the register map window functions are described in Table 4-27.
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Table 4-27. X-Data Memory and Clocking Control
Register Address
R1048148 (0xF_FE54)
DSP1_Ext_window_A
Bit
31
Label
DSP1_EXT_A_PSIZE16
15:0 DSP1_EXT_A_PAGE[15:0]
R1048150 (0xF_FE56)
DSP1_Ext_window_B
31
DSP1_EXT_B_PSIZE16
15:0 DSP1_EXT_B_PAGE[15:0]
R1048152 (0xF_FE58)
DSP1_Ext_window_C
31
DSP1_EXT_C_PSIZE16
15:0 DSP1_EXT_C_PAGE[15:0]
R1048154 (0xF_FE5A)
DSP1_Ext_window_D
31
DSP1_EXT_D_PSIZE16
15:0 DSP1_EXT_D_PAGE[15:0]
4.4.2
Default
Description
0
Register Window A page width select
0 = 32-bit
1 = 16-bit
Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.
0x0000 Sets the Base Address of Register Window A in X-memory.
Coded as LSB = 512 (0x200)
0
Register Window B page width select
0 = 32-bit
1 = 16-bit
Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.
0x0000 Sets the Base Address of Register Window B in X-memory.
Coded as LSB = 512 (0x200)
0
Register Window C page width select
0 = 32-bit
1 = 16-bit
Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.
0x0000 Sets the Base Address of Register Window C in X-memory.
Coded as LSB = 512 (0x200)
0
Register Window D page width select
0 = 32-bit
1 = 16-bit
Note that, in 32-Bit Mode, only the lower 24 bits can be accessed.
0x0000 Sets the Base Address of Register Window D in X-memory.
Coded as LSB = 512 (0x200)
DSP Memory Locking
The DSP core has the capability for read/write access to all register fields throughout the device, including the codec
control registers, DSP peripheral control registers, and the virtual DSP control registers. Access to these registers is
supported via the DSP X-memory (using the register windows), as described in Section 4.4.1.
The CS47L15 provides a register-locking feature that blocks DSP register-write attempts to invalid register regions,
preventing the firmware from making unintentional changes to register and memory contents. An interrupt event and
associated debug information are generated if any write-access attempt is blocked; this can be used to assist software
development and debug.
The register map and DSP firmware memories are partitioned into four regions; each region can be locked independently.
This allows full flexibility to lock different register/memory regions according to the applicable DSP firmware configuration.
The DSP has direct access to its own X-, Y-, Z-, and P- memories; this is always enabled and cannot be locked. Access
to the codec registers, DSP peripheral registers, and the virtual DSP registers is effected using the X-memory register
windows (fixed codec window, and four configurable windows)—write access to these locations is governed by the
register-locking configuration settings.
The virtual DSP registers occupy addresses within the codec register space; these registers represent one of the lockable
regions within the register map—two independent locks are provided for the codec and virtual DSP registers.
Note:
A DSP register window can be mapped onto the X-, Y-, Z-, or P- memory region of the DSP. In this event, write
access via that window is governed by the register locks, potentially blocking the DSP from accessing its own
memory. This is not the intended use of the register lock, however.
The lockable register/memory regions are defined in Table 4-28.
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Table 4-28. DSP Memory Locking Regions
Region
Region 0
Region 1
Region 2
Region 3
Description
Virtual DSP registers
Codec registers
DSP peripheral control registers
DSP1 memory
Register Address
0x00_1000–0x00_2FFF
0x00_0000–0x03_FFFE
0x04_0000–0x07_FFFE
0x08_0000–0x09_FFFE
Notes
Excludes memory lock and watchdog reset registers
Excludes virtual DSP registers
—
—
The register locks are controlled using the DSP1_CTRL_REGIONm_LOCK fields (where m identifies the register/memory
region). The associated lock determines whether the DSP core is granted write access to region m. To change the lock
status, two writes must be made to the respective register field:
•
Writing 0x5555, followed by 0xAAAA, sets the respective lock
•
Writing 0xCCCC, followed by 0x3333, clears the respective lock
The status of each lock can be read from the DSP1_CTRL_REGIONm_LOCK_STS bits.
Write access to the DSP1_CTRL_REGIONm_LOCK fields is always possible. This means that the DSP core always has
write access for configuring the memory-access locks.
The DSP memory locking function is an input to the interrupt control circuit and can be used to trigger an interrupt event
if an invalid register write is attempted—see Section 4.4.5. Additional status and control fields are provided for debug
purposes, as described in Section 4.4.6.
The control registers associated with the DSP memory locking functions are described in Table 4-29.
Table 4-29. DSP Memory Locking Control
Register Address
R1048164 (0xF_FE64)
DSP1_Region_lock_sts_0
R1048166 (0xF_FE66)
DSP1_Region_lock_1___
DSP1_Region_lock_0
R1048168 (0xF_FE68)
DSP1_Region_lock_3___
DSP1_Region_lock_2
Bit
3
2
1
0
31:16
Label
DSP1_CTRL_REGION3_LOCK_STS
DSP1_CTRL_REGION2_LOCK_STS
DSP1_CTRL_REGION1_LOCK_STS
DSP1_CTRL_REGION0_LOCK_STS
DSP1_CTRL_REGION1_LOCK[15:0]
15:0 DSP1_CTRL_REGION0_LOCK[15:0]
31:16 DSP1_CTRL_REGION3_LOCK[15:0]
15:0 DSP1_CTRL_REGION2_LOCK[15:0]
Default
0
0
0
0
See
Footnote 1
See
Footnote 1
See
Footnote 1
See
Footnote 1
Description
DSP1 memory region m lock status
0 = Unlocked
1 = Locked (write access is blocked)
DSP1 memory region m lock.
Write 0x5555, then 0xAAAA, to set the lock.
Write 0xCCCC, then 0x3333, to clear the lock.
1. Default is not applicable to these write-only fields
4.4.3
DSP Firmware Control
The configuration and control of the DSP firmware is described in the following subsections.
4.4.3.1 DSP Memory
The DSP memory (program, X-data, Y-data, and coefficient) is enabled by setting DSP1_MEM_ENA. This memory must
be enabled (DSP1_MEM_ENA = 1) for read/write access, code execution, and DMA functions. The DSP memory is
disabled, and the contents lost, whenever the DSP1_MEM_ENA bit is cleared.
The DSP1_MEM_ENA bit is not affected by software reset; it remains in its previous state under software reset conditions.
Accordingly, the DSP memory contents are maintained through software reset, provided DCVDD is held above its reset
threshold.
The DSP firmware memory is always cleared under power-on reset, hardware reset, and Sleep Mode conditions. See
Section 5.2 for a summary of the CS47L15 reset behavior.
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4.4 DSP Firmware Control
4.4.3.2 DSP Clocking
Clocking is required for the DSP processing block, when executing software or when supporting DMA functions. (Note that
clocking is not required for access to the firmware registers by the host processor.)
Clocking within the DSP is enabled and disabled automatically, as required by the DSP core and DMA channel status.
In normal operating conditions, the clock source for the DSP is derived from DSPCLK. See Section 4.13 for details of how
to configure DSPCLK. See Section 4.4.3.4 for supported clocking configurations when DSPCLK is not enabled.
The clock frequency for the DSP is selected using DSP1_CLK_FREQ_SEL. The DSP clock frequency must be less than
or equal to the DSPCLK frequency.
The DSP1_CLK_FREQ_STS field indicates the clock frequency for the DSP core. This can be used to confirm the clock
frequency, in cases where code execution has a minimum clock frequency requirement. The DSP1_CLK_FREQ_STS
field is only valid when the core is running code; typical usage of this field would be for the DSP core itself to read the clock
status and to take action as applicable, in particular, if the available clock does not meet the application requirements.
Note that, depending on the DSPCLK frequency and the available clock dividers, the DSP1 clock frequency may differ
from the selected clock. In most cases, the DSP1 clock frequency equals or exceeds the requested frequency. A lower
frequency is implemented if limited by either the DSPCLK frequency or the maximum DSP1 clocking frequency.
The DSPCLK configuration provides input to the interrupt control circuit and can be used to trigger an interrupt event when
the DSP1 clock frequency is less than the requested frequency; see Section 4.12.
4.4.3.3 DSP Code Execution
After the DSP firmware has been loaded, and the clocks configured, the DSP block is enabled by setting DSP1_CORE_
ENA. When the DSP is configured and enabled, the firmware execution can be started by writing 1 to DSP1_START.
Alternative methods to trigger the firmware execution can also be configured using the DSP1_START_IN_SEL field.
Using the DSP1_START_IN_SEL field, the DSP firmware execution can be linked to the respective DMA function, the
IRQ2 status, or to the FIFO status in one of the event loggers:
•
DMA function: firmware execution commences when all enabled DSP input (WDMA) channel buffers have been
filled, and all enabled DSP output (RDMA) channel buffers have been emptied
•
IRQ2: firmware execution commences when one or more of the unmasked IRQ2 events has occurred
•
Event logger status: firmware execution commences when the FIFO not-empty status is asserted within the
respective event logger
To enable firmware execution on the DSP block, the DSP1_CORE_ENA bit must be set. Note that the usage of the DSP1_
START bit may vary depending on the particular firmware that is being executed: in some applications (e.g., when an
alternative trigger is selected using DSP1_START_IN_SEL), writing to the DSP1_START bit is not required.
4.4.3.4 DSP Operation without DSPCLK
In normal operating conditions, the clock source for the DSP block is derived from DSPCLK. The CS47L15 also supports
DSP operation when DSPCLK is not enabled; this provides capability for always-on DSP applications.
The alternative clock source, for DSP clocking without DSPCLK, is the always-on FLL (FLL_AO). The FLL_AO output
frequency range is approximately 45–50 MHz and is suitable for low-speed DSP clocking requirements.
The default FLL_AO settings are configured to provide a 49.152-MHz output, suitable for use as the always-on DSP clock
source. Note that the FLL_AO control registers must always hold valid settings—either enabled and locked to an input
reference clock, or else configured in FLL Hold Mode. See Section 4.13.9 for details of FLL_AO.
The always-on DSP clocking options are configured using the DSP1_FLL_AO_CLKENA and EVENTLOGn_FLL_AO_
CLKENA bits:
•
82
Setting DSP1_FLL_AO_CLKENA causes the DSP to be clocked directly from FLL_AO if DSP_CLK_ENA = 0. This
allows the DSP core to execute firmware code while DSPCLK is absent.
DS1137PP1
CS47L15
4.4 DSP Firmware Control
•
Setting EVENTLOGn_FLL_AO_CLKENA enables the DSP core to be clocked directly from FLL_AO if DSP_CLK_
ENA = 0 and the FIFO not-empty status is asserted for the respective event logger. This allows the DSP core to
execute firmware code while DSPCLK is absent, triggered by an event detected on one of the event loggers. Note
that the DSP core is only clocked in this case if the start trigger for the DSP is derived from the status of the
respective event logger (i.e., DSP1_START_IN_SEL selects the event logger as the start signal). See Section 4.5.1
for details of the event loggers; the EVENTLOGn_FLL_AO_CLKENA bits are defined in Table 4-34.
Note that these control bits do not automatically start DSP firmware execution—the DSP block must also be enabled using
DSP1_CORE_ENA, and the start signal must be configured, as applicable.
The intended use case of the EVENTLOGn_FLL_AO_CLKENA bit is where the DSP core is configured to use an event
logger status bit as its start condition. Note that, to support continued operation of the DSP core after the event log status
is cleared (i.e., the FIFO buffer has been emptied), clocking of the DSP core must be enabled using DSP1_FLL_AO_
CLKENA, or else by enabling DSPCLK as per the normal system clocking operation. One or other of these actions could
be effected via the DSP firmware code.
The clock frequency for the DSP in these always-on clocking modes is selected using the DSP1_CLK_FREQ_SEL field
(same as normal DSP clocking). Note that, depending on the FLL_AO output frequency and the available clock dividers,
the DSP clock frequency may differ from the selected frequency. In most cases, the DSP clock frequency equals or
exceeds the requested frequency. A lower frequency is implemented if limited by the FLL_AO frequency.
The DSP_CLK_SRC field is ignored in the always-on clocking modes. The DSP core reverts to the normal (DSPCLK)
clocking configuration if DSP_CLK_ENA = 1.
4.4.3.5
DSP Watchdog Timer
A watchdog timer is provided for the DSP, which can be used to detect software lock-ups, and other conditions that require
corrective action in order to resume the intended DSP behavior.
The DSP1 watchdog is enabled using DSP1_WDT_ENA. The timeout period is configured using DSP1_WDT_MAX_
COUNT.
In normal operation, the watchdog should be reset regularly—this action is used to confirm that the DSP code is running
correctly. The watchdog is reset by writing 0x5555, followed by 0xAAAA, to the DSP1_WDT_RESET field.
The watchdog status bit, DSP1_WDT_TIMEOUT_STS, is set if the timeout period elapses before the watchdog is reset;
this event typically signals that a lock-up or other error condition has occurred.
The DSP watchdog is an input to the interrupt control circuit and can be used to trigger an interrupt event if the timeout
period elapses—see Section 4.4.5.
Note that write access to the DSP1_WDT_RESET field is not affected by the register locking mechanism (see
Section 4.4.2). This means that the DSP core always has write access to reset the watchdog.
4.4.3.6 DSP Control Registers
The DSP memory, clocking, code-execution, and watchdog control registers are described in Table 4-30.
The audio signal paths connecting to/from the DSP processing block are configured as described in Section 4.3. Note that
the DSP firmware must be loaded and enabled before audio signal paths can be enabled.
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4.4 DSP Firmware Control
Table 4-30. DSP Memory and Clocking Control
Register Address
R1048064 (0xF_FE00)
DSP1_Config_1
R1048066 (0xF_FE02)
DSP1_Config_2
R1048070 (0xF_FE06)
DSP1_Status_2
Bit
24
Label
DSP1_FLL_AO_
CLKENA
4
DSP1_MEM_ENA
1
DSP1_CORE_ENA
0
DSP1_START
15:0 DSP1_CLK_FREQ_
SEL[15:0]
0
DSP1_CLK_AVAIL
R1048072 (0xF_FE08)
DSP1_Status_3
15:0 DSP1_CLK_FREQ_
STS[15:0]
R1048074 (0xF_FE0A)
DSP1_Watchdog_1
4:1
DSP1_WDT_MAX_
COUNT[3:0]
0
DSP1_WDT_ENA
R1048120 (0xF_FE38)
DSP1_External_Start
4:0
DSP1_START_IN_
SEL[4:0]
R1048158 (0xF_FE5E)
DSP1_Watchdog_2
R1048186 (0xF_FE7A)
DSP1_Region_lock_
ctrl_0
15:0 DSP1_WDT_
RESET[15:0]
4.4.4
13
DSP1_WDT_
TIMEOUT_STS
Default
Description
0
DSP1 always-on clock control
Selects the DSP1 clocking if DSPCLK is disabled
0 = No clock
1 = DSP1 is clocked directly from FLL_AO
0
DSP1 memory control
0 = Disabled
1 = Enabled
The DSP1 memory contents are lost when DSP1_MEM_ENA =0. Note
that this bit is not affected by software reset; it remains in its previous
condition.
0
DSP1 enable. Controls the DSP1 firmware execution
0 = Disabled
1 = Enabled
—
DSP1 start
Write 1 to start DSP1 firmware execution
0x0000 DSP1 clock frequency select
Coded as LSB = 1/64 MHz, Valid from 5.6 to 148 MHz.
The DSP1 clock must be less than or equal to the DSPCLK frequency. The
DSP1 clock is generated by division of DSPCLK, and may differ from the
selected frequency. The DSP1 clock frequency can be read from DSP1_
CLK_FREQ_STS.
0
DSP1 clock availability (read only)
0 = No Clock
1 = Clock Available
This bit exists for legacy software support only; it is not recommended for
future designs—it may be unreliable on the latest device architectures.
0x0000 DSP1 clock frequency (read only). Valid only when the respective DSP
core is enabled.
Coded as LSB = 1/64 MHz.
0x0
DSP1 watchdog timeout value.
0xA = 2 s
0x5 = 64 ms
0x0 = 2 ms
0xB = 4 s
0x6 = 128 ms
0x1 = 4 ms
0xC = 8 s
0x7 = 256 ms
0x2 = 8 ms
0xD–0xF = reserved
0x8 = 512 ms
0x3 = 16 ms
0x9 = 1 s
0x4 = 32 ms
0
DSP1 watchdog enable
0 = Disabled
1 = Enabled
0x00
DSP1 firmware execution control. Selects the trigger for DSP1 firmware
execution.
0x00 = DMA
0x10 = Event Logger 1
0x0B = IRQ2
0x11 = Event Logger 2
All other codes are reserved.
Note that the DSP1_START bit also starts the DSP1 firmware execution,
regardless of this field setting.
0x0000 DSP1 watchdog reset.
Write 0x5555, followed by 0xAAAA, to reset the watchdog.
0
DSP1 watchdog timeout status
This bit, when set, indicates that the watchdog timeout has occurred. This
bit is latched when set; it is cleared when the watchdog is disabled or
reset.
DSP Direct Memory Access (DMA) Control
The DSP provides a multichannel DMA function; this is configured using the registers described in Table 4-31.
84
DS1137PP1
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4.4 DSP Firmware Control
There are eight WDMA (DSP input) and six RDMA (DSP output) channels; these are enabled using the DSP1_WDMA_
CHANNEL_ENABLE and DSP1_RDMA_CHANNEL_ENABLE fields. The status of each WDMA channel is indicated in
DSP1_WDMA_ACTIVE_CHANNELS.
The DMA can access the X-data memory or Y-data memory associated with the DSP block. The applicable memory is
selected using bit [15] of the respective x_START_ADDRESS field for each DMA channel.
The start address of each DMA channel is configured as described in Table 4-31. Note that the required address is defined
relative to the base address of the selected (X-data or Y-data) memory.
The buffer length of the DMA channels is configured using the DSP1_DMA_BUFFER_LENGTH field. The selected buffer
length applies to all enabled DMA channels.
Note that the start-address fields and buffer-length fields are defined in 24-bit DSP data word units. This means that the
LSB of these fields represents one 24-bit DSP memory word. This differs from the CS47L15 register map layout described
in Table 4-26.
The parameters of a DMA channel (i.e., start address or offset address) must not be changed while the respective DMA
is enabled. All of the DMA channels must be disabled before changing the DMA buffer length.
Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the DSP. The buffers are
called ping and pong, and are of configurable size, as noted above. Data is transferred to/from each of the buffers in turn.
When the ping input data buffer is full, the DSP1_PING_FULL bit is set, and a DSP start signal is generated. The start
signal from the DMA is typically used to start firmware execution, as noted in Table 4-30. Meanwhile, further DSP input
data fills up the pong buffer.
When the pong input buffer is full, the DSP1_PONG_FULL bit is set, and another DSP start signal is generated. The DSP
firmware must take care to read the input data from the applicable buffer, in accordance with the DSP1_PING_FULL and
DSP1_PONG_FULL status bits.
Twin buffers are also used on the DSP output (RDMA) channels. The output ping buffers are emptied at the same time as
the input ping buffers are filled; the output pong buffers are emptied at the same time that the input pong buffers are filled.
The DSP core supports 24-bit signal processing. Under default conditions, the DSP audio data is in 2’s complement Q3.20
format (i.e., 0xF00000 corresponds to the –1.0 level, and 0x100000 corresponds to the +1.0 level; a sine wave with peak
values of ±1.0 corresponds to the 0 dBFS level). If DSP1_DMA_WORD_SEL is set, audio data is transferred to and from
the DSP in Q0.23 format. The applicable format should be set according to the requirements of the specific DSP firmware.
Note that the DSP core is optimized for Q3.20 audio data processing; Q0.23 data can be supported, but the firmware
implementation may incur a reduction in power efficiency due to the higher MIPS required for arithmetic operations in
non-native data word format.
The DMA function is an input to the interrupt control circuit—see Section 4.4.5. The respective interrupt event is triggered
if all enabled input (WDMA) channel buffers have been filled and all enabled output (RDMA) channel buffers have been
emptied.
Further details of the DMA are provided in the software programming guide; contact your Cirrus Logic representative if
required.
DS1137PP1
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CS47L15
4.4 DSP Firmware Control
Table 4-31. DMA Control
Register Address
R1048068 (0xF_FE04)
DSP1_Status_1
Bit
31
Label
DSP1_PING_FULL
Default
0
30
DSP1_PONG_FULL
0
23:16 DSP1_WDMA_ACTIVE_
CHANNELS[7:0]
0x00
R1048080 (0xF_FE10) 31:16 DSP1_START_ADDRESS_
WDMA_BUFFER_1[15:0]
DSP1_WDMA_Buffer_1
0x0000
15:0 DSP1_START_ADDRESS_
WDMA_BUFFER_0[15:0]
0x0000
R1048082 (0xF_FE12) 31:16 DSP1_START_ADDRESS_
WDMA_BUFFER_3[15:0]
DSP1_WDMA_Buffer_2
15:0 DSP1_START_ADDRESS_
WDMA_BUFFER_2[15:0]
0x0000
R1048084 (0xF_FE14) 31:16 DSP1_START_ADDRESS_
WDMA_BUFFER_5[15:0]
DSP1_WDMA_Buffer_3
15:0 DSP1_START_ADDRESS_
WDMA_BUFFER_4[15:0]
0x0000
R1048086 (0xF_FE16) 31:16 DSP1_START_ADDRESS_
WDMA_BUFFER_7[15:0]
DSP1_WDMA_Buffer_4
15:0 DSP1_START_ADDRESS_
WDMA_BUFFER_6[15:0]
0x0000
R1048096 (0xF_FE20)
DSP1_RDMA_Buffer_1
31:16 DSP1_START_ADDRESS_
RDMA_BUFFER_1[15:0]
0x0000
15:0 DSP1_START_ADDRESS_
RDMA_BUFFER_0[15:0]
0x0000
31:16 DSP1_START_ADDRESS_
RDMA_BUFFER_3[15:0]
0x0000
15:0 DSP1_START_ADDRESS_
RDMA_BUFFER_2[15:0]
0x0000
31:16 DSP1_START_ADDRESS_
RDMA_BUFFER_5[15:0]
0x0000
15:0 DSP1_START_ADDRESS_
RDMA_BUFFER_4[15:0]
0x0000
R1048098 (0xF_FE22)
DSP1_RDMA_Buffer_2
R1048100 (0xF_FE24)
DSP1_RDMA_Buffer_3
86
0x0000
0x0000
0x0000
Description
DSP1 WDMA Ping Buffer Status
0 = Not Full
1 = Full
DSP1 WDMA Pong Buffer Status
0 = Not Full
1 = Full
DSP1 WDMA Channel Status
There are eight WDMA channels; each bit of this field indicates
the status of the respective WDMA channel.
Each bit is coded as follows:
0 = Inactive
1 = Active
DSP1 WDMA Channel 1 Start Address
Bit [15] = Memory select
0 = X-data memory
1 = Y-data memory
Bits [14:0] = Address select
The address is defined relative to the base address of the
applicable data memory. The LSB represents one 24-bit DSP
memory word.
Note that the start address is also controlled by the respective
DSP1_WDMA_CHANNEL_OFFSET bit.
DSP1 WDMA Channel 0 Start Address
Field description is as above.
DSP1 WDMA Channel 3 Start Address
Field description is as above.
DSP1 WDMA Channel 2 Start Address
Field description is as above.
DSP1 WDMA Channel 5 Start Address
Field description is as above.
DSP1 WDMA Channel 4 Start Address
Field description is as above.
DSP1 WDMA Channel 7 Start Address
Field description is as above.
DSP1 WDMA Channel 6 Start Address
Field description is as above.
DSP1 RDMA Channel 1 Start Address
Bit [15] = Memory select
0 = X-data memory
1 = Y-data memory
Bits [14:0] = Address select
The address is defined relative to the base address of the
applicable data memory. The LSB represents one 24-bit DSP
memory word.
Note that the start address is also controlled by the respective
DSP1_RDMA_CHANNEL_OFFSET bit.
DSP1 RDMA Channel 0 Start Address
Field description is as above.
DSP1 RDMA Channel 3 Start Address
Field description is as above.
DSP1 RDMA Channel 2 Start Address
Field description is as above.
DSP1 RDMA Channel 5 Start Address
Field description is as above.
DSP1 RDMA Channel 4 Start Address
Field description is as above.
DS1137PP1
CS47L15
4.4 DSP Firmware Control
Table 4-31. DMA Control (Cont.)
Register Address
R1048112 (0xF_FE30)
DSP1_DMA_Config_1
Bit
Label
23:16 DSP1_WDMA_CHANNEL_
ENABLE[7:0]
Default
0x00
13:0 DSP1_DMA_BUFFER_
LENGTH[13:0]
0x0000
R1048114 (0xF_FE32)
DSP1_DMA_Config_2
R1048116 (0xF_FE34)
DSP1_DMA_Config_3
7:0
DSP1_WDMA_CHANNEL_
OFFSET[7:0]
0x00
21:16 DSP1_RDMA_CHANNEL_
OFFSET[5:0]
0x00
R1048118 (0xF_FE36)
DSP1_DMA_Config_4
4.4.5
5:0
DSP1_RDMA_CHANNEL_
ENABLE[5:0]
0x00
0
DSP1_DMA_WORD_SEL
0
Description
DSP1 WDMA Channel Enable
There are eight WDMA channels; each bit of this field enables
the respective WDMA channel.
Each bit is coded as follows:
0 = Disabled
1 = Enabled
DSP1 DMA Buffer Length
Selects the amount of data transferred in each DMA channel.
The LSB represents one 24-bit DSP memory word.
DSP1 WDMA Channel Offset
There are eight WDMA channels; each bit of this field offsets the
start Address of the respective WDMA channel.
Each bit is coded as follows:
0 = No offset
1 = Offset by 0x8000
DSP1 RDMA Channel Offset
There are six RDMA channels; each bit of this field offsets the
start Address of the respective RDMA channel.
Each bit is coded as follows:
0 = No offset
1 = Offset by 0x8000
DSP1 RDMA Channel Enable
There are six RDMA channels; each bit of this field enables the
respective RDMA channel.
Each bit is coded as follows:
0 = Disabled
1 = Enabled
DSP1 Data Word Format
0 = Q3.20 format (4 integer bits, 20 fractional bits)
1 = Q0.23 format (1 integer bit, 23 fractional bits)
The data word format should be set according to the
requirements of the applicable DSP firmware.
DSP Interrupts
The DSP core provides inputs to the interrupt circuit and can be used to trigger an interrupt event when the associated
conditions occur. The following interrupts are provided for DSP core:
•
DMA interrupt—Asserted when all enabled DSP input (WDMA) channel buffers have been filled, and all enabled
DSP output (RDMA) channel buffers have been emptied
•
DSP Start 1, DSP Start 2 interrupts—Asserted when the respective start signal is triggered
•
DSP Busy interrupt—Asserted when the DSP is busy (i.e., when firmware execution or DMA processes are started)
•
DSP Bus Error interrupt—Asserted when a locked register address, invalid memory address, or watchdog timeout
error is detected
The CS47L15 also provides 16 control bits that allow the DSP core to generate programmable interrupt events. When a
1 is written to these bits (see Table 4-32), the respective DSP interrupt (DSP_IRQn_EINTx) is triggered. The associated
interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.
See Section 4.12 for further details.
Table 4-32. DSP Interrupts
Register Address
R5632 (0x1600)
ADSP2_IRQ0
R5633 (0x1601)
ADSP2_IRQ1
DS1137PP1
Bit
1
0
1
0
Label
DSP_IRQ2
DSP_IRQ1
DSP_IRQ4
DSP_IRQ3
Default
0
0
0
0
Description
DSP IRQ2. Write 1 to trigger the DSP_IRQ2_EINTn interrupt.
DSP IRQ1. Write 1 to trigger the DSP_IRQ1_EINTn interrupt.
DSP IRQ4. Write 1 to trigger the DSP_IRQ4_EINTn interrupt.
DSP IRQ3. Write 1 to trigger the DSP_IRQ3_EINTn interrupt.
87
CS47L15
4.4 DSP Firmware Control
Table 4-32. DSP Interrupts (Cont.)
Register Address
R5634 (0x1602)
ADSP2_IRQ2
R5635 (0x1603)
ADSP2_IRQ3
R5636 (0x1604)
ADSP2_IRQ4
R5637 (0x1605)
ADSP2_IRQ5
R5638 (0x1606)
ADSP2_IRQ6
R5639 (0x1607)
ADSP2_IRQ7
4.4.6
Bit
1
0
1
0
1
0
1
0
1
0
1
0
Label
DSP_IRQ6
DSP_IRQ5
DSP_IRQ8
DSP_IRQ7
DSP_IRQ10
DSP_IRQ9
DSP_IRQ12
DSP_IRQ11
DSP_IRQ14
DSP_IRQ13
DSP_IRQ16
DSP_IRQ15
Default
0
0
0
0
0
0
0
0
0
0
0
0
Description
DSP IRQ6. Write 1 to trigger the DSP_IRQ6_EINTn interrupt.
DSP IRQ5. Write 1 to trigger the DSP_IRQ5_EINTn interrupt.
DSP IRQ8. Write 1 to trigger the DSP_IRQ8_EINTn interrupt.
DSP IRQ7. Write 1 to trigger the DSP_IRQ7_EINTn interrupt.
DSP IRQ10. Write 1 to trigger the DSP_IRQ10_EINTn interrupt.
DSP IRQ9. Write 1 to trigger the DSP_IRQ9_EINTn interrupt.
DSP IRQ12. Write 1 to trigger the DSP_IRQ12_EINTn interrupt.
DSP IRQ11. Write 1 to trigger the DSP_IRQ11_EINTn interrupt.
DSP IRQ14. Write 1 to trigger the DSP_IRQ14_EINTn interrupt.
DSP IRQ13. Write 1 to trigger the DSP_IRQ13_EINTn interrupt.
DSP IRQ16. Write 1 to trigger the DSP_IRQ16_EINTn interrupt.
DSP IRQ15. Write 1 to trigger the DSP_IRQ15_EINTn interrupt.
DSP Debug Support
General-purpose registers are provided for the DSP. These have no assigned function and can be used to assist in
algorithm development.
The JTAG interface provides test and debug access to the CS47L15, as described in Section 4.17. The JTAG interface
clock can be enabled for the DSP core using DSP1_DBG_CLK_ENA. Note that, when the JTAG interface is used to
access the DSP core, the DSP1_CORE_ENA bit must also be set.
The DSP1_LOCK_ERR_STS bit indicates that the DSP attempted to write to a locked register address. The DSP1_
ADDR_ERR_STS bit indicates that the DSP attempted to access an invalid memory address (i.e., an address whose
contents are undefined). Once set, these bits remain set until a 1 is written to DSP1_ERR_CLEAR.
The DSP1_PMEM_ERR_ADDR and DSP1_XMEM_ERR_ADDR fields contain the program memory and X-data memory
addresses associated with a locked register address error condition. If DSP1_LOCK_ERR_STS is set, these fields
correspond to the first-detected locked register address error. Note that no subsequent error event can be reported in
these fields until the DSP1_LOCK_ERR_STS is cleared.
Note:
The DSP1_PMEM_ERR_ADDR value is the prefetched address of a code instruction that has not yet been
executed; it does not point directly to the instruction that caused the error.
The DSP1_BUS_ERR_ADDR field indicates the register/memory address that resulted in a register-access error. The
field relates either to a locked register address error or to an invalid memory address error, as follows:
•
If DSP1_LOCK_ERR_STS is set, the DSP1_BUS_ERR_ADDR value corresponds to the first-detected locked
register address error. Note that no subsequent error event can be reported in this field until DSP1_LOCK_ERR_
STS is cleared.
•
If DSP1_ADDR_ERR_STS is set, and DSP1_LOCK_ERR_STS is clear, the DSP1_BUS_ERR_ADDR field
corresponds to the most recent invalid memory address error.
•
If the DSP1_LOCK_ERR_STS and DSP1_ADDR_ERR_STS are both clear, the DSP1_BUS_ERR_ADDR field is
undefined.
Note:
The DSP1_BUS_ERR_ADDR value is coded using a byte-referenced address, so the actual register address is
equal to DSP1_BUS_ERR_ADDR / 2. If the register-access error is the result of an attempt to access the virtual
DSP registers, a register address of 0 is reported.
If the DSP1_ERR_PAUSE bit is set, the DSP code execution stops immediately on detection of a locked register address
error. This enables debug information to be retrieved from the DSP core during code development. In this event, code
execution can be restarted by clearing the DSP1_ERR_PAUSE bit. Alternatively, the DSP core can restarted by clearing
and setting DSP1_CORE_ENA (described in Section 4.4.3.3).
88
DS1137PP1
CS47L15
4.4 DSP Firmware Control
Table 4-33. DSP Debug Support
Register Address
R1048064 (0xF_FE00)
DSP1_Config_1
Description
DSP1 Debug Clock Enable
0 = Disabled
1 = Enabled
R1048128 (0xF_FE40)
31:16 DSP1_SCRATCH_1[15:0]
0x0000 DSP1 Scratch Register 1
DSP1_Scratch_1
15:0 DSP1_SCRATCH_0[15:0]
0x0000 DSP1 Scratch Register 0
R1048130 (0xF_FE42)
31:16 DSP1_SCRATCH_3[15:0]
0x0000 DSP1 Scratch Register 3
DSP1_Scratch_2
15:0 DSP1_SCRATCH_2[15:0]
0x0000 DSP1 Scratch Register 2
R1048146 (0xF_FE52)
23:0 DSP1_BUS_ERR_ADDR[23:0]
0x00_0000 Contains the register address of a memory region lock
or memory address error event.
DSP1_Bus_Error_Addr
Note the associated register address is equal to DSP1_
BUS_ERR_ADDR / 2.
R1048186 (0xF_FE7A)
15 DSP1_LOCK_ERR_STS
0
DSP1 memory region lock error status.
DSP1_Region_lock_ctrl_0
This bit, when set, indicates that DSP1 attempted to
write to a locked register address.
This bit is latched when set; it is cleared when a 1 is
written to DSP1_ERR_CLEAR.
14 DSP1_ADDR_ERR_STS
0
DSP1 memory address error status.
This bit, when set, indicates that DSP1 attempted to
access an undefined locked register address.
This bit is latched when set; it is cleared when a 1 is
written to DSP1_ERR_CLEAR.
1
DSP1_ERR_PAUSE
0
DSP1 bus address error control.
Configures the DSP1 response to a memory region
lock error event.
0 = No action
1 = Pause DSP1 code execution
0
DSP1_ERR_CLEAR
0
Write 1 to clear the memory region lock error and
memory address error status bits.
30:16 DSP1_PMEM_ERR_ADDR[14:0]
0x0000 Contains the program memory address of a memory
R1048188 (0xF_FE7C)
region lock error event. Note this is the prefetched
DSP1_PMEM_Err_Addr___
address of a subsequent instruction; it does not point
XMEM_ERR_Addr
directly to the address that caused the error.
15:0 DSP1_XMEM_ERR_ADDR[15:0]
0x0000 Contains the X-data memory address of a memory
region lock error event.
4.4.7
Bit
3
Label
DSP1_DBG_CLK_ENA
Default
0
Virtual DSP Registers
The DSP control registers are described throughout Section 4.4. Each control register has a unique location within the
CS47L15 register map.
An additional set of DSP control registers is also defined, which can be used in firmware to access the DSP control fields:
the virtual DSP (or DSP 0) registers are defined at address R4096 (0x1000) in the device register map. The full register
map listing is provided in Section 6.
Note that read/write access to the virtual DSP registers is only possible via firmware running on the integrated DSP core.
When DSP firmware accesses the virtual registers, the registers are automatically mapped onto the DSP1 control
registers. The virtual DSP registers are designed to allow software to be transferable across different DSPs (e.g., on
multicore devices) without modification to the software code.
The virtual DSP registers are defined at register addresses R4096–R4192 (0x1000–0x1060) in the device register map.
Note that these registers cannot be accessed directly at the addresses shown; they can be only accessed through DSP
firmware code, using the register window function shown in Fig. 4-30. The virtual DSP registers are located at address
0xD000 in the X-data memory map.
DS1137PP1
89
CS47L15
4.5 DSP Peripheral Control
4.5 DSP Peripheral Control
The CS47L15 incorporates a suite of DSP peripheral functions that can be integrated together to provide an enhanced
capability for DSP applications. Configurable event log functions provide multichannel monitoring of internal and external
signals. The general-purpose timers provide time-stamp data for the event logs; they also support the watchdog and other
miscellaneous time-based functions. Maskable GPIO provides an efficient mechanism for the DSP core to access the
required input and output signals.
The peripherals are designed to support a comprehensive DSP capability, operating with a high degree of autonomy from
the host processor.
4.5.1
Event Loggers
The CS47L15 provides two event log functions, supporting multichannel, edge-sensitive monitoring and recording of
internal or external signals.
4.5.1.1 Overview
The event loggers allow status information to be captured from a large number of sources, to be prioritized and acted upon
as required. For the purposes of the event loggers, an event is recorded when a logic transition (edge) is detected on a
selected signal source.
The logged events are held in a FIFO buffer, which is managed by the application software. A 32-bit time stamp, derived
from one of the general-purpose timers, is associated and recorded with each FIFO index, to provide a comprehensive
record of the detected events.
Each event logger must be associated with one of the general-purpose timers. The selected timer is the source of time
stamp data for any logged events. If DSPCLK is disabled, the timer also provides the clock source for the event logger. (If
DSPCLK is enabled, DSPCLK is used as the clock source instead.)
A maximum of one event per cycle of the clock source can be logged. If more than one event occurs within the cycle time,
the highest priority (lowest channel number) event is logged at the rising edge of the clock. In this case, any lower priority
events is queued, and is logged as soon as no higher priority events are pending. It is possible for recurring events on a
high-priority channel to be logged, while low-priority ones remain queued. Note that recurring instances of events that are
queued would not be logged.
The event logger can use a slow clock (e.g., 32 kHz), but higher clock frequencies may also be commonly used, depending
on the application and use case. The clock frequency determines the maximum possible event logging rate.
4.5.1.2 Event Logger Control
The event logger is enabled by setting EVENTLOGn_ENA (where n identifies the respective event logger, 1 or 2).
The event logger can be reset by writing 1 to EVENTLOGn_RST. Executing this function clears all the event logger status
flags and clears the contents of the FIFO buffer.
The associated timer (and time-stamp source) is selected using EVENTLOGn_TIME_SEL. Note that the event logger
must be disabled (EVENTLOGn_ENA = 0) when selecting the timer source.
4.5.1.3 Input Channel Configuration
The event logger allows up to 16 input channels to be configured for detection and logging. The EVENTLOGn_CHx_SEL
field selects the applicable input source for each channel (where x identifies the channel number, 1 to 16). The polarity
selection and debounce options are configured using the EVENTLOGn_CHx_POL and EVENTLOGn_CHx_DB bits
respectively.
The input channels can be enabled or disabled freely, using EVENTLOGn_CHx_ENA, without having to disable the event
logger entirely. An input channel must be disabled whenever the associated x_SEL, x_POL, or x_DB fields are written. It
is possible to reconfigure input channels while the event logger is enabled, provided the channels being reconfigured are
disabled when doing so.
90
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
The available input sources include GPIO inputs, external accessory status (jack, mic, sensors), and signals generated by
the integrated DSP core. A list of the valid input sources for the event loggers is provided in Table 4-35. Note that, to log
both rising and falling events from any source, two separate input channels must be configured—one for each polarity.
If an input channel is configured for rising edge detection (EVENTLOGn_CHx_POL = 0), and the corresponding input
signal is asserted (Logic 1) at the time when the event logger is enabled, an event is logged in respect of this initial state.
Similarly, if an input channel is configured for falling edge detection, and is deasserted (Logic 0) when the event logger is
enabled, a corresponding event is logged. If rising and falling edges are both configured for detection, an event is always
logged in respect of the initial condition.
4.5.1.4 FIFO Buffer
Each event (signal transition) that meets the criteria of an enabled channel is written to the 16-stage FIFO buffer. The
buffer is filled cyclically, but does not overwrite unread data when full. An error condition occurs if the buffer fills up
completely.
Note that the FIFO behavior is not enforced or fully implemented in the device hardware, but assumes that a compatible
software implementation is in place. New events are written to the buffer in a cyclic manner, but the data can be read out
in any order, if desired. The designed FIFO behavior requires the software to update the read pointer (RPTR) in the
intended manner for smooth operation.
The entire contents of the 16-stage FIFO buffer can be accessed directly in the register map. Each FIFO index (y = 0 to
15) comprises the EVENTLOGn_FIFOy_ID (identifying the source signal of the associated log event), the EVENTLOGn_
FIFOy_POL (the polarity of the respective event transition), and the EVENTLOGn_FIFOy_TIME field (containing the 32-bit
time stamp from the associated timer).
The FIFO buffer is managed using EVENTLOGn_FIFO_WPTR and EVENTLOGn_FIFO_RPTR. The write pointer
(WPTR) field identifies the index location (0 to 15) in which the next event is logged. The read pointer (RPTR) field
identifies the index location of the first set of unread data, if any exists. Both of these fields are initialized to 0 when the
event logger is reset.
•
If RPTR  WPTR, the buffer contains new data. The number of new events is equal to the difference between the
two pointer values (WPTR – RPTR, allowing for wraparound beyond Index 15). For example, if WPTR = 12 and
RPTR = 8, this means that there are four unread data sets in the buffer, at index locations 8, 9, 10, and 11.
After reading the new data from the buffer, the RPTR value should be incremented by the corresponding amount
(e.g., increment by 4, in the example described above). Note that the RPTR value can either be incremented once
for each read, or can be incremented in larger steps after a batch read.
•
If RPTR = WPTR, the buffer is either empty (0 events) or full (16 events). In this case, the status bits described in
Section 4.5.1.5 confirm the current status of the buffer.
4.5.1.5 Status Bits
The EVENTLOGn_NOT_EMPTY bit indicates whether the FIFO buffer is empty. When this bit is set, it indicates one or
more new sets of data in the FIFO.
The EVENTLOGn_WMARK_STS bit indicates when the number of FIFO index locations available for new events reaches
a configurable threshold, known as the watermark level. The watermark level is held in the EVENTLOGn_FIFO_WMARK
field.
The EVENTLOGn_FULL bit indicates when the FIFO buffer is full. When this bit is set, it indicates that there are 16 sets
of new event data in the FIFO. Note that this does not mean that a buffer overflow condition has occurred, but further
events are not logged or indicated until the buffer has been cleared.
Note:
Following a buffer full condition, the FIFO operation resumes as soon as the RPTR field has been updated to a
new value. Writing the same value to RPTR does not restart the FIFO operation, even if the entire buffer contents
have been read. After all of the required data has been read from the buffer, the RPTR value should be set equal
to the WPTR value; an intermediate (different) value must also be written to the RPTR field in order to clear the
buffer full status and restart the FIFO operation.
DS1137PP1
91
CS47L15
4.5 DSP Peripheral Control
4.5.1.6 Interrupts, GPIO, Write Sequencer, and DSP Firmware Control
The control-write sequencer is automatically triggered whenever the NOT_EMPTY status of the event log buffer is
asserted. A different control sequence may be configured for each event logger; see Section 4.15 for further details.
The event log status flags are inputs to the interrupt control circuit and can be used to trigger an interrupt event when the
respective FIFO condition (full, not empty, or watermark level) occurs; see Section 4.12.
The event log status can be output directly on a GPIO pin as an external indication of the event logger; see Section 4.11
to configure a GPIO pin for this function.
The event log NOT_EMPTY status can also be selected as a start trigger for DSP firmware execution; see Section 4.4.
4.5.1.7 Event Logger Control Registers
The event logger control registers are described in Table 4-34.
Table 4-34. Event Logger (EVENTLOGn) Control
Register Address
Bit
Label
Event Log 1 Base Address = R294912 (0x4_8000)
Event Log 2 Base Address = R295424 (0x4_8200)
base address
8
EVENTLOGn_FLL_AO_
CLKENA
EVENTLOGn_CONTROL
Default
Description
0
Event Log DSP Clock Control
Configures clocking of the DSP core if DSPCLK is disabled,
according to the Event Log FIFO status.
0 = FIFO status has no effect on DSP clocking
1 = DSP core clocked directly from FLL_AO if Event Log n FIFO
is not empty
Event Log Reset
Write 1 to reset the status outputs and clear the FIFO buffer.
Event Log Enable
0 = Disabled
1 = Enabled
Event Log Timer Source Select
00 = Timer 1
01 = Timer 2
Note that the event log must be disabled when updating this
field
Event Log FIFO Watermark. The watermark status output is
asserted when the number of FIFO locations available for new
events is less than or equal to the FIFO watermark.
Valid from 0 to 15.
Event Log FIFO Full Status. This bit, when set, indicates that
the FIFO buffer is full. It is cleared when a new value is written
to the FIFO read pointer, or when the event log is Reset.
Event Log FIFO Watermark Status. This bit, when set, indicates
that the FIFO space available for new events to be logged is
less than or equal to the watermark threshold.
Event Log FIFO Not Empty Status. This bit, when set, indicates
one or more new sets of logged event data in the FIFO.
Event Log FIFO Write Pointer. Indicates the FIFO index
location in which the next event is logged.
This is a read-only field.
Event Log FIFO Read Pointer. Indicates the FIFO index
location of the first set of unread data, if any exists. For the
intended FIFO behavior, this field must be incremented after
the respective data has been read.
1
EVENTLOGn_RST
0
0
EVENTLOGn_ENA
0
Base address +0x04
EVENTLOGn_TIMER_SEL
1:0
EVENTLOGn_TIMER_
SEL[1:0]
00
Base address +0x0C
EVENTLOGn_FIFO_
CONTROL1
3:0
EVENTLOGn_FIFO_
WMARK[3:0]
0x1
Base address +0x0E
EVENTLOGn_FIFO_
POINTER1
18
EVENTLOGn_FULL
0
17
EVENTLOGn_WMARK_STS
0
16
EVENTLOGn_NOT_EMPTY
0
92
11:8 EVENTLOGn_FIFO_
WPTR[3:0]
0x0
3:0
0x0
EVENTLOGn_FIFO_
RPTR[3:0]
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
Table 4-34. Event Logger (EVENTLOGn) Control (Cont.)
Register Address
Base address +0x20
EVENTLOGn_CH_ENABLE
Base address +0x40
EVENTLOGn_CH1_DEFINE
Base address +0x42
EVENTLOGn_CH2_DEFINE
Base address +0x44
EVENTLOGn_CH3_DEFINE
DS1137PP1
Bit
15
Label
EVENTLOGn_CH16_ENA
14
EVENTLOGn_CH15_ENA
13
EVENTLOGn_CH14_ENA
12
EVENTLOGn_CH13_ENA
11
EVENTLOGn_CH12_ENA
10
EVENTLOGn_CH11_ENA
9
EVENTLOGn_CH10_ENA
8
EVENTLOGn_CH9_ENA
7
EVENTLOGn_CH8_ENA
6
EVENTLOGn_CH7_ENA
5
EVENTLOGn_CH6_ENA
4
EVENTLOGn_CH5_ENA
3
EVENTLOGn_CH4_ENA
2
EVENTLOGn_CH3_ENA
1
EVENTLOGn_CH2_ENA
0
EVENTLOGn_CH1_ENA
15
EVENTLOGn_CH1_DB
14
EVENTLOGn_CH1_POL
8:0
EVENTLOGn_CH1_SEL[8:0]
15
EVENTLOGn_CH2_DB
14
EVENTLOGn_CH2_POL
8:0
EVENTLOGn_CH2_SEL[8:0]
15
EVENTLOGn_CH3_DB
14
EVENTLOGn_CH3_POL
8:0
EVENTLOGn_CH3_SEL[8:0]
Default
Description
0
Event Log Channel 16 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 15 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 14 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 13 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 12 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 11 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 10 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 9 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 8 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 7 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 6 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 5 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 4 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 3 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 2 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 1 Enable
0 = Disabled, 1 = Enabled
0
Event Log Channel 1 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 1 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 1 source 1
Note that channel must be disabled when updating this field
0
Event Log Channel 2 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 2 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 2 source 1
Field description is as above.
0
Event Log Channel 3 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 3 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 3 source 1
Field description is as above.
93
CS47L15
4.5 DSP Peripheral Control
Table 4-34. Event Logger (EVENTLOGn) Control (Cont.)
Register Address
Base address +0x46
EVENTLOGn_CH4_DEFINE
Bit
15
14
8:0
Base address +0x48
EVENTLOGn_CH5_DEFINE
15
14
8:0
Base address +0x4A
EVENTLOGn_CH6_DEFINE
15
14
8:0
Base address +0x4C
EVENTLOGn_CH7_DEFINE
15
14
8:0
Base address +0x4E
EVENTLOGn_CH8_DEFINE
15
14
8:0
Base address +0x50
EVENTLOGn_CH9_DEFINE
15
14
8:0
Base address +0x52
EVENTLOGn_CH10_
DEFINE
15
14
8:0
94
Label
EVENTLOGn_CH4_DB
Default
Description
0
Event Log Channel 4 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH4_POL
0
Event Log Channel 4 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH4_SEL[8:0] 0x000 Event Log Channel 4 source 1
Field description is as above.
EVENTLOGn_CH5_DB
0
Event Log Channel 5 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH5_POL
0
Event Log Channel 5 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH5_SEL[8:0] 0x000 Event Log Channel 5 source 1
Field description is as above.
EVENTLOGn_CH6_DB
0
Event Log Channel 6 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH6_POL
0
Event Log Channel 6 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH6_SEL[8:0] 0x000 Event Log Channel 6 source 1
Field description is as above.
EVENTLOGn_CH7_DB
0
Event Log Channel 7 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH7_POL
0
Event Log Channel 7 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH7_SEL[8:0] 0x000 Event Log Channel 7 source 1
Field description is as above.
EVENTLOGn_CH8_DB
0
Event Log Channel 8 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH8_POL
0
Event Log Channel 8 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH8_SEL[8:0] 0x000 Event Log Channel 8 source 1
Field description is as above.
EVENTLOGn_CH9_DB
0
Event Log Channel 9 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH9_POL
0
Event Log Channel 9 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH9_SEL[8:0] 0x000 Event Log Channel 9 source 1
Field description is as above.
EVENTLOGn_CH10_DB
0
Event Log Channel 10 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
EVENTLOGn_CH10_POL
0
Event Log Channel 10 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
EVENTLOGn_CH10_SEL[8:0] 0x000 Event Log Channel 10 source 1
Field description is as above.
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
Table 4-34. Event Logger (EVENTLOGn) Control (Cont.)
Register Address
Base address +0x54
EVENTLOGn_CH11_
DEFINE
Base address +0x56
EVENTLOGn_CH12_
DEFINE
Base address +0x58
EVENTLOGn_CH13_
DEFINE
Base address +0x5A
EVENTLOGn_CH14_
DEFINE
Base address +0x5C
EVENTLOGn_CH15_
DEFINE
Base address +0x5E
EVENTLOGn_CH16_
DEFINE
Base address +0x80
EVENTLOGn_FIFO0_READ
Base address +0x82
EVENTLOGn_FIFO0_TIME
Base address +0x84
EVENTLOGn_FIFO1_READ
DS1137PP1
Bit
15
Label
EVENTLOGn_CH11_DB
14
EVENTLOGn_CH11_POL
8:0
EVENTLOGn_CH11_SEL[8:0]
15
EVENTLOGn_CH12_DB
14
EVENTLOGn_CH12_POL
8:0
EVENTLOGn_CH12_SEL[8:0]
15
EVENTLOGn_CH13_DB
14
EVENTLOGn_CH13_POL
8:0
EVENTLOGn_CH13_SEL[8:0]
15
EVENTLOGn_CH14_DB
14
EVENTLOGn_CH14_POL
8:0
EVENTLOGn_CH14_SEL[8:0]
15
EVENTLOGn_CH15_DB
14
EVENTLOGn_CH15_POL
8:0
EVENTLOGn_CH15_SEL[8:0]
15
EVENTLOGn_CH16_DB
14
EVENTLOGn_CH16_POL
8:0
EVENTLOGn_CH16_SEL[8:0]
12
EVENTLOGn_FIFO0_POL
8:0 EVENTLOGn_FIFO0_ID[8:0]
31:0 EVENTLOGn_FIFO0_
TIME[31:0]
12
EVENTLOGn_FIFO1_POL
8:0
EVENTLOGn_FIFO1_ID[8:0]
Default
Description
0
Event Log Channel 11 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 11 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 11 source 1
Field description is as above.
0
Event Log Channel 12 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 12 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 12 source 1
Field description is as above.
0
Event Log Channel 13 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 13 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 13 source 1
Field description is as above.
0
Event Log Channel 14 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 14 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 14 source 1
Field description is as above.
0
Event Log Channel 15 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 15 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 15 source 1
Field description is as above.
0
Event Log Channel 16 debounce
0 = Disabled, 1 = Enabled
Note that channel must be disabled when updating this field
0
Event Log Channel 16 polarity
0 = Rising edge triggered, 1 = Falling edge triggered
Note that channel must be disabled when updating this field
0x000 Event Log Channel 16 source 1
Field description is as above.
0
Event Log FIFO Index 0 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 0 source 1
0x0000 Event Log FIFO Index 0 Time
_0000
0
Event Log FIFO Index 1 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 1 source 1
95
CS47L15
4.5 DSP Peripheral Control
Table 4-34. Event Logger (EVENTLOGn) Control (Cont.)
Register Address
Base address +0x86
EVENTLOGn_FIFO1_TIME
Base address +0x88
EVENTLOGn_FIFO2_READ
Base address +0x8A
EVENTLOGn_FIFO2_TIME
Base address +0x8C
EVENTLOGn_FIFO3_READ
Base address +0x8E
EVENTLOGn_FIFO3_TIME
Base address +0x90
EVENTLOGn_FIFO4_READ
Base address +0x92
EVENTLOGn_FIFO4_TIME
Base address +0x94
EVENTLOGn_FIFO5_READ
Base address +0x96
EVENTLOGn_FIFO5_TIME
Base address +0x98
EVENTLOGn_FIFO6_READ
Base address +0x9A
EVENTLOGn_FIFO6_TIME
Base address +0x9C
EVENTLOGn_FIFO7_READ
Base address +0x9E
EVENTLOGn_FIFO7_TIME
Base address +0xA0
EVENTLOGn_FIFO8_READ
Base address +0xA2
EVENTLOGn_FIFO8_TIME
Base address +0xA4
EVENTLOGn_FIFO9_READ
Base address +0xA6
EVENTLOGn_FIFO9_TIME
Base address +0xA8
EVENTLOGn_FIFO10_
READ
Bit
Label
31:0 EVENTLOGn_FIFO1_
TIME[31:0]
12
EVENTLOGn_FIFO2_POL
8:0 EVENTLOGn_FIFO2_ID[8:0]
31:0 EVENTLOGn_FIFO2_
TIME[31:0]
12
EVENTLOGn_FIFO3_POL
8:0 EVENTLOGn_FIFO3_ID[8:0]
31:0 EVENTLOGn_FIFO3_
TIME[31:0]
12
EVENTLOGn_FIFO4_POL
8:0 EVENTLOGn_FIFO4_ID[8:0]
31:0 EVENTLOGn_FIFO4_
TIME[31:0]
12
EVENTLOGn_FIFO5_POL
8:0 EVENTLOGn_FIFO5_ID[8:0]
31:0 EVENTLOGn_FIFO5_
TIME[31:0]
12
EVENTLOGn_FIFO6_POL
8:0 EVENTLOGn_FIFO6_ID[8:0]
31:0 EVENTLOGn_FIFO6_
TIME[31:0]
12
EVENTLOGn_FIFO7_POL
8:0 EVENTLOGn_FIFO7_ID[8:0]
31:0 EVENTLOGn_FIFO7_
TIME[31:0]
12
EVENTLOGn_FIFO8_POL
8:0 EVENTLOGn_FIFO8_ID[8:0]
31:0 EVENTLOGn_FIFO8_
TIME[31:0]
12
EVENTLOGn_FIFO9_POL
8:0 EVENTLOGn_FIFO9_ID[8:0]
31:0 EVENTLOGn_FIFO9_
TIME[31:0]
Default
Description
0x0000 Event Log FIFO Index 1 Time
_0000
0
Event Log FIFO Index 2 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 2 source 1
0x0000 Event Log FIFO Index 2 Time
_0000
0
Event Log FIFO Index 3 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 3 source 1
0x0000 Event Log FIFO Index 3 Time
_0000
0
Event Log FIFO Index 4 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 4 source 1
0x0000 Event Log FIFO Index 4 Time
_0000
0
Event Log FIFO Index 5 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 5 source 1
0x0000 Event Log FIFO Index 5 Time
_0000
0
Event Log FIFO Index 6 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 6 source 1
0x0000 Event Log FIFO Index 6 Time
_0000
0
Event Log FIFO Index 7 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 7 source 1
0x0000 Event Log FIFO Index 7 Time
_0000
0
Event Log FIFO Index 8 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 8 source 1
0x0000 Event Log FIFO Index 8 Time
_0000
0
Event Log FIFO Index 9 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 9 source 1
0x0000 Event Log FIFO Index 9 Time
_0000
Event Log FIFO Index 10 polarity
0 = Rising edge, 1 = Falling edge
8:0 EVENTLOGn_FIFO10_ID[8:0] 0x000 Event Log FIFO Index 10 source 1
Base address +0xAA
31:0 EVENTLOGn_FIFO10_
0x0000 Event Log FIFO Index 10 Time
TIME[31:0]
_0000
EVENTLOGn_FIFO10_TIME
Base address +0xAC
12 EVENTLOGn_FIFO11_POL
0
Event Log FIFO Index 11 polarity
EVENTLOGn_FIFO11_
0 = Rising edge, 1 = Falling edge
READ
8:0 EVENTLOGn_FIFO11_ID[8:0] 0x000 Event Log FIFO Index 11 source 1
Base address +0xAE
31:0 EVENTLOGn_FIFO11_
0x0000 Event Log FIFO Index 11 Time
TIME[31:0]
_0000
EVENTLOGn_FIFO11_TIME
Base address +0xB0
EVENTLOGn_FIFO12_
READ
96
12
EVENTLOGn_FIFO10_POL
0
12
EVENTLOGn_FIFO12_POL
0
8:0
Event Log FIFO Index 12 polarity
0 = Rising edge, 1 = Falling edge
EVENTLOGn_FIFO12_ID[8:0] 0x000 Event Log FIFO Index 12 source 1
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
Table 4-34. Event Logger (EVENTLOGn) Control (Cont.)
Register Address
Bit
Label
Base address +0xB2
31:0 EVENTLOGn_FIFO12_
TIME[31:0]
EVENTLOGn_FIFO12_TIME
Base address +0xB4
12 EVENTLOGn_FIFO13_POL
EVENTLOGn_FIFO13_
READ
8:0 EVENTLOGn_FIFO13_ID[8:0]
Base address +0xB6
31:0 EVENTLOGn_FIFO13_
TIME[31:0]
EVENTLOGn_FIFO13_TIME
Base address +0xB8
12 EVENTLOGn_FIFO14_POL
EVENTLOGn_FIFO14_
READ
8:0 EVENTLOGn_FIFO14_ID[8:0]
Base address +0xBA
31:0 EVENTLOGn_FIFO14_
TIME[31:0]
EVENTLOGn_FIFO14_TIME
Base address +0xBC
EVENTLOGn_FIFO15_
READ
12
EVENTLOGn_FIFO15_POL
Default
Description
0x0000 Event Log FIFO Index 12 Time
_0000
0
Event Log FIFO Index 13 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 13 source 1
0x0000 Event Log FIFO Index 13 Time
_0000
0
Event Log FIFO Index 14 polarity
0 = Rising edge, 1 = Falling edge
0x000 Event Log FIFO Index 14 source 1
0x0000 Event Log FIFO Index 14 Time
_0000
0
Event Log FIFO Index 15 polarity
0 = Rising edge, 1 = Falling edge
8:0 EVENTLOGn_FIFO15_ID[8:0] 0x000 Event Log FIFO Index 15 source 1
Base address +0xBE
31:0 EVENTLOGn_FIFO15_
0x0000 Event Log FIFO Index 15 Time
TIME[31:0]
_0000
EVENTLOGn_FIFO15_TIME
1.See Table 4-35 for valid channel source selections
4.5.1.8 Event Logger Input Sources
A list of the valid input sources for the event loggers is provided in Table 4-35.
The EDGE type noted is coded as S (single edge) or D (dual edge). Note that a single-edge input source only provides
valid input to the event logger in the default (rising edge triggered) polarity.
Caution is advised when enabling IRQ1 or IRQ2 as an input source for the event loggers; a recursive loop, where the IRQn
signal is also an output from the same event logger, must be avoided.
Table 4-35. Event Logger Input Sources
ID
3
4
9
24
27
32
33
34
80
88
89
96
97
98
99
100
101
128
129
160
161
162
163
164
Description
irq1
irq2
sysclk_fail
fll1_lock
fll_ao_lock
frame_start_g1r1
frame_start_g1r2
frame_start_g1r3
hpdet
micdet1
micdet2
jd1_rise
jd1_fall
jd2_rise
jd2_fall
micd_clamp_rise
micd_clamp_fall
drc1_sig_det
drc2_sig_det
dsp_irq1
dsp_irq2
dsp_irq3
dsp_irq4
dsp_irq5
DS1137PP1
Edge
D
D
S
D
D
S
S
S
S
S
S
S
S
S
S
S
S
D
D
S
S
S
S
S
ID
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
182
224
225
226
256
257
258
259
260
Description
dsp_irq6
dsp_irq7
dsp_irq8
dsp_irq9
dsp_irq10
dsp_irq11
dsp_irq12
dsp_irq13
dsp_irq14
dsp_irq15
dsp_irq16
hp1l_sc
hp1r_sc
hp2l_sc
hp2r_sc
spkoutl_short
spk_shutdown
spk_overheat
spk_overheat_warn
gpio1
gpio2
gpio3
gpio4
gpio5
Edge
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
D
D
S
S
D
D
D
D
D
ID
261
262
263
264
265
266
267
268
269
270
320
321
336
337
352
353
368
369
384
416
432
448
464
Description
gpio6
gpio7
gpio8
gpio9
gpio10
gpio11
gpio12
gpio13
gpio14
gpio15
Timer1
Timer2
event1_not_empty
event2_not_empty
event1_full
event2_full
event1_wmark
event2_wmark
dsp1_dma
dsp1_start1
dsp1_start2
dsp1_start
dsp1_busy
Edge
D
D
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
S
S
S
S
D
97
CS47L15
4.5 DSP Peripheral Control
4.5.2
General-Purpose Timers
The CS47L15 incorporates two general-purpose timers, which support a wide variety of uses. The general-purpose timers
provide time-stamp data for the event logs; they also support the watchdog and other miscellaneous time-based functions,
providing additional capability for signal-processing applications.
4.5.2.1 Overview
The timers allow time-stamp information to be associated with external signal detection, and other system events, enabling
real-time data to be more easily integrated into user applications. The timers allow many advanced functions to be
implemented with a high degree of autonomy from a host processor.
The timers can use either internal system clocks, or external clock signals, as a reference. The selected reference is scaled
down, using configurable dividers, to the required clock count frequency.
4.5.2.2 Timer Control
The reference clock for each timer is selected using TIMERn_REFCLK_SRC, (where n identifies the applicable timer, 1
or 2).
If SYSCLK or DSPCLK is selected, a lower clock frequency, derived from the applicable system clock, can be selected
using the TIMERn_REFCLK_FREQ_SEL field (for SYSCLK source) or the TIMERn_DSPCLK_FREQ_SEL field (for
DSPCLK source). The applicable division ratio is determined automatically, assuming the respective clock source has
been correctly configured as described in Section 4.13.
Note that, depending on the DSPCLK frequency and the available clock dividers, the timer reference clock may differ from
the selected clock if DSPCLK is the selected source. In most cases, the reference clock frequency equals or exceeds the
requested frequency. A lower frequency is implemented if limited by either the DSPCLK frequency or the maximum
TIMERn clocking frequency.
If any source other than DSPCLK is selected, the clock can be further divided using TIMERn_REFCLK_DIV. Division ratios
in the range 1 to 128 can be selected.
Note that, if DSPCLK is enabled, the CS47L15 synchronizes the selected reference clock to DSPCLK. As a result of this,
if a non-DSPCLK is selected as source, the following additional constraints must be observed: the reference clock
frequency (after TIMERn_REFCLK_FREQ_SEL and after TIMERn_REFCLK_DIV) must be less than DSPCLK / 3, and
must be less than 12 MHz; it must also be close to 50% duty cycle. The TIMERn_REFCLK_DIV field can be used to ensure
that these criteria are met.
One final division, controlled by TIMERn_PRESCALE, determines the timer count frequency. This field is valid for all clock
reference sources; division ratios in the range 1 to 128 can be selected. The output from this division corresponds to the
frequency at which the TIMERn_COUNT fields are incremented (or decremented).
The maximum count value of the timer is determined by the TIMERn_MAX_COUNT field. This is the final count value
(when counting up), or the initial count value (when counting down). The current value of the timer counter can be read
from the TIMERn_CUR_COUNT field.
The timer is started by writing 1 to TIMERn_START. Note that, if the timer is already running, it restarts from its initial value.
The timer is stopped by writing 1 to TIMERn_STOP. The count direction (up or down) is selected using the TIMERn_DIR
bit.
The TIMERn_CONTINUOUS bit selects whether the timer automatically restarts after the end-of-count condition has been
reached. The TIMERn_RUNNING_STS indicates whether the timer is running, or if it has stopped.
Note that the timers should be stopped before making any changes to the respective configuration registers. The timer
configuration should only be changed if TIMERn_RUNNING_STS = 0.
4.5.2.3 Interrupts, GPIO, and Class D Speaker Driver Control
The timer status is an input to the interrupt control circuit and can be used to trigger an interrupt event after the final count
value is reached; see Section 4.12. Note that the interrupt does not occur immediately when the final count value is
reached; the interrupt is triggered at the point when the next update to the timer count value would be due.
98
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
The timer status can be output directly on a GPIO pin as an external indication of the timer activity. See Section 4.11 to
configure a GPIO pin for this function.
The timers can be used as a watchdog function to trigger a shutdown of the Class D speaker drivers. See Section 4.18 to
configure this function.
4.5.2.4 Timer Block Diagram and Control Registers
The timer block is shown in Fig. 4-31.
DSPCLK
32k Clock
MCLK1
MCLK2
SYSCLK
GPIO3
GPIO7
GPIO11
TIMERn_REFCLK_SRC
If DSPCLK is enabled, and a clock
source other than DSPCLK is selected,
f ≤ DSPCLK/3, f ≤ 12MHz
Divider
Divider
Divider
TIMERn_REFCLK_FREQ_SEL
SYSCLK only
TIMERn_DSPCLK_FREQ_SEL
DSPCLK only
TIMERn_REFCLK_DIV
Divide by 1, 2, 4, 8 … 64
except DSPCLK
TIMERn_PRESCALE
Divide by 1, 2, 4, 8 … 128
f = TIMERn
count rate
Figure 4-31. General-Purpose Timer
The timer control registers are described in Table 4-36.
DS1137PP1
99
CS47L15
4.5 DSP Peripheral Control
Table 4-36. General-Purpose Timer (TIMERn) Control
Register Address Bit
Label
Default
Description
Timer 1 Base Address = R311296 (0x4_C000)
Timer 2 Base Address = R311424 (0x4_C080)
Base address
21 TIMERn_
0
Timer Continuous Mode select
CONTINUOUS
Timern_Control
0 = Single mode
1 = Continuous mode
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field
20 TIMERn_DIR
0
Timer Count Direction
0 = Down
1 = Up
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field
18:16 TIMERn_
000 Timer Count Rate Prescale
PRESCALE[2:0]
000 = Divide by 1
011 = Divide by 8
110 = Divide by 64
001 = Divide by 2
100 = Divide by 16
111 = Divide by 128
010 = Divide by 4
101 = Divide by 32
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field
14:12 TIMERn_
000 Timer Reference Clock Divide (Not valid for DSPCLK source).
REFCLK_
011 = Divide by 8
110 = Divide by 64
000 = Divide by 1
DIV[2:0]
001 = Divide by 2
100 = Divide by 16
111 = Divide by 128
010 = Divide by 4
101 = Divide by 32
If DSPCLK is enabled, and DSPCLK is not selected as source, the output frequency from
this divider must be set less than or equal to DSPCLK / 3, and less than or equal to
12 MHz.
If DSPCLK is disabled, the output of this divider is used as clock reference for any
associated event logger. In this case, the divider output corresponds to the frequency of
event logging opportunities on the respective modules.
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field
10:8 TIMERn_
000 Timer Reference Frequency Select (SYSCLK source)
REFCLK_
000 = 6.144 MHz (5.6448 MHz)
FREQ_SEL[2:0]
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
011 = 49.152 MHz (45.1584 MHz)
All other codes are reserved.
The selected frequency must be less than or equal to the frequency of the source.
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field.
3:0 TIMERn_
0000 Timer Reference Source Select. Timer must be stopped (TIMERn_RUNNING_STS=0)
REFCLK_
when updating this field. Codes not listed are reserved.
SRC[3:0]
0000 = DSPCLK
0101 = MCLK2
1110 = GPIO7
0001 = 32-kHz clock
1000 = SYSCLK
1111 = GPIO11
0100 = MCLK1
1101 = GPIO3
Base address
31:0 TIMERn_MAX_ 0x0000 Timer Maximum Count.
+0x02
COUNT[31:0]
_0000 Final count value (when counting up). Starting count value (when counting down).
Timern_Count_
Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field.
Preset
Base address
4
TIMERn_STOP
0
Timer Stop Control
+0x06
Write 1 to stop.
Timern_Start_
0
TIMERn_
0
Timer Start Control
and_Stop
START
Write 1 to start.
If the timer is already running, it restarts from its initial value.
0
TIMERn_
0
Timer Running Status
Base address
RUNNING_STS
+0x08
0 = Timer stopped
Timern_Status
1 = Timer running
Base address
31:0 TIMERn_CUR_ 0x0000 Timer Current Count value
+0x0A
COUNT[31:0]
Timern_Count_
Readback
100
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
Table 4-36. General-Purpose Timer (TIMERn) Control (Cont.)
Register Address Bit
Label
Base address
15:0 TIMERn_
+0x0C
DSPCLK_
FREQ_
Timern_DSP_
SEL[15:0]
Clock_Config
Base address
+0x0E
Timern_DSP_
Clock_Status
4.5.3
15:0 TIMERn_
DSPCLK_
FREQ_
STS[15:0]
Default
Description
0x0000 Timer Reference Frequency Select (DSPCLK source)
Coded as LSB = 1/64 MHz, Valid from 5.6 MHz to 148 MHz.
The timer reference frequency must be less than or equal to the DSPCLK frequency. The
timer reference is generated by division of DSPCLK, and may differ from the selected
frequency. The timer reference frequency can be read from TIMERn_DSPCLK_FREQ_
STS.
Timer must be stopped (TIMERn_RUNNING_STS=0) when updating this field.
0x0000 Timer Reference Frequency (Read only)
Only valid when DSPCLK is the selected clock source.
Coded as LSB = 1/64 MHz.
DSP GPIO
The DSP GPIO function provides an advanced I/O capability, supporting enhanced flexibility for signal-processing
applications.
4.5.3.1 Overview
The CS47L15 supports up to 15 GPIO pins; these are implemented as alternate functions to a pin-specific capability.
The GPIOs can be used to provide status outputs and control signals to external hardware; the supported functions include
interrupt output, FLL clock output, accessory detection status, and S/PDIF or PWM-coded audio channels; see
Section 4.11.
The GPIOs can support miscellaneous logic input and output, interfacing directly with the integrated DSPs, or with the Host
Application software. A basic level of I/O functionality is described in Section 4.11, under the configuration where GPn_
FN = 0x001. The GPn_FN field selects the functionality for the respective pin, GPIOn.
The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected combinations of
GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in hardware. In a
typical use case, a different GPIO mask is defined for each DSP function; this provides a highly efficient mechanism for
the DSP to access the required input and output signals.
4.5.3.2 DSP GPIO Control
The DSP GPIO function is selected by setting GPn_FN = 0x002 for the respective GPIO pin (where n identifies the
applicable GPIOn pin).
Each DSP GPIO is controlled using bits that determine the direction (input/output) and the logic state (0/1) of the pin. These
bits are replicated in four control sets; each which can determine the logic level of any DSP GPIO.
Mask bits are provided within each control set, to determine which of the control sets has control of each DSP GPIO. To
avoid logic contention, a DSP GPIO output must be controlled (unmasked) in a maximum of one control set at any time.
Note that write access to the direction control bits (DSPGPn_SETx_DIR) and level control bits (DSPGPn_SETx_LVL) is
only valid when the channel (DSPGPn) is unmasked in the respective control set. Writes to these fields are implemented
for the unmasked DSP GPIOs, and are ignored in respect of the masked DSP GPIOs. Note that the level control bits
(DSPGPn_SETx_LVL) provide output level control only—they cannot be used to read the status of DSP GPIO inputs.
The logic level of the unmasked DSP GPIO outputs in any control set can be configured using a single register write.
Writing to the output level control registers determines the logic level of the unmasked DSP GPIOs in that set only; all other
outputs are unaffected.
DSP GPIO status bits are provided, indicating the logic level of every input or output pin that is configured as a DSP GPIO.
The DSPGPn_STS bits also provide logic-level indication for any pin that is configured as a GPIO input, with GPn_
FN = 0x001.Note that there is only one set of DSP GPIO status bits.
DS1137PP1
101
CS47L15
4.5 DSP Peripheral Control
The status bits indicate the logic level of the DSP GPIO outputs. The respective pins are driven as outputs if configured
as a DSP GPIO output, and unmasked in one of the control sets. Note that a DSP GPIO continues to be driven as an
output, even if the mask bit is subsequently asserted in that set. The pin only ceases to be driven if it is configured as a
DSP GPIO input and is unmasked in one of the control sets, or if the pin is configured as an input under a different GPn_
FN field selection.
4.5.3.3 Common Functions to Standard GPIOs
The DSP GPIO functions are implemented alongside the standard GPIO capability, providing an alternative method of
maskable I/O control for all of the GPIO pins. The DSP GPIO control bits in the register map are implemented in a manner
that supports efficient read/write access for multiple GPIOs at once.
The DSP GPIO logic is shown in Fig. 4-32, which also shows the control fields relating to the standard GPIO.
The DSP GPIO function is selected by setting GPn_FN = 0x002 for the respective GPIO pin. Integrated pull-up and
pull-down resistors are provided on each of the GPIO pins, which are also valid for DSP GPIO function. A bus keeper
function is supported on the GPIO pins; this is enabled using the respective pull-up and pull-down control bits. The bus
keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated). See
Table 4-72 for details of the GPIO pull-up and pull-down control bits.
4.5.3.4 DSP GPIO Block Diagram and Control Registers
Pin-Specific
Function
GPn_FN = 0x000
Input / Output control
Logic Level control
DSPGPn_SET1_LVL
DSPGPn_SET1_DIR
Input / Output control
Logic Level control
DSPGPn_SET2_LVL
DSPGPn_SET2_DIR
Input / Output control
Logic Level control
DSPGPn_SET3_LVL
DSPGPn_SET3_DIR
Input / Output control
Logic Level control
DSPGPn_SET4_LVL
DSPGPn_SET4_DIR
GPIO Control
& Readback
Mask control
DSPGPn_SET1_MASK
GPn_LVL
GPn_FN = 0x001
Mask control
DSPGPn_SET2_MASK
DSP GPIO
Readback
GPIOn
GPn_FN = 0x002
DSPGPn_STS
Mask control
GPn_PU
GPn_PD
GPn_FN
DSPGPn_SET3_MASK
GPn_FN > 0x002
Other GPIO
functions
Mask control
DSPGPn_SET4_MASK
GPn_POL
GPn_OP_CFG
These bits have no effect if GPn_FN = 0x000 or 0x002.
GPn_DB
Valid for GPn_LVL readback and GPIO IRQ event trigger only.
GPn_DIR
These bits have no effect if GPn_FN = 0x000 or 0x002.
If GPn_FN = 0x000, pin direction is set automatically .
If GPn_FN = 0x002, pin direction is set by DSPGPn_SETx_DIR.
Figure 4-32. DSP GPIO Control
102
DS1137PP1
CS47L15
4.5 DSP Peripheral Control
The control registers associated with the DSP GPIO are described in Table 4-37.
Table 4-37. DSP GPIO Control
Register Address
R315392 (0x4_D000)
DSPGP_Status_1
R315424 (0x4_D020)
DSPGP_SET1_Mask_1
R315456 (0x4_D040)
DSPGP_SET2_Mask_1
R315488 (0x4_D060)
DSPGP_SET3_Mask_1
R315520 (0x4_D080)
DSPGP_SET4_Mask_1
R315432 (0x4_D028)
DSPGP_SET1_Direction_1
R315464 (0x4_D048)
DSPGP_SET2_Direction_1
R315496 (0x4_D068)
DSPGP_SET3_Direction_1
R315528 (0x4_D088)
DSPGP_SET4_Direction_1
DS1137PP1
Bit
Label
14 DSPGP15_STS
13
12
11
10
9
8
7
6
5
4
3
2
1
0
14
DSPGP14_STS
DSPGP13_STS
DSPGP12_STS
DSPGP11_STS
DSPGP10_STS
DSPGP9_STS
DSPGP8_STS
DSPGP7_STS
DSPGP6_STS
DSPGP5_STS
DSPGP4_STS
DSPGP3_STS
DSPGP2_STS
DSPGP1_STS
DSPGP15_SETn_MASK
13
12
11
10
9
8
7
6
5
4
3
2
1
0
14
DSPGP14_SETn_MASK
DSPGP13_SETn_MASK
DSPGP12_SETn_MASK
DSPGP11_SETn_MASK
DSPGP10_SETn_MASK
DSPGP9_SETn_MASK
DSPGP8_SETn_MASK
DSPGP7_SETn_MASK
DSPGP6_SETn_MASK
DSPGP5_SETn_MASK
DSPGP4_SETn_MASK
DSPGP3_SETn_MASK
DSPGP2_SETn_MASK
DSPGP1_SETn_MASK
DSPGP15_SETn_DIR
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DSPGP14_SETn_DIR
DSPGP13_SETn_DIR
DSPGP12_SETn_DIR
DSPGP11_SETn_DIR
DSPGP10_SETn_DIR
DSPGP9_SETn_DIR
DSPGP8_SETn_DIR
DSPGP7_SETn_DIR
DSPGP6_SETn_DIR
DSPGP5_SETn_DIR
DSPGP4_SETn_DIR
DSPGP3_SETn_DIR
DSPGP2_SETn_DIR
DSPGP1_SETn_DIR
Default
Description
0
DSPGP15 Status
Valid for DSPGP input and output
0
DSPGP14 Status
0
DSPGP13 Status
0
DSPGP12 Status
0
DSPGP11 Status
0
DSPGP10 Status
0
DSPGP9 Status
0
DSPGP8 Status
0
DSPGP7 Status
0
DSPGP6 Status
0
DSPGP5 Status
0
DSPGP4 Status
0
DSPGP3 Status
0
DSPGP2 Status
0
DSPGP1 Status
1
DSP SETn GPIO15 Mask Control
0 = Unmasked
1 = Masked
A GPIO pin should be unmasked in a maximum of one SET at any time.
1
DSP SETn GPIO14 Mask Control
1
DSP SETn GPIO13 Mask Control
1
DSP SETn GPIO12 Mask Control
1
DSP SETn GPIO11 Mask Control
1
DSP SETn GPIO10 Mask Control
1
DSP SETn GPIO9 Mask Control
1
DSP SETn GPIO8 Mask Control
1
DSP SETn GPIO7 Mask Control
1
DSP SETn GPIO6 Mask Control
1
DSP SETn GPIO5 Mask Control
1
DSP SETn GPIO4 Mask Control
1
DSP SETn GPIO3 Mask Control
1
DSP SETn GPIO2 Mask Control
1
DSP SETn GPIO1 Mask Control
1
DSP SETn GPIO15 Direction Control
0 = Output
1 = Input
1
DSP SETn GPIO14 Direction Control
1
DSP SETn GPIO13 Direction Control
1
DSP SETn GPIO12 Direction Control
1
DSP SETn GPIO11 Direction Control
1
DSP SETn GPIO10 Direction Control
1
DSP SETn GPIO9 Direction Control
1
DSP SETn GPIO8 Direction Control
1
DSP SETn GPIO7 Direction Control
1
DSP SETn GPIO6 Direction Control
1
DSP SETn GPIO5 Direction Control
1
DSP SETn GPIO4 Direction Control
1
DSP SETn GPIO3 Direction Control
1
DSP SETn GPIO2 Direction Control
1
DSP SETn GPIO1 Direction Control
103
CS47L15
4.6 Digital Audio Interface
Table 4-37. DSP GPIO Control (Cont.)
Register Address
R315440 (0x4_D030)
DSPGP_SET1_Level_1
R315472 (0x4_D050)
DSPGP_SET2_Level_1
R315504 (0x4_D070)
DSPGP_SET3_Level_1
R315536 (0x4_D090)
DSPGP_SET4_Level_1
Bit
Label
14 DSPGP15_SETn_LVL
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DSPGP14_SETn_LVL
DSPGP13_SETn_LVL
DSPGP12_SETn_LVL
DSPGP11_SETn_LVL
DSPGP10_SETn_LVL
DSPGP9_SETn_LVL
DSPGP8_SETn_LVL
DSPGP7_SETn_LVL
DSPGP6_SETn_LVL
DSPGP5_SETn_LVL
DSPGP4_SETn_LVL
DSPGP3_SETn_LVL
DSPGP2_SETn_LVL
DSPGP1_SETn_LVL
Default
Description
0
DSP SETn GPIO15 Output Level
0 = Logic 0
1 = Logic 1
0
DSP SETn GPIO14 Output Level
0
DSP SETn GPIO13 Output Level
0
DSP SETn GPIO12 Output Level
0
DSP SETn GPIO11 Output Level
0
DSP SETn GPIO10 Output Level
0
DSP SETn GPIO9 Output Level
0
DSP SETn GPIO8 Output Level
0
DSP SETn GPIO7 Output Level
0
DSP SETn GPIO6 Output Level
0
DSP SETn GPIO5 Output Level
0
DSP SETn GPIO4 Output Level
0
DSP SETn GPIO3 Output Level
0
DSP SETn GPIO2 Output Level
0
DSP SETn GPIO1 Output Level
4.6 Digital Audio Interface
The CS47L15 provides three audio interfaces, AIF1, AIF2, and AIF3. Each of these is independently configurable on the
respective transmit (TX) and receive (RX) paths. AIF1 supports up to six channels of input and output signal paths; AIF2
supports up to four channels of input and output signal paths; AIF3 supports up to two channels of input and output signal
paths.
The data sources for the audio interface transmit (TX) paths can be selected from any of the CS47L15 input signal paths,
or from the digital-core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of
the digital-core processing functions or digital-core outputs. See Section 4.3 for details of the digital-core routing options.
The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical
connections include applications processor, baseband processor, and wireless transceiver. A typical configuration is
shown in Fig. 4-33.
Applications
Processor
Audio Interface 1
Baseband
Processor
Audio Interface 2
Wireless
Transceiver
Audio Interface 3
CS47L15
Figure 4-33. Typical AIF Connections
In the general case, the digital audio interface uses four pins:
104
DS1137PP1
CS47L15
4.6 Digital Audio Interface
•
TXDAT: data output
•
RXDAT: data input
•
BCLK: bit clock, for synchronization
•
LRCLK: left/right data-alignment clock
In Master Mode, the clock signals BCLK and LRCLK are outputs from the CS47L15. In Slave Mode, these signals are
inputs, as shown in Section 4.6.1.
The following interface formats are supported on AIF1–AIF3:
•
DSP Mode A.
•
DSP Mode B
•
I2S
•
Left-justified
The left-justified and DSP-B formats are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the CS47L15).
These modes cannot be supported in Slave Mode.
The audio interface formats are described in Section 4.6.2. The bit order is MSB-first in each case; data words are encoded
in 2’s complement format. Mono PCM operation can be supported using the DSP modes. Refer to Table 3-16 through
Table 3-18 for signal timing information.
4.6.1
Master and Slave Mode Operation
The CS47L15 digital audio interfaces can operate as a master or slave, as shown in Fig. 4-34 and Fig. 4-35. The
associated control bits are described in Section 4.7.
BCLK
BCLK
LRCLK
CS47L15
TXDAT
LRCLK
Processor
CS47L15
RXDAT
Figure 4-34. Master Mode
4.6.2
TXDAT
Processor
RXDAT
Figure 4-35. Slave Mode
Audio Data Formats
The CS47L15 digital audio interfaces can be configured to operate in I2S, left-justified, DSP-A, or DSP-B interface modes.
Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the
CS47L15).
The digital audio interfaces also provide flexibility to support multiple slots of audio data within each LRCLK frame. This
flexibility allows multiple audio channels to be supported within a single LRCLK frame.
The data formats described in this section are generic descriptions, assuming only one stereo pair of audio samples per
LRCLK frame. In these cases, the AIF is configured to transmit (or receive) in the first available position in each frame (i.e.,
the Slot 0 position).
The options for multichannel operation are described in Section 4.6.3.
DS1137PP1
105
CS47L15
4.6 Digital Audio Interface
The audio data modes supported by the CS47L15 are described as follows. Note that the BCLK and LRCLK signals are
configurable—the polarity of these signals can be inverted if required, and the timing of the LRCLK transition can also be
adjusted. The following descriptions all assume the default configuration (noninverted polarity, normal timing) of these
signals.
•
In DSP modes, the left channel MSB is available on either the first (Mode B) or second (Mode A) rising edge of
BCLK following a rising edge of LRCLK. Right-channel data immediately follows left channel data. Depending on
word length, BCLK frequency, and sample rate, there may be unused BCLK cycles between the LSB of the right
channel data and the next sample.
In Master Mode, the LRCLK output resembles the frame pulse shown in Fig. 4-36 and Fig. 4-37. In Slave Mode, it
is possible to use any length of frame pulse less than 1/Fs, providing the falling edge of the frame pulse occurs at
least one BCLK period before the rising edge of the next frame pulse.
PCM operation is supported in DSP interface mode. CS47L15 data that is output on the left channel is read as mono
data by the receiving equipment. Mono PCM data received by the CS47L15 is treated as left-channel data. This
may be routed to the left/right playback paths using the control fields described in Section 4.3.
DSP Mode A data format is shown in Fig. 4-36.
1/Fs
LRCLK
In Slave Mode, the falling edge can occur anywhere in this area
1 BCLK
1 BCLK
BCLK
LEFT CHANNEL
RXDAT/
TXDAT
1
2
MSB
3
RIGHT CHANNEL
n-2
n-1
n
1
2
3
n-2
n-1
n
LSB
Input Word Length (WL)
Figure 4-36. DSP Mode A Data Format
DSP Mode B data format is shown in Fig. 4-37.
1/Fs
LRCLK
In Slave Mode, the falling edge can occur anywhere in this area
1 BCLK
1 BCLK
BCLK
LEFT CHANNEL
RXDAT/
TXDAT
1
2
3
MSB
n-2
RIGHT CHANNEL
n-1
n
1
2
3
n-2
n-1
n
LSB
Input Word Length (WL)
Figure 4-37. DSP Mode B Data Format
•
In I2S Mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits
up to the LSB are then transmitted in order. Depending on word length, BCLK frequency, and sample rate, there
may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
I2S Mode data format is shown in Fig. 4-38.
1/Fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
1 BCLK
RXDAT/
TXDAT
1
MSB
2
1 BCLK
3
n-2
n-1
Input Word Length (WL)
n
1
2
3
n-2
n-1
n
LSB
Figure 4-38. I2S Data Format (Assuming n-Bit Word Length)
106
DS1137PP1
CS47L15
4.6 Digital Audio Interface
•
In Left-Justified Mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other
bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency, and sample rate, there
may be unused BCLK cycles before each LRCLK transition.
Left-Justified Mode data format is shown in Fig. 4-39.
1/Fs
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
RXDAT/
TXDAT
1
MSB
2
3
n-2
n-1
Input Word Length (WL)
n
1
2
3
n-2
n-1
n
LSB
Figure 4-39. Left-Justified Data Format (Assuming n-Bit Word Length)
4.6.3
AIF Time-Slot Configuration
Digital audio interfaces AIF1 and AIF2 support multichannel operation, with up to six channels of input and output on AIF1,
and up to four channels on AIF2. A high degree of flexibility is provided to define the position of the audio samples within
each LRCLK frame; the audio channel samples may be arranged in any order within the frame.
AIF3 also provides flexible configuration options, but this interface supports only one stereo input and one stereo output
path.
Note that, on each interface, all input and output channels must operate at the same sample rate (Fs).
Each of the audio channels can be enabled or disabled independently on the transmit (TX) and receive (RX) signal paths.
For each enabled channel, the audio samples are assigned to one time slot within the LRCLK frame.
In DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and left-justified modes,
the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered time slots are
arranged in the second half of the frame.
The time slots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is no requirement to
assign every available time slot to an audio sample; slots may be left unused, if desired. Care is required, however, to
ensure that no time slot is allocated to more than one audio channel.
The number of BCLK cycles within a slot is configurable; this is the slot-length. The number of valid data bits within a slot
is also configurable; this is the word length. The number of BCLK cycles per LRCLK frame must be configured; it must be
ensured that there are enough BCLK cycles within each LRCLK frame to transmit or receive all of the enabled audio
channels.
Examples of the AIF time-slot configurations are shown in Fig. 4-40 through Fig. 4-43. One example is shown for each of
the four possible data formats.
DS1137PP1
107
CS47L15
4.6 Digital Audio Interface
Fig. 4-40 shows an example of DSP Mode A format. Four enabled audio channels are shown, allocated to time slots 0
through 3.
LRCLK
BCLK
TXDAT/
RXDAT
Slot 0
Channel 1
Slot 0 AIF1[TX1/RX1]_SLOT = 0
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
...
Slot 1 AIF1[TX2/RX2]_SLOT = 1
Channel 2
Slot 2 AIF1[TX3/RX3]_SLOT = 2
Channel 3
Slot 3 AIF1[TX4/RX4]_SLOT = 3
Channel 4
Figure 4-40. DSP Mode A Example
Fig. 4-41 shows an example of DSP Mode B format. Six enabled audio channels are shown, with time slots 4 and 5
unused.
LRCLK
BCLK
TXDAT/
RXDAT
Slot 0
Slot 1
Slot 2
Slot 4
Slot 5
Slot 6
Slot 7
...
Slot 2 AIF1[TX1/RX1]_SLOT = 2
Channel 1
Slot 3 AIF1[TX2/RX2]_SLOT = 3
Channel 2
Channel 3
Slot 3
Slot 0 AIF1[TX3/RX3]_SLOT = 0
Slot 1 AIF1[TX4/RX4]_SLOT = 1
Channel 4
Slot 6 AIF1[TX5/RX5]_SLOT = 6
Channel 5
Slot 7 AIF1[TX6/RX6]_SLOT = 7
Channel 6
Figure 4-41. DSP Mode B Example
Fig. 4-42 shows an example of I2S format. Four enabled channels are shown, allocated to time slots 0 through 3.
LRCLK
BCLK
TXDAT/
RXDAT
Slot 0
Channel 1
Slot 0 AIF1[TX1/RX1]_SLOT = 0
Slot 2
Slot 4
...
Channel 4
Slot 3
Slot 5
...
Slot 1 AIF1[TX2/RX2]_SLOT = 1
Channel 2
Channel 3
Slot 1
Slot 2 AIF1[TX3/RX3]_SLOT = 2
Slot 3 AIF1[TX4/RX4]_SLOT = 3
Figure 4-42. I2S Example
108
DS1137PP1
CS47L15
4.6 Digital Audio Interface
Fig. 4-43 shows an example of left-justified format. Six enabled channels are shown.
LRCLK
BCLK
TXDAT/
RXDAT
Slot 0
Slot 2
Slot 4
...
Slot 1
Slot 3
Slot 4 AIF1[TX2/RX2]_SLOT = 4
Slot 1 AIF1[TX3/RX3]_SLOT = 1
Channel 3
Slot 3 AIF1[TX4/RX4]_SLOT = 3
Channel 4
Channel 5
Channel 6
...
Slot 5 AIF1[TX1/RX1]_SLOT = 5
Channel 1
Channel 2
Slot 5
Slot 0 AIF1[TX5/RX5]_SLOT = 0
Slot 2 AIF1[TX6/RX6]_SLOT = 2
Figure 4-43. Left-Justified Example
4.6.4
TDM Operation Between Three or More Devices
The AIF operation described in Section 4.6.3 illustrates how multiple audio channels can be interleaved on a single TXDAT
or RXDAT pin. The interface uses TDM to allocate time periods to each of the audio channels in turn.
This form of TDM is implemented between two devices, using the electrical connections shown Fig. 4-34 or Fig. 4-35.
It is also possible to implement TDM between three or more devices. This allows one codec to receive audio data from
two other devices simultaneously on a single audio interface, as shown in Fig. 4-44, Fig. 4-45, and Fig. 4-46.
The CS47L15 provides full support for TDM operation. The TXDAT pin can be tristated when not transmitting data, in order
to allow other devices to transmit on the same wire. The behavior of the TXDAT pin is configurable, to allow maximum
flexibility to interface with other devices in this way.
Typical configurations of TDM operation between three devices are shown in Fig. 4-44, Fig. 4-45, and Fig. 4-46.
DS1137PP1
109
CS47L15
4.6 Digital Audio Interface
BCLK
BCLK
LRCLK
LRCLK
CS47L15
CS47L15
or similar
CODEC
Processor
TXDAT
CS47L15
TXDAT
RXDAT
RXDAT
BCLK
BCLK
LRCLK
CS47L15
or similar
CODEC
TXDAT
RXDAT
Processor
LRCLK
TXDAT
RXDAT
Figure 4-44. TDM with CS47L15 as Master
Figure 4-45. TDM with Other Codec as Master
BCLK
LRCLK
CS47L15
TXDAT
Processor
RXDAT
BCLK
CS47L15
or similar
CODEC
LRCLK
TXDAT
RXDAT
Figure 4-46. TDM with Processor as Master
Note:
110
The CS47L15 is a 24-bit device. If the user operates the CS47L15 in 32-Bit Mode, the 8 LSBs are ignored on the
receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if
necessary to the RXDAT line and the TXDAT line in TDM mode.
DS1137PP1
CS47L15
4.7 Digital Audio Interface Control
4.7 Digital Audio Interface Control
This section describes the configuration of the CS47L15 digital audio interface paths.
AIF1 supports up to six input signal paths and up to six output signal paths; AIF2 supports up to four input signal paths
and up to four output signal paths; AIF3 supports up to two channels of input and output signal paths. The digital audio
interfaces can be configured as master or slave interfaces; mixed master/slave configurations are also possible.
Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input (RX) paths
use shared BCLK and LRCLK control signals.
The digital audio interface supports flexible data formats, selectable word length, configurable time-slot allocations, and
TDM tristate control.
The audio interfaces can be reconfigured while enabled, including changes to the LRCLK frame length and the channel
time-slot configurations. Care is required to ensure that any on-the-fly reconfiguration does not cause corruption to the
active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.
4.7.1
AIF Sample-Rate Control
The AIF RX inputs may be selected as input to the digital mixers or signal-processing functions within the CS47L15 digital
core. The AIF TX outputs are derived from the respective output mixers.
The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE field—see Table 4-24.
Note that sample-rate conversion is required when routing the AIF paths to any signal chain that is configured for a different
sample rate.
4.7.2
AIF Pin Configuration
The external connections associated with each digital audio interface (AIF) are implemented on multi-function GPIO pins,
which must be configured for the respective AIF functions when required. The AIF connections are alternative functions
available on specific GPIO pins. See Section 4.11 to configure the GPIO pins for AIF operation.
Integrated pull-up and pull-down resistors can be enabled on the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This is
provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices. Each of the
pull-up and pull-down resistors can be configured independently using the fields described in Table 4-72.
If the pull-up and pull-down resistors are both enabled, the CS47L15 provides a bus keeper function on the respective pin.
The bus-keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated).
4.7.3
AIF Master/Slave Control
The digital audio interfaces can operate in master or slave modes and also in mixed master/slave configurations. In Master
Mode, the BCLK and LRCLK signals are generated by the CS47L15 when any of the respective digital audio interface
channels is enabled. In Slave Mode, these outputs are disabled by default to allow another device to drive these pins.
Master Mode is selected on the AIFnBCLK pin by setting AIFn_BCLK_MSTR. In Master Mode, the AIFnBCLK signal is
generated by the CS47L15 when one or more AIFn channels is enabled.
When the AIFn_BCLK_FRC bit is set in BCLK Master Mode, the AIFnBCLK signal is output at all times, including when
none of the AIFn channels is enabled.
The AIFnBCLK signal can be inverted in master or slave modes using the AIFn_BCLK_INV bit.
Master Mode is selected on the AIFnLRCLK pin by setting AIFn_LRCLK_MSTR. In Master Mode, the AIFnLRCLK signal
is generated by the CS47L15 when one or more AIFn channels is enabled.
When AIFn_LRCLK_FRC is set in LRCLK Master Mode, the AIFnLRCLK signal is output at all times, including when none
of the AIFn channels is enabled. Note that AIFnLRCLK is derived from AIFnBCLK, and an internal or external AIFnBCLK
signal must be present to generate AIFnLRCLK.
The AIFnLRCLK signal can be inverted in master or slave modes using the AIFn_LRCLK_INV bit.
DS1137PP1
111
CS47L15
4.7 Digital Audio Interface Control
The timing of the AIFnLRCLK signal is selectable using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition
is advanced to the previous BCLK phase (as compared with the default behavior). Further details of this option, and
conditions for valid use cases, are described in Section 4.7.3.1.
The AIF1 master/slave control registers are described in Table 4-38.
Table 4-38. AIF1 Master/Slave Control
Register Address Bit
Label
R1280 (0x0500)
7 AIF1_
BCLK_INV
AIF1_BCLK_Ctrl
R1282 (0x0502)
AIF1_Rx_Pin_Ctrl
Default
Description
0
AIF1 Audio Interface BCLK Invert
0 = AIF1BCLK not inverted
1 = AIF1BCLK inverted
6 AIF1_
0
AIF1 Audio Interface BCLK Output Control
BCLK_FRC
0 = Normal
1 = AIF1BCLK always enabled in Master Mode
5 AIF1_
0
AIF1 Audio Interface BCLK Master Select
BCLK_
0 = AIF1BCLK Slave Mode
MSTR
1 = AIF1BCLK Master Mode
4 AIF1_
0
AIF1 Audio Interface LRCLK Advance
LRCLK_
0 = Normal
ADV
1 = AIF1LRCLK transition is advanced to the previous BCLK phase
2 AIF1_
0
AIF1 Audio Interface LRCLK Invert
LRCLK_INV
0 = AIF1LRCLK not inverted
1 = AIF1LRCLK inverted
1 AIF1_
0
AIF1 Audio Interface LRCLK Output Control
LRCLK_
0 = Normal
FRC
1 = AIF1LRCLK always enabled in Master Mode
0 AIF1_
0
AIF1 Audio Interface LRCLK Master Select
LRCLK_
0 = AIF1LRCLK Slave Mode
MSTR
1 = AIF1LRCLK Master Mode
The AIF2 master/slave control registers are described in Table 4-39.
Table 4-39. AIF2 Master/Slave Control
Register Address Bit
Label
Default
Description
R1344 (0x0540)
7 AIF2_BCLK_
0
AIF2 Audio Interface BCLK Invert
INV
AIF2_BCLK_Ctrl
0 = AIF2BCLK not inverted
1 = AIF2BCLK inverted
6 AIF2_BCLK_
0
AIF2 Audio Interface BCLK Output Control
FRC
0 = Normal
1 = AIF2BCLK always enabled in Master Mode
5 AIF2_BCLK_
0
AIF2 Audio Interface BCLK Master Select
MSTR
0 = AIF2BCLK Slave Mode
1 = AIF2BCLK Master Mode
R1346 (0x0542)
4 AIF2_
0
AIF2 Audio Interface LRCLK Advance
LRCLK_ADV
AIF2_Rx_Pin_Ctrl
0 = Normal
1 = AIF2LRCLK transition is advanced to the previous BCLK phase
2 AIF2_
0
AIF2 Audio Interface LRCLK Invert
LRCLK_INV
0 = AIF2LRCLK not inverted
1 = AIF2LRCLK inverted
1 AIF2_
0
AIF2 Audio Interface LRCLK Output Control
LRCLK_FRC
0 = Normal
1 = AIF2LRCLK always enabled in Master Mode
0 AIF2_
0
AIF2 Audio Interface LRCLK Master Select
LRCLK_
0 = AIF2LRCLK Slave Mode
MSTR
1 = AIF2LRCLK Master Mode
112
DS1137PP1
CS47L15
4.7 Digital Audio Interface Control
The AIF3 master/slave control registers are described in Table 4-40.
Table 4-40. AIF3 Master/Slave Control
Register Address Bit
Label
Default
Description
R1408 (0x0580)
7 AIF3_BCLK_
0
AIF3 Audio Interface BCLK Invert
INV
AIF3_BCLK_Ctrl
0 = AIF3BCLK not inverted
1 = AIF3BCLK inverted
6 AIF3_BCLK_
0
AIF3 Audio Interface BCLK Output Control
FRC
0 = Normal
1 = AIF3BCLK always enabled in Master Mode
5 AIF3_BCLK_
0
AIF3 Audio Interface BCLK Master Select
MSTR
0 = AIF3BCLK Slave Mode
1 = AIF3BCLK Master Mode
R1410 (0x0582)
4 AIF3_
0
AIF3 Audio Interface LRCLK Advance
LRCLK_ADV
AIF3_Rx_Pin_Ctrl
0 = Normal
1 = AIF3LRCLK transition is advanced to the previous BCLK phase
2 AIF3_
0
AIF3 Audio Interface LRCLK Invert
LRCLK_INV
0 = AIF3LRCLK not inverted
1 = AIF3LRCLK inverted
1 AIF3_
0
AIF3 Audio Interface LRCLK Output Control
LRCLK_FRC
0 = Normal
1 = AIF3LRCLK always enabled in Master Mode
0 AIF3_
0
AIF3 Audio Interface LRCLK Master Select
LRCLK_
0 = AIF3LRCLK Slave Mode
MSTR
1 = AIF3LRCLK Master Mode
4.7.3.1 LRCLK Advance
The timing of the AIFnLRCLK signal can be adjusted using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition
is advanced to the previous BCLK phase (as compared with the default behavior).
The LRCLK-advance option (AIFn_LRCLK_ADV = 1) is valid for DSP-A mode only, operating in Master Mode.
Note:
BCLK inversion must be enabled (AIFn_BCLK_INV = 1) if the LRCLK-advance option is enabled.
The adjusted interface timing (AIFn_LRCLK_ADV = 1), is shown in Fig. 4-47. The left-channel MSB is available on the
second rising edge of BCLK, 1.5 BCLK cycles after the LRCLK rising edge—assuming the BCLK output is inverted.
1/Fs
LRCLK
1.5 BCLK
BCLK
LEFT CHANNEL
RXDAT/
TXDAT
1
MSB
2
3
n-2
Input Word Length (WL)
RIGHT CHANNEL
n-1
n
1
2
3
n-2
n-1
n
LSB
Figure 4-47. LRCLK advance—DSP-A Master Mode
4.7.4
AIF Signal Path Enable
The AIF1 interface supports up to six input (RX) channels and up to six output (TX) channels. Each channel is enabled or
disabled using the bits defined in Table 4-41.
The AIF2 interface supports up to four input (RX) channels and up to four output (TX) channels. Each channel is enabled
or disabled using the bits defined in Table 4-42.
The AIF3 interface supports up to two input (RX) channels and up to two output (TX) channels. Each channel is enabled
or disabled using the bits defined in Table 4-43.
DS1137PP1
113
CS47L15
4.7 Digital Audio Interface Control
The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. See Section 4.13 for
details of the system clocks.
The audio interfaces can be reconfigured if enabled, including changes to the LRCLK frame length and the channel
time-slot configurations. Care is required to ensure that this on-the-fly reconfiguration does not cause corruption to the
active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the
commanded signal paths and processing functions. If the frequency is too low, an attempt to enable an AIF signal path
fails. Note that active signal paths are not affected under such circumstances.
The AIF1 signal-path-enable bits are described in Table 4-41.
Table 4-41. AIF1 Signal Path Enable
Register Address
R1305 (0x0519)
AIF1_Tx_Enables
R1306 (0x051A)
AIF1_Rx_Enables
114
Bit
5
Label
AIF1TX6_ENA
Default
0
4
AIF1TX5_ENA
0
3
AIF1TX4_ENA
0
2
AIF1TX3_ENA
0
1
AIF1TX2_ENA
0
0
AIF1TX1_ENA
0
5
AIF1RX6_ENA
0
4
AIF1RX5_ENA
0
3
AIF1RX4_ENA
0
2
AIF1RX3_ENA
0
1
AIF1RX2_ENA
0
0
AIF1RX1_ENA
0
Description
AIF1 Audio Interface TX Channel 6 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface TX Channel 5 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface TX Channel 4 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface TX Channel 3 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface TX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface TX Channel 1 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 6 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 5 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 4 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 3 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF1 Audio Interface RX Channel 1 Enable
0 = Disabled
1 = Enabled
DS1137PP1
CS47L15
4.7 Digital Audio Interface Control
The AIF2 signal-path-enable bits are described in Table 4-42.
Table 4-42. AIF2 Signal Path Enable
Register Address
R1369 (0x0559)
AIF2_Tx_Enables
R1370 (0x055A)
AIF2_Rx_Enables
Bit
3
Label
AIF2TX4_ENA
Default
0
2
AIF2RX3_ENA
0
1
AIF2RX2_ENA
0
0
AIF2TX1_ENA
0
3
AIF2RX4_ENA
0
2
AIF2RX3_ENA
0
1
AIF2RX2_ENA
0
0
AIF2RX1_ENA
0
Description
AIF2 Audio Interface TX Channel 4 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 3 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface TX Channel 1 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 4 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 3 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF2 Audio Interface RX Channel 1 Enable
0 = Disabled
1 = Enabled
The AIF3 signal-path-enable bits are described in Table 4-43.
Table 4-43. AIF3 Signal Path Enable
Register Address
R1433 (0x0599)
AIF3_Tx_Enables
R1434 (0x059A)
AIF3_Rx_Enables
4.7.5
Bit
1
Label
AIF3TX2_ENA
Default
0
0
AIF3TX1_ENA
0
1
AIF3RX2_ENA
0
0
AIF3RX1_ENA
0
Description
AIF3 Audio Interface TX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF3 Audio Interface TX Channel 1 Enable
0 = Disabled
1 = Enabled
AIF3 Audio Interface RX Channel 2 Enable
0 = Disabled
1 = Enabled
AIF3 Audio Interface RX Channel 1 Enable
0 = Disabled
1 = Enabled
AIF BCLK and LRCLK Control
The AIFnBCLK frequency is selected using the AIFn_BCLK_FREQ field. For each setting of this field, the actual frequency
depends on whether AIFn is configured for a 48-kHz-related sample rate (SAMPLE_RATE_n = 01XXX or 10XXX) or a
44.1kHz-related sample rate (SAMPLE_RATE_n = 10XXX), as described in Table 4-44 through Table 4-46.
The selected AIFnBCLK rate must be less than or equal to SYSCLK/2. See Section 4.13 for details of SYSCLK clock
domain, and the associated control registers.
The AIFnLRCLK frequency is controlled relative to AIFnBCLK by the AIFn_BCPF divider.
Note that the BCLK rate must be configured in master or slave modes, using the AIFn_BCLK_FREQ fields. The LRCLK
rates only require to be configured in Master Mode.
DS1137PP1
115
CS47L15
4.7 Digital Audio Interface Control
The AIF1 BCLK/LRCLK control fields are described in Table 4-44.
Table 4-44. AIF1 BCLK and LRCLK Control
Register
Address
R1280
(0x0500)
AIF1_
BCLK_Ctrl
Bit
Label
4:0 AIF1_BCLK_
FREQ[4:0]
R1286
12:0 AIF1_
(0x0506)
BCPF[12:0]
AIF1_Rx_
BCLK_Rate
Default
Description
0x0C
AIF1BCLK Rate. The AIF1BCLK rate must be less than or equal to SYSCLK/2.
0x00–0x01 = Reserved
0x07 = 384 kHz (352.8 kHz)
0x0D = 3.072 MHz (2.8824 MHz)
0x02 = 64 kHz (58.8 kHz)
0x08 = 512 kHz (470.4 kHz)
0x0E = 4.096 MHz (3.7632 MHz)
0x03 = 96 kHz (88.2 kHz)
0x09 = 768 kHz (705.6 kHz)
0x0F = 6.144 MHz (5.6448 MHz)
0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz)
0x10 = 8.192 MHz (7.5264 MHz)
0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz)
0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz)
The frequencies in brackets apply for 44.1 kHz–related sample rates only (SAMPLE_RATE_
n = 01XXX).
0x0040 AIF1LRCLK Rate. Selects the number of BCLK cycles per AIF1LRCLK frame. AIF1LRCLK
clock = AIF1BCLK/AIF1_BCPF.
Integer (LSB = 1), Valid from 8 to 8191.
The AIF2 BCLK/LRCLK control fields are described in Table 4-45.
Table 4-45. AIF2 BCLK and LRCLK Control
Register
Address
R1344
(0x0540)
AIF2_
BCLK_Ctrl
Bit
Label
4:0 AIF2_BCLK_
FREQ[4:0]
R1350
12:0 AIF2_
(0x0546)
BCPF[12:0]
AIF2_Rx_
BCLK_Rate
Default
Description
0x0C
AIF2BCLK Rate. The AIF2BCLK rate must be less than or equal to SYSCLK/2.
0x00–0x01 = Reserved
0x07 = 384 kHz (352.8 kHz)
0x0D = 3.072 MHz (2.8824 MHz)
0x02 = 64 kHz (58.8 kHz)
0x08 = 512 kHz (470.4 kHz)
0x0E = 4.096 MHz (3.7632 MHz)
0x03 = 96 kHz (88.2 kHz)
0x09 = 768 kHz (705.6 kHz)
0x0F = 6.144 MHz (5.6448 MHz)
0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz)
0x10 = 8.192 MHz (7.5264 MHz)
0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz)
0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz)
The frequencies in brackets apply for 44.1 kHz–related sample rates only (SAMPLE_RATE_
n = 01XXX).
0x0040 AIF2LRCLK Rate. Selects the number of BCLK cycles per AIF2LRCLK frame. AIF2LRCLK
clock = AIF2BCLK/AIF2_BCPF.
Integer (LSB = 1), Valid from 8 to 8191.
The AIF3 BCLK/LRCLK control fields are described in Table 4-46.
Table 4-46. AIF3 BCLK and LRCLK Control
Register
Address
R1408
(0x0580)
AIF3_
BCLK_Ctrl
R1414
(0x0586)
AIF3_Rx_
BCLK_Rate
116
Bit
Label
4:0 AIF3_
BCLK_
FREQ[4:0]
Default
Description
0x0C
AIF3BCLK Rate. The AIF3BCLK rate must be less than or equal to SYSCLK/2.
0x00–0x01 = Reserved
0x07 = 384 kHz (352.8 kHz)
0x0D = 3.072 MHz (2.8824 MHz)
0x02 = 64 kHz (58.8 kHz)
0x08 = 512 kHz (470.4 kHz)
0x0E = 4.096 MHz (3.7632 MHz)
0x03 = 96 kHz (88.2 kHz)
0x09 = 768 kHz (705.6 kHz)
0x0F = 6.144 MHz (5.6448 MHz)
0x04 = 128 kHz (117.6 kHz) 0x0A = 1.024 MHz (940.8 kHz)
0x10 = 8.192 MHz (7.5264 MHz)
0x05 = 192 kHz (176.4 kHz) 0x0B = 1.536 MHz (1.4112 MHz) 0x11 = 12.288 MHz (11.2896 MHz)
0x06 = 256 kHz (235.2 kHz) 0x0C = 2.048 MHz (1.8816 MHz) 0x12 = 24.576 MHz (22.5792 MHz)
The frequencies in brackets apply for 44.1 kHz–related sample rates only (SAMPLE_RATE_
n = 01XXX).
12:0 AIF3_
0x0040 AIF3LRCLK Rate. Selects the number of BCLK cycles per AIF3LRCLK frame. AIF3LRCLK clock =
BCPF[12:0]
AIF3BCLK/AIF3_BCPF.
Integer (LSB = 1), Valid from 8 to 8191.
DS1137PP1
CS47L15
4.7 Digital Audio Interface Control
4.7.6
AIF Digital Audio Data Control
The fields controlling the audio data format, word length, and slot configurations for AIF1, AIF2, and AIF3 are described
in Table 4-47, Table 4-48, and Table 4-49 respectively.
Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the
CS47L15).
The AIFn slot length is the number of BCLK cycles in one time slot within the overall LRCLK frame. The word length is the
number of valid data bits within each time slot. If the word length is less than the slot length, there are unused BCLK cycles
at the end of each time slot. The AIFn word length and slot length is independently selectable for the input (RX) and output
(TX) paths.
For each AIF input (RX) and AIF output (TX) channel, the position of the audio data sample within the LRCLK frame is
configurable. The x_SLOT fields define the time-slot position of the audio sample for the associated audio channel. Valid
selections are Slot 0 upwards. The time slots are numbered as shown in Fig. 4-40 through Fig. 4-43.
Note that, in DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and
left-justified modes, the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered
time slots are arranged in the second half of the frame.
The AIF1 data control fields are described in Table 4-47.
Table 4-47. AIF1 Digital Audio Data Control
Register Address
R1284 (0x0504)
AIF1_Format
Bit
2:0
R1287 (0x0507)
AIF1_Frame_Ctrl_
1
13:8 AIF1TX_WL[5:0]
0x18
7:0
0x18
R1288 (0x0508)
AIF1_Frame_Ctrl_
2
13:8 AIF1RX_WL[5:0]
0x18
7:0
AIF1RX_SLOT_
LEN[7:0]
0x18
R1289 (0x0509)
to
R1294 (0x050E)
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
AIF1TX1_SLOT[5:0]
AIF1TX2_SLOT[5:0]
AIF1TX3_SLOT[5:0]
AIF1TX4_SLOT[5:0]
AIF1TX5_SLOT[5:0]
AIF1TX6_SLOT[5:0]
AIF1RX1_SLOT[5:0]
AIF1RX2_SLOT[5:0]
AIF1RX3_SLOT[5:0]
AIF1RX4_SLOT[5:0]
AIF1RX5_SLOT[5:0]
AIF1RX6_SLOT[5:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
0x2
0x3
0x4
0x5
R1297 (0x0511)
to
R1302 (0x0516)
DS1137PP1
Label
AIF1_FMT[2:0]
AIF1TX_SLOT_
LEN[7:0]
Default
000
Description
AIF1 Audio Interface Format
000 = DSP Mode A
001 = DSP Mode B
010 = I2S mode
011 = Left-Justified mode
Other codes are reserved.
AIF1 TX Word Length (Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
AIF1 TX Slot Length (Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
AIF1 RX Word Length (Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
AIF1 RX Slot Length (Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
AIF1 TX Channel n Slot position
Defines the TX time slot position of the Channel n audio sample
Integer (LSB=1); Valid from 0 to 63
AIF1 RX Channel n Slot position
Defines the RX time slot position of the Channel n audio sample
Integer (LSB=1); Valid from 0 to 63
117
CS47L15
4.7 Digital Audio Interface Control
The AIF2 data control fields are described in Table 4-48.
Table 4-48. AIF2 Digital Audio Data Control
Register Address Bit
Label
R1348 (0x0544)
2:0 AIF2_FMT[2:0]
AIF2_Format
R1351 (0x0547)
13:8 AIF2TX_WL[5:0]
AIF2_Frame_Ctrl_
1
7:0 AIF2TX_SLOT_
LEN[7:0]
R1352 (0x0548)
13:8 AIF2RX_WL[5:0]
AIF2_Frame_Ctrl_
2
7:0 AIF2RX_SLOT_
LEN[7:0]
R1353 (0x0549)
to
R1356 (0x054C)
R1361 (0x0551)
to
R1364 (0x0554)
5:0 AIF2TX1_
SLOT[5:0]
5:0 AIF2TX2_
SLOT[5:0]
5:0 AIF2TX3_
SLOT[5:0]
5:0 AIF2TX4_
SLOT[5:0]
5:0 AIF2RX1_
SLOT[5:0]
5:0 AIF2RX2_
SLOT[5:0]
5:0 AIF2RX3_
SLOT[5:0]
5:0 AIF2RX4_
SLOT[5:0]
Default
Description
000 AIF2 Audio Interface Format
000 = DSP Mode A
001 = DSP Mode B
010 = I2S mode
011 = Left-Justified mode
Other codes are reserved.
0x18 AIF2 TX Word Length
(Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
0x18 AIF2 TX Slot Length
(Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
0x18 AIF2 RX Word Length
(Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
0x18 AIF2 RX Slot Length
(Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
0x0 AIF2 TX Channel n Slot position
Defines the TX time slot position of the Channel n audio sample
0x1 Integer (LSB=1); Valid from 0 to 63
0x2
0x3
0x0
0x1
AIF2 RX Channel n Slot position
Defines the RX time slot position of the Channel n audio sample
Integer (LSB=1); Valid from 0 to 63
0x2
0x3
The AIF3 data control fields are described in Table 4-49.
Table 4-49. AIF3 Digital Audio Data Control
Register Address Bit
Label
R1412 (0x0584)
2:0 AIF3_FMT[2:0]
AIF3_Format
R1415 (0x0587)
13:8 AIF3TX_WL[5:0]
AIF3_Frame_Ctrl_
1
7:0 AIF3TX_SLOT_
LEN[7:0]
13:8 AIF3RX_WL[5:0]
R1416 (0x0588)
AIF3_Frame_Ctrl_
2
7:0 AIF3RX_SLOT_
LEN[7:0]
118
Default
Description
000 AIF3 Audio Interface Format
000 = DSP Mode A
001 = DSP Mode B
010 = I2S mode
011 = Left-Justified mode
Other codes are reserved.
0x18 AIF3 TX Word Length (Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
0x18 AIF3 TX Slot Length (Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
0x18 AIF3 RX Word Length (Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
0x18 AIF3 RX Slot Length (Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
DS1137PP1
CS47L15
4.7 Digital Audio Interface Control
Table 4-49. AIF3 Digital Audio Data Control (Cont.)
Register Address Bit
Label
R1417 (0x0589)
5:0 AIF3TX1_
SLOT[5:0]
AIF3_Frame_Ctrl_
3
R1418 (0x058A)
5:0 AIF3TX2_
SLOT[5:0]
AIF3_Frame_Ctrl_
4
5:0 AIF3RX1_
R1425 (0x0591)
SLOT[5:0]
AIF3_Frame_Ctrl_
11
R1426 (0x0592)
5:0 AIF3RX2_
SLOT[5:0]
AIF3_Frame_Ctrl_
12
4.7.7
Default
Description
0x0 AIF3 TX Channel 1 Slot position
Defines the TX time slot position of the Channel 1 audio sample
Integer (LSB=1); Valid from 0 to 63
0x1 AIF3 TX Channel 2 Slot position
Defines the TX time slot position of the Channel 2 audio sample
Integer (LSB=1); Valid from 0 to 63
0x0 AIF3 RX Channel 1 Slot position
Defines the RX time slot position of the Channel 1 audio sample
Integer (LSB=1); Valid from 0 to 63
0x1 AIF3 RX Channel 2 Slot position
Defines the RX time slot position of the Channel 2 audio sample
Integer (LSB=1); Valid from 0 to 63
AIF TDM and Tristate Control
The AIFn output pins are tristated when the AIFn_TRI bit is set. Note that this function only affects output pins configured
for the respective AIFn function—a GPIO pin that is configured for a different function is not affected by AIFn_TRI. See
Section 4.11 to configure the GPIO pins.
Under default conditions, the AIFnTXDAT output is held at Logic 0 when the CS47L15 is not transmitting data (i.e., during
time slots that are not enabled for output by the CS47L15). If the AIFnTX_DAT_TRI bit is set, the CS47L15 tristates the
respective AIFnTXDAT pin when not transmitting data, allowing other devices to drive the AIFnTXDAT connection.
The AIF1 TDM and tristate control fields are described in Table 4-50.
Table 4-50. AIF1 TDM and Tristate Control
Register Address
R1281 (0x0501)
AIF1_Tx_Pin_Ctrl
R1283 (0x0503)
AIF1_Rate_Ctrl
Bit
5
6
Label
Default
Description
AIF1TX_DAT_TRI
0
AIF1TXDAT Tristate Control
0 = Logic 0 during unused time slots
1 = Tristated during unused time slots
AIF1_TRI
0
AIF1 Audio Interface Tristate Control
0 = Normal
1 = AIF1 Outputs are tristated
Note that this bit only affects output pins configured for the respective AIF1 function.
The AIF2 TDM and tristate control fields are described in Table 4-51.
Table 4-51. AIF2 TDM and Tristate Control
Register Address
R1345 (0x0541)
AIF2_Tx_Pin_Ctrl
R1347 (0x0543)
AIF2_Rate_Ctrl
DS1137PP1
Bit
5
6
Label
Default
Description
AIF2TX_DAT_TRI
0
AIF2TXDAT Tristate Control
0 = Logic 0 during unused time slots
1 = Tristated during unused time slots
AIF2_TRI
0
AIF2 Audio Interface Tristate Control
0 = Normal
1 = AIF2 Outputs are tristated
Note that this bit only affects output pins configured for the respective AIF2 function.
119
CS47L15
4.8 Output Signal Path
The AIF3 TDM and tristate control fields are described in Table 4-52.
Table 4-52. AIF3 TDM and Tristate Control
Register Address
R1409 (0x0581)
AIF3_Tx_Pin_Ctrl
R1411 (0x0583)
AIF3_Rate_Ctrl
Bit
5
6
Label
Default
Description
AIF3TX_DAT_TRI
0
AIF3TXDAT Tristate Control
0 = Logic 0 during unused time slots
1 = Tristated during unused time slots
AIF3_TRI
0
AIF3 Audio Interface Tristate Control
0 = Normal
1 = AIF3 Outputs are tristated
Note that this bit only affects output pins configured for the respective AIF3 function.
4.8 Output Signal Path
The CS47L15 provides three audio output signal paths. These outputs comprise ground-referenced headphone/earpiece
drivers, differential speaker driver, and a digital output interface suitable for external speaker drivers. The output signal
paths are summarized in Table 4-53.
Table 4-53. Output Signal Path Summary
Signal Path
OUT1L, OUT1R
OUT4L
OUT5L, OUT5R
Descriptions
Ground-referenced headphone/earpiece output
Differential speaker output
Digital speaker (PDM) output
Output Pins
HPOUTL, HPOUTR or EPOUTP, EPOUTN
SPKOUTN, SPKOUTP
SPKTXDAT, SPKCLK
The analog output paths incorporate high performance 24-bit sigma-delta DACs.
The headphone/earpiece output path is configurable as a stereo headphone driver (HPOUTL and HPOUTR pins), or as
a differential earpiece driver (EPOUTP and EPOUTN pins). The ground-referenced headphone output path incorporates
a common mode feedback path for rejection of system-related noise. The headphone and earpiece outputs each support
direct connection to external loads, with no requirement for AC coupling capacitors.
The speaker output path is configured to drive a differential (BTL) output. The Class D design offers high efficiency at large
signal levels. With a suitable choice of external speaker, the Class D output can drive a loudspeaker directly, without any
additional filter components.
The digital output path provides a stereo pulse-density modulation (PDM) output interface, for connection to external audio
devices. The PDM interface supports two digital output channels. The CS47L15 also supports a two-channel digital input
path that is synchronized to the PDM interface; the two-way interface can be used to support digital feedback from a PDM
speaker driver, enabling advanced speaker protection algorithms to be implemented.
Digital volume control is available on all outputs (analog and digital), with programmable ramp control for smooth,
glitch-free operation. A configurable noise-gate function is available on each of the output signal paths. Any two of the
output signal paths may be selected as input to the AEC loop-back paths.
The CS47L15 incorporates thermal protection functions, and provides short-circuit detection on the Class D speaker and
headphone/earpiece output paths. The general-purpose timers (see Section 4.5.2) can also be used as a watchdog
function, to trigger a shutdown of the Class D speaker drivers; see Section 4.18.
The Class D speaker output is designed to support monitoring of external loudspeakers, giving real-time feedback for
algorithms such as Cirrus Logic’s speaker-protection software, running on the DSP core. This enables loudspeakers to be
protected against damage from excessive signal levels and other electro-mechanical constraints. This feature requires
additional external component connections, as described in Section 4.8.8.
The CS47L15 output signal paths are shown in Fig. 4-48.
The OUT2, OUT3, and OUT4R paths are not implemented on this device.
120
DS1137PP1
CS47L15
4.8 Output Signal Path
Digital Core
OUT1L output
HPOUTL
DAC
HP1L_ENA
OUT1L_ VOL [6 :0]
OUT1_MONO
HPOUTR
DAC
OUT1R output
HPOUTFB1
HPOUTFB2
EP _SEL
HP1R_ENA
OUT1R_VOL [6:0]
EPOUTP
HP1L_ENA
EPOUTN
HP1R_ENA
OUT4L output
SPKOUTP
SPKOUTN
DAC
OUT4L_ VOL [6 :0]
SPKOUTL_ENA
OUT5L output
OUT5L_ VOL [6 :0]
OUT5_OSR
0 = Normal mode
1 = High Performance
SPK 1L_MUTE
PDM Output
Driver
SPKCLK
SPKTXDAT
SPK 1_FMT
OUT5L_ENA
OUT5R_ENA
OUT5R output
OUT5R_VOL [6:0]
SPK 1R_ MUTE
Mute Sequence
SPK 1_MUTE_ENDIAN
SPK 1_MUTE_SEQ
AEC
Loopback
inputs
AEC1_LOOPBACK _ENA
AEC1_LOOPBACK _SRC [1:0]
PDM connection to
IN2 digital input path
SPKRXDAT
AEC2_LOOPBACK _ENA
AEC2_LOOPBACK _SRC [1:0]
Figure 4-48. Output Signal Paths
DS1137PP1
121
CS47L15
4.8 Output Signal Path
4.8.1
Output Signal Path Enable
The output signal paths are enabled using the bits described in Table 4-54. The respective bits must be enabled for analog
or digital output on the respective output paths.
The OUT1 path is associated with the headphone and the earpiece output drivers. The HP1L_ENA and HP1R_ENA bits
control either the HPOUT or EPOUT drivers, depending on the EP_SEL register bit selection. See Table 4-56 for details
of the EP_SEL register.
The output signal paths are muted by default. It is recommended that deselecting the mute should be the final step of the
path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control sequence.
The output signal path mute functions are controlled using the bits described in Table 4-54.
The supply rails for the OUT1 outputs (HPOUT and EPOUT) are generated using an integrated dual-mode charge pump.
The charge pump is enabled automatically by the CS47L15 when required by the output drivers; see Section 4.16.
The CS47L15 schedules a pop-suppressed control sequence to enable or disable the OUT1 and OUT4L signal paths.
This is automatically managed by the control-write sequencer in response to setting the respective HPnx_ENA or
SPKOUTL_ENA bits; see Section 4.15 for further details.
The output signal path enable/disable control sequences are inputs to the interrupt circuit and can be used to trigger an
interrupt event when a sequence completes; see Section 4.12.
The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. See Section 4.13 for
details of the system clocks.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output
signal paths and associated DACs. If the frequency is too low, an attempt to enable an output signal path fails. Note that
active signal paths are not affected under such circumstances.
The status bits in Register R1025 and R1030 indicate the status of each of the output signal paths. If an underclocked
error condition occurs, these bits indicate which signal paths have been enabled.
Table 4-54. Output Signal Path Enable
Register Address
R1024 (0x0400)
Output_Enables_1
Bit
Label
9 OUT5L_ENA
8 OUT5R_ENA
7 SPKOUTL_ENA
1 HP1L_ENA
0 HP1R_ENA
122
Default
Description
0
Output Path 5 (left) enable
0 = Disabled
1 = Enabled
0
Output Path 5 (right) enable
0 = Disabled
1 = Enabled
0
Output Path 4 (left) enable
0 = Disabled
1 = Enabled
0
Output Path 1 (left) enable
When EP_SEL = 0, this bit controls the HPOUTL output driver.
When EP_SEL = 1, this bit controls the EPOUTP output driver.
0 = Disabled
1 = Enabled
0
Output Path 1 (right) enable
When EP_SEL = 0, this bit controls the HPOUTR output driver.
When EP_SEL = 1, this bit controls the EPOUTN output driver.
0 = Disabled
1 = Enabled
DS1137PP1
CS47L15
4.8 Output Signal Path
Table 4-54. Output Signal Path Enable (Cont.)
Register Address
R1025 (0x0401)
Output_Status_1
Bit
Label
Default
Description
9 OUT5L_ENA_STS
0
Output Path 5 (left) enable status
0 = Disabled
1 = Enabled
8 OUT5R_ENA_STS
0
Output Path 5 (right) enable status
0 = Disabled
1 = Enabled
7 OUT4L_ENA_STS
0
Output Path 4 (left) enable status
0 = Disabled
1 = Enabled
R1030 (0x0406)
1 OUT1L_ENA_STS
0
Output Path 1 (left) enable status
Raw_Output_Status_1
0 = Disabled
1 = Enabled
0 OUT1R_ENA_STS
0
Output Path 1 (right) enable status
0 = Disabled
1 = Enabled
4.8.2
Output Signal Path Sample-Rate Control
The output signal paths are derived from the respective output mixers within the CS47L15 digital core. The sample rate
for the output signal paths is configured using OUT_RATE—see Table 4-24.
Note that sample-rate conversion is required when routing the output signal paths to any signal chain that is configured
for a different sample rate.
4.8.3
Output Signal Path Control
The OUT1 path is associated with the headphone and the earpiece output drivers. The EP_SEL bit controls which of these
outputs can be used—it is not possible to enable the headphone and earpiece drivers simultaneously.
Under default register conditions, the OUT1 path is configured for stereo output. The path can be configured for mono
differential (BTL) output using the OUT1_MONO bit; this is ideal for driving an earpiece or hearing aid coil.
When the OUT1_MONO bit is set, the respective right channel output is an inverted copy of the left channel output signal;
this creates a differential output between the respective outputs. The left and right channel output drivers must both be
enabled in Mono Mode; both channels should be enabled simultaneously using the fields described in Table 4-54.
The mono (BTL) signal paths are shown in Fig. 4-48. Note that, in Mono Mode, the effective gain of the signal path is
increased by 6 dB.
For stereo output on HPOUTL and HPOUTR, the required settings are as follows:
•
EP_SEL = 0
•
OUT1_MONO = 0
For mono differential output on EPOUTP and EPOUTN, the required settings are as follows:
•
EP_SEL = 1
•
OUT1_MONO = 1
Note that the EP_SEL and OUT1_MONO bits should not be changed while the headphone or earpiece drivers are
enabled. These bits should be configured before enabling the respective drivers, and should remain unchanged until after
the drivers have been disabled. The HPOUT and EPOUT drivers are enabled using the HP1L_ENA and HP1R_ENA bits,
as described in Table 4-54.
The SPKCLK frequency of the PDM output path (OUT5) is controlled by OUT5_OSR, as described in Table 4-55. When
the OUT5_OSR bit is set, the audio performance is improved, but power consumption is also increased.
DS1137PP1
123
CS47L15
4.8 Output Signal Path
Note that the SPKCLK frequencies noted in Table 4-55 assume that the SYSCLK frequency is a multiple of 6.144 MHz
(SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the SPKCLK frequency
is scaled accordingly.
Table 4-55. SPKCLK Frequency
OUT5_OSR
0
1
Description
Normal mode
High Performance mode
SPKCLK Frequency
3.072 MHz
6.144 MHz
The output signal path control registers are defined in Table 4-56.
Table 4-56. Output Signal Path Control
Register Address Bit
Label
R1024 (0x0400)
15 EP_SEL
Output_Enables_1
R1040 (0x0410)
Output_Path_
Config_1L
R1072 (0x0430)
Output_Path_
Config_5L
4.8.4
Default
Description
0
Output Path 1 Output Driver select
0 = HPOUTL and HPOUTR
1 = EPOUTP and EPOUTN
12 OUT1_MONO
0
Output Path 1 Mono Mode (Configures HPOUT and EPOUT as a mono differential output.)
0 = Disabled
1 = Enabled
The gain of the signal path is increased by 6 dB in differential (mono) mode.
13 OUT5_OSR
0
Output Path 5 Oversample Rate
0 = Normal mode
1 = High Performance mode
Output Signal Path Digital Volume Control
A digital volume control is provided on each of the output signal paths, providing –64 to +31.5 dB gain control in 0.5-dB
steps. An independent mute control is also provided for each output signal path.
Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a
programmable rate. For increasing gain (or unmute), the rate is controlled by OUT_VI_RAMP. For decreasing gain (or
mute), the rate is controlled by OUT_VD_RAMP.
Note:
The OUT_VI_RAMP and OUT_VD_RAMP fields should not be changed while a volume ramp is in progress.
The OUT_VU bits control the loading of the output signal path digital volume and mute controls. When OUT_VU is cleared,
the digital volume and mute settings are loaded into the respective control register, but do not change the signal path gain.
The digital volume and mute settings on all of the output signal paths are updated when a 1 is written to OUT_VU. This
makes it possible to update the gain of multiple signal paths simultaneously.
Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in
0.125-dB steps. This allows a very high degree of gain control—smooth volume ramping under all operating conditions.
Note:
The 0 dBFS level of the OUT5 digital output path is not equal to the 0 dBFS level of the CS47L15 digital core. The
maximum digital output level is –6 dBFS (see Table 3-8). Under 0 dB gain conditions, a 0 dBFS output from the
digital core corresponds to a –6 dBFS level in the PDM output.
The digital volume control registers are described in Table 4-57 and Table 4-58.
124
DS1137PP1
CS47L15
4.8 Output Signal Path
Table 4-57. Output Signal Path Digital Volume Control
Register Address
R1033 (0x0409)
Output_Volume_
Ramp
R1041 (0x0411)
DAC_Digital_
Volume_1L
Bit
6:4
Label
OUT_VD_
RAMP[2:0]
2:0
OUT_VI_
RAMP[2:0]
9
OUT_VU
8
OUT1L_MUTE
7:0
R1045 (0x0415)
DAC_Digital_
Volume_1R
9
OUT_VU
8
OUT1R_MUTE
7:0
R1065 (0x0429)
DAC_Digital_
Volume_4L
OUT_VU
8
OUT4L_MUTE
OUT4L_VOL[7:0]
9
OUT_VU
8
OUT5L_MUTE
7:0
DS1137PP1
OUT1R_VOL[7:0]
9
7:0
R1073 (0x0431)
DAC_Digital_
Volume_5L
OUT1L_VOL[7:0]
OUT5L_VOL[7:0]
Default
010
010
See
Footnote 1
1
0x80
See
Footnote 1
1
0x80
See
Footnote 1
1
0x80
See
Footnote 1
1
0x80
Description
Output Volume Decreasing Ramp Rate (seconds/6 dB)
This field should not be changed while a volume ramp is in progress.
000 = 0 ms
011 = 2 ms
110 = 15 ms
001 = 0.5 ms
100 = 4 ms
111 = 30 ms
010 = 1 ms
101 = 8 ms
Output Volume Increasing Ramp Rate (seconds/6 dB)
This field should not be changed while a volume ramp is in progress.
000 = 0 ms
011 = 2 ms
110 = 15 ms
001 = 0.5 ms
100 = 4 ms
111 = 30 ms
010 = 1 ms
101 = 8 ms
Output Signal Paths Volume Update. Writing 1 to this bit causes the Output Signal
Paths Volume and Mute settings to be updated simultaneously
Output Path 1 (Left) Digital Mute
0 = Unmute
1 = Mute
Output Path 1 (Left) Digital Volume (see Table 4-58 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
… (0.5-dB steps)
0x01 = –63.5dB
0xBF = +31.5 dB
… (0.5-dB steps)
Output Signal Paths Volume Update. Writing 1 to this bit causes the Output Signal
Paths Volume and Mute settings to be updated simultaneously
Output Path 1 (Right) Digital Mute
0 = Unmute
1 = Mute
Output Path 1 (Right) Digital Volume (see Table 4-58 for volume register
definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
Output Signal Paths Volume Update. Writing 1 to this bit causes the Output Signal
Paths Volume and Mute settings to be updated simultaneously
Output Path 4 (Left) Digital Mute
0 = Unmute
1 = Mute
Output Path 4 (Left) Digital Volume (see Table 4-58 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
Output Signal Paths Volume Update. Writing 1 to this bit causes the Output Signal
Paths Volume and Mute settings to be updated simultaneously
Output Path 5 (Left) Digital Mute
0 = Unmute
1 = Mute
Output Path 5 (Left) Digital Volume (see Table 4-58 for volume register definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x00 = –64dB
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
125
CS47L15
4.8 Output Signal Path
Table 4-57. Output Signal Path Digital Volume Control (Cont.)
Register Address
R1077 (0x0435)
DAC_Digital_
Volume_5R
Bit
9
Label
OUT_VU
Default
Description
See
Output Signal Paths Volume Update. Writing 1 to this bit causes the Output Signal
Footnote 1 Paths Volume and Mute settings to be updated simultaneously
8
OUT5R_MUTE
1
Output Path 5 (Right) Digital Mute
0 = Unmute
1 = Mute
7:0 OUT5R_VOL[7:0]
0x80
Output Path 5 (Right) Digital Volume (see Table 4-58 for volume register
definition).
–64 dB to +31.5 dB in 0.5-dB steps
0x80 = 0 dB
0xC0 to 0xFF = Reserved
0x00 = –64dB
0x01 = –63.5dB
… (0.5-dB steps)
… (0.5-dB steps)
0xBF = +31.5 dB
1. Default is not applicable to these write-only bits
Table 4-58 lists the output signal path digital volume settings.
Table 4-58. Output Signal Path Digital Volume Range
Output Volume
Register
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
126
Volume (dB)
–64.0
–63.5
–63.0
–62.5
–62.0
–61.5
–61.0
–60.5
–60.0
–59.5
–59.0
–58.5
–58.0
–57.5
–57.0
–56.5
–56.0
–55.5
–55.0
–54.5
–54.0
–53.5
–53.0
–52.5
–52.0
–51.5
–51.0
–50.5
–50.0
–49.5
–49.0
–48.5
–48.0
–47.5
–47.0
–46.5
Output Volume
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
Volume (dB)
–39.5
–39.0
–38.5
–38.0
–37.5
–37.0
–36.5
–36.0
–35.5
–35.0
–34.5
–34.0
–33.5
–33.0
–32.5
–32.0
–31.5
–31.0
–30.5
–30.0
–29.5
–29.0
–28.5
–28.0
–27.5
–27.0
–26.5
–26.0
–25.5
–25.0
–24.5
–24.0
–23.5
–23.0
–22.5
–22.0
Output Volume
Register
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
Volume (dB)
–15.0
–14.5
–14.0
–13.5
–13.0
–12.5
–12.0
–11.5
–11.0
–10.5
–10.0
–9.5
–9.0
–8.5
–8.0
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
Output Volume
Register
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
Volume (dB)
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
DS1137PP1
CS47L15
4.8 Output Signal Path
Table 4-58. Output Signal Path Digital Volume Range (Cont.)
Output Volume
Register
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
4.8.5
Volume (dB)
–46.0
–45.5
–45.0
–44.5
–44.0
–43.5
–43.0
–42.5
–42.0
–41.5
–41.0
–40.5
–40.0
Output Volume
Register
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
Volume (dB)
–21.5
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–17.5
–17.0
–16.5
–16.0
–15.5
Output Volume
Register
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
Volume (dB)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
Output Volume
Register
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0–0xFF
Volume (dB)
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
Reserved
Output Signal Path Noise-Gate Control
The CS47L15 provides a digital noise-gate function for each of the output signal paths. The noise gate ensures best noise
performance when the signal path is idle. When the noise gate is enabled, and the applicable signal level is below the
noise-gate threshold, the noise gate is activated, causing the signal path to be muted.
The noise-gate function is enabled by setting NGATE_ENA, as described in Table 4-59.
For each output path, the noise gate may be associated with one or more of the signal path threshold detection functions
using the x_NGATE_SRC fields. When more than one signal threshold is selected, the output-path noise gate is only
activated (i.e., muted) when all of the respective signal thresholds are satisfied.
For example, if the OUT1L noise gate is associated with the OUT1L and OUT1R signal paths, the OUT1L signal path is
only muted if both the OUT1L and OUT1R signal levels are below the respective thresholds.
The noise-gate threshold (the signal level below which the noise gate is activated) is set using NGATE_THR. Note that,
for each output path, the noise-gate threshold represents the signal level at the respective output pins; the threshold is
therefore independent of the digital volume and PGA gain settings.
Note that, although there is only one noise-gate threshold level (NGATE_THR), each of the output-path noise gates may
be activated independently, according to the respective signal content and the associated threshold configurations.
To prevent erroneous triggering, a time delay is applied before the gate is activated; the noise gate is only activated (i.e.,
muted) when the output levels are below the applicable signal level thresholds for longer than the noise-gate hold time.
The hold time is set using the NGATE_HOLD field.
When the noise gate is activated, the CS47L15 gradually attenuates the respective signal path at the rate set by OUT_
VD_RAMP (see Table 4-57). When the noise gate is deactivated, the output volume increases at the rate set by OUT_VI_
RAMP.
DS1137PP1
127
CS47L15
4.8 Output Signal Path
Table 4-59. Output Signal Path Noise-Gate Control
Register Address
R1043 (0x0413)
Noise_Gate_Select_1L
Bit
Label
11:0 OUT1L_NGATE_
SRC[11:0]
R1047 (0x0417)
Noise_Gate_Select_1R
R1067 (0x042B)
Noise_Gate_Select_4L
R1075 (0x0433)
Noise_Gate_Select_5L
R1079 (0x0437)
Noise_Gate_Select_5R
R1112 (0x0458)
Noise_Gate_Control
11:0 OUT1R_NGATE_
SRC[11:0]
11:0 OUT4L_NGATE_
SRC[11:0]
11:0 OUT5L_NGATE_
SRC[11:0]
11:0 OUT5R_NGATE_
SRC[11:0]
0x200
5:4 NGATE_
HOLD[1:0]
00
3:1 NGATE_THR[2:0]
000
0
4.8.6
Default
Description
0x001 Output Signal Path Noise-Gate Source. Enables one of more signal paths as
inputs to the respective noise gate. If more than one signal path is enabled as
an input, the noise gate is only activated (i.e., muted) when all of the respective
signal thresholds are satisfied.
Each bit is coded as 0 = Disabled, 1 = Enabled
0x002 [11] = Reserved
[7] = Reserved
[3] = Reserved
[10] = Reserved
[6] = OUT4L
[2] = Reserved
0x040 [9] = OUT5R
[5] = Reserved
[1] = OUT1R
[8] = OUT5L
[4] = Reserved
[0] = OUT1L
0x100
NGATE_ENA
0
Output Signal Path Noise-Gate Hold Time (delay before noise gate is activated)
00 = 30 ms
10 = 250 ms
01 = 120 ms
11 = 500 ms
Output Signal Path Noise-Gate Threshold
000 = –78 dB
011 = –96 dB
110 = –114 dB
001 = –84 dB
100 = –102 dB
111 = –120 dB
010 = –90 dB
101 = –108 dB
Output Signal Path Noise-Gate Enable
0 = Disabled
1 = Enabled
Output Signal Path AEC Loop-Back
The CS47L15 incorporates two loop-back signal paths, which are ideally suited as a reference for AEC processing. Any
two of the output signal paths may be selected as the AEC loop-back sources.
When configured with suitable DSP firmware, the CS47L15 can provide an integrated AEC capability. The AEC loop-back
feature also enables convenient hook-up to an external device for implementing the required signal-processing algorithms.
The AEC loop-back source is connected after the respective digital volume controls, as shown in Fig. 4-48. The AEC
loop-back signals can be selected as input to any of the digital mixers within the CS47L15 digital core. The sample rate
for the AEC loop-back paths is configured using OUT_RATE—see Table 4-24.
The AEC loop-back function is enabled using the AECn_LOOPBACK_ENA bits (where n identifies the applicable path,
AEC1 or AEC2). The source signals for the Transmit Path AEC function are selected using the AECn_LOOPBACK_SRC
bits.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the AEC
loop-back function. If the frequency is too low, an attempt to enable this function fails. Note that active signal paths are not
affected under such circumstances.
The AECn_ENA_STS bits indicate the status of the AEC loop-back functions. If an underclocked error condition occurs,
these bits indicate whether the AEC loop-back function has been enabled.
128
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4.8 Output Signal Path
Table 4-60. Output Signal Path AEC Loop-Back Control
Register Address
R1104 (0x0450)
DAC_AEC_
Control_1
R1105 (0x0451)
DAC_AEC_
Control_2
4.8.7
Bit
5:2
Label
AEC1_LOOPBACK_
SRC[3:0]
Default
0000
1
AEC1_ENA_STS
0
0
AEC1_LOOPBACK_
ENA
0
5:2
AEC2_LOOPBACK_
SRC[3:0]
0000
1
AEC2_ENA_STS
0
0
AEC2_LOOPBACK_
ENA
0
Description
Input source for Tx AEC1 function
0000 = OUT1L
0110 = OUT4L
1001 = OUT5R
0001 = OUT1R
1000 = OUT5L
All other codes are reserved
Transmit (Tx) Path AEC1 Control Status
0 = Disabled
1 = Enabled
Transmit (Tx) Path AEC1 Control
0 = Disabled
1 = Enabled
Input source for Tx AEC2 function
0000 = OUT1L
0110 = OUT4L
1001 = OUT5R
0001 = OUT1R
1000 = OUT5L
All other codes are reserved
Transmit (Tx) Path AEC2 Control Status
0 = Disabled
1 = Enabled
Transmit (Tx) Path AEC2 Control
0 = Disabled
1 = Enabled
Headphone and Earpiece Outputs
The headphone/earpiece driver outputs, HPOUTL, HPOUTR, EPOUTP, and EPOUTN, are suitable for direct connection
to external headphones and earpieces. The outputs are ground referenced, eliminating any requirement for AC coupling
capacitors.
The headphone output (HPOUTL, HPOUTR) incorporates a common-mode, or ground-loop, feedback path that provides
rejection of system-related ground noise. The feedback pin must be connected to ground for normal operation of the
headphone output.
The ground feedback path for HPOUTL and HPOUTR is selected using HP1_GND_SEL—see Table 4-61. Note that the
selected pin should be connected to GND as close as possible to the respective headphone jack ground pin, as shown in
Fig. 4-49.
Table 4-61. Headphone Output (HPOUT) Ground Feedback Control
Register Address
R1042 (0x0412)
Output_Path_
Config_1
Bit
2:0
Label
HP1_GND_
SEL[2:0]
Default
000
Description
HPOUT ground feedback pin select
000 = HPOUTFB1
001 = HPOUTFB2
All other codes are reserved
The earpiece output (EPOUTP, EPOUTN) does not support common-mode feedback. The HP1_GND_SEL bit has no
effect if the earpiece output is selected (EP_SEL = 1).
The headphone and earpiece connections are shown in Fig. 4-49.
DS1137PP1
129
CS47L15
4.8 Output Signal Path
CS47L15
HPOUTL
HPOUTR
HPOUTFB1
HPOUTFB2
Ground feedback for HPOUT is supported on the
HPOUTFB1 and HPOUTFB2 pins. The applicable
feedback pin is configured using HP1_GND_SEL.
EPOUTP
EPOUTN
Earpiece
Figure 4-49. Headphone and Earpiece Connection
4.8.8
Speaker Outputs (Analog)
The speaker driver outputs SPKOUTP and SPKOUTN provide differential (BTL) outputs suitable for direct connection to
an external loudspeaker. The integrated Class D speaker driver provides high efficiency at large signal levels.
The speaker driver signal path incorporates a boost function that shifts the signal levels between the AVDD and SPKVDD
voltage domains. The boost is preconfigured (+12 dB) for the recommended AVDD and SPKVDD operating voltages (see
Table 3-3).
Ultralow leakage and high PSRR allow the speaker supply SPKVDD to be connected directly to a lithium battery.
Note that SYSCLK must be present and enabled when using the Class D speaker output; see Section 4.13 for details of
SYSCLK and the associated control fields.
The OUT4L output signal path is associated with the analog outputs SPKOUTP and SPKOUTN.
The Class D speaker output is a pulse-width modulated signal, and requires external filtering in order to recreate the audio
signal. With a suitable choice of external speakers, the speakers themselves can provide the necessary filtering. See
Section 5 for further information on Class D speaker connections.
The external speaker connection is shown in Fig. 4-50, assuming a suitable speaker is chosen to provide the PWM
filtering.
CS47L15
SPKOUTP
SPKOUTN
Figure 4-50. Speaker Connection
The speaker output path is designed to support monitoring of external loudspeakers, giving real-time feedback for
algorithms such as Cirrus Logic’s speaker-protection software. Specific external connections are necessary when using
this feature, as detailed below.
130
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4.8 Output Signal Path
The speaker-protection software, implemented on the integrated DSP core, enables loudspeakers to be protected from
excessive signal levels and other electro-mechanical constraints. The monitoring circuit enables the operational limits to
be continually optimized for the particular loudspeaker and the prevailing conditions. Factors such as cone excursion,
resonance, and thermal behavior of the loudspeaker are modeled in the speaker-protection software. As a result, the
maximum audio output can be achieved, while ensuring the loudspeakers are also fully protected from damage.
Separate P/N ground connections are provided for the speaker driver; these pins relate to the positive/negative output
transistors respectively, to allow comprehensive current monitoring in the output path, as an input to the speaker protection
algorithm.
The external speaker connections, incorporating the output current monitoring requirements, are shown in Fig. 4-51. Note
that, if output current monitoring is not required, these connections should be tied directly to ground on the PCB.
CS47L15
SPKOUTP
SPKOUTN
IN2P
IN2N
SPKGNDP
SPKGNDN
0.1
(1%, 100ppm/°C)
Figure 4-51. Speaker Output Current Monitoring Connections (Speaker Protection)
Please contact your Cirrus Logic representative for further information on the Speaker Protection software.
4.8.9
Speaker Outputs (Digital PDM)
The CS47L15 supports a two-channel pulse-density modulation (PDM) digital speaker interface; the PDM outputs are
associated with the OUT5L and OUT5R output signal paths.
The external connections associated with the PDM outputs are implemented on multi-function GPIO pins, which must be
configured for the respective PDM functions when required. The PDM output connections are alternative functions
available on specific GPIO pins. See Section 4.11 to configure the GPIO pins for the PDM output.
The PDM digital speaker interface is a stereo interface; the OUT5L and OUT5R output signal paths are interleaved on the
SPKTXDAT output, and clocked using SPKCLK.
Note that the PDM interface supports two different operating modes; these are selected using SPK1_FMT. See Table 3-15
for detailed timing information in both modes.
•
If SPK1_FMT = 0 (Mode A), the left PDM channel is valid at the rising edge of SPKCLK; the right PDM channel is
valid at the falling edge of SPKCLK.
•
If SPK1_FMT = 1 (Mode B), the left PDM channel is valid during the low phase of SPKCLK; the right PDM channel
is valid during the high phase of SPKCLK.
The PDM interface timing is shown in Fig. 4-52.
DS1137PP1
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CS47L15
4.8 Output Signal Path
SPKCLK output (Mode A)
SPKCLK output (Mode B)
Left channel output
1
Right channel output
SPKTXDAT output
(left & right channels interleaved)
1
2
1
2
1
2
1
2
2
1
2
Figure 4-52. Digital Speaker (PDM) Interface Timing
Clocking for the PDM interface is derived from SYSCLK. Note that SYSCLK_ENA must also be set. See Section 4.13 for
further details of the system clocks and control registers.
If the OUT5L or OUT5R output signal path is enabled, the PDM interface clock signal is output on the SPKCLK pin.
The output signal paths support normal and high performance operating modes, as described in Section 4.8.3. The
SPKCLK frequency is set according to the operating mode of the relevant output path, as described in Table 4-55. The
OUT5_OSR bit is defined in Table 4-56.
The PDM output channels can be independently muted. When muted, the default output on each channel is a
DSD-compliant silent stream (0110_1001b). The mute output code can be programmed to other values if required, using
the SPK1_MUTE_SEQ field. The mute output code can be transmitted MSB-first or LSB-first; this is selectable using the
SPK1_MUTE_ENDIAN bit.
Note that the PDM Mute function is not a soft-mute; the audio output is interrupted immediately when the PDM mute is
asserted. It is recommended to use the output signal path mute function before applying the PDM mute. See Table 4-57
for details of the OUT5L_MUTE and OUT5R_MUTE bits.
The PDM output interface registers are described in Table 4-62.
Table 4-62. Digital Speaker (PDM) Output Control
Register Address Bit
Label
R1168 (0x0490)
13 SPK1R_MUTE
PDM_SPK1_
CTRL_1
12 SPK1L_MUTE
8 SPK1_MUTE_
ENDIAN
7:0 SPK1_MUTE_
SEQ[7:0]
R1169 (0x0491)
PDM_SPK1_
CTRL_2
0 SPK1_FMT
Default
Description
0
PDM Speaker Output 1 (Right) Mute
0 = Audio output (OUT5R)
1 = Mute Sequence output
0
PDM Speaker Output 1 (Left) Mute
0 = Audio output (OUT5L)
1 = Mute Sequence output
0
PDM Speaker Output 1 Mute Sequence Control
0 = Mute sequence is LSB first
1 = Mute sequence output is MSB first
0x69 PDM Speaker Output 1 Mute Sequence
Defines the 8-bit code that is output on muted SPKTXDAT channels.
0
PDM Speaker Output 1 timing format
0 = Mode A (PDM data is valid at the rising/falling edges of SPKCLK)
1 = Mode B (PDM data is valid during the high/low phase of SPKCLK)
The digital speaker (PDM) outputs SPKTXDAT and SPKCLK are intended for direct connection to a compatible external
speaker driver. A typical configuration is shown in Fig. 4-53.
132
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4.9 External Accessory Detection
CS47L15
SPKCLK
Speaker Driver
Right
Speaker Driver
Left
SPKTXDAT
Figure 4-53. Digital Speaker (PDM) Connection
The CS47L15 supports a two-channel digital input path that is synchronized to the PDM interface; this allows a
bidirectional audio interface to be supported, using SPKCLK as a shared clock. The PDM interface can be used in this
way to support digital feedback from an external speaker driver, enabling advanced speaker protection algorithms to be
implemented. See Section 4.2 to configure the SPKRXDAT digital input path.
Typical connections for an external speaker driver, incorporating the digital feedback path, are shown in Fig. 4-54.
CS47L15
SPKCLK
SPKTXDAT
Speaker Driver
SPKRXDAT
Figure 4-54. Digital Speaker (PDM) Connection with Feedback
4.9 External Accessory Detection
The CS47L15 provides external accessory detection functions that can sense the presence and impedance of external
components. This can be used to detect the insertion or removal of an external headphone or headset, and to provide an
indication of key/button push events.
Jack insertion is detected using the JACKDET1 and JACKDET2 pins, which must be connected to a switch contact within
the jack sockets. An interrupt event is generated whenever a jack insertion or jack removal event is detected.
Suppression of pops and clicks caused by jack insertion or removal is provided using the MICDET clamp function. This
function can also be used to trigger interrupt events, and to trigger the control-write sequencer. The integrated
general-purpose switch can be synchronized with the MICDET clamp, to provide additional pop-suppression capability.
Microphones, push buttons, and other accessories can be detected via the MICDET1 or MICDET2 pins. The presence of
a microphone, and the status of a hook switch can be detected. This feature can also be used to detect push-button
operation. (Note that accessory detection is also possible via the HPOUTx and JACKDETn pins, subject to some
additional constraints.)
DS1137PP1
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4.9 External Accessory Detection
Headphone impedance can be detected via the HPOUTL and HPOUTR pins; this can be used to set different gain levels
or other configuration settings according to the type of load connected. For example, different settings may be applicable
to headphone or line output loads. (Note that impedance measurement is also possible via the MICDETn and JACKDETn
pins, subject to some additional constraints.)
The internal 32-kHz clock must be present and enabled when using the microphone detect or headphone detect functions;
the 32-kHz clock is also required for the jack detect function, assuming input debounce is enabled. See Section 4.13 for
details of the internal 32-kHz clock and associated control fields.
4.9.1
Jack Detect
The CS47L15 provides support for jack insertion switch detection. The jack insertion status can be read using the relevant
register status bits. A jack insertion or removal can also be used to trigger an interrupt event.
The jack-detect interrupt (IRQ) functionality is maintained in Sleep Mode (see Section 4.10). This enables a jack insertion
event to be used to trigger a wake-up of the CS47L15.
Jack insertion and removal is detected using the JACKDET1 and JACKDET2 pins. The recommended external
connections are shown in Fig. 4-55. Note that the logic thresholds associated with the two JACKDET differ from each
other, as described in Table 3-11—this provides support for different jack switch configurations.
The jack detect feature is enabled using the JDn_ENA bits (where n = 1 or 2 for JACKDET1 or JACKDET2 respectively);
the jack insertion status can be read using JDn_STSx. Note that the JDn_STS1 and JDn_STS2 bits provide the same
information in respect of the applicable JACKDETn input.
The jack detect input debounce is selected using the JDn_DB bits, as described in Table 4-63. Note that, under normal
operating conditions, the debounce circuit uses the 32-kHz clock, which must be enabled whenever input debounce
functions are required. Input debounce is not provided in Sleep Mode; the JDn_DB bits have no effect in Sleep Mode.
Note that the jack detect signals, JD1 and JD2, can be used as inputs to the MICDET clamp function—this provides
additional functionality relating to jack insertion and removal events.
An interrupt request (IRQ) event is generated whenever a jack insertion or jack removal is detected (see Section 4.12).
Separate mask bits are provided, to allow IRQ events on the rising and/or falling edges of the JD1 or JD2 signals.
The control registers associated with the jack detect function are described in Table 4-63.
Table 4-63. Jack Detect Control
Register Address
R723 (0x02D3)
Jack_detect_
analog
R6278 (0x1886)
IRQ1_Raw_
Status_7
134
Bit
1
Label
JD2_ENA
Default
0
0
JD1_ENA
0
2
JD2_STS1
0
0
JD1_STS1
0
Description
JACKDET2 enable
0 = Disabled
1 = Enabled
JACKDET1 enable
0 = Disabled
1 = Enabled
JACKDET2 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET2 pin is pulled low on jack insertion.)
JACKDET1 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET1 pin is pulled low on jack insertion.)
DS1137PP1
CS47L15
4.9 External Accessory Detection
Table 4-63. Jack Detect Control (Cont.)
Register Address
R6534 (0x1986)
IRQ2_Raw_
Status_7
R6662 (0x1A06)
Interrupt_
Debounce_7
Bit
2
Label
JD2_STS2
Default
0
0
JD1_STS2
0
2
JD2_DB
0
0
JD1_DB
0
Description
JACKDET2 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET2 pin is pulled low on jack insertion.)
JACKDET1 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET1 pin is pulled low on jack insertion.)
JACKDET2 input debounce
0 = Disabled
1 = Enabled
JACKDET1 input debounce
0 = Disabled
1 = Enabled
A recommended connection circuit, including headphone output on HPOUT and microphone connections, is shown in
Fig. 4-55. See Section 5.1 for details of recommended external components.
CS47L15
2.2 k(±2%)
MICBIAS1x
* IN1BLP, IN1BRP
C
MICDET1
HPOUTL
HPOUTR
HPOUTFB2
(jack insertion switch )
JACKDETn
* Note that the IN1Bxx analog mic
channels are recommended with the
external accessory detect function
Note: The illustrated circuit
assumes the jack insertion
switch contacts are closed
when the jack is inserted.
Figure 4-55. Jack Detect and External Accessory Connections
The internal comparator circuit used to detect the JACKDETn status is shown in Fig. 4-56. The threshold voltages for the
jack detect circuit are noted in Table 3-11. Note that separate thresholds are defined for jack insertion and removal.
DS1137PP1
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4.9 External Accessory Detection
AVDD
Note: The illustrated circuit
assumes the jack insertion
switch contacts are closed
when jack is inserted.
1M
Jack Detect logic
+
-
reference
JACKDETn
(jack insertion switch)
Figure 4-56. Jack Detect Comparator
4.9.2
Jack Pop Suppression (MICDET Clamp and GP Switch)
Under typical configuration of a 3.5-mm headphone/accessory jack connection, there is a risk of pops and clicks arising
from jack insertion or removal. This can occur if the headphone load makes momentary contact with the MICBIAS output
when the jack is not fully inserted.
The CS47L15 provides a MICDET clamp function to suppress pops and clicks caused by jack insertion or removal. It can
be controlled directly, or can be activated by a configurable logic function derived from the JACKDETn inputs. The clamp
status can be read using the relevant register status bit. The clamp status can also be used to trigger an interrupt (IRQ)
event or to trigger the control-write sequencer.
A general-purpose analog switch is incorporated, which can be configured to augment the MICDET clamp functions and
to support the pop-suppression circuits, as described in Section 4.9.2.3.
4.9.2.1 MICDET Clamp Control
The MICDET clamp function can be configured using the MICD_CLAMP_MODE field. Selectable logic conditions (derived
from the JD1 and JD2 signals—see Table 4-63) provide support for different jack-detect circuit configurations. Setting the
MICD_CLAMP_OVD bit enables the MICDET clamp, regardless of other conditions.
Note:
The MICD_CLAMP_OVD bit is set by default. Accordingly, the MICDET clamp is always enabled following
power-on reset, hardware reset, or software reset.
The MICDET clamp functionality (including the external IRQ) is maintained in Sleep Mode (see Section 4.10). This enables
a jack insertion event to be used to trigger a wake-up of the CS47L15. The recommended control sequence for the jack
detect and MICDET clamp control is described in Section 4.9.2.5.
If the MICDET clamp is enabled, the MICDET1/HPOUTFB1 and MICDET2/HPOUTFB2 pins are shorted together. The
grounding of the MICDET pin is achieved via the applicable HPOUTFB pin—it is assumed that the HPOUTFB connection
is grounded externally, as shown in Fig. 4-57.
The selectable logic conditions supported by the MICD_CLAMP_MODE field provides flexibility in selecting the
appropriate conditions for controlling the MICDET clamp. The status of the clamp can be read using the MICD_CLAMP_
STSx bits. Note that the MICD_CLAMP_STS1 and MICD_CLAMP_STS2 bits provide the same information. The status of
the clamp in the overridden (MICD_CLAMP_OVD = 1) state is not indicated.
The MICDET clamp debounce is selected by setting MICD_CLAMP_DB, as described in Table 4-64. Note that, under
normal operating conditions, the debounce circuit uses the 32-kHz clock, which must be enabled whenever input
debounce functions are required. Input debounce is not provided in Sleep Mode; the MICD_CLAMP_DB bit has no effect
in Sleep Mode.
136
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4.9 External Accessory Detection
The MICDET clamp function is shown in Fig. 4-57. Note that the jack plug is shown partially removed, with the MICDET1
pin in contact with the headphone load.
CS47L15
2.2 k(±2%)
MICBIAS1x
MICD_CLAMP_OVD
* IN1BLP, IN1BRP
MICD_CLAMP_MODE
MICD_CLAMP_STSx
MICD_CLAMP_DB
MICDET1/
HPOUTFB1
C
* Note: The Jack plug is shown
partially removed, with the MICDET1
pin in contact with the headphone load.
* see note
MICDET2/
HPOUTFB2
MICDET
Clamp Control
When the MICDET Clamp is active in the configuration
shown, the MICDET1 pin is grounded via the
headphone jack ground connection.
* Note that the IN1Bxx analog mic
channels are recommended with the
external accessory detect function
Figure 4-57. MICDET Clamp Circuit
4.9.2.2 Interrupts and Write-Sequencer Control
An interrupt request (IRQ) event can be generated in response to the MICDET clamp status. A MICDET clamp interrupt
is generated whenever the logic condition of the JDn signals cause a change in the clamp status. Separate maskable
interrupts are provided for the rising and falling edges of the MICDET clamp status—see Section 4.12.
The control-write sequencer can be triggered by the MICDET clamp status. This is enabled using the WSEQ_ENA_MICD_
CLAMP_FALL and WSEQ_ENA_MICD_CLAMP_RISE bits. Note that the control-sequencer events are only valid if the
clamp status changed in response to the JDn signals. See Section 4.15 for details of the control-write sequencer.
4.9.2.3 Pop Suppression using General-Purpose Switch
In applications where a large decoupling capacitance is present on the MICBIAS output, the MICDET clamp function may
be unable to discharge the capacitor sufficiently to eliminate pops and clicks associated with jack insertion and removal.
In this case, it may be desirable to use the general-purpose switch on the CS47L15 to provide isolation from the MICBIAS
output; an example circuit is shown in Fig. 4-58.
The general-purpose switch is configured using SW1_MODE. This field allows the switch to be disabled, enabled, or
synchronized to the MICDET clamp status, as described in Table 4-64.
For jack pop suppression, it is recommended to set SW1_MODE = 11. In this case, the switch contacts are open whenever
the MICDET clamp status bits are set (clamp enabled), and the switch contacts are closed whenever the MICDET clamp
status bits are clear (clamp disabled).
A typical pop-suppression circuit, incorporating the general-purpose switch and MICDET clamp function, is shown in
Fig. 4-58. Normal accessory functions are supported when the switch contacts (GPSWP and GPSWN) are closed, and
the MICDET clamp is disabled. Ground clamping of MICDET, and isolation of MICBIAS are achieved when the switch
contacts are open, and the MICDET clamp is enabled.
DS1137PP1
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CS47L15
4.9 External Accessory Detection
Note that the MICDET clamp function must also be configured appropriately if using this method of pop suppression
control.
R1 + R2 = 2.2 k(±2%)
R1
CS47L15
MICBIAS1x
C
GPSWP
GPSWN
General- Purpose
Switch Control
R2
SW1_MODE
* IN1BLP, IN1BRP
MICD_CLAMP_OVD
MICD_CLAMP_MODE
MICD_CLAMP_STSx
MICD_CLAMP_DB
MICDET1/
HPOUTFB1
C
* Note: The Jack plug is shown
partially removed, with the MICDET1
pin in contact with the headphone load.
* see note
MICDET2/
HPOUTFB2
MICDET
Clamp Control
* Note that the IN1Bxx analog mic
channels are recommended with the
external accessory detect function
When the MICDET Clamp is active in the configuration
shown, the MICDET1 pin is grounded via the
headphone jack ground connection.
Figure 4-58. General-Purpose Switch Circuit
4.9.2.4 MICDET Clamp Control Registers
The control registers associated with the MICDET clamp and general-purpose switch functions are described in
Table 4-64.
Table 4-64. MICDET Clamp and General-Purpose Switch Control
Register Address
R65 (0x0041)
Sequence_control
138
Bit
Label
Default
Description
7 WSEQ_ENA_
0
MICDET Clamp (Falling) Write Sequencer Select
MICD_CLAMP_
0 = Disabled
FALL
1 = Enabled
6 WSEQ_ENA_
0
MICDET Clamp (Rising) Write Sequencer Select
MICD_CLAMP_
0 = Disabled
RISE
1 = Enabled
DS1137PP1
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4.9 External Accessory Detection
Table 4-64. MICDET Clamp and General-Purpose Switch Control (Cont.)
Register Address
R710 (0x02C6)
Micd_Clamp_
control
R712 (0x02C8)
GP_Switch_1
R6278 (0x1886)
IRQ1_Raw_
Status_7
R6534 (0x1986)
IRQ2_Raw_
Status_7
R6662 (0x1A06)
Interrupt_
Debounce_7
Bit
Label
Default
Description
4 MICD_CLAMP_
1
MICDET Clamp Override
OVD
0 = Disabled (clamp is controlled by MICD_CLAMP_MODE)
1 = Enabled (clamp is enabled)
3:0 MICD_CLAMP_ 0000 MICDET Clamp Mode
MODE[3:0]
0x0 = Disabled
0x9 = Enabled if JD1=0 or JD2=1
0x1 = Enabled (MICDET1/MICDET2 shorted together) 0xA = Enabled if JD1=1 or JD2=0
0x2–0x3 = Reserved
0xB = Enabled if JD1=1 or JD2=1
0x4 = Enabled if JD1=0
0xC = Enabled if JD1=0 and JD2=0
0x5 = Enabled if JD1=1
0xD = Enabled if JD1=0 and JD2=1
0x6 = Enabled if JD2=0
0xE = Enabled if JD1=1 and JD2=0
0x7 = Enabled if JD2=1
0xF = Enabled if JD1=1 and JD2=1
0x8 = Enabled if JD1=0 or JD2=0
1:0 SW1_
00
General-purpose Switch control
MODE[1:0]
00 = Disabled (switch open)
10 = Enabled if MICDET clamp status is set
01 = Enabled (switch closed) 11 = Enabled if MICDET clamp status is clear
4 MICD_CLAMP_
0
MICDET Clamp status
STS1
0 = Clamp disabled
1 = Clamp enabled
4 MICD_CLAMP_
0
MICDET Clamp status
STS2
0 = Clamp disabled
1 = Clamp enabled
4 MICD_CLAMP_
0
MICDET Clamp debounce
DB
0 = Disabled
1 = Enabled
4.9.2.5 Control Sequence for Jack Detect and MICDET Clamp
A summary of the jack detect and MICDET clamp functionality, and the recommended usage in typical applications, is
described as follows.
•
On device power-up, and following reset, the MICDET clamp is enabled due to the default setting of MICD_CLAMP_
OVD; this ensures no spurious output can occur during jack insertion. It is recommended to keep the MICDET clamp
enabled (MICD_CLAMP_OVD = 1) until after a jack insertion has been detected.
The MICDET_CLAMP_MODE field should be set according to the required JD1/JD2 logic condition (configured to
enable the clamp when jack is removed).
•
Jack insertion is indicated using the JD1/JD2 signals or MICDET clamp interrupt (assuming that the MICDET_
CLAMP_MODE field has been correctly set for the applicable JD1/JD2 signal configuration); the associated status
bits can be read directly, or associated signals can be unmasked as inputs to the interrupt controller.
After jack insertion has been detected, the applicable headset functions (headphone, microphone, accessory
detect) may then be enabled.
If the headset function requires MICBIAS to be enabled on the respective jack, the MICDET clamp should be
disabled (MICD_CLAMP_OVD = 0) immediately before enabling the MICBIAS (or immediately before enabling
MICD_ENA). Note that, if MICBIAS is not required on the respective jack, the clamp should not be disabled (e.g.,
for headphone-only operation).
•
Jack removal is also indicated using the JD1/JD2 signals or MICDET clamp interrupts. The associated status bits
can be read directly, or can be unmasked as inputs to the interrupt controller. The MICDET clamp ensures fast and
automatic silencing of the jack outputs.
Under typical use cases, the respective MICBIAS generator and headset audio paths should all be disabled
following jack removal.
After jack removal has been detected, the MICDET clamp override bit (MICD_CLAMP_OVD) should be set, to make
the system ready for a jack insertion.
The recommended control sequence for jack detect and MICDET clamp is summarized in Table 4-65.
DS1137PP1
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4.9 External Accessory Detection
Table 4-65. Control Sequence for Jack Detect and MICDET Clamp
4.9.3
Event
Initial condition
Jack insertion
Device Actions
Clamp enabled by default
Jack insertion signaled via IRQ
Jack removal
Jack removal signaled via IRQ,
Clamp enabled automatically
Recommended User Actions
Configure MICDET_CLAMP_MODE
For headphone-only operation:
Enable output signal paths
For other use cases:
Disable clamp, MICD_CLAMP_OVD = 0
Enable MICBIAS and MICDET
Enable I/O signal paths
Disable MICBIAS and MICDET
Disable I/O signal paths
Enable clamp MICD_CLAMP_OVD = 1
Microphone Detect
The CS47L15 microphone detection circuit measures the impedance of an external load connected to one of the MICDET
pins. This feature can be used to detect the presence of a microphone, and the status of the associated hook switch. It
can also be used to detect push-button status or the connection of other external accessories.
4.9.3.1 Microphone Detect Control
The microphone detection circuit measures the external impedance connected to the MICDETn pins. In the discrete
measurement mode, the function reports whether the measured impedance lies within one of eight predefined levels. In
the ADC measurement mode, a more specific result is provided in the form of a 7-bit ADC output.
Note that microphone/accessory detection is also possible via the HPOUTx and JACKDETn pins, subject to some
additional constraints. If the measurement (sense) pin is connected to MICVDD or MICBIAS1x (typically via a 2.2-k bias
resistor), MICDETn must always be used.
The microphone detection circuit typically uses one of the MICBIAS outputs as a reference. The CS47L15 automatically
enables the appropriate MICBIAS output when required in order to perform the detection function; this allows the detection
function to be supported in low-power standby operating conditions.
The internal 32-kHz clock must be present and enabled when using the microphone detection function; see Section 4.13
for details.
To configure the microphone detection circuit, the applicable pin connections for the intended measurement must be
written to the MICD1_SENSE_SEL and MICD1_GND_SEL fields. The detection circuit measures the external impedance
between the pins selected by these two fields; the valid selections for each are defined in Table 4-66.
Note:
There is no requirement for the SENSE and GND pin selections to be uniquely assigned between the microphone
detect and headphone detect functions—the same pin may be used as a SENSE or GND connection for more
than one of the detection functions. If multiple microphone/headphone detections are enabled, the respective
measurements are automatically scheduled in isolation to each other. See Section 4.9.4 for details of the
headphone detect function.
The microphone detection circuit uses MICVDD, or any one of the MICBIAS1x sources, as a reference. The applicable
source is configured using the MICD1_BIAS_SRC field. If HPOUTx or JACKDETn is selected as the measurement pin
(MICD1_SENSE_SEL = 1XX), MICD1_BIAS_SRC should be set to 1111.
The microphone detection function is enabled by setting MICD1_ENA.
When microphone detection is enabled, the CS47L15 performs a number of measurements in order to determine the
external impedance between the selected pins. The measurement process is repeated at a cyclic rate controlled by
MICD1_RATE. The MICD1_RATE field selects the delay between completion of one measurement and the start of the
next. When the microphone detection result has settled, the CS47L15 indicates valid data by setting MICD1_VALID.
The discrete measurement mode and ADC measurement mode provide different capabilities for microphone detection.
The control requirements and the measurement indication mechanisms differ according to the selected mode, as follows:
140
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4.9 External Accessory Detection
•
In the discrete measurement mode (MICD1_ADC_MODE = 0), the measured impedance is only deemed valid after
more than one successive measurement has produced the same result. The MICD1_DBTIME field provides control
of the debounce period; this can be either two measurements or four measurements.
When the microphone detection result has settled (i.e., after the applicable debounce period), the CS47L15
indicates valid data by setting the MICD1_VALID bit. The measured impedance is indicated using the MICD1_LVL
and MICD1_STS bits, as described in Table 4-66.
The MICD1_VALID bit, when set, remains asserted for as long as the microphone detection function is enabled (i.e.,
while MICD1_ENA = 1). If the detected impedance changes, the MICD1_LVL and MICD1_STS fields change, but
the MICD1_VALID bit remains set, indicating valid data at all times.
The detection circuit supports up to eight impedance levels (including the no-accessory-detected level), enabling
detection of a typical microphone and up to six push buttons. Each measurement level can be enabled or disabled
independently; this provides flexibility according to the required thresholds, and offers a faster measurement time
in some applications. The MICD1_LVL_SEL field is described in Section 4.9.3.3. The default configuration supports
a maximum of four push buttons, in accordance with the Android™ wired headset specification.
Note that, for typical headset detection, the choice of external resistance values must take into account the
impedance of the microphone—the detected impedance corresponds to the combined parallel resistance of the
microphone and any asserted push button. Examples of suitable external components are described in
Section 5.1.8.
•
In the ADC measurement mode (MICD1_ADC_MODE = 1), the detection function generates two output results,
contained within the MICD1_ADCVAL and MICD1_ADCVAL_DIFF fields. These fields contain the most recent
measurement value (MICD1_ADCVAL) and the measurement difference value (MICD1_ADCVAL_DIFF). The
difference value indicates the difference between the latest measurement and the previous measurement; this can
be used to determine whether the measurement is stable and reliable.
In ADC measurement mode, the detection function must be disabled before the measurement can be read. When
the CS47L15 indicates valid data (MICD1_VALID = 1), the detection must be disabled by setting MICD1_ENA = 0.
Note that MICD1_ADCVAL and MICD1_ADCVAL_DIFF do not follow a linear coding. The appropriate test condition
for accepting the measurement value (or for rescheduling the measurement) varies depending on the application
requirements, and depending on the expected impedance value.
The microphone detection functions are inputs to the interrupt control circuit and can be used to trigger an interrupt event
every time an accessory insertion, removal, or impedance change is detected; see Section 4.12.
The fields associated with microphone detection (or other accessories) are described in Table 4-66. The external circuit
configuration is shown in Fig. 4-59.
Table 4-66. Microphone Detect Control
Register
Address
R674 (0x02A2)
Mic_Detect_1_
Control_0
Bit
Default
15
MICD1_ADC_
MODE
7:4
MICD1_SENSE_
SEL[3:0]
0001
MICD1_GND_
SEL[2:0]
000
2:0
DS1137PP1
Label
0
Description
Mic Detect 1 Measurement Mode
0 = Discrete Mode
1 = ADC Mode
Mic Detect 1 Sense Select
0000 = MICDET1
0001 = MICDET2
0100 = HPOUTL
0101 = HPOUTR
Mic Detect 1 Ground Select
000 = MICDET1/HPOUTFB1
001 = MICDET2/HPOUTFB2
All other codes are reserved
0110 = JACKDET1
0111 = JACKDET2
All other codes are reserved
141
CS47L15
4.9 External Accessory Detection
Table 4-66. Microphone Detect Control (Cont.)
Register
Bit
Label
Default
Description
Address
0001 Mic Detect 1 Bias Start-up Delay (Selects the delay time between enabling the
R675 (0x02A3) 15:12 MICD1_BIAS_
STARTTIME[3:0]
MICBIASnx reference and performing the MICDET function.)
Mic_Detect_1_
Control_1
0000 = 0 ms (continuous)
0101 = 4 ms
1010 = 128 ms
0001 = 0.25 ms
0110 = 8 ms
1011 = 256 ms
0010 = 0.5 ms
0111 = 16 ms
1100 = 512 ms
0011 = 1 ms
1000 = 32 ms
1101 = 24 ms
0100 = 2 ms
1001 = 64 ms
1110 to 1111 = 512 ms
11:8 MICD1_
0001 Mic Detect 1 Rate (Selects the delay between successive MICDET measurements.)
RATE[3:0]
0000 = 0 ms (continuous)
0101 = 4 ms
1010 = 128 ms
0001 = 0.25 ms
0110 = 8 ms
1011 = 256 ms
0010 = 0.5 ms
0111 = 16 ms
1100 = 512 ms
1000 = 32 ms
1101 = 24 ms
0011 = 1 ms
0100 = 2 ms
1001 = 64 ms
1110 to 1111 = 512 ms
7:4 MICD1_BIAS_
0000 Mic Detect 1 Reference Select
SRC[3:0]
0000 = MICBIAS1A
0010 = MICBIAS1C
All other codes are reserved
0001 = MICBIAS1B
1111 = MICVDD
1
MICD1_DBTIME
1
Mic Detect 1 Debounce
0 = 2 measurements
1 = 4 measurements
Only valid if MICD1_ADC_MODE = 0.
0
MICD1_ENA
0
Mic Detect 1 Enable
0 = Disabled
1 = Enabled
R676 (0x02A4) 7:0 MICD1_LVL_
1001_ Mic Detect 1 Level Select (enables mic/accessory detection in specific impedance ranges)
SEL[7:0]
1111 [7] = Enable 1–30 k detection
Mic_Detect_1_
[3] = Not used
Control_2
[6] = Not used
[2] = Enable 360–680  detection
[5] = Not used
[1] = Enable 210–290  detection
[4] = Not used
[0] = Enable 110–180  detection
Only valid if MICD1_ADC_MODE = 0.
R677 (0x02A5) 10:2 MICD1_LVL[8:0]
0_
Mic Detect 1 Level (indicates the measured impedance)
0000_ [8] = 1–30 k
Mic_Detect_1_
[3] = 360–680 
0000 [7] = Not used
Control_3
[2] = 210–290 
[6] = Not used
[1] = 110–180 
[5] = Not used
[0] = 0–70 
[4] = Not used
Accessory detection is assured within the specified impedance limits. Note that other
impedance conditions, including loads >30 k, may also be indicated using these bits.
Only valid if MICD1_ADC_MODE = 0.
1
MICD1_VALID
0
Mic Detect 1 Data Valid
0 = Not Valid
1 = Valid
0
MICD1_STS
0
Mic Detect 1 Status
0 = Mic/accessory not detected
1 = Mic/accessory detected
Mic/accessory detection is assured for load impedance up to 30 k.
Only valid when MICD1_ADC_MODE = 0.
R683 (0x02AB) 15:8 MICD1_
0x00 Mic Detect 1 ADC Level (Difference)
ADCVAL_
Mic_Detect_1_
Only valid if MICD1_ADC_MODE = 1.
DIFF[7:0]
Control_4
6:0 MICD1_
0x00 Mic Detect 1 ADC Level
ADCVAL[6:0]
Only valid if MICD1_ADC_MODE = 1.
The external connections for the microphone detect circuit are shown in Fig. 4-59. In typical applications, it can be used
to detect a microphone or button press.
Note that, when using the microphone detect circuit, it is recommended to use the IN1BLP or IN1BRP analog microphone
input paths to ensure best immunity to electrical transients arising from the external accessory.
142
DS1137PP1
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4.9 External Accessory Detection
Note that the IN1Bxx analog mic channels are
recommended for use with the external accessory
detect function.
If measuring the impedance on a MICBIAS-powered
pin, one of the MICDETn inputs must always be used
as the sense pin, as shown.
MICVDD
MICBIAS1A
MICBIAS1B
MICBIAS1C
2.2 k
(±2%)
External accessories
Accessory-detect reference supply
selected by MICD1_BIAS_SRC (MICVDD or MICBIASnx)
C
INnx
Analog Input
MICDETn
HPOUTx
JACKDETn
Sense pin selected by
MICD1_SENSE_SEL
Accessory /
Button Detect
MICDETn
Button 2
Hookswitch
/ Button 1
Microphone
Ground pin selected
by MICD1_GND_SEL
Figure 4-59. Microphone- and Accessory-Detect Interface
4.9.3.2 MICBIAS Reference Control
The voltage reference for the microphone detection is configured using the MICD1_BIAS_SRC field, as described in
Table 4-66. The microphone detection function automatically enables the applicable reference when required for
impedance measurement.
If the selected reference (MICBIAS1x) is not already enabled, the microphone detect circuit automatically enables the
respective MICBIAS output for short periods of time only, every time the impedance measurement is scheduled. To allow
time for the associated circuitry to stabilize, a time delay is applied before the measurement is performed; this is configured
using MICD1_BIAS_STARTTIME, as described in Table 4-66. If the measurement rate setting (MICD1_RATE) is greater
than 0x0, the delay (MICD1_BIAS_STARTTIME) should be set to 0.25 ms or more.
Note:
The microphone detection automatically enables the applicable MICBIAS1x output switch, every time the
impedance measurement is scheduled. The MICBIAS generator is not controlled automatically—the MICBIAS1
generator must be enabled using the MICB1_ENA bit, as described in Table 4-103.
The timing of the microphone detect function is shown in Fig. 4-60. Two different cases are shown, according to whether
MICBIAS1x is enabled periodically by the impedance measurement function, or is enabled at all times.
If the selected reference (MICBIAS1x) is not enabled continuously, the respective MICBIAS1x discharge bits should be
cleared. The MICBIAS control registers are described in Section 4.16.
DS1137PP1
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CS47L15
4.9 External Accessory Detection
MICB1_ENA = 1, MICB1x_ENA = 0:
MICBIAS1x is enabled periodically for
measurement function
Measurement time
(100 s to 500 s)
time
MICD1_BIAS_STARTTIME
(0 ms to 512 ms; 0.25 ms default)
MICD1_RATE
(0 ms to 512 ms; 0.25 ms default)
MICB1_ENA = 1, MICB1x_ENA = 1:
MICBIAS1x is enabled constantly
Measurement time
(100 s to 500 s)
time
MICD1_RATE
(0 ms to 512 ms; 0.25 ms default)
Figure 4-60. Microphone- and Accessory-Detect Timing
4.9.3.3 Measurement Range Control
If the discrete measurement mode is selected (MICD1_ADC_MODE = 000), the MICD1_LVL_SEL[7:0] bits allow each of
the impedance measurement levels to be enabled or disabled independently. This allows the function to be tailored to the
particular application requirements.
If one or more bits MICD1_LVL_SEL is cleared, the corresponding impedance level is disabled. Any measured impedance
which lies in a disabled level is reported as the next lowest, enabled level.
For example, the MICD1_LVL_SEL[2] bit enables the detection of a 360–680  impedance. If MICD1_LVL_SEL[2] = 0,
an external impedance in this range is indicated in the next lowest detection range (210–290 ); this would be reported in
the MICD1_LVL field as MICD1_LVL[2] = 1.
With default register configuration, and all measurement levels enabled, the CS47L15 can detect the presence of a typical
microphone and up to four push buttons. It is possible to configure the detection circuit for up to eight push buttons, by
adjusting the impedance detection thresholds. However, adjustment of the detection thresholds is outside the scope of
this datasheet—please contact your local Cirrus Logic representative for further information, if required.
The measurement time varies between 100–500 s, depending on the impedance of the external load, and depending on
how many impedance measurement levels are enabled. A high impedance is measured faster than a low impedance.
4.9.3.4 External Components
The external connections for the microphone detect circuit are shown in Fig. 4-59. Examples of suitable external
components are described in Section 5.1.8.
The accuracy of the microphone detect function is assured whenever the connected load is within the applicable limits
specified in Table 3-11. It is required that a 2.2-k (2%) resistor must also be connected between the measurement
(SENSE) pin and the selected MICBIAS reference—different resistor values lead to inaccuracy in the impedance
measurement.
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4.9 External Accessory Detection
Note that, for typical headset detection, the choice of external resistance values must take into account the impedance of
the microphone—the detected impedance corresponds to the combined parallel resistance of the microphone and any
asserted push button.
4.9.4
Headphone Detect
The CS47L15 headphone detection circuit measures the impedance of an external headphone load. This feature can be
used to set different gain levels or to apply other configuration settings according to the type of load connected. Separate
monitor pins are provided for headphone detection on the left and right channels of HPOUT.
4.9.4.1 Headphone Detection Control
The headphone detection circuit measures the external impedance connected to the HPOUTL or HPOUTR pin. In typical
usage, this provides measurement of the load impedance on the headphone outputs.
Note that impedance measurement is also possible via the MICDETn and JACKDETn pins, subject to some additional
constraints. If the measurement (sense) pin is connected to one of the headphone outputs, HPOUTL, HPOUTR, or
JACKDET1 must always be used. The valid measurement range and the measurement accuracy are reduced, if using the
MICDETn or JACKDETn pins.
To configure the headphone detection circuit, the applicable pin connections for the intended measurement must be
written to the HPD_SENSE_SEL and HPD_GND_SEL fields. The headphone detection circuit measures the external
impedance between the pins selected by these two fields; the valid selections for each are defined in Table 4-69.
•
When measuring the load impedance on the HPOUT output paths, the HPD_GND_SEL selection should be the
same MICDETn/HPOUTFBn pin as the ground feedback pin for the headphone output. See Section 4.8.7 to
configure the ground feedback pin for HPOUT.
The HPD_FRC_SEL field must also be configured, to select where the measurement current is applied. As a general rule,
this should be the same as the HPD_SENSE_SEL pin. Other configurations can be used if required—for example, to
improve measurement accuracy in cases where the SENSE input path includes significant unwanted resistance.
Note:
There is no requirement for the SENSE and GND pin selections to be uniquely assigned between the microphone
detect and headphone detect functions—the same pin may be used as a SENSE or GND connection for more
than one of the detection functions. If multiple microphone/headphone detections are enabled, the respective
measurements are automatically scheduled in isolation to each other. See Section 4.9.3 for details of the
microphone detect function.
Headphone detection on the selected channel is commanded by writing 1 to HPD_POLL.
The impedance measurement range is configured using HPD_IMPEDANCE_RANGE. This field should be set in
accordance with the expected load impedance. Note that a number of separate measurements are typically required to
determine the load impedance; the recommended control requirements are described in Section 4.9.4.2.
Note:
Setting HPD_IMPEDANCE_RANGE is not required for detection on the MICDETn or JACKDETn pins (HPD_
SENSE_SEL = 0XX or 11X). The impedance measurement range, and measurement accuracy, in these cases
are different to the HPOUTL and HPOUTR measurements.
For correct operation, the respective output drivers must be disabled when headphone detection is commanded on
HPOUTL or HPOUTR. The required settings are shown in Table 4-67.
Table 4-67. Output Configuration for Headphone Detect
Description
Requirement
HPOUTL Impedance measurement
HP1L_ENA = 0
HPOUTR Impedance measurement
HP1R_ENA = 0
Note: The applicable headphone outputs configuration must be maintained until after the headphone
detection has completed. See Table 4-54 for details of the HP1L_ENA and HP1R_ENA bits.
If headphone detection is performed using a measurement pin that is not connected to one of the headphone outputs, the
HPD_OVD_ENA bit should be cleared.
DS1137PP1
145
CS47L15
4.9 External Accessory Detection
If headphone detection is performed using a measurement pin that is also connected to one of the MICBIAS outputs, the
respective MICBIAS output must be disabled and floating (MICBnx_ENA = 0, MICBnx_DISCH = 0).
When headphone detection is commanded, the CS47L15 uses an adjustable current source to determine the connected
impedance. A sweep of measurement currents is applied. The rate of this sweep can be adjusted using HPD_CLK_DIV
and HPD_RATE.
4.9.4.2 Measurement Output
The headphone detection process typically comprises a number of separate measurements (for different impedance
ranges). Completion of each measurement is indicated by HPD_DONE. When this bit is set, the measurement result can
be read from the HPD_DACVAL field, and decoded as described in Eq. 4-2.
Impedance   
C 0 +  C 1  Offset 
- – C5
= -----------------------------------------------------------------------------------------------------------------------------------------------------------------HPD_DACVAL + 0.5 
1
– ------------------------------------------------------C2
C 3  1 +  C 4  Gradient  
Equation 4-2. Headphone Impedance Calculation
The associated parameters for decoding the measurement result are defined Table 4-68. The applicable values are
dependent on the HPD_IMPEDANCE_RANGE setting in each case. The Offset and Gradient values are derived from
register fields that are factory-calibrated for each device.
Table 4-68. Headphone Measurement Decode Parameters
HPD_IMPEDANCE_
RANGE = 01
1.0
C0
C1
–0.0043
C2
7975
C3
69.6
C4
0.0055
C5
HPD_SENSE_SEL = 0100 or 0101 33.35
All other cases 0.85
Offset
HP_OFFSET_01
Gradient
HP_GRADIENT_0X
Parameter
HPD_IMPEDANCE_
RANGE = 10
9.633
–0.0795
7300
62.9
0.0045
33.35
0.85
HP_OFFSET_10
HP_GRADIENT_1X
HPD_IMPEDANCE_
RANGE = 11
100.684
–0.9494
7300
63.2
0.0045
33.35
0.85
HP_OFFSET_11
HP_GRADIENT_1X
Note that, to achieve the specified measurement accuracy, the above equation must be calculated to an accuracy of at
least 5 decimal places throughout.
The impedance measurement result is valid if 169  HPD_DACVAL  1019. (In case of any contradiction with the HPD_
IMPEDANCE_RANGE description, the HPD_DACVAL validity takes precedence.)
If the external impedance is entirely unknown (i.e., it could lie in any of the HPD_IMPEDANCE_RANGE regions), it is
recommended to test initially with HPD_IMPEDANCE_RANGE = 01. If the resultant HPD_DACVAL is < 169, the
impedance is higher than the selected measurement range, so the test should be scheduled again, after incrementing
HPD_IMPEDANCE_RANGE.
Each measurement is triggered by writing 1 to HPD_POLL. Completion of each measurement is indicated by HPD_DONE.
Note that, after HPD_DONE has been asserted, it remains asserted until the next measurement has been commanded.
Note:
A simpler, but less accurate, procedure for headphone impedance measurement is also supported, using the
HPD_LVL field. When the HPD_DONE bit is set, indicating completion of a measurement, the impedance can be
read directly from the HPD_LVL field, provided that the value lies within the range of the applicable HPD_
IMPEDANCE_RANGE setting.
Note that, for detection using the MICDETn or JACKDETn pins, the HPD_LVL field is the only supported
measurement output option. The HPD_IMPEDANCE_RANGE field is not valid for detection on the MICDETn or
JACKDETn pins. See Table 4-69 for further description of the HPD_LVL field.
146
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CS47L15
4.9 External Accessory Detection
The headphone detection function is an input to the interrupt control circuit and can be used to trigger an interrupt event
on completion of the headphone detection; see Section 4.12.
The fields associated with headphone detection are described in Table 4-69. The external circuit configuration is shown
Fig. 4-61.
Note that 32-bit register addressing is used from R12888 (0x3000) upwards; 16-bit format is used otherwise. The registers
noted in Table 4-69 contain a mixture of 16- and 32-bit register addresses.
Table 4-69. Headphone Detect Control
Register Address
R665 (0x0299)
Headphone_
Detect_0
R667 (0x029B)
Headphone_
Detect_1
Bit
15
Default
0
14:12 HPD_OUT_
SEL[2:0]
000
11:8 HPD_FRC_
SEL[3:0]
000
7:4
HPD_SENSE_
SEL[3:0]
0000
2:0
HPD_GND_
SEL[2:0]
000
10:9 HPD_
IMPEDANCE_
RANGE[1:0]
00
4:3
HPD_CLK_
DIV[1:0]
00
2:1
HPD_
RATE[1:0]
00
HPD_POLL
0
0
DS1137PP1
Label
HPD_OVD_
ENA
Description
Headphone Detect Output Override Enable
This bit, when set, causes the HPD_OUT_SEL headphone output channel to be
automatically configured for headphone detection each time headphone detection is
scheduled. Note that the respective output driver must also be disabled (HP1x_
ENA = 0) for the duration of a headphone output impedance measurement.
0 = Disabled
1 = Enabled
Headphone Detect Output Channel Select
000 = HPOUTL
All other codes are reserved
001 = HPOUTR
Headphone Detect Measurement Current Pin Select
0000 = MICDET1
0110 = JACKDET1
0001 = MICDET2
0111 = JACKDET2
0100 = HPOUTL
All other codes are reserved
0101 = HPOUTR
Headphone Detect Sense Pin Select
0000 = MICDET1
0110 = JACKDET1
0001 = MICDET2
0111 = JACKDET2
0100 = HPOUTL
All other codes are reserved
0101 = HPOUTR
Headphone Detect Ground Pin Select
000 = MICDET1/HPOUTFB1
All other codes are reserved
001 = MICDET2/HPOUTFB2
Headphone Detect Range
00 = Reserved
01 = 0  to 90 
10 = 90  to 1000 
11 = 1 k to 10 k
Only valid when HPD_SENSE_SEL = 0100 or 0101.
Headphone Detect Clock Rate (Selects the clocking rate of the headphone detect
adjustable current source. Decreasing the clock rate gives a slower measurement
time.)
00 = 32 kHz
01 = 16 kHz
10 = 8 kHz
11 = 4 kHz
Headphone Detect Sweep Rate
(Selects the step size between successive measurements. Increasing the step size
gives a faster measurement time.)
00 = 1
01 = 2
10 = 4
11 = Reserved
Headphone Detect Enable
Write 1 to start HP Detect function
147
CS47L15
4.9 External Accessory Detection
Table 4-69. Headphone Detect Control (Cont.)
Register Address
R668 (0x029C)
Headphone_
Detect_2
Bit
15
Label
HPD_DONE
14:0 HPD_
LVL[14:0]
Default
0
0x0000
Description
Headphone Detect Status
0 = HP Detect not complete
1 = HP Detect done
Headphone Detect Level
For HPOUTL or HPOUTR measurement (HPD_SENSE_SEL = 0100 or 0101), HPD_
LVL is valid from 4  to10 k, within the range selected by HPD_IMPEDANCE_
RANGE.
74 = 4 or less
75 = 4.5 
76 = 5 
77 = 5.5 
…
20,066 = 10 k
If HPD_LVL reports a value outside the valid range, the range should be adjusted and
the measurement repeated. A 0- result may be reported if the measurement is less
than the minimum value for the selected range.
R669 (0x029D)
9:0 HPD_
0x000
DACVAL[9:0]
Headphone_
Detect_3
R131076
31:24 HP_OFFSET_
See
(0x20004)
11[7:0]
Footnote 1
OTP_HPDET_Cal_
1
23:16 HP_OFFSET_
See
10[7:0]
Footnote 1
15:8 HP_OFFSET_
See
01[7:0]
Footnote 1
R131078
15:8 HP_
(0x20006)
GRADIENT_
1X[7:0]
OTP_HPDET_Cal_
2
7:0
HP_
GRADIENT_
0X[7:0]
See
Footnote 1
See
Footnote 1
For all other measurements, HPD_LVL is valid from 400  to 6 k only.
800 = 400 or less
801 = 400.5 
802 = 401 
803 = 401.5 
…
12,000 = 6 k
Headphone Detect Level (Coded as integer, LSB = 1).
See separate description for full decode information.
Headphone Detect Calibration field.
Signed number, LSB = 0.25.
Range is –31.75 to +31.75.
Default value is factory-set per device.
Headphone Detect Calibration field.
Signed number, LSB = 0.25.
Range is –31.75 to +31.75.
Default value is factory-set per device.
Headphone Detect Calibration field.
Signed number, LSB = 0.25.
Range is –31.75 to +31.75.
Default value is factory-set per device.
Headphone Detect Calibration field.
Signed number, LSB = 0.25.
Range is –31.75 to +31.75.
Default value is factory-set per device.
Headphone Detect Calibration field.
Signed number, LSB = 0.25.
Range is –31.75 to +31.75.
Default value is factory-set per device.
1. Default value is factory-set per device.
The external connections for the headphone detect circuit are shown in Fig. 4-61.
148
DS1137PP1
CS47L15
4.10 Low Power Sleep Configuration
Note that the HPOUTFB ground connection should
be close to headset jack.
MICDETn
JACKDETn
HPOUTL
HPOUTR
If measuring the impedance on a headphone output
path, HPOUTL, HPOUTR, or JACKDET1 must be
used as the sense pin.
Sense pin selected by
HPD_SENSE_SEL
(optional
series resistors)
Measurement current pin
selected by HPD_FRC_SEL
HPOUTL
HPOUTR
MICDETn/HPOUTFBn
Ground feedback pin
selected by HP1_GND_SEL
Ground measurement pin
selected by HPD_GND_SEL
Figure 4-61. Headphone Detect Interface
Under default conditions, the measurement time varies between 17–244 ms, depending on the impedance of the external
load. A high impedance is measured faster than a low impedance.
4.10 Low Power Sleep Configuration
The CS47L15 supports a low-power Sleep Mode, in which most functions are disabled and power consumption is
minimized. The CS47L15 enters Sleep Mode when the DCVDD supply is removed. Note that the AVDD and DBVDD
supplies must be present throughout the Sleep Mode duration.
In Sleep Mode, the CS47L15 can generate an interrupt event in response to a change in voltage on the JACKDET1 or
JACKDET2 pins. This enables a jack insertion event (or other digital logic transition) to be used to trigger a wake-up of the
CS47L15.
The system clocks (SYSCLK, DSPCLK) should be disabled before selecting Sleep Mode. The external clock input
(MCLKn) may also be stopped, if desired.
The functionality and control fields associated with Sleep Mode are supported via an internal always-on supply domain.
The always-on control registers are listed in Table 4-70. These fields are maintained (i.e., not reset) in Sleep Mode.
Note that the control interface is not supported in Sleep Mode; read/write access to the always-on registers is not possible.
Access to the register map using any of the control interfaces should be ceased before selecting Sleep Mode.
Table 4-70. Sleep Mode Always-On Control Registers
Register Address
Label
R710 (0x02C6)
MICD_CLAMP_OVD
MICD_CLAMP_MODE[3:0]
R723 (0x02D3)
JD2_ENA
JD1_ENA
DS1137PP1
Reference
See Section 4.9
149
CS47L15
4.10 Low Power Sleep Configuration
Table 4-70. Sleep Mode Always-On Control Registers (Cont.)
Register Address
Label
R6150 (0x1806)
MICD_CLAMP_FALL_EINT1
MICD_CLAMP_RISE_EINT1
JD2_FALL_EINT1
JD2_RISE_EINT1
JD1_FALL_EINT1
JD1_RISE_EINT1
R6214 (0x1846)
IM_MICD_CLAMP_FALL_EINT1
IM_MICD_CLAMP_RISE_EINT1
IM_JD2_FALL_EINT1
IM_JD2_RISE_EINT1
IM_JD1_FALL_EINT1
IM_JD1_RISE_EINT1
R6784 (0x1A80)
IM_IRQ1
IRQ_POL
IRQ_OP_CFG
R6864 (0x1AD0)
RESET_PU
RESET_PD
Reference
See Section 4.12
See Section 4.19
The always-on digital I/O pins are listed in Table 4-71. All other digital input pins have no effect in Sleep Mode; all other
digital output pins are undriven (floating).
The IRQ output is normally deasserted in Sleep Mode. In Sleep Mode, the IRQ output can be asserted only in response
to the JACKDET1 or JACKDET2 inputs. If the IRQ output is asserted in Sleep Mode, it can be deasserted only after a
wake-up transition.
Output drivers and bus keepers are disabled in Sleep Mode, for all pins not on the always-on domain; this means that the
logic level on these pins is undefined. If a defined logic state is required during Sleep Mode (e.g., as input to another
device), an external pull resistor may be required. If an external pull resistor is connected to a pin that also supports a bus
keeper function, the pull resistance should be chosen carefully, taking into account the resistance of the bus keeper. See
Section 4.11.1 for specific notes concerning the GPIO pins.
Table 4-71. Sleep Mode Always-On Digital Input/Output Pins
Pin Name
Description
Reference
IRQ
Interrupt Request output
See Section 4.12
JACKDET1
Jack Detect input 1
See Section 4.9
JACKDET2
Jack Detect input 2
See Section 4.9
RESET
Digital Reset input (active low)
See Section 4.19
The always-on functionality includes the JD1 and JD2 control signals, which provide support for the low-power Sleep
Mode. The MICDET clamp status signal is also supported; this is controlled by a selectable logic function, derived from
JD1 and/or JD2.
The JD1, JD2 and MICDET clamp status signals are derived from the JACKDET1 and JACKDET2 inputs, and can be used
to trigger the interrupt controller.
•
The JD1 and JD2 signals are derived from the jack detect function (see Section 4.9). These inputs can be used to
trigger a response to a jack insertion or jack removal detection.
When these signals are enabled, the JD1 and JD2 signals indicate the status of the JACKDET1 and JACKDET2
input pins respectively. See Table 4-63 for details of the associated control fields.
•
The MICDET clamp status is controlled by the JD1 and/or JD2 signals (see Section 4.9). The configurable logic
provides flexibility in selecting the appropriate conditions for activating the MICDET clamp. The clamp status can
be used to trigger a response to a jack insertion or jack removal detection.
The MICDET clamp function is configured using MICD_CLAMP_MODE, as described in Table 4-64.
150
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CS47L15
4.11 General-Purpose I/O
The interrupt functionality associated with these signals is part of the always-on functionality, enabling the CS47L15 to
provide indication of jack insertion or jack removal to the host processor in Sleep Mode; see Section 4.12.
Note that the JACKDET1 and JACKDET2 inputs do not result in a wake-up transition directly; a wake-up transition only
occurs by reapplication of DCVDD. In a typical application, the JACKDETn inputs provide a signal to the applications
processor, via the IRQ output; if a wake-up transition is required, this is triggered by the applications processor enabling
the DCVDD supply.
4.11 General-Purpose I/O
The CS47L15 provides a number of GPIO functions to enable interfacing and detection of external hardware and to
provide logic outputs to other devices. The GPIO input functions can be used to generate an interrupt (IRQ) event. The
GPIO and interrupt circuits support the following functions:
•
Pin-specific alternative functions for external interfaces (AIF, PDM)
•
Logic input/button detect (GPIO input)
•
Logic 1 and Logic 0 output (GPIO output)
•
Interrupt (IRQ) status output
•
Clock output
•
Frequency-locked loop (FLL) status output
•
FLL clock output
•
IEC-60958-3–compatible S/PDIF output
•
Pulse-width modulation (PWM) signal output
•
Overtemperature, speaker short-circuit protection, and speaker shutdown status output
•
General-purpose timer status output
•
Event logger FIFO buffer status output
Logic input and output (GPIO) can be supported in two different ways on the CS47L15. The standard mechanism
described in this section provides a comprehensive suite of options including input debounce, and selectable output drive
configuration. The DSP GPIO circuit is tailored towards more advanced requirements typically demanded by DSP software
features. The DSP GPIO functions are described in Section 4.5.3.
The CS47L15 also incorporates a general-purpose switch feature, which can be used as a controllable analog switch, as
described in Section 4.11.16.
If the master-boot function is selected, the GPIO13 and GPIO14 pins support an I2C control interface that provides read/
write access to the CS47L15 control registers. If the I2C control interface is enabled, the respective GPIO configuration
registers have no effect and the GPIO pins cannot be assigned any other function. See Section 4.14 for details of the
master-boot function.
If the JTAG interface is enabled, the GPIO5 and GPIO9–11 pins are configured as a JTAG interface that provides test and
debug access to the CS47L15 DSP core. The respective GPIO configuration registers have no effect in this case, and the
GPIO pins cannot be assigned any other function. See Section 4.17 for details of the JTAG interface.
4.11.1 GPIO Control
For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1–15). The pin
direction, set by GPn_DIR, must be set according to function selected by GPn_FN.
If a pin is configured as a GPIO input (GPn_DIR = 1, GPn_FN = 0x001), the logic level at the pin can be read from the
respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit.
A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting
the respective GPn_DB bit. The debounce circuit uses the 32-kHz clock, which must be enabled whenever input debounce
functions are required. The debounce time is configurable using the GP_DBTIME field. See Section 4.13 for further details
of the CS47L15 clocking configuration.
DS1137PP1
151
CS47L15
4.11 General-Purpose I/O
Each of the GPIO pins is an input to the interrupt control circuit and can be used to trigger an interrupt event. An interrupt
event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bit is latched once set; it can
be polled at any time or used to control the IRQ signal. See Section 4.12 for details of the interrupt event handling.
Integrated pull-up and pull-down resistors are provided on each of the GPIO pins; these can be configured independently
using the GPn_PU and GPn_PD fields. When the pull-up and pull-down control bits are both enabled, the CS47L15
provides a bus keeper function on the respective pin. The bus keeper function holds the logic level unchanged whenever
the pin is undriven (e.g., if the signal is tristated).
Note:
The bus keeper is enabled by default on all GPIO pins and, if not actively driven, may result in either a Logic 0 or
Logic 1 at the respective input on start-up. If an external pull resistor is connected (e.g., to control the logic level
in Sleep Mode), the chosen resistance should take account of the bus keeper resistance (see Table 3-10). A
strong pull resistor (e.g., 10 k) is required, if a specific start-up condition is to be forced by the external pull
component.
If a pin is configured as a GPIO output (GPn_DIR = 0, GPn_FN = 0x001), its level can be set to Logic 0 or Logic 1 using
the GPn_LVL field. Note that the GPn_LVL bits are write-only when the respective GPIO pin is configured as an output.
If a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the GPn_POL bit. When GPn_
POL = 1, the selected output function is inverted. In the case of logic level output (GPn_FN = 0x001), the external output
is the opposite logic level to GPn_LVL when GPn_POL = 1. Note that, if GPn_FN = 0x000 or 0x002, the GPn_POL bit has
no effect on the respective GPIO pin.
A GPIO output can be either CMOS driven or open drain. This is selected on each pin using the respective GPn_OP_CFG
bit. Note that if GPn_FN = 0x000 or 0x002, the GPn_OP_CFG bit has no effect on the respective GPIO pin—the respective
pin output is CMOS in this case.
The register fields that control the GPIO pins are described in Table 4-72.
Table 4-72. GPIO Control
Register Address
R5888 (0x1700)
GPIO1_CTRL_1
to
R5916 (0x171C)
GPIO15_CTRL_1
152
Bit
15
Label
GPn_LVL
14
GPn_OP_CFG
13
GPn_DB
12
GPn_POL
8:0
GPn_FN[8:0]
Default
Description
See
GPIOn level. Write to this bit to set a GPIO output. Read from this bit to read GPIO
Footnote 2 input level.
For output functions only, if GPn_POL is set, the GPn_LVL bit is the opposite logic
level to the external pin.
Note that, if GPn_DIR = 0, the GPn_LVL bit is write-only.
0
GPIOn Output Configuration
0 = CMOS
1 = Open drain
Note that, if GPn_FN = 0x000 or 0x002, this bit has no effect on the GPIOn output.
If GPn_FN = 0x000, the pin configuration is set according to the applicable
pin-specific function (see Table 4-74). If GPn_FN = 0x002, the pin configuration is
CMOS.
1
GPIOn Input Debounce
0 = Disabled
1 = Enabled
0
GPIOn Output Polarity Select
0 = Noninverted (Active High)
1 = Inverted (Active Low)
Note that, if GPn_FN = 0x000 or 0x002, this bit has no effect on the GPIOn output.
0x001 GPIOn Pin Function
(see Table 4-73 for details)
DS1137PP1
CS47L15
4.11 General-Purpose I/O
Table 4-72. GPIO Control (Cont.)
Register Address
R5889 (0x1701)
GPIO1_CTRL_2
to
R5917 (0x171D)
GPIO15_CTRL_2
Bit
15
Label
GPn_DIR
Default
1
Description
GPIOn Pin Direction
0 = Output
1 = Input
The GPn_DIR bit has no effect if GPn_FN = 0x000 or 0x002. If GPn_FN = 0x000,
the pin direction is set according to the applicable pin-specific function (see
Table 4-74). If GPn_FN = 0x002, the pin direction is set according to the DSP GPIO
configuration.
14 GPn_PU
1
GPIOn Pull-Up Enable
0 = Disabled
1 = Enabled
Note: If GPn_PD and GPn_PU are both set, a bus keeper function is enabled on
the respective GPIOn pin.
13 GPn_PD
1
GPIOn Pull-Down Enable
0 = Disabled
1 = Enabled
Note: If GPn_PD and GPn_PU are both set, a bus keeper function is enabled on
the respective GPIOn pin.
R6848 (0x1AC0)
3:0 GP_DBTIME[3:0]
0000
GPIO Input debounce time
GPIO_Debounce_
0x0 = 100 s
Config
0x1 = 1.5 ms
0x2 = 3 ms
0x3 = 6 ms
0x4 = 12 ms
0x5 = 24 ms
0x6 = 48 ms
0x7 = 96 ms
0x8 = 192 ms
0x9 = 384 ms
0xA = 768 ms
0xB to 0xF = Reserved
1. n is a number (1–15) that identifies the individual GPIO.
2. The default value of GPn_LVL depends upon whether the pin is actively driven by another device. If the pin is actively driven, the bus keeper
maintains this logic level. If the pin is not actively driven, the bus keeper may establish either a Logic 1 or Logic 0 as the initial input level.
4.11.2 GPIO Function Select
The available GPIO functions are described in Table 4-73. The function of each GPIO is set using GPn_FN, where n
identifies the GPIO pin (1–15). Note that the respective GPn_DIR must also be set according to whether the function is an
input or output.
Table 4-73. GPIO Function Select
GPn_FN
Description
0x000 Pin-specific alternate function
0x001
Button-detect input/logic-level
output
0x002
0x003
DSP GPIO
IRQ1 output
0x004
IRQ2 output
0x010
0x013
FLL1 clock
FLL_AO clock
DS1137PP1
Comments
Alternate functions supporting digital microphone, digital audio interface, master control
interface, and PDM output functions.
GPn_DIR = 0: GPIO pin logic level is set by GPn_LVL.
GPn_DIR = 1: Button detect or logic level input.
Low latency input/output for DSP functions.
Interrupt (IRQ1) output
0 = IRQ1 not asserted
1 = IRQ1 asserted
Interrupt (IRQ2) output
0 = IRQ2 not asserted
1 = IRQ2 asserted
Clock output from FLL1
Clock output from FLL_AO
153
CS47L15
4.11 General-Purpose I/O
Table 4-73. GPIO Function Select (Cont.)
GPn_FN
Description
0x018 FLL1 lock
0x01B
FLL_AO lock
0x040
0x048
0x049
0x04C
0x0B6
OPCLK clock output
PWM1 output
PWM2 output
S/PDIF output
SPKOUTL short circuit status
0x0E0
Speaker shutdown status
0x0E1
Speaker overheat shutdown
0x0E2
Speaker overheat warning
0x140
Timer 1 status
0x141
Timer 2 status
0x150
0x151
Comments
Indicates FLL1 lock status
0 = Not locked
1 = Locked
Indicates FLL_AO lock status
0 = Not locked
1 = Locked
Configurable clock output derived from SYSCLK
Configurable PWM output PWM1
Configurable PWM output PWM2
IEC-60958-3–compatible S/PDIF output
SPKOUT short circuit status
0 = Normal
1 = Short Circuit detected
Speaker shutdown status
0 = Normal
1 = Speaker shutdown completed (due to overheat temperature, short-circuit protection, or
general-purpose timer condition)
Indicates shutdown temperature status
0 = Temperature is below shutdown level
1 = Temperature is above shutdown level
Indicates warning temperature status
0 = Temperature is below warning level
1 = Temperature is above warning level
Timer 1 status
A pulse is output after the timer reaches its final count value.
Timer 2 status
A pulse is output after the timer reaches its final count value.
Event Log 1 FIFO not-empty status Event Log 1 FIFO Not-Empty status
0 = FIFO Empty
1 = FIFO Not Empty
Event Log 2 FIFO not-empty status Event Log 2 FIFO Not-Empty status
0 = FIFO Empty
1 = FIFO Not Empty
4.11.3 Pin-Specific Alternative Function—GPn_FN = 0x000
The CS47L15 GPIO capability is multiplexed with the pin-specific functions listed in Table 4-74. The alternate functions
are selected by setting the respective GPn_FN fields to 0x000, as described in Section 4.11.1. Note that each function is
unique to the associated pin and can be supported only on that pin.
If the alternate function is selected on a GPIO pin, the pin direction (input or output) and the output driver configuration
(CMOS or open drain) are set automatically as described in Table 4-74. The respective GPn_DIR and GPn_OP_CFG bits
have no effect in this case.
Table 4-74. GPIO Alternate Functions
Name
AIF1BCLK/GPIO3
AIF1LRCLK/GPIO4
AIF1RXDAT/GPIO2
AIF1TXDAT/GPIO1
AIF2BCLK/GPIO7
AIF2LRCLK/GPIO8
AIF2RXDAT/GPIO6
AIF2TXDAT/GPIO5
AIF3BCLK/GPIO11
154
Condition
GP3_FN = 0x000
GP4_FN = 0x000
GP2_FN = 0x000
GP1_FN = 0x000
GP7_FN = 0x000
GP8_FN = 0x000
GP6_FN = 0x000
GP5_FN = 0x000
GP11_FN = 0x000
Description
Audio Interface 1 bit clock
Audio Interface 1 left/right clock
Audio Interface 1 RX digital audio data
Audio Interface 1 TX digital audio data
Audio Interface 2 bit clock
Audio Interface 2 left/right clock
Audio Interface 2 RX digital audio data
Audio Interface 2 TX digital audio data
Audio Interface 3 bit clock
Direction
Digital I/O
Digital I/O
Digital input
Digital output
Digital I/O
Digital I/O
Digital input
Digital output
Digital I/O
Output Driver
Configuration
CMOS
CMOS
—
CMOS
CMOS
CMOS
—
CMOS
CMOS
DS1137PP1
CS47L15
4.11 General-Purpose I/O
Table 4-74. GPIO Alternate Functions (Cont.)
Name
AIF3LRCLK/GPIO12
AIF3RXDAT/GPIO10
AIF3TXDAT/GPIO9
SPKCLK/GPIO14
SPKTXDAT/GPIO13
SPKRXDAT/GPIO15
Condition
GP12_FN = 0x000
GP10_FN = 0x000
GP9_FN = 0x000
GP14_FN = 0x000
GP13_FN = 0x000
GP15_FN = 0x000
Description
Audio Interface 3 left/right clock
Audio Interface 3 RX digital audio data
Audio Interface 3 TX digital audio data
Digital speaker (PDM) clock
Digital speaker (PDM) TX data
Digital speaker (PDM) RX data
Direction
Digital I/O
Digital input
Digital output
Digital output
Digital output
Digital input
Output Driver
Configuration
CMOS
—
CMOS
CMOS
CMOS
—
If the master-boot function is selected, the GPIO13 and GPIO14 pins support an I2C control interface that provides read/
write access to the CS47L15 control registers. If the I2C control interface is enabled, the respective GPIO configuration
registers have no effect and the GPIO pins cannot be assigned any other function. See Section 4.14 for details of the
master-boot function.
If the JTAG interface is enabled, the GPIO5 and GPIO9–11 pins are configured as a JTAG interface. In this case, the
respective GPIO configuration registers have no effect, and the GPIO pins cannot be assigned any other function. See
Section 4.17 for details of the JTAG interface.
4.11.4 Button Detect (GPIO Input)—GPn_FN = 0x001
Button-detect functionality can be selected on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1. The same functionality can be used to support a jack-detect input function.
It is recommended to enable the GPIO input debounce feature when using GPIOs as button input or jack-detect input.
The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable debounce controls.
Note that GPn_LVL is not affected by the GPn_POL bit.
The debounced GPIO signals are also inputs to the interrupt-control circuit. An interrupt event is triggered on the rising
and falling edges of the GPIO input. The associated interrupt bits are latched once set; they can be polled at any time or
used to control the IRQ signal. See Section 4.12 for details of the interrupt event handling.
4.11.5 Logic 1 and Logic 0 Output (GPIO Output)—GPn_FN = 0x001
The CS47L15 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting the GPIO Output
function as described in Section 4.11.1.
The output logic level is selected using the respective GPn_LVL bit. Note that, if a GPIO pin is configured as an output,
the respective GPn_LVL bits are write-only.
The polarity of the GPIO output can be inverted using the GPn_POL bits. If GPn_POL = 1, the external output is the
opposite logic level to GPn_LVL.
4.11.6 DSP GPIO (Low-Latency DSP Input/Output)—GPn_FN = 0x002
The DSP GPIO function provides an advanced I/O capability for signal-processing applications. The DSP GPIO pins are
accessed using maskable sets of I/O control registers; this allows the selected combinations of GPIOs to be controlled
with ease, regardless of how the allocation of GPIO pins has been implemented in hardware.
The DSP GPIO function is selected by setting the respective GPIO fields as described in Section 4.11.1.
A full description of the DSP GPIO function is provided in Section 4.5.3.
Note that, if GPn_FN is set to 0x002, the respective pin direction (input or output) is set according to the DSP GPIO
configuration for that pin—the GPn_DIR control bit has no effect in this case.
DS1137PP1
155
CS47L15
4.11 General-Purpose I/O
4.11.7 Interrupt (IRQ) Status Output—GPn_FN = 0x003, 0x004
The CS47L15 has an interrupt controller, which can be used to indicate when any selected interrupt events occur.
Individual interrupts may be masked in order to configure the interrupt as required. See Section 4.12 for full definition of
all supported interrupt events.
The interrupt controller supports two separate interrupt request (IRQ) outputs. The IRQ1 or IRQ2 status may be output
directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.11.1.
Note that the IRQ1 status is output on the IRQ pin at all times.
4.11.8 Frequency-Locked Loop (FLL) Clock Output—GPn_FN = 0x010, 0x013
Clock outputs derived from the FLLs may be output on a GPIO pin. The GPIO output from each FLL (FLL1 or FLL_AO) is
controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA fields, as described in Table 4-75.
It is recommended to disable the clock output (FLLn_GPCLK_ENA = 0) before making any change to the respective
FLLn_GPCLK_DIV field.
Note that FLLn_GPCLK_DIV and FLLn_GPCLK_ENA affect the GPIO outputs only; they do not affect the FLL frequency.
The maximum output frequency supported for GPIO output is noted in Table 3-10.
The FLL clock outputs may be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1.
See Section 4.13 for details of the CS47L15 system clocking and how to configure the FLLs.
Table 4-75. FLL Clock Output Control
Register Address
R394 (0x018A)
FLL1_GPIO_Clock
R490 (0x01EA)
FLL_AO_GPIO_
Clock
Bit
7:1
Label
FLL1_GPCLK_
DIV[6:0]
Default
0x02
0
FLL1_GPCLK_
ENA
0
7:1
FLL_AO_GPCLK_
DIV[6:0]
0x01
0
FLL_AO_GPCLK_
ENA
0
Description
FLL1 GPIO Clock Divider
0x00 = Reserved
0x01 = Reserved
0x02 = Divide by 2
0x03 = Divide by 3
0x04 = Divide by 4
…
0x7F = Divide by 127
(FGPIO = FVCO/FLL1_GPCLK_DIV)
FLL1 GPIO Clock Enable
0 = Disabled
1 = Enabled
FLL_AO GPIO Clock Divider
0x00 = Divide by 1
0x01 = Divide by 1
0x02 = Divide by 2
0x03 = Divide by 3
0x04 = Divide by 4
…
0x7F = Divide by 127
(FGPIO = FVCO/FLL_AO_GPCLK_DIV)
FLL_AO GPIO Clock Enable
0 = Disabled
1 = Enabled
4.11.9 Frequency-Locked Loop (FLL) Status Output—GPn_FN = 0x018, 0x01B
The CS47L15 provides FLL status flags, which may be used to control other events. The FLL lock signals indicate whether
FLL lock has been achieved. See Section 4.13.8 and Section 4.13.9 for details of the FLLs.
The FLL lock signals may be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1.
156
DS1137PP1
CS47L15
4.11 General-Purpose I/O
The FLL lock signals are inputs to the interrupt controller circuit. An interrupt event is triggered on the rising edge of these
signals. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal.
See Section 4.12 for details of the interrupt event handling.
4.11.10 OPCLK Clock Output—GPn_FN = 0x040
A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency is controlled by
OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled by setting OPCLK_ENA, as described in Table 4-76.
It is recommended to disable the clock output (OPCLK_ENA = 0) before making any change to OPCLK_DIV or OPCLK_
SEL.
The OPCLK clock can be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1.
Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The maximum output frequency
supported for GPIO output is noted in Table 3-10.
See Section 4.13 for details of the SYSCLK system clock.
Table 4-76. OPCLK Control
Register Address
R329 (0x0149)
Output_system_
clock
Bit
15
Label
OPCLK_ENA
7:3
OPCLK_DIV[4:0]
2:0
OPCLK_SEL[2:0]
Default
Description
0
OPCLK Enable
0 = Disabled
1 = Enabled
0x00 OPCLK Divider
0x02 = Divide by 2
0x04 = Divide by 4
0x06 = Divide by 6
… (even numbers only)
0x1E = Divide by 30
Note that only even numbered divisions (2, 4, 6, etc.) are valid selections.
All other codes are reserved when the OPCLK signal is enabled.
000 OPCLK Source Frequency
000 = 6.144 MHz (5.6448 MHz)
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
011 = 49.152 MHz (45.1584 MHz)
All other codes are reserved
The frequencies in brackets apply for 44.1 kHz–related SYSCLK rates only (i.e.,
SAMPLE_RATE_n = 01XXX).
The OPCLK Source Frequency must be less than or equal to the SYSCLK
frequency.
4.11.11 Pulse-Width Modulation (PWM) Signal Output—GPn_FN = 0x048, 0x049
The CS47L15 incorporates two PWM signal generators, which can be enabled as GPIO outputs. The duty cycle of each
PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting.
The PWM outputs may be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1.
See Section 4.3.12 for details of how to configure the PWM signal generators.
4.11.12 S/PDIF Audio Output—GPn_FN = 0x04C
The CS47L15 incorporates an IEC-60958-3–compatible S/PDIF transmitter, which can be selected as a GPIO output. The
S/PDIF transmitter supports stereo audio channels and allows full control over the S/PDIF validity bits and channel status
information.
DS1137PP1
157
CS47L15
4.11 General-Purpose I/O
The S/PDIF signal may be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1.
See Section 4.3.8 for details of how to configure the S/PDIF output generator.
4.11.13 Overtemperature, Short-Circuit Protection, and Speaker Shutdown Status Output—
GPn_FN = 0x0B6, 0x0E0, 0x0E1, 0x0E2.
The CS47L15 incorporates a temperature sensor, which detects when the device temperature is within normal limits or if
the device is approaching a hazardous temperature condition.
The temperature status may be output directly on a GPIO pin by setting the respective GPIO fields as described in
Section 4.11.1. A GPIO pin can be used to indicate either an Overheat Warning Temperature event or an Overheat
Shutdown Temperature event.
The CS47L15 provides short-circuit protection on the Class D speaker outputs, and on each of the headphone output
paths.
The status of the Class D speaker short-circuit detection circuits may be output directly on a GPIO pin by setting the
respective GPIO fields as described in Section 4.11.1.
If the Overheat Shutdown Temperature is exceeded, or if a short circuit is detected on the Class D speaker outputs, the
Class D speaker outputs are automatically disabled in order to protect the device. The general-purpose timers can be used
as a watchdog function to trigger a shutdown of the Class D speaker drivers. Further details of the Speaker Shutdown
functions are described in Section 4.18. When the speaker driver shutdown is complete, the Speaker Shutdown signal is
asserted. The speaker driver shutdown status can also be output directly on a GPIO pin.
The Overtemperature, short-circuit protection, and Speaker Shutdown status flags are inputs to the interrupt control circuit.
An interrupt event may be triggered on the applicable edges of these signals. The associated interrupt bit is latched once
set; it can be polled at any time or used to control the IRQ signal. See Section 4.12 for details of the interrupt event
handling.
4.11.14 General-Purpose Timer Status Output—GPn_FN = 0x140, 0x141
The general-purpose timers can count up or down, and support continuous or single count modes. Status outputs
indicating the progress of these timers are provided. See Section 4.5.2 for details of the general-purpose timers.
A logic signal from the general-purpose timers may be output directly on a GPIO pin by setting the respective GPIO fields
as described in Section 4.11.1. This logic signal is pulsed high whenever the respective timer reaches its final count value.
The general-purpose timers also provide inputs to the interrupt control circuit. An interrupt event is triggered whenever the
respective timer reaches its final count value. The associated interrupt bits are latched once set; they can be polled at any
time or used to control the IRQ signal. See Section 4.12 for details of the interrupt event handling.
4.11.15 Event Logger FIFO Buffer Status Output—GPn_FN = 0x150, 0x151
The event loggers are each provided with a 16-stage FIFO buffer, in which any detected events (signal transitions) are
recorded. Status outputs for each FIFO buffer are provided. See Section 4.5.1 for details of the event loggers.
A logic signal from the event loggers may be output directly on a GPIO pin by setting the respective GPIO fields as
described in Section 4.11.1. This logic signal is set high whenever the FIFO not-empty condition is true.
The event loggers also provide inputs to the interrupt control circuit. An interrupt event is triggered whenever the respective
FIFO condition occurs. The associated interrupt bits are latched once set; they can be polled at any time or used to control
the IRQ signal. See Section 4.12 for details of the interrupt event handling.
4.11.16 General-Purpose Switch
The CS47L15 provides a general-purpose switch, which can be used as a controllable analog switch for external functions.
The switch is implemented between the GPSWP and GPSWN pins. Note that this feature is entirely independent of the
GPIOn pins.
158
DS1137PP1
CS47L15
4.12 Interrupts
The general-purpose switch is configured using SW1_MODE. This field allows the switch to be disabled, enabled, or
synchronized to the MICDET clamp status, as described in Table 4-77.
The switch is a bidirectional analog switch, offering flexibility in the potential circuit applications. Refer to Table 3-2 and
Table 3-10 for further details.
The switch can be used in conjunction with the MICDET clamp function to suppress pops and clicks associated with jack
insertion and removal. An example circuit is shown in Fig. 4-58 within the External Accessory Detection section. Note that
the MICDET clamp function must also be configured appropriately when using this method of pop suppression.
Table 4-77. General-Purpose Switch Control
Register Address
R712 (0x02C8)
GP_Switch_1
Bit
1:0
Label
SW1_MODE[1:0]
Default
00
Description
General-purpose Switch control
00 = Disabled (open)
01 = Enabled (closed)
10 = Enabled when MICDET clamp is active
11 = Enabled when MICDET clamp is not active
4.12 Interrupts
The interrupt controller has multiple inputs. These include the jack detect and GPIO input pins, DSP_IRQn flags,
headphone/accessory detection, FLL lock detection, and status flags from DSP peripheral functions. See Table 4-78 and
Table 4-79 for a full definition of the interrupt controller inputs. Any combination of these inputs can be used to trigger an
interrupt request event.
The interrupt controller supports two sets of interrupt registers. This allows two separate interrupt request (IRQ) outputs
to be generated, and for each IRQ to report a different set of input or status conditions.
For each interrupt request (IRQ1 and IRQ2) output, there is an interrupt register field associated with each of the interrupt
inputs. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on
rising edges only; some are triggered on both edges. Separate rising and falling interrupt bits are provided for the JD1 and
JD2 signals. The interrupt register fields for IRQ1 are described in Table 4-78. The interrupt register fields for IRQ2 are
described in Table 4-79. The interrupt flags can be polled at any time or in response to the interrupt request output being
signaled via the IRQ pin or a GPIO pin.
All interrupts are edge triggered, as noted above. Many are triggered on both the rising and falling edges and, therefore,
the interrupt bits cannot indicate which edge has been detected. The raw status fields described in Table 4-78 and
Table 4-79 indicate the current value of the corresponding inputs to the interrupt controller. Note that the raw status bits
associated with IRQ1 and IRQ2 provide the same information. The status of any GPIO (or DSP GPIO) inputs can also be
read using the GPIO (or DSP GPIO) control fields, as described in Table 4-72 and Table 4-37.
Individual mask bits can enable or disable different functions from the interrupt controller. The mask bits are described in
Table 4-78 (for IRQ1) and Table 4-79 (for IRQ2). Note that a masked interrupt input does not assert the corresponding
interrupt register field and does not cause the associated interrupt request output to be asserted.
The interrupt request outputs represent the logical OR of the associated interrupt registers. IRQ1 is derived from the x_
EINT1 registers; IRQ2 is derived from the x_EINT2 registers. The interrupt register fields are latching fields and, once they
are set, they are not reset until a 1 is written to the respective bits. The interrupt request outputs are not reset until each
of the associated interrupts has been reset.
A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin using the
fields described in Table 4-72. The GPIO debounce circuit uses the 32-kHz clock, which must be enabled whenever the
GPIO debounce function is required.
The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 bits. When not masked, the IRQ status can be
read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs.
The IRQ1 output is provided externally on the IRQ pin. Under default conditions, this output is active low. The polarity can
be inverted using IRQ_POL. The IRQ output can be either CMOS driven or open drain; this is selected using the IRQ_
OP_CFG bit.
DS1137PP1
159
CS47L15
4.12 Interrupts
The IRQ2 status can be used to trigger DSP firmware execution; see Section 4.4. This allows the DSP firmware execution
to be linked to external events (e.g., jack detection, or GPIO input), or to any of the status conditions flagged by the
interrupt registers.
The IRQ1 and IRQ2 signals may be output on a GPIO pin; see Section 4.11.
The CS47L15 interrupt controller circuit is shown in Fig. 4-62. (Note that not all interrupt inputs are shown.) The control
fields associated with IRQ1 and IRQ2 are described in Table 4-78 and Table 4-79 respectively. The global interrupt mask
bits, status bits, and output configuration fields are described Table 4-80.
Note that, under default register conditions, the boot done status is the only unmasked interrupt source; a falling edge on
the IRQ pin indicates completion of the boot sequence.
De-bouncing & Edge detection
xxx_STSn
xxx_STSn
GP1_LVLn
FLL1_LOCK_STSn
DRC1_SIG_DET_STSn
DSP_IRQ1_STSn
xxx_EINT1
IM_xxx_EINT1
xxx_EINT1
IM_xxx_EINT1
GP1_EINT1
IM_GP1_EINT1
IRQ1_STS
FLL1_LOCK_EINT1
IM_IRQ1
IM_FLL1_LOCK_EINT1
DRC1_SIG_DET_EINT1
IM_DRC1_SIG_DET_EINT1
DSP_IRQ1_EINT1
IM_DSP_IRQ1_EINT1
xxx_EINT2
IM_xxx_EINT2
xxx_EINT2
IM_xxx_EINT2
GP1_EINT2
IM_GP1_EINT2
IRQ2_STS
FLL1_LOCK_EINT2
IM_IRQ2
IM_FLL1_LOCK_EINT2
DRC1_SIG_DET_EINT2
IM_DRC1_SIG_DET_EINT2
DSP_IRQ1_EINT2
IM_DSP_IRQ1_EINT2
Note: not all available interrupt sources are shown
Figure 4-62. Interrupt Controller
The IRQ1 interrupt, mask, and status control registers are described in Table 4-78.
Table 4-78. Interrupt 1 Control Registers
Register Address
R6144 (0x1800)
IRQ1_Status_1
160
Bit
12
Label
CTRLIF_ERR_EINT1
Default
0
9
SYSCLK_FAIL_EINT1
0
7
BOOT_DONE_EINT1
0
Description
Control Interface Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SYSCLK Fail Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Boot Done Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6145 (0x1801)
IRQ1_Status_2
R6149 (0x1805)
IRQ1_Status_6
R6150 (0x1806)
IRQ1_Status_7
R6152 (0x1808)
IRQ1_Status_9
DS1137PP1
Bit
15
Label
FLL_AO_REF_LOST_EINT1
Default
0
14
DSPCLK_ERR_EINT1
0
12
SYSCLK_ERR_EINT1
0
11
FLL_AO_LOCK_EINT1
0
8
FLL1_LOCK_EINT1
0
9
MICDET2_EINT1
0
8
MICDET1_EINT1
0
0
HPDET_EINT1
0
5
MICD_CLAMP_FALL_EINT1
0
4
MICD_CLAMP_RISE_EINT1
0
3
JD2_FALL_EINT1
0
2
JD2_RISE_EINT1
0
1
JD1_FALL_EINT1
0
0
JD1_RISE_EINT1
0
2
INPUTS_SIG_DET_EINT1
0
1
DRC2_SIG_DET_EINT1
0
0
DRC1_SIG_DET_EINT1
0
Description
FLL_AO Reference Lost Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSPCLK Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SYSCLK Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
FLL_AO Lock Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
FLL1 Lock Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Mic/Accessory Detect 2 Interrupt (Detection event triggered)
Note: Cleared when a 1 is written.
Mic/Accessory Detect 1 Interrupt (Detection event triggered)
Note: Cleared when a 1 is written.
Headphone Detect Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
MICDET Clamp Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
MICDET Clamp Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
JD2 Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
JD2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
JD1 Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
JD1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Input Path Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
DRC2 Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
DRC1 Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
161
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6154 (0x180A)
IRQ1_Status_11
R6155 (0x180B)
IRQ1_Status_12
R6156 (0x180C)
IRQ1_Status_13
R6157 (0x180D)
IRQ1_Status_14
162
Bit
15
Label
DSP_IRQ16_EINT1
Default
0
14
DSP_IRQ15_EINT1
0
13
DSP_IRQ14_EINT1
0
12
DSP_IRQ13_EINT1
0
11
DSP_IRQ12_EINT1
0
10
DSP_IRQ11_EINT1
0
9
DSP_IRQ10_EINT1
0
8
DSP_IRQ9_EINT1
0
7
DSP_IRQ8_EINT1
0
6
DSP_IRQ7_EINT1
0
5
DSP_IRQ6_EINT1
0
4
DSP_IRQ5_EINT1
0
3
DSP_IRQ4_EINT1
0
2
DSP_IRQ3_EINT1
0
1
DSP_IRQ2_EINT1
0
0
DSP_IRQ1_EINT1
0
6
SPKOUTL_SC_EINT1
0
3
HP2R_SC_EINT1
0
2
HP2L_SC_EINT1
0
1
HP1R_SC_EINT1
0
0
HP1L_SC_EINT1
0
6
SPKOUTL_ENABLE_DONE_EINT1
0
1
HP1R_ENABLE_DONE_EINT1
0
0
HP1L_ENABLE_DONE_EINT1
0
6
SPKOUTL_DISABLE_DONE_EINT1
0
1
HP1R_DISABLE_DONE_EINT1
0
0
HP1L_DISABLE_DONE_EINT1
0
Description
DSP IRQ16 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ15 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ14 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ13 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ12 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ11 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ10 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ9 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ8 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ7 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ6 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ5 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ4 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ3 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUT Short Circuit Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
EPOUTN Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
EPOUTP Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUT Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR/EPOUTN Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL/EPOUTP Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUTL Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR/EPOUTN Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL/EPOUTP Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6158 (0x180E)
IRQ1_Status_15
R6160 (0x1810)
IRQ1_Status_17
R6164 (0x1814)
IRQ1_Status_21
R6165 (0x1815)
IRQ1_Status_22
R6166 (0x1816)
IRQ1_Status_23
R6167 (0x1817)
IRQ1_Status_24
R6168 (0x1818)
IRQ1_Status_25
R6170 (0x181A)
IRQ1_Status_27
DS1137PP1
Bit
2
Label
SPK_OVERHEAT_WARN_EINT1
Default
0
1
SPK_OVERHEAT_EINT1
0
0
SPK_SHUTDOWN_EINT1
0
14
GP15_EINT1
0
13
GP14_EINT1
0
12
GP13_EINT1
0
11
GP12_EINT1
0
10
GP11_EINT1
0
9
GP10_EINT1
0
8
GP9_EINT1
0
7
GP8_EINT1
0
6
GP7_EINT1
0
5
GP6_EINT1
0
4
GP5_EINT1
0
3
GP4_EINT1
0
2
GP3_EINT1
0
1
GP2_EINT1
0
0
GP1_EINT1
0
1
TIMER2_EINT1
0
0
TIMER1_EINT1
0
1
EVENT2_NOT_EMPTY_EINT1
0
0
EVENT1_NOT_EMPTY_EINT1
0
1
EVENT2_FULL_EINT1
0
0
EVENT1_FULL_EINT1
0
1
EVENT2_WMARK_EINT1
0
0
EVENT1_WMARK_EINT1
0
0
DSP1_DMA_EINT1
00
0
DSP1_START1_EINT1
0
Description
Speaker Overheat Warning Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Speaker Overheat Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Speaker Shutdown Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO15 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO14 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO13 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO12 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO11 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO10 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO9 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO8 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO7 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO6 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO5 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO4 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO3 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO2 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO1 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
Timer 2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Timer 1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Not Empty Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Not Empty Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Full Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Full Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Watermark Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Watermark Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 DMA Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 Start 1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
163
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6171 (0x181B)
IRQ1_Status_28
R6173 (0x181D)
IRQ1_Status_30
R6176 (0x1820)
IRQ1_Status_33
R6208 (0x1840)
to
R6240 (0x1860)
Bit
0
R6272 (0x1880)
IRQ1_Raw_
Status_1
12
CTRLIF_ERR_STS1
7
BOOT_DONE_STS1
15
FLL_AO_REF_LOST_STS1
14
DSPCLK_ERR_STS1
12
SYSCLK_ERR_STS1
11
FLL_AO_LOCK_STS1
8
FLL1_LOCK_STS1
4
MICD_CLAMP_STS1
2
JD2_STS1
0
JD1_STS1
2
INPUTS_SIG_DET_STS1
1
DRC2_SIG_DET_STS1
0
DRC1_SIG_DET_STS1
R6273 (0x1881)
IRQ1_Raw_
Status_2
R6278 (0x1886)
IRQ1_Raw_
Status_7
R6280 (0x1888)
IRQ1_Raw_
Status_9
164
Label
DSP1_START2_EINT1
0
DSP1_BUSY_EINT1
0
DSP1_BUS_ERR_EINT1
IM_*
Default
0
Description
DSP1 Start 2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
0
DSP1 Busy Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
0
DSP1 Bus Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
See
For each x_EINT1 interrupt bit in R6144 to R6176, a
Footnote 1 corresponding mask bit (IM_*) is provided in R6208 to R6240.
The mask bits are coded as follows:
0 = Do not mask interrupt
1 = Mask interrupt
0
Control Interface Error Status
0 = Normal
1 = Control Interface Error
0
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot
Sequence has completed.
0
FLL_AO Reference Lost Status
0 = Normal
1 = Reference Lost
0
DSPCLK Error Interrupt Status
0 = Normal
1 = Insufficient DSPCLK cycles for the requested DSP1 clock
frequency
0
SYSCLK Error Interrupt Status
0 = Normal
1 = Insufficient SYSCLK cycles for the requested signal path
functionality
0
FLL_AO Lock Status
0 = Not locked
1 = Locked
0
FLL1 Lock Status
0 = Not locked
1 = Locked
0
MICDET Clamp status
0 = Clamp not active
1 = Clamp active
0
JACKDET2 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET2 pin is pulled low on jack insertion.)
0
JACKDET1 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET1 pin is pulled low on jack insertion.)
0
Input Path Signal-Detect Status
0 = Normal
1 = Signal detected
0
DRC2 Signal-Detect Status
0 = Normal
1 = Signal detected
0
DRC1 Signal-Detect Status
0 = Normal
1 = Signal detected
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6283 (0x188B)
IRQ1_Raw_
Status_12
R6284 (0x188C)
IRQ1_Raw_
Status_13
R6285 (0x188D)
IRQ1_Raw_
Status_14
R6286 (0x188E)
IRQ1_Raw_
Status_15
DS1137PP1
Bit
6
Label
SPKOUTL_SC_STS1
Default
0
3
HP2R_SC_STS1
0
2
HP2L_SC_STS1
0
1
HP1R_SC_STS1
0
0
HP1L_SC_STS1
0
6
SPKOUTL_ENABLE_DONE_STS1
0
1
HP1R_ENABLE_DONE_STS1
0
0
HP1L_ENABLE_DONE_STS1
0
6
SPKOUTL_DISABLE_DONE_STS1
0
1
HP1R_DISABLE_DONE_STS1
0
0
HP1L_DISABLE_DONE_STS1
0
2
SPK_OVERHEAT_WARN_STS1
0
1
SPK_OVERHEAT_STS1
0
0
SPK_SHUTDOWN_STS1
0
Description
SPKOUT Short Circuit Status
0 = Normal
1 = Short Circuit detected
EPOUTN Short Circuit Status
0 = Normal
1 = Short Circuit detected
EPOUTP Short Circuit Status
0 = Normal
1 = Short Circuit detected
HPOUTR Short Circuit Status
0 = Normal
1 = Short Circuit detected
HPOUTL Short Circuit Status
0 = Normal
1 = Short Circuit detected
SPKOUT Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTR/EPOUTN Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTL/EPOUTP Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
SPKOUT Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTR/EPOUTN Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTL/EPOUTP Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
Speaker Overheat Warning Status
0 = Normal
1 = Warning temperature exceeded
Speaker Overheat Status
0 = Normal
1 = Shutdown temperature exceeded
Speaker Shutdown Status
0 = Normal
1 = Speaker Shutdown completed (due to Overheat
Temperature or Short Circuit condition)
165
CS47L15
4.12 Interrupts
Table 4-78. Interrupt 1 Control Registers (Cont.)
Register Address
R6288 (0x1890)
IRQ1_Raw_
Status_17
R6293 (0x1895)
IRQ1_Raw_
Status_22
Bit
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
Label
GP15_STS1
GP14_STS1
GP13_STS1
GP12_STS1
GP11_STS1
GP10_STS1
GP9_STS1
GP8_STS1
GP7_STS1
GP6_STS1
GP5_STS1
GP4_STS1
GP3_STS1
GP2_STS1
GP1_STS1
EVENT2_NOT_EMPTY_STS1
EVENT1_NOT_EMPTY_STS1
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6294 (0x1896)
IRQ1_Raw_
Status_23
1
0
EVENT2_FULL_STS1
EVENT1_FULL_STS1
0
0
R6295 (0x1897)
IRQ1_Raw_
Status_24
1
0
EVENT2_WMARK_STS1
EVENT1_WMARK_STS1
0
0
R6296 (0x1898)
IRQ1_Raw_
Status_25
0
DSP1_DMA_STS1
00
R6301 (0x189D)
IRQ1_Raw_
Status_30
0
DSP1_BUSY_STS1
0
Description
GPIOn Input status. Reads back the logic level of GPIOn.
Only valid for pins configured as GPIO input (does not include
DSPGPIO inputs).
Event Log n FIFO Not Empty status
0 = FIFO Empty
1 = FIFO Not Empty
Event Log n FIFO Full status
0 = FIFO Not Full
1 = FIFO Full
Event Log n FIFO Watermark status
0 = FIFO Watermark not reached
1 = FIFO Watermark reached
DSP1 DMA status
0 = Normal
1 = All enabled WDMA buffers filled, and all enabled RDMA
buffers emptied
DSP1 Busy status
0 = DSP Idle
1 = DSP Busy
1.The BOOT_DONE_EINT1 interrupt is 0 (unmasked) by default; all other interrupts are 1 (masked) by default.
The IRQ2 interrupt, mask, and status control registers are described in Table 4-79.
Table 4-79. Interrupt 2 Control Registers
Register Address
R6400 (0x1900)
IRQ2_Status_1
R6401 (0x1901)
IRQ2_Status_2
166
Bit
12
Label
CTRLIF_ERR_EINT2
Default
0
9
SYSCLK_FAIL_EINT2
0
7
BOOT_DONE_EINT2
0
15
FLL_AO_REF_LOST_EINT2
0
14
DSPCLK_ERR_EINT2
0
12
SYSCLK_ERR_EINT2
0
11
FLL_AO_LOCK_EINT2
0
8
FLL1_LOCK_EINT2
0
Description
Control Interface Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SYSCLK Fail Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Boot Done Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
FLL_AO Reference Lost Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSPCLK Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SYSCLK Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
FLL_AO Lock Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
FLL1 Lock Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6405 (0x1905)
IRQ2_Status_6
R6406 (0x1906)
IRQ2_Status_7
R6408 (0x1908)
IRQ2_Status_9
DS1137PP1
Bit
9
Label
MICDET2_EINT2
Default
0
8
MICDET1_EINT2
0
0
HPDET_EINT2
0
5
MICD_CLAMP_FALL_EINT2
0
4
MICD_CLAMP_RISE_EINT2
0
3
JD2_FALL_EINT2
0
2
JD2_RISE_EINT2
0
1
JD1_FALL_EINT2
0
0
JD1_RISE_EINT2
0
2
INPUTS_SIG_DET_EINT2
0
1
DRC2_SIG_DET_EINT2
0
0
DRC1_SIG_DET_EINT2
0
Description
Mic/Accessory Detect 2 Interrupt (Detection event triggered)
Note: Cleared when a 1 is written.
Mic/Accessory Detect 1 Interrupt (Detection event triggered)
Note: Cleared when a 1 is written.
Headphone Detect Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
MICDET Clamp Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
MICDET Clamp Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
JD2 Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
JD2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
JD1 Interrupt (Falling edge triggered)
Note: Cleared when a 1 is written.
JD1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Input Path Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
DRC2 Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
DRC1 Signal-Detect Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
167
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6410 (0x190A)
IRQ2_Status_11
R6411 (0x190B)
IRQ2_Status_12
R6412 (0x190C)
IRQ2_Status_13
R6413 (0x190D)
IRQ2_Status_14
168
Bit
15
Label
DSP_IRQ16_EINT2
Default
0
14
DSP_IRQ15_EINT2
0
13
DSP_IRQ14_EINT2
0
12
DSP_IRQ13_EINT2
0
11
DSP_IRQ12_EINT2
0
10
DSP_IRQ11_EINT2
0
9
DSP_IRQ10_EINT2
0
8
DSP_IRQ9_EINT2
0
7
DSP_IRQ8_EINT2
0
6
DSP_IRQ7_EINT2
0
5
DSP_IRQ6_EINT2
0
4
DSP_IRQ5_EINT2
0
3
DSP_IRQ4_EINT2
0
2
DSP_IRQ3_EINT2
0
1
DSP_IRQ2_EINT2
0
0
DSP_IRQ1_EINT2
0
6
SPKOUTL_SC_EINT2
0
3
HP2R_SC_EINT2
0
2
HP2L_SC_EINT2
0
1
HP1R_SC_EINT2
0
0
HP1L_SC_EINT2
0
6
SPKOUTL_ENABLE_DONE_EINT2
0
1
HP1R_ENABLE_DONE_EINT2
0
0
HP1L_ENABLE_DONE_EINT2
0
6
SPKOUTL_DISABLE_DONE_EINT2
0
1
HP1R_DISABLE_DONE_EINT2
0
0
HP1L_DISABLE_DONE_EINT2
0
Description
DSP IRQ16 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ15 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ14 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ13 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ12 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ11 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ10 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ9 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ8 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ7 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ6 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ5 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ4 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ3 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP IRQ1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUT Short Circuit Interrupt (Rising and falling edge
triggered)
Note: Cleared when a 1 is written.
EPOUTN Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
EPOUTP Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL Short Circuit Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUT Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR/EPOUTN Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL/EPOUTP Enable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
SPKOUT Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTR/EPOUTN Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
HPOUTL/EPOUTP Disable Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6414 (0x190E)
IRQ2_Status_15
R6416 (0x1910)
Bit
2
Label
SPK_OVERHEAT_WARN_EINT2
Default
0
1
SPK_OVERHEAT_EINT2
0
0
SPK_SHUTDOWN_EINT2
0
14
GP15_EINT2
0
13
GP14_EINT2
0
12
GP13_EINT2
0
11
GP12_EINT2
0
10
GP11_EINT2
0
9
GP10_EINT2
0
8
GP9_EINT2
0
7
GP8_EINT2
0
6
GP7_EINT2
0
5
GP6_EINT2
0
4
GP5_EINT2
0
3
GP4_EINT2
0
2
GP3_EINT2
0
1
GP2_EINT2
0
0
GP1_EINT2
0
1
TIMER2_EINT2
0
0
TIMER1_EINT2
0
1
EVENT2_NOT_EMPTY_EINT2
0
0
EVENT1_NOT_EMPTY_EINT2
0
1
EVENT2_FULL_EINT2
0
0
EVENT1_FULL_EINT2
0
1
EVENT2_WMARK_EINT2
0
0
EVENT1_WMARK_EINT2
0
0
DSP1_DMA_EINT2
00
0
DSP1_START1_EINT2
0
IRQ2_Status_17
R6420 (0x1914)
IRQ2_Status_21
R6421 (0x1915)
IRQ2_Status_22
R6422 (0x1916)
IRQ2_Status_23
R6423 (0x1917)
IRQ2_Status_24
R6424 (0x1918)
IRQ2_Status_25
R6426 (0x191A)
IRQ2_Status_27
DS1137PP1
Description
Speaker Overheat Warning Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Speaker Overheat Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Speaker Shutdown Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO15 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO14 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO13 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO12 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO11 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO10 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO9 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO8 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO7 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO6 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO5 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO4 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO3 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO2 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
GPIO1 Interrupt (Rising and falling edge triggered)
Note: Cleared when a 1 is written.
Timer 2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Timer 1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Not Empty Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Not Empty Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Full Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Full Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 2 FIFO Watermark Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
Event Log 1 FIFO Watermark Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 DMA Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 Start 1 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
169
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6427 (0x191B)
IRQ2_Status_28
R6429 (0x191D)
IRQ2_Status_30
R6432 (0x1920)
IRQ2_Status_33
R6464 (0x1940)
to
R6496 (0x1960)
Bit
0
R6528 (0x1980)
IRQ2_Raw_
Status_1
R6529 (0x1981)
IRQ2_Raw_
Status_2
R6534 (0x1986)
IRQ2_Raw_
Status_7
R6536 (0x1988)
IRQ2_Raw_
Status_9
170
Label
DSP1_START2_EINT2
Default
0
0
DSP1_BUSY_EINT2
0
0
DSP1_BUS_ERR_EINT2
0
IM_*
1
12
CTRLIF_ERR_STS2
0
7
BOOT_DONE_STS2
0
15
FLL_AO_REF_LOST_STS2
0
14
DSPCLK_ERR_STS2
0
12
SYSCLK_ERR_STS2
0
11
FLL_AO_LOCK_STS2
0
8
FLL1_LOCK_STS2
0
4
MICD_CLAMP_STS2
0
2
JD2_STS2
0
0
JD1_STS2
0
2
INPUTS_SIG_DET_STS2
0
1
DRC2_SIG_DET_STS2
0
0
DRC1_SIG_DET_STS2
0
Description
DSP1 Start 2 Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 Busy Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
DSP1 Bus Error Interrupt (Rising edge triggered)
Note: Cleared when a 1 is written.
For each x_EINT2 interrupt bit in R6400 to R6432, a
corresponding mask bit (IM_*) is provided in R6464 to R6496.
The mask bits are coded as follows:
0 = Do not mask interrupt
1 = Mask interrupt
Control Interface Error Status
0 = Normal
1 = Control Interface Error
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot
Sequence has completed.
FLL_AO Reference Lost Status
0 = Normal
1 = Reference Lost
DSPCLK Error Interrupt Status
0 = Normal
1 = Insufficient DSPCLK cycles for the requested DSP1 clock
frequency
SYSCLK Error Interrupt Status
0 = Normal
1 = Insufficient SYSCLK cycles for the requested signal path
functionality
FLL_AO Lock Status
0 = Not locked
1 = Locked
FLL1 Lock Status
0 = Not locked
1 = Locked
MICDET Clamp status
0 = Clamp not active
1 = Clamp active
JACKDET2 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET2 pin is pulled low on jack insertion.)
JACKDET1 input status
0 = Jack not detected
1 = Jack is detected
(Assumes the JACKDET1 pin is pulled low on jack insertion.)
Input Path Signal-Detect Status
0 = Normal
1 = Signal detected
DRC2 Signal-Detect Status
0 = Normal
1 = Signal detected
DRC1 Signal-Detect Status
0 = Normal
1 = Signal detected
DS1137PP1
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6539 (0x198B)
IRQ2_Raw_
Status_12
R6540 (0x198C)
IRQ2_Raw_
Status_13
R6541 (0x198D)
IRQ2_Raw_
Status_14
R6542 (0x198E)
IRQ2_Raw_
Status_15
DS1137PP1
Bit
6
Label
SPKOUTL_SC_STS2
Default
0
3
HP2R_SC_STS2
0
2
HP2L_SC_STS2
0
1
HP1R_SC_STS2
0
0
HP1L_SC_STS2
0
6
SPKOUTL_ENABLE_DONE_STS2
0
1
HP1R_ENABLE_DONE_STS2
0
0
HP1L_ENABLE_DONE_STS2
0
6
SPKOUTL_DISABLE_DONE_STS2
0
1
HP1R_DISABLE_DONE_STS2
0
0
HP1L_DISABLE_DONE_STS2
0
2
SPK_OVERHEAT_WARN_STS2
0
1
SPK_OVERHEAT_STS2
0
0
SPK_SHUTDOWN_STS2
0
Description
SPKOUT Short Circuit Status
0 = Normal
1 = Short Circuit detected
EPOUTN Short Circuit Status
0 = Normal
1 = Short Circuit detected
EPOUTP Short Circuit Status
0 = Normal
1 = Short Circuit detected
HPOUTR Short Circuit Status
0 = Normal
1 = Short Circuit detected
HPOUTL Short Circuit Status
0 = Normal
1 = Short Circuit detected
SPKOUT Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTR/EPOUTN Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTL/EPOUTP Enable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
SPKOUT Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTR/EPOUTN Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
HPOUTL/EPOUTP Disable Status
0 = Busy (sequence in progress)
1 = Idle (sequence completed)
Speaker Overheat Warning Status
0 = Normal
1 = Warning temperature exceeded
Speaker Overheat Status
0 = Normal
1 = Shutdown temperature exceeded
Speaker Shutdown Status
0 = Normal
1 = Speaker Shutdown completed (due to Overheat
Temperature or Short Circuit condition)
171
CS47L15
4.12 Interrupts
Table 4-79. Interrupt 2 Control Registers (Cont.)
Register Address
R6544 (0x1990)
IRQ2_Raw_
Status_17
R6549 (0x1995)
IRQ2_Raw_
Status_22
Bit
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
Label
GP15_STS2
GP14_STS2
GP13_STS2
GP12_STS2
GP11_STS2
GP10_STS2
GP9_STS2
GP8_STS2
GP7_STS2
GP6_STS2
GP5_STS2
GP4_STS2
GP3_STS2
GP2_STS2
GP1_STS2
EVENT2_NOT_EMPTY_STS2
EVENT1_NOT_EMPTY_STS2
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6550 (0x1996)
IRQ2_Raw_
Status_23
1
0
EVENT2_FULL_STS2
EVENT1_FULL_STS2
0
0
R6551 (0x1997)
IRQ2_Raw_
Status_24
1
0
EVENT2_WMARK_STS2
EVENT1_WMARK_STS2
0
0
R6552 (0x1998)
IRQ2_Raw_
Status_25
0
DSP1_DMA_STS2
00
R6557 (0x199D)
IRQ2_Raw_
Status_30
0
DSP1_BUSY_STS2
0
Description
GPIOn Input status
Reads back the logic level of GPIOn.
Only valid for pins configured as GPIO input (does not include
DSPGPIO inputs).
Event Log n FIFO Not Empty status
0 = FIFO Empty
1 = FIFO Not Empty
Event Log n FIFO Full status
0 = FIFO Not Full
1 = FIFO Full
Event Log n FIFO Watermark status
0 = FIFO Watermark not reached
1 = FIFO Watermark reached
DSP1 DMA status
0 = Normal
1 = All enabled WDMA buffers filled, and all enabled RDMA
buffers emptied
DSP1 Busy status
0 = DSP Idle
1 = DSP Busy
The IRQ output and polarity control registers are described in Table 4-80.
Table 4-80. Interrupt Control Registers
Register Address
R6784 (0x1A80)
IRQ1_CTRL
Bit
11
Label
IM_IRQ1
10
IRQ_POL
1
9
IRQ_OP_CFG
0
R6786 (0x1A82)
IRQ2_CTRL
11
IM_IRQ2
0
R6816 (0x1AA0)
Interrupt_Raw_
Status_1
1
IRQ2_STS
0
0
IRQ1_STS
0
172
Default
0
Description
IRQ1 Output Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
IRQ Output Polarity Select
0 = Noninverted (Active High)
1 = Inverted (Active Low)
IRQ Output Configuration
0 = CMOS
1 = Open drain
IRQ2 Output Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
IRQ2 Status. IRQ2_STS is the logical OR of all unmasked x_EINT2 interrupts.
0 = Not asserted
1 = Asserted
IRQ1 Status. IRQ1_STS is the logical OR of all unmasked x_EINT1 interrupts.
0 = Not asserted
1 = Asserted
DS1137PP1
CS47L15
4.13 Clocking and Sample Rates
4.13 Clocking and Sample Rates
The CS47L15 requires a clock reference for its internal functions and also for the input (ADC) paths, output (DAC) paths,
and digital audio interfaces. Under typical clocking configurations, all commonly used audio sample rates can be derived
directly from the external reference; for additional flexibility, the CS47L15 incorporates two FLL circuits to perform
frequency conversion and filtering.
External clock signals may be connected via MCLK1 and MCLK2. In AIF Slave Modes, the BCLK signals may be used as
a reference for the system clocks. To avoid audible glitches, all clock configurations must be set up before enabling
playback.
4.13.1 System Clocking Overview
The CS47L15 supports two primary clock domains—SYSCLK and DSPCLK.
The SYSCLK clock domain is the reference clock for all the audio signal paths on the CS47L15. Up to three different
sample rates may be independently selected for specific audio interfaces and other input/output signal paths.
The DSPCLK clock domain is the reference clock for the programmable DSP core on the CS47L15. A wide range of
DSPCLK frequencies can be supported, and a programmable clock divider is also provided for the DSP core, allowing the
DSP clocking (and power consumption) to be optimized according to the applicable processing requirements. See
Section 4.3 for further details.
Note that there is no requirement for DSPCLK to be synchronized to SYSCLK. The DSPCLK controls the software
execution in the DSP core; audio outputs from the DSP are synchronized to SYSCLK, regardless of the applicable
DSPCLK rate.
Excluding the DSP, each subsystem within the CS47L15 digital core is clocked at a dynamically controlled rate, limited by
the SYSCLK frequency. For maximum signal mixing and processing capacity, it is recommended that the highest possible
SYSCLK frequency is configured.
The DSP core is clocked at the DSPCLK rate (or supported divisions of the DSPCLK frequency). The DSPCLK
configuration must ensure that sufficient clock cycles are available for the applicable processing requirements. The
requirements vary, according to the particular software that is in use.
4.13.2 Sample-Rate Control
The CS47L15 audio signal paths are synchronized to the SYSCLK system clock.
Different sample rates may be selected for each of the audio interfaces (AIF1, AIF2, AIF3), and for the input (ADC) and
output (DAC) paths, but each enabled interface must still be synchronized to SYSCLK.
The CS47L15 can support a maximum of three different sample rates at any time. The supported sample rates range from
8kHz to 192kHz.
The applicable sample rates are selected using SAMPLE_RATE_1, SAMPLE_RATE_2 and SAMPLE_RATE_3. These
must each be numerically related to each other and to the SYSCLK frequency (further details of these requirements are
provided in Table 4-81 and the accompanying text).
Each of the audio interfaces, input paths, and output paths is associated with one of the sample rates selected by the
SAMPLE_RATE_n fields.
Note that, when any of the SAMPLE_RATE_n fields is written to, the activation of the new setting is automatically
synchronized by the CS47L15 to ensure continuity of all active signal paths. The SAMPLE_RATE_n_STS bits provide
indication of the sample rate selections that have been implemented.
The following restrictions must be observed regarding the sample-rate control configuration:
•
All external clock references (MCLK input or Slave Mode AIF input) must be within 1% of the applicable register
field settings.
•
The input (ADC/DMIC) sample rate is valid from 8–192 kHz. If 384- or 768-kHz DMIC clock rate is selected on any
of the input paths, the supported sample rate is valid only up to 48 or 96 kHz respectively.
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4.13 Clocking and Sample Rates
•
The S/PDIF sample rate is valid from 32–192 kHz.
•
The isochronous sample-rate converters (ISRCs) support sample rates 8–192 kHz. For each ISRC, the higher
sample rate must be an integer multiple of the lower rate.
4.13.3 Automatic Sample-Rate Detection
The CS47L15 supports automatic sample-rate detection on the digital audio interfaces (AIF1–AIF3). Note that this is only
possible when the respective interface is operating in Slave Mode (i.e., when LRCLK and BCLK are inputs to the
CS47L15).
Automatic sample-rate detection is enabled by setting RATE_EST_ENA. The LRCLK input pin selected for sample-rate
detection is set using LRCLK_SRC.
As many as four audio sample rates can be configured for automatic detection; these sample rates are selected using the
SAMPLE_RATE_DETECT_n fields. Note that the function only detects sample rates that match one of the SAMPLE_
RATE_DETECT_n fields.
If one of the selected audio sample rates is detected on the selected LRCLK input, the control-write sequencer is triggered.
A unique sequence of actions may be programmed for each of the detected sample rates. Note that the applicable control
sequences must be programmed by the user for each detection outcome; see Section 4.15.
The TRIG_ON_STARTUP bit controls whether the sample-rate detection circuit responds to the initial detection of the
applicable interface (i.e., when the AIFn interface starts up).
•
If TRIG_ON_STARTUP = 0, the detection circuit only responds (i.e., trigger the control-write sequencer) to a
change in the detected sample rate—the initial sample-rate detection is ignored. (Note that the initial sample-rate
detection is the first detection of a sample rate that matches one of the SAMPLE_RATE_DETECT_n fields.)
•
If TRIG_ON_STARTUP = 1, the detection circuit triggers the control-write sequencer whenever a selected sample
rate is detected, including when the AIF interface starts up, or when the sample-rate detection is first enabled.
As described above, setting TRIG_ON_STARTUP = 0 is designed to inhibit any response to the initial detection of a
sample rate that matches one of the SAMPLE_RATE_DETECT_n fields. Note that, if the LRCLK_SRC setting is changed,
or if the detection function is disabled and reenabled, a subsequent detection of a matching sample rate may trigger the
control-write sequencer, regardless of the TRIG_ON_STARTUP setting.
There are some restrictions to be observed regarding the automatic sample-rate detection configuration, as noted in the
following:
•
The same sample rate must not be selected on more than one of the SAMPLE_RATE_DETECT_n fields.
•
Sample rates 192 kHz and 176.4 kHz must not be selected concurrently.
•
Sample rates 96 kHz and 88.2 kHz must not be selected concurrently.
The control registers associated with the automatic sample-rate detection function are described in Table 4-82.
4.13.4 System Clock Configuration
The system clocks (SYSCLK and DSPCLK) may be provided directly from external inputs (MCLK, or Slave Mode BCLK
inputs). Alternatively, these clocks can be derived using the integrated FLLs, with MCLK, BCLK or LRCLK as a reference.
Each clock is configured independently, as described in the following sections.
The SYSCLK clock must be configured and enabled before any audio path is enabled. The DSPCLK clock must be
configured and enabled, if running firmware applications on any of the DSP cores.
4.13.4.1 SYSCLK Configuration
The required SYSCLK frequency is dependent on the SAMPLE_RATE_n fields. Table 4-81 illustrates the valid SYSCLK
frequencies for every supported sample rate.
The SYSCLK frequency must be valid for all of the SAMPLE_RATE_n fields. It follows that all of the SAMPLE_RATE_n
fields must select numerically-related values, that is, all from the same group of sample rates as represented in Table 4-81.
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4.13 Clocking and Sample Rates
Table 4-81. SYSCLK Frequency Selection
SYSCLK Frequency (MHz)
6.144
12.288
24.576
49.152
98.304
SYSCLK_FREQ
000
001
010
011
100
SYSCLK_FRAC
0
Sample Rate (kHz)
SAMPLE_RATE_n
12
0x01
24
0x02
48
0x03
96
0x04
192
0x05
8
0x11
16
0x12
32
0x13
5.6448
000
1
11.025
0x09
11.2896
001
22.05
0x0A
22.5792
010
44.1
0x0B
45.1584
011
88.2
0x0C
90.3168
100
176.4
0x0D
Note: The SAMPLE_RATE_n fields must each be set to a value from the same group of sample rates, and from the same
group as the SYSCLK frequency.
SYSCLK_SRC is used to select the SYSCLK source, as described in Table 4-82. The source may be MCLKn, AIFnBCLK,
or FLLn. If an FLL circuit is selected as the source, the relevant FLL must be enabled and configured, as described in
Section 4.13.8 and Section 4.13.9.
Note:
FLL_AO is designed to support low-power always-on use cases only; for hi-fi audio use cases, it is recommended
to use FLL1.
If FLL_AO is selected as SYSCLK source, two different clock frequencies are available—the loop frequency
(45–50 MHz) or a higher frequency (loop frequency multiplied by 2). If either of these clocks is the SYSCLK
source, FLL_AO must be enabled and configured. The FLL_AO_FREQ field must also be configured for the
applicable (loop) frequency.
SYSCLK_FREQ and SYSCLK_FRAC must be set according to the frequency of the selected SYSCLK source.
The SYSCLK-referenced circuits within the digital core are clocked at a dynamically controlled rate that is limited by the
SYSCLK frequency. For maximum signal mixing and processing capacity, the highest possible SYSCLK frequency should
be used.
The SAMPLE_RATE_n fields are set according to the sample rates that are required by one or more of the CS47L15 audio
interfaces. The CS47L15 supports sample rates ranging from 8–192 kHz.
The SYSCLK signal is enabled by setting SYSCLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLLn) must
be enabled before setting SYSCLK_ENA. This bit should be cleared before stopping or removing the applicable clock
source.
The CS47L15 supports seamless switching between clock sources. To change the SYSCLK configuration while SYSCLK
is enabled, the SYSCLK_FRAC, SYSCLK_FREQ, and SYSCLK_SRC fields must be updated together in one register
write operation. Note that, if changing the frequency only (not the source), SYSCLK_ENA should be cleared before the
clock frequency is updated. The current SYSCLK frequency and source can be read from the SYSCLK_FREQ_STS and
SYSCLK_SRC_STS fields respectively.
The CS47L15 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the
commanded signal paths and processing functions. If the frequency is too low, an attempt to enable a signal path or
processing function fails. Note that active signal paths are not affected under such circumstances.
The SYSCLK frequency check provides input to the interrupt-control circuit and can be used to trigger an interrupt event
if the frequency is not high enough to support the commanded functionality; see Section 4.12.
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4.13 Clocking and Sample Rates
4.13.4.2 DSPCLK Configuration
The required DSPCLK frequency depends on the requirements of firmware loaded on the DSP core. The DSP is clocked
at the DSPCLK rate or at supported divisions of the DSPCLK frequency. The DSPCLK configuration must ensure that
sufficient clock cycles are available for the applicable processing requirements. The requirements vary, according to the
particular software that is in use.
A configurable clock divider is also provided for the DSP core, allowing the DSP clocking (and power consumption) to be
optimized according to the applicable processing requirements; see Section 4.4 for details.
DSP_CLK_FREQ must be configured for the applicable DSPCLK frequency. This field is coded in LSB units of 1/64 MHz.
Note that, if the field coding cannot represent the DSPCLK frequency exactly, the DSPCLK frequency must be rounded
down in the DSP_CLK_FREQ field.
The suggested method for calculating DSP_CLK_FREQ is to multiply the DSPCLK frequency by 64, round down to the
nearest integer, and use the resulting integer as DSP_CLK_FREQ (LSB = 1).
DSP_CLK_SRC is used to select the DSPCLK source, as described in Table 4-82. The source may be MCLKn,
AIFnBCLK, or FLLn. If an FLL circuit is selected as the source, the relevant FLL must be enabled and configured, as
described in Section 4.13.8 and Section 4.13.9.
Note:
If FLL1 is selected as DSPCLK source, the DSPCLK frequency is FVCO × 1.5.
If FLL_AO is selected as DSPCLK source, two different clock frequencies are available—the loop frequency
(45–50 MHz) or a higher frequency (loop frequency multiplied by 3). If either of these clocks is the DSPCLK
source, the FLL_AO must be enabled and configured. The FLL_AO_FREQ must also be configured for the
applicable (loop) frequency.
The DSPCLK signal is enabled by setting DSP_CLK_ENA. The applicable clock source (MCLKn, AIFnBCLK, or FLL) must
be enabled before setting DSP_CLK_ENA. This bit should be cleared when reconfiguring the clock sources.
The CS47L15 supports seamless switching between clock sources. To change the DSPCLK configuration while DSPCLK
is enabled, the DSP_CLK_FREQ field must be updated before DSP_CLK_SRC. The new configuration becomes effective
when the DSP_CLK_SRC field is written. Note that, if changing the frequency only (not the source), the DSP_CLK_ENA
bit should be cleared before the clock frequency is updated. The current DSPCLK frequency and source can be read from
the DSP_CLK_FREQ_STS and DSP_CLK_SRC_STS fields respectively.
In a typical application, DSPCLK and SYSCLK are derived from a single FLL source. Note that there is no requirement for
DSPCLK to be synchronized to SYSCLK. The DSPCLK controls the software execution in the DSP core; audio outputs
from the DSP are synchronized to SYSCLK, regardless of the applicable DSPCLK rate.
Under specific conditions, the CS47L15 can provide clocking to the DSP core when DSPCLK is disabled. This capability
is supported using the always-on FLL (FLL_AO), either in Free-Running Mode or locked to a valid clock reference. See
Section 4.4.3 for further details.
4.13.5 Miscellaneous Clock Controls
The CS47L15 incorporates a 32-kHz clock circuit, which is required for input signal debounce, and microphone/accessory
detect circuits. The 32-kHz clock must be configured and enabled whenever any of these features are in use.
The 32-kHz clock can be generated automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The
32-kHz clock source is selected using CLK_32K_SRC. The 32-kHz clock is enabled by setting CLK_32K_ENA.
A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See Section 4.11 for details on configuring
a GPIO pin for this function.
The CS47L15 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a flexible capability
for interfacing with other devices.
The clocking scheme for the CS47L15 is shown in Fig. 4-63.
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4.13 Clocking and Sample Rates
32k Clock
CLK_32K_ENA
CLK_32K_SRC
Divider
(Auto)
OPCLK
MCLK1
MCLK2
OPCLK_ENA
Divider
AIF1BCLK
AIF2BCLK
AIF3BCLK
OPCLK_SEL
OPCLK_DIV
SYSCLK
x2
SYSCLK_ENA
SYSCLK_SRC
DSPCLK
x1.5
DSP_CLK_ENA
x3
DSP_CLK_SRC
FLL1
GPIO
Divider
FLL1_REFCLK_SRC
FLL1_GPCLK_ENA
FLL1_GPCLK_DIV
(see note )
FLL(AO)CLK
‘Always-On’ clock for DSP core
(disabled by default )
FLL_
AO
Divider
FLL_AO_REFCLK_SRC
GPIO
FLL_AO_GPCLK_ENA
FLL_AO_GPCLK_DIV
(see note )
Automatic Clocking Control
Note:
AIFnLRCLK can also be selected as FLLn input reference
.
SYSCLK _FREQ [2:0]
SYSCLK _FRAC
DSP_CLK_FREQ [15:0]
FLL_AO_FREQ [15:0]
SAMPLE_RATE_1 [4:0]
SAMPLE_RATE_2 [4:0]
SAMPLE_RATE_3 [4:0]
Figure 4-63. System Clocking
The CS47L15 clocking control registers are described in Table 4-82.
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4.13 Clocking and Sample Rates
Table 4-82. Clocking Control
Register Address
R256 (0x0100)
Clock_32k_1
R257 (0x0101)
System_Clock_1
Bit
6
Label
CLK_32K_ENA
1:0
CLK_32K_
SRC[1:0]
10
15
SYSCLK_FRAC
0
10:8 SYSCLK_
FREQ[2:0]
6
SYSCLK_ENA
Default
0
100
0
3:0
SYSCLK_
SRC[3:0]
0100
R258 (0x0102)
Sample_rate_1
4:0
SAMPLE_RATE_
1[4:0]
0x11
R259 (0x0103)
Sample_rate_2
4:0
SAMPLE_RATE_
2[4:0]
0x11
178
Description
32kHz Clock Enable
0 = Disabled
1 = Enabled
32kHz Clock Source
00 = MCLK1 (direct)
01 = MCLK2 (direct)
10 = SYSCLK (automatically divided)
11 = Reserved
SYSCLK Frequency
0 = SYSCLK is a multiple of 6.144MHz
1 = SYSCLK is a multiple of 5.6448MHz
SYSCLK Frequency
000 = 6.144 MHz (5.6448 MHz)
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
011 = 49.152 MHz (45.1584 MHz)
100 = 98.304 MHz (90.3168 MHz)
All other codes are reserved
The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e.,
SAMPLE_RATE_n = 01XXX).
SYSCLK Control
0 = Disabled
1 = Enabled
SYSCLK should only be enabled after the applicable clock source has been
configured and enabled. Set this bit to 0 when reconfiguring the clock sources.
All digital core (audio mixer) x_SRC fields must be cleared before clearing
SYSCLK_ENA = 0.
SYSCLK Source
0000 = MCLK1
0001 = MCLK2
0100 = FLL1
0111 = FLL_AO (x2)
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1111 = FLL_AO
All other codes are reserved
Sample Rate 1 Select
0x00 = None
0x01 = 12 kHz
0x02 = 24 kHz
0x03 = 48 kHz
0x04 = 96 kHz
0x05 = 192 kHz
0x09 = 11.025 kHz
0x0A = 22.05 kHz
0x0B = 44.1 kHz
0x0C = 88.2 kHz
0x0D = 176.4 kHz
0x11 = 8 kHz
0x12 = 16 kHz
0x13 = 32 kHz
All other codes are reserved
Sample Rate 2 Select
Field coding is same as SAMPLE_RATE_1.
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4.13 Clocking and Sample Rates
Table 4-82. Clocking Control (Cont.)
Register Address
R260 (0x0104)
Sample_rate_3
R266 (0x010A)
Sample_rate_1_
status
Bit
4:0
Label
SAMPLE_RATE_
3[4:0]
Default
0x11
4:0
SAMPLE_RATE_
1_STS[4:0]
0x00
R267 (0x010B)
Sample_rate_2_
status
4:0
SAMPLE_RATE_
2_STS[4:0]
0x00
R268 (0x010C)
Sample_rate_3_
status
4:0
SAMPLE_RATE_
3_STS[4:0]
0x00
R288 (0x0120)
DSP_Clock_1
6
3:0
DSP_CLK_ENA
DSP_CLK_
SRC[3:0]
0
0100
R290 (0x0122)
DSP_Clock_2
15:0 DSP_CLK_
FREQ[15:0]
0x0000
R292 (0x0124)
DSP_Clock_3
R294 (0x0126)
DSP_Clock_4
R295 (0x0127)
DSP_Clock_5
15:0 FLL_AO_
FREQ[15:0]
0x0000
15:0 DSP_CLK_
FREQ_STS[15:0]
0x0000
DS1137PP1
3:0
DSP_CLK_SRC_
STS[3:0]
0000
Description
Sample Rate 3 Select
Field coding is same as SAMPLE_RATE_1.
Sample Rate 1 Status
(Read only)
Field coding is same as SAMPLE_RATE_1.
Sample Rate 2 Status
(Read only)
Field coding is same as SAMPLE_RATE_1.
Sample Rate 3 Status
(Read only)
Field coding is same as SAMPLE_RATE_1.
DSPCLK Control
0 = Disabled
1 = Enabled
DSPCLK should only be enabled after the applicable clock source has been
configured and enabled.
Set this bit to 0 when reconfiguring the clock sources.
DSPCLK Source
0000 = MCLK1
0001 = MCLK2
0100 = FLL1 (x1.5)
0111 = FLL_AO (x3)
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1111 = FLL_AO
All other codes are reserved
DSPCLK Frequency
Coded as LSB = 1/64 MHz, Valid from 5.6 MHz to 148 MHz.
Note that, if this field is written while DSPCLK is enabled, the new frequency does
not become effective until DSP_CLK_SRC is updated. To reconfigure DSPCLK
while DSPCLK is enabled, the DSP_CLK_FREQ field must be updated before
DSP_CLK_SRC.
FLL_AO Frequency
Coded as LSB = 1/64 MHz, Valid from 45 MHz to 50 MHz.
DSPCLK Frequency (Read only)
Coded as LSB = 1/64 MHz.
DSPCLK Source (Read only)
0000 = MCLK1
0001 = MCLK2
0100 = FLL1 (FVCO x 1.5)
0111 = FLL_AO (FNCO x 3)
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1111 = FLL_AO (FNCO)
All other codes are reserved
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Table 4-82. Clocking Control (Cont.)
Register Address
R329 (0x0149)
Output_system_
clock
R334 (0x014E)
Clock_Gen_Pad_
Ctrl
R338 (0x0152)
Rate_Estimator_1
Bit
15
Label
OPCLK_ENA
Default
0
7:3
OPCLK_DIV[4:0]
0x00
2:0
OPCLK_SEL[2:0]
000
8
MCLK2_PD
0
7
MCLK1_PD
0
4
TRIG_ON_
STARTUP
0
3:1
LRCLK_SRC[2:0]
000
0
RATE_EST_ENA
0
R339 (0x0153)
Rate_Estimator_2
4:0
SAMPLE_RATE_
DETECT_A[4:0]
0x00
R340 (0x0154)
Rate_Estimator_3
4:0
SAMPLE_RATE_
DETECT_B[4:0]
0x00
R341 (0x0155)
Rate_Estimator_4
4:0
SAMPLE_RATE_
DETECT_C[4:0]
0x00
180
Description
OPCLK Enable
0 = Disabled
1 = Enabled
OPCLK Divider
0x02 = Divide by 2
0x04 = Divide by 4
0x06 = Divide by 6
… (even numbers only)
0x1E = Divide by 30
Note that only even numbered divisions (2, 4, 6, etc.) are valid selections.
All other codes are reserved when the OPCLK signal is enabled.
OPCLK Source Frequency
000 = 6.144 MHz (5.6448 MHz)
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
011 = 49.152 MHz (45.1584 MHz)
All other codes are reserved
The frequencies in brackets apply for 44.1 kHz–related SYSCLK rates only (i.e.,
SAMPLE_RATE_n = 01XXX).
The OPCLK Source Frequency must be less than or equal to the SYSCLK
frequency.
MCLK2 Pull-Down Control
0 = Disabled
1 = Enabled
MCLK1 Pull-Down Control
0 = Disabled
1 = Enabled
Automatic Sample-Rate Detection Start-Up select
0 = Do not trigger Write Sequencer on initial detection
1 = Always trigger the Write Sequencer on sample-rate detection
Automatic Sample-Rate Detection source
000 = AIF1LRCLK
010 = AIF2LRCLK
100 = AIF3LRCLK
All other codes are reserved
Automatic Sample-Rate Detection control
0 = Disabled
1 = Enabled
Automatic Detection Sample Rate A
(Up to four different sample rates can be configured for automatic detection.)
Field coding is same as SAMPLE_RATE_n.
Automatic Detection Sample Rate B
(Up to four different sample rates can be configured for automatic detection.)
Field coding is same as SAMPLE_RATE_n.
Automatic Detection Sample Rate C
(Up to four different sample rates can be configured for automatic detection.)
Field coding is same as SAMPLE_RATE_n.
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4.13 Clocking and Sample Rates
Table 4-82. Clocking Control (Cont.)
Register Address
R342 (0x0156)
Rate_Estimator_5
Bit
4:0
Label
SAMPLE_RATE_
DETECT_D[4:0]
Default
0x00
R352 (0x0160)
Clocking_debug_5
6:4
SYSCLK_FREQ_
STS[2:0]
000
3:0
SYSCLK_SRC_
STS[3:0]
0000
Description
Automatic Detection Sample Rate D
(Up to four different sample rates can be configured for automatic detection.)
Field coding is same as SAMPLE_RATE_n.
SYSCLK Frequency (Read only)
000 = 6.144 MHz (5.6448 MHz)
001 = 12.288 MHz (11.2896 MHz)
010 = 24.576 MHz (22.5792 MHz)
011 = 49.152 MHz (45.1584 MHz)
100 = 98.304 MHz (90.3168 MHz)
All other codes are reserved
The frequencies in brackets apply for 44.1 kHz–related sample rates only (i.e.,
SAMPLE_RATE_n = 01XXX).
SYSCLK Source (Read only)
0000 = MCLK1
0001 = MCLK2
0100 = FLL1
0111 = FLL_AO (x2)
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1111 = FLL_AO
All other codes are reserved
In AIF Slave Modes, it is important to ensure that SYSCLK is synchronized with the associated external LRCLK. This can
be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by
selecting the external BCLK or LRCLK signal as a reference input to one of the FLLs, as a source for SYSCLK.
If the AIF clock domain is not synchronized with the LRCLK, clicks arising from dropped or repeated audio samples occur,
due to the inherent tolerances of multiple, asynchronous, system clocks. See Section 5.4 for further details on valid
clocking configurations.
4.13.6 BCLK and LRCLK Control
The digital audio interfaces (AIF1–AIF3) use BCLK and LRCLK signals for synchronization. In Master Mode, these are
output signals, generated by the CS47L15. In Slave Mode, these are input signals to the CS47L15. It is also possible to
support mixed master/slave operation.
The BCLK and LRCLK signals are controlled as shown in Fig. 4-64. See Section 4.7 for details of the associated control
fields.
Note that the BCLK and LRCLK signals are synchronized to SYSCLK. See Section 4.3.13 for further details.
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SYSCLK
AIF1_BCLK_MSTR
AIF1_LRCLK_MSTR
AIF1_BCLK_FREQ [4:0]
AIF1_BCPF [12:0]
f/N
Master
Mode
Clock
Outputs
f/N
AIF1BCLK
AIF1LRCLK
AIF2_BCLK_MSTR
AIF2_LRCLK_MSTR
AIF2_BCLK_FREQ [4:0]
AIF2_BCPF [12:0]
f/N
Master
Mode
Clock
Outputs
f/N
AIF3_BCLK_FREQ
[4:0]
AIF2BCLK
AIF2LRCLK
AIF3_BCLK_MSTR
AIF3_LRCLK_MSTR
AIF3_BCPF [12:0]
f/N
f/N
Master
Mode
Clock
Outputs
AIF3BCLK
AIF3LRCLK
Figure 4-64. BCLK and LRCLK Control
4.13.7 Control Interface Clocking
Register map access is possible with or without a system clock—there is no requirement for SYSCLK, or any other system
clock, to be enabled when accessing the register map.
See Section 4.14 for details of control register access.
4.13.8 Frequency-Locked Loop (FLL1)
Two integrated FLLs are provided to support the clocking requirements of the CS47L15. These can be configured
according to the available reference clocks and the application requirements. The reference clock may use a high
frequency (e.g., 12.288 MHz) or low frequency (e.g., 32.768 kHz). The FLL is tolerant of jitter and may be used to generate
a stable output clock from a less stable input reference.
There are two FLL implementations on the CS47L15:
•
FLL1 incorporates two subsystems—the main loop and the synchronizer loop—providing an advanced capability to
use more than one reference clock to achieve best performance. FLL1 is described in the following subsections.
•
FLL_AO is low-power FLL that supports additional always-on capability to provide system clocking when other
references are unavailable or disabled. FLL_AO is described in Section 4.13.9. Note that FLL_AO is designed to
support low-power always-on use cases only; for hi-fi audio use cases, it is recommended to use FLL1.
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4.13.8.1 Overview
The FLL characteristics are summarized in Table 3-11. In normal operation, the FLL output is frequency locked to an input
clock reference. The FLL can be used to generate a free-running clock in the absence of any external reference, as
described in Section 4.13.8.7. Configurable spread-spectrum modulation can be applied to the FLL outputs, to control
electro-magnetic interference (EMI) effects.
The FLL comprises two subsystems—the main loop and the synchronizer loop; these can be used together to maintain
best frequency accuracy and noise (jitter) performance across multiple use cases. The two-loop design enables the FLL
to synchronize effectively to an input clock that may be intermittent or noisy, while also achieving the performance benefits
of a stable clock reference that may be asynchronous to the audio data.
The main loop takes a constant and stable clock reference as its input. For best performance, a high-frequency (e.g.,
12.288 MHz) reference is recommended. The main FLL loop is free running without any clock reference if the input signal
is removed; it can also be configured to initiate an output in the absence of any reference signal.
The synchronizer loop takes a separate clock reference as its input. The synchronizer input may be intermittent (e.g.,
during voice calls only). The FLL uses the synchronizer input, when available, as the frequency reference. To achieve the
designed performance advantage, the synchronizer input must be synchronous with the audio data.
Note that, if only a single clock input reference is used, this must be configured as the main FLL input reference. The
synchronizer should be disabled in this case.
The synchronizer loop should only be used when the main loop clock reference is present. If the input reference to the
main FLL is intermittent, or may be interrupted unexpectedly, the synchronizer should be disabled.
4.13.8.2 FLL Enable
The FLL is enabled by setting FLL1_ENA. The FLL synchronizer is enabled by setting FLL1_SYNC_ENA. The FLL should
be fully configured before setting the FLL1_ENA bit—this should be set as the final step of the FLL-enable sequence.
The FLL1_SYNC_ENA bit should not be changed if FLL1_ENA is set—the FLL1_ENA bit should be cleared before setting
or clearing FLL1_SYNC_ENA.
The FLL supports configurable free-running operation, using the FLL1_FREERUN bit described in Section 4.13.8.7. Note
that, once the FLL output has been established, the FLL is always free running if the input reference clock is stopped,
regardless of the FLL1_FREERUN bit.
To disable the FLL while the input reference clock has stopped, FLL1_FREERUN must be set before clearing the FLL1_
ENA bit.
When changing FLL settings, it is recommended to disable the FLL by clearing the FLL1_ENA bit before updating the other
register fields. When changing the input reference frequency FREF, the FLL should be reset by clearing the FLL1_ENA bit
before updating the affected register fields.
Note that some of the FLL configuration registers can be updated while the FLL is enabled, as described in
Section 4.13.8.4. As a general rule, however, it is recommended to configure the FLL (and FLL Synchronizer, if
applicable), before setting the corresponding x_ENA bits.
The FLL configuration is shown in Fig. 4-65.
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4.13 Clocking and Sample Rates
Main FLL path
MCLK1
MCLK2
Divide by
FLL1_REFCLK_DIV
AIFnBCLK,
AIFnLRCLK
Divide by 1, 2, 4 or 8
FLL1_REFCLK_SRC
FREF
Multiply
by N.K
Multiply by
FLL1_FRATIO
FVCO (90 MHz ≤ Fvco ≤ 104 MHz)
FLL Synchronizer path
Divide by
FLL1_SYNCCLK_DIV
Divide by 1, 2, 4 or 8
FLL1_SYNCCLK_SRC
Synchronizer disabled: N.K = FLL1_N +
Synchronizer enabled:
N.K = FLL1_N +
FOUT (SYSCLK)
Multiply by
1, 2, 3 … 16
FREF <
13.5MHz
FSYNC
FLL1_ENA (FLL Enable)
Multiply
by N.K
(Sync )
FSYNC <
13.5MHz
Multiply by
FLL1_SYNC_FRATIO
Multiply by
1.5
FOUT (DSPCLK)
Divide by
FLL1_GPCLK_DIV
F OUT (GPIO)
Divide by 2, 3 … 127
Multiply by
1, 2, 4, 8 or 16
FLL1_SYNC_ENA
(FLL Synchronizer Enable)
FLL1_THETA
FLL1_LAMBDA
FLL1_THETA
65536
N.K (Sync) = FLL1_SYNC_N +
FLL1_SYNC_THETA
FLL1_SYNC_LAMBDA
Figure 4-65. FLL Configuration
The procedure for configuring the FLL is described in the following subsections. Note that the configuration of the main
FLL path and the FLL synchronizer path are very similar. One or both paths must be configured, depending on the
application requirements:
•
If a single clock input reference is used, only the main FLL path should be used.
•
If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly, only the main FLL path
should be used.
•
If two clock input references are used, the constant or low-noise clock is configured on the main FLL path and the
high-accuracy clock is configured on the FLL synchronizer path. Note that the synchronizer input must be
synchronous with the audio data.
4.13.8.3 Input Frequency Control
The main input reference is selected using FLL1_REFCLK_SRC. The synchronizer input reference is selected using
FLL1_SYNCCLK_SRC. The available options in each case are MCLK1, MCLK2, AIFnBCLK, or AIFnLRCLK.
The FLL1_REFCLK_DIV field controls a programmable divider on the main input reference. The FLL1_SYNCCLK_DIV
field controls a programmable divider on the synchronizer input reference. Each input can be divided by 1, 2, 4 or 8. The
divider should be set to bring each reference down to 13.5 MHz or below. For best performance, it is recommended that
the highest possible frequency—within the 13.5 MHz limit—should be selected.
4.13.8.4 Output Frequency Control—Main Loop
The FLL output frequency, relative to the main input reference FREF, is a function of the following:
•
The FLL oscillator frequency, FVCO
•
The frequency ratio set by FLL1_FRATIO
•
The real number represented by N.K. (N = integer; K = fractional portion)
The FVCO frequency must be in the range 90–104 MHz.
If the FLL is selected as SYSCLK source, the respective FVCO frequency must be exactly 98.304 MHz (for 48 kHz–related
sample rates) or 90.3168 MHz (for 44.1 kHz–related sample rates).
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4.13 Clocking and Sample Rates
If the FLL is selected as DSPCLK source, the DSPCLK frequency is FVCO × 1.5. Note that the DSPCLK can be divided to
lower frequencies for clocking the DSP core.
The FLL clock can be configured as a GPIO output; a programmable divider supports division ratios in the range 2 through
127, enabling a wide range of GPIO clock output frequencies.
Note:
The chosen FVCO frequency can be used to support multiple outputs simultaneously (e.g., SYSCLK, DSPCLK,
and GPIO), as shown in Fig. 4-65.
The FLL oscillator frequency, FVCO is set according to the following equation:
FVCO = (FREF x N.K x FLL1_FRATIO)
The value of N.K can thus be determined as follows:
N.K = FVCO / (FLL1_FRATIO x FREF)
It is recommended to calculate N.K using an initial assumption of FLL1_FRATIO = 1. If N > 1023, FLL1_FRATIO should
be incremented until N < 1024.
Note that, in the above equations, the following interpretations are assumed:
•
FREF is the input frequency, after division by FLL1_REFCLK_DIV, where applicable
•
FLL1_FRATIO is the FVCO clock ratio (1, 2, 3, … 16)
The value of N is held in FLL1_N.
The value of K is determined by the FLL1_THETA and FLL1_LAMBDA fields. In integer mode (K = 0), FLL1_THETA must
be set to 0. (FLL1_LAMBDA is ignored in integer mode.) In fractional mode (K > 0), the FLL1_THETA and FLL1_LAMBDA
fields can be derived as described in Section 4.13.8.6.
The FLL1_N, FLL1_THETA, and FLL1_LAMBDA fields are all coded as integers (LSB = 1).
The FLL1_CTRL_UPD bit controls the updating of the FLL1_N and FLL1_THETA fields:
•
If the FLL1_N or FLL1_THETA fields are updated while the FLL is enabled (FLL1_ENA = 1), the new values are
only effective when a 1 is written to FLL1_CTRL_UPD. This makes it possible to update the two fields
simultaneously, without disabling the FLL.
Note that, if the FLL is disabled (FLL1_ENA = 0), the FLL1_N and FLL1_THETA fields can be updated without
writing to FLL1_CTRL_UPD.
The FLL1_GAIN and FLL1_PHASE_ENA fields should be set as shown in Table 4-83, depending on FREF, FLL1_THETA,
and whether the FLL synchronizer is enabled.
Table 4-83. Selection of FLL1_GAIN and FLL1_PHASE_ENA
Condition
Synchronizer disabled (FLL1_SYNC_ENA = 0) and
FLL Integer Mode (FLL1_THETA = 0)
Synchronizer enabled (FLL1_SYNC_ENA = 1) or
FLL Fractional Mode (FLL1_THETA > 0)
FLL1_GAIN
0x2
FREF < 768 kHz
0x3
FREF  768 kHz
0x0
FREF < 100 kHz
0x2
100 kHz  FREF < 375 kHz
0x3
375 kHz  FREF < 1.5 MHz
1.5 MHz  FREF < 6.0 MHz
0x4
FREF  6.0 MHz
0x5
Note: FREF is the input frequency, after division by FLL1_REFCLK_DIV, where applicable.
FLL1_PHASE_ENA
1
0
4.13.8.5 Output Frequency Control—Synchronizer Loop
A similar procedure applies for the derivation of the FLL synchronizer parameters—assuming that this function is used.
The FLL1_SYNC_FRATIO field selects the frequency division ratio of the FLL synchronizer input. The FLL1_GAIN and
FLL1_SYNC_DFSAT fields are used to optimize the FLL, according to the input frequency. These fields should be set as
described in Table 4-84.
Note:
The FLL1_SYNC_FRATIO coding differs from that of FLL1_FRATIO.
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4.13 Clocking and Sample Rates
Table 4-84. Selection of FLL1_SYNC_FRATIO, FLL1_SYNC_GAIN, FLL1_SYNC_DFSAT
Condition
FLL1_SYNC_FRATIO
FLL1_SYNC_GAIN
FLL1_SYNC_DFSAT
1 MHz  FSYNC < 13.5 MHz
0x0 (divide by 1)
0x4 (16x gain)
0 (wide bandwidth)
256 kHz  FSYNC < 1 MHz
0x1 (divide by 2)
0x2 (4x gain)
0 (wide bandwidth)
0x2 (divide by 4)
0x0 (1x gain)
0 (wide bandwidth)
128 kHz  FSYNC < 256 kHz
64 kHz  FSYNC < 128 kHz
0x3 (divide by 8)
0x0 (1x gain)
1 (narrow bandwidth)
FSYNC < 64 kHz
0x4 (divide by 16)
0x0 (1x gain)
1 (narrow bandwidth)
Note: FSYNC is the synchronizer input frequency, after division by FLL1_SYNCCLK_DIV, where applicable.
The FLL oscillator frequency, FVCO, is the same frequency calculated as described in Section 4.13.8.4.
The value of N.K (Sync) can then be determined as follows:
N.K (Sync) = FVCO / (FLL1_SYNC_FRATIO x FSYNC)
Note that, in the above equation, the following interpretations are assumed:
•
FSYNC is the synchronizer input frequency, after division by FLL1_SYNCCLK_DIV, where applicable
•
FLL1_SYNC_FRATIO is the FVCO clock ratio (1, 2, 4, 8, or 16)
The value of N (Sync) is held in FLL1_SYNC_N.
The value of K (Sync) is determined by the FLL1_SYNC_THETA and FLL1_SYNC_LAMBDA fields. See Section 4.13.8.6
to derive the recommended settings for these fields.
The FLL1_SYNC_N, FLL1_SYNC_THETA, and FLL1_SYNC_LAMBDA fields are all coded as integers (LSB = 1).
4.13.8.6 Calculation of Theta and Lambda
In Fractional Mode, with the synchronizer disabled (K > 0, and FLL1_SYNC_ENA = 0), FLL1_THETA and FLL1_LAMBDA
are calculated with the following steps:
1. Calculate GCD(FLL) using the Greatest Common Denominator function:
GCD(FLL) = GCD(FLL1_FRATIO x FREF, FVCO),
where GCD(x, y) is the greatest common denominator of x and y.
FREF is the input frequency, after division by FLL1_REFCLK_DIV, where applicable.
2. Calculate FLL1_THETA and FLL1_LAMBDA using the following equations:
FLL1_THETA = (FVCO – (FLL_N x FLL1_FRATIO x FREF)) / GCD(FLL)
FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL)
Note that the values of FLL1_THETA and FLL1_LAMBDA must be coprime (i.e., not divisible by any common integer).
The calculation above ensures that the values are coprime. The value of K must be less than 1 (i.e., FLL1_THETA must
be less than FLL1_LAMBDA).
If the synchronizer is enabled, the FLL1_SYNC_THETA and FLL1_SYNC_LAMBDA fields are calculated in the same
manner described above, using the corresponding synchronizer parameters.
In Fractional Mode, with the synchronizer enabled (K > 0, and FLL1_SYNC_ENA = 1), FLL1_THETA is calculated as
FLL1_THETA = K x 65536. The FLL1_LAMBDA field is ignored in this case, and the coprime requirement for FLL1_
LAMBDA and FLL1_THETA is not applicable.
4.13.8.7 Free-Running FLL Mode
The FLL can generate a clock signal even if no external reference is available. This may be because the normal input
reference has been interrupted, or may be during a standby or start-up period when no initial reference clock is available.
Free-Running FLL Mode is enabled by setting FLL1_FREERUN. Note that FLL1_ENA must also be enabled in
Free-Running FLL Mode.
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In Free-Running FLL Mode, the normal feedback mechanism of the FLL is halted and the FLL oscillates independently of
the external input references.
If the FLL was previously operating normally (with an input reference clock), the FLL output frequency remains unchanged
when Free-Running FLL Mode is enabled. The FLL output is independent of the input reference while operating with
FLL1_FREERUN = 1.
The main FLL loop always runs freely if the input reference clock is stopped (regardless of the FLL1_FREERUN setting).
If FLL1_FREERUN = 0, the FLL relocks to the input reference whenever it is available.
In Free-Running FLL Mode, (with FLL1_FREERUN = 1), the FLL integrator value (part of the feedback mechanism) can
be commanded directly using FLL1_FRC_INTEG_VAL. The integrator value in this field is applied to the FLL when a 1 is
written to FLL1_FRC_INTEG_UPD.
If the FLL is started up in Free-Running FLL Mode, (i.e., it was not previously running), the default value of FLL1_FRC_
INTEG_VAL is applied.
The FLL integrator value (part of the feedback mechanism) can be read from the FLL1_INTEG field; the value of this field
may be stored for later use. Note that the value of FLL1_INTEG is only valid if FLL1_FREERUN = 1 and the FLL1_INTEG_
VALID = 1.
The FLL integrator setting does not ensure a specific output frequency for the FLL across all devices and operating
conditions; some level of variation applies.
The free-running FLL clock may be selected as the SYSCLK or DSPCLK source, as shown in Fig. 4-63.
4.13.8.8 Spread-Spectrum FLL Control
The CS47L15 can apply modulation to the FLL output, using spread-spectrum techniques. This can be used to control the
EMI characteristics of the circuits that are clocked via the FLL.
The FLL can be configured for triangle modulation, zero mean frequency modulation (ZMFM), or dither. The amplitude
and frequency parameters of the spread spectrum functions is also programmable, using the fields described in
Section 4.13.8.9.
4.13.8.9 FLL Control Registers
The FLL control registers are described in Table 4-85.
Example settings for a variety of reference frequencies and output frequencies are shown in Section 4.13.8.12.
Table 4-85. FLL1 Register Map
Register Address
R369 (0x0171)
FLL1_Control_1
R370 (0x0172)
FLL1_Control_2
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Bit
1
Label
FLL1_
FREERUN
0
FLL1_ENA
15
FLL1_CTRL_
UPD
9:0
FLL1_N[9:0]
Default
Description
1
FLL1 Free-Running Mode Enable
0 = Disabled
1 = Enabled
The FLL feedback mechanism is halted in Free-Running FLL Mode, and the latest
integrator setting is maintained
0
FLL1 Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the FLL1 enable sequence, i.e., after the other
FLL fields have been configured.
0
FLL1 Control Update
Write 1 to apply the FLL1_N and FLL1_THETA field settings.
(Only valid if FLL1_ENA = 1)
0x008 FLL1 Integer multiply for FREF
(LSB = 1)
If updated while the FLL is enabled, the new value is only effective when a 1 is written
to FLL1_CTRL_UPD.
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Table 4-85. FLL1 Register Map (Cont.)
Register Address Bit
Label
R371 (0x0173)
15:0 FLL1_
THETA[15:0]
FLL1_Control_3
R372 (0x0174)
FLL1_Control_4
R373 (0x0175)
FLL1_Control_5
R374 (0x0176)
FLL1_Control_6
R375 (0x0177)
FLL1_Loop_
Filter_Test_1
R376 (0x0178)
FLL1_NCO_Test_
0
R377 (0x0179)
FLL1_Control_7
R378 (0x017A)
FLL1_Control_8
R385 (0x0181)
FLL1_
Synchroniser_1
R386 (0x0182)
FLL1_
Synchroniser_2
R387 (0x0183)
FLL1_
Synchroniser_3
Default
Description
0x0018 FLL1 Fractional multiply for FREF. Sets the numerator (multiply) part of the FLL1_
THETA / FLL1_LAMBDA ratio.
Coded as LSB = 1.
If updated while the FLL is enabled, the new value is only effective when a 1 is written
to FLL1_CTRL_UPD.
15:0 FLL1_
0x007D FLL1 Fractional multiply for FREF
LAMBDA[15:0]
This field sets the denominator (dividing) part of the FLL1_THETA / FLL1_LAMBDA
ratio.
Coded as LSB = 1.
11:8 FLL1_
0x0
FLL1 FVCO clock divider
FRATIO[3:0]
0x0 = 1
0x2 = 3
…
0x1 = 2
0x3 = 4
0xF = 16
7:6 FLL1_REFCLK_
00
FLL1 Clock Reference Divider
DIV[1:0]
00 = 1
10 = 4
01 = 2
11 = 8
MCLK (or other input reference) must be divided down to 13.5 MHz.
3:0 FLL1_REFCLK_
0000 FLL1 Clock source
SRC[3:0]
0000 = MCLK1
1001 = AIF2BCLK
1101 = AIF2LRCLK
0001 = MCLK2
1010 = AIF3BCLK
1110 = AIF3LRCLK
1000 = AIF1BCLK
1100 = AIF1LRCLK
All other codes are reserved
15 FLL1_FRC_
0
Write 1 to apply the FLL1_FRC_INTEG_VAL setting.
INTEG_UPD
(Only valid if FLL1_FREERUN = 1)
11:0 FLL1_FRC_
0x281 FLL1 Forced Integrator Value
INTEG_
VAL[11:0]
15 FLL1_INTEG_
0
FLL1 Integrator Valid. Indicates whether FLL1_INTEG is valid
VALID
0 = Not valid
1 = Valid
11:0 FLL1_
0x000 FLL1 Integrator Value (Read-only). Indicates the current FLL1 integrator setting. Only
INTEG[11:0]
valid if FLL1_INTEG_VALID = 1.
5:2 FLL1_GAIN[3:0]
0000 FLL1 Gain
0110 = 64
0000 = 1
0011 = 8
0111 = 128
0001 = 2
0100 = 16
0101 = 32
1000–1111 = 256
0010 = 4
11 FLL1_PHASE_
1
FLL1 Phase Integrator Control
ENA
0 = Disabled
1 = Enabled
0
FLL1_SYNC_
0
FLL1 Synchronizer Enable
ENA
0 = Disabled
1 = Enabled
This should be set as the final step of the FLL1 synchronizer enable sequence, i.e.,
after the other synchronizer fields have been configured.
9:0 FLL1_SYNC_
0x000 FLL1 Integer multiply for FSYNC
N[9:0]
(LSB = 1)
15:0 FLL1_SYNC_
THETA[15:0]
R388 (0x0184)
FLL1_
Synchroniser_4
15:0 FLL1_SYNC_
LAMBDA[15:0]
R389 (0x0185)
FLL1_
Synchroniser_5
10:8 FLL1_SYNC_
FRATIO[2:0]
188
0x0000 FLL1 Fractional multiply for FSYNC
This field sets the numerator (multiply) part of the FLL1_SYNC_THETA / FLL1_
SYNC_LAMBDA ratio.
Coded as LSB = 1.
0x0000 FLL1 Fractional multiply for FSYNC
This field sets the denominator (dividing) part of the FLL1_SYNC_THETA / FLL1_
SYNC_LAMBDA ratio.
Coded as LSB = 1.
000
FLL1 Synchronizer FVCO clock divider
000 = 1
010 = 4
1XX = 16
001 = 2
011 = 8
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4.13 Clocking and Sample Rates
Table 4-85. FLL1 Register Map (Cont.)
Register Address
R390 (0x0186)
FLL1_
Synchroniser_6
Bit
7:6
3:0
R391 (0x0187)
FLL1_
Synchroniser_7
5:2
0
R393 (0x0189)
FLL1_Spread_
Spectrum
5:4
3:2
1:0
Label
FLL1_
SYNCCLK_
DIV[1:0]
Default
Description
00
FLL1 Synchronizer Clock Reference Divider
00 = 1
10 = 4
01 = 2
11 = 8
MCLK (or other input reference) must be divided down to 13.5 MHz.
FLL1_
0000 FLL1 Synchronizer Clock source
SYNCCLK_SRC
0000 = MCLK1
1001 = AIF2BCLK
1101 = AIF2LRCLK
0001 = MCLK2
1010 = AIF3BCLK
1110 = AIF3LRCLK
1000 = AIF1BCLK
1100 = AIF1LRCLK
All other codes are reserved
FLL1_SYNC_
0000 FLL1 Synchronizer Gain
GAIN[3:0]
0000 = 1
0011 = 8
0110 = 64
0001 = 2
0100 = 16
0111 = 128
0010 = 4
0101 = 32
1000–1111 = 256
FLL1_SYNC_
1
FLL1 Synchronizer Bandwidth
DFSAT
0 = Wide bandwidth
1 = Narrow bandwidth
FLL1_SS_
00
FLL1 Spread Spectrum Amplitude. Controls the extent of the spread-spectrum
AMPL[1:0]
modulation.
00 = 0.7% (triangle), 0.7% (ZMFM, dither) 10 = 2.3% (triangle), 2.6% (ZMFM, dither)
01 = 1.1% (triangle), 1.3% (ZMFM, dither) 11 = 4.6% (triangle), 5.2% (ZMFM, dither)
FLL1_SS_
00
FLL1 Spread Spectrum Frequency. Controls the spread spectrum modulation
FREQ[1:0]
frequency in Triangle Mode.
00 = 439 kHz
10 = 1.17 MHz
01 = 878 kHz
11 = 1.76 MHz
FLL1_SS_
00
FLL1 Spread Spectrum Select.
SEL[1:0]
00 = Disabled
10 = Triangle
01 = Zero Mean Frequency (ZMFM)
11 = Dither
4.13.8.10FLL Interrupts and GPIO Output
The CS47L15 provides an FLL lock signal, which indicates whether FLL lock has been achieved (i.e., the FLL is locked to
the input reference signal).
The FLL lock signal is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.12.
The FLL lock signal can be output directly on a GPIO pin as an external indication of the FLL status. See Section 4.11 to
configure a GPIO pin for these functions.
Clock output signals derived from the FLL can be output on a GPIO pin. See Section 4.11 to configure a GPIO pin for this
function.
The FLL clocking configuration is shown in Fig. 4-65.
4.13.8.11Example FLL Calculation
The following example illustrates how to derive the FLL1 register fields to generate an oscillator frequency (FVCO) of
98.304 MHz from a 12.000-MHz reference clock (FREF). This is suitable for generating SYSCLK at 98.304 MHz and/or
DSPCLK at 147.456 MHz.
1. Set FLL1_REFCLK_DIV to generate FREF  13.5 MHz:
FLL1_REFCLK_DIV = 00 (divide by 1)
2. Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO × FREF). Assume FLL1_FRATIO = 0x0 (divide by 1).
N.K = 98304000 / (1 × 12000000) = 8.192
3. Confirm that the calculated value of N is less than 1024.
4. Determine FLL1_N from the integer portion of N.K:
FLL1_N = 8 (0x008)
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5. Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO × FREF, FVCO):
GCD(FLL) = GCD(1 × 12000000, 98304000) = 96000
6. Determine FLL1_THETA, as given by FLL1_THETA = (FVCO – (FLL1_N × FLL1_FRATIO × FREF)) / GCD(FLL):
FLL1_THETA = ((98304000) – (8 × 1 × 12000000)) / 96000
FLL1_THETA = 24 (0x0018)
7. Determine FLL1_LAMBDA, as given by FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL):
FLL1_LAMBDA = (1 × 12000000) / 96000
FLL1_LAMBDA = 125 (0x007D)
8. Determine FLL1_GAIN and FLL1_PHASE_ENA as specified in Section 4.13.8.4:
FLL1_GAIN = 0x5
FLL1_PHASE_ENA = 1
4.13.8.12Example FLL Settings
Table 4-86 shows FLL settings for generating an oscillator frequency (FVCO) of 98.304 MHz from a variety of low- and
high-frequency reference inputs. This is suitable for generating SYSCLK at 98.304 MHz and/or DSPCLK at 147.456 MHz.
Table 4-86. Example FLL Settings
FSOURCE
32.000 kHz
32.768 kHz
48 kHz
128 kHz
512 kHz
1.536 MHz
3.072 MHz
11.2896 MHz
12.000 MHz
12.288 MHz
13.000 MHz
19.200 MHz
24 MHz
26 MHz
27 MHz
FVCO (MHz)1 FREF Divider2
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
FRATIO2
N.K 3
FLL1_N
FLL1_
THETA
FLL1_
LAMBDA
FLL1_
GAIN 4
4
3
3
1
1
1
1
1
1
1
1
1
1
1
1
768
1000
682.6667
768
192
64
32
8.7075
8.192
8
7.5618
10.24
8.192
7.5618
7.2818
0x300
0x3E8
0x2AA
0x300
0x0C0
0x040
0x020
0x008
0x008
0x008
0x007
0x00A
0x008
0x007
0x007
0x0000
0x0000
0x0002
0x0000
0x0000
0x0000
0x0000
0x0068
0x0018
0x0000
0x0391
0x0006
0x0018
0x0391
0x013D
0x0001
0x0001
0x0003
0x0001
0x0001
0x0001
0x0001
0x0093
0x007D
0x0001
0x0659
0x0019
0x007D
0x0659
0x0465
0x2
0x2
0x0
0x2
0x2
0x3
0x3
0x5
0x5
0x3
0x5
0x5
0x5
0x5
0x5
FLL1_
PHASE_
ENA 4
1
1
0
1
1
1
1
0
0
1
0
0
0
0
0
1.FVCO = (FSOURCE/FREF Divider) × N.K × FRATIO
2.See Table 4-85 for the coding of the FLL1_REFCLK_DIV and FLL1_FRATIO fields.
3.N.K values are represented in the FLL1_N, FLL1_THETA, and FLL1_LAMBDA fields.
4.Assumes the FLL synchronizer is disabled. If the FLL synchronizer is enabled, see Table 4-83 for required settings.
The FLL synchronizer, when used, is configured similarly to the FLL main loop, using the corresponding register fields.
Note that the recommended FRATIO and GAIN settings on the FLL synchronizer circuit differ from those of the main
loop—the FLL1_SYNC_FRATIO, FLL1_GAIN and FLL1_SYNC_DFSAT fields are set as described in Table 4-84.
Note that the FLL1_SYNC_FRATIO coding differs from that of FLL1_FRATIO.
Table 4-87 shows FLL synchronizer settings for generating an oscillator frequency (FVCO) of 98.304 MHz from a variety
of low- and high-frequency reference inputs.
190
DS1137PP1
CS47L15
4.13 Clocking and Sample Rates
Table 4-87. Example FLL Synchronizer Settings
FSOURCE
32.000 kHz
32.768 kHz
48 kHz
128 kHz
512 kHz
1.536 MHz
3.072 MHz
11.2896 MHz
12.000 MHz
12.288 MHz
13.000 MHz
19.200 MHz
24 MHz
26 MHz
27 MHz
FVCO (MHz) 1 FREF Divider2
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
294.912
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
FRATIO2
N.K 3
FLL1_
SYNC_N
16
16
16
4
2
1
1
1
1
1
1
1
1
1
1
192
187.5
128
192
96
64
32
8.7075
8.192
8
7.5618
10.24
8.192
7.5618
7.2818
0x0C0
0x0BB
0x080
0x0C0
0x060
0x040
0x020
0x008
0x008
0x008
0x007
0x00A
0x008
0x007
0x007
FLL1_
SYNC_
THETA
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
0x0068
0x0018
0x0000
0x0391
0x0006
0x0018
0x0391
0x013D
FLL1_
SYNC_
LAMBDA
0x0001
0x0002
0x0001
0x0001
0x0001
0x0001
0x0001
0x0093
0x007D
0x0001
0x0659
0x0019
0x007D
0x0659
0x0465
FLL1_
SYNC_
GAIN
0x0
0x0
0x0
0x0
0x2
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x4
FLL1_
SYNC_
DFSAT
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1.FVCO = (FSOURCE/FREF Divider) × N.K × FRATIO
2.See Table 4-85 for the coding of the FLL1_REFCLK_DIV and FLL1_SYNC_FRATIO fields.
3.N.K values are represented in the FLL1_SYNC_N, FLL1_SYNC_THETA, and FLL1_SYNC_LAMBDA fields.
4.13.9 Frequency-Locked Loop (FLL_AO)
Two integrated FLLs are provided to support the clocking requirements of the CS47L15. These can be configured
according to the available reference clocks and the application requirements. The reference clock may use a high
frequency (e.g., 12.288 MHz) or low frequency (e.g., 32.768 kHz). The FLL is tolerant of jitter and may be used to generate
a stable output clock from a less stable input reference.
There are two FLL implementations on the CS47L15:
•
FLL1 provides an advanced capability to use more than one reference clock to achieve best performance. See
Section 4.13.8.
•
FLL_AO is low-power FLL that supports additional always-on capability to provide system clocking when other
references are unavailable or disabled. FLL_AO is described in the following subsections. Note that FLL_AO is
designed to support low-power always-on use cases only; for hi-fi audio use cases, it is recommended to use FLL1.
4.13.9.1 Overview
The FLL_AO characteristics are summarized in Table 3-11. In normal operation, the FLL output is frequency-locked to an
input clock reference. The FLL can also be used to generate a free-running clock in the absence of any external reference,
as described in Section 4.13.9.5.
FLL_AO is a low-power FLL that can be configured as the source for SYSCLK or DSPCLK system clocks. It also supports
always-on functions—it can be used to provide clocking for the DSP core if DSPCLK is not enabled (e.g., for always-on
DSP applications). See Section 4.4.3.4 to configure FLL_AO for always-on DSP operation.
The default FLL_AO settings are configured to provide a 49.152-MHz output, without any input reference required. The
FLL_AO can be used in its default settings or can be reconfigured for different input/output frequencies. The FLL_AO
control registers must always hold valid settings—either enabled and locked to an input reference clock or configured in
FLL Hold Mode.
FLL_AO takes a constant and stable clock reference as its input. Under typical application conditions, a low-frequency
(e.g., 32.768 kHz) reference is used. FLL_AO is free running without any clock reference if the input signal is removed; it
can also initiate an output in the absence of any reference signal.
DS1137PP1
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CS47L15
4.13 Clocking and Sample Rates
4.13.9.2 FLL Enable
FLL_AO is enabled by setting FLL_AO_ENA. In normal operation, the FLL_AO output is frequency locked to the selected
input reference.
FLL_AO supports free-running operation in FLL Hold Mode, using the FLL_AO_HOLD bit described in Section 4.13.9.5.
If the FLL is enabled and FLL Hold Mode is selected, the configured output frequency is maintained without any input
reference required. Note that, once the FLL output has been established, FLL_AO always runs freely if the input reference
clock is stopped, regardless of the FLL_AO_HOLD bit.
To disable FLL_AO, FLL_AO_HOLD must be set before clearing FLL_AO_ENA. FLL_AO_HOLD must always be set if
the FLL is disabled; this holds the oscillator loop-configuration settings, in readiness for always-on system requirements.
FLL_AO_HOLD should remain set when enabling FLL_AO. If normal (input-reference locked) FLL operation is required,
FLL_AO_HOLD should be cleared after FLL_AO_ENA has been set.
When changing FLL_AO settings, FLL_AO_HOLD must be set before writing to the configuration registers. FLL_AO_
HOLD must not be cleared until after the new register values have been written. Note that, if the FLL is disabled, the FLL_
AO_HOLD bit must remain set until after FLL_AO_ENA has been set.
Under default conditions, FLL_AO is preconfigured to generate 49.152-MHz output, without any input reference required.
Setting FLL_AO_ENA without changing any other control bits enables this reference clock output, which may be selected
as SYSCLK or DSPCLK source, as shown in Fig. 4-63.
The FLL_AO configuration is shown in Fig. 4-66.
FLL_AO_ENA (FLL Enable)
MCLK1
MCLK2
FLL_AO loop control
AIFnBCLK,
AIFnLRCLK
FOUT (SYSCLK)
FLL_AO_REFCLK_SRC
Multiply by 2
FNCO (45 MHz ≤ FNCO ≤ 50 MHz)
FOUT (DSPCLK)
Multiply by 3
Divide by
FLL_AO _GPCLK _DIV
FOUT (GPIO)
Divide by 1, 2, … 127
Figure 4-66. FLL_AO Configuration
The procedure for configuring FLL_AO is described in the following subsections. The associated register control fields are
described in Table 4-88.
4.13.9.3 Input Frequency Control
The main input reference is selected using FLL_AO_REFCLK_SRC. The available options in each case are MCLK1,
MCLK2, AIFnBCLK, or AIFnLRCLK.
The FLL_AO reference clock provides input to the interrupt control circuit and can be used to trigger an interrupt event
when the input reference is stopped; see Section 4.12.
192
DS1137PP1
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4.13 Clocking and Sample Rates
4.13.9.4 Output Frequency Control
If FLL_AO is selected as SYSCLK source, the associated multiplexer can select the FLL_AO oscillator frequency (equal
to FNCO) or a multiplied frequency (equal to FNCO x 2). For hi-fi audio use, FNCO must be exactly 49.152 MHz for
48 kHz–related sample rates or 45.1584 MHz for 44.1 kHz–related sample rates.
If FLL_AO is selected as DSPCLK source, the associated multiplexer can select the basic frequency (equal to FNCO) or a
multiplied frequency (equal to FNCO x 3). Note that the DSPCLK can be divided to lower frequencies for clocking the DSP
core.
If FLL_AO is selected as a GPIO output, a programmable divider supports division ratios in the range 1 through 127,
enabling a wide range of GPIO clock output frequencies.
Note:
The chosen FNCO frequency can be used to support multiple outputs simultaneously (e.g., SYSCLK and
DSPCLK); each FLL clock output path is controlled by a separate divider function, as shown in Fig. 4-66.
4.13.9.5 FLL Hold Mode
FLL Hold Mode enables the FLL to generate a clock signal even if no external reference clock is available, such as when
the normal input reference has been interrupted during a standby or start-up period. FLL Hold Mode is selected by setting
FLL_AO_HOLD.
•
If the FLL is enabled and FLL Hold Mode is selected, the normal feedback mechanism of the FLL is halted and the
FLL oscillates independently of the external input references—the FLL output frequency remains unchanged if FLL
Hold Mode is enabled.
•
If the FLL is enabled and the input reference clock is stopped, the loop always runs freely, regardless of the FLL_
AO_HOLD setting. If FLL_AO_HOLD = 0, the FLL relocks to the input reference whenever it is available.
•
If the FLL is disabled and FLL Hold Mode is selected, the latest oscillator loop configuration is held for later use.
Note that this is the default condition of FLL_AO: preconfigured to generate 49.152-MHz output with no input
reference required.
Note:
For specified CS47L15 functionality, FLL_AO_HOLD must be set before disabling the FLL and must always be
set if the FLL is disabled.
4.13.9.6 FLL Control Registers
The FLL_AO control registers are described in Table 4-88.
Example settings for a variety of reference frequencies and output frequencies are shown in Section 4.13.9.8.
Table 4-88. FLL_AO Register Map
Register
Address
R465 (0x01D1)
FLL_AO_Control_
1
R470 (0x01D6)
FLL_AO_Control_
6
Bit
Label
Default
Description
FLL_AO Hold Mode Enable
0 = Disabled
1 = Enabled
The FLL feedback mechanism is halted in FLL Hold Mode, and the latest integrator
setting is maintained. This bit must always be set if FLL_AO is disabled.
FLL_AO Enable
0 = Disabled
1 = Enabled
FLL_AO Clock source
0000 = MCLK1
1001 = AIF2BCLK
1101 = AIF2LRCLK
0001 = MCLK2
1010 = AIF3BCLK
1110 = AIF3LRCLK
1000 = AIF1BCLK
1100 = AIF1LRCLK
All other codes are reserved
2
FLL_AO_HOLD
1
0
FLL_AO_ENA
0
3:0
FLL_AO_
REFCLK_
SRC[3:0]
0100
4.13.9.7 FLL Interrupts and GPIO Output
For each FLL, the CS47L15 provides an FLL lock signal, which indicates whether FLL lock has been achieved (i.e., the
FLL is locked to the input reference signal).
DS1137PP1
193
CS47L15
4.13 Clocking and Sample Rates
The FLL lock signals are inputs to the interrupt control circuit and can be used to trigger an interrupt event; see
Section 4.12.
The FLL lock signal can be output directly on a GPIO pin as an external indication of the FLL status. See Section 4.11 to
configure a GPIO pin for these functions.
Clock output signals derived from the FLL can be output on a GPIO pin. See Section 4.11 to configure a GPIO pin for this
function.
The FLL_AO configuration is shown in Fig. 4-66.
4.13.9.8 Example FLL Settings
Table 4-89 shows FLL settings for generating an oscillator frequency (FNCO) of 45.1854 MHz or 49.152 MHz from a variety
of low-frequency reference inputs.
Table 4-89. Example FLL_AO Settings
Input Reference
32.000 kHz
32.768 kHz
44.100 kHz
48.000 kHz
194
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Configuration Sequence—
45.1584 MHz output
Write 0x02C1 to address 0x01D2
Write 0x0003 to address 0x01D3
Write 0x0005 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0005 to address 0x01DD
Write 0x82C1 to address 0x01D2
Write 0x02B1 to address 0x01D2
Write 0x0001 to address 0x01D3
Write 0x0010 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0005 to address 0x01DD
Write 0x82B1 to address 0x01D2
Write 0x0200 to address 0x01D2
Write 0x0000 to address 0x01D3
Write 0x0001 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0085 to address 0x01DD
Write 0x8200 to address 0x01D2
Write 0x01D6 to address 0x01D2
Write 0x0002 to address 0x01D3
Write 0x0005 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0005 to address 0x01DD
Write 0x81D6 to address 0x01D2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Configuration Sequence—
49.152 MHz output
Write 0x0300 to address 0x01D2
Write 0x0000 to address 0x01D3
Write 0x0001 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0085 to address 0x01DD
Write 0x8300 to address 0x01D2
Write 0x02EE to address 0x01D2
Write 0x0000 to address 0x01D3
Write 0x0001 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0085 to address 0x01DD
Write 0x82EE to address 0x01D2
Write 0x022D to address 0x01D2
Write 0x0029 to address 0x01D3
Write 0x0093 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0005 to address 0x01DD
Write 0x822D to address 0x01D2
Write 0x0200 to address 0x01D2
Write 0x0000 to address 0x01D3
Write 0x0001 to address 0x01D4
Write 0x0002 to address 0x01D5
Write 0x8001 to address 0x01D6
Write 0x0004 to address 0x01D8
Write 0x0077 to address 0x01DA
Write 0x06D8 to address 0x01DC
Write 0x0085 to address 0x01DD
Write 0x8200 to address 0x01D2
DS1137PP1
CS47L15
4.14 Control Interface and Master-Boot Interface
Notes: For correct FLL_AO configuration, the register values must be written in the sequence shown. The sequence must
be executed in full, regardless of the previous contents of the respective registers.
The example FLL_AO settings assume MCLK2 is input source. The register 0x01D6 value should be amended,
if a different input source is used. See Table 4-88 for the applicable register field definitions.
To enable the FLL_AO output, the FLL_AO_HOLD and FLL_AO_ENA control bits must also be written. See
Section 4.13.9.2 for further details.
4.14 Control Interface and Master-Boot Interface
The CS47L15 supports a control interface for read/write access to its control registers. The control interface is a slave
interface and can be configured in 4-wire SPI or 2-wire I2C modes.
The CS47L15 also supports a master interface that can be used to download firmware and register-configuration data from
an external non-volatile memory (e.g., EEPROM or flash memory). This enables the device to self-boot to an
application-specific configuration and to be used independently of a host processor. The master interface operates in
4-wire SPI mode.
The control interface and master-boot interface selection is configured at power-up and following hardware reset,
according to the logic level applied to the MSTRBOOT, SPISCLK, and SPISS pins. This is described in Table 4-90.
If the master-boot function is selected, the SPI interface pins are assigned to the master-boot interface (for connection to
an external memory). In this case, the GPIO13 and GPIO14 pins support an I2C control interface—this is intended for
development purposes and can be used to provide register access for a debug tool if the master-boot function is selected.
The I2C control interface is enabled by default (if the master-boot function is selected); it can be disabled by clearing I2C_
DEBUG.
Note that, if the digital speaker (PDM) interface is required following the master-boot start-up configuration, the I2C control
interface on GPIO13/14 must be disabled. The external memory can be programmed to disable the I2C control interface.
Table 4-90. Control Interface and Master-Boot Interface Selection
MSTRBOOT
Logic 0
Logic 1
SPISCLK
Logic 0
SPISS
Logic 1
—
—
—
—
Control Interface Configuration
Master Boot Interface Configuration
Slave I2C:
—
• SDA—Data input/output
• SCLK—Interface clock input
Slave SPI:
—
• SPIMISO—Data output
• SPIMOSI—Data input
• SPISCLK—Interface clock input
• SPISS—Slave select input
Master SPI:
Slave I2C:
• SPIMISO—Data input
• GPIO13—Data input/output (SDA)
• SPIMOSI—Data output
• GPIO14—Interface clock input (SCLK)
Note: Slave I2C interface can be disabled (e.g., • SPISCLK—Interface clock output
to support SPKCLK/SPKTXDAT functions)
• SPISS—Slave select output
The control interface and master-boot interface configurations are illustrated in Fig. 4-67, Fig. 4-68, and Fig. 4-69.
DS1137PP1
195
CS47L15
4.14 Control Interface and Master-Boot Interface
CS47L15
SPISS
SPISCLK
SPIMOSI/SDA
SPIMISO/SCLK
MSTRBOOT
CS47L15
DBVDD
DGND
SDA
SCL
Processor
MSTRBOOT
DGND
Figure 4-67. I2C Slave Control Interface
SS
SCLK
MOSI
MISO
SPISS
SPISCLK
SPIMOSI/SDA
SPIMISO/SCLK
Processor
DGND
Figure 4-68. SPI Slave Control Interface
CS47L15
SPISS
SPISCLK
SPIMOSI/SDA
SPIMISO/SCLK
MSTRBOOT
SS
SCLK
MOSI
MISO
External
Memory
DBVDD
(or connect to the RESET signal)
see Section 4.14.3
SPKTXDAT/GPIO13
SPKCLK/GPIO14
SDA
SCL
Debug
Tool
Figure 4-69. I2C Slave and SPI Master Interfaces
The control interface function can be supported with or without system clocking—there is no requirement for SYSCLK, or
any other system clock, to be enabled when accessing the register map.
The CS47L15 executes a boot sequence following power-on reset, hardware reset, software reset, or wake-up from Sleep
Mode. Note that control register writes should not be attempted until the boot sequence has completed. See Section 4.19.1
for further details.
The CS47L15 provides an integrated pull-down resistor on the SPIMISO/SCLK pin. This provides a flexible capability for
interfacing with other devices. A pull-down resistor is also provided on the MSTRBOOT pin. The pull-downs are controlled
using the MISO_SCLK_PD and MSTRBOOT_PD bits, as described in Table 4-91.
Note:
196
When writing to the MISO_SCLK_PD bit, take care not to change other nonzero bits that are configured at the
same register address.
DS1137PP1
CS47L15
4.14 Control Interface and Master-Boot Interface
Table 4-91. Control Interface Pull-Down
Register Address
R8 (0x0008)
Ctrl_IF_CFG_1
Bit
7
Label
MISO_SCLK_PD
Default
0
R18 (0x0012)
Ctrl_IF_Pin_Cfg_1
10
I2C_DEBUG
1
R334 (0x014E)
Clock_Gen_Pad_Ctrl
9
MSTRBOOT_PD
1
Description
SPIMISO/SCLK Pull-Down Control
0 = Disabled
1 = Enabled
I2C Debug Interface Control
0 = Disabled
1 = Enabled
The I2C debug interface is supported on the
GPIO13/GPIO14 pins if master-boot is selected.
MSTRBOOT Pull-Down Control
0 = Disabled
1 = Enabled
A detailed description of the SPI and I2C control interface modes is provided in Section 4.14.3 and Section 4.14.3. The
master-boot interface function is described in Section 4.14.3.
4.14.1 Four-Wire (SPI) Control Interface
The SPI control interface mode uses the SS, SCLK, MOSI, and MISO pin functions, as described in Table 4-90.
In write operations (R/W = 0), the MOSI pin input is driven by the controlling device.
In read operations (R/W = 1), the MOSI pin is ignored following receipt of the valid register address.
If SS is asserted (Logic 0), the MISO output is actively driven when outputting data and is high impedance at other times.
If SS is not asserted, the MISO output is high impedance.
The high-impedance state of the MISO output allows the pin to be shared with other slaves. An internal pull-down resistor
can be enabled on the SPIMISO pin, as described in Table 4-91.
Data transfers in SPI mode must use the applicable SPI message format, according to the register address space that is
being accessed:
•
When accessing register addresses below R12288 (0x3000), the applicable SPI protocol comprises a 31-bit register
address and 16-bit data words.
•
When accessing register addresses from R12888 (0x3000) upwards, the applicable SPI protocol comprises a 31-bit
register address and 32-bit data words.
•
Note that, in all cases, the complete SPI message protocol also includes a read/write bit and a 16-bit padding phase
(see Fig. 4-70 and Fig. 4-71 below).
Continuous read and write modes enable multiple register operations to be scheduled faster than is possible with single
register operations. In these modes, the CS47L15 automatically increments the register address at the end of each data
word, for as long as SS is held low and SCLK is toggled. Successive data words can be input/output every 16 (or 32) clock
cycles (depending on the applicable register address space).
The SPI protocol is shown in Fig. 4-70 and Fig. 4-71. Note that 16-bit data words are shown, but the equivalent protocol
also applies to 32-bit data words.
Fig. 4-70 shows a single register write to a specified address.
SS
SCLK
MOSI
R/W A30 A29
A1
31-bit register address
A0
X
X
X
16-bit padding
X
B15 B14
B1
B0
16-bit data word
Figure 4-70. Control Interface SPI Register Write (16-Bit Data Words)
DS1137PP1
197
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4.14 Control Interface and Master-Boot Interface
Fig. 4-71 shows a single register read from a specified address.
SS
SCLK
MOSI
R/W A30 A29
A1
A0
X
X
X
X
X
X
B15 B14
MISO
31-bit register address
16-bit padding
X
X
B1
B0
16-bit data word
Figure 4-71. Control Interface SPI Register Read (16-Bit Data Words)
See Table 3-20 for a detailed timing specification of the SPI control interface.
4.14.2 Two-Wire (I2C) Control Interface
The I2C control interface mode uses the SCLK and SDA pin functions, as described in Table 4-90.
In I2C Mode, the CS47L15 is a slave device on the control interface; SCLK is a clock input, while SDA is a bidirectional
data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the CS47L15 transmits
Logic 1 by tristating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high
so that the Logic 1 can be recognized by the master.
In order to allow many devices to share a single two-wire control bus, every device on the bus has a unique 8-bit device
ID (this is not the same as the address of each register in the CS47L15).
The CS47L15 device ID is 0011_0100 (0x34). Note that the LSB of the device ID is the read/write bit; this bit is set to Logic
1 for read and Logic 0 for write.
The CS47L15 operates as a slave device only. The controller indicates the start of data transfer with a high-to-low
transition on SDA while SCLK remains high. This indicates that a device ID and subsequent address/data bytes follow.
The CS47L15 responds to the start condition and shifts in the next 8 bits on SDA (8-bit device ID, including read/write bit,
MSB first). If the device ID received matches the device ID of the CS47L15, the CS47L15 responds by pulling SDA low
on the next clock pulse (ACK). If the device ID is not recognized or the R/W bit is set incorrectly, the CS47L15 returns to
the idle condition and waits for a new start condition.
If the device ID matches the device ID of the CS47L15, the data transfer continues. The controller indicates the end of
data transfer with a low-to-high transition on SDA while SCLK remains high. After receiving a complete address and data
sequence the CS47L15 returns to the idle state and waits for another start condition. If a start or stop condition is detected
out of sequence at any point during data transfer (i.e., SDA changes while SCLK is high), the device returns to the idle
condition.
Data transfers in I2C mode must use the applicable I2C message format, according to the register address space that is
being accessed:
•
When accessing register addresses below R12288 (0x3000), the applicable I2C protocol comprises a 32-bit register
address and 16-bit data words.
•
When accessing register addresses from R12888 (0x3000) upwards, the applicable I2C protocol comprises a 32-bit
register address and 32-bit data words.
•
Note that, in all cases, the complete I2C message protocol also includes a device ID, a read/write bit, and other
signaling bits (see Fig. 4-72 and Fig. 4-73).
198
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4.14 Control Interface and Master-Boot Interface
The CS47L15 supports the following read and write operations:
•
Single write
•
Single read
•
Multiple write
•
Multiple read
Continuous (multiple) read and write modes allow register operations to be scheduled faster than is possible with single
register operations. In these modes, the CS47L15 automatically increments the register address after each data word.
Successive data words can be input/output every 2 (or 4) data bytes, depending on the applicable register address space.
The I2C protocol for a single, 16-bit register write operation is shown in Fig. 4-72.
SCLK
D7
SDA
D1
R/W
A 31
A25
A24
A23
A17
A16
A 15
device ID (Write) ACK register address A 31–A24 ACK register address A23 –A16 ACK
START
A1
A8
A7
register address A15– A8 ACK
A0
register address A7–A0
A9
B 15
ACK
B9
B8
B7
ACK
data bits B15 –B8
B1
B0
data bits B 7–B0
ACK
STOP
Note: The SDA pin is used as input for the control register address and data; SDA
is pulled low by the receiving device to provide the acknowledge(ACK) response
Figure 4-72. Control Interface I2C Register Write (16-Bit Data Words)
The I2C protocol for a single, 16-bit register read operation is shown in Fig. 4-73.
SCLK
D7
SDA
START
D1
R/W
A 31
A25
A24
A23
device ID (Write) ACK register address A 31–A24
A1
D7
ACK
A16
A 15
register address A23 –A16 ACK
A0
register address A7– A0
A17
Rpt
START
D1
R/W
device ID (Read) ACK
A9
A8
A7
register address A15– A8 ACK
B 15
B9
B8
data bits B15–B 8
B7
ACK
B1
data bits B7–B0
B0
ACK
STOP
Note: The SDA pin is driven by both the master and slave devices in turn
to transfer device address, register address, data and ACK responses
Figure 4-73. Control Interface I2C Register Read (16-Bit Data Words)
See Table 3-19 for a detailed timing specification of the I2C control interface.
The control interface also supports other register operations; the interface protocol for these operations is shown in
Fig. 4-74 through Fig. 4-77. The terminology used in the following figures is detailed in Table 4-92.
Note that 16-bit data words are shown in these illustrations. The equivalent protocol is also applicable to 32-bit words, with
4 data bytes transmitted (or received) instead of 2.
Table 4-92. Control Interface (I2C) Terminology
Terminology
S
Sr
A
A
DS1137PP1
Description
Start condition
Repeated start
Acknowledge (SDA low)
Not acknowledge (SDA high)
199
CS47L15
4.14 Control Interface and Master-Boot Interface
Table 4-92. Control Interface (I2C) Terminology (Cont.)
Terminology
P
Description
Stop condition
Read/not write
0 = Write; 1 = Read
Data flow from bus master to CS47L15
Data flow from CS47L15 to bus master
R/W
[White field]
[Gray field]
Fig. 4-74 shows a single register write to a specified address.
8-Bit Device ID
S
Device ID
8 bits
R/W A
(0)
8 bits
Address Byte [3]
A
8 bits
Address Byte [2]
A
8 bits
Address Byte [1]
A
(Most Significant Byte)
Address Byte [0]
(Least Significant Byte )
8 bits
A
8 bits
MSByte Data
A
LSByte Data
A
P
A
P
A
P
A
P
Figure 4-74. Single-Register Write to Specified Address
Fig. 4-75 shows a single register read from a specified address.
S
Device ID
R/W A
Address Byte [3]
A
Address Byte [2]
A
Address Byte [1]
A
(Most Significant Byte)
(0)
Address Byte [0]
(Least Significant Byte )
A
Sr
Device ID
R/W A
MSByte Data
A
LSByte Data
(1)
Figure 4-75. Single-Register Read from Specified Address
Fig. 4-76 shows a multiple register write to a specified address.
S
Device ID
R/W A
Address Byte [3]
A
Address Byte [2]
A
Address Byte [1]
A
Address Byte [0]
(0)
Written to Register Address
A
MSByte Data 0
A
Written to Register Address + 1
LSByte Data 0
A
MSByte Data 1
Written to Register Address + N - 1
A
MSByte Data N-1
A
A
LSByte Data 1
A
Written to Register Address + N
LSByte Data N-1
A
MSByte Data N
A
LSByte Data N
Figure 4-76. Multiple-Register Write to Specified Address
Fig. 4-77 shows a multiple register read from a specified address.
S
Device ID
R/W A
Address Byte [3]
A
Address Byte [2]
A
Address Byte [1]
A
Address Byte [0]
(0)
Read from Register Address
A
Sr
Device ID
R/W A
MSByte Data 0
A
LSByte Data 0
A
(1)
Read from Register Address + N - 1
A
MSByte Data N-1
A
LSByte Data N-1
Read from Register Address + N
A
MSByte Data N
A
LSByte Data N
Figure 4-77. Multiple-Register Read from Specified Address
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4.14 Control Interface and Master-Boot Interface
4.14.3 SPI Master-Boot Interface
The SPI master-boot interface mode uses the SS, SCLK, MOSI, and MISO pin functions, as described in Table 4-90. The
interface connects directly to an external non-volatile memory (e.g., EEPROM or flash memory), enabling the CS47L15 to
self-boot to an application-specific configuration and to be used independently of a host processor.
The SPI master-boot interface is selected using the MSTRBOOT pin—if a Logic 1 is detected on the MSTRBOOT pin
during device start-up, the CS47L15 downloads the firmware and register-configuration data over the SPI master interface.
This self-boot function is scheduled as part of power-on reset or hardware reset (assuming a Logic 1 is detected on the
MSTRBOOT pin).
Note that, if a Logic 1 is applied to the MSTRBOOT pin, the output pins of the SPI interface are actively driven—including
during reset. To allow programming of the external memory, the output pins of the SPI interface must be tristated by
applying a Logic 0 to the MSTRBOOT input. The CS47L15 should be held in reset during memory programming by
asserting the RESET input (Logic 0) as described in Section 4.19.2. It is recommended to connect the RESET and
MSTRBOOT pins as shown in Fig. 4-78.
CS47L15
SPISS
SPISCLK
SPIMOSI/SDA
SPIMISO/SCLK
SS
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
Programmer
External
Memory
MSTRBOOT
RESET
SPKTXDAT/GPIO13
SPKCLK/GPIO14
SDA
SCL
Debug
Tool
Figure 4-78. SPI Master-Boot Connections
The external memory data contents are compiled using a dedicated application-development tool. The compiled data
includes a boot header that contains identifier fields, interface timing parameters, CRC data, and other fields that describe
the associated data packets. The firmware and register-configuration data is contained within data packets; these may be
formatted in a number of different ways to optimize the overall file size and electrical/timing requirements. Please contact
your local Cirrus Logic representative for details of the external memory development tool.
The CS47L15 reads the external memory using SPI Mode 0 bus protocol. Two types of SPI read instruction are
supported—the standard read instruction is used by default; the fast read instruction is used if the external memory
contents are configured to enable this option.
Continuous read modes are used to enable multiple register operations to be scheduled faster than is possible with single
register operations. In these modes, the CS47L15 (and the external memory) automatically increment the register address
at the end of each data word, for as long as SS is held low and SCLK is toggled.
The standard read instruction is shown in Fig. 4-79.
DS1137PP1
201
CS47L15
4.15 Control-Write Sequencer
SS
SCLK
MOSI
MISO
Read command
byte (0x03)
Memory address bytes
(24 bits, MSB first)
N x 8-bit data words (MSB first)
Figure 4-79. SPI Master Standard Read Instruction
The fast read instruction is shown in Fig. 4-80.
SS
SCLK
MOSI
MISO
Read command
byte (0x0B)
Memory address bytes
(24 bits, MSB first)
8 bits padding
N x 8-bit data words (MSB first)
Figure 4-80. SPI Master Fast Read Instruction
See Table 3-21 for a detailed timing specification of the SPI master interface.
Refer to Section 5.1.9 for recommended external memory components.
4.15 Control-Write Sequencer
The control-write sequencer is a programmable unit that forms part of the CS47L15 control interface logic. It provides the
ability to perform a sequence of register-write operations with the minimum of demands on the host processor—the
sequence may be initiated by a single operation from the host processor and then left to execute independently.
Default sequences for pop-suppressed start-up and shutdown of each headphone/earpiece output driver are provided
(these are scheduled automatically when the respective output paths are enabled or disabled). Other control sequences
can be programmed, and may be associated with sample-rate detection, DRC, MICDET clamp, or event-logger status;
these sequences are automatically scheduled whenever a corresponding event is detected.
When a sequence is initiated, the sequencer performs a series of predefined register writes. The start index of a control
sequence within the sequencer’s memory may be commanded directly by the host processor. The applicable start index
for each of the sequences associated with sample-rate detection, DRC, or MICDET clamp, or event logger status is held
in a user-programmed control register.
The control-write sequencer may be triggered by a number of different events. Multiple sequences are queued if
necessary, and each is scheduled in turn.
The control-write sequencer can be supported with or without system clocking—there is no requirement for SYSCLK or for
any other system clock to be enabled when using the control-write sequencer. The timing accuracy of the sequencer
operation is improved when SYSCLK is present, but the general functionality is supported with or without SYSCLK.
4.15.1 Initiating a Sequence
The fields associated with running the control-write sequencer are described in Table 4-93.
The CS47L15 provides 16 general-purpose trigger bits for the write sequencer to allow easy triggering of the associated
control sequences. Writing 1 to the trigger bit initiates a control sequence, starting at the respective index position within
the control-write sequencer memory.
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4.15 Control-Write Sequencer
The WSEQ_TRG1_INDEX field defines the sequencer start index corresponding to the WSEQ_TRG1 trigger control bit.
Equivalent start index fields are provided for each of the trigger control bits, as described in Table 4-93. Note that a
sequencer start index of 0x1FF causes the respective sequence to be aborted.
The general-purpose control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode
transition. The general-purpose control sequences must be reconfigured by the host processor following any of these
events. Note that all control sequences are maintained in the sequencer memory through software reset.
The write sequencer can also be commanded using control bits in register R22 (0x16). In this case, the write sequencer
is enabled using the WSEQ_ENA bit and the index location of the first command in the sequence is held in the WSEQ_
START_INDEX field. Writing 1 to the WSEQ_START bit commands the sequencer to execute a control sequence, starting
at the specified index position. Note that, if the sequencer is already running, the WSEQ_START command is queued and
executed when the sequencer becomes available.
Note:
The mechanism for queuing multiple sequence requests has limitations when the WSEQ_START bit is used to
trigger the write sequencer. If a sequence is initiated using the WSEQ_START bit, no other control sequences
should be triggered until the sequence completes. The WSEQ_BUSY bit (described in Table 4-99) provides an
indication of the sequencer status and can be used to confirm the sequence has completed.
Multiple control sequences triggered by any other method are queued if necessary, and scheduled in turn.
The write sequencer can be interrupted by writing 1 to the WSEQ_ABORT bit. Note that this command only aborts a
sequence that is currently running; if other sequence commands are pending and not yet started, these sequences are
not aborted by writing to the WSEQ_ABORT bit.
The write sequencer stores up to 252 register-write commands. These are defined in registers R12288 (0x3000) through
R12790 (0x31F6). See Table 4-100 for a description of these registers.
Table 4-93. Write Sequencer Control—Initiating a Sequence
Register Address
R22 (0x0016)
Write_Sequencer_
Ctrl_0
Bit
11
10
9
8:0
DS1137PP1
Label
Default
Description
WSEQ_ABORT
0
Writing 1 to this bit aborts the current sequence.
WSEQ_START
0
Writing 1 to this bit starts the write sequencer at the index location selected by WSEQ_
START_INDEX. At the end of the sequence, this bit is reset by the write sequencer.
WSEQ_ENA
0
Write Sequencer Enable
0 = Disabled
1 = Enabled
Only applies to sequences triggered using the WSEQ_START bit.
WSEQ_
0x000 Sequence Start Index. Contains the index location in the sequencer memory of the first
START_
command in the selected sequence.
INDEX[8:0]
Only applies to sequences triggered using the WSEQ_START bit.
Valid from 0 to 251 (0x0FB).
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CS47L15
4.15 Control-Write Sequencer
Table 4-93. Write Sequencer Control—Initiating a Sequence (Cont.)
Register Address
R66 (0x0042)
Spare_Triggers
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R75 (0x004B)
Spare_Sequence_
Select_1
R76 (0x004C)
Spare_Sequence_
Select_2
R77 (0x004D)
Spare_Sequence_
Select_3
R78 (0x004E)
Spare_Sequence_
Select_4
R79 (0x004F)
Spare_Sequence_
Select_5
R80 (0x0050)
Spare_Sequence_
Select_6
R89 (0x0059)
Spare_Sequence_
Select_7
R90 (0x005A)
Spare_Sequence_
Select_8
204
8:0
8:0
8:0
8:0
8:0
8:0
8:0
8:0
Label
Default
Description
WSEQ_TRG16
0
Write Sequence Trigger 16
Write 1 to trigger
WSEQ_TRG15
0
Write Sequence Trigger 15
Write 1 to trigger
WSEQ_TRG14
0
Write Sequence Trigger 14
Write 1 to trigger
WSEQ_TRG13
0
Write Sequence Trigger 13
Write 1 to trigger
WSEQ_TRG12
0
Write Sequence Trigger 12
Write 1 to trigger
WSEQ_TRG11
0
Write Sequence Trigger 11
Write 1 to trigger
WSEQ_TRG10
0
Write Sequence Trigger 10
Write 1 to trigger
WSEQ_TRG9
0
Write Sequence Trigger 9
Write 1 to trigger
WSEQ_TRG8
0
Write Sequence Trigger 8
Write 1 to trigger
WSEQ_TRG7
0
Write Sequence Trigger 7
Write 1 to trigger
WSEQ_TRG6
0
Write Sequence Trigger 6
Write 1 to trigger
WSEQ_TRG5
0
Write Sequence Trigger 5
Write 1 to trigger
WSEQ_TRG4
0
Write Sequence Trigger 4
Write 1 to trigger
WSEQ_TRG3
0
Write Sequence Trigger 3
Write 1 to trigger
WSEQ_TRG2
0
Write Sequence Trigger 2
Write 1 to trigger
WSEQ_TRG1
0
Write Sequence Trigger 1
Write 1 to trigger
WSEQ_TRG1_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG1 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG2_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG2 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG3_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG3 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG4_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG4 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG5_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG5 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG6_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG6 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG7_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG7 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_TRG8_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG8 trigger.
Valid from 0 to 251 (0x0FB).
DS1137PP1
CS47L15
4.15 Control-Write Sequencer
Table 4-93. Write Sequencer Control—Initiating a Sequence (Cont.)
Register Address
R91 (0x005B)
Spare_Sequence_
Select_9
R92 (0x005C)
Spare_Sequence_
Select_10
Bit
8:0
R93 (0x005D)
Spare_Sequence_
Select_11
8:0
R94 (0x005E)
Spare_Sequence_
Select_12
8:0
R104 (0x0068)
Spare_Sequence_
Select_13
8:0
R105 (0x0069)
Spare_Sequence_
Select_14
8:0
R106 (0x006A)
Spare_Sequence_
Select_15
8:0
R107 (0x006B)
Spare_Sequence_
Select_16
8:0
8:0
Label
Default
Description
WSEQ_TRG9_ 0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
INDEX[8:0]
memory of the first command in the sequence associated with the WSEQ_TRG9 trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG10_
memory of the first command in the sequence associated with the WSEQ_TRG10
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG11_
memory of the first command in the sequence associated with the WSEQ_TRG11
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG12_
memory of the first command in the sequence associated with the WSEQ_TRG12
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG13_
memory of the first command in the sequence associated with the WSEQ_TRG13
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG14_
memory of the first command in the sequence associated with the WSEQ_TRG14
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG15_
memory of the first command in the sequence associated with the WSEQ_TRG15
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
WSEQ_
0x1FF Write Sequence trigger 1 start index. Contains the index location in the sequencer
TRG16_
memory of the first command in the sequence associated with the WSEQ_TRG16
INDEX[8:0]
trigger.
Valid from 0 to 251 (0x0FB).
4.15.2 Automatic Sample-Rate Detection Sequences
The CS47L15 supports automatic sample-rate detection on the digital audio interfaces (AIF1–AIF3) when operating in AIF
Slave Mode. Automatic sample-rate detection is enabled by setting RATE_EST_ENA—see Table 4-82.
As many as four audio sample rates can be configured for automatic detection; these sample rates are selected using the
SAMPLE_RATE_DETECT_n fields. If a selected audio sample rate is detected, the control-write sequencer is triggered.
The applicable start index location within the sequencer memory is separately configurable for each detected sample rate.
The WSEQ_SAMPLE_RATE_DETECT_A_INDEX field defines the sequencer start index corresponding to the SAMPLE_
RATE_DETECT_A sample rate. Equivalent start index fields are defined for the other sample rates, as described in
Table 4-94.
Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.
The automatic sample-rate detection control sequences are undefined following power-on reset, a hardware reset, or a
Sleep Mode transition. The automatic sample-rate detection control sequences must be reconfigured by the host
processor following any of these events. Note that all control sequences are maintained in the sequencer memory through
software reset.
See Section 4.13 for further details of the automatic sample-rate detection function.
DS1137PP1
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4.15 Control-Write Sequencer
Table 4-94. Write Sequence Control—Automatic Sample-Rate Detection
Register Address
R97 (0x0061)
Sample_Rate_
Sequence_Select_1
Bit
8:0
R98 (0x0062)
Sample_Rate_
Sequence_Select_2
8:0
R99 (0x0063)
Sample_Rate_
Sequence_Select_3
8:0
R100 (0x0064)
Sample_Rate_
Sequence_Select_4
8:0
Label
Default
Description
WSEQ_SAMPLE_ 0x1FF Sample Rate A Write Sequence start index. Contains the index location in the
RATE_DETECT_
sequencer memory of the first command in the sequence associated with Sample
A_INDEX[8:0]
Rate A detection.
Valid from 0 to 251 (0x0FB).
WSEQ_SAMPLE_ 0x1FF Sample Rate B Write Sequence start index. Contains the index location in the
RATE_DETECT_
sequencer memory of the first command in the sequence associated with Sample
B_INDEX[8:0]
Rate B detection.
Valid from 0 to 251 (0x0FB).
WSEQ_SAMPLE_ 0x1FF Sample Rate C Write Sequence start index. Contains the index location in the
RATE_DETECT_
sequencer memory of the first command in the sequence associated with Sample
C_INDEX[8:0]
Rate C detection.
Valid from 0 to 251 (0x0FB).
WSEQ_SAMPLE_ 0x1FF Sample Rate D Write Sequence start index. Contains the index location in the
RATE_DETECT_
sequencer memory of the first command in the sequence associated with Sample
D_INDEX[8:0]
Rate D detection.
Valid from 0 to 251 (0x0FB).
4.15.3 DRC Signal-Detect Sequences
The DRC function within the CS47L15 digital core provides a configurable signal-detect function. This allows the signal
level at the DRC input to be monitored and used to trigger other events.
The DRC signal-detect functions are enabled and configured using the fields described in Table 4-16 and Table 4-17 for
DRC1 and DRC2 respectively.
A control-write sequence can be associated with a rising edge and/or a falling edge of the DRC1 signal-detect output. This
is enabled by setting DRC1_WSEQ_SIG_DET_ENA, as described in Table 4-16.
Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available
on DRC1 only.
When the DRC signal-detect sequence is enabled, the control-write sequencer is triggered whenever the DRC1
signal-detect output transitions (high or low). The applicable start index location within the sequencer memory is separately
configurable for each logic condition.
The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX field defines the sequencer start index corresponding to a DRC1
signal-detect rising edge event, as described in Table 4-95. The WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX field
defines the sequencer start index corresponding to a DRC1 signal-detect falling edge event.
Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.
The DRC signal-detect sequences cannot be independently enabled for rising and falling edges. Instead, a start index of
0x1FF can be used to disable the sequence for either edge, if required.
The DRC signal-detect control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode
transition. The DRC signal-detect control sequences must be reconfigured by the host processor following any of these
events. Note that all control sequences are maintained in the sequencer memory through software reset.
See Section 4.3.5 for further details of the DRC function.
Table 4-95. Write Sequencer Control—DRC Signal-Detect
Register Address Bit
Label
R110 (0x006E)
8:0 WSEQ_DRC1_
SIG_DET_RISE_
Trigger_
INDEX[8:0]
Sequence_
Select_32
R111 (0x006F)
8:0 WSEQ_DRC1_
SIG_DET_FALL_
Trigger_
INDEX[8:0]
Sequence_
Select_33
206
Default
Description
0x1FF DRC1 Signal-Detect (Rising) Write Sequence start index. Contains the index location in
the sequencer memory of the first command in the sequence associated with DRC1
Signal-Detect (Rising) detection.
Valid from 0 to 251 (0x0FB).
0x1FF DRC1 Signal-Detect (Falling) Write Sequence start index. Contains the index location in
the sequencer memory of the first command in the sequence associated with DRC1
Signal-Detect (Falling) detection.
Valid from 0 to 251 (0x0FB).
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4.15 Control-Write Sequencer
4.15.4 MICDET Clamp Sequences
The CS47L15 supports external accessory detection functions, including the MICDET clamp circuit. The MICDET clamp
status can be used to trigger the control-write sequencer. The MICDET clamp is controlled by the JD1 and/or JD2 signals,
as described in Table 4-64.
A control-write sequence can be associated with a rising edge and/or a falling edge of the MICDET clamp status. This is
configured using the fields described in Table 4-64.
If one of the selected logic conditions is detected, the control-write sequencer is triggered. The applicable start index
location within the sequencer memory is separately configurable for the rising and falling edge conditions.
The WSEQ_MICD_CLAMP_RISE_INDEX field defines the sequencer start index corresponding to a MICDET clamp
rising edge (clamp active) event, as described in Table 4-96. The WSEQ_MICD_CLAMP_FALL_INDEX field defines the
sequencer start index corresponding to a MICDET clamp falling edge event.
Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.
The MICDET clamp control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode
transition. The MICDET clamp control sequences must be reconfigured by the host processor following any of these
events. Note that all control sequences are maintained in the sequencer memory through software reset.
See Section 4.9 for further details of the MICDET clamp status signals.
Table 4-96. Write Sequencer Control—MICDET Clamp
Register Address
R102 (0x0066)
Always_On_Triggers_
Sequence_Select_1
Bit
Label
8:0 WSEQ_MICD_
CLAMP_RISE_
INDEX[8:0]
R103 (0x0067)
Always_On_Triggers_
Sequence_Select_2
8:0 WSEQ_MICD_
CLAMP_FALL_
INDEX[8:0]
Default
Description
0x1FF MICDET Clamp (Rising) Write Sequence start index. Contains the index location in
the sequencer memory of the first command in the sequence associated with
MICDET clamp (Rising) detection.
Valid from 0 to 251 (0x0FB).
0x1FF MICDET Clamp (Falling) Write Sequence start index. Contains the index location in
the sequencer memory of the first command in the sequence associated with
MICDET clamp (Falling) detection.
Valid from 0 to 251 (0x0FB).
4.15.5 Event Logger Sequences
The CS47L15 provides two event log functions, for monitoring and recording internal or external signals. The logged
events are held in a FIFO buffer, from which the application software can read details of the detected logic transitions.
The control-write sequencer is automatically triggered whenever the NOT_EMPTY status of the event log buffer is
asserted. A different control sequence may be configured for each of the event loggers.
The WSEQ_EVENTLOGn_INDEX field defines the sequencer start index corresponding to respective event logger (where
n is 1 or 2), as described in Table 4-97.
Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.
The event logger control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode transition.
The event logger control sequences must be reconfigured by the host processor following any of these events. Note that
all control sequences are maintained in the sequencer memory through software reset.
See Section 4.5.1 for further details of the event loggers.
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Table 4-97. Write Sequencer Control—Event Loggers
Register Address Bit
Label
R120 (0x0078)
8:0 WSEQ_
EVENTLOG1_
Eventlog_
INDEX[8:0]
Sequence_
Select_1
R121 (0x0079)
8:0 WSEQ_
EVENTLOG2_
Eventlog_
INDEX[8:0]
Sequence_
Select_2
Default
Description
0x1FF Event Log 1 Write Sequence start index. Contains the index location in the sequencer
memory of the first command in the sequence associated with Event Log 1 FIFO
Not-Empty detection.
Valid from 0 to 251 (0x0FB).
0x1FF Event Log 2 Write Sequence start index. Contains the index location in the sequencer
memory of the first command in the sequence associated with Event Log 2 FIFO
Not-Empty detection.
Valid from 0 to 251 (0x0FB).
4.15.6 Boot Sequence
The CS47L15 executes a boot sequence following power-on reset, hardware reset, software reset, or wake-up from Sleep
Mode. The boot sequence configures the CS47L15 with factory-set trim (calibration) data. See Section 4.19.5 for further
details.
The start index location of the boot sequence is 224 (0x0E0). See Table 4-102 for details of the write sequencer memory
allocation.
The boot sequence can be commanded at any time by writing 1 to the WSEQ_BOOT_START bit.
Table 4-98. Write Sequencer Control—Boot Sequence
Register Address
R24 (0x0018)
Write_Sequencer_
Ctrl_2
Bit
1
Label
WSEQ_BOOT_
START
Default
0
Description
Writing 1 to this bit starts the write sequencer at the index location configured for
the Boot Sequence.
The Boot Sequence start index is 224 (0x0E0).
4.15.7 Sequencer Status Indication
The status of the write sequencer can be read using WSEQ_BUSY and WSEQ_CURRENT_INDEX, as described in
Table 4-99. When the WSEQ_BUSY bit is asserted, this indicates that the write sequencer is busy.
The index address of the most recent write sequencer command can be read from the WSEQ_CURRENT_INDEX field.
This can be used to provide a precise indication of the write sequencer progress.
Table 4-99. Write Sequencer Control—Status Indication
Register Address Bit
Label
R23 (0x0017)
9 WSEQ_BUSY
Write_Sequencer_
(read only)
Ctrl_1
8:0 WSEQ_CURRENT_
INDEX[8:0]
(read only)
Default
Description
0
Sequencer Busy flag (Read Only).
0 = Sequencer idle
1 = Sequencer busy
0x000 Sequence Current Index. This indicates the memory location of the most recently
accessed command in the write sequencer memory.
Coding is the same as WSEQ_START_INDEX.
4.15.8 Programming a Sequence
A control-write sequence comprises a series of write operations to data bits within the control register map. Standard write
operations are defined by 5 fields, contained within a single 32-bit register. An extended instruction set is also defined; the
associated actions makes use of alternate definitions of the 32-bit registers.
The sequencer instruction fields are replicated 252 times, defining each of the sequencer’s 252 possible index addresses.
Many sequences can be stored in the sequencer memory at the same time, with each assigned a unique range of index
addresses. The WSEQ_DELAYn field is used to identify the end-of-sequence position, as described below.
The general definition of the sequencer instruction fields is described as follows, where n denotes the sequencer index
address (valid from 0 to 251):
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•
WSEQ_DATA_WIDTHn is a 3-bit field that identifies the width of the data block to be written. Note that the maximum
value of this field selects a width of 8 bits; writes to fields that are larger than 8 bits wide must be performed using
two separate operations of the write sequencer.
•
WSEQ_ADDRn is a 12-bit field containing the register address in which the data should be written. The applicable
register address is referenced to the base address currently configured for the sequencer—it is calculated as: (base
address * 512) + WSEQ_ADDRn. Note that the base address is configured using the sequencer’s extended
instruction set.
•
WSEQ_DELAYn is a 4-bit field that controls the waiting time between the current step and the next step in the
sequence (i.e., the delay occurs after the write in which it was called). The total delay time per step (including
execution) is defined below, giving a useful range of execution/delay times from 3.3 s up to 1 s per step.
If WSEQ_DELAYn = 0x0 or 0xF, the step execution time is 3.3 s
For all other values, the step execution time is 61.44 s x ((2 WSEQ_DELAY) – 1)
Setting this field to 0xF identifies the step as the last in the sequence
•
WSEQ_DATA_STARTn is a 4-bit field that identifies the LSB position within the selected control register to which
the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 selects bit [4] as the LSB position
of the data to be written.
•
WSEQ_DATAn is an 8-bit field that contains the data to be written to the selected control register. The WSEQ_
DATA_WIDTHn field determines how many of these bits are written to the selected control register; the most
significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are ignored.
The extended instruction set for the write sequencer is accessed by setting WSEQ_MODEn (bit [28]) in the respective
sequencer definition register. The extended instruction set comprises the following functions:
•
If bits [31:24] = 0x11, the register base address is set equal to the value contained in bits [23:0].
•
If bits [31:16] = 0x12FF, the sequencer performs an unconditional jump to the index location defined in bits [15:0].
The index location is valid in the range 0 to 251 (0x0FB).
•
All other settings within the extended instruction set are reserved.
The control field definitions for Step 0 are described in Table 4-100. The equivalent definitions also apply to Step 1 through
Step 251, in the subsequent register address locations.
Table 4-100. Write Sequencer Control—Programming a Sequence
Register Address Bit
Label
R12288 (0x3000) 31:29 WSEQ_DATA_
WIDTH0[2:0]
WSEQ_
Sequence_1
Default
Description
000 Width of the data block written in this sequence step.
000 = 1 bit
011 = 4 bits
110 = 7 bits
001 = 2 bits
100 = 5 bits
111 = 8 bits
010 = 3 bits
101 = 6 bits
28 WSEQ_MODE0
0
Extended Sequencer Instruction select
0 = Basic instruction set
1 = Extended instruction set
27:16 WSEQ_ADDR0[11:0] 0x000 Control Register Address to be written to in this sequence step.
The register address is calculated as: (Base Address * 512) + WSEQ_ADDRn.
Base Address is 0x00_0000 by default, and is configured using the sequencer’s
extended instruction set.
15:12 WSEQ_DELAY0[3:0] 0000 Time delay after executing this step.
0x0 = 3.3 s
0x1 to 0xE = 61.44 s x ((2WSEQ_DELAY)–1)
0xF = End of sequence marker
11:8 WSEQ_DATA_
0000 Bit position of the LSB of the data block written in this sequence step.
START0[3:0]
0000 = Bit 0
…
1111 = Bit 15
7:0 WSEQ_DATA0[7:0]
0x00 Data to be written in this sequence step. When the data width is less than 8 bits,
one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that
unused bits be cleared.
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4.15.9 Sequencer Memory Definition
The write sequencer memory defines up to 252 write operations; these are indexed as 0 to 251 in the sequencer memory
map.
The write sequencer memory reverts to its default contents following power-on reset, a hardware reset, or a Sleep Mode
transition. In these cases, the sequence memory contains the boot sequence and the OUT1–OUT4 signal path enable/
disable sequences; the remainder of the sequence memory is undefined.
User-defined sequences can be programmed after power-up. The user-defined control sequences must be reconfigured
by the host processor following power-on reset, a hardware reset, or a Sleep Mode transition. Note that all control
sequences are maintained in the sequencer memory through software reset. See Section 5.2 for a summary of the
CS47L15 memory reset conditions.
The default control sequences can be overwritten in the sequencer memory, if required. Note that the headphone and
earpiece output path enable bits (HPnx_ENA, SPKOUTx_ENA) always trigger the write sequencer (at the predetermined
start index addresses).
Writing 1 to the WSEQ_LOAD_MEM bit clears the sequencer memory to the power-on reset state.
Table 4-101. Write Sequencer Control—Load Memory Control
Register Address
R24 (0x0018)
Write_Sequencer_Ctrl_2
Bit
0
Label
WSEQ_LOAD_
MEM
Default
0
Description
Writing 1 to this bit resets the sequencer memory to the power-on reset
state.
The sequencer memory is summarized in Table 4-102. User-defined sequences should be assigned space within the
allocated portion (user space) of the write sequencer memory.
The start index for the user-defined sequences is configured using the fields described in Table 4-93 through Table 4-97.
Table 4-102. Write Sequencer Memory Allocation
Description
Default Sequences
User Space
Boot Sequence
Sequence Index Range
0 to 155
156 to 223
224 to 251
4.16 Charge Pumps, Regulators, and Voltage Reference
The CS47L15 incorporates a charge-pump circuit to support the ground-referenced headphone/earpiece driver. It also
provides a MICBIAS generator (with three switchable outputs), which provide low noise reference voltages suitable for
biasing ECM-type microphones or powering digital microphones.
Refer to Section 5.1 for recommended external components.
4.16.1 Charge Pump (CP) Control
The charge pump (CP) circuit is used to generate the positive and negative supply rails for the analog output drivers. The
charge pump is enabled automatically by the CS47L15 when required. The charge pump circuit is shown in Fig. 4-81.
Note that decoupling capacitors and flyback capacitors are required for these circuits. Refer to Section 5.1 for
recommended external components.
4.16.2 Microphone Bias (MICBIAS) Control
A single MICBIAS generator is incorporated, which provides a low-noise reference suitable for biasing ECM-type
microphones or powering digital microphones. The MICBIAS generator is powered from MICVDD, as shown in Fig. 4-81.
Refer to Section 5.1.3 for recommended external components.
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Switchable outputs from the MICBIAS generator allows three separate reference/supply outputs to be independently
controlled. The MICBIAS regulator is enabled using the MICB1_ENA bit. The MICBIAS output switches are enabled using
MICB1A_ENA, MICB1B_ENA, and MICB1C_ENA.
Note that, to enable any of the MICBIAS1x outputs, the regulator and the respective output switch must both be enabled.
When a MICBIAS output is disabled, it can be configured to be floating or to be actively discharged. This is configured
using the MICB1x_DISCH bits (for each of the switched outputs), and the MICB1_DISCH bit (for the MICBIAS regulator).
Each discharge path is only effective when the respective output, or regulator, is disabled.
The MICBIAS generator can operate in Regulator Mode or in Bypass Mode. The applicable mode is selected using the
MICB1_BYPASS bit.
In Regulator Mode (MICB1_BYPASS = 0), the output voltage is selected using the MICB1_LVL field. In this mode,
MICVDD must be at least 200mV greater than the required MICBIAS output voltage. The MICBIAS outputs are powered
from the MICVDD pin and use the internal band-gap circuit as a reference.
In Regulator Mode, the MICBIAS regulator is designed to operate without external decoupling capacitors. The regulator
can be configured to support a capacitive load if required, using the MICB1_EXT_CAP bit. (This may be appropriate for a
DMIC supply.) It is important that the external capacitance is compatible with the MICB1_EXT_CAP setting. The
compatible load conditions are detailed in Table 3-11.
In Bypass Mode (MICB1_BYPASS = 1), the outputs (MICBIAS1x), when enabled, are connected directly to MICVDD. This
enables a low power operating state. Note that the MICB1_EXT_CAP setting is not applicable in Bypass Mode—there are
no restrictions on the external MICBIAS capacitance in Bypass Mode.
The MICBIAS generator incorporates a pop-free control circuit to ensure smooth transitions when the MICBIAS outputs
are enabled or disabled in Bypass Mode; this feature is enabled using the MICB1_RATE bit.
The MICBIAS generator is shown in Fig. 4-81. The MICBIAS control fields are described in Table 4-103.
The maximum output current for the MICBIAS regulator is noted in Table 3-11. This limit must be observed across all three
MICBIAS1x outputs, especially if more than one microphone is connected to the regulator simultaneously. Note that the
maximum output current differs between Regulator Mode and Bypass Mode.
4.16.3 Voltage-Reference Circuit
The CS47L15 incorporates a voltage-reference circuit, powered by AVDD. This circuit ensures the accuracy of the
MICBIAS voltage settings.
4.16.4 Block Diagram and Control Registers
The charge-pump and regulator circuits are shown in Fig. 4-81. Note that decoupling capacitors and flyback capacitors
are required for these circuits. Refer to Section 5.1 for recommended external components.
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CPVDD
CPC1A
CPC1B
CPC2A
CPC2B
CPVOUT1P
CPVOUT1N
CPVOUT2P
CPVOUT2N
4.16 Charge Pumps, Regulators, and Voltage Reference
Charge Pump
CPGND
Analog
Output
Supply
MICVDD
Analog
Input
Supply
MICB1_ENA
MICB1_BYPASS
MICB1_LVL[3:0]
MICB1_RATE
MICB1_DISCH
MICB1_EXT_CAP
Analog
Supply
AVDD
AGND
MICBIAS1A
MICB1A_ENA
MICB1A_DISCH
MICBIAS1B
MICB1B_ENA
MICB1B_DISCH
MICBIAS1C
AVDD
Voltage
Reference
Analog
Reference
MICB1C_ENA
MICB1C_DISCH
Figure 4-81. Charge Pumps and Regulators
The charge-pump and regulator control registers are described in Table 4-103.
Table 4-103. Charge-Pump and MICBIAS Control Registers
Register Address Bit
Label
Default
Description
R536 (0x0218)
15 MICB1_EXT_CAP
0
Microphone Bias 1 External Capacitor (when MICB1_BYPASS = 0).
Mic_Bias_Ctrl_1
Configures the MICBIAS1 regulator according to the specified capacitance connected
to the MICBIAS1x outputs.
0 = No external capacitor
1 = External capacitor connected
8:5 MICB1_LVL[3:0]
0x7 Microphone Bias 1 Voltage Control (when MICB1_BYPASS = 0)
0x0 = 1.5 V
… (0.1-V steps)
0xD to 0xF = 2.8 V
0x1 = 1.6 V
0xC = 2.7 V
3 MICB1_RATE
0
Microphone Bias 1 Rate (Bypass Mode)
0 = Fast start-up/shutdown
1 = Pop-free start-up/shutdown
2 MICB1_DISCH
1
Microphone Bias 1 Discharge
0 = MICBIAS1 floating when disabled
1 = MICBIAS1 discharged when disabled
1 MICB1_BYPASS
1
Microphone Bias 1 Mode
0 = Regulator Mode
1 = Bypass Mode
0 MICB1_ENA
0
Microphone Bias 1 Enable
0 = Disabled
1 = Enabled
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4.17 JTAG Interface
Table 4-103. Charge-Pump and MICBIAS Control Registers (Cont.)
Register Address Bit
Label
R540 (0x021C)
9 MICB1C_DISCH
Mic_Bias_Ctrl_5
8
MICB1C_ENA
5
MICB1B_DISCH
4
MICB1B_ENA
1
MICB1A_DISCH
0
MICB1A_ENA
Default
Description
1
Microphone Bias 1C Discharge
0 = MICBIAS1B floating when disabled
1 = MICBIAS1B discharged when disabled
0
Microphone Bias 1C Enable
0 = Disabled
1 = Enabled
1
Microphone Bias 1B Discharge
0 = MICBIAS1B floating when disabled
1 = MICBIAS1B discharged when disabled
0
Microphone Bias 1B Enable
0 = Disabled
1 = Enabled
1
Microphone Bias 1A Discharge
0 = MICBIAS1A floating when disabled
1 = MICBIAS1A discharged when disabled
0
Microphone Bias 1A Enable
0 = Disabled
1 = Enabled
4.17 JTAG Interface
The JTAG interface provides test and debug access to the CS47L15 DSP core. The interface comprises five connections
that are multiplexed with AIF2/AIF3 pins, as noted in Table 4-104.
Table 4-104. JTAG Interface Connections
Pin No
J14
G14
G8
G10
H13
Pin Name
AIF3BCLK/GPIO11
AIF2TXDAT/GPIO5
AIF3LRCLK/GPIO12
AIF3RXDAT/GPIO10
AIF3TXDAT/GPIO9
JTAG Function
TCK
TDI
TDO
TMS
TRST
JTAG Description
Clock input
Data input
Data output
Mode select input
Test access port reset input (active low)
The JTAG interface is selected by setting the DSP_JTAG_MODE bit. If the JTAG interface is selected, the AIF and GPIO
functions on the respective pins are disabled.
Note that, under default register conditions, DSP_JTAG_MODE is locked to prevent accidental selection—the user key
must be set before writing to DSP_JTAG_MODE. The user key is set by writing 0x5555, followed by 0xAAAA, to the
USER_KEY_CTRL field.
It is recommended to clear the user key after writing to DSP_JTAG_MODE. (Note that clearing the user key does not
change the value of DSP_JTAG_MODE.) The user key is cleared by writing 0xCCCC, followed by 0x3333, to USER_
KEY_CTRL.
For normal operation (test and debug access disabled), the JTAG interface should be disabled or held in reset. If DSP_
JTAG_MODE = 0, the JTAG interface is disabled. If DSP_JTAG_MODE = 1, the JTAG interface is held in reset if the
TRST pin is Logic 0. An internal pull-down resistor can be used to hold the TRST pin at Logic 0 (i.e., JTAG interface in
reset) when not actively driven.
Integrated pull-up and pull-down resistors can be enabled on each of the JTAG pins. This is provided as part of the GPIO
functionality, and provides a flexible capability for interfacing with other devices. The pull-up and pull-down resistors can
be configured independently using the fields described in Table 4-72.
If the JTAG interface is enabled (TRST deasserted and TCK active) at the time of any reset, a software reset must be
scheduled, with the TCK input stopped or TRST asserted (Logic 0), before using the JTAG interface.
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4.18 Thermal, Short-Circuit, and Timer-Controlled Protection
It is recommended to always schedule a software reset before starting the JTAG clock or deasserting the JTAG reset. In
this event, the JTAG interface should be held in its reset state until the software reset has completed, and the BOOT_
DONE_STSx bits have been set. See Section 4.19.3 for further details of the CS47L15 software reset.
The JTAG interface control registers are described in Table 4-105.
Table 4-105. JTAG Interface Control
Register Address
R140 (0x008C)
User_Key_Ctrl
Bit
15:0
Label
USER_KEY_
CTRL
Default
0x0000
R334 (0x014E)
Clock_Gen_Pad_Ctrl
11
DSP_JTAG_
MODE
0
Description
User Key Control
Write 0x5555, then 0xAAAA, to set the key. (Registers unlocked.)
Write 0xCCCC, then 0x3333, to clear the key. (Registers locked.)
DSP JTAG Mode Enable
0 = Disabled
1 = Enabled
Under default conditions, this bit is locked and cannot be written. To
change the value of this bit, the user key must be set before writing to
DSP_JTAG_MODE.
4.18 Thermal, Short-Circuit, and Timer-Controlled Protection
The CS47L15 incorporates thermal protection, short-circuit detection, and timer-controlled speaker disable functions;
these are described in the following subsections.
4.18.1 Thermal Shutdown
The temperature sensor detects when the device temperature is within normal limits or if the device is approaching a
hazardous temperature condition.
The temperature sensor is an input to the interrupt control circuit and can be used to trigger an interrupt event; see
Section 4.12. A two-stage indication is provided, via the SPK_OVERHEAT_WARN_EINTn and SPK_OVERHEAT_EINTn
interrupts.
If the upper temperature threshold (SPK_OVERHEAT_EINTn) is exceeded, the Class D speaker outputs are
automatically disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt,
SPK_SHUTDOWN_EINTn, is asserted.
4.18.2 Short Circuit Protection
The short-circuit detection function for the Class D speaker output is triggered when the respective output driver is enabled
(see Table 4-54). If a short circuit is detected at this time, the enable does not succeed, and the output driver is not
enabled.
The Class D speaker short-circuit detection provides inputs to the interrupt control circuit and can be used to trigger an
interrupt event; see Section 4.12. If the Class D speaker short-circuit condition is detected, the respective driver is
automatically disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt,
SPK_SHUTDOWN_EINTn, is asserted.
To enable the Class D speaker outputs following a short-circuit detection, the host processor must disable and reenable
the output drivers. Note that the short-circuit status bits are always cleared when the drivers are disabled.
The short-circuit detection function for the headphone and earpiece output paths operates continuously if the respective
output driver is enabled. If a short circuit is detected on the headphone or earpiece output, current limiting is applied to
protect the respective output driver. Note that the driver continues to operate, but the output is current-limited.
The headphone and earpiece short-circuit detection function provides input to the interrupt control circuit and can be used
to trigger an interrupt event when a short-circuit condition is detected; see Section 4.12.
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4.19 Power-Up, Resets, and Device ID
4.18.3 Timer-Controlled Speaker Shutdown
The general-purpose timers (see Section 4.5.2) can also be used to trigger a shutdown of the Class D speaker driver. This
is configured using the SPK_SHUTDOWN_TIMER_SEL field, as described in Table 4-106.
If one of the general-purpose timers is selected for the speaker shutdown function, and the respective timer reaches its
final count value, the Class D speaker driver is automatically disabled. When the driver shutdown is complete, an interrupt
event (SPK_SHUTDOWN_EINTn) is signaled.
To enable the Class D speaker output following a timeout condition, the host processor must disable and reenable the
output driver using the control bits described in Table 4-54.
Table 4-106. Speaker Shutdown—Timer Control
Register Address
R620 (0x026D)
SPK_Watchdog_1
Bit
3:0
Label
SPK_SHUTDOWN_
TIMER_SEL[3:0]
Default
0x0
Description
Speaker Shutdown Timer select.
0x0 = Disabled
0x1 = Timer 1
0x2 = Timer 2
All other codes are reserved
4.18.4 GPIO Output
The thermal status, Class D speaker short-circuit protection, and Class D speaker shutdown flags can be output directly
on a GPIO pin as an external indication of the associated events. See Section 4.11 to configure a GPIO pin for this
function.
4.19 Power-Up, Resets, and Device ID
The CS47L15 incorporates a power-on reset function to control the device start-up procedure. Hardware- and
software-controlled reset functions are also supported. The resets and the sleep/wake-up state transitions provide similar
functionality, and are described in the following subsections.
The CS47L15 device ID can be read from the Software_Reset (R0) control register, as described in Section 4.19.8.
4.19.1 Power-On Reset (POR)
The CS47L15 remains in the reset state until AVDD, DBVDD, and DCVDD are above their respective reset thresholds.
Note that specified device performance is not assured outside the voltage ranges defined in Table 3-3.
The POR sequence is scheduled on initial power-up, when AVDD, DBVDD, and DCVDD are above their respective reset
thresholds. After the initial power-up, the POR is also scheduled following an interrupt to the DBVDD or AVDD supplies.
4.19.2 Hardware Reset
The CS47L15 provides a hardware reset function, which is executed whenever the RESET input is asserted (Logic 0). The
RESET input is active low and is referenced to the DBVDD power domain. A hardware reset causes all of the CS47L15
control registers to be reset to their default states.
An internal pull-up resistor is enabled by default on the RESET pin; this can be configured using the RESET_PU bit. A
pull-down resistor is also available, as described in Table 4-107. When the pull-up and pull-down resistors are both
enabled, the CS47L15 provides a bus keeper function on the RESET pin. The bus keeper function holds the input logic
level unchanged whenever the external circuit removes the drive (e.g., if the signal is tristated).
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4.19 Power-Up, Resets, and Device ID
Table 4-107. Reset Pull-Up/Pull-Down Configuration
Register Address Bit
R6864 (0x1AD0)
AOD_Pad_Ctrl
Label
Default
Description
1 RESET_PU
1
RESET Pull-up enable
0 = Disabled
1 = Enabled
Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the
RESET pin.
0 RESET_PD
0
RESET Pull-down enable
0 = Disabled
1 = Enabled
Note: If RESET_PD and RESET_PU are both set, a bus keeper function is enabled on the
RESET pin.
4.19.3 Software Reset
A software reset is executed by writing any value to register R0. A software reset causes most of the CS47L15 control
registers to be reset to their default states. Note that the control-write sequencer memory is retained during software reset.
4.19.4 Wake-Up
The CS47L15 is in Sleep Mode when AVDD and DBVDD are present, and DCVDD is below its reset threshold. (Note that
specific control requirements are also applicable for entering Sleep Mode, as described in Section 4.10.)
In Sleep Mode, most of the digital core (and control registers) are held in reset; selected functions and control registers
are maintained via an always-on internal supply domain. See Section 4.10 for details of the always-on functions.
A wake-up transition (from Sleep Mode) is similar to a software reset, but selected functions and control registers are
maintained via an always-on internal supply domain—the always-on registers are not reset during wake-up. See
Section 4.10 for details of the always-on functions.
4.19.5 Boot Sequence
Following power-on reset, hardware reset, software reset, or wake-up from Sleep Mode, a boot sequence is executed.
The BOOT_DONE_STSx bits (see Table 4-109) are asserted on completion of the boot sequence. Control-register writes
should not be attempted until BOOT_DONE_STSx has been asserted. Note that the BOOT_DONE_STS1 and BOOT_
DONE_STS2 bits provide the same information.
The BOOT_DONE_STSx status is an input to the interrupt control circuit and can be used to trigger an interrupt event on
completion of the boot sequence; see Section 4.12. Under default register conditions, a falling edge on the IRQ pin
indicates completion of the boot sequence.
For details of the boot sequence, see Section 4.15.
An additional sequence of initialization settings must be written after the boot sequence has completed—this is specified
in Table 4-108. The host system should ensure the CS47L15 is ready (i.e., BOOT_DONE_STSx is set) before scheduling
these register operations.
Note:
216
If the master-boot function is selected (see Section 4.14), the initialization sequence must be incorporated within
the device configuration file on the external EEPROM.
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4.19 Power-Up, Resets, and Device ID
Table 4-108. CS47L15 Initialization Sequence
•
•
•
•
•
•
•
•
•
Control Register Writes
Write 0x5555 to address 0x008C
Write 0xAAAA to address 0x008C
Write 0x0080 to address 0x0314
Write 0x6023 to address 0x04A8
Write 0x6023 to address 0x04A9
Write 0x0008 to address 0x04D4
Write 0x0F00 to address 0x04CF
Write 0xCCCC to address 0x008C
Write 0x3333 to address 0x008C
If the master-boot function is selected, the IRQ pin is asserted (Logic 0) after the normal boot sequence has completed.
The subsequent behavior depends upon what event caused the boot sequence to occur:
•
If the boot sequence was scheduled due to a power-on reset or hardware reset, the CS47L15 downloads data from
the external EEPROM, and is configured according to the applicable user program data. Clearing the interrupt, and
the subsequent behavior of the IRQ output, is dependent on the user program data.
•
If the boot sequence was scheduled due to a software reset or wake-up from Sleep Mode, the CS47L15 does not
download data from the external EEPROM. Caution is advised if scheduling a software reset or wake-up transition
in master-boot applications.
The BOOT_DONE_STSx bits are defined in Table 4-109.
Table 4-109. Device Boot-Up Status
Register Address Bit
Label
R6272 (0x1880)
7 BOOT_DONE_
STS1
IRQ1_Raw_
Status_1
R6528 (0x1980)
IRQ2_Raw_
Status_1
7 BOOT_DONE_
STS2
Default
Description
0
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot Sequence has completed.
0
Boot Status
0 = Busy (boot sequence in progress)
1 = Idle (boot sequence completed)
Control register writes should not be attempted until Boot Sequence has completed.
4.19.6 Digital I/O Status in Reset
Table 1-1 describes the default status of the CS47L15 digital I/O pins on completion of power-on reset and before any
register writes. The same default conditions are also applicable on completion of a hardware reset or software reset.
The default conditions are also applicable following a wake-up transition, except for the IRQ and RESET pins—these are
always-on pins whose configuration is unchanged in Sleep Mode and during a wake-up transition.
Note that the default conditions described in Table 1-1 are not valid if modified by the boot sequence or by a wake-up
control sequence. See Section 4.15 for details of these functions.
4.19.7 Write Sequencer and DSP Firmware Memory Control in Reset and Wake-Up
The control-write sequencer memory reverts to its default state following power-on reset, a hardware reset, or a Sleep
Mode transition. The control sequences (including any user-defined sequences) are maintained in the sequencer memory
through software reset.
The DSP firmware memory contents are cleared following power-on reset, a hardware reset, or a Sleep Mode transition.
The firmware memory contents are not affected by software reset, provided DCVDD is held above its reset threshold.
See Section 5.2 for a summary of the CS47L15 memory reset conditions.
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5 Applications
4.19.8 Device ID
The device ID can be read from Register R0. The hardware revision can be read from Register R1.
The software revision can be read from Register R2. The software revision code is incremented if software driver
compatibility or software feature support is changed.
Table 4-110. Device Reset and ID
Register Address Bit
Label
R0 (0x0000)
15:0 SW_RST_DEV_
ID[15:0]
Software_Reset
R1 (0x0001)
7:0 HW_
REVISION[7:0]
Hardware_
Revision
R2 (0x0002)
7:0 SW_
REVISION[7:0]
Software_Revision
Default
Description
0x6370 Writing to this register resets all registers to their default state.
Reading from this register indicates Device ID 0x6370.
—
Hardware Device revision. This field is incremented for every new revision of the
device.
—
Software Device revision. This field is incremented if software driver compatibility or
software feature support is changed.
5 Applications
5.1 Recommended External Components
This section provides information on the recommended external components for use with the CS47L15.
5.1.1
Analog Input Paths
The CS47L15 supports up to five analog audio input connections. Four analog inputs are multiplexed on the IN1 signal
path; a mono analog input is also supported on the IN2 signal path.
The IN1xP and IN1xN pins are biased to the internal DC reference, VREF. (Note that this reference voltage is present on
the VREFC pin.) A DC-blocking capacitor is required when connecting to these input pins. The choice of capacitor is
determined by the filter that is formed between that capacitor and the impedance of the input pin. The circuit is shown in
Fig. 5-1.
Fc =
VREF
Input
IN1xP
+
PGA
–
R
1
2  RC
Fc = High-pass 3 dB cut-off frequency
C
Figure 5-1. Audio Input Path DC-Blocking Capacitor (IN1x pins only)
In accordance with the CS47L15 input pin resistance (see Table 3-5), a 1-F capacitance gives good results in most
cases, with a 3-dB cut-off frequency around 13 Hz.
Ceramic capacitors are suitable, but take care to ensure the desired capacitance is maintained at the AVDD operating
voltage. Also, ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give rise to
electrical signals. This is particularly problematic for microphone input paths where a large signal gain is required.
A single capacitor is required for a single-ended line or microphone input connection. For a differential input connection,
a DC-blocking capacitor is required on both input pins. The external connections for single-ended and differential
microphones, incorporating the CS47L15 microphone bias circuit, are shown in Fig. 5-2.
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The IN2P and IN2N pins support ground-referenced input signals only. Input capacitors must not be used on the IN2x pins.
5.1.2
Digital Input Paths
The CS47L15 supports up to four channels of digital input. Two channels of audio data can be multiplexed on the
DMICDAT pin and a further two channels can be multiplexed on the SPKRXDAT pin.
The external connections for digital microphones, incorporating the CS47L15 microphone bias circuit, are shown in
Fig. 5-4. The data on the DMICDAT input pin is clocked using the DMICCLK signal. Ceramic decoupling capacitors for the
digital microphones may be required—refer to the specific recommendations for the application microphones.
If two microphones are connected to DMICDAT, the microphones must be configured to ensure that the left mic transmits
a data bit when DMICCLK is high, and the right mic transmits a data bit when DMICCLK is low. The CS47L15 samples
the DMIC data at the end of each DMICCLK phase. Each microphone must tristate its data output when the other
microphone is transmitting. An integrated pull-down resistor can be enabled on the DMICDAT pin if required.
The voltage reference for the DMICDAT/DMICCLK interface is selectable. It is important that the selected reference for
the CS47L15 interface is compatible with the applicable configuration of the external microphone.
Digital audio input is also supported on the SPKRXDAT pin; this digital input path forms the receive (RX) side of the digital
speaker (PDM) output interface. Two channels of audio data are multiplexed on the SPKRXDAT pin; the data on the
SPKRXDAT input pin is clocked using the SPKCLK signal. The voltage reference for the SPKCLK, SPKRXDAT, and
SPKTXDAT pins is DBVDD.
If two digital microphones are connected to the SPKRXDAT pin, each microphone must tristate its data output when the
other microphone is transmitting. Ceramic decoupling capacitors for the digital microphones may be required.
5.1.3
Microphone Bias Circuit
The CS47L15 is designed to interface easily with analog or digital microphones.
Each microphone requires a bias current (electret condenser microphones) or voltage supply (silicon microphones); these
can be provided by the MICBIAS regulator on the CS47L15. A single MICBIAS generator is available, with switchable
outputs allowing three separate reference/supply outputs to be independently controlled.
Note that the MICVDD pin can also be used (instead of MICBIAS1x) as a reference or power supply for external
microphones. The MICBIAS outputs are recommended, as these offer better noise performance and independent enable/
disable control.
Analog microphones may be connected in single-ended or differential configurations, as shown in Fig. 5-2. The differential
configuration provides better performance due to its rejection of common-mode noise; the single-ended method provides
a reduction in external component count.
A bias resistor is required when using an ECM. The bias resistor should be chosen according to the minimum operating
impedance of the microphone and MICBIAS voltage so that the maximum bias current of the CS47L15 is not exceeded.
A 2.2-k bias resistor is recommended; this provides compatibility with a wide range of microphone components.
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5.1 Recommended External Components
MICBIAS
MICBIAS
IN1xP
ECM
IN1xN
IN1xP
+
PGA
–
To ADC
+
PGA
–
ECM
IN1xN
To ADC
GND
VREF
VREF
GND
Figure 5-2. Single-Ended and Differential ECM Microphone Connections
Analog MEMS microphones can be connected to the CS47L15 as shown in Fig. 5-3. In this configuration, the MICBIAS
generators provide a low-noise supply for the microphones; a bias resistor is not required.
MICBIAS
MICBIAS
VDD
MEMS
Mic
IN1xP
IN1xP
OUT
GND
IN1xN
GND
VREF
+
PGA
–
To ADC
MEMS
Mic
VDD
OUT-P
OUT-N
GND
GND
IN1xN
+
PGA
–
To ADC
VREF
Figure 5-3. Single-Ended and Differential Analog MEMS Microphone Connections
DMIC connection to the CS47L15 is shown in Fig. 5-4. Note that ceramic decoupling capacitors at the DMIC power supply
pins may be required—refer to the specific recommendations for the application microphones.
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5.1 Recommended External Components
MICVDD or MICBIAS1x
DMICCLK
DMICDAT
VDD
VDD
CLK DATA
Digital Mic
CHAN
VDD
Digital
Microphone
Interface
The DMIC inputs are referenced to
MICVDD or MICBIAS1.
CLK DATA
Digital Mic
The supply for each digital microphone
should provide the same voltage as the
applicable reference.
CHAN
AGND
Figure 5-4. DMIC Connection
The MICBIAS generator can operate in Regulator Mode or in Bypass Mode. See Section 4.16 for details of the MICBIAS
generator.
In Regulator Mode, the MICBIAS regulator is designed to operate without external decoupling capacitors. The regulator
can be configured to support a capacitive load if required (e.g., for DMIC supply decoupling). The compatible load
conditions are detailed in Table 3-11.
If the capacitive load on the MICBIAS1x outputs exceeds the specified conditions for Regulator Mode (e.g., due to a
decoupling capacitor or long PCB trace), the MICBIAS generator must be configured in Bypass Mode.
The maximum output current for the MICBIAS regulator is noted in Table 3-11. This limit must be observed in respect of
all enabled MICBIAS1x outputs, especially if more than one microphone is connected. Note that the maximum output
current differs between Regulator Mode and Bypass Mode. The MICBIAS output voltage can be adjusted using register
control in Regulator Mode.
5.1.4
Headphone/Earpiece Driver Output Path
The CS47L15 provides a stereo headphone output driver and a mono (differential) earpiece output driver. Note that the
respective output signal path is common to both drivers; only one of these drivers may be enabled at any time. These
outputs are all ground referenced, allowing direct connection to the external loads. There is no requirement for
DC-blocking capacitors.
Under default register conditions, the headphone/earpiece output path is configured for stereo output on HPOUTL and
HPOUTR; this is ideal for stereo headphone loads. In Mono Mode, with the earpiece output driver selected, the output
path is configured for mono (differential) output on EPOUTP and EPOUTN; this is suitable for an earpiece or hearing coil
load.
The headphone output (HPOUTL, HPOUTR) incorporates a common-mode, or ground-loop, feedback path that provides
rejection of system-related ground noise. The feedback pin must be connected to ground for normal operation of the
headphone output.
The ground feedback path for HPOUTL and HPOUTR is selected using HP1_GND_SEL. Note that the selected pin should
be connected to GND as close as possible to the respective headphone jack ground pin, as shown in Fig. 5-5.
Note that the earpiece output (EPOUTP, EPOUTN) does not support common-mode feedback.
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5.1 Recommended External Components
It is recommended to ensure that the electrical characteristics of the PCB traces for each output pair are closely matched.
This is particularly important to matching the two traces of a differential (BTL) output.
Typical headphone and earpiece connections are shown in Fig. 5-5.
CS47L15
HPOUTL
HPOUTR
HPOUTFB1
HPOUTFB2
Ground feedback for HPOUT is supported on the
HPOUTFB1 and HPOUTFB2 pins. The applicable
feedback pin is configured using HP1_GND_SEL.
EPOUTP
EPOUTN
Earpiece
Figure 5-5. Headphone and Earpiece Connection
It is common for ESD diodes to be wired to pins that link to external connectors. This provides protection from potentially
harmful ESD effects. In a typical application, ESD diodes are recommended if the headphone path is used for external
headphone or line output.
The HPOUT outputs are ground-referenced, and the respective voltages may swing between +1.8V and –1.8V. The ESD
diode configuration must be carefully chosen.
The recommended ESD diode configuration for these ground-referenced outputs is shown in Fig. 5-6. The back-to-back
arrangement prevents clipping and distortion of the output signal.
Note that similar care is required when connecting the CS47L15 outputs to external circuits that provide input path ESD
protection; the configuration on those input circuits must be correctly designed to accommodate ground-referenced
signals.
CS47L15
HPOUTL
External Headphone/Line
Output Connection
HPOUTR
External Headphone/Line
Output Connection
ESD Protection Diodes
Figure 5-6. ESD Diode Configuration for External Output Connections
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5.1 Recommended External Components
5.1.5
Speaker-Driver Output Path
The CS47L15 incorporates a Class D speaker driver, offering high amplifier efficiency at large signal levels. As the Class D
output is a pulse-width modulated signal, the choice of speakers and tracking of signals is critical for ensuring good
performance and reducing EMI.
The efficiency of the speaker driver is affected by the series resistance between the CS47L15 and the speaker (e.g., PCB
track loss and inductor ESR) as shown in Fig. 5-7. This resistance should be as low as possible to maximize efficiency.
SPKVDD
Switching
Losses
Class D
output
SPKVDD/2
GND
Losses due to resistance between output driver and
speaker (e.g., inductor ESR). This resistance must be
minimised in order to maximise efficiency .
Figure 5-7. Speaker Connection Losses
The Class D output requires external filtering to recreate the audio signal. This may be implemented using a 2nd order LC
or 1st order RC filter, or else may be achieved by using a loudspeaker whose internal inductance provides the required
filter response. An LC or RC filter should be used if the loudspeaker characteristics are unknown or unsuitable, or if the
length of the loudspeaker connection is likely to lead to EMI problems.
In applications where it is necessary to provide Class D filter components, a second-order LC filter is the recommended
solution as it provides more attenuation at higher frequencies and minimizes power dissipated in the filter when compared
to a first order RC filter (lower ESR). This maximizes both rejection of unwanted switching frequencies and overall speaker
efficiency. A suitable implementation is shown in Fig. 5-8.
CS47L15
SPKOUTP
SPKOUTN
L = 22H
Fc =
1
2  LC
C = 3F
Fc = Low-pass 3 dB cut-off frequency
Figure 5-8. Class D Output Filter Components
A simple equivalent circuit of a loudspeaker consists of a series-connected resistor and inductor, as shown in Fig. 5-9.
This circuit provides a low-pass filter for the speaker output. If the loudspeaker characteristics are suitable, the
loudspeaker itself can be used in place of the filter components described earlier. This is known as filterless operation.
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5.1 Recommended External Components
Fc =
SPKOUTP
CS47L15
R
2L
L
R
Fc = Low-pass 3 dB cut-off frequency
SPKOUTN
Figure 5-9. Speaker Equivalent Circuit for Filterless Operation
For filterless Class D operation, it is important to ensure that a speaker with suitable inductance is chosen. For example,
if we know the speaker impedance is 8  and the desired cut-off frequency is 20 kHz, the optimum speaker inductance
may be calculated as shown in Eq. 5-1.
L
R
8
= ---------- = ------------------------ =
2Fc
2  20kHz
64H
Equation 5-1. Speaker Inductance Calculation
An 8- loudspeaker typically has an inductance in the range 20–100 H; however, it should be noted that a loudspeaker
inductance is not constant across the relevant frequencies for Class D operation (up to and beyond the Class D switching
frequency). Care should be taken to ensure that the cut-off frequency of the loudspeaker’s filtering is low enough to
suppress the high-frequency energy of the Class D switching and, in so doing, to prevent speaker damage. The Class D
outputs of the CS47L15 operate at much higher frequencies than is recommended for most speakers, and it must be
ensured that the cut-off frequency is low enough to protect the speaker.
The Class D speaker outputs are designed to support monitoring of external loudspeakers, giving real-time feedback for
algorithms such as Cirrus Logic’s speaker protection software. This enables maximum audio output to be achieved, while
ensuring the loudspeakers are also fully protected from damage.
The external speaker connections, incorporating the output current monitoring requirements, are shown in Fig. 5-10. Note
that, if output current monitoring is not required on one or more speaker channels, the respective ground connections
should be tied directly to ground on the PCB.
CS47L15
SPKOUTP
SPKOUTN
IN2P
IN2N
SPKGNDP
SPKGNDN
0.1
(1%, 100ppm/°C)
Figure 5-10. Speaker Output Current Monitoring Connections (Speaker Protection)
5.1.6
Power Supply/Reference Decoupling
Electrical coupling exists particularly in digital logic systems where switching in one subsystem causes fluctuations on the
power supply. This effect occurs because the inductance of the power supply acts in opposition to the changes in current
flow that are caused by the logic switching. The resultant variations (spikes) in the power-supply voltage can cause
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5.1 Recommended External Components
malfunctions and unintentional behavior in other components. A decoupling (bypass) capacitor can be used as an energy
storage component that provides power to the decoupled circuit for the duration of these power-supply variations,
protecting it from malfunctions that could otherwise arise.
Coupling also occurs in a lower frequency form when ripple is present on the power supply rail caused by changes in the
load current or by limitations of the power-supply regulation method. In audio components such as the CS47L15, these
variations can alter the performance of the signal path, leading to degradation in signal quality. A decoupling capacitor can
be used to filter these effects by presenting the ripple voltage with a low-impedance path that does not affect the circuit to
be decoupled.
These coupling effects are addressed by placing a capacitor between the supply rail and the corresponding ground
reference. In the case of systems comprising multiple power supply rails, decoupling should be provided on each rail.
PCB layout is also a contributory factor for coupling effects. If multiple power supply rails are connected to a single supply
source, it is recommended to provide separate PCB tracks connecting each rail to the supply. See Section 5.5 for
PCB-layout recommendations.
The recommended power-supply decoupling capacitors for CS47L15 are detailed in Table 5-1.
Table 5-1. Power Supply Decoupling Capacitors
Power Supply
AVDD
CPVDD
DBVDD
DCVDD
MICVDD
SPKVDD
VREFC
Decoupling Capacitor
1.0 F ceramic
4.7 F ceramic
0.1 F ceramic 1
2.2 F ceramic
1.0 F ceramic
4.7 F ceramic
2.2 F ceramic
1.Total capacitance of 4.7 F is required for the DBVDD domain. This can be provided
by dedicated DBVDD decoupling or by other capacitors on the same power rail.
All decoupling capacitors should be placed as close as possible to the CS47L15 device. The connection between AGND,
the AVDD decoupling capacitor, and the main system ground should be made at a single point as close as possible to the
AGND balls of the CS47L15.
Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the selected components
provide the required capacitance across the required temperature and voltage ranges in the intended application. Ceramic
capacitors with X5R dielectric are recommended.
5.1.7
Charge-Pump Components
The CS47L15 incorporates a charge-pump circuit that generates the CPVOUTnx supply rails for the headphone/earpiece
drivers. Decoupling capacitors are required on each of the charge-pump outputs. Two fly-back capacitors are also
required.
The recommended charge-pump capacitors for CS47L15 are detailed in Table 5-2.
Table 5-2. Charge-Pump External Capacitors
Description
CPVOUT1P decoupling
CPVOUT1N decoupling
CP fly-back 1
(connect between CPC1A and CPC1B)
CPVOUT2P decoupling
CPVOUT2N decoupling
CP fly-back 2
(connect between CPC2A and CPC2B)
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2.2 F ceramic
2.2 F ceramic
1.0 F ceramic
4.7 F ceramic
4.7 F ceramic
2.2 F ceramic
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CS47L15
5.1 Recommended External Components
Ceramic capacitors are recommended for these charge-pump requirements. Care must be taken to ensure that the
selected components provide the required capacitance across the required temperature and voltage ranges in the
intended application. Ceramic capacitors with X5R dielectric are recommended.
The positioning of the charge-pump capacitors is important. These capacitors (particularly the fly-back capacitors) must
be placed as close as possible to the CS47L15.
5.1.8
External Accessory Detection Components
The external accessory detection circuit measures jack insertion using the JACKDET1 and JACKDET2 pins. The insertion
switch status is detected using an internal pull-up resistor circuit on the respective pin. Note that the logic thresholds
associated with the two JACKDET differ from each other, as described in Table 3-11—this provides support for different
jack switch configurations.
Microphone detection and key-button press detection is supported using the MICDETn pins. The applicable pin should be
connected to one of the MICBIAS1x outputs, via a 2.2-k bias resistor, as described in Section 5.1.3. Note that, when
using the external accessory detection function, the MICBIAS1x resistor must be 2.2 k ±2%.
A recommended circuit configuration, including headphone output on HPOUT and microphone connections, is shown in
Fig. 5-11. See Section 5.1.1 for details of the DC-blocking microphone input capacitor selection.
The recommended external components and connections for microphone/push-button detection are shown in Fig. 5-11.
Note that, when using the microphone detect circuit, it is recommended to use the IN1BLP or IN1BRP analog microphone
input paths to ensure best immunity to electrical transients arising from the external accessory.
CS47L15
2.2 k(±2%)
MICBIAS1x
* IN1BLP, IN1BRP
C
MICDET1
HPOUTL
HPOUTR
HPOUTFB2
(jack insertion switch )
JACKDETn
* Note that the IN1Bxx analog mic
channels are recommended with the
external accessory detect function
Note: The illustrated circuit
assumes the jack insertion
switch contacts are closed
when the jack is inserted.
Figure 5-11. External Accessory Detection
The accessory detection circuit measures the impedance of an external load connected to one of the MICDET pins.
The microphone-detection circuit uses MICVDD, MICBIAS1A, MICBIAS1B, or MICBIAS1C as a reference. The applicable
source is configured using MICD1_BIAS_SRC.
The CS47L15 can detect the presence of a typical microphone and up to six push buttons, using the components shown
in Fig. 5-12. When the microphone detection circuit is enabled, each of the push buttons shown causes a different bit in
the MICD1_LVL field to be set.
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The choice of external resistor values must take into account the impedance of the microphone—the detected impedance
corresponds to the combined parallel resistance of the microphone and any asserted push button. The components shown
in Fig. 5-12 are examples only, assuming default impedance measurement ranges and a microphone impedance of 1 k
or higher.
The measured impedance is reported using the MICD1_STS and MICD1_LVL bits.
If no accessory or push button is detected, the MICD1_STS bit is cleared.
MICBIAS
If MICD1_STS = 1, one of the MICD1_LVL bits is set to indicate the measured
impedance.
The applicable MICD1_LVL bit for each push button is noted below.
2.2 k
(±2%)
Detection of the microphone alone (no push buttons closed) is indicated in
MICD1_LVL[8].
Analog Input
Rmic 1 k
MICD1_LVL[8] –
Microphone detect
R1 = 0 
4 x Push Buttons
MICD1_LVL[0]
R2 = 150 
MICD1_LVL[1]
R3 = 270 
MICD1_LVL[2]
MICD1_LVL[3]
R4 = 620 
C
MICDETn
HPOUTx
JACKDETn
Sense pin selected by
MICD1_SENSE_SEL
MICDETn
Microphone
Ground pin selected
by MICD1_GND_SEL
Figure 5-12. External Accessory Detect Components
5.1.9
External Memory Components
The CS47L15 supports a master interface that can be used to download firmware and register-configuration data from an
external non-volatile memory (e.g., EEPROM or flash memory). This enables the device to self-boot to an
application-specific configuration and to be used independently of a host processor.
Compatible external-memory devices should be selected to meet the following criteria:
•
Four-wire SPI interface (slave select, clock, data in, data out)
•
SPI Mode 0 bus protocol support
•
Memory size 500 kBit (minimum), 2–8 MBit (recommended)
•
SPI speed 6 MHz (minimum), 20–40 MHz (recommended)
•
Operating voltage compatible with DBVDD
The CS47L15 reads the external memory using the read instruction sequences illustrated in Fig. 4-79 and Fig. 4-80. As a
minimum requirement, the external memory must support the standard read instruction shown in Fig. 4-79.
The following memory devices are recommended for use with the CS47L15 master-boot function. These devices have
been chosen for compatibility with the CS47L15 master-boot function, and also for compatibility with the CS47L15
development tools. Please contact your local Cirrus Logic representative for details of the external memory development
tool.
•
Microchip Technology SST25WF080B (8 MBit, 40 MHz)
•
Winbound Electronics W25Q80BWSVIG (8 MBit, 80 MHz)
•
Atmel AT25DL161 (16 MBit, 100 MHz)
DS1137PP1
227
CS47L15
5.2 Resets Summary
5.2 Resets Summary
Table 5-3 summarizes of the CS47L15 registers and other programmable memory under different reset conditions. The
associated events and conditions are listed as follows:
•
A power-on reset occurs when AVDD or DBVDD is below its respective reset threshold. Note that DCVDD is also
required for initial start-up; subsequent interruption to DCVDD should only be permitted as part of a control
sequence for entering Sleep Mode.
•
A hardware reset occurs when the RESET input is asserted (Logic 0).
•
A software reset occurs when register R0 is written to.
•
Sleep Mode is selected when DCVDD is removed. Note that the AVDD and DBVDD supplies must be present
throughout the Sleep Mode duration.
Table 5-3. Memory Reset Summary
Reset Type
Power-on reset
Hardware reset
Software reset
Sleep Mode
Always-On Registers 1
Reset
Reset
Reset
Retained
Other Registers
Reset
Reset
Reset
Reset
Control-Write Sequencer Memory DSP Firmware Memory
Reset
Reset
Reset
Reset
Retained
Retained 2
Reset
Reset
1.See Section 4.10 for details of Sleep Mode and the always-on registers.
2.To retain the DSP firmware memory contents during software reset, it must be ensured that DCVDD is held above its reset threshold.
5.3 Output-Signal Drive-Strength Control
The CS47L15 supports configurable drive-strength control for the digital output pins. This can be used to assist
system-level integration and design considerations.
The drive-strength control bits are described in Table 5-4. Note that, in the case of bidirectional pins (e.g., GPIOn), the
drive-strength control bits are only applicable if the pin is configured as an output.
Table 5-4. Output Drive-Strength and Slew-Rate Control
Register Address Bit
Label
R5889 (0x1701)
12:11 GP1_DRV_
STR[1:0]
GPIO1_CTRL2
R5891 (0x1703)
GPIO2_CTRL2
R5893 (0x1705)
GPIO3_CTRL2
R5895 (0x1707)
GPIO4_CTRL2
R5897 (0x1709)
GPIO5_CTRL2
R5899 (0x170B)
GPIO6_CTRL2
R5901 (0x170D)
GPIO7_CTRL2
R5903 (0x170F)
GPIO8_CTRL2
R5905 (0x1711)
GPIO9_CTRL2
R5907 (0x1713)
GPIO10_CTRL2
R5909 (0x1715)
GPIO11_CTRL2
228
Default
01
12:11 GP2_DRV_
STR[1:0]
01
12:11 GP3_DRV_
STR[1:0]
01
12:11 GP4_DRV_
STR[1:0]
01
12:11 GP5_DRV_
STR[1:0]
01
12:11 GP6_DRV_
STR[1:0]
01
12:11 GP7_DRV_
STR[1:0]
01
12:11 GP8_DRV_
STR[1:0]
01
12:11 GP9_DRV_
STR[1:0]
01
12:11 GP10_DRV_
STR[1:0]
01
12:11 GP11_DRV_
STR[1:0]
01
Description
AIF1TXDAT/GPIO1 output drive strength
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
AIF1RXDAT/GPIO2 output drive strength
Field description is as above.
AIF1BCLK/GPIO3 output drive strength
Field description is as above.
AIF1LRCLK/GPIO4 output drive strength
Field description is as above.
AIF2TXDAT/GPIO5 output drive strength
Field description is as above.
AIF2RXDAT/GPIO6 output drive strength
Field description is as above.
AIF2BCLK/GPIO7 output drive strength
Field description is as above.
AIF2LRCLK/GPIO8 output drive strength
Field description is as above.
AIF3TXDAT/GPIO9 output drive strength
Field description is as above.
AIF3RXDAT/GPIO10 output drive strength
Field description is as above.
AIF3BCLK/GPIO11 output drive strength
Field description is as above.
DS1137PP1
CS47L15
5.4 Digital Audio Interface Clocking Configurations
Table 5-4. Output Drive-Strength and Slew-Rate Control (Cont.)
Register Address
R5911 (0x1717)
GPIO12_CTRL2
R5913 (0x1719)
GPIO13_CTRL2
R5915 (0x171B)
GPIO14_CTRL2
R5917 (0x171D)
GPIO15_CTRL2
Bit
Label
12:11 GP12_DRV_
STR[1:0]
Default
01
12:11 GP13_DRV_
STR[1:0]
01
12:11 GP14_DRV_
STR[1:0]
01
12:11 GP15_DRV_
STR[1:0]
01
Description
AIF3LRCLK/GPIO12 output drive strength
Field description is as above.
SPKTXDAT/GPIO13 output drive strength
Field description is as above.
SPKCLK/GPIO14 output drive strength
Field description is as above.
SPKRXTDAT/GPIO15 output drive strength
Field description is as above.
5.4 Digital Audio Interface Clocking Configurations
The digital audio interfaces (AIF1–AIF3) can be configured in master or slave modes. In all applications, it is important that
the system clocking configuration is correctly designed. Incorrect clock configurations lead to audible clicks arising from
dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks.
To ensure reliable clocking of the audio interface functions, the external interface clocks (e.g., BCLK, LRCLK) must be
derived from the same clock source as SYSCLK.
In AIF Master Mode, the external BCLK and LRCLK signals are generated by the CS47L15 and synchronization of these
signals with SYSCLK is ensured. In this case, clocking of the AIF is typically derived from the MCLK1 or MCLK2 inputs,
either directly or via the FLL circuit. Alternatively, another AIFn interface (configured in Slave Mode) can be used to provide
the reference clock to which the AIF master can be synchronized.
In AIF Slave Mode, the external BCLK and LRCLK signals are generated by another device, as inputs to the CS47L15. In
this case, the system clock (SYSCLK) must be generated from a source that is synchronized to the external BCLK and
LRCLK inputs.
In a typical Slave Mode application, the BCLK input is selected as the clock reference, using the FLL to perform frequency
shifting. The MCLK1 or MCLK2 inputs can also be used, but only if the selected clock is synchronized externally to the
BCLK and LRCLK inputs.
The valid AIF clocking configurations are listed in Table 5-5 for AIF Master and AIF Slave Modes.
Table 5-5. AIF Clocking Configurations
AIF Mode
AIF Master Mode
AIF Slave Mode
Clocking Configuration
SYSCLK_SRC selects MCLK1 or MCLK2 as SYSCLK source.
SYSCLK_SRC selects FLL1 as SYSCLK source;
FLL1_REFCLK_SRC selects MCLK1 or MCLK2 as FLL1 source.
SYSCLK_SRC selects FLL1 as SYSCLK source;
FLL1_REFCLK_SRC selects a different interface (BCLK, LRCLK) as FLL1 source.
SYSCLK_SRC selects FLL1 as SYSCLK source;
FLL1_REFCLK_SRC selects BCLK as FLL1 source.
SYSCLK_SRC selects MCLK1 or MCLK2 as SYSCLK source, provided MCLK is externally
synchronized to the BCLK input.
SYSCLK_SRC selects FLL1 as SYSCLK source;
FLL1_REFCLK_SRC selects MCLK1 or MCLK2 as FLL1 source, provided MCLK is externally
synchronized to the BCLK input.
SYSCLK_SRC selects FLL1 as SYSCLK source;
FLL1_REFCLK_SRC selects a different interface (BCLK, LRCLK) as FLL1 source, provided the
other interface is externally synchronized to the BCLK input.
In each case, the SYSCLK frequency must be a valid ratio to the LRCLK frequency; the supported clocking rates are
defined by the SYSCLK_FREQ and SAMPLE_RATE_n fields.
The valid AIF clocking configurations are shown in Fig. 5-13 to Fig. 5-19. Note that, where MCLK1 is shown as the clock
source, it is equally possible to select MCLK2 as the clock source.
DS1137PP1
229
CS47L15
5.4 Digital Audio Interface Clocking Configurations
Fig. 5-13 shows AIF Master Mode operation, using MCLK as the clock reference.
CS47L15
Processor
AIFnBCLK
FLL1
AIFnBCLK
SYSCLK
AIFn
(Master Mode)
AIFnLRCLK
AIFnRXDAT
MCLK2
MCLK1
AIFnTXDAT
SYSCLK_SRC
Oscillator
Figure 5-13. AIF Master Mode, Using MCLK as Reference
Fig. 5-14 shows AIF Master Mode operation, using MCLK as the clock reference. In this example, the FLL is used to
generate the system clock, with MCLK as the reference.
Processor
CS47L15
AIFnLRCLK
AIFnBCLK
FLL1
FLL1_REFCLK_SRC
AIFnBCLK
AIFnBCLK
MCLK1
MCLK2
SYSCLK
AIFn
(Master Mode)
AIFnLRCLK
AIFnRXDAT
MCLK2
MCLK1
AIFnTXDAT
SYSCLK_SRC
Oscillator
Figure 5-14. AIF Master Mode, Using MCLK and FLL as Reference
230
DS1137PP1
CS47L15
5.4 Digital Audio Interface Clocking Configurations
Fig. 5-15 shows AIF Master Mode operation, using a separate interface as the clock reference. In this example, the FLL
is used to generate the system clock, with LRCLK or BCLK input (from a separate AIFn slave interface) as the reference.
CS47L15
Processor
MCLK1
MCLK2
FLL1
AIFnBCLK
MCLK1
MCLK2
AIFnBCLK
AIFnLRCLK
FLL1_REFCLK_SRC
AIFnBCLK
SYSCLK
AIFn
(Master Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
SYSCLK_SRC
Processor
AIFnBCLK
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
Figure 5-15. AIF Master Mode, Using Another Interface as Reference
Fig. 5-16 shows AIF Slave Mode operation, using BCLK as the clock reference. In this example, the FLL is used to
generate the system clock, with BCLK as the reference.
Processor
CS47L15
AIFnBCLK
MCLK1
MCLK2
FLL1_REFCLK_SRC
FLL1
AIFnBCLK
AIFnBCLK
MCLK1
MCLK2
SYSCLK
SYSCLK_SRC
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
Figure 5-16. AIF Slave Mode, Using BCLK and FLL as Reference
DS1137PP1
231
CS47L15
5.4 Digital Audio Interface Clocking Configurations
Fig. 5-17 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input
must be fully synchronized to the audio interface.
CS47L15
Processor
AIFnBCLK
MCLK2
MCLK1
FLL1
AIFnBCLK
SYSCLK
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
SYSCLK_SRC
Synchronous
Clock Generator
Figure 5-17. AIF Slave Mode, Using MCLK as Reference
Fig. 5-18 shows AIF Slave Mode operation, using MCLK as the clock reference. For correct operation, the MCLK input
must be fully synchronized to the audio interface. In this example, the FLL is used to generate the system clock, with MCLK
as the reference.
CS47L15
Processor
AIFnLRCLK
AIFnBCLK
FLL1
MCLK2
MCLK1
FLL1_REFCLK_SRC
AIFnBCLK
AIFnBCLK
MCLK1
MCLK2
SYSCLK
SYSCLK_SRC
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
Synchronous
Clock Generator
Figure 5-18. AIF Slave Mode, Using MCLK and FLL as Reference
232
DS1137PP1
CS47L15
5.5 PCB Layout Considerations
Fig. 5-19 shows AIF Slave Mode operation, using a separate interface as the clock reference. In this example, the FLL is
used to generate the system clock, with LRCLK or BCLK input (from a separate AIFn slave interface) as the reference.
For correct operation, the reference input must be fully synchronized to the other audio interfaces.
Processor
CS47L15
AIFnBCLK
AIFnLRCLK
MCLK1
MCLK2
FLL1
AIFnBCLK
FLL1_REFCLK_SRC AIFnBCLK
MCLK1
MCLK2
SYSCLK
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
SYSCLK_SRC
Synchronous
Clock Generator
Processor
AIFnBCLK
AIFn
(Slave Mode)
AIFnLRCLK
AIFnRXDAT
AIFnTXDAT
Figure 5-19. AIF Slave Mode, Using Another Interface as Reference
5.5 PCB Layout Considerations
Poor PCB layout degrades the performance and is a contributory factor in EMI, ground bounce, and resistive voltage
losses. All external components should be placed as close to the CS47L15 device as possible, with current loop areas
kept as small as possible.
PCB layout should be carefully considered, to ensure optimum performance of the CS47L15. Poor PCB layout degrades
the performance and is a contributory factor in EMI, ground bounce, and resistive voltage losses. All external components
should be placed close to the CS47L15, with current loop areas kept as small as possible. The following specific
considerations should be noted:
•
Placement of the charge pump capacitors is a high priority requirement—these capacitors (particularly the fly-back
capacitors) must be placed as close as possible to the CS47L15.
•
Decoupling capacitors should be placed as close as possible to the CS47L15. The connection between AGND, the
AVDD decoupling capacitor, and the main system ground should be made at a single point as close as possible to
the AGND ball of the CS47L15.
•
The VREFC capacitor should be placed as close as possible to the CS47L15. The ground connection to the VREFC
capacitor should be as close as possible to the AGND ball of the CS47L15.
•
If multiple power supply rails are connected to a single supply source, it is recommended to provide separate PCB
tracks connecting each rail to the supply. This configuration is also known as star connection.
•
If power supply rails are routed between different layers of the PCB, it is recommended to use several track vias, in
order to minimize resistive voltage losses.
•
Differential input signal tracks should be routed as a pair, ensuring similar length/width dimensions on each track.
Input signal paths should be kept away from high frequency digital signals.
•
Differential output signal tracks should be routed as a pair, ensuring similar length/width dimensions on each track.
The tracks should provide a low resistance path from the device output pin to the load (< 1% of the minimum load).
DS1137PP1
233
CS47L15
6 Register Map
•
The headphone output ground-feedback pins should be connected to GND as close as possible to the respective
headphone jack ground pin. The ground-feedback PCB track should follow the same route as the respective output
signal paths.
6 Register Map
The CS47L15 control registers are listed in the following tables. Note that only the register addresses described here
should be accessed; writing to other addresses may result in undefined behavior. Register bits that are not documented
should not be changed from the default values.
The CS47L15 register map is defined in two regions:
•
The codec register space (below 0x3000) is defined in 16-bit word format
•
The DSP register space (from 0x3000 upwards) is defined in 32-bit word format
It is important to ensure that all control interface register operations use the applicable data word format, in accordance
with the applicable register addresses.
The 16-bit codec register space is described in Table 6-1.
Table 6-1. Register Map Definition—16-bit region
Register
R0
(0h)
R1
(1h)
R2
(2h)
R8
(8h)
R18
(12h)
R22
(16h)
R23
(17h)
R24
(18h)
Name
Software_Reset
15
Hardware_Revision
0
0
0
0
0
0
0
0
HW_REVISION [7:0]
0000h
Software_Revision
0
0
0
0
0
0
0
0
SW_REVISION [7:0]
0000h
Ctrl_IF_CFG_1
0
0
1
1
0
1
1
1
MISO_
SCLK_PD
0
1
1
1
0
1
1
373Bh
Ctrl_IF_Pin_Cfg_1
1
0
1
0
0
I2C_
DEBUG
0
0
0
0
0
0
0
0
0
1
A401h
Write_Sequencer_Ctrl_0
0
0
0
0
WSEQ_
ABORT
WSEQ_
START
WSEQ_
ENA
WSEQ_START_INDEX [8:0]
0000h
Write_Sequencer_Ctrl_1
0
0
0
0
0
0
WSEQ_
BUSY
WSEQ_CURRENT_INDEX [8:0]
0000h
Write_Sequencer_Ctrl_2
0
0
0
0
0
0
0
R32
(20h)
R33
(21h)
R34
(22h)
R35
(23h)
R36
(24h)
R48
(30h)
R49
(31h)
R50
(32h)
R65
(41h)
Tone_Generator_1
0
R66
(42h)
R75
(4Bh)
R76
(4Ch)
R77
(4Dh)
R78
(4Eh)
R79
(4Fh)
R80
(50h)
Spare_Triggers
234
14
13
12
11
10
9
TONE_RATE [3:0]
0
0
TONE_OFFSET [1:0]
Tone_Generator_2
Tone_Generator_3
8
7
6
5
4
3
2
1
0
SW_RST_DEV_ID [15:0]
0
0
0
0
0
0
TONE2_ TONE1_
OVD
OVD
0
0
0
0
WSEQ_ WSEQ_
BOOT_ LOAD_
START
MEM
TONE2_ TONE1_
ENA
ENA
0
0
0
0
0
0
Tone_Generator_4
0000h
0000h
1000h
TONE1_LVL [23:8]
0
Default
6370h
0
0000h
TONE1_LVL [7:0]
1000h
TONE2_LVL [23:8]
Tone_Generator_5
0
PWM_Drive_1
0
PWM_Drive_2
0
0
0
0
0
0
PWM1_LVL [9:0]
0100h
PWM_Drive_3
0
0
0
0
0
0
PWM2_LVL [9:0]
0100h
Sequence_control
0
0
0
0
0
0
0
0
WSEQ_
TRG16
WSEQ_
TRG15
WSEQ_
TRG14
WSEQ_
TRG13
WSEQ_
TRG12
WSEQ_
TRG11
WSEQ_
TRG10
WSEQ_
TRG9
0
0
0
0
0
0
0
WSEQ_TRG1_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG2_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG3_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG4_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG5_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG6_INDEX [8:0]
01FFh
Spare_Sequence_
Select_1
Spare_Sequence_
Select_2
Spare_Sequence_
Select_3
Spare_Sequence_
Select_4
Spare_Sequence_
Select_5
Spare_Sequence_
Select_6
0
0
0
0
PWM_RATE [3:0]
0
0
0
PWM_CLK_SEL [2:0]
0000h
TONE2_LVL [7:0]
0
0
WSEQ_ WSEQ_
ENA_
ENA_
MICD_
MICD_
CLAMP_ CLAMP_
FALL
RISE
WSEQ_ WSEQ_
TRG8
TRG7
PWM2_
OVD
PWM1_
OVD
0
0
PWM2_
ENA
PWM1_
ENA
0000h
0
0
0
0
0
0
0000h
WSEQ_
TRG6
WSEQ_
TRG5
WSEQ_
TRG4
WSEQ_
TRG3
WSEQ_
TRG2
WSEQ_
TRG1
0000h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R89
(59h)
R90
(5Ah)
R91
(5Bh)
R92
(5Ch)
R93
(5Dh)
R94
(5Eh)
R97
(61h)
R98
(62h)
R99
(63h)
R100
(64h)
R102
(66h)
R103
(67h)
R104
(68h)
R105
(69h)
R106
(6Ah)
R107
(6Bh)
R110
(6Eh)
R111
(6Fh)
R120
(78h)
R121
(79h)
R140
(8Ch)
R144
(90h)
R145
(91h)
R146
(92h)
R147
(93h)
R148
(94h)
R149
(95h)
R150
(96h)
R151
(97h)
R152
(98h)
R160
(A0h)
R256
(100h)
R257
(101h)
R258
(102h)
R259
(103h)
R260
(104h)
R266
(10Ah)
R267
(10Bh)
Name
Spare_Sequence_
Select_7
Spare_Sequence_
Select_8
Spare_Sequence_
Select_9
Spare_Sequence_
Select_10
Spare_Sequence_
Select_11
Spare_Sequence_
Select_12
Sample_Rate_
Sequence_Select_1
Sample_Rate_
Sequence_Select_2
Sample_Rate_
Sequence_Select_3
Sample_Rate_
Sequence_Select_4
Always_On_Triggers_
Sequence_Select_1
Always_On_Triggers_
Sequence_Select_2
Spare_Sequence_
Select_13
Spare_Sequence_
Select_14
Spare_Sequence_
Select_15
Spare_Sequence_
Select_16
Trigger_Sequence_
Select_32
Trigger_Sequence_
Select_33
Eventlog_Sequence_
Select_1
Eventlog_Sequence_
Select_2
User_Key_Ctrl
15
14
13
12
11
10
9
0
0
0
0
0
0
0
WSEQ_TRG7_INDEX [8:0]
Default
01FFh
0
0
0
0
0
0
0
WSEQ_TRG8_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG9_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG10_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG11_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG12_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_SAMPLE_RATE_DETECT_A_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_SAMPLE_RATE_DETECT_B_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_SAMPLE_RATE_DETECT_C_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_SAMPLE_RATE_DETECT_D_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_MICD_CLAMP_RISE_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_MICD_CLAMP_FALL_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG13_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG14_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG15_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_TRG16_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_DRC1_SIG_DET_RISE_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_DRC1_SIG_DET_FALL_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_EVENTLOG1_INDEX [8:0]
01FFh
0
0
0
0
0
0
0
WSEQ_EVENTLOG2_INDEX [8:0]
01FFh
Haptics_Control_1
0
Haptics_Control_2
0
Haptics_phase_1_
intensity
Haptics_phase_1_
duration
Haptics_phase_2_
intensity
Haptics_phase_2_
duration
Haptics_phase_3_
intensity
Haptics_phase_3_
duration
Haptics_Status
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Comfort_Noise_
Generator
Clock_32k_1
0
0
0
0
0
0
NOISE_
GEN_ENA
0
0
0
0
0
0
0
0
0
CLK_32K_
ENA
0
0
System_Clock_1
SYSCLK_
FRAC
0
0
0
0
0
SYSCLK_
ENA
0
0
Sample_rate_1
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_1 [4:0]
0011h
Sample_rate_2
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_2 [4:0]
0011h
Sample_rate_3
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_3 [4:0]
0011h
Sample_rate_1_status
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_1_STS [4:0]
0000h
Sample_rate_2_status
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE_2_STS [4:0]
0000h
DS1137PP1
8
7
6
5
4
3
2
1
0
0000h
USER_KEY_CTRL [15:0]
HAP_RATE [3:0]
0
0
0
0
0
0
ONESHOT
_TRIG
HAP_CTRL [1:0]
HAP_ACT
0
7FFFh
LRA_FREQ [14:0]
NOISE_GEN_RATE [3:0]
0
0000h
PHASE1_INTENSITY [7:0]
0000h
PHASE1_DURATION [8:0]
0
0000h
PHASE2_INTENSITY [7:0]
0000h
PHASE2_DURATION [10:0]
0
0000h
PHASE3_INTENSITY [7:0]
0000h
PHASE3_DURATION [8:0]
SYSCLK_FREQ [2:0]
0000h
0
0
0
0
ONESHOT
_STS
0000h
NOISE_GEN_GAIN [4:0]
0000h
0
0002h
0
CLK_32K_SRC [1:0]
SYSCLK_SRC [3:0]
0404h
235
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R268
(10Ch)
R288
(120h)
R290
(122h)
R292
(124h)
R294
(126h)
R295
(127h)
R329
(149h)
R334
(14Eh)
Name
Sample_rate_3_status
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
DSP_Clock_1
0
0
0
0
0
0
1
1
0
DSP_
CLK_ENA
0
4
3
2
1
0
SAMPLE_RATE_3_STS [4:0]
0
Default
0000h
0304h
DSP_CLK_SRC [3:0]
DSP_Clock_2
DSP_CLK_FREQ [15:0]
0000h
DSP_Clock_3
FLL_AO_FREQ [15:0]
0000h
DSP_Clock_4
DSP_CLK_FREQ_STS [15:0]
0000h
DSP_Clock_5
0
0
0
0
0000h
0
0
0
0
0
0
0
0
DSP_CLK_SRC_STS [3:0]
Output_system_clock
OPCLK_
ENA
0
0
0
0
0
0
0
Clock_Gen_Pad_Ctrl
0
0
0
0
1
R338
(152h)
R339
(153h)
R340
(154h)
R341
(155h)
R342
(156h)
R352
(160h)
R369
(171h)
R370
(172h)
Rate_Estimator_1
0
0
0
0
DSP_
JTAG_
MODE
0
0
0
0
Rate_Estimator_2
0
0
0
0
0
0
0
Rate_Estimator_3
0
0
0
0
0
0
Rate_Estimator_4
0
0
0
0
0
Rate_Estimator_5
0
0
0
0
Clocking_debug_5
0
0
0
FLL1_Control_1
0
0
FLL1_Control_2
FLL1_
CTRL_
UPD
0
R371
(173h)
R372
(174h)
R373
(175h)
R374
(176h)
R375
(177h)
FLL1_Control_3
FLL1_THETA [15:0]
0018h
FLL1_Control_4
FLL1_LAMBDA [15:0]
007Dh
R376
(178h)
FLL1_NCO_Test_0
R377
(179h)
R378
(17Ah)
OPCLK_DIV [4:0]
MSTRBOO MCLK2_ MCLK1_
T_PD
PD
PD
0000h
OPCLK_SEL [2:0]
0
0
0
0660h
RATE_
EST_ENA
0000h
1
1
0
0
0
0
TRIG_ON_
STARTUP
0
0
0
0
SAMPLE_RATE_DETECT_A [4:0]
0000h
0
0
0
0
0
SAMPLE_RATE_DETECT_B [4:0]
0000h
0
0
0
0
0
0
SAMPLE_RATE_DETECT_C [4:0]
0000h
0
0
0
0
0
0
0
SAMPLE_RATE_DETECT_D [4:0]
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LRCLK_SRC [2:0]
SYSCLK_FREQ_STS [2:0]
0
0
0
0
0000h
SYSCLK_SRC_STS [3:0]
0
0
FLL1_ FLL1_ENA
FREERUN
0002h
0008h
FLL1_N [9:0]
FLL1_Control_5
0
0
0
0
FLL1_Control_6
0
0
0
0
0
0
0
FLL1_FRC_INTEG_VAL [11:0]
0281h
0
0
0
FLL1_INTEG [11:0]
0000h
FLL1_Control_7
FLL1_
FRC_
INTEG_
UPD
FLL1_
INTEG_
VALID
0
0
0
0
0
0
0
0
0
0
FLL1_Control_8
0
0
1
0
0
0
1
0
0
0
0
0
R385
(181h)
FLL1_Synchroniser_1
0
0
0
0
FLL1_
PHASE_
ENA
0
0
0
0
0
0
0
0
0
R386
(182h)
R387
(183h)
R388
(184h)
R389
(185h)
R390
(186h)
R391
(187h)
FLL1_Synchroniser_2
0
0
0
0
0
0
FLL1_Loop_Filter_Test_
1
FLL1_FRATIO [3:0]
0
0
0
0
0
0
FLL1_REFCLK_DIV
[1:0]
0
0
0
0
0
0
0
0000h
0000h
FLL1_REFCLK_SRC [3:0]
0
0
0000h
1
1
0
2906h
0
0
FLL1_
SYNC_
ENA
0000h
FLL1_GAIN [3:0]
0000h
FLL1_SYNC_N [9:0]
FLL1_Synchroniser_3
FLL1_SYNC_THETA [15:0]
0000h
FLL1_Synchroniser_4
FLL1_SYNC_LAMBDA [15:0]
0000h
FLL1_Synchroniser_5
0
0
0
0
0
FLL1_Synchroniser_6
0
0
0
0
0
0
0
0
FLL1_Synchroniser_7
0
0
0
0
0
0
0
0
0
0
R393
(189h)
R394
(18Ah)
FLL1_Spread_Spectrum
0
0
0
0
0
0
0
0
0
0
FLL1_GPIO_Clock
0
0
0
0
0
0
0
0
R465
(1D1h)
R470
(1D6h)
R490
(1EAh)
FLL_AO_Control_1
0
0
0
0
0
0
0
0
0
0
0
0
FLL_AO_Control_6
1
0
0
0
0
0
0
0
0
0
0
0
FLL_AO_GPIO_Clock
0
0
0
0
0
0
0
0
236
0
FLL1_SYNC_FRATIO [2:0]
0
0
FLL1_SYNCCLK_DIV
[1:0]
0
0
0
0
0
0
0
0
FLL1_SYNCCLK_SRC [3:0]
FLL1_SYNC_GAIN [3:0]
0
FLL1_
SYNC_
DFSAT
FLL1_SS_AMPL [1:0] FLL1_SS_FREQ [1:0] FLL1_SS_SEL [1:0]
FLL1_GPCLK_DIV [6:0]
0
FLL_AO_GPCLK_DIV [6:0]
FLL_AO_
HOLD
0
FLL1_
GPCLK_
ENA
FLL_AO_
ENA
FLL_AO_REFCLK_SRC [3:0]
FLL_AO_
GPCLK_
ENA
0000h
0000h
0001h
0000h
0004h
0004h
8004h
0002h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R536
(218h)
R540
(21Ch)
R620
(26Ch)
R665
(299h)
R667
(29Bh)
R668
(29Ch)
R669
(29Dh)
R674
(2A2h)
Name
Mic_Bias_Ctrl_1
15
14
13
12
11
10
9
MICB1_
EXT_CAP
0
0
0
0
0
0
Mic_Bias_Ctrl_5
0
0
0
0
0
0
SPK_Watchdog_1
0
0
0
0
0
0
Headphone_Detect_0
HPD_
OVD_ENA
Headphone_Detect_1
0
Headphone_Detect_2
HPD_
DONE
Headphone_Detect_3
0
HPD_OUT_SEL [2:0]
0
0
8
7
MICB1C_ MICB1C_
DISCH
ENA
0
0
0
0
0
0
HPD_FRC_SEL [3:0]
0
0
HPD_IMPEDANCE_
RANGE [1:0]
6
5
MICB1_LVL [3:0]
0
0
0
0
0
0
ADC_
MODE
MICD1_BIAS_STARTTIME [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
MICB1A_ MICB1A_
DISCH
ENA
SPK_SHUTDOWN_TIMER_SEL [3:0]
0
HPD_RATE [1:0]
0
0
HPD_
POLL (M)
0010h
MICD1_BIAS_SRC [3:0]
0
0
1102h
0
0
0
0
0
0
0
0
R712
(2C8h)
R723
(2D3h)
R768
(300h)
R769
(301h)
R776
(308h)
R777
(309h)
R780
(30Ch)
R784
(310h)
R785
(311h)
R786
(312h)
R788
(314h)
R789
(315h)
R790
(316h)
GP_Switch_1
0
0
0
0
0
0
0
0
0
0
Jack_detect_analogue
0
0
0
0
0
0
0
0
0
Input_Enables
0
0
0
0
0
0
0
0
Input_Enables_Status
0
0
0
0
0
0
0
Input_Rate
0
0
Input_Volume_Ramp
0
0
0
0
0
HPF_Control
0
0
0
0
0
IN1L_Control
IN1L_HPF
0
0
R792
(318h)
R793
(319h)
R794
(31Ah)
R796
(31Ch)
R797
(31Dh)
R798
(31Eh)
IN2L_Control
R832
(340h)
R840
(348h)
R1024
(400h)
R1025
(401h)
R1030
(406h)
Signal_Detect_Globals
0
Mic_Detect_1_Control_3
0
0
0
0
0
Mic_Detect_1_Control_4
0
0
0
IN1L_SRC [1:0]
DMIC1L_Control
IN1L_SIG_
DET_ENA
0
0
IN1R_Control
IN1R_HPF
0
0
IN1R_SRC [1:0]
IN1_DMIC_SUP [1:0]
0
0
0
0
IN1_DMICCLK_SRC
[1:0] (K)
MICD1_
DBTIME
MICD1_
ENA
009Fh
MICD1_LVL_SEL [7:0]
MICD1_LVL [8:0]
MICD1_ADCVAL_DIFF [7:0]
IN_RATE [3:0]
0000h
MICD1_GND_SEL [2:0]
0
0
0000h
0
0
0
0000h
MICD1_SENSE_SEL [3:0]
0
0
0222h
0000h
HPD_GND_SEL [2:0]
HPD_CLK_DIV [1:0]
Default
00E6h
0000h
Micd_Clamp_control
0
DMIC1R_Control
0
MICB1_
ENA
HPD_DACVAL [9:0]
MICD1_RATE [3:0]
Mic_Detect_1_Control_2
0
1
MICB1_
BYPASS
HPD_SENSE_SEL [3:0]
Mic_Detect_1_Control_1
ADC_Digital_Volume_1R
2
MICB1_
DISCH
MICB1B_ MICB1B_
DISCH
ENA
R675
(2A3h)
R676
(2A4h)
R677
(2A5h)
R683
(2ABh)
R710
(2C6h)
0
3
MICB1_
RATE
HPD_LVL [14:0]
Mic_Detect_1_Control_0 MICD1_
ADC_Digital_Volume_1L
4
0
MICD1_
VALID
0
MICD1_
STS
0000h
0000h
MICD1_ADCVAL [6:0]
0010h
0
MICD_
CLAMP_
OVD
0
0
0
SW1_MODE [1:0]
0000h
0
0
0
0
0
JD2_ENA JD1_ENA
0000h
0
0
0
0
IN2L_ENA IN2R_ENA IN1L_ENA IN1R_ENA
0000h
0
0
0
0
0
IN2L_
IN2R_
IN1L_
IN1R_
ENA_STS ENA_STS ENA_STS ENA_STS
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IN1_
MODE
0
0
0
IN_VU
IN1L_
MUTE
IN1_OSR [2:0]
0
0
0
0
0
IN_VU
IN1R_
MUTE
IN_VD_RAMP [2:0]
0
0
0
0
0
0
0
IN_VI_RAMP [2:0]
0022h
0
IN_HPF_CUT [2:0]
0002h
0
0
0
0
0080h
0180h
IN1L_VOL [7:0]
0
0000h
0
IN1L_PGA_VOL [6:0]
0
0
MICD_CLAMP_MODE [3:0]
0
0
IN1R_PGA_VOL [6:0]
0
0500h
0
0080h
0180h
IN1R_VOL [7:0]
IN1R_
SIG_DET_
ENA
IN2L_HPF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
0
0
0
0
IN2_
MODE
0
0
0
0
0
0
0
0
0
0
0000h
0
0
0
0
IN2L_LP_
MODE
0
IN_VU
IN2L_
MUTE
DMIC2L_Control
IN2L_SIG_
DET_ENA
0
0
0
0
IN2R_Control
IN2R_HPF
0
0
0
1
0
0
0
0
0
0
0
1
0
IN_VU
IN2R_
MUTE
IN2R_
SIG_DET_
ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Dig_Mic_Pad_Ctrl
0
0
0
0
0
0
0
Output_Enables_1
EP_SEL
0
0
0
0
0
Output_Status_1
0
0
0
0
0
0
Raw_Output_Status_1
0
0
0
0
0
0
ADC_Digital_Volume_2L
ADC_Digital_Volume_2R
DMIC2R_Control
DS1137PP1
IN2_OSR [2:0]
0980h
IN2L_VOL [7:0]
0
0
0
0
0
0
0
0
0500h
0
0
0
0
0
0
0
0
0800h
0980h
IN2R_VOL [7:0]
0
0
0
0
0
IN_SIG_DET_THR [4:0]
0
0
0
0000h
0001h
IN_SIG_DET_HOLD [3:0]
0
0
0
0
0
0
DMICDAT1
_PD
0000h
OUT5L_ OUT5R_ SPKOUTL
ENA
ENA
_ENA
0
0
0
0
0
HP1L_
ENA
HP1R_
ENA
0000h
OUT5L_ OUT5R_ OUT4L_
ENA_STS ENA_STS ENA_STS
0
0
0
0
0
0
0
0000h
0
0
0
0
0
0
0
0
0
0
OUT1L_ OUT1R_
ENA_STS ENA_STS
0000h
237
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1032
(408h)
R1033
(409h)
R1040
(410h)
R1041
(411h)
R1042
(412h)
R1043
(413h)
R1045
(415h)
R1047
(417h)
R1065
(429h)
R1067
(42Bh)
R1072
(430h)
R1073
(431h)
R1075
(433h)
R1077
(435h)
R1079
(437h)
R1104
(450h)
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1_
MONO
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC_Digital_Volume_1R
0
0
0
0
Noise_Gate_Select_1R
0
0
0
0
DAC_Digital_Volume_4L
0
0
0
0
Noise_Gate_Select_4L
0
0
0
0
Output_Path_Config_5L
0
0
OUT5_
OSR
0
0
0
DAC_Digital_Volume_5L
0
0
0
0
0
0
Noise_Gate_Select_5L
0
0
0
0
DAC_Digital_Volume_5R
0
0
0
0
Noise_Gate_Select_5R
0
0
0
0
DAC_AEC_Control_1
0
0
0
0
0
0
0
0
0
0
R1105
(451h)
DAC_AEC_Control_2
0
0
0
0
0
0
0
0
0
0
R1112
(458h)
R1168
(490h)
Noise_Gate_Control
0
0
0
0
0
0
0
0
0
0
PDM_SPK1_CTRL_1
0
0
SPK1R_
MUTE
SPK1L_
MUTE
0
0
0
R1169
(491h)
R1280
(500h)
PDM_SPK1_CTRL_2
0
0
0
0
0
0
0
SPK1_
MUTE_
ENDIAN
0
AIF1_BCLK_Ctrl
0
0
0
0
0
0
0
0
R1281
(501h)
R1282
(502h)
AIF1_Tx_Pin_Ctrl
0
0
0
0
0
0
0
0
AIF1_Rx_Pin_Ctrl
0
0
0
0
0
0
0
0
0
0
0
R1283
(503h)
R1284
(504h)
R1286
(506h)
R1287
(507h)
R1288
(508h)
R1289
(509h)
R1290
(50Ah)
R1291
(50Bh)
R1292
(50Ch)
R1293
(50Dh)
R1294
(50Eh)
R1297
(511h)
R1298
(512h)
R1299
(513h)
AIF1_Rate_Ctrl
0
0
0
0
0
AIF1_TRI
AIF1_Format
0
0
0
0
0
0
0
0
AIF1_Rx_BCLK_Rate
0
0
0
AIF1_Frame_Ctrl_1
0
0
AIF1TX_WL [5:0]
AIF1TX_SLOT_LEN [7:0]
1818h
AIF1_Frame_Ctrl_2
0
0
AIF1RX_WL [5:0]
AIF1RX_SLOT_LEN [7:0]
1818h
AIF1_Frame_Ctrl_3
0
0
0
0
0
0
0
0
0
0
AIF1TX1_SLOT [5:0]
0000h
AIF1_Frame_Ctrl_4
0
0
0
0
0
0
0
0
0
0
AIF1TX2_SLOT [5:0]
0001h
AIF1_Frame_Ctrl_5
0
0
0
0
0
0
0
0
0
0
AIF1TX3_SLOT [5:0]
0002h
AIF1_Frame_Ctrl_6
0
0
0
0
0
0
0
0
0
0
AIF1TX4_SLOT [5:0]
0003h
AIF1_Frame_Ctrl_7
0
0
0
0
0
0
0
0
0
0
AIF1TX5_SLOT [5:0]
0004h
AIF1_Frame_Ctrl_8
0
0
0
0
0
0
0
0
0
0
AIF1TX6_SLOT [5:0]
0005h
AIF1_Frame_Ctrl_11
0
0
0
0
0
0
0
0
0
0
AIF1RX1_SLOT [5:0]
0000h
AIF1_Frame_Ctrl_12
0
0
0
0
0
0
0
0
0
0
AIF1RX2_SLOT [5:0]
0001h
AIF1_Frame_Ctrl_13
0
0
0
0
0
0
0
0
0
0
AIF1RX3_SLOT [5:0]
0002h
238
Name
Output_Rate_1
15
14
Output_Volume_Ramp
0
0
0
0
Output_Path_Config_1L
0
0
0
DAC_Digital_Volume_1L
0
0
Output_Path_Config_1
0
Noise_Gate_Select_1L
0
13
12
11
OUT_RATE [3:0]
0
0
0
OUT_VU OUT1L_
MUTE
0
0
0
0022h
OUT_VI_RAMP [2:0]
0
0
0
0
0
0
0
0
0
0
OUT_VU OUT1R_
MUTE
0
0000h
HP1_GND_SEL [2:0]
0001h
0180h
OUT1R_VOL [7:0]
0002h
OUT1R_NGATE_SRC [11:0]
0
0
OUT_VU OUT4L_
MUTE
0180h
OUT4L_VOL [7:0]
0040h
OUT4L_NGATE_SRC [11:0]
0
0
0
0
0
0
OUT_VU OUT5L_
MUTE
0
0
0
0
0
OUT_VU OUT5R_
MUTE
0100h
0180h
OUT5R_VOL [7:0]
0200h
OUT5R_NGATE_SRC [11:0]
0
AEC1_LOOPBACK_SRC [3:0]
AEC1_
AEC1_
ENA_STS LOOPBAC
K_ENA
AEC2_LOOPBACK_SRC [3:0]
AEC2_
AEC2_
ENA_STS LOOPBAC
K_ENA
NGATE_HOLD [1:0]
NGATE_THR [2:0]
NGATE_
ENA
0
AIF1_
AIF1_
BCLK_INV BCLK_
FRC
0
0
0
0
AIF1_
BCLK_
MSTR
AIF1TX_
DAT_TRI
0
0000h
0000h
0000h
0069h
SPK1_MUTE_SEQ [7:0]
0
0000h
0180h
OUT5L_VOL [7:0]
OUT5L_NGATE_SRC [11:0]
0
0080h
0180h
OUT1L_VOL [7:0]
OUT1L_NGATE_SRC [11:0]
AIF1_RATE [3:0]
0
OUT_VD_RAMP [2:0]
Default
0000h
0
0
SPK1_
FMT
0000h
000Ch
AIF1_BCLK_FREQ [4:0]
0
0
0
0
0
0000h
0
0
AIF1_
LRCLK_
INV
0
AIF1_
LRCLK_
FRC
0
AIF1_
LRCLK_
MSTR
0
0000h
0
AIF1_
LRCLK_
ADV
0
0
0
0
AIF1_FMT [2:0]
0000h
0000h
0040h
AIF1_BCPF [12:0]
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1300
(514h)
R1301
(515h)
R1302
(516h)
R1305
(519h)
R1306
(51Ah)
R1344
(540h)
Name
AIF1_Frame_Ctrl_14
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
AIF1RX4_SLOT [5:0]
Default
0003h
AIF1_Frame_Ctrl_15
0
0
0
0
0
0
0
0
0
0
AIF1RX5_SLOT [5:0]
0004h
AIF1_Frame_Ctrl_16
0
0
0
0
0
0
0
0
0
0
AIF1RX6_SLOT [5:0]
0005h
AIF1_Tx_Enables
0
0
0
0
0
0
0
0
0
0
AIF1TX6_ AIF1TX5_ AIF1TX4_ AIF1TX3_ AIF1TX2_ AIF1TX1_
ENA
ENA
ENA
ENA
ENA
ENA
0000h
AIF1_Rx_Enables
0
0
0
0
0
0
0
0
0
0
AIF1RX6_ AIF1RX5_ AIF1RX4_ AIF1RX3_ AIF1RX2_ AIF1RX1_
ENA
ENA
ENA
ENA
ENA
ENA
0000h
AIF2_BCLK_Ctrl
0
0
0
0
0
0
0
0
000Ch
R1345
(541h)
R1346
(542h)
AIF2_Tx_Pin_Ctrl
0
0
0
0
0
0
0
0
AIF2_
BCLK_
MSTR
AIF2TX_
DAT_TRI
AIF2_Rx_Pin_Ctrl
0
0
0
0
0
0
0
0
0
0
0
R1347
(543h)
R1348
(544h)
R1350
(546h)
R1351
(547h)
R1352
(548h)
R1353
(549h)
R1354
(54Ah)
R1355
(54Bh)
R1356
(54Ch)
R1361
(551h)
R1362
(552h)
R1363
(553h)
R1364
(554h)
R1369
(559h)
R1370
(55Ah)
R1408
(580h)
AIF2_Rate_Ctrl
0
0
0
0
0
AIF2_TRI
AIF2_Format
0
0
0
0
0
0
0
0
AIF2_Rx_BCLK_Rate
0
0
0
AIF2_Frame_Ctrl_1
0
0
AIF2TX_WL [5:0]
AIF2TX_SLOT_LEN [7:0]
1818h
AIF2_Frame_Ctrl_2
0
0
AIF2RX_WL [5:0]
AIF2RX_SLOT_LEN [7:0]
1818h
AIF2_Frame_Ctrl_3
0
0
0
0
0
0
0
0
0
0
AIF2TX1_SLOT [5:0]
0000h
AIF2_Frame_Ctrl_4
0
0
0
0
0
0
0
0
0
0
AIF2TX2_SLOT [5:0]
0001h
AIF2_Frame_Ctrl_5
0
0
0
0
0
0
0
0
0
0
AIF2TX3_SLOT [5:0]
0002h
AIF2_Frame_Ctrl_6
0
0
0
0
0
0
0
0
0
0
AIF2TX4_SLOT [5:0]
0003h
AIF2_Frame_Ctrl_11
0
0
0
0
0
0
0
0
0
0
AIF2RX1_SLOT [5:0]
0000h
AIF2_Frame_Ctrl_12
0
0
0
0
0
0
0
0
0
0
AIF2RX2_SLOT [5:0]
0001h
AIF2_Frame_Ctrl_13
0
0
0
0
0
0
0
0
0
0
AIF2RX3_SLOT [5:0]
0002h
AIF2_Frame_Ctrl_14
0
0
0
0
0
0
0
0
0
0
AIF2RX4_SLOT [5:0]
0003h
AIF2_Tx_Enables
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX4_ AIF2TX3_ AIF2TX2_ AIF2TX1_
ENA
ENA
ENA
ENA
0000h
AIF2_Rx_Enables
0
0
0
0
0
0
0
0
0
0
0
0
AIF2RX4_ AIF2RX3_ AIF2RX2_ AIF2RX1_
ENA
ENA
ENA
ENA
0000h
AIF3_BCLK_Ctrl
0
0
0
0
0
0
0
0
R1409
(581h)
R1410
(582h)
AIF3_Tx_Pin_Ctrl
0
0
0
0
0
0
0
0
AIF3_Rx_Pin_Ctrl
0
0
0
0
0
0
0
0
0
0
0
R1411
(583h)
R1412
(584h)
R1414
(586h)
R1415
(587h)
R1416
(588h)
R1417
(589h)
R1418
(58Ah)
R1425
(591h)
R1426
(592h)
R1433
(599h)
R1434
(59Ah)
AIF3_Rate_Ctrl
0
0
0
0
0
AIF3_TRI
AIF3_Format
0
0
0
0
0
0
0
0
AIF3_Rx_BCLK_Rate
0
0
0
AIF3_Frame_Ctrl_1
0
0
AIF3TX_WL [5:0]
AIF3TX_SLOT_LEN [7:0]
1818h
AIF3_Frame_Ctrl_2
0
0
AIF3RX_WL [5:0]
AIF3RX_SLOT_LEN [7:0]
1818h
AIF3_Frame_Ctrl_3
0
0
0
0
0
0
0
0
0
0
AIF3TX1_SLOT [5:0]
0000h
AIF3_Frame_Ctrl_4
0
0
0
0
0
0
0
0
0
0
AIF3TX2_SLOT [5:0]
0001h
AIF3_Frame_Ctrl_11
0
0
0
0
0
0
0
0
0
0
AIF3RX1_SLOT [5:0]
0000h
AIF3_Frame_Ctrl_12
0
0
0
0
0
0
0
0
0
0
AIF3RX2_SLOT [5:0]
0001h
AIF3_Tx_Enables
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX2_ AIF3TX1_
ENA
ENA
0000h
AIF3_Rx_Enables
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3RX2_ AIF3RX1_
ENA
ENA
0000h
DS1137PP1
AIF2_RATE [3:0]
0
0
AIF2_
AIF2_
BCLK_INV BCLK_
FRC
0
0
5
4
3
2
1
0
AIF2_BCLK_FREQ [4:0]
0
0
0
0
0
0000h
0
0
AIF2_
LRCLK_
INV
0
AIF2_
LRCLK_
FRC
0
AIF2_
LRCLK_
MSTR
0
0000h
0
AIF2_
LRCLK_
ADV
0
0
0
0
0000h
AIF2_FMT [2:0]
0040h
AIF2_BCPF [12:0]
AIF3_RATE [3:0]
0
0
AIF3_
AIF3_
BCLK_INV BCLK_
FRC
0
0
0000h
AIF3_
BCLK_
MSTR
AIF3TX_
DAT_TRI
000Ch
AIF3_BCLK_FREQ [4:0]
0
0
0
0
0
0000h
0
0
AIF3_
LRCLK_
INV
0
AIF3_
LRCLK_
FRC
0
AIF3_
LRCLK_
MSTR
0
0000h
0
AIF3_
LRCLK_
ADV
0
0
0
0
AIF3_FMT [2:0]
0000h
0000h
0040h
AIF3_BCPF [12:0]
239
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1474
(5C2h)
R1475
(5C3h)
R1476
(5C4h)
R1477
(5C5h)
R1600
(640h)
R1601
(641h)
R1602
(642h)
R1603
(643h)
R1604
(644h)
R1605
(645h)
R1606
(646h)
R1607
(647h)
R1608
(648h)
R1609
(649h)
R1610
(64Ah)
R1611
(64Bh)
R1612
(64Ch)
R1613
(64Dh)
R1614
(64Eh)
R1615
(64Fh)
R1664
(680h)
R1665
(681h)
R1666
(682h)
R1667
(683h)
R1668
(684h)
R1669
(685h)
R1670
(686h)
R1671
(687h)
R1672
(688h)
R1673
(689h)
R1674
(68Ah)
R1675
(68Bh)
R1676
(68Ch)
R1677
(68Dh)
R1678
(68Eh)
R1679
(68Fh)
R1712
(6B0h)
R1713
(6B1h)
240
Name
SPD1_TX_Control
SPD1_TX_Channel_
Status_1
SPD1_TX_Channel_
Status_2
SPD1_TX_Channel_
Status_3
PWM1MIX_Input_1_
Source
PWM1MIX_Input_1_
Volume
PWM1MIX_Input_2_
Source
PWM1MIX_Input_2_
Volume
PWM1MIX_Input_3_
Source
PWM1MIX_Input_3_
Volume
PWM1MIX_Input_4_
Source
PWM1MIX_Input_4_
Volume
PWM2MIX_Input_1_
Source
PWM2MIX_Input_1_
Volume
PWM2MIX_Input_2_
Source
PWM2MIX_Input_2_
Volume
PWM2MIX_Input_3_
Source
PWM2MIX_Input_3_
Volume
PWM2MIX_Input_4_
Source
PWM2MIX_Input_4_
Volume
OUT1LMIX_Input_1_
Source
OUT1LMIX_Input_1_
Volume
OUT1LMIX_Input_2_
Source
OUT1LMIX_Input_2_
Volume
OUT1LMIX_Input_3_
Source
OUT1LMIX_Input_3_
Volume
OUT1LMIX_Input_4_
Source
OUT1LMIX_Input_4_
Volume
OUT1RMIX_Input_1_
Source
OUT1RMIX_Input_1_
Volume
OUT1RMIX_Input_2_
Source
OUT1RMIX_Input_2_
Volume
OUT1RMIX_Input_3_
Source
OUT1RMIX_Input_3_
Volume
OUT1RMIX_Input_4_
Source
OUT1RMIX_Input_4_
Volume
OUT4LMIX_Input_1_
Source
OUT4LMIX_Input_1_
Volume
15
14
13
12
11
10
9
8
0
0
SPD1_
VAL2
SPD1_
VAL1
0
0
0
0
SPD1_CATCODE [7:0]
SPD1_FREQ [3:0]
7
6
SPD1_CHSTMODE
[1:0]
SPD1_CHNUM2 [3:0]
5
SPD1_RATE [3:0]
4
3
2
1
0
0
0
0
SPD1_
ENA
0
0
0
0
SPD1_ORGSAMP [3:0]
SPD1_TXWL [2:0]
PWM1MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM2MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM2MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM2MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM2MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1RMI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1RMI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1RMI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1RMI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT4LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPD1_
SPD1_
SPD1_
NOCOPY NOAUDIO PRO
0000h
SPD1_SRCNUM [3:0]
0001h
SPD1_PREEMPH [2:0]
SPD1_CHNUM1 [3:0]
SPD1_ SPD1_CS31_30 [1:0] SPD1_CLKACU [1:0]
MAXWL
PWM1MIX_VOL1 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
OUT1RMIX_SRC4 [7:0]
0
0080h
0000h
OUT4LMIX_SRC1 [7:0]
OUT4LMIX_VOL1 [6:0]
0080h
0000h
OUT1RMIX_SRC3 [7:0]
OUT1RMIX_VOL3 [6:0]
0080h
0000h
OUT1RMIX_SRC2 [7:0]
OUT1RMIX_VOL2 [6:0]
0080h
0000h
OUT1RMIX_SRC1 [7:0]
OUT1RMIX_VOL1 [6:0]
0080h
0000h
OUT1LMIX_SRC4 [7:0]
OUT1LMIX_VOL4 [6:0]
0080h
0000h
OUT1LMIX_SRC3 [7:0]
OUT1LMIX_VOL3 [6:0]
0080h
0000h
OUT1LMIX_SRC2 [7:0]
OUT1LMIX_VOL2 [6:0]
0080h
0000h
OUT1LMIX_SRC1 [7:0]
OUT1LMIX_VOL1 [6:0]
0080h
0000h
PWM2MIX_SRC4 [7:0]
PWM2MIX_VOL4 [6:0]
0080h
0000h
PWM2MIX_SRC3 [7:0]
PWM2MIX_VOL3 [6:0]
0080h
0000h
PWM2MIX_SRC2 [7:0]
PWM2MIX_VOL2 [6:0]
0080h
0000h
PWM2MIX_SRC1 [7:0]
PWM2MIX_VOL1 [6:0]
0080h
0000h
PWM1MIX_SRC4 [7:0]
PWM1MIX_VOL4 [6:0]
0080h
0000h
PWM1MIX_SRC3 [7:0]
PWM1MIX_VOL3 [6:0]
0080h
0000h
PWM1MIX_SRC2 [7:0]
PWM1MIX_VOL2 [6:0]
0000h
0000h
PWM1MIX_SRC1 [7:0]
OUT1RMIX_VOL4 [6:0]
Default
0000h
0
0080h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1714
(6B2h)
R1715
(6B3h)
R1716
(6B4h)
R1717
(6B5h)
R1718
(6B6h)
R1719
(6B7h)
R1728
(6C0h)
R1729
(6C1h)
R1730
(6C2h)
R1731
(6C3h)
R1732
(6C4h)
R1733
(6C5h)
R1734
(6C6h)
R1735
(6C7h)
R1736
(6C8h)
R1737
(6C9h)
R1738
(6CAh)
R1739
(6CBh)
R1740
(6CCh)
R1741
(6CDh)
R1742
(6CEh)
R1743
(6CFh)
R1792
(700h)
R1793
(701h)
R1794
(702h)
R1795
(703h)
R1796
(704h)
R1797
(705h)
R1798
(706h)
R1799
(707h)
R1800
(708h)
R1801
(709h)
R1802
(70Ah)
R1803
(70Bh)
R1804
(70Ch)
R1805
(70Dh)
R1806
(70Eh)
R1807
(70Fh)
Name
OUT4LMIX_Input_2_
Source
OUT4LMIX_Input_2_
Volume
OUT4LMIX_Input_3_
Source
OUT4LMIX_Input_3_
Volume
OUT4LMIX_Input_4_
Source
OUT4LMIX_Input_4_
Volume
OUT5LMIX_Input_1_
Source
OUT5LMIX_Input_1_
Volume
OUT5LMIX_Input_2_
Source
OUT5LMIX_Input_2_
Volume
OUT5LMIX_Input_3_
Source
OUT5LMIX_Input_3_
Volume
OUT5LMIX_Input_4_
Source
OUT5LMIX_Input_4_
Volume
OUT5RMIX_Input_1_
Source
OUT5RMIX_Input_1_
Volume
OUT5RMIX_Input_2_
Source
OUT5RMIX_Input_2_
Volume
OUT5RMIX_Input_3_
Source
OUT5RMIX_Input_3_
Volume
OUT5RMIX_Input_4_
Source
OUT5RMIX_Input_4_
Volume
AIF1TX1MIX_Input_1_
Source
AIF1TX1MIX_Input_1_
Volume
AIF1TX1MIX_Input_2_
Source
AIF1TX1MIX_Input_2_
Volume
AIF1TX1MIX_Input_3_
Source
AIF1TX1MIX_Input_3_
Volume
AIF1TX1MIX_Input_4_
Source
AIF1TX1MIX_Input_4_
Volume
AIF1TX2MIX_Input_1_
Source
AIF1TX2MIX_Input_1_
Volume
AIF1TX2MIX_Input_2_
Source
AIF1TX2MIX_Input_2_
Volume
AIF1TX2MIX_Input_3_
Source
AIF1TX2MIX_Input_3_
Volume
AIF1TX2MIX_Input_4_
Source
AIF1TX2MIX_Input_4_
Volume
DS1137PP1
15
14
13
12
11
10
9
8
OUT4LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT4LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT4LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5RMI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5RMI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5RMI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT5RMI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX1MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX1MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX1MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX1MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX2MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX2MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX2MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX2MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
OUT4LMIX_SRC2 [7:0]
OUT4LMIX_VOL2 [6:0]
0000h
OUT4LMIX_SRC3 [7:0]
OUT4LMIX_VOL3 [6:0]
0
0000h
OUT4LMIX_SRC4 [7:0]
OUT4LMIX_VOL4 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
AIF1TX2MIX_SRC4 [7:0]
AIF1TX2MIX_VOL4 [6:0]
0080h
0000h
AIF1TX2MIX_SRC3 [7:0]
AIF1TX2MIX_VOL3 [6:0]
0080h
0000h
AIF1TX2MIX_SRC2 [7:0]
AIF1TX2MIX_VOL2 [6:0]
0080h
0000h
AIF1TX2MIX_SRC1 [7:0]
AIF1TX2MIX_VOL1 [6:0]
0080h
0000h
AIF1TX1MIX_SRC4 [7:0]
AIF1TX1MIX_VOL4 [6:0]
0080h
0000h
AIF1TX1MIX_SRC3 [7:0]
AIF1TX1MIX_VOL3 [6:0]
0080h
0000h
AIF1TX1MIX_SRC2 [7:0]
AIF1TX1MIX_VOL2 [6:0]
0080h
0000h
AIF1TX1MIX_SRC1 [7:0]
AIF1TX1MIX_VOL1 [6:0]
0080h
0000h
OUT5RMIX_SRC4 [7:0]
OUT5RMIX_VOL4 [6:0]
0080h
0000h
OUT5RMIX_SRC3 [7:0]
OUT5RMIX_VOL3 [6:0]
0080h
0000h
OUT5RMIX_SRC2 [7:0]
OUT5RMIX_VOL2 [6:0]
0080h
0000h
OUT5RMIX_SRC1 [7:0]
OUT5RMIX_VOL1 [6:0]
0080h
0000h
OUT5LMIX_SRC4 [7:0]
OUT5LMIX_VOL4 [6:0]
0080h
0000h
OUT5LMIX_SRC3 [7:0]
OUT5LMIX_VOL3 [6:0]
0080h
0000h
OUT5LMIX_SRC2 [7:0]
OUT5LMIX_VOL2 [6:0]
0080h
0000h
OUT5LMIX_SRC1 [7:0]
OUT5LMIX_VOL1 [6:0]
0080h
0
0080h
241
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1808
(710h)
R1809
(711h)
R1810
(712h)
R1811
(713h)
R1812
(714h)
R1813
(715h)
R1814
(716h)
R1815
(717h)
R1816
(718h)
R1817
(719h)
R1818
(71Ah)
R1819
(71Bh)
R1820
(71Ch)
R1821
(71Dh)
R1822
(71Eh)
R1823
(71Fh)
R1824
(720h)
R1825
(721h)
R1826
(722h)
R1827
(723h)
R1828
(724h)
R1829
(725h)
R1830
(726h)
R1831
(727h)
R1832
(728h)
R1833
(729h)
R1834
(72Ah)
R1835
(72Bh)
R1836
(72Ch)
R1837
(72Dh)
R1838
(72Eh)
R1839
(72Fh)
R1856
(740h)
R1857
(741h)
R1858
(742h)
R1859
(743h)
R1860
(744h)
R1861
(745h)
242
Name
AIF1TX3MIX_Input_1_
Source
AIF1TX3MIX_Input_1_
Volume
AIF1TX3MIX_Input_2_
Source
AIF1TX3MIX_Input_2_
Volume
AIF1TX3MIX_Input_3_
Source
AIF1TX3MIX_Input_3_
Volume
AIF1TX3MIX_Input_4_
Source
AIF1TX3MIX_Input_4_
Volume
AIF1TX4MIX_Input_1_
Source
AIF1TX4MIX_Input_1_
Volume
AIF1TX4MIX_Input_2_
Source
AIF1TX4MIX_Input_2_
Volume
AIF1TX4MIX_Input_3_
Source
AIF1TX4MIX_Input_3_
Volume
AIF1TX4MIX_Input_4_
Source
AIF1TX4MIX_Input_4_
Volume
AIF1TX5MIX_Input_1_
Source
AIF1TX5MIX_Input_1_
Volume
AIF1TX5MIX_Input_2_
Source
AIF1TX5MIX_Input_2_
Volume
AIF1TX5MIX_Input_3_
Source
AIF1TX5MIX_Input_3_
Volume
AIF1TX5MIX_Input_4_
Source
AIF1TX5MIX_Input_4_
Volume
AIF1TX6MIX_Input_1_
Source
AIF1TX6MIX_Input_1_
Volume
AIF1TX6MIX_Input_2_
Source
AIF1TX6MIX_Input_2_
Volume
AIF1TX6MIX_Input_3_
Source
AIF1TX6MIX_Input_3_
Volume
AIF1TX6MIX_Input_4_
Source
AIF1TX6MIX_Input_4_
Volume
AIF2TX1MIX_Input_1_
Source
AIF2TX1MIX_Input_1_
Volume
AIF2TX1MIX_Input_2_
Source
AIF2TX1MIX_Input_2_
Volume
AIF2TX1MIX_Input_3_
Source
AIF2TX1MIX_Input_3_
Volume
15
14
13
12
11
10
9
8
AIF1TX3MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX3MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX3MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX3MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX4MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX4MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX4MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX4MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX5MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX5MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX5MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX5MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX6MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX6MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX6MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF1TX6MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX1MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX1MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX1MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
AIF1TX3MIX_SRC1 [7:0]
AIF1TX3MIX_VOL1 [6:0]
0000h
AIF1TX3MIX_SRC2 [7:0]
AIF1TX3MIX_VOL2 [6:0]
0
0000h
AIF1TX3MIX_SRC3 [7:0]
AIF1TX3MIX_VOL3 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
AIF2TX1MIX_SRC3 [7:0]
AIF2TX1MIX_VOL3 [6:0]
0080h
0000h
AIF2TX1MIX_SRC2 [7:0]
AIF2TX1MIX_VOL2 [6:0]
0080h
0000h
AIF2TX1MIX_SRC1 [7:0]
AIF2TX1MIX_VOL1 [6:0]
0080h
0000h
AIF1TX6MIX_SRC4 [7:0]
AIF1TX6MIX_VOL4 [6:0]
0080h
0000h
AIF1TX6MIX_SRC3 [7:0]
AIF1TX6MIX_VOL3 [6:0]
0080h
0000h
AIF1TX6MIX_SRC2 [7:0]
AIF1TX6MIX_VOL2 [6:0]
0080h
0000h
AIF1TX6MIX_SRC1 [7:0]
AIF1TX6MIX_VOL1 [6:0]
0080h
0000h
AIF1TX5MIX_SRC4 [7:0]
AIF1TX5MIX_VOL4 [6:0]
0080h
0000h
AIF1TX5MIX_SRC3 [7:0]
AIF1TX5MIX_VOL3 [6:0]
0080h
0000h
AIF1TX5MIX_SRC2 [7:0]
AIF1TX5MIX_VOL2 [6:0]
0080h
0000h
AIF1TX5MIX_SRC1 [7:0]
AIF1TX5MIX_VOL1 [6:0]
0080h
0000h
AIF1TX4MIX_SRC4 [7:0]
AIF1TX4MIX_VOL4 [6:0]
0080h
0000h
AIF1TX4MIX_SRC3 [7:0]
AIF1TX4MIX_VOL3 [6:0]
0080h
0000h
AIF1TX4MIX_SRC2 [7:0]
AIF1TX4MIX_VOL2 [6:0]
0080h
0000h
AIF1TX4MIX_SRC1 [7:0]
AIF1TX4MIX_VOL1 [6:0]
0080h
0000h
AIF1TX3MIX_SRC4 [7:0]
AIF1TX3MIX_VOL4 [6:0]
0080h
0
0080h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1862
(746h)
R1863
(747h)
R1864
(748h)
R1865
(749h)
R1866
(74Ah)
R1867
(74Bh)
R1868
(74Ch)
R1869
(74Dh)
R1870
(74Eh)
R1871
(74Fh)
R1872
(750h)
R1873
(751h)
R1874
(752h)
R1875
(753h)
R1876
(754h)
R1877
(755h)
R1878
(756h)
R1879
(757h)
R1880
(758h)
R1881
(759h)
R1882
(75Ah)
R1883
(75Bh)
R1884
(75Ch)
R1885
(75Dh)
R1886
(75Eh)
R1887
(75Fh)
R1920
(780h)
R1921
(781h)
R1922
(782h)
R1923
(783h)
R1924
(784h)
R1925
(785h)
R1926
(786h)
R1927
(787h)
R1928
(788h)
R1929
(789h)
R1930
(78Ah)
R1931
(78Bh)
Name
AIF2TX1MIX_Input_4_
Source
AIF2TX1MIX_Input_4_
Volume
AIF2TX2MIX_Input_1_
Source
AIF2TX2MIX_Input_1_
Volume
AIF2TX2MIX_Input_2_
Source
AIF2TX2MIX_Input_2_
Volume
AIF2TX2MIX_Input_3_
Source
AIF2TX2MIX_Input_3_
Volume
AIF2TX2MIX_Input_4_
Source
AIF2TX2MIX_Input_4_
Volume
AIF2TX3MIX_Input_1_
Source
AIF2TX3MIX_Input_1_
Volume
AIF2TX3MIX_Input_2_
Source
AIF2TX3MIX_Input_2_
Volume
AIF2TX3MIX_Input_3_
Source
AIF2TX3MIX_Input_3_
Volume
AIF2TX3MIX_Input_4_
Source
AIF2TX3MIX_Input_4_
Volume
AIF2TX4MIX_Input_1_
Source
AIF2TX4MIX_Input_1_
Volume
AIF2TX4MIX_Input_2_
Source
AIF2TX4MIX_Input_2_
Volume
AIF2TX4MIX_Input_3_
Source
AIF2TX4MIX_Input_3_
Volume
AIF2TX4MIX_Input_4_
Source
AIF2TX4MIX_Input_4_
Volume
AIF3TX1MIX_Input_1_
Source
AIF3TX1MIX_Input_1_
Volume
AIF3TX1MIX_Input_2_
Source
AIF3TX1MIX_Input_2_
Volume
AIF3TX1MIX_Input_3_
Source
AIF3TX1MIX_Input_3_
Volume
AIF3TX1MIX_Input_4_
Source
AIF3TX1MIX_Input_4_
Volume
AIF3TX2MIX_Input_1_
Source
AIF3TX2MIX_Input_1_
Volume
AIF3TX2MIX_Input_2_
Source
AIF3TX2MIX_Input_2_
Volume
DS1137PP1
15
14
13
12
11
10
9
8
AIF2TX1MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX2MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX2MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX2MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX2MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX3MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX3MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX3MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX3MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX4MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX4MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX4MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF2TX4MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX1MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX1MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX1MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX1MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX2MI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX2MI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
AIF2TX1MIX_SRC4 [7:0]
AIF2TX1MIX_VOL4 [6:0]
0000h
AIF2TX2MIX_SRC1 [7:0]
AIF2TX2MIX_VOL1 [6:0]
0
0000h
AIF2TX2MIX_SRC2 [7:0]
AIF2TX2MIX_VOL2 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
AIF3TX2MIX_SRC2 [7:0]
AIF3TX2MIX_VOL2 [6:0]
0080h
0000h
AIF3TX2MIX_SRC1 [7:0]
AIF3TX2MIX_VOL1 [6:0]
0080h
0000h
AIF3TX1MIX_SRC4 [7:0]
AIF3TX1MIX_VOL4 [6:0]
0080h
0000h
AIF3TX1MIX_SRC3 [7:0]
AIF3TX1MIX_VOL3 [6:0]
0080h
0000h
AIF3TX1MIX_SRC2 [7:0]
AIF3TX1MIX_VOL2 [6:0]
0080h
0000h
AIF3TX1MIX_SRC1 [7:0]
AIF3TX1MIX_VOL1 [6:0]
0080h
0000h
AIF2TX4MIX_SRC4 [7:0]
AIF2TX4MIX_VOL4 [6:0]
0080h
0000h
AIF2TX4MIX_SRC3 [7:0]
AIF2TX4MIX_VOL3 [6:0]
0080h
0000h
AIF2TX4MIX_SRC2 [7:0]
AIF2TX4MIX_VOL2 [6:0]
0080h
0000h
AIF2TX4MIX_SRC1 [7:0]
AIF2TX4MIX_VOL1 [6:0]
0080h
0000h
AIF2TX3MIX_SRC4 [7:0]
AIF2TX3MIX_VOL4 [6:0]
0080h
0000h
AIF2TX3MIX_SRC3 [7:0]
AIF2TX3MIX_VOL3 [6:0]
0080h
0000h
AIF2TX3MIX_SRC2 [7:0]
AIF2TX3MIX_VOL2 [6:0]
0080h
0000h
AIF2TX3MIX_SRC1 [7:0]
AIF2TX3MIX_VOL1 [6:0]
0080h
0000h
AIF2TX2MIX_SRC4 [7:0]
AIF2TX2MIX_VOL4 [6:0]
0080h
0000h
AIF2TX2MIX_SRC3 [7:0]
AIF2TX2MIX_VOL3 [6:0]
0080h
0
0080h
243
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R1932
(78Ch)
R1933
(78Dh)
R1934
(78Eh)
R1935
(78Fh)
R2048
(800h)
R2049
(801h)
R2056
(808h)
R2057
(809h)
R2176
(880h)
R2177
(881h)
R2178
(882h)
R2179
(883h)
R2180
(884h)
R2181
(885h)
R2182
(886h)
R2183
(887h)
R2184
(888h)
R2185
(889h)
R2186
(88Ah)
R2187
(88Bh)
R2188
(88Ch)
R2189
(88Dh)
R2190
(88Eh)
R2191
(88Fh)
R2192
(890h)
R2193
(891h)
R2194
(892h)
R2195
(893h)
R2196
(894h)
R2197
(895h)
R2198
(896h)
R2199
(897h)
R2200
(898h)
R2201
(899h)
R2202
(89Ah)
R2203
(89Bh)
R2204
(89Ch)
R2205
(89Dh)
244
Name
AIF3TX2MIX_Input_3_
Source
AIF3TX2MIX_Input_3_
Volume
AIF3TX2MIX_Input_4_
Source
AIF3TX2MIX_Input_4_
Volume
SPDIF1TX1MIX_Input_
1_Source
SPDIF1TX1MIX_Input_
1_Volume
SPDIF1TX2MIX_Input_
1_Source
SPDIF1TX2MIX_Input_
1_Volume
EQ1MIX_Input_1_
Source
EQ1MIX_Input_1_
Volume
EQ1MIX_Input_2_
Source
EQ1MIX_Input_2_
Volume
EQ1MIX_Input_3_
Source
EQ1MIX_Input_3_
Volume
EQ1MIX_Input_4_
Source
EQ1MIX_Input_4_
Volume
EQ2MIX_Input_1_
Source
EQ2MIX_Input_1_
Volume
EQ2MIX_Input_2_
Source
EQ2MIX_Input_2_
Volume
EQ2MIX_Input_3_
Source
EQ2MIX_Input_3_
Volume
EQ2MIX_Input_4_
Source
EQ2MIX_Input_4_
Volume
EQ3MIX_Input_1_
Source
EQ3MIX_Input_1_
Volume
EQ3MIX_Input_2_
Source
EQ3MIX_Input_2_
Volume
EQ3MIX_Input_3_
Source
EQ3MIX_Input_3_
Volume
EQ3MIX_Input_4_
Source
EQ3MIX_Input_4_
Volume
EQ4MIX_Input_1_
Source
EQ4MIX_Input_1_
Volume
EQ4MIX_Input_2_
Source
EQ4MIX_Input_2_
Volume
EQ4MIX_Input_3_
Source
EQ4MIX_Input_3_
Volume
15
14
13
12
11
10
9
8
AIF3TX2MI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIF3TX2MI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPDIF1TX
1_STS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPDIF1TX
2_STS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ1MIX_
STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ1MIX_
STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ1MIX_
STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ1MIX_
STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ2MIX_
STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ2MIX_
STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ2MIX_
STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ2MIX_
STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ3MIX_
STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ3MIX_
STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ3MIX_
STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ3MIX_
STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ4MIX_
STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ4MIX_
STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EQ4MIX_
STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
AIF3TX2MIX_SRC3 [7:0]
AIF3TX2MIX_VOL3 [6:0]
0000h
AIF3TX2MIX_SRC4 [7:0]
AIF3TX2MIX_VOL4 [6:0]
0
0000h
SPDIF1TX1_SRC [7:0]
SPDIF1TX1_VOL [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
EQ4MIX_SRC3 [7:0]
EQ4MIX_VOL3 [6:0]
0080h
0000h
EQ4MIX_SRC2 [7:0]
EQ4MIX_VOL2 [6:0]
0080h
0000h
EQ4MIX_SRC1 [7:0]
EQ4MIX_VOL1 [6:0]
0080h
0000h
EQ3MIX_SRC4 [7:0]
EQ3MIX_VOL4 [6:0]
0080h
0000h
EQ3MIX_SRC3 [7:0]
EQ3MIX_VOL3 [6:0]
0080h
0000h
EQ3MIX_SRC2 [7:0]
EQ3MIX_VOL2 [6:0]
0080h
0000h
EQ3MIX_SRC1 [7:0]
EQ3MIX_VOL1 [6:0]
0080h
0000h
EQ2MIX_SRC4 [7:0]
EQ2MIX_VOL4 [6:0]
0080h
0000h
EQ2MIX_SRC3 [7:0]
EQ2MIX_VOL3 [6:0]
0080h
0000h
EQ2MIX_SRC2 [7:0]
EQ2MIX_VOL2 [6:0]
0080h
0000h
EQ2MIX_SRC1 [7:0]
EQ2MIX_VOL1 [6:0]
0080h
0000h
EQ1MIX_SRC4 [7:0]
EQ1MIX_VOL4 [6:0]
0080h
0000h
EQ1MIX_SRC3 [7:0]
EQ1MIX_VOL3 [6:0]
0080h
0000h
EQ1MIX_SRC2 [7:0]
EQ1MIX_VOL2 [6:0]
0080h
0000h
EQ1MIX_SRC1 [7:0]
EQ1MIX_VOL1 [6:0]
0080h
0000h
SPDIF1TX2_SRC [7:0]
SPDIF1TX2_VOL [6:0]
0080h
0
0080h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R2206
(89Eh)
R2207
(89Fh)
R2240
(8C0h)
R2241
(8C1h)
R2242
(8C2h)
R2243
(8C3h)
R2244
(8C4h)
R2245
(8C5h)
R2246
(8C6h)
R2247
(8C7h)
R2248
(8C8h)
R2249
(8C9h)
R2250
(8CAh)
R2251
(8CBh)
R2252
(8CCh)
R2253
(8CDh)
R2254
(8CEh)
R2255
(8CFh)
R2256
(8D0h)
R2257
(8D1h)
R2258
(8D2h)
R2259
(8D3h)
R2260
(8D4h)
R2261
(8D5h)
R2262
(8D6h)
R2263
(8D7h)
R2264
(8D8h)
R2265
(8D9h)
R2266
(8DAh)
R2267
(8DBh)
R2268
(8DCh)
R2269
(8DDh)
R2270
(8DEh)
R2271
(8DFh)
R2304
(900h)
R2305
(901h)
R2306
(902h)
R2307
(903h)
Name
EQ4MIX_Input_4_
Source
EQ4MIX_Input_4_
Volume
DRC1LMIX_Input_1_
Source
DRC1LMIX_Input_1_
Volume
DRC1LMIX_Input_2_
Source
DRC1LMIX_Input_2_
Volume
DRC1LMIX_Input_3_
Source
DRC1LMIX_Input_3_
Volume
DRC1LMIX_Input_4_
Source
DRC1LMIX_Input_4_
Volume
DRC1RMIX_Input_1_
Source
DRC1RMIX_Input_1_
Volume
DRC1RMIX_Input_2_
Source
DRC1RMIX_Input_2_
Volume
DRC1RMIX_Input_3_
Source
DRC1RMIX_Input_3_
Volume
DRC1RMIX_Input_4_
Source
DRC1RMIX_Input_4_
Volume
DRC2LMIX_Input_1_
Source
DRC2LMIX_Input_1_
Volume
DRC2LMIX_Input_2_
Source
DRC2LMIX_Input_2_
Volume
DRC2LMIX_Input_3_
Source
DRC2LMIX_Input_3_
Volume
DRC2LMIX_Input_4_
Source
DRC2LMIX_Input_4_
Volume
DRC2RMIX_Input_1_
Source
DRC2RMIX_Input_1_
Volume
DRC2RMIX_Input_2_
Source
DRC2RMIX_Input_2_
Volume
DRC2RMIX_Input_3_
Source
DRC2RMIX_Input_3_
Volume
DRC2RMIX_Input_4_
Source
DRC2RMIX_Input_4_
Volume
HPLP1MIX_Input_1_
Source
HPLP1MIX_Input_1_
Volume
HPLP1MIX_Input_2_
Source
HPLP1MIX_Input_2_
Volume
DS1137PP1
15
14
13
12
11
10
9
8
EQ4MIX_
STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1RMI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1RMI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1RMI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC1RMI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2RMI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2RMI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2RMI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC2RMI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF1MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF1MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
EQ4MIX_SRC4 [7:0]
EQ4MIX_VOL4 [6:0]
0000h
DRC1LMIX_SRC1 [7:0]
DRC1LMIX_VOL1 [6:0]
0
0000h
DRC1LMIX_SRC2 [7:0]
DRC1LMIX_VOL2 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
LHPF1MIX_SRC2 [7:0]
LHPF1MIX_VOL2 [6:0]
0080h
0000h
LHPF1MIX_SRC1 [7:0]
LHPF1MIX_VOL1 [6:0]
0080h
0000h
DRC2RMIX_SRC4 [7:0]
DRC2RMIX_VOL4 [6:0]
0080h
0000h
DRC2RMIX_SRC3 [7:0]
DRC2RMIX_VOL3 [6:0]
0080h
0000h
DRC2RMIX_SRC2 [7:0]
DRC2RMIX_VOL2 [6:0]
0080h
0000h
DRC2RMIX_SRC1 [7:0]
DRC2RMIX_VOL1 [6:0]
0080h
0000h
DRC2LMIX_SRC4 [7:0]
DRC2LMIX_VOL4 [6:0]
0080h
0000h
DRC2LMIX_SRC3 [7:0]
DRC2LMIX_VOL3 [6:0]
0080h
0000h
DRC2LMIX_SRC2 [7:0]
DRC2LMIX_VOL2 [6:0]
0080h
0000h
DRC2LMIX_SRC1 [7:0]
DRC2LMIX_VOL1 [6:0]
0080h
0000h
DRC1RMIX_SRC4 [7:0]
DRC1RMIX_VOL4 [6:0]
0080h
0000h
DRC1RMIX_SRC3 [7:0]
DRC1RMIX_VOL3 [6:0]
0080h
0000h
DRC1RMIX_SRC2 [7:0]
DRC1RMIX_VOL2 [6:0]
0080h
0000h
DRC1RMIX_SRC1 [7:0]
DRC1RMIX_VOL1 [6:0]
0080h
0000h
DRC1LMIX_SRC4 [7:0]
DRC1LMIX_VOL4 [6:0]
0080h
0000h
DRC1LMIX_SRC3 [7:0]
DRC1LMIX_VOL3 [6:0]
0080h
0
0080h
245
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R2308
(904h)
R2309
(905h)
R2310
(906h)
R2311
(907h)
R2312
(908h)
R2313
(909h)
R2314
(90Ah)
R2315
(90Bh)
R2316
(90Ch)
R2317
(90Dh)
R2318
(90Eh)
R2319
(90Fh)
R2320
(910h)
R2321
(911h)
R2322
(912h)
R2323
(913h)
R2324
(914h)
R2325
(915h)
R2326
(916h)
R2327
(917h)
R2328
(918h)
R2329
(919h)
R2330
(91Ah)
R2331
(91Bh)
R2332
(91Ch)
R2333
(91Dh)
R2334
(91Eh)
R2335
(91Fh)
R2368
(940h)
R2369
(941h)
R2370
(942h)
R2371
(943h)
R2372
(944h)
R2373
(945h)
R2374
(946h)
R2375
(947h)
R2376
(948h)
R2377
(949h)
246
Name
HPLP1MIX_Input_3_
Source
HPLP1MIX_Input_3_
Volume
HPLP1MIX_Input_4_
Source
HPLP1MIX_Input_4_
Volume
HPLP2MIX_Input_1_
Source
HPLP2MIX_Input_1_
Volume
HPLP2MIX_Input_2_
Source
HPLP2MIX_Input_2_
Volume
HPLP2MIX_Input_3_
Source
HPLP2MIX_Input_3_
Volume
HPLP2MIX_Input_4_
Source
HPLP2MIX_Input_4_
Volume
HPLP3MIX_Input_1_
Source
HPLP3MIX_Input_1_
Volume
HPLP3MIX_Input_2_
Source
HPLP3MIX_Input_2_
Volume
HPLP3MIX_Input_3_
Source
HPLP3MIX_Input_3_
Volume
HPLP3MIX_Input_4_
Source
HPLP3MIX_Input_4_
Volume
HPLP4MIX_Input_1_
Source
HPLP4MIX_Input_1_
Volume
HPLP4MIX_Input_2_
Source
HPLP4MIX_Input_2_
Volume
HPLP4MIX_Input_3_
Source
HPLP4MIX_Input_3_
Volume
HPLP4MIX_Input_4_
Source
HPLP4MIX_Input_4_
Volume
DSP1LMIX_Input_1_
Source
DSP1LMIX_Input_1_
Volume
DSP1LMIX_Input_2_
Source
DSP1LMIX_Input_2_
Volume
DSP1LMIX_Input_3_
Source
DSP1LMIX_Input_3_
Volume
DSP1LMIX_Input_4_
Source
DSP1LMIX_Input_4_
Volume
DSP1RMIX_Input_1_
Source
DSP1RMIX_Input_1_
Volume
15
14
13
12
11
10
9
8
LHPF1MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF1MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF2MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF2MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF2MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF2MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF3MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF3MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF3MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF3MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF4MIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF4MIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF4MIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LHPF4MIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1LMIX
_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1LMIX
_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1LMIX
_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1LMIX
_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1RMI
X_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Default
0000h
0
0080h
LHPF1MIX_SRC3 [7:0]
LHPF1MIX_VOL3 [6:0]
0000h
LHPF1MIX_SRC4 [7:0]
LHPF1MIX_VOL4 [6:0]
0
0000h
LHPF2MIX_SRC1 [7:0]
LHPF2MIX_VOL1 [6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0080h
0000h
DSP1RMIX_SRC1 [7:0]
DSP1RMIX_VOL1 [6:0]
0080h
0000h
DSP1LMIX_SRC4 [7:0]
DSP1LMIX_VOL4 [6:0]
0080h
0000h
DSP1LMIX_SRC3 [7:0]
DSP1LMIX_VOL3 [6:0]
0080h
0000h
DSP1LMIX_SRC2 [7:0]
DSP1LMIX_VOL2 [6:0]
0080h
0000h
DSP1LMIX_SRC1 [7:0]
DSP1LMIX_VOL1 [6:0]
0080h
0000h
LHPF4MIX_SRC4 [7:0]
LHPF4MIX_VOL4 [6:0]
0080h
0000h
LHPF4MIX_SRC3 [7:0]
LHPF4MIX_VOL3 [6:0]
0080h
0000h
LHPF4MIX_SRC2 [7:0]
LHPF4MIX_VOL2 [6:0]
0080h
0000h
LHPF4MIX_SRC1 [7:0]
LHPF4MIX_VOL1 [6:0]
0080h
0000h
LHPF3MIX_SRC4 [7:0]
LHPF3MIX_VOL4 [6:0]
0080h
0000h
LHPF3MIX_SRC3 [7:0]
LHPF3MIX_VOL3 [6:0]
0080h
0000h
LHPF3MIX_SRC2 [7:0]
LHPF3MIX_VOL2 [6:0]
0080h
0000h
LHPF3MIX_SRC1 [7:0]
LHPF3MIX_VOL1 [6:0]
0080h
0000h
LHPF2MIX_SRC4 [7:0]
LHPF2MIX_VOL4 [6:0]
0080h
0000h
LHPF2MIX_SRC3 [7:0]
LHPF2MIX_VOL3 [6:0]
0080h
0000h
LHPF2MIX_SRC2 [7:0]
LHPF2MIX_VOL2 [6:0]
0080h
0
0080h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R2378
(94Ah)
R2379
(94Bh)
R2380
(94Ch)
R2381
(94Dh)
R2382
(94Eh)
R2383
(94Fh)
R2384
(950h)
R2392
(958h)
R2400
(960h)
R2408
(968h)
R2416
(970h)
R2424
(978h)
R2816
(B00h)
R2824
(B08h)
R2832
(B10h)
R2840
(B18h)
R2848
(B20h)
R2856
(B28h)
R2864
(B30h)
R2872
(B38h)
R2880
(B40h)
R2888
(B48h)
R2896
(B50h)
R2904
(B58h)
R2912
(B60h)
R2920
(B68h)
R2928
(B70h)
R2936
(B78h)
R3584
(E00h)
R3585
(E01h)
R3600
(E10h)
R3601
(E11h)
R3602
(E12h)
R3603
(E13h)
R3604
(E14h)
R3605
(E15h)
R3606
(E16h)
R3607
(E17h)
Name
DSP1RMIX_Input_2_
Source
DSP1RMIX_Input_2_
Volume
DSP1RMIX_Input_3_
Source
DSP1RMIX_Input_3_
Volume
DSP1RMIX_Input_4_
Source
DSP1RMIX_Input_4_
Volume
DSP1AUX1MIX_Input_
1_Source
DSP1AUX2MIX_Input_
1_Source
DSP1AUX3MIX_Input_
1_Source
DSP1AUX4MIX_Input_
1_Source
DSP1AUX5MIX_Input_
1_Source
DSP1AUX6MIX_Input_
1_Source
ISRC1DEC1MIX_Input_
1_Source
ISRC1DEC2MIX_Input_
1_Source
ISRC1DEC3MIX_Input_
1_Source
ISRC1DEC4MIX_Input_
1_Source
ISRC1INT1MIX_Input_
1_Source
ISRC1INT2MIX_Input_
1_Source
ISRC1INT3MIX_Input_
1_Source
ISRC1INT4MIX_Input_
1_Source
ISRC2DEC1MIX_Input_
1_Source
ISRC2DEC2MIX_Input_
1_Source
ISRC2DEC3MIX_Input_
1_Source
ISRC2DEC4MIX_Input_
1_Source
ISRC2INT1MIX_Input_
1_Source
ISRC2INT2MIX_Input_
1_Source
ISRC2INT3MIX_Input_
1_Source
ISRC2INT4MIX_Input_
1_Source
FX_Ctrl1
15
14
13
12
11
10
9
8
DSP1RMI
X_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1RMI
X_STS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1RMI
X_STS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1AUX
1_STS
0
0
0
0
0
0
0
DSP1AUX1_SRC [7:0]
0000h
DSP1AUX
2_STS
0
0
0
0
0
0
0
DSP1AUX2_SRC [7:0]
0000h
DSP1AUX
3_STS
0
0
0
0
0
0
0
DSP1AUX3_SRC [7:0]
0000h
DSP1AUX
4_STS
0
0
0
0
0
0
0
DSP1AUX4_SRC [7:0]
0000h
DSP1AUX
5_STS
0
0
0
0
0
0
0
DSP1AUX5_SRC [7:0]
0000h
DSP1AUX
6_STS
0
0
0
0
0
0
0
DSP1AUX6_SRC [7:0]
0000h
ISRC1DEC
1_STS
0
0
0
0
0
0
0
ISRC1DEC1_SRC [7:0]
0000h
ISRC1DEC
2_STS
0
0
0
0
0
0
0
ISRC1DEC2_SRC [7:0]
0000h
ISRC1DEC
3_STS
0
0
0
0
0
0
0
ISRC1DEC3_SRC [7:0]
0000h
ISRC1DEC
4_STS
0
0
0
0
0
0
0
ISRC1DEC4_SRC [7:0]
0000h
ISRC1INT
1_STS
0
0
0
0
0
0
0
ISRC1INT1_SRC [7:0]
0000h
ISRC1INT
2_STS
0
0
0
0
0
0
0
ISRC1INT2_SRC [7:0]
0000h
ISRC1INT
3_STS
0
0
0
0
0
0
0
ISRC1INT3_SRC [7:0]
0000h
ISRC1INT
4_STS
0
0
0
0
0
0
0
ISRC1INT4_SRC [7:0]
0000h
ISRC2DEC
1_STS
0
0
0
0
0
0
0
ISRC2DEC1_SRC [7:0]
0000h
ISRC2DEC
2_STS
0
0
0
0
0
0
0
ISRC2DEC2_SRC [7:0]
0000h
ISRC2DEC
3_STS
0
0
0
0
0
0
0
ISRC2DEC3_SRC [7:0]
0000h
ISRC2DEC
4_STS
0
0
0
0
0
0
0
ISRC2DEC4_SRC [7:0]
0000h
ISRC2INT
1_STS
0
0
0
0
0
0
0
ISRC2INT1_SRC [7:0]
0000h
ISRC2INT
2_STS
0
0
0
0
0
0
0
ISRC2INT2_SRC [7:0]
0000h
ISRC2INT
3_STS
0
0
0
0
0
0
0
ISRC2INT3_SRC [7:0]
0000h
ISRC2INT
4_STS
0
0
0
0
0
0
0
ISRC2INT4_SRC [7:0]
0000h
0
0
0
0
FX_RATE [3:0]
FX_Ctrl2
7
6
5
4
EQ1_B1_GAIN [4:0]
EQ1_B2_GAIN [4:0]
EQ1_2
EQ1_B4_GAIN [4:0]
EQ1_B5_GAIN [4:0]
2
1
DSP1RMIX_VOL2 [6:0]
0
Default
0000h
0
0080h
0000h
DSP1RMIX_SRC3 [7:0]
DSP1RMIX_VOL3 [6:0]
0
DSP1RMIX_VOL4 [6:0]
0
0
0
0
0
0
0080h
0
0
0
0
0000h
0
0
1
0
0002h
EQ1_ENA
6318h
EQ1_B1_
MODE
6300h
EQ1_B3_GAIN [4:0]
0
0080h
0000h
DSP1RMIX_SRC4 [7:0]
FX_STS [11:0]
EQ1_1
3
DSP1RMIX_SRC2 [7:0]
0
0
0
EQ1_3
EQ1_B1_A [15:0]
0FC8h
EQ1_4
EQ1_B1_B [15:0]
03FEh
EQ1_5
EQ1_B1_PG [15:0]
00E0h
EQ1_6
EQ1_B2_A [15:0]
1EC4h
EQ1_7
EQ1_B2_B [15:0]
F136h
EQ1_8
EQ1_B2_C [15:0]
0409h
DS1137PP1
247
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R3608
(E18h)
R3609
(E19h)
R3610
(E1Ah)
R3611
(E1Bh)
R3612
(E1Ch)
R3613
(E1Dh)
R3614
(E1Eh)
R3615
(E1Fh)
R3616
(E20h)
R3617
(E21h)
R3618
(E22h)
R3619
(E23h)
R3620
(E24h)
R3622
(E26h)
R3623
(E27h)
R3624
(E28h)
R3625
(E29h)
R3626
(E2Ah)
R3627
(E2Bh)
R3628
(E2Ch)
R3629
(E2Dh)
R3630
(E2Eh)
R3631
(E2Fh)
R3632
(E30h)
R3633
(E31h)
R3634
(E32h)
R3635
(E33h)
R3636
(E34h)
R3637
(E35h)
R3638
(E36h)
R3639
(E37h)
R3640
(E38h)
R3641
(E39h)
R3642
(E3Ah)
R3644
(E3Ch)
R3645
(E3Dh)
R3646
(E3Eh)
R3647
(E3Fh)
248
Name
15
14
EQ1_9
13
12
11
10
9
EQ1_B2_PG [15:0]
8
Default
04CCh
EQ1_10
EQ1_B3_A [15:0]
1C9Bh
EQ1_11
EQ1_B3_B [15:0]
F337h
EQ1_12
EQ1_B3_C [15:0]
040Bh
EQ1_13
EQ1_B3_PG [15:0]
0CBBh
EQ1_14
EQ1_B4_A [15:0]
16F8h
EQ1_15
EQ1_B4_B [15:0]
F7D9h
EQ1_16
EQ1_B4_C [15:0]
040Ah
EQ1_17
EQ1_B4_PG [15:0]
1F14h
EQ1_18
EQ1_B5_A [15:0]
058Ch
EQ1_19
EQ1_B5_B [15:0]
0563h
EQ1_20
EQ1_B5_PG [15:0]
4000h
EQ1_21
EQ1_B1_C [15:0]
0B75h
EQ2_1
EQ2_B1_GAIN [4:0]
EQ2_B2_GAIN [4:0]
EQ2_2
EQ2_B4_GAIN [4:0]
EQ2_B5_GAIN [4:0]
7
6
5
4
3
2
1
EQ2_B3_GAIN [4:0]
0
0
0
0
0
0
EQ2_ENA
6318h
EQ2_B1_
MODE
6300h
EQ2_3
EQ2_B1_A [15:0]
0FC8h
EQ2_4
EQ2_B1_B [15:0]
03FEh
EQ2_5
EQ2_B1_PG [15:0]
00E0h
EQ2_6
EQ2_B2_A [15:0]
1EC4h
EQ2_7
EQ2_B2_B [15:0]
F136h
EQ2_8
EQ2_B2_C [15:0]
0409h
EQ2_9
EQ2_B2_PG [15:0]
04CCh
EQ2_10
EQ2_B3_A [15:0]
1C9Bh
EQ2_11
EQ2_B3_B [15:0]
F337h
EQ2_12
EQ2_B3_C [15:0]
040Bh
EQ2_13
EQ2_B3_PG [15:0]
0CBBh
EQ2_14
EQ2_B4_A [15:0]
16F8h
EQ2_15
EQ2_B4_B [15:0]
F7D9h
EQ2_16
EQ2_B4_C [15:0]
040Ah
EQ2_17
EQ2_B4_PG [15:0]
1F14h
EQ2_18
EQ2_B5_A [15:0]
058Ch
EQ2_19
EQ2_B5_B [15:0]
0563h
EQ2_20
EQ2_B5_PG [15:0]
4000h
EQ2_21
EQ2_B1_C [15:0]
0B75h
EQ3_1
EQ3_B1_GAIN [4:0]
EQ3_B2_GAIN [4:0]
EQ3_2
EQ3_B4_GAIN [4:0]
EQ3_B5_GAIN [4:0]
EQ3_B3_GAIN [4:0]
0
0
0
0
0
EQ3_ENA
6318h
EQ3_B1_
MODE
6300h
EQ3_3
EQ3_B1_A [15:0]
0FC8h
EQ3_4
EQ3_B1_B [15:0]
03FEh
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R3648
(E40h)
R3649
(E41h)
R3650
(E42h)
R3651
(E43h)
R3652
(E44h)
R3653
(E45h)
R3654
(E46h)
R3655
(E47h)
R3656
(E48h)
R3657
(E49h)
R3658
(E4Ah)
R3659
(E4Bh)
R3660
(E4Ch)
R3661
(E4Dh)
R3662
(E4Eh)
R3663
(E4Fh)
R3664
(E50h)
R3666
(E52h)
R3667
(E53h)
R3668
(E54h)
R3669
(E55h)
R3670
(E56h)
R3671
(E57h)
R3672
(E58h)
R3673
(E59h)
R3674
(E5Ah)
R3675
(E5Bh)
R3676
(E5Ch)
R3677
(E5Dh)
R3678
(E5Eh)
R3679
(E5Fh)
R3680
(E60h)
R3681
(E61h)
R3682
(E62h)
R3683
(E63h)
R3684
(E64h)
R3685
(E65h)
R3686
(E66h)
Name
15
14
EQ3_5
13
12
11
10
9
EQ3_B1_PG [15:0]
8
Default
00E0h
EQ3_6
EQ3_B2_A [15:0]
1EC4h
EQ3_7
EQ3_B2_B [15:0]
F136h
EQ3_8
EQ3_B2_C [15:0]
0409h
EQ3_9
EQ3_B2_PG [15:0]
04CCh
EQ3_10
EQ3_B3_A [15:0]
1C9Bh
EQ3_11
EQ3_B3_B [15:0]
F337h
EQ3_12
EQ3_B3_C [15:0]
040Bh
EQ3_13
EQ3_B3_PG [15:0]
0CBBh
EQ3_14
EQ3_B4_A [15:0]
16F8h
EQ3_15
EQ3_B4_B [15:0]
F7D9h
EQ3_16
EQ3_B4_C [15:0]
040Ah
EQ3_17
EQ3_B4_PG [15:0]
1F14h
EQ3_18
EQ3_B5_A [15:0]
058Ch
EQ3_19
EQ3_B5_B [15:0]
0563h
EQ3_20
EQ3_B5_PG [15:0]
4000h
EQ3_21
EQ3_B1_C [15:0]
0B75h
EQ4_1
EQ4_B1_GAIN [4:0]
EQ4_B2_GAIN [4:0]
EQ4_2
EQ4_B4_GAIN [4:0]
EQ4_B5_GAIN [4:0]
7
6
5
4
3
2
1
EQ4_B3_GAIN [4:0]
0
0
0
0
0
0
EQ4_ENA
6318h
EQ4_B1_
MODE
6300h
EQ4_3
EQ4_B1_A [15:0]
0FC8h
EQ4_4
EQ4_B1_B [15:0]
03FEh
EQ4_5
EQ4_B1_PG [15:0]
00E0h
EQ4_6
EQ4_B2_A [15:0]
1EC4h
EQ4_7
EQ4_B2_B [15:0]
F136h
EQ4_8
EQ4_B2_C [15:0]
0409h
EQ4_9
EQ4_B2_PG [15:0]
04CCh
EQ4_10
EQ4_B3_A [15:0]
1C9Bh
EQ4_11
EQ4_B3_B [15:0]
F337h
EQ4_12
EQ4_B3_C [15:0]
040Bh
EQ4_13
EQ4_B3_PG [15:0]
0CBBh
EQ4_14
EQ4_B4_A [15:0]
16F8h
EQ4_15
EQ4_B4_B [15:0]
F7D9h
EQ4_16
EQ4_B4_C [15:0]
040Ah
EQ4_17
EQ4_B4_PG [15:0]
1F14h
EQ4_18
EQ4_B5_A [15:0]
058Ch
EQ4_19
EQ4_B5_B [15:0]
0563h
EQ4_20
EQ4_B5_PG [15:0]
4000h
EQ4_21
EQ4_B1_C [15:0]
0B75h
DS1137PP1
249
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R3712 DRC1_ctrl1
(E80h)
15
14
13
12
DRC1_SIG_DET_RMS [4:0]
R3713
(E81h)
R3714
(E82h)
R3715
(E83h)
R3716
(E84h)
R3720
(E88h)
DRC1_ctrl2
R3721
(E89h)
R3722
(E8Ah)
R3723
(E8Bh)
R3724
(E8Ch)
R3776
(EC0h)
R3777
(EC1h)
R3780
(EC4h)
R3781
(EC5h)
R3784
(EC8h)
R3785
(EC9h)
R3788
(ECCh)
R3789
(ECDh)
R3824
(EF0h)
R3825
(EF1h)
R3826
(EF2h)
DRC2_ctrl2
R3827
(EF3h)
R3828
(EF4h)
R3829
(EF5h)
ISRC2_CTRL_1
0
ISRC2_FSH [3:0]
ISRC2_CTRL_2
0
ISRC2_FSL [3:0]
R5632
(1600h)
R5633
(1601h)
R5634
(1602h)
R5635
(1603h)
R5636
(1604h)
R5637
(1605h)
R5638
(1606h)
R5639
(1607h)
R5888
(1700h)
R5889
(1701h)
R5890
(1702h)
R5891
(1703h)
R5892
(1704h)
ADSP2_IRQ0
0
0
0
ADSP2_IRQ1
0
0
ADSP2_IRQ2
0
ADSP2_IRQ3
250
0
DRC1_ctrl3
0
0
DRC1_NG_MINGAIN [3:0]
11
0
0
0
0
0
DRC1_ctrl5
0
0
0
0
0
DRC2_SIG_DET_RMS [4:0]
0
DRC2_ctrl3
0
9
0
DRC2_NG_MINGAIN [3:0]
0
5
4
3
DRC1_HI_COMP [2:0]
DRC1_KNEE2_IP [4:0]
DRC2_NG_EXP [1:0] DRC2_QR_THR [1:0] DRC2_QR_DCY [1:0]
0
0
0
0
DRC2_ctrl5
0
0
0
0
0
0
HPLPF1_1
0
0
0
0
0
0
2
1
0
DRC1_LO_COMP [2:0]
DRC2_KNEE2_IP [4:0]
0
0
0
0
0
0
0
0
0
0
0
0
HPLPF2_2
0
0
0
0
0
0
0
0
HPLPF3_2
0
0
0000h
DRC2L_ DRC2R_
ENA
ENA
0018h
DRC2_MAXGAIN [1:0]
0933h
DRC2_LO_COMP [2:0]
0
0
0
0
0
0
HPLPF4_2
0
0
0018h
DRC2_KNEE_OP [4:0]
0000h
DRC2_KNEE2_OP [4:0]
0000h
0
0
LHPF1_
MODE
LHPF1_
ENA
0000h
0000h
0
0
0
0
0
LHPF2_
MODE
LHPF2_
ENA
0000h
0000h
0
0
0
0
0
LHPF3_
MODE
LHPF3_
ENA
0000h
0000h
LHPF3_COEFF [15:0]
0
0018h
DRC1_KNEE2_OP [4:0]
LHPF2_COEFF [15:0]
0
0933h
0000h
LHPF1_COEFF [15:0]
0
Default
0018h
DRC1_KNEE_OP [4:0]
DRC2_HI_COMP [2:0]
DRC2_KNEE_IP [5:0]
HPLPF1_2
HPLPF4_1
6
DRC2_SIG_DET_PK DRC2_ DRC2_ DRC2_ DRC2_ DRC2_QR DRC2_
0
[1:0]
NG_ENA SIG_DET_ SIG_DET KNEE2_
ANTICLIP
MODE
OP_ENA
DRC2_ATK [3:0]
DRC2_DCY [3:0]
DRC2_MINGAIN [2:0]
0
HPLPF3_1
7
DRC1_KNEE_IP [5:0]
DRC2_ctrl4
HPLPF2_1
8
DRC1_NG_EXP [1:0] DRC1_QR_THR [1:0] DRC1_QR_DCY [1:0]
DRC1_ctrl4
DRC2_ctrl1
10
DRC1_SIG_DET_PK DRC1_ DRC1_ DRC1_ DRC1_ DRC1_QR DRC1_ DRC1_ DRC1L_ DRC1R_
[1:0]
NG_ENA SIG_DET_ SIG_DET KNEE2_
ANTICLIP WSEQ_
ENA
ENA
MODE
OP_ENA
SIG_DET_
ENA
DRC1_ATK [3:0]
DRC1_DCY [3:0]
DRC1_MINGAIN [2:0]
DRC1_MAXGAIN [1:0]
0
0
0
0
0
LHPF4_
MODE
LHPF4_
ENA
0000h
0000h
LHPF4_COEFF [15:0]
ISRC1_CTRL_1
0
ISRC1_FSH [3:0]
0
0
0
0
0
0
0
0
0
0
0
0000h
ISRC1_CTRL_2
0
ISRC1_FSL [3:0]
0
0
0
0
0
0
0
0
0
0
1
0001h
0
ISRC1_
DEC2_
ENA
0
ISRC1_
DEC3_
ENA
0
ISRC1_
DEC4_
ENA
0
0
0
0
0
0
0
0000h
0
ISRC1_
DEC1_
ENA
0
0
0
0
0
0
0
0000h
0
0
0
0
0
0
0
0
0
0
1
0001h
0
0
ISRC2_
DEC4_
ENA
0
0
0
0
0
0000h
0
ISRC2_
DEC3_
ENA
0
0
0
ISRC2_
DEC2_
ENA
0
0
0
ISRC2_
DEC1_
ENA
0
0
0
0
0
DSP_IRQ2DSP_IRQ1
0000h
0
0
0
0
0
0
0
0
0
0
0
0
DSP_IRQ4DSP_IRQ3
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_IRQ6DSP_IRQ5
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_IRQ8DSP_IRQ7
0000h
ADSP2_IRQ4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_ DSP_IRQ9
IRQ10
0000h
ADSP2_IRQ5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_
IRQ12
DSP_
IRQ11
0000h
ADSP2_IRQ6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_
IRQ14
DSP_
IRQ13
0000h
ADSP2_IRQ7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP_
IRQ16
DSP_
IRQ15
0000h
ISRC1_CTRL_3
ISRC2_CTRL_3
ISRC1_ ISRC1_ ISRC1_ ISRC1_
INT1_ENA INT2_ENA INT3_ENA INT4_ENA
ISRC2_ ISRC2_ ISRC2_ ISRC2_
INT1_ENA INT2_ENA INT3_ENA INT4_ENA
0
GPIO1_CTRL_1
GP1_LVL GP1_OP_ GP1_DB GP1_POL GP1_IP_
CFG
CFG
0
GPIO1_CTRL_2
GP1_DIR GP1_PU GP1_PD GP1_DRV_STR [1:0]
0
GPIO2_CTRL_1
GP2_LVL GP2_OP_ GP2_DB GP2_POL GP2_IP_
CFG
CFG
0
GPIO2_CTRL_2
GP2_DIR GP2_PU GP2_PD GP2_DRV_STR [1:0]
0
GPIO3_CTRL_1
GP3_LVL GP3_OP_ GP3_DB GP3_POL GP3_IP_
CFG
CFG
0
2801h
GP1_FN [9:0]
0
0
0
0
0
0
0
0
0
0
2801h
GP2_FN [9:0]
0
0
0
0
0
0
GP3_FN [9:0]
E800h
0
0
0
0
E800h
2801h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
R5893
(1705h)
R5894
(1706h)
R5895
(1707h)
R5896
(1708h)
R5897
(1709h)
R5898
(170Ah)
R5899
(170Bh)
R5900
(170Ch)
R5901
(170Dh)
R5902
(170Eh)
R5903
(170Fh)
R5904
(1710h)
R5905
(1711h)
R5906
(1712h)
R5907
(1713h)
R5908
(1714h)
R5909
(1715h)
R5910
(1716h)
R5911
(1717h)
R5912
(1718h)
R5913
(1719h)
R5914
(171Ah)
R5915
(171Bh)
R5916
(171Ch)
R5917
(171Dh)
R6144
(1800h)
Name
GPIO3_CTRL_2
10
9
8
7
6
5
4
3
2
1
0
GP3_DIR GP3_PU GP3_PD GP3_DRV_STR [1:0]
0
0
0
0
0
0
0
0
0
0
0
GPIO4_CTRL_1
GP4_LVL GP4_OP_ GP4_DB GP4_POL GP4_IP_
CFG
CFG
0
GPIO4_CTRL_2
GP4_DIR GP4_PU GP4_PD GP4_DRV_STR [1:0]
0
GPIO5_CTRL_1
GP5_LVL GP5_OP_ GP5_DB GP5_POL GP5_IP_
CFG
CFG
0
GPIO5_CTRL_2
GP5_DIR GP5_PU GP5_PD GP5_DRV_STR [1:0]
0
GPIO6_CTRL_1
GP6_LVL GP6_OP_ GP6_DB GP6_POL GP6_IP_
CFG
CFG
0
GPIO6_CTRL_2
GP6_DIR GP6_PU GP6_PD GP6_DRV_STR [1:0]
0
GPIO7_CTRL_1
GP7_LVL GP7_OP_ GP7_DB GP7_POL GP7_IP_
CFG
CFG
0
GPIO7_CTRL_2
GP7_DIR GP7_PU GP7_PD GP7_DRV_STR [1:0]
0
GPIO8_CTRL_1
GP8_LVL GP8_OP_ GP8_DB GP8_POL GP8_IP_
CFG
CFG
0
GPIO8_CTRL_2
GP8_DIR GP8_PU GP8_PD GP8_DRV_STR [1:0]
0
GPIO9_CTRL_1
GP9_LVL GP9_OP_ GP9_DB GP9_POL GP9_IP_
CFG
CFG
0
GPIO9_CTRL_2
GP9_DIR GP9_PU GP9_PD GP9_DRV_STR [1:0]
0
GPIO10_CTRL_1
GP10_LVL GP10_ GP10_DB
OP_CFG
GP10_ GP10_IP_
POL
CFG
0
GPIO10_CTRL_2
GP10_DIR GP10_PU GP10_PD GP10_DRV_STR [1:0]
0
GPIO11_CTRL_1
GP11_LVL GP11_OP_ GP11_DB GP11_POL GP11_IP_
CFG
CFG
0
GPIO11_CTRL_2
GP11_DIR GP11_PU GP11_PD GP11_DRV_STR [1:0]
0
GPIO12_CTRL_1
GP12_LVL GP12_ GP12_DB
OP_CFG
GP12_ GP12_IP_
POL
CFG
0
GPIO12_CTRL_2
GP12_DIR GP12_PU GP12_PD GP12_DRV_STR [1:0]
0
GPIO13_CTRL_1
GP13_LVL GP13_ GP13_DB
OP_CFG
GP13_ GP13_IP_
POL
CFG
0
GPIO13_CTRL_2
GP13_DIR GP13_PU GP13_PD GP13_DRV_STR [1:0]
0
GPIO14_CTRL_1
GP14_LVL GP14_ GP14_DB
OP_CFG
GP14_ GP14_IP_
POL
CFG
0
GPIO14_CTRL_2
GP14_DIR GP14_PU GP14_PD GP14_DRV_STR [1:0]
0
GPIO15_CTRL_1
GP15_LVL GP15_ GP15_DB
OP_CFG
GP15_ GP15_IP_
POL
CFG
0
GPIO15_CTRL_2
GP15_DIR GP15_PU GP15_PD GP15_DRV_STR [1:0]
0
0
0
0
0
0
0
0
0
0
0
E800h
0
SYSCLK_
FAIL_
EINT1
0
0
BOOT_
DONE_
EINT1
0
0
0
0
0
0
0
0
0000h
0
0
0
0
0
0
0
0000h
0
0
0
0
0
0
0
HPDET_
EINT1
0000h
JD2_
FALL_
EINT1
JD2_
RISE_
EINT1
JD1_
FALL_
EINT1
JD1_
RISE_
EINT1
0000h
IRQ1_Status_1
R6145 IRQ1_Status_2
(1801h)
R6149 IRQ1_Status_6
(1805h)
R6150 IRQ1_Status_7
(1806h)
15
0
14
0
FLL_AO_ DSPCLK_
REF_
ERR_
LOST_
EINT1
EINT1
0
0
13
0
0
12
11
CTRLIF_
0
ERR_
EINT1
SYSCLK_ FLL_AO_
ERR_
LOCK_
EINT1
EINT1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MICDET2_ MICDET1_
EINT1
EINT1
0
0
0
0
0
0
0
0
R6152 IRQ1_Status_9
(1808h)
0
0
0
0
0
0
0
0
0
0
R6154 IRQ1_Status_11
(180Ah)
DSP_
IRQ16_
EINT1
0
DSP_
IRQ15_
EINT1
0
DSP_
IRQ14_
EINT1
0
DSP_
IRQ13_
EINT1
0
DSP_
IRQ12_
EINT1
0
DSP_
IRQ11_
EINT1
0
DSP_
IRQ10_
EINT1
0
DSP_
IRQ9_
EINT1
0
DSP_
IRQ8_
EINT1
0
R6156 IRQ1_Status_13
(180Ch)
0
0
0
0
0
0
0
0
0
R6157 IRQ1_Status_14
(180Dh)
0
0
0
0
0
0
0
0
0
MICD_
MICD_
CLAMP_ CLAMP_
FALL_
RISE_
EINT1
EINT1
0
0
DSP_
DSP_
IRQ7_
IRQ6_
EINT1
EINT1
SPKOUTL
0
_SC_
EINT1
SPKOUTL
0
_ENABLE_
DONE_
EINT1
SPKOUTL
0
_
DISABLE_
DONE_
EINT1
E800h
2801h
0
0
0
0
E800h
2801h
GP15_FN [9:0]
FLL1_
LOCK_
EINT1
E800h
2801h
GP14_FN [9:0]
0
E800h
2801h
GP13_FN [9:0]
0
E800h
2801h
GP12_FN [9:0]
0
E800h
2801h
GP11_FN [9:0]
0
E800h
2801h
GP10_FN [9:0]
0
E800h
2801h
GP9_FN [9:0]
0
E800h
2801h
GP8_FN [9:0]
0
E800h
2801h
GP7_FN [9:0]
0
E800h
2801h
GP6_FN [9:0]
0
DS1137PP1
0
GP5_FN [9:0]
0
R6155 IRQ1_Status_12
(180Bh)
2801h
GP4_FN [9:0]
0
Default
E800h
0
INPUTS_ DRC2_ DRC1_
SIG_DET_ SIG_DET_ SIG_DET_
EINT1
EINT1
EINT1
DSP_
DSP_
DSP_
DSP_
DSP_
IRQ5_
IRQ4_
IRQ3_
IRQ2_
IRQ1_
EINT1
EINT1
EINT1
EINT1
EINT1
0
HP2R_ HP2L_SC_ HP1R_ HP1L_SC_
SC_EINT1 EINT1 SC_EINT1 EINT1
0
0
0
0
0
0
HP1R_
HP1L_
ENABLE_ ENABLE_
DONE_ DONE_
EINT1
EINT1
HP1R_
HP1L_
DISABLE_ DISABLE_
DONE_ DONE_
EINT1
EINT1
0000h
0000h
0000h
0000h
0000h
251
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R6158 IRQ1_Status_15
(180Eh)
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
R6159 IRQ1_Status_16
(180Fh)
0
0
0
0
0
0
0
0
0
0
0
R6160 IRQ1_Status_17
(1810h)
R6164 IRQ1_Status_21
(1814h)
R6165 IRQ1_Status_22
(1815h)
0
GP15_
EINT1
GP14_
EINT1
GP13_
EINT1
GP12_
EINT1
GP11_
EINT1
GP10_
EINT1
GP6_
EINT1
GP5_
EINT1
GP4_
EINT1
GP3_
EINT1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIMER2_ TIMER1_
EINT1
EINT1
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6167 IRQ1_Status_24
(1817h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6168 IRQ1_Status_25
(1818h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6170 IRQ1_Status_27
(181Ah)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6171 IRQ1_Status_28
(181Bh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6173 IRQ1_Status_30
(181Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6174 IRQ1_Status_31
(181Eh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6175 IRQ1_Status_32
(181Fh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
R6176 IRQ1_Status_33
(1820h)
0
0
0
0
0
0
0
0
0
0
0
0
MIF4_
DONE_
EINT1
MIF4_
BLOCK_
EINT1
0
EVENT1_
NOT_
EMPTY_
EINT1
EVENT1_
FULL_
EINT1
EVENT1_
WMARK_
EINT1
DSP1
DMA_
EINT1
DSP1_
START1_
EINT1
DSP1_
START2_
EINT1
DSP1_
BUSY_
EINT1
0
0000h
R6166 IRQ1_Status_23
(1816h)
EVENT2_
NOT_
EMPTY_
EINT1
EVENT2_
FULL_
EINT1
EVENT2_
WMARK_
EINT1
0
0
0
0000h
R6208 IRQ1_Mask_1
(1840h)
0
0
0
IM_
0
IM_BOOT_
SYSCLK_
DONE_
FAIL_
EINT1
EINT1
0
IM_FLL1_
0
LOCK_
EINT1
0
0
0
0
0
0
DSP1_
BUS_
ERR_
EINT1
0
0
0
0
0
0
0
0
D900h
IM_
IM_
MICDET2_ MICDET1_
EINT1
EINT1
0
0
0
0
0
0
0
0
R6209 IRQ1_Mask_2
(1841h)
R6213 IRQ1_Mask_6
(1845h)
IM_FLL_
IM_
AO_REF_ DSPCLK_
LOST_
ERR_
EINT1
EINT1
0
0
0
0
IM_
0
CTRLIF_
ERR_
EINT1
IM_
IM_FLL_
SYSCLK_ AO_
ERR_
LOCK_
EINT1
EINT1
0
0
0
0
0
R6214 IRQ1_Mask_7
(1846h)
0
0
0
0
0
0
R6216 IRQ1_Mask_9
(1848h)
0
0
0
0
0
0
R6218 IRQ1_Mask_11
(184Ah)
R6219 IRQ1_Mask_12
(184Bh)
0
MIF4_
0
OVERCLO
CKED_
EINT1
GP9_
GP8_
GP7_
EINT1
EINT1
EINT1
0
IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_
IRQ16_ IRQ15_ IRQ14_ IRQ13_ IRQ12_ IRQ11_ IRQ10_
IRQ9_
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
0
0
0
0
0
0
0
0
R6220 IRQ1_Mask_13
(184Ch)
0
0
0
0
0
0
0
0
R6221 IRQ1_Mask_14
(184Dh)
0
0
0
0
0
0
0
0
R6222 IRQ1_Mask_15
(184Eh)
0
0
0
0
0
0
0
0
R6223 IRQ1_Mask_16
(184Fh)
0
0
0
0
0
0
0
0
R6224 IRQ1_Mask_17
(1850h)
R6228 IRQ1_Mask_21
(1854h)
0
252
0
IM_GP15_ IM_GP14_ IM_GP13_ IM_GP12_ IM_GP11_ IM_GP10_ IM_GP9_
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
0
0
0
0
0
0
0
0
2
1
0
SPK_
SPK_
SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_EINT1 WN_EINT1
EINT1
0
0
0
GP2_
EINT1
GP1_
EINT1
IM_
HPDET_
EINT1
0
0
IM_MICD_ IM_MICD_ IM_JD2_ IM_JD2_ IM_JD1_ IM_JD1_
CLAMP_ CLAMP_ FALL_
RISE_
FALL_
RISE_
FALL_
RISE_
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
0
0
0
0
0
IM_ IM_DRC2_ IM_DRC1_
INPUTS_ SIG_DET_ SIG_DET_
SIG_DET_ EINT1
EINT1
EINT1
IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_
IRQ8_
IRQ7_
IRQ6_
IRQ5_
IRQ4_
IRQ3_
IRQ2_
IRQ1_
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
0
IM_
0
0
IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_
SPKOUTL
SC_EINT1 SC_EINT1 SC_EINT1 SC_EINT1
_SC_
EINT1
0
IM_
0
0
0
0
IM_HP1R_ IM_HP1L_
SPKOUTL
ENABLE_ ENABLE_
_ENABLE_
DONE_ DONE_
DONE_
EINT1
EINT1
EINT1
0
IM_
0
0
0
0
IM_HP1R_ IM_HP1L_
SPKOUTL
DISABLE_ DISABLE_
_
DONE_ DONE_
DISABLE_
EINT1
EINT1
DONE_
EINT1
0
0
0
0
0
IM_SPK_ IM_SPK_ IM_SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_EINT1 WN_EINT1
EINT1
IM_MIF4_
0
0
0
0
0
0
0
OVERCLO
CKED_
EINT1
IM_GP8_ IM_GP7_ IM_GP6_ IM_GP5_ IM_GP4_ IM_GP3_ IM_GP2_ IM_GP1_
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
EINT1
0
0
0
0
0
0
IM_
IM_
TIMER2_ TIMER1_
EINT1
EINT1
Default
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
1200h
0301h
003Fh
0007h
FFFFh
004Fh
0043h
0043h
0007h
0080h
7FFFh
0003h
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R6229 IRQ1_Mask_22
(1855h)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6230 IRQ1_Mask_23
(1856h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6231 IRQ1_Mask_24
(1857h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6232 IRQ1_Mask_25
(1858h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_
EVENT2_
NOT_
EMPTY_
EINT1
IM_
EVENT2_
FULL_
EINT1
IM_
EVENT2_
WMARK_
EINT1
0
R6234 IRQ1_Mask_27
(185Ah)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6235 IRQ1_Mask_28
(185Bh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6237 IRQ1_Mask_30
(185Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6238 IRQ1_Mask_31
(185Eh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6239 IRQ1_Mask_32
(185Fh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0008h
R6240 IRQ1_Mask_33
(1860h)
0
0
0
0
0
0
0
0
0
0
0
0
IM_MIF4_
DONE_
EINT1
IM_MIF4_
BLOCK_
EINT1
0
IM_
EVENT1_
NOT_
EMPTY_
EINT1
IM_
EVENT1_
FULL_
EINT1
IM_
EVENT1_
WMARK_
EINT1
IM_DSP1
DMA_
EINT1
IM_DSP1_
START1_
EINT1
IM_DSP1_
START2_
EINT1
IM_DSP1_
BUSY_
EINT1
0
0
0
0008h
R6272 IRQ1_Raw_Status_1
(1880h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL1_
LOCK_
STS1
BOOT_
DONE_
STS1
0
IM_DSP1_
BUS_
ERR_
EINT1
0
0
0
0
0
0
0
0
0000h
0
JD2_STS1
0
JD1_STS1
0000h
INPUTS_ DRC2_ DRC1_
SIG_DET_ SIG_DET_ SIG_DET_
STS1
STS1
STS1
HP2R_ HP2L_SC_ HP1R_ HP1L_SC_
SC_STS1 STS1 SC_STS1 STS1
0000h
R6273 IRQ1_Raw_Status_2
(1881h)
R6278 IRQ1_Raw_Status_7
(1886h)
FLL_AO_ DSPCLK_
REF_
ERR_
LOST_
STS1
STS1
0
0
0
CTRLIF_
0
ERR_
STS1
SYSCLK_ FLL_AO_
ERR_
LOCK_
STS1
STS1
0
0
0
0
0
0
0
0
0003h
0003h
0001h
0001h
0001h
0001h
0008h
0000h
R6280 IRQ1_Raw_Status_9
(1888h)
0
0
0
0
0
0
0
0
0
0
0
MICD_
CLAMP_
STS1
0
R6283 IRQ1_Raw_Status_12
(188Bh)
R6284 IRQ1_Raw_Status_13
(188Ch)
0
0
0
0
0
0
0
0
0
SPKOUTL
_SC_STS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6285 IRQ1_Raw_Status_14
(188Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
R6286 IRQ1_Raw_Status_15
(188Eh)
0
0
0
0
0
0
0
0
0
SPKOUTL
_ENABLE_
DONE_
STS1
SPKOUTL
_
DISABLE_
DONE_
STS1
0
0
0
0
R6287 IRQ1_Raw_Status_16
(188Fh)
0
0
0
0
0
0
0
0
0
0
0
R6288 IRQ1_Raw_Status_17
(1890h)
R6293 IRQ1_Raw_Status_22
(1895h)
0
GPIO6_
STS1
GPIO5_
STS1
GPIO4_
STS1
GPIO3_
STS1
GPIO2_
STS1
GPIO1_
STS1
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6295 IRQ1_Raw_Status_24
(1897h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6296 IRQ1_Raw_Status_25
(1898h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6301 IRQ1_Raw_Status_30
(189Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6302 IRQ1_Raw_Status_31
(189Eh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6303 IRQ1_Raw_Status_32
(189Fh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
R6400 IRQ2_Status_1
(1900h)
0
0
0
CTRLIF_
ERR_
EINT2
0
0
SYSCLK_
FAIL_
EINT2
0
BOOT_
DONE_
EINT2
0
0
0
MIF4_
DONE_
STS1
MIF4_
BLOCK_
STS1
0
EVENT1_
NOT_
EMPTY_
STS1
EVENT1_
FULL_
STS1
EVENT1_
WMARK_
STS1
DSP1
DMA_
STS1
DSP1_
BUSY_
STS1
0
0000h
R6294 IRQ1_Raw_Status_23
(1896h)
EVENT2_
NOT_
EMPTY_
STS1
EVENT2_
FULL_
STS1
EVENT2_
WMARK_
STS1
0
0
0
0
0000h
DS1137PP1
0
Default
0003h
MIF4_
0
OVERCLO
CKED_
STS1
GPIO15_ GPIO14_ GPIO13_ GPIO12_ GPIO11_ GPIO10_ GPIO9_ GPIO8_ GPIO7_
STS1
STS1
STS1
STS1
STS1
STS1
STS1
STS1
STS1
0
0000h
HP1R_
HP1L_
ENABLE_ ENABLE_
DONE_ DONE_
STS1
STS1
HP1R_
HP1L_
DISABLE_ DISABLE_
DONE_ DONE_
STS1
STS1
0000h
SPK_
SPK_
SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_STS1 WN_STS1
STS1
0
0
0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
253
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R6401 IRQ2_Status_2
(1901h)
R6405 IRQ2_Status_6
(1905h)
R6406 IRQ2_Status_7
(1906h)
15
14
FLL_AO_ DSPCLK_
REF_
ERR_
LOST_
EINT2
EINT2
0
0
13
0
12
11
SYSCLK_ FLL_AO_
ERR_
LOCK_
EINT2
EINT2
10
9
8
7
6
5
4
3
2
1
0
0
0
FLL1_
LOCK_
EINT2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HPDET_
EINT2
0000h
JD2_
FALL_
EINT2
JD2_
RISE_
EINT2
JD1_
FALL_
EINT2
JD1_
RISE_
EINT2
0000h
0
0
0
0
MICDET2_ MICDET1_
EINT2
EINT2
0
0
0
0
0
0
0
0
0
0
R6408 IRQ2_Status_9
(1908h)
0
0
0
0
0
0
0
0
0
0
R6410 IRQ2_Status_11
(190Ah)
DSP_
IRQ16_
EINT2
0
DSP_
IRQ15_
EINT2
0
DSP_
IRQ14_
EINT2
0
DSP_
IRQ13_
EINT2
0
DSP_
IRQ12_
EINT2
0
DSP_
IRQ11_
EINT2
0
DSP_
IRQ10_
EINT2
0
DSP_
IRQ9_
EINT2
0
DSP_
IRQ8_
EINT2
0
R6412 IRQ2_Status_13
(190Ch)
0
0
0
0
0
0
0
0
0
R6413 IRQ2_Status_14
(190Dh)
0
0
0
0
0
0
0
0
0
R6414 IRQ2_Status_15
(190Eh)
0
0
0
0
0
0
0
0
0
R6415 IRQ2_Status_16
(190Fh)
0
0
0
0
0
0
0
0
R6416 IRQ2_Status_17
(1910h)
R6420 IRQ2_Status_21
(1914h)
R6421 IRQ2_Status_22
(1915h)
0
GP15_
EINT2
GP14_
EINT2
GP13_
EINT2
GP12_
EINT2
GP11_
EINT2
GP10_
EINT2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6422 IRQ2_Status_23
(1916h)
0
0
0
0
0
0
0
R6423 IRQ2_Status_24
(1917h)
0
0
0
0
0
0
R6424 IRQ2_Status_25
(1918h)
0
0
0
0
0
R6426 IRQ2_Status_27
(191Ah)
0
0
0
0
R6427 IRQ2_Status_28
(191Bh)
0
0
0
R6429 IRQ2_Status_30
(191Dh)
0
0
R6430 IRQ2_Status_31
(191Eh)
0
R6431 IRQ2_Status_32
(191Fh)
R6411 IRQ2_Status_12
(190Bh)
MICD_
MICD_
CLAMP_ CLAMP_
FALL_
RISE_
EINT2
EINT2
0
0
DSP_
DSP_
IRQ7_
IRQ6_
EINT2
EINT2
SPKOUTL
0
_SC_
EINT2
SPKOUTL
0
_ENABLE_
DONE_
EINT2
SPKOUTL
0
_
DISABLE_
DONE_
EINT2
0
0
0
INPUTS_ DRC2_ DRC1_
SIG_DET_ SIG_DET_ SIG_DET_
EINT2
EINT2
EINT2
DSP_
DSP_
DSP_
DSP_
DSP_
IRQ5_
IRQ4_
IRQ3_
IRQ2_
IRQ1_
EINT2
EINT2
EINT2
EINT2
EINT2
0
HP2R_ HP2L_SC_ HP1R_ HP1L_SC_
SC_EINT2 EINT2 SC_EINT2 EINT2
Default
0000h
0000h
0000h
0000h
HP1R_
HP1L_
ENABLE_ ENABLE_
DONE_ DONE_
EINT2
EINT2
HP1R_
HP1L_
DISABLE_ DISABLE_
DONE_ DONE_
EINT2
EINT2
0000h
SPK_
SPK_
SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_EINT2 WN_EINT2
EINT2
0
0
0
0000h
0
0
0
0
0
0
0
0
0
0
0
GP6_
EINT2
GP5_
EINT2
GP4_
EINT2
GP3_
EINT2
0
0
0
0
0
TIMER2_ TIMER1_
EINT2
EINT2
0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
R6432 IRQ2_Status_33
(1920h)
0
0
0
0
0
0
0
0
0
0
0
0
MIF4_
DONE_
EINT2
MIF4_
BLOCK_
EINT2
0
EVENT1_
NOT_
EMPTY_
EINT2
EVENT1_
FULL_
EINT2
EVENT1_
WMARK_
EINT2
DSP1
DMA_
EINT2
DSP1_
START1_
EINT2
DSP1_
START2_
EINT2
DSP1_
BUSY_
EINT2
0
0000h
0
EVENT2_
NOT_
EMPTY_
EINT2
EVENT2_
FULL_
EINT2
EVENT2_
WMARK_
EINT2
0
0
0
0000h
R6464 IRQ2_Mask_1
(1940h)
0
0
0
IM_
0
IM_BOOT_
SYSCLK_
DONE_
FAIL_
EINT2
EINT2
0
IM_FLL1_
0
LOCK_
EINT2
0
0
0
0
0
0
DSP1_
BUS_
ERR_
EINT2
0
0
0
0
0
0
0
0
D900h
IM_
IM_
MICDET2_ MICDET1_
EINT2
EINT2
0
0
0
0
0
0
0
0
R6465 IRQ2_Mask_2
(1941h)
R6469 IRQ2_Mask_6
(1945h)
R6470 IRQ2_Mask_7
(1946h)
R6472 IRQ2_Mask_9
(1948h)
R6474 IRQ2_Mask_11
(194Ah)
254
IM_FLL_
IM_
AO_REF_ DSPCLK_
LOST_
ERR_
EINT2
EINT2
0
0
0
0
IM_
0
CTRLIF_
ERR_
EINT2
IM_
IM_FLL_
SYSCLK_ AO_
ERR_
LOCK_
EINT2
EINT2
0
0
0
0
0
MIF4_
0
OVERCLO
CKED_
EINT2
GP9_
GP8_
GP7_
EINT2
EINT2
EINT2
0
GP2_
EINT2
GP1_
EINT2
IM_
HPDET_
EINT2
0
0
0
0
0
0
0
0
IM_MICD_ IM_MICD_ IM_JD2_ IM_JD2_ IM_JD1_ IM_JD1_
CLAMP_ CLAMP_ FALL_
RISE_
FALL_
RISE_
FALL_
RISE_
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_ IM_DRC2_ IM_DRC1_
INPUTS_ SIG_DET_ SIG_DET_
SIG_DET_ EINT2
EINT2
EINT2
IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_ IM_DSP_
IRQ16_ IRQ15_ IRQ14_ IRQ13_ IRQ12_ IRQ11_ IRQ10_
IRQ9_
IRQ8_
IRQ7_
IRQ6_
IRQ5_
IRQ4_
IRQ3_
IRQ2_
IRQ1_
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
1280h
0301h
003Fh
0007h
FFFFh
DS1137PP1
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R6475 IRQ2_Mask_12
(194Bh)
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
R6476 IRQ2_Mask_13
(194Ch)
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_HP1R_ IM_HP1L_
ENABLE_ ENABLE_
DONE_ DONE_
EINT2
EINT2
0043h
R6477 IRQ2_Mask_14
(194Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_HP1R_ IM_HP1L_
DISABLE_ DISABLE_
DONE_ DONE_
EINT2
EINT2
0043h
R6478 IRQ2_Mask_15
(194Eh)
0
0
0
0
0
0
0
0
0
IM_
SPKOUTL
_SC_
EINT2
IM_
SPKOUTL
_ENABLE_
DONE_
EINT2
IM_
SPKOUTL
_
DISABLE_
DONE_
EINT2
0
0
0
0
0007h
R6479 IRQ2_Mask_16
(194Fh)
0
0
0
0
0
0
0
0
IM_SPK_ IM_SPK_ IM_SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_EINT2 WN_EINT2
EINT2
0
0
0
R6480 IRQ2_Mask_17
(1950h)
R6484 IRQ2_Mask_21
(1954h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6485 IRQ2_Mask_22
(1955h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6486 IRQ2_Mask_23
(1956h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6487 IRQ2_Mask_24
(1957h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6488 IRQ2_Mask_25
(1958h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM_
TIMER2_
EINT2
IM_
EVENT2_
NOT_
EMPTY_
EINT2
IM_
EVENT2_
FULL_
EINT2
IM_
EVENT2_
WMARK_
EINT2
0
R6490 IRQ2_Mask_27
(195Ah)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6491 IRQ2_Mask_28
(195Bh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6493 IRQ2_Mask_30
(195Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6494 IRQ2_Mask_31
(195Eh)
0
0
0
0
0
0
0
0
0
0
0
0
0
R6495 IRQ2_Mask_32
(195Fh)
0
0
0
0
0
0
0
0
0
0
0
0
R6496 IRQ1_Mask_33
(1960h)
0
0
0
0
0
0
0
0
0
0
0
0
IM_MIF4_
DONE_
EINT2
IM_MIF4_
BLOCK_
EINT2
0
R6528 IRQ2_Raw_Status_1
(1980h)
0
0
0
0
0
0
0
0
0
0
0
FLL1_
LOCK_
STS2
BOOT_
DONE_
STS2
0
0
0
R6529 IRQ2_Raw_Status_2
(1981h)
R6534 IRQ2_Raw_Status_7
(1986h)
3
2
0
IM_MIF4_
0
0
0
0
OVERCLO
CKED_
EINT2
IM_GP15_ IM_GP14_ IM_GP13_ IM_GP12_ IM_GP11_ IM_GP10_ IM_GP9_ IM_GP8_ IM_GP7_ IM_GP6_ IM_GP5_ IM_GP4_ IM_GP3_ IM_GP2_ IM_GP1_
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
EINT2
FLL_AO_ DSPCLK_
REF_
ERR_
LOST_
STS2
STS2
0
0
0
CTRLIF_
0
ERR_
STS2
SYSCLK_ FLL_AO_
ERR_
LOCK_
STS2
STS2
0
0
0
0
0
0
0
0
0
Default
004Fh
0080h
7FFFh
0003h
0
IM_
TIMER1_
EINT2
IM_
EVENT1_
NOT_
EMPTY_
EINT2
IM_
EVENT1_
FULL_
EINT2
IM_
EVENT1_
WMARK_
EINT2
IM_DSP1
DMA_
EINT2
IM_DSP1_
START1_
EINT2
IM_DSP1_
START2_
EINT2
IM_DSP1_
BUSY_
EINT2
0
0
0
0
0008h
0
0
0000h
0
0
0
IM_DSP1_
BUS_
ERR_
EINT2
0
0
0
0
0
0
0000h
0
JD2_STS2
0
JD1_STS2
0000h
INPUTS_ DRC2_ DRC1_
SIG_DET_ SIG_DET_ SIG_DET_
STS2
STS2
STS2
HP2R_ HP2L_SC_ HP1R_ HP1L_SC_
SC_STS2 STS2 SC_STS2 STS2
0000h
R6536 IRQ2_Raw_Status_9
(1988h)
0
0
0
0
0
0
0
0
0
0
0
MICD_
CLAMP_
STS2
0
R6539 IRQ2_Raw_Status_12
(198Bh)
R6540 IRQ2_Raw_Status_13
(198Ch)
0
0
0
0
0
0
0
0
0
SPKOUTL
_SC_STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6541 IRQ2_Raw_Status_14
(198Dh)
0
0
0
0
0
0
0
0
0
0
0
0
0
R6542 IRQ2_Raw_Status_15
(198Eh)
0
0
0
0
0
0
0
0
0
SPKOUTL
_ENABLE_
DONE_
STS2
SPKOUTL
_
DISABLE_
DONE_
STS2
0
0
0
0
R6543 IRQ2_Raw_Status_16
(198Fh)
0
0
0
0
0
0
0
0
MIF4_
OVERCLO
CKED_
STS2
0
0
0
0
DS1137PP1
1
IM_HP2R_ IM_HP2L_ IM_HP1R_ IM_HP1L_
SC_EINT2 SC_EINT2 SC_EINT2 SC_EINT2
0
0003h
0003h
0003h
0001h
0001h
0001h
0001h
0008h
0000h
0000h
HP1R_
HP1L_
ENABLE_ ENABLE_
DONE_ DONE_
STS2
STS2
HP1R_
HP1L_
DISABLE_ DISABLE_
DONE_ DONE_
STS2
STS2
0000h
SPK_
SPK_
SPK_
OVERHEA OVERHEA SHUTDO
T_WARN_ T_STS2 WN_STS2
STS2
0
0
0
0000h
0000h
0000h
255
CS47L15
6 Register Map
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
R6544 IRQ2_Raw_Status_17
(1990h)
R6549 IRQ2_Raw_Status_22
(1995h)
15
7
6
5
4
3
2
1
0
GPIO8_
STS2
GPIO7_
STS2
GPIO6_
STS2
GPIO5_
STS2
GPIO4_
STS2
GPIO3_
STS2
GPIO2_
STS2
GPIO1_
STS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENT1_
NOT_
EMPTY_
STS2
EVENT1_
FULL_
STS2
EVENT1_
WMARK_
STS2
DSP1
DMA_
STS2
DSP1_
BUSY_
STS2
0
0000h
0
EVENT2_
NOT_
EMPTY_
STS2
EVENT2_
FULL_
STS2
EVENT2_
WMARK_
STS2
0
R6550 IRQ2_Raw_Status_23
(1996h)
0
0
0
0
0
0
R6551 IRQ2_Raw_Status_24
(1997h)
0
0
0
0
0
R6552 IRQ2_Raw_Status_25
(1998h)
0
0
0
0
R6557 IRQ2_Raw_Status_30
(199Dh)
0
0
0
R6558 IRQ2_Raw_Status_31
(199Eh)
0
0
R6559 IRQ2_Raw_Status_32
(199Fh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000h
R6662 Interrupt_Debounce_7
(1A06h)
0
0
0
0
0
0
0
0
0
0
0
0
JD1_DB
0000h
IRQ1_CTRL
0
1
0
0
IM_IRQ1 IRQ_POL IRQ_OP_
CFG
0
0
0
0
MICD_
CLAMP_
DB
0
R6784
(1A80h)
R6786
(1A82h)
R6816
(1AA0h)
R6848
(1AC0h)
R6864
(1AD0h)
IRQ2_CTRL
0
0
0
0
IM_IRQ2
0
0
0
0
0
0
Interrupt_Raw_Status_1
0
0
0
0
0
0
0
0
0
0
GPIO_Debounce_Config
0
0
0
0
0
0
0
0
0
AOD_Pad_Ctrl
0
1
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
GPIO15_ GPIO14_ GPIO13_ GPIO12_ GPIO11_ GPIO10_ GPIO9_
STS2
STS2
STS2
STS2
STS2
STS2
STS2
MIF4_
0
DONE_
STS2
MIF4_
0
BLOCK_
STS2
0
JD2_DB
Default
0000h
0000h
0000h
0000h
0000h
0000h
0
0
0
0
4400h
0
0
0
0
0
0000h
0
0
0
0
0
0
0
0
0
0
0
0
20
4
19
3
18
2
IRQ2_STS IRQ1_STS
0000h
0000h
GP_DBTIME [3:0]
RESET_ RESET_
PU
PD
4002h
The 32-bit DSP register space is described in Table 6-2.
Table 6-2. Register Map Definition—32-bit region
Register
Name
R12288 WSEQ_Sequence_1
(3000h)
R12290 WSEQ_Sequence_2
(3002h)
R12292 WSEQ_Sequence_3
(3004h)
R12294 WSEQ_Sequence_4
(3006h)
R12296 WSEQ_Sequence_5
(3008h)
R12298 WSEQ_Sequence_6
(300Ah)
R12300 WSEQ_Sequence_7
(300Ch)
R12302 WSEQ_Sequence_8
(300Eh)
R12304 WSEQ_Sequence_9
(3010h)
R12306 WSEQ_Sequence_10
(3012h)
R12308 WSEQ_Sequence_11
(3014h)
R12310 WSEQ_Sequence_12
(3016h)
R12312 WSEQ_Sequence_13
(3018h)
R12314 WSEQ_Sequence_14
(301Ah)
R12316 WSEQ_Sequence_15
(301Ch)
R12318 WSEQ_Sequence_16
(301Eh)
R12320 WSEQ_Sequence_17
(3020h)
256
31
15
30
14
29
13
WSEQ_DATA_WIDTH0 [2:0]
WSEQ_DELAY0 [3:0]
WSEQ_DATA_WIDTH1 [2:0]
WSEQ_DELAY1 [3:0]
WSEQ_DATA_WIDTH2 [2:0]
WSEQ_DELAY2 [3:0]
WSEQ_DATA_WIDTH3 [2:0]
WSEQ_DELAY3 [3:0]
WSEQ_DATA_WIDTH4 [2:0]
WSEQ_DELAY4 [3:0]
WSEQ_DATA_WIDTH5 [2:0]
WSEQ_DELAY5 [3:0]
WSEQ_DATA_WIDTH6 [2:0]
WSEQ_DELAY6 [3:0]
WSEQ_DATA_WIDTH7 [2:0]
WSEQ_DELAY7 [3:0]
WSEQ_DATA_WIDTH8 [2:0]
WSEQ_DELAY8 [3:0]
WSEQ_DATA_WIDTH9 [2:0]
WSEQ_DELAY9 [3:0]
WSEQ_DATA_WIDTH10 [2:0]
WSEQ_DELAY10 [3:0]
WSEQ_DATA_WIDTH11 [2:0]
WSEQ_DELAY11 [3:0]
WSEQ_DATA_WIDTH12 [2:0]
WSEQ_DELAY12 [3:0]
WSEQ_DATA_WIDTH13 [2:0]
WSEQ_DELAY13 [3:0]
WSEQ_DATA_WIDTH14 [2:0]
WSEQ_DELAY14 [3:0]
WSEQ_DATA_WIDTH15 [2:0]
WSEQ_DELAY15 [3:0]
WSEQ_DATA_WIDTH16 [2:0]
WSEQ_DELAY16 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
Default
WSEQ_DATA0 [7:0]
0000F000h
WSEQ_ADDR1 [12:0]
WSEQ_DATA_START1 [3:0]
WSEQ_DATA1 [7:0]
0000F000h
WSEQ_ADDR2 [12:0]
WSEQ_DATA_START2 [3:0]
WSEQ_DATA2 [7:0]
0000F000h
WSEQ_ADDR3 [12:0]
WSEQ_DATA_START3 [3:0]
WSEQ_DATA3 [7:0]
82253719h
WSEQ_ADDR4 [12:0]
WSEQ_DATA_START4 [3:0]
WSEQ_DATA4 [7:0]
C2300001h
WSEQ_ADDR5 [12:0]
WSEQ_DATA_START5 [3:0]
WSEQ_DATA5 [7:0]
02251301h
WSEQ_ADDR6 [12:0]
WSEQ_DATA_START6 [3:0]
WSEQ_DATA6 [7:0]
8225191Fh
WSEQ_ADDR7 [12:0]
WSEQ_DATA_START7 [3:0]
WSEQ_DATA7 [7:0]
82310B00h
WSEQ_ADDR8 [12:0]
WSEQ_DATA_START8 [3:0]
WSEQ_DATA8 [7:0]
E231023Bh
WSEQ_ADDR9 [12:0]
WSEQ_DATA_START9 [3:0]
WSEQ_DATA9 [7:0]
02313B01h
WSEQ_ADDR10 [12:0]
WSEQ_DATA_START10 [3:0]
WSEQ_DATA10 [7:0]
62300000h
WSEQ_ADDR11 [12:0]
WSEQ_DATA_START11 [3:0]
WSEQ_DATA11 [7:0]
E2314288h
WSEQ_ADDR12 [12:0]
WSEQ_DATA_START12 [3:0]
WSEQ_DATA12 [7:0]
02310B00h
WSEQ_ADDR13 [12:0]
WSEQ_DATA_START13 [3:0]
WSEQ_DATA13 [7:0]
02310B00h
WSEQ_ADDR14 [12:0]
WSEQ_DATA_START14 [3:0]
WSEQ_DATA14 [7:0]
02250E01h
WSEQ_ADDR15 [12:0]
WSEQ_DATA_START15 [3:0]
WSEQ_DATA15 [7:0]
42310C02h
WSEQ_ADDR16 [12:0]
WSEQ_DATA_START16 [3:0]
16
0
0000F000h
WSEQ_ADDR0 [12:0]
WSEQ_DATA_START0 [3:0]
17
1
WSEQ_DATA16 [7:0]
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12322 WSEQ_Sequence_18
(3022h)
R12324 WSEQ_Sequence_19
(3024h)
R12326 WSEQ_Sequence_20
(3026h)
R12328 WSEQ_Sequence_21
(3028h)
R12330 WSEQ_Sequence_22
(302Ah)
R12332 WSEQ_Sequence_23
(302Ch)
R12334 WSEQ_Sequence_24
(302Eh)
R12336 WSEQ_Sequence_25
(3030h)
R12338 WSEQ_Sequence_26
(3032h)
R12340 WSEQ_Sequence_27
(3034h)
R12342 WSEQ_Sequence_28
(3036h)
R12344 WSEQ_Sequence_29
(3038h)
R12346 WSEQ_Sequence_30
(303Ah)
R12348 WSEQ_Sequence_31
(303Ch)
R12350 WSEQ_Sequence_32
(303Eh)
R12352 WSEQ_Sequence_33
(3040h)
R12354 WSEQ_Sequence_34
(3042h)
R12356 WSEQ_Sequence_35
(3044h)
R12358 WSEQ_Sequence_36
(3046h)
R12360 WSEQ_Sequence_37
(3048h)
R12362 WSEQ_Sequence_38
(304Ah)
R12364 WSEQ_Sequence_39
(304Ch)
R12366 WSEQ_Sequence_40
(304Eh)
R12368 WSEQ_Sequence_41
(3050h)
R12370 WSEQ_Sequence_42
(3052h)
R12372 WSEQ_Sequence_43
(3054h)
R12374 WSEQ_Sequence_44
(3056h)
R12376 WSEQ_Sequence_45
(3058h)
R12378 WSEQ_Sequence_46
(305Ah)
R12380 WSEQ_Sequence_47
(305Ch)
R12382 WSEQ_Sequence_48
(305Eh)
R12384 WSEQ_Sequence_49
(3060h)
R12386 WSEQ_Sequence_50
(3062h)
R12388 WSEQ_Sequence_51
(3064h)
R12390 WSEQ_Sequence_52
(3066h)
R12392 WSEQ_Sequence_53
(3068h)
DS1137PP1
31
15
30
14
29
13
WSEQ_DATA_WIDTH17 [2:0]
WSEQ_DELAY17 [3:0]
WSEQ_DATA_WIDTH18 [2:0]
WSEQ_DELAY18 [3:0]
WSEQ_DATA_WIDTH19 [2:0]
WSEQ_DELAY19 [3:0]
WSEQ_DATA_WIDTH20 [2:0]
WSEQ_DELAY20 [3:0]
WSEQ_DATA_WIDTH21 [2:0]
WSEQ_DELAY21 [3:0]
WSEQ_DATA_WIDTH22 [2:0]
WSEQ_DELAY22 [3:0]
WSEQ_DATA_WIDTH23 [2:0]
WSEQ_DELAY23 [3:0]
WSEQ_DATA_WIDTH24 [2:0]
WSEQ_DELAY24 [3:0]
WSEQ_DATA_WIDTH25 [2:0]
WSEQ_DELAY25 [3:0]
WSEQ_DATA_WIDTH26 [2:0]
WSEQ_DELAY26 [3:0]
WSEQ_DATA_WIDTH27 [2:0]
WSEQ_DELAY27 [3:0]
WSEQ_DATA_WIDTH28 [2:0]
WSEQ_DELAY28 [3:0]
WSEQ_DATA_WIDTH29 [2:0]
WSEQ_DELAY29 [3:0]
WSEQ_DATA_WIDTH30 [2:0]
WSEQ_DELAY30 [3:0]
WSEQ_DATA_WIDTH31 [2:0]
WSEQ_DELAY31 [3:0]
WSEQ_DATA_WIDTH32 [2:0]
WSEQ_DELAY32 [3:0]
WSEQ_DATA_WIDTH33 [2:0]
WSEQ_DELAY33 [3:0]
WSEQ_DATA_WIDTH34 [2:0]
WSEQ_DELAY34 [3:0]
WSEQ_DATA_WIDTH35 [2:0]
WSEQ_DELAY35 [3:0]
WSEQ_DATA_WIDTH36 [2:0]
WSEQ_DELAY36 [3:0]
WSEQ_DATA_WIDTH37 [2:0]
WSEQ_DELAY37 [3:0]
WSEQ_DATA_WIDTH38 [2:0]
WSEQ_DELAY38 [3:0]
WSEQ_DATA_WIDTH39 [2:0]
WSEQ_DELAY39 [3:0]
WSEQ_DATA_WIDTH40 [2:0]
WSEQ_DELAY40 [3:0]
WSEQ_DATA_WIDTH41 [2:0]
WSEQ_DELAY41 [3:0]
WSEQ_DATA_WIDTH42 [2:0]
WSEQ_DELAY42 [3:0]
WSEQ_DATA_WIDTH43 [2:0]
WSEQ_DELAY43 [3:0]
WSEQ_DATA_WIDTH44 [2:0]
WSEQ_DELAY44 [3:0]
WSEQ_DATA_WIDTH45 [2:0]
WSEQ_DELAY45 [3:0]
WSEQ_DATA_WIDTH46 [2:0]
WSEQ_DELAY46 [3:0]
WSEQ_DATA_WIDTH47 [2:0]
WSEQ_DELAY47 [3:0]
WSEQ_DATA_WIDTH48 [2:0]
WSEQ_DELAY48 [3:0]
WSEQ_DATA_WIDTH49 [2:0]
WSEQ_DELAY49 [3:0]
WSEQ_DATA_WIDTH50 [2:0]
WSEQ_DELAY50 [3:0]
WSEQ_DATA_WIDTH51 [2:0]
WSEQ_DELAY51 [3:0]
WSEQ_DATA_WIDTH52 [2:0]
WSEQ_DELAY52 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA17 [7:0]
02313B01h
WSEQ_ADDR18 [12:0]
WSEQ_DATA_START18 [3:0]
WSEQ_DATA18 [7:0]
E2314266h
WSEQ_ADDR19 [12:0]
WSEQ_DATA_START19 [3:0]
WSEQ_DATA19 [7:0]
E2315294h
WSEQ_ADDR20 [12:0]
WSEQ_DATA_START20 [3:0]
WSEQ_DATA20 [7:0]
02310B00h
WSEQ_ADDR21 [12:0]
WSEQ_DATA_START21 [3:0]
WSEQ_DATA21 [7:0]
02310B00h
WSEQ_ADDR22 [12:0]
WSEQ_DATA_START22 [3:0]
WSEQ_DATA22 [7:0]
E2251734h
WSEQ_ADDR23 [12:0]
WSEQ_DATA_START23 [3:0]
WSEQ_DATA23 [7:0]
0225F501h
WSEQ_ADDR24 [12:0]
WSEQ_DATA_START24 [3:0]
WSEQ_DATA24 [7:0]
0000F000h
WSEQ_ADDR25 [12:0]
WSEQ_DATA_START25 [3:0]
WSEQ_DATA25 [7:0]
0000F000h
WSEQ_ADDR26 [12:0]
WSEQ_DATA_START26 [3:0]
WSEQ_DATA26 [7:0]
0000F000h
WSEQ_ADDR27 [12:0]
WSEQ_DATA_START27 [3:0]
WSEQ_DATA27 [7:0]
0000F000h
WSEQ_ADDR28 [12:0]
WSEQ_DATA_START28 [3:0]
WSEQ_DATA28 [7:0]
0000F000h
WSEQ_ADDR29 [12:0]
WSEQ_DATA_START29 [3:0]
WSEQ_DATA29 [7:0]
0000F000h
WSEQ_ADDR30 [12:0]
WSEQ_DATA_START30 [3:0]
WSEQ_DATA30 [7:0]
02253A01h
WSEQ_ADDR31 [12:0]
WSEQ_DATA_START31 [3:0]
WSEQ_DATA31 [7:0]
C2251300h
WSEQ_ADDR32 [12:0]
WSEQ_DATA_START32 [3:0]
WSEQ_DATA32 [7:0]
02250B00h
WSEQ_ADDR33 [12:0]
WSEQ_DATA_START33 [3:0]
WSEQ_DATA33 [7:0]
0225FF01h
WSEQ_ADDR34 [12:0]
WSEQ_DATA_START34 [3:0]
WSEQ_DATA34 [7:0]
0000F000h
WSEQ_ADDR35 [12:0]
WSEQ_DATA_START35 [3:0]
WSEQ_DATA35 [7:0]
0000F000h
WSEQ_ADDR36 [12:0]
WSEQ_DATA_START36 [3:0]
WSEQ_DATA36 [7:0]
0000F000h
WSEQ_ADDR37 [12:0]
WSEQ_DATA_START37 [3:0]
WSEQ_DATA37 [7:0]
0000F000h
WSEQ_ADDR38 [12:0]
WSEQ_DATA_START38 [3:0]
WSEQ_DATA38 [7:0]
0000F000h
WSEQ_ADDR39 [12:0]
WSEQ_DATA_START39 [3:0]
WSEQ_DATA39 [7:0]
0000F000h
WSEQ_ADDR40 [12:0]
WSEQ_DATA_START40 [3:0]
WSEQ_DATA40 [7:0]
0000F000h
WSEQ_ADDR41 [12:0]
WSEQ_DATA_START41 [3:0]
WSEQ_DATA41 [7:0]
0000F000h
WSEQ_ADDR42 [12:0]
WSEQ_DATA_START42 [3:0]
WSEQ_DATA42 [7:0]
0000F000h
WSEQ_ADDR43 [12:0]
WSEQ_DATA_START43 [3:0]
WSEQ_DATA43 [7:0]
82263719h
WSEQ_ADDR44 [12:0]
WSEQ_DATA_START44 [3:0]
WSEQ_DATA44 [7:0]
C2300001h
WSEQ_ADDR45 [12:0]
WSEQ_DATA_START45 [3:0]
WSEQ_DATA45 [7:0]
02261301h
WSEQ_ADDR46 [12:0]
WSEQ_DATA_START46 [3:0]
WSEQ_DATA46 [7:0]
8226191Fh
WSEQ_ADDR47 [12:0]
WSEQ_DATA_START47 [3:0]
WSEQ_DATA47 [7:0]
82310B02h
WSEQ_ADDR48 [12:0]
WSEQ_DATA_START48 [3:0]
WSEQ_DATA48 [7:0]
E231023Bh
WSEQ_ADDR49 [12:0]
WSEQ_DATA_START49 [3:0]
WSEQ_DATA49 [7:0]
02313B01h
WSEQ_ADDR50 [12:0]
WSEQ_DATA_START50 [3:0]
WSEQ_DATA50 [7:0]
62300000h
WSEQ_ADDR51 [12:0]
WSEQ_DATA_START51 [3:0]
WSEQ_DATA51 [7:0]
E2314288h
WSEQ_ADDR52 [12:0]
WSEQ_DATA_START52 [3:0]
17
1
E2310227h
WSEQ_ADDR17 [12:0]
WSEQ_DATA_START17 [3:0]
18
2
WSEQ_DATA52 [7:0]
257
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12394 WSEQ_Sequence_54
(306Ah)
R12396 WSEQ_Sequence_55
(306Ch)
R12398 WSEQ_Sequence_56
(306Eh)
R12400 WSEQ_Sequence_57
(3070h)
R12402 WSEQ_Sequence_58
(3072h)
R12404 WSEQ_Sequence_59
(3074h)
R12406 WSEQ_Sequence_60
(3076h)
R12408 WSEQ_Sequence_61
(3078h)
R12410 WSEQ_Sequence_62
(307Ah)
R12412 WSEQ_Sequence_63
(307Ch)
R12414 WSEQ_Sequence_64
(307Eh)
R12416 WSEQ_Sequence_65
(3080h)
R12418 WSEQ_Sequence_66
(3082h)
R12420 WSEQ_Sequence_67
(3084h)
R12422 WSEQ_Sequence_68
(3086h)
R12424 WSEQ_Sequence_69
(3088h)
R12426 WSEQ_Sequence_70
(308Ah)
R12428 WSEQ_Sequence_71
(308Ch)
R12430 WSEQ_Sequence_72
(308Eh)
R12432 WSEQ_Sequence_73
(3090h)
R12434 WSEQ_Sequence_74
(3092h)
R12436 WSEQ_Sequence_75
(3094h)
R12438 WSEQ_Sequence_76
(3096h)
R12440 WSEQ_Sequence_77
(3098h)
R12442 WSEQ_Sequence_78
(309Ah)
R12444 WSEQ_Sequence_79
(309Ch)
R12446 WSEQ_Sequence_80
(309Eh)
R12448 WSEQ_Sequence_81
(30A0h)
R12450 WSEQ_Sequence_82
(30A2h)
R12452 WSEQ_Sequence_83
(30A4h)
R12454 WSEQ_Sequence_84
(30A6h)
R12456 WSEQ_Sequence_85
(30A8h)
R12458 WSEQ_Sequence_86
(30AAh)
R12460 WSEQ_Sequence_87
(30ACh)
R12462 WSEQ_Sequence_88
(30AEh)
R12464 WSEQ_Sequence_89
(30B0h)
258
31
15
30
14
29
13
WSEQ_DATA_WIDTH53 [2:0]
WSEQ_DELAY53 [3:0]
WSEQ_DATA_WIDTH54 [2:0]
WSEQ_DELAY54 [3:0]
WSEQ_DATA_WIDTH55 [2:0]
WSEQ_DELAY55 [3:0]
WSEQ_DATA_WIDTH56 [2:0]
WSEQ_DELAY56 [3:0]
WSEQ_DATA_WIDTH57 [2:0]
WSEQ_DELAY57 [3:0]
WSEQ_DATA_WIDTH58 [2:0]
WSEQ_DELAY58 [3:0]
WSEQ_DATA_WIDTH59 [2:0]
WSEQ_DELAY59 [3:0]
WSEQ_DATA_WIDTH60 [2:0]
WSEQ_DELAY60 [3:0]
WSEQ_DATA_WIDTH61 [2:0]
WSEQ_DELAY61 [3:0]
WSEQ_DATA_WIDTH62 [2:0]
WSEQ_DELAY62 [3:0]
WSEQ_DATA_WIDTH63 [2:0]
WSEQ_DELAY63 [3:0]
WSEQ_DATA_WIDTH64 [2:0]
WSEQ_DELAY64 [3:0]
WSEQ_DATA_WIDTH65 [2:0]
WSEQ_DELAY65 [3:0]
WSEQ_DATA_WIDTH66 [2:0]
WSEQ_DELAY66 [3:0]
WSEQ_DATA_WIDTH67 [2:0]
WSEQ_DELAY67 [3:0]
WSEQ_DATA_WIDTH68 [2:0]
WSEQ_DELAY68 [3:0]
WSEQ_DATA_WIDTH69 [2:0]
WSEQ_DELAY69 [3:0]
WSEQ_DATA_WIDTH70 [2:0]
WSEQ_DELAY70 [3:0]
WSEQ_DATA_WIDTH71 [2:0]
WSEQ_DELAY71 [3:0]
WSEQ_DATA_WIDTH72 [2:0]
WSEQ_DELAY72 [3:0]
WSEQ_DATA_WIDTH73 [2:0]
WSEQ_DELAY73 [3:0]
WSEQ_DATA_WIDTH74 [2:0]
WSEQ_DELAY74 [3:0]
WSEQ_DATA_WIDTH75 [2:0]
WSEQ_DELAY75 [3:0]
WSEQ_DATA_WIDTH76 [2:0]
WSEQ_DELAY76 [3:0]
WSEQ_DATA_WIDTH77 [2:0]
WSEQ_DELAY77 [3:0]
WSEQ_DATA_WIDTH78 [2:0]
WSEQ_DELAY78 [3:0]
WSEQ_DATA_WIDTH79 [2:0]
WSEQ_DELAY79 [3:0]
WSEQ_DATA_WIDTH80 [2:0]
WSEQ_DELAY80 [3:0]
WSEQ_DATA_WIDTH81 [2:0]
WSEQ_DELAY81 [3:0]
WSEQ_DATA_WIDTH82 [2:0]
WSEQ_DELAY82 [3:0]
WSEQ_DATA_WIDTH83 [2:0]
WSEQ_DELAY83 [3:0]
WSEQ_DATA_WIDTH84 [2:0]
WSEQ_DELAY84 [3:0]
WSEQ_DATA_WIDTH85 [2:0]
WSEQ_DELAY85 [3:0]
WSEQ_DATA_WIDTH86 [2:0]
WSEQ_DELAY86 [3:0]
WSEQ_DATA_WIDTH87 [2:0]
WSEQ_DELAY87 [3:0]
WSEQ_DATA_WIDTH88 [2:0]
WSEQ_DELAY88 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA53 [7:0]
02310B00h
WSEQ_ADDR54 [12:0]
WSEQ_DATA_START54 [3:0]
WSEQ_DATA54 [7:0]
02260E01h
WSEQ_ADDR55 [12:0]
WSEQ_DATA_START55 [3:0]
WSEQ_DATA55 [7:0]
42310C03h
WSEQ_ADDR56 [12:0]
WSEQ_DATA_START56 [3:0]
WSEQ_DATA56 [7:0]
E2310227h
WSEQ_ADDR57 [12:0]
WSEQ_DATA_START57 [3:0]
WSEQ_DATA57 [7:0]
02313B01h
WSEQ_ADDR58 [12:0]
WSEQ_DATA_START58 [3:0]
WSEQ_DATA58 [7:0]
E2314266h
WSEQ_ADDR59 [12:0]
WSEQ_DATA_START59 [3:0]
WSEQ_DATA59 [7:0]
E2315294h
WSEQ_ADDR60 [12:0]
WSEQ_DATA_START60 [3:0]
WSEQ_DATA60 [7:0]
02310B00h
WSEQ_ADDR61 [12:0]
WSEQ_DATA_START61 [3:0]
WSEQ_DATA61 [7:0]
02310B00h
WSEQ_ADDR62 [12:0]
WSEQ_DATA_START62 [3:0]
WSEQ_DATA62 [7:0]
E2261734h
WSEQ_ADDR63 [12:0]
WSEQ_DATA_START63 [3:0]
WSEQ_DATA63 [7:0]
0226F501h
WSEQ_ADDR64 [12:0]
WSEQ_DATA_START64 [3:0]
WSEQ_DATA64 [7:0]
0000F000h
WSEQ_ADDR65 [12:0]
WSEQ_DATA_START65 [3:0]
WSEQ_DATA65 [7:0]
0000F000h
WSEQ_ADDR66 [12:0]
WSEQ_DATA_START66 [3:0]
WSEQ_DATA66 [7:0]
0000F000h
WSEQ_ADDR67 [12:0]
WSEQ_DATA_START67 [3:0]
WSEQ_DATA67 [7:0]
0000F000h
WSEQ_ADDR68 [12:0]
WSEQ_DATA_START68 [3:0]
WSEQ_DATA68 [7:0]
0000F000h
WSEQ_ADDR69 [12:0]
WSEQ_DATA_START69 [3:0]
WSEQ_DATA69 [7:0]
0000F000h
WSEQ_ADDR70 [12:0]
WSEQ_DATA_START70 [3:0]
WSEQ_DATA70 [7:0]
02263A01h
WSEQ_ADDR71 [12:0]
WSEQ_DATA_START71 [3:0]
WSEQ_DATA71 [7:0]
C2261300h
WSEQ_ADDR72 [12:0]
WSEQ_DATA_START72 [3:0]
WSEQ_DATA72 [7:0]
02260B00h
WSEQ_ADDR73 [12:0]
WSEQ_DATA_START73 [3:0]
WSEQ_DATA73 [7:0]
0226FF01h
WSEQ_ADDR74 [12:0]
WSEQ_DATA_START74 [3:0]
WSEQ_DATA74 [7:0]
0000F000h
WSEQ_ADDR75 [12:0]
WSEQ_DATA_START75 [3:0]
WSEQ_DATA75 [7:0]
0000F000h
WSEQ_ADDR76 [12:0]
WSEQ_DATA_START76 [3:0]
WSEQ_DATA76 [7:0]
0000F000h
WSEQ_ADDR77 [12:0]
WSEQ_DATA_START77 [3:0]
WSEQ_DATA77 [7:0]
0000F000h
WSEQ_ADDR78 [12:0]
WSEQ_DATA_START78 [3:0]
WSEQ_DATA78 [7:0]
0000F000h
WSEQ_ADDR79 [12:0]
WSEQ_DATA_START79 [3:0]
WSEQ_DATA79 [7:0]
0000F000h
WSEQ_ADDR80 [12:0]
WSEQ_DATA_START80 [3:0]
WSEQ_DATA80 [7:0]
0000F000h
WSEQ_ADDR81 [12:0]
WSEQ_DATA_START81 [3:0]
WSEQ_DATA81 [7:0]
0000F000h
WSEQ_ADDR82 [12:0]
WSEQ_DATA_START82 [3:0]
WSEQ_DATA82 [7:0]
0000F000h
WSEQ_ADDR83 [12:0]
WSEQ_DATA_START83 [3:0]
WSEQ_DATA83 [7:0]
026D0101h
WSEQ_ADDR84 [12:0]
WSEQ_DATA_START84 [3:0]
WSEQ_DATA84 [7:0]
44B00004h
WSEQ_ADDR85 [12:0]
WSEQ_DATA_START85 [3:0]
WSEQ_DATA85 [7:0]
04020701h
WSEQ_ADDR86 [12:0]
WSEQ_DATA_START86 [3:0]
WSEQ_DATA86 [7:0]
04AE5801h
WSEQ_ADDR87 [12:0]
WSEQ_DATA_START87 [3:0]
WSEQ_DATA87 [7:0]
A4AE201Fh
WSEQ_ADDR88 [12:0]
WSEQ_DATA_START88 [3:0]
17
1
02310B00h
WSEQ_ADDR53 [12:0]
WSEQ_DATA_START53 [3:0]
18
2
WSEQ_DATA88 [7:0]
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12466 WSEQ_Sequence_90
(30B2h)
R12468 WSEQ_Sequence_91
(30B4h)
R12470 WSEQ_Sequence_92
(30B6h)
R12472 WSEQ_Sequence_93
(30B8h)
R12474 WSEQ_Sequence_94
(30BAh)
R12476 WSEQ_Sequence_95
(30BCh)
R12478 WSEQ_Sequence_96
(30BEh)
R12480 WSEQ_Sequence_97
(30C0h)
R12482 WSEQ_Sequence_98
(30C2h)
R12484 WSEQ_Sequence_99
(30C4h)
R12486 WSEQ_Sequence_100
(30C6h)
R12488 WSEQ_Sequence_101
(30C8h)
R12490 WSEQ_Sequence_102
(30CAh)
R12492 WSEQ_Sequence_103
(30CCh)
R12494 WSEQ_Sequence_104
(30CEh)
R12496 WSEQ_Sequence_105
(30D0h)
R12498 WSEQ_Sequence_106
(30D2h)
R12500 WSEQ_Sequence_107
(30D4h)
R12502 WSEQ_Sequence_108
(30D6h)
R12504 WSEQ_Sequence_109
(30D8h)
R12506 WSEQ_Sequence_110
(30DAh)
R12508 WSEQ_Sequence_111
(30DCh)
R12510 WSEQ_Sequence_112
(30DEh)
R12512 WSEQ_Sequence_113
(30E0h)
R12514 WSEQ_Sequence_114
(30E2h)
R12516 WSEQ_Sequence_115
(30E4h)
R12518 WSEQ_Sequence_116
(30E6h)
R12520 WSEQ_Sequence_117
(30E8h)
R12522 WSEQ_Sequence_118
(30EAh)
R12524 WSEQ_Sequence_119
(30ECh)
R12526 WSEQ_Sequence_120
(30EEh)
R12528 WSEQ_Sequence_121
(30F0h)
R12530 WSEQ_Sequence_122
(30F2h)
R12532 WSEQ_Sequence_123
(30F4h)
R12534 WSEQ_Sequence_124
(30F6h)
R12536 WSEQ_Sequence_125
(30F8h)
DS1137PP1
31
15
30
14
29
13
WSEQ_DATA_WIDTH89 [2:0]
WSEQ_DELAY89 [3:0]
WSEQ_DATA_WIDTH90 [2:0]
WSEQ_DELAY90 [3:0]
WSEQ_DATA_WIDTH91 [2:0]
WSEQ_DELAY91 [3:0]
WSEQ_DATA_WIDTH92 [2:0]
WSEQ_DELAY92 [3:0]
WSEQ_DATA_WIDTH93 [2:0]
WSEQ_DELAY93 [3:0]
WSEQ_DATA_WIDTH94 [2:0]
WSEQ_DELAY94 [3:0]
WSEQ_DATA_WIDTH95 [2:0]
WSEQ_DELAY95 [3:0]
WSEQ_DATA_WIDTH96 [2:0]
WSEQ_DELAY96 [3:0]
WSEQ_DATA_WIDTH97 [2:0]
WSEQ_DELAY97 [3:0]
WSEQ_DATA_WIDTH98 [2:0]
WSEQ_DELAY98 [3:0]
WSEQ_DATA_WIDTH99 [2:0]
WSEQ_DELAY99 [3:0]
WSEQ_DATA_WIDTH100 [2:0]
WSEQ_DELAY100 [3:0]
WSEQ_DATA_WIDTH101 [2:0]
WSEQ_DELAY101 [3:0]
WSEQ_DATA_WIDTH102 [2:0]
WSEQ_DELAY102 [3:0]
WSEQ_DATA_WIDTH103 [2:0]
WSEQ_DELAY103 [3:0]
WSEQ_DATA_WIDTH104 [2:0]
WSEQ_DELAY104 [3:0]
WSEQ_DATA_WIDTH105 [2:0]
WSEQ_DELAY105 [3:0]
WSEQ_DATA_WIDTH106 [2:0]
WSEQ_DELAY106 [3:0]
WSEQ_DATA_WIDTH107 [2:0]
WSEQ_DELAY107 [3:0]
WSEQ_DATA_WIDTH108 [2:0]
WSEQ_DELAY108 [3:0]
WSEQ_DATA_WIDTH109 [2:0]
WSEQ_DELAY109 [3:0]
WSEQ_DATA_WIDTH110 [2:0]
WSEQ_DELAY110 [3:0]
WSEQ_DATA_WIDTH111 [2:0]
WSEQ_DELAY111 [3:0]
WSEQ_DATA_WIDTH112 [2:0]
WSEQ_DELAY112 [3:0]
WSEQ_DATA_WIDTH113 [2:0]
WSEQ_DELAY113 [3:0]
WSEQ_DATA_WIDTH114 [2:0]
WSEQ_DELAY114 [3:0]
WSEQ_DATA_WIDTH115 [2:0]
WSEQ_DELAY115 [3:0]
WSEQ_DATA_WIDTH116 [2:0]
WSEQ_DELAY116 [3:0]
WSEQ_DATA_WIDTH117 [2:0]
WSEQ_DELAY117 [3:0]
WSEQ_DATA_WIDTH118 [2:0]
WSEQ_DELAY118 [3:0]
WSEQ_DATA_WIDTH119 [2:0]
WSEQ_DELAY119 [3:0]
WSEQ_DATA_WIDTH120 [2:0]
WSEQ_DELAY120 [3:0]
WSEQ_DATA_WIDTH121 [2:0]
WSEQ_DELAY121 [3:0]
WSEQ_DATA_WIDTH122 [2:0]
WSEQ_DELAY122 [3:0]
WSEQ_DATA_WIDTH123 [2:0]
WSEQ_DELAY123 [3:0]
WSEQ_DATA_WIDTH124 [2:0]
WSEQ_DELAY124 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA89 [7:0]
A4AE301Dh
WSEQ_ADDR90 [12:0]
WSEQ_DATA_START90 [3:0]
WSEQ_DATA90 [7:0]
A4AE203Ch
WSEQ_ADDR91 [12:0]
WSEQ_DATA_START91 [3:0]
WSEQ_DATA91 [7:0]
A4AE303Ch
WSEQ_ADDR92 [12:0]
WSEQ_DATA_START92 [3:0]
WSEQ_DATA92 [7:0]
026D4F01h
WSEQ_ADDR93 [12:0]
WSEQ_DATA_START93 [3:0]
WSEQ_DATA93 [7:0]
026D0100h
WSEQ_ADDR94 [12:0]
WSEQ_DATA_START94 [3:0]
WSEQ_DATA94 [7:0]
04B00200h
WSEQ_ADDR95 [12:0]
WSEQ_DATA_START95 [3:0]
WSEQ_DATA95 [7:0]
04C7F101h
WSEQ_ADDR96 [12:0]
WSEQ_DATA_START96 [3:0]
WSEQ_DATA96 [7:0]
0000F000h
WSEQ_ADDR97 [12:0]
WSEQ_DATA_START97 [3:0]
WSEQ_DATA97 [7:0]
0000F000h
WSEQ_ADDR98 [12:0]
WSEQ_DATA_START98 [3:0]
WSEQ_DATA98 [7:0]
0000F000h
WSEQ_ADDR99 [12:0]
WSEQ_DATA_START99 [3:0]
WSEQ_DATA99 [7:0]
0000F000h
WSEQ_ADDR100 [12:0]
WSEQ_DATA_START100 [3:0]
WSEQ_DATA100 [7:0]
0000F000h
WSEQ_ADDR101 [12:0]
WSEQ_DATA_START101 [3:0]
WSEQ_DATA101 [7:0]
0000F000h
WSEQ_ADDR102 [12:0]
WSEQ_DATA_START102 [3:0]
WSEQ_DATA102 [7:0]
0000F000h
WSEQ_ADDR103 [12:0]
WSEQ_DATA_START103 [3:0]
WSEQ_DATA103 [7:0]
0000F000h
WSEQ_ADDR104 [12:0]
WSEQ_DATA_START104 [3:0]
WSEQ_DATA104 [7:0]
0000F000h
WSEQ_ADDR105 [12:0]
WSEQ_DATA_START105 [3:0]
WSEQ_DATA105 [7:0]
026D0101h
WSEQ_ADDR106 [12:0]
WSEQ_DATA_START106 [3:0]
WSEQ_DATA106 [7:0]
A4AE101Dh
WSEQ_ADDR107 [12:0]
WSEQ_DATA_START107 [3:0]
WSEQ_DATA107 [7:0]
A4AE0003h
WSEQ_ADDR108 [12:0]
WSEQ_DATA_START108 [3:0]
WSEQ_DATA108 [7:0]
04AE1800h
WSEQ_ADDR109 [12:0]
WSEQ_DATA_START109 [3:0]
WSEQ_DATA109 [7:0]
04024700h
WSEQ_ADDR110 [12:0]
WSEQ_DATA_START110 [3:0]
WSEQ_DATA110 [7:0]
A4AE0003h
WSEQ_ADDR111 [12:0]
WSEQ_DATA_START111 [3:0]
WSEQ_DATA111 [7:0]
026D0F00h
WSEQ_ADDR112 [12:0]
WSEQ_DATA_START112 [3:0]
WSEQ_DATA112 [7:0]
04C7F301h
WSEQ_ADDR113 [12:0]
WSEQ_DATA_START113 [3:0]
WSEQ_DATA113 [7:0]
0000F000h
WSEQ_ADDR114 [12:0]
WSEQ_DATA_START114 [3:0]
WSEQ_DATA114 [7:0]
0000F000h
WSEQ_ADDR115 [12:0]
WSEQ_DATA_START115 [3:0]
WSEQ_DATA115 [7:0]
0000F000h
WSEQ_ADDR116 [12:0]
WSEQ_DATA_START116 [3:0]
WSEQ_DATA116 [7:0]
0000F000h
WSEQ_ADDR117 [12:0]
WSEQ_DATA_START117 [3:0]
WSEQ_DATA117 [7:0]
0000F000h
WSEQ_ADDR118 [12:0]
WSEQ_DATA_START118 [3:0]
WSEQ_DATA118 [7:0]
0000F000h
WSEQ_ADDR119 [12:0]
WSEQ_DATA_START119 [3:0]
WSEQ_DATA119 [7:0]
0000F000h
WSEQ_ADDR120 [12:0]
WSEQ_DATA_START120 [3:0]
WSEQ_DATA120 [7:0]
0000F000h
WSEQ_ADDR121 [12:0]
WSEQ_DATA_START121 [3:0]
WSEQ_DATA121 [7:0]
0000F000h
WSEQ_ADDR122 [12:0]
WSEQ_DATA_START122 [3:0]
WSEQ_DATA122 [7:0]
0000F000h
WSEQ_ADDR123 [12:0]
WSEQ_DATA_START123 [3:0]
WSEQ_DATA123 [7:0]
0000F000h
WSEQ_ADDR124 [12:0]
WSEQ_DATA_START124 [3:0]
17
1
A4AE201Fh
WSEQ_ADDR89 [12:0]
WSEQ_DATA_START89 [3:0]
18
2
WSEQ_DATA124 [7:0]
259
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12538 WSEQ_Sequence_126
(30FAh)
R12540 WSEQ_Sequence_127
(30FCh)
R12542 WSEQ_Sequence_128
(30FEh)
R12544 WSEQ_Sequence_129
(3100h)
R12546 WSEQ_Sequence_130
(3102h)
R12548 WSEQ_Sequence_131
(3104h)
R12550 WSEQ_Sequence_132
(3106h)
R12552 WSEQ_Sequence_133
(3108h)
R12554 WSEQ_Sequence_134
(310Ah)
R12556 WSEQ_Sequence_135
(310Ch)
R12558 WSEQ_Sequence_136
(310Eh)
R12560 WSEQ_Sequence_137
(3110h)
R12562 WSEQ_Sequence_138
(3112h)
R12564 WSEQ_Sequence_139
(3114h)
R12566 WSEQ_Sequence_140
(3116h)
R12568 WSEQ_Sequence_141
(3118h)
R12570 WSEQ_Sequence_142
(311Ah)
R12572 WSEQ_Sequence_143
(311Ch)
R12574 WSEQ_Sequence_144
(311Eh)
R12576 WSEQ_Sequence_145
(3120h)
R12578 WSEQ_Sequence_146
(3122h)
R12580 WSEQ_Sequence_147
(3124h)
R12582 WSEQ_Sequence_148
(3126h)
R12584 WSEQ_Sequence_149
(3128h)
R12586 WSEQ_Sequence_150
(312Ah)
R12588 WSEQ_Sequence_151
(312Ch)
R12590 WSEQ_Sequence_152
(312Eh)
R12592 WSEQ_Sequence_153
(3130h)
R12594 WSEQ_Sequence_154
(3132h)
R12596 WSEQ_Sequence_155
(3134h)
R12598 WSEQ_Sequence_156
(3136h)
R12600 WSEQ_Sequence_157
(3138h)
R12602 WSEQ_Sequence_158
(313Ah)
R12604 WSEQ_Sequence_159
(313Ch)
R12606 WSEQ_Sequence_160
(313Eh)
R12608 WSEQ_Sequence_161
(3140h)
260
31
15
30
14
29
13
WSEQ_DATA_WIDTH125 [2:0]
WSEQ_DELAY125 [3:0]
WSEQ_DATA_WIDTH126 [2:0]
WSEQ_DELAY126 [3:0]
WSEQ_DATA_WIDTH127 [2:0]
WSEQ_DELAY127 [3:0]
WSEQ_DATA_WIDTH128 [2:0]
WSEQ_DELAY128 [3:0]
WSEQ_DATA_WIDTH129 [2:0]
WSEQ_DELAY129 [3:0]
WSEQ_DATA_WIDTH130 [2:0]
WSEQ_DELAY130 [3:0]
WSEQ_DATA_WIDTH131 [2:0]
WSEQ_DELAY131 [3:0]
WSEQ_DATA_WIDTH132 [2:0]
WSEQ_DELAY132 [3:0]
WSEQ_DATA_WIDTH133 [2:0]
WSEQ_DELAY133 [3:0]
WSEQ_DATA_WIDTH134 [2:0]
WSEQ_DELAY134 [3:0]
WSEQ_DATA_WIDTH135 [2:0]
WSEQ_DELAY135 [3:0]
WSEQ_DATA_WIDTH136 [2:0]
WSEQ_DELAY136 [3:0]
WSEQ_DATA_WIDTH137 [2:0]
WSEQ_DELAY137 [3:0]
WSEQ_DATA_WIDTH138 [2:0]
WSEQ_DELAY138 [3:0]
WSEQ_DATA_WIDTH139 [2:0]
WSEQ_DELAY139 [3:0]
WSEQ_DATA_WIDTH140 [2:0]
WSEQ_DELAY140 [3:0]
WSEQ_DATA_WIDTH141 [2:0]
WSEQ_DELAY141 [3:0]
WSEQ_DATA_WIDTH142 [2:0]
WSEQ_DELAY142 [3:0]
WSEQ_DATA_WIDTH143 [2:0]
WSEQ_DELAY143 [3:0]
WSEQ_DATA_WIDTH144 [2:0]
WSEQ_DELAY144 [3:0]
WSEQ_DATA_WIDTH145 [2:0]
WSEQ_DELAY145 [3:0]
WSEQ_DATA_WIDTH146 [2:0]
WSEQ_DELAY146 [3:0]
WSEQ_DATA_WIDTH147 [2:0]
WSEQ_DELAY147 [3:0]
WSEQ_DATA_WIDTH148 [2:0]
WSEQ_DELAY148 [3:0]
WSEQ_DATA_WIDTH149 [2:0]
WSEQ_DELAY149 [3:0]
WSEQ_DATA_WIDTH150 [2:0]
WSEQ_DELAY150 [3:0]
WSEQ_DATA_WIDTH151 [2:0]
WSEQ_DELAY151 [3:0]
WSEQ_DATA_WIDTH152 [2:0]
WSEQ_DELAY152 [3:0]
WSEQ_DATA_WIDTH153 [2:0]
WSEQ_DELAY153 [3:0]
WSEQ_DATA_WIDTH154 [2:0]
WSEQ_DELAY154 [3:0]
WSEQ_DATA_WIDTH155 [2:0]
WSEQ_DELAY155 [3:0]
WSEQ_DATA_WIDTH156 [2:0]
WSEQ_DELAY156 [3:0]
WSEQ_DATA_WIDTH157 [2:0]
WSEQ_DELAY157 [3:0]
WSEQ_DATA_WIDTH158 [2:0]
WSEQ_DELAY158 [3:0]
WSEQ_DATA_WIDTH159 [2:0]
WSEQ_DELAY159 [3:0]
WSEQ_DATA_WIDTH160 [2:0]
WSEQ_DELAY160 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA125 [7:0]
0000F000h
WSEQ_ADDR126 [12:0]
WSEQ_DATA_START126 [3:0]
WSEQ_DATA126 [7:0]
0000F000h
WSEQ_ADDR127 [12:0]
WSEQ_DATA_START127 [3:0]
WSEQ_DATA127 [7:0]
110007FFh
WSEQ_ADDR128 [12:0]
WSEQ_DATA_START128 [3:0]
WSEQ_DATA128 [7:0]
00000100h
WSEQ_ADDR129 [12:0]
WSEQ_DATA_START129 [3:0]
WSEQ_DATA129 [7:0]
A0340000h
WSEQ_ADDR130 [12:0]
WSEQ_DATA_START130 [3:0]
WSEQ_DATA130 [7:0]
E0310000h
WSEQ_ADDR131 [12:0]
WSEQ_DATA_START131 [3:0]
WSEQ_DATA131 [7:0]
A0300800h
WSEQ_ADDR132 [12:0]
WSEQ_DATA_START132 [3:0]
WSEQ_DATA132 [7:0]
E0300000h
WSEQ_ADDR133 [12:0]
WSEQ_DATA_START133 [3:0]
WSEQ_DATA133 [7:0]
11000206h
WSEQ_ADDR134 [12:0]
WSEQ_DATA_START134 [3:0]
WSEQ_DATA134 [7:0]
C0080040h
WSEQ_ADDR135 [12:0]
WSEQ_DATA_START135 [3:0]
WSEQ_DATA135 [7:0]
00080800h
WSEQ_ADDR136 [12:0]
WSEQ_DATA_START136 [3:0]
WSEQ_DATA136 [7:0]
A000001Dh
WSEQ_ADDR137 [12:0]
WSEQ_DATA_START137 [3:0]
WSEQ_DATA137 [7:0]
60090008h
WSEQ_ADDR138 [12:0]
WSEQ_DATA_START138 [3:0]
WSEQ_DATA138 [7:0]
60090808h
WSEQ_ADDR139 [12:0]
WSEQ_DATA_START139 [3:0]
WSEQ_DATA139 [7:0]
11000000h
WSEQ_ADDR140 [12:0]
WSEQ_DATA_START140 [3:0]
WSEQ_DATA140 [7:0]
01200600h
WSEQ_ADDR141 [12:0]
WSEQ_DATA_START141 [3:0]
WSEQ_DATA141 [7:0]
01010600h
WSEQ_ADDR142 [12:0]
WSEQ_DATA_START142 [3:0]
WSEQ_DATA142 [7:0]
41D10005h
WSEQ_ADDR143 [12:0]
WSEQ_DATA_START143 [3:0]
WSEQ_DATA143 [7:0]
E1220080h
WSEQ_ADDR144 [12:0]
WSEQ_DATA_START144 [3:0]
WSEQ_DATA144 [7:0]
E1220825h
WSEQ_ADDR145 [12:0]
WSEQ_DATA_START145 [3:0]
WSEQ_DATA145 [7:0]
E1240080h
WSEQ_ADDR146 [12:0]
WSEQ_DATA_START146 [3:0]
WSEQ_DATA146 [7:0]
E124080Ch
WSEQ_ADDR147 [12:0]
WSEQ_DATA_START147 [3:0]
WSEQ_DATA147 [7:0]
61200007h
WSEQ_ADDR148 [12:0]
WSEQ_DATA_START148 [3:0]
WSEQ_DATA148 [7:0]
01200601h
WSEQ_ADDR149 [12:0]
WSEQ_DATA_START149 [3:0]
WSEQ_DATA149 [7:0]
110007FFh
WSEQ_ADDR150 [12:0]
WSEQ_DATA_START150 [3:0]
WSEQ_DATA150 [7:0]
E0020080h
WSEQ_ADDR151 [12:0]
WSEQ_DATA_START151 [3:0]
WSEQ_DATA151 [7:0]
E0020825h
WSEQ_ADDR152 [12:0]
WSEQ_DATA_START152 [3:0]
WSEQ_DATA152 [7:0]
00000401h
WSEQ_ADDR153 [12:0]
WSEQ_DATA_START153 [3:0]
WSEQ_DATA153 [7:0]
00030001h
WSEQ_ADDR154 [12:0]
WSEQ_DATA_START154 [3:0]
WSEQ_DATA154 [7:0]
0000F101h
WSEQ_ADDR155 [12:0]
WSEQ_DATA_START155 [3:0]
WSEQ_DATA155 [7:0]
0000F000h
WSEQ_ADDR156 [12:0]
WSEQ_DATA_START156 [3:0]
WSEQ_DATA156 [7:0]
0000F000h
WSEQ_ADDR157 [12:0]
WSEQ_DATA_START157 [3:0]
WSEQ_DATA157 [7:0]
0000F000h
WSEQ_ADDR158 [12:0]
WSEQ_DATA_START158 [3:0]
WSEQ_DATA158 [7:0]
0000F000h
WSEQ_ADDR159 [12:0]
WSEQ_DATA_START159 [3:0]
WSEQ_DATA159 [7:0]
0000F000h
WSEQ_ADDR160 [12:0]
WSEQ_DATA_START160 [3:0]
17
1
0000F000h
WSEQ_ADDR125 [12:0]
WSEQ_DATA_START125 [3:0]
18
2
WSEQ_DATA160 [7:0]
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12610 WSEQ_Sequence_162
(3142h)
R12612 WSEQ_Sequence_163
(3144h)
R12614 WSEQ_Sequence_164
(3146h)
R12616 WSEQ_Sequence_165
(3148h)
R12618 WSEQ_Sequence_166
(314Ah)
R12620 WSEQ_Sequence_167
(314Ch)
R12622 WSEQ_Sequence_168
(314Eh)
R12624 WSEQ_Sequence_169
(3150h)
R12626 WSEQ_Sequence_170
(3152h)
R12628 WSEQ_Sequence_171
(3154h)
R12630 WSEQ_Sequence_172
(3156h)
R12632 WSEQ_Sequence_173
(3158h)
R12634 WSEQ_Sequence_174
(315Ah)
R12636 WSEQ_Sequence_175
(315Ch)
R12638 WSEQ_Sequence_176
(315Eh)
R12640 WSEQ_Sequence_177
(3160h)
R12642 WSEQ_Sequence_178
(3162h)
R12644 WSEQ_Sequence_179
(3164h)
R12646 WSEQ_Sequence_180
(3166h)
R12648 WSEQ_Sequence_181
(3168h)
R12650 WSEQ_Sequence_182
(316Ah)
R12652 WSEQ_Sequence_183
(316Ch)
R12654 WSEQ_Sequence_184
(316Eh)
R12656 WSEQ_Sequence_185
(3170h)
R12658 WSEQ_Sequence_186
(3172h)
R12660 WSEQ_Sequence_187
(3174h)
R12662 WSEQ_Sequence_188
(3176h)
R12664 WSEQ_Sequence_189
(3178h)
R12666 WSEQ_Sequence_190
(317Ah)
R12668 WSEQ_Sequence_191
(317Ch)
R12670 WSEQ_Sequence_192
(317Eh)
R12672 WSEQ_Sequence_193
(3180h)
R12674 WSEQ_Sequence_194
(3182h)
R12676 WSEQ_Sequence_195
(3184h)
R12678 WSEQ_Sequence_196
(3186h)
R12680 WSEQ_Sequence_197
(3188h)
DS1137PP1
31
15
30
14
29
13
WSEQ_DATA_WIDTH161 [2:0]
WSEQ_DELAY161 [3:0]
WSEQ_DATA_WIDTH162 [2:0]
WSEQ_DELAY162 [3:0]
WSEQ_DATA_WIDTH163 [2:0]
WSEQ_DELAY163 [3:0]
WSEQ_DATA_WIDTH164 [2:0]
WSEQ_DELAY164 [3:0]
WSEQ_DATA_WIDTH165 [2:0]
WSEQ_DELAY165 [3:0]
WSEQ_DATA_WIDTH166 [2:0]
WSEQ_DELAY166 [3:0]
WSEQ_DATA_WIDTH167 [2:0]
WSEQ_DELAY167 [3:0]
WSEQ_DATA_WIDTH168 [2:0]
WSEQ_DELAY168 [3:0]
WSEQ_DATA_WIDTH169 [2:0]
WSEQ_DELAY169 [3:0]
WSEQ_DATA_WIDTH170 [2:0]
WSEQ_DELAY170 [3:0]
WSEQ_DATA_WIDTH171 [2:0]
WSEQ_DELAY171 [3:0]
WSEQ_DATA_WIDTH172 [2:0]
WSEQ_DELAY172 [3:0]
WSEQ_DATA_WIDTH173 [2:0]
WSEQ_DELAY173 [3:0]
WSEQ_DATA_WIDTH174 [2:0]
WSEQ_DELAY174 [3:0]
WSEQ_DATA_WIDTH175 [2:0]
WSEQ_DELAY175 [3:0]
WSEQ_DATA_WIDTH176 [2:0]
WSEQ_DELAY176 [3:0]
WSEQ_DATA_WIDTH177 [2:0]
WSEQ_DELAY177 [3:0]
WSEQ_DATA_WIDTH178 [2:0]
WSEQ_DELAY178 [3:0]
WSEQ_DATA_WIDTH179 [2:0]
WSEQ_DELAY179 [3:0]
WSEQ_DATA_WIDTH180 [2:0]
WSEQ_DELAY180 [3:0]
WSEQ_DATA_WIDTH181 [2:0]
WSEQ_DELAY181 [3:0]
WSEQ_DATA_WIDTH182 [2:0]
WSEQ_DELAY182 [3:0]
WSEQ_DATA_WIDTH183 [2:0]
WSEQ_DELAY183 [3:0]
WSEQ_DATA_WIDTH184 [2:0]
WSEQ_DELAY184 [3:0]
WSEQ_DATA_WIDTH185 [2:0]
WSEQ_DELAY185 [3:0]
WSEQ_DATA_WIDTH186 [2:0]
WSEQ_DELAY186 [3:0]
WSEQ_DATA_WIDTH187 [2:0]
WSEQ_DELAY187 [3:0]
WSEQ_DATA_WIDTH188 [2:0]
WSEQ_DELAY188 [3:0]
WSEQ_DATA_WIDTH189 [2:0]
WSEQ_DELAY189 [3:0]
WSEQ_DATA_WIDTH190 [2:0]
WSEQ_DELAY190 [3:0]
WSEQ_DATA_WIDTH191 [2:0]
WSEQ_DELAY191 [3:0]
WSEQ_DATA_WIDTH192 [2:0]
WSEQ_DELAY192 [3:0]
WSEQ_DATA_WIDTH193 [2:0]
WSEQ_DELAY193 [3:0]
WSEQ_DATA_WIDTH194 [2:0]
WSEQ_DELAY194 [3:0]
WSEQ_DATA_WIDTH195 [2:0]
WSEQ_DELAY195 [3:0]
WSEQ_DATA_WIDTH196 [2:0]
WSEQ_DELAY196 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA161 [7:0]
0000F000h
WSEQ_ADDR162 [12:0]
WSEQ_DATA_START162 [3:0]
WSEQ_DATA162 [7:0]
0000F000h
WSEQ_ADDR163 [12:0]
WSEQ_DATA_START163 [3:0]
WSEQ_DATA163 [7:0]
0000F000h
WSEQ_ADDR164 [12:0]
WSEQ_DATA_START164 [3:0]
WSEQ_DATA164 [7:0]
0000F000h
WSEQ_ADDR165 [12:0]
WSEQ_DATA_START165 [3:0]
WSEQ_DATA165 [7:0]
0000F000h
WSEQ_ADDR166 [12:0]
WSEQ_DATA_START166 [3:0]
WSEQ_DATA166 [7:0]
0000F000h
WSEQ_ADDR167 [12:0]
WSEQ_DATA_START167 [3:0]
WSEQ_DATA167 [7:0]
0000F000h
WSEQ_ADDR168 [12:0]
WSEQ_DATA_START168 [3:0]
WSEQ_DATA168 [7:0]
0000F000h
WSEQ_ADDR169 [12:0]
WSEQ_DATA_START169 [3:0]
WSEQ_DATA169 [7:0]
0000F000h
WSEQ_ADDR170 [12:0]
WSEQ_DATA_START170 [3:0]
WSEQ_DATA170 [7:0]
0000F000h
WSEQ_ADDR171 [12:0]
WSEQ_DATA_START171 [3:0]
WSEQ_DATA171 [7:0]
0000F000h
WSEQ_ADDR172 [12:0]
WSEQ_DATA_START172 [3:0]
WSEQ_DATA172 [7:0]
0000F000h
WSEQ_ADDR173 [12:0]
WSEQ_DATA_START173 [3:0]
WSEQ_DATA173 [7:0]
0000F000h
WSEQ_ADDR174 [12:0]
WSEQ_DATA_START174 [3:0]
WSEQ_DATA174 [7:0]
0000F000h
WSEQ_ADDR175 [12:0]
WSEQ_DATA_START175 [3:0]
WSEQ_DATA175 [7:0]
0000F000h
WSEQ_ADDR176 [12:0]
WSEQ_DATA_START176 [3:0]
WSEQ_DATA176 [7:0]
0000F000h
WSEQ_ADDR177 [12:0]
WSEQ_DATA_START177 [3:0]
WSEQ_DATA177 [7:0]
0000F000h
WSEQ_ADDR178 [12:0]
WSEQ_DATA_START178 [3:0]
WSEQ_DATA178 [7:0]
0000F000h
WSEQ_ADDR179 [12:0]
WSEQ_DATA_START179 [3:0]
WSEQ_DATA179 [7:0]
0000F000h
WSEQ_ADDR180 [12:0]
WSEQ_DATA_START180 [3:0]
WSEQ_DATA180 [7:0]
0000F000h
WSEQ_ADDR181 [12:0]
WSEQ_DATA_START181 [3:0]
WSEQ_DATA181 [7:0]
0000F000h
WSEQ_ADDR182 [12:0]
WSEQ_DATA_START182 [3:0]
WSEQ_DATA182 [7:0]
0000F000h
WSEQ_ADDR183 [12:0]
WSEQ_DATA_START183 [3:0]
WSEQ_DATA183 [7:0]
0000F000h
WSEQ_ADDR184 [12:0]
WSEQ_DATA_START184 [3:0]
WSEQ_DATA184 [7:0]
0000F000h
WSEQ_ADDR185 [12:0]
WSEQ_DATA_START185 [3:0]
WSEQ_DATA185 [7:0]
0000F000h
WSEQ_ADDR186 [12:0]
WSEQ_DATA_START186 [3:0]
WSEQ_DATA186 [7:0]
0000F000h
WSEQ_ADDR187 [12:0]
WSEQ_DATA_START187 [3:0]
WSEQ_DATA187 [7:0]
0000F000h
WSEQ_ADDR188 [12:0]
WSEQ_DATA_START188 [3:0]
WSEQ_DATA188 [7:0]
0000F000h
WSEQ_ADDR189 [12:0]
WSEQ_DATA_START189 [3:0]
WSEQ_DATA189 [7:0]
0000F000h
WSEQ_ADDR190 [12:0]
WSEQ_DATA_START190 [3:0]
WSEQ_DATA190 [7:0]
0000F000h
WSEQ_ADDR191 [12:0]
WSEQ_DATA_START191 [3:0]
WSEQ_DATA191 [7:0]
0000F000h
WSEQ_ADDR192 [12:0]
WSEQ_DATA_START192 [3:0]
WSEQ_DATA192 [7:0]
0000F000h
WSEQ_ADDR193 [12:0]
WSEQ_DATA_START193 [3:0]
WSEQ_DATA193 [7:0]
0000F000h
WSEQ_ADDR194 [12:0]
WSEQ_DATA_START194 [3:0]
WSEQ_DATA194 [7:0]
0000F000h
WSEQ_ADDR195 [12:0]
WSEQ_DATA_START195 [3:0]
WSEQ_DATA195 [7:0]
0000F000h
WSEQ_ADDR196 [12:0]
WSEQ_DATA_START196 [3:0]
17
1
0000F000h
WSEQ_ADDR161 [12:0]
WSEQ_DATA_START161 [3:0]
18
2
WSEQ_DATA196 [7:0]
261
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12682 WSEQ_Sequence_198
(318Ah)
R12684 WSEQ_Sequence_199
(318Ch)
R12686 WSEQ_Sequence_200
(318Eh)
R12688 WSEQ_Sequence_201
(3190h)
R12690 WSEQ_Sequence_202
(3192h)
R12692 WSEQ_Sequence_203
(3194h)
R12694 WSEQ_Sequence_204
(3196h)
R12696 WSEQ_Sequence_205
(3198h)
R12698 WSEQ_Sequence_206
(319Ah)
R12700 WSEQ_Sequence_207
(319Ch)
R12702 WSEQ_Sequence_208
(319Eh)
R12704 WSEQ_Sequence_209
(31A0h)
R12706 WSEQ_Sequence_210
(31A2h)
R12708 WSEQ_Sequence_211
(31A4h)
R12710 WSEQ_Sequence_212
(31A6h)
R12712 WSEQ_Sequence_213
(31A8h)
R12714 WSEQ_Sequence_214
(31AAh)
R12716 WSEQ_Sequence_215
(31ACh)
R12718 WSEQ_Sequence_216
(31AEh)
R12720 WSEQ_Sequence_217
(31B0h)
R12722 WSEQ_Sequence_218
(31B2h)
R12724 WSEQ_Sequence_219
(31B4h)
R12726 WSEQ_Sequence_220
(31B6h)
R12728 WSEQ_Sequence_221
(31B8h)
R12730 WSEQ_Sequence_222
(31BAh)
R12732 WSEQ_Sequence_223
(31BCh)
R12734 WSEQ_Sequence_224
(31BEh)
R12736 WSEQ_Sequence_225
(31C0h)
R12738 WSEQ_Sequence_226
(31C2h)
R12740 WSEQ_Sequence_227
(31C4h)
R12742 WSEQ_Sequence_228
(31C6h)
R12744 WSEQ_Sequence_229
(31C8h)
R12746 WSEQ_Sequence_230
(31CAh)
R12748 WSEQ_Sequence_231
(31CCh)
R12750 WSEQ_Sequence_232
(31CEh)
R12752 WSEQ_Sequence_233
(31D0h)
262
31
15
30
14
29
13
WSEQ_DATA_WIDTH197 [2:0]
WSEQ_DELAY197 [3:0]
WSEQ_DATA_WIDTH198 [2:0]
WSEQ_DELAY198 [3:0]
WSEQ_DATA_WIDTH199 [2:0]
WSEQ_DELAY199 [3:0]
WSEQ_DATA_WIDTH200 [2:0]
WSEQ_DELAY200 [3:0]
WSEQ_DATA_WIDTH201 [2:0]
WSEQ_DELAY201 [3:0]
WSEQ_DATA_WIDTH202 [2:0]
WSEQ_DELAY202 [3:0]
WSEQ_DATA_WIDTH203 [2:0]
WSEQ_DELAY203 [3:0]
WSEQ_DATA_WIDTH204 [2:0]
WSEQ_DELAY204 [3:0]
WSEQ_DATA_WIDTH205 [2:0]
WSEQ_DELAY205 [3:0]
WSEQ_DATA_WIDTH206 [2:0]
WSEQ_DELAY206 [3:0]
WSEQ_DATA_WIDTH207 [2:0]
WSEQ_DELAY207 [3:0]
WSEQ_DATA_WIDTH208 [2:0]
WSEQ_DELAY208 [3:0]
WSEQ_DATA_WIDTH209 [2:0]
WSEQ_DELAY209 [3:0]
WSEQ_DATA_WIDTH210 [2:0]
WSEQ_DELAY210 [3:0]
WSEQ_DATA_WIDTH211 [2:0]
WSEQ_DELAY211 [3:0]
WSEQ_DATA_WIDTH212 [2:0]
WSEQ_DELAY212 [3:0]
WSEQ_DATA_WIDTH213 [2:0]
WSEQ_DELAY213 [3:0]
WSEQ_DATA_WIDTH214 [2:0]
WSEQ_DELAY214 [3:0]
WSEQ_DATA_WIDTH215 [2:0]
WSEQ_DELAY215 [3:0]
WSEQ_DATA_WIDTH216 [2:0]
WSEQ_DELAY216 [3:0]
WSEQ_DATA_WIDTH217 [2:0]
WSEQ_DELAY217 [3:0]
WSEQ_DATA_WIDTH218 [2:0]
WSEQ_DELAY218 [3:0]
WSEQ_DATA_WIDTH219 [2:0]
WSEQ_DELAY219 [3:0]
WSEQ_DATA_WIDTH220 [2:0]
WSEQ_DELAY220 [3:0]
WSEQ_DATA_WIDTH221 [2:0]
WSEQ_DELAY221 [3:0]
WSEQ_DATA_WIDTH222 [2:0]
WSEQ_DELAY222 [3:0]
WSEQ_DATA_WIDTH223 [2:0]
WSEQ_DELAY223 [3:0]
WSEQ_DATA_WIDTH224 [2:0]
WSEQ_DELAY224 [3:0]
WSEQ_DATA_WIDTH225 [2:0]
WSEQ_DELAY225 [3:0]
WSEQ_DATA_WIDTH226 [2:0]
WSEQ_DELAY226 [3:0]
WSEQ_DATA_WIDTH227 [2:0]
WSEQ_DELAY227 [3:0]
WSEQ_DATA_WIDTH228 [2:0]
WSEQ_DELAY228 [3:0]
WSEQ_DATA_WIDTH229 [2:0]
WSEQ_DELAY229 [3:0]
WSEQ_DATA_WIDTH230 [2:0]
WSEQ_DELAY230 [3:0]
WSEQ_DATA_WIDTH231 [2:0]
WSEQ_DELAY231 [3:0]
WSEQ_DATA_WIDTH232 [2:0]
WSEQ_DELAY232 [3:0]
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
16
0
Default
WSEQ_DATA197 [7:0]
0000F000h
WSEQ_ADDR198 [12:0]
WSEQ_DATA_START198 [3:0]
WSEQ_DATA198 [7:0]
0000F000h
WSEQ_ADDR199 [12:0]
WSEQ_DATA_START199 [3:0]
WSEQ_DATA199 [7:0]
0000F000h
WSEQ_ADDR200 [12:0]
WSEQ_DATA_START200 [3:0]
WSEQ_DATA200 [7:0]
0000F000h
WSEQ_ADDR201 [12:0]
WSEQ_DATA_START201 [3:0]
WSEQ_DATA201 [7:0]
0000F000h
WSEQ_ADDR202 [12:0]
WSEQ_DATA_START202 [3:0]
WSEQ_DATA202 [7:0]
0000F000h
WSEQ_ADDR203 [12:0]
WSEQ_DATA_START203 [3:0]
WSEQ_DATA203 [7:0]
0000F000h
WSEQ_ADDR204 [12:0]
WSEQ_DATA_START204 [3:0]
WSEQ_DATA204 [7:0]
0000F000h
WSEQ_ADDR205 [12:0]
WSEQ_DATA_START205 [3:0]
WSEQ_DATA205 [7:0]
0000F000h
WSEQ_ADDR206 [12:0]
WSEQ_DATA_START206 [3:0]
WSEQ_DATA206 [7:0]
0000F000h
WSEQ_ADDR207 [12:0]
WSEQ_DATA_START207 [3:0]
WSEQ_DATA207 [7:0]
0000F000h
WSEQ_ADDR208 [12:0]
WSEQ_DATA_START208 [3:0]
WSEQ_DATA208 [7:0]
0000F000h
WSEQ_ADDR209 [12:0]
WSEQ_DATA_START209 [3:0]
WSEQ_DATA209 [7:0]
0000F000h
WSEQ_ADDR210 [12:0]
WSEQ_DATA_START210 [3:0]
WSEQ_DATA210 [7:0]
0000F000h
WSEQ_ADDR211 [12:0]
WSEQ_DATA_START211 [3:0]
WSEQ_DATA211 [7:0]
0000F000h
WSEQ_ADDR212 [12:0]
WSEQ_DATA_START212 [3:0]
WSEQ_DATA212 [7:0]
0000F000h
WSEQ_ADDR213 [12:0]
WSEQ_DATA_START213 [3:0]
WSEQ_DATA213 [7:0]
0000F000h
WSEQ_ADDR214 [12:0]
WSEQ_DATA_START214 [3:0]
WSEQ_DATA214 [7:0]
0000F000h
WSEQ_ADDR215 [12:0]
WSEQ_DATA_START215 [3:0]
WSEQ_DATA215 [7:0]
0000F000h
WSEQ_ADDR216 [12:0]
WSEQ_DATA_START216 [3:0]
WSEQ_DATA216 [7:0]
0000F000h
WSEQ_ADDR217 [12:0]
WSEQ_DATA_START217 [3:0]
WSEQ_DATA217 [7:0]
0000F000h
WSEQ_ADDR218 [12:0]
WSEQ_DATA_START218 [3:0]
WSEQ_DATA218 [7:0]
0000F000h
WSEQ_ADDR219 [12:0]
WSEQ_DATA_START219 [3:0]
WSEQ_DATA219 [7:0]
0000F000h
WSEQ_ADDR220 [12:0]
WSEQ_DATA_START220 [3:0]
WSEQ_DATA220 [7:0]
0000F000h
WSEQ_ADDR221 [12:0]
WSEQ_DATA_START221 [3:0]
WSEQ_DATA221 [7:0]
0000F000h
WSEQ_ADDR222 [12:0]
WSEQ_DATA_START222 [3:0]
WSEQ_DATA222 [7:0]
0000F000h
WSEQ_ADDR223 [12:0]
WSEQ_DATA_START223 [3:0]
WSEQ_DATA223 [7:0]
FFFFFFFFh
WSEQ_ADDR224 [12:0]
WSEQ_DATA_START224 [3:0]
WSEQ_DATA224 [7:0]
FFFFFFFFh
WSEQ_ADDR225 [12:0]
WSEQ_DATA_START225 [3:0]
WSEQ_DATA225 [7:0]
FFFFFFFFh
WSEQ_ADDR226 [12:0]
WSEQ_DATA_START226 [3:0]
WSEQ_DATA226 [7:0]
FFFFFFFFh
WSEQ_ADDR227 [12:0]
WSEQ_DATA_START227 [3:0]
WSEQ_DATA227 [7:0]
FFFFFFFFh
WSEQ_ADDR228 [12:0]
WSEQ_DATA_START228 [3:0]
WSEQ_DATA228 [7:0]
FFFFFFFFh
WSEQ_ADDR229 [12:0]
WSEQ_DATA_START229 [3:0]
WSEQ_DATA229 [7:0]
FFFFFFFFh
WSEQ_ADDR230 [12:0]
WSEQ_DATA_START230 [3:0]
WSEQ_DATA230 [7:0]
FFFFFFFFh
WSEQ_ADDR231 [12:0]
WSEQ_DATA_START231 [3:0]
WSEQ_DATA231 [7:0]
FFFFFFFFh
WSEQ_ADDR232 [12:0]
WSEQ_DATA_START232 [3:0]
17
1
0000F000h
WSEQ_ADDR197 [12:0]
WSEQ_DATA_START197 [3:0]
18
2
WSEQ_DATA232 [7:0]
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R12754 WSEQ_Sequence_234
(31D2h)
R12756 WSEQ_Sequence_235
(31D4h)
R12758 WSEQ_Sequence_236
(31D6h)
R12760 WSEQ_Sequence_237
(31D8h)
R12762 WSEQ_Sequence_238
(31DAh)
R12764 WSEQ_Sequence_239
(31DCh)
R12766 WSEQ_Sequence_240
(31DEh)
R12768 WSEQ_Sequence_241
(31E0h)
R12770 WSEQ_Sequence_242
(31E2h)
R12772 WSEQ_Sequence_243
(31E4h)
R12774 WSEQ_Sequence_244
(31E6h)
R12776 WSEQ_Sequence_245
(31E8h)
R12778 WSEQ_Sequence_246
(31EAh)
R12780 WSEQ_Sequence_247
(31ECh)
R12782 WSEQ_Sequence_248
(31EEh)
R12784 WSEQ_Sequence_249
(31F0h)
R12786 WSEQ_Sequence_250
(31F2h)
R12788 WSEQ_Sequence_251
(31F4h)
R12790 WSEQ_Sequence_252
(31F6h)
R131076 OTP_HPDET_Cal_1
(20004h)
R131078 OTP_HPDET_Cal_2
(20006h)
R265216 MIF4_SPI_CLK_
(40C00h) CONFIG
R265222 MIF4_SPI_CLK_
(40C06h) STATUS_1
R265224 MIF4_SPI_CONFIG_1
(40C08h)
R265226 MIF4_SPI_CONFIG_2
(40C0Ah)
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
WSEQ_DATA_WIDTH233 [2:0]
WSEQ_ADDR233 [12:0]
WSEQ_DELAY233 [3:0]
WSEQ_DATA_START233 [3:0]
WSEQ_DATA_WIDTH234 [2:0]
WSEQ_ADDR234 [12:0]
WSEQ_DELAY234 [3:0]
WSEQ_DATA_START234 [3:0]
WSEQ_DATA_WIDTH235 [2:0]
WSEQ_ADDR235 [12:0]
WSEQ_DELAY235 [3:0]
WSEQ_DATA_START235 [3:0]
WSEQ_DATA_WIDTH236 [2:0]
WSEQ_ADDR236 [12:0]
WSEQ_DELAY236 [3:0]
WSEQ_DATA_START236 [3:0]
WSEQ_DATA_WIDTH237 [2:0]
WSEQ_ADDR237 [12:0]
WSEQ_DELAY237 [3:0]
WSEQ_DATA_START237 [3:0]
WSEQ_DATA_WIDTH238 [2:0]
WSEQ_ADDR238 [12:0]
WSEQ_DELAY238 [3:0]
WSEQ_DATA_START238 [3:0]
WSEQ_DATA_WIDTH239 [2:0]
WSEQ_ADDR239 [12:0]
WSEQ_DELAY239 [3:0]
WSEQ_DATA_START239 [3:0]
WSEQ_DATA_WIDTH240 [2:0]
WSEQ_ADDR240 [12:0]
WSEQ_DELAY240 [3:0]
WSEQ_DATA_START240 [3:0]
WSEQ_DATA_WIDTH241 [2:0]
WSEQ_ADDR241 [12:0]
WSEQ_DELAY241 [3:0]
WSEQ_DATA_START241 [3:0]
WSEQ_DATA_WIDTH242 [2:0]
WSEQ_ADDR242 [12:0]
WSEQ_DELAY242 [3:0]
WSEQ_DATA_START242 [3:0]
WSEQ_DATA_WIDTH243 [2:0]
WSEQ_ADDR243 [12:0]
WSEQ_DELAY243 [3:0]
WSEQ_DATA_START243 [3:0]
WSEQ_DATA_WIDTH244 [2:0]
WSEQ_ADDR244 [12:0]
WSEQ_DELAY244 [3:0]
WSEQ_DATA_START244 [3:0]
WSEQ_DATA_WIDTH245 [2:0]
WSEQ_ADDR245 [12:0]
WSEQ_DELAY245 [3:0]
WSEQ_DATA_START245 [3:0]
WSEQ_DATA_WIDTH246 [2:0]
WSEQ_ADDR246 [12:0]
WSEQ_DELAY246 [3:0]
WSEQ_DATA_START246 [3:0]
WSEQ_DATA_WIDTH247 [2:0]
WSEQ_ADDR247 [12:0]
WSEQ_DELAY247 [3:0]
WSEQ_DATA_START247 [3:0]
WSEQ_DATA_WIDTH248 [2:0]
WSEQ_ADDR248 [12:0]
WSEQ_DELAY248 [3:0]
WSEQ_DATA_START248 [3:0]
WSEQ_DATA_WIDTH249 [2:0]
WSEQ_ADDR249 [12:0]
WSEQ_DELAY249 [3:0]
WSEQ_DATA_START249 [3:0]
WSEQ_DATA_WIDTH250 [2:0]
WSEQ_ADDR250 [12:0]
WSEQ_DELAY250 [3:0]
WSEQ_DATA_START250 [3:0]
WSEQ_DATA_WIDTH251 [2:0]
WSEQ_ADDR251 [12:0]
WSEQ_DELAY251 [3:0]
WSEQ_DATA_START251 [3:0]
HP_OFFSET_11 [7:0]
HP_OFFSET_01 [7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HP_GRADIENT_1X [7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MIF4_SCLK_FREQ_STS [15:0]
0
0
0
0
MIF4_SS_IDLE_COUNT [3:0]
0
0
0
0
0
0
0
0
0
0
MIF4_3_
0
MIF4_
MIF4_
WIRE
DPHA
CPHA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
4
19
3
18
2
17
1
16
0
FFFFFFFFh
WSEQ_DATA233 [7:0]
FFFFFFFFh
WSEQ_DATA234 [7:0]
FFFFFFFFh
WSEQ_DATA235 [7:0]
FFFFFFFFh
WSEQ_DATA236 [7:0]
FFFFFFFFh
WSEQ_DATA237 [7:0]
FFFFFFFFh
WSEQ_DATA238 [7:0]
FFFFFFFFh
WSEQ_DATA239 [7:0]
FFFFFFFFh
WSEQ_DATA240 [7:0]
FFFFFFFFh
WSEQ_DATA241 [7:0]
FFFFFFFFh
WSEQ_DATA242 [7:0]
FFFFFFFFh
WSEQ_DATA243 [7:0]
FFFFFFFFh
WSEQ_DATA244 [7:0]
FFFFFFFFh
WSEQ_DATA245 [7:0]
FFFFFFFFh
WSEQ_DATA246 [7:0]
FFFFFFFFh
WSEQ_DATA247 [7:0]
FFFFFFFFh
WSEQ_DATA248 [7:0]
FFFFFFFFh
WSEQ_DATA249 [7:0]
FFFFFFFFh
WSEQ_DATA250 [7:0]
FFFFFFFFh
WSEQ_DATA251 [7:0]
HP_OFFSET_10 [7:0]
0
0
0
0
0
0
HP_GRADIENT_0X [7:0]
0
0
0
MIF4_SCLK_FREQ_SEL [5:0]
0
0
0
0
MIF4_
CPOL
0
0
0
0
0
00000000h
0
0
00000000h
0
0
00000000h
00000000h
MIF4_SS_DELAY_COUNT [3:0]
MIF4_SS_SEL [2:0]
R265228 MIF4_SPI_CONFIG_4
(40C0Ch)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R265344 MIF4_SPI_STATUS_1
(40C80h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R265346 MIF4_SPI_STATUS_2
(40C82h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R265472 MIF4_CONFIG_1
(40D00h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R265474 MIF4_CONFIG_2
(40D02h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R265478 MIF4_CONFIG_4
(40D06h)
0
0
0
0
0
0
0
0
0
R265488 MIF4_CONFIG_5
(40D10h)
0
0
0
0
0
0
0
0
0
MIF4_RX_LENGTH [20:16]
R265490 MIF4_CONFIG_6
(40D12h)
0
0
0
0
0
0
0
0
0
0
DS1137PP1
0
0
MIF4_READ_WRITE_
SEL [1:0]
0
0
0
0
00000000h
0
0
0
MIF4_SS_
OVD
0
0
0
0
0
0
0
MIF4_
WDT_ENA
0
0
0
0
0
0
MIF4_
MIF4_
ABORT_ DONE_
STS
STS
0
0
0
0
0
0
0
MIF4_
STALL_
STS
0
0
0
0
0
0
0
MIF4_
START
0
0
0
0
0
0
0
MIF4_
ABORT
MIF4_TX_LENGTH [20:16]
0
0
MIF4_TX_LENGTH [15:0]
0
0
MIF4_RX_LENGTH [15:0]
0
0
0
0
Default
0
0
0
0
0
MIF4_TX_BLOCK_LENGTH [6:0]
0
0
0
0
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
263
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R265492 MIF4_CONFIG_7
(40D14h)
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MIF4_RX_
DONE (U)
0
0
0
0
20
4
19
3
18
2
17
1
16
0
0
0
0
0
0
0
0
0
R265602 MIF4_STATUS_2
(40D82h)
0
0
0
0
0
0
0
0
0
0
0
0
0
MIF4_RX_BLOCK_LENGTH [6:0]
0
0
0
0
0
0
0
MIF4_WORD_SIZE [2:0]
0
0
0
0
0
0
0
0
0
MIF4_TX_
DONE
0
0
0
0
MIF4_
BUSY_
STS
0
0
0
0
MIF4_TX_
REQUEST
MIF4_TX_BYTE_COUNT [20:16]
R265604 MIF4_STATUS_3
(40D84h)
0
0
0
0
0
0
0
MIF4_RX_BYTE_COUNT [20:16]
R265494 MIF4_CONFIG_8
(40D16h)
R265496 MIF4_CONFIG_9
(40D18h)
R265600 MIF4_STATUS_1
(40D80h)
R265728 MIF4_TX_1
(40E00h)
R265730 MIF4_TX_2
(40E02h)
R265732 MIF4_TX_3
(40E04h)
R265734 MIF4_TX_4
(40E06h)
R265736 MIF4_TX_5
(40E08h)
R265738 MIF4_TX_6
(40E0Ah)
R265740 MIF4_TX_7
(40E0Ch)
R265742 MIF4_TX_8
(40E0Eh)
R265744 MIF4_TX_9
(40E10h)
R265746 MIF4_TX_10
(40E12h)
R265748 MIF4_TX_11
(40E14h)
R265750 MIF4_TX_12
(40E16h)
R265752 MIF4_TX_13
(40E18h)
R265754 MIF4_TX_14
(40E1Ah)
R265756 MIF4_TX_15
(40E1Ch)
R265758 MIF4_TX_16
(40E1Eh)
R265984 MIF4_RX_1
(40F00h)
R265986 MIF4_RX_2
(40F02h)
R265988 MIF4_RX_3
(40F04h)
R265990 MIF4_RX_4
(40F06h)
R265992 MIF4_RX_5
(40F08h)
R265994 MIF4_RX_6
(40F0Ah)
R265996 MIF4_RX_7
(40F0Ch)
R265998 MIF4_RX_8
(40F0Eh)
R266000 MIF4_RX_9
(40F10h)
R266002 MIF4_RX_10
(40F12h)
R266004 MIF4_RX_11
(40F14h)
R266006 MIF4_RX_12
(40F16h)
R266008 MIF4_RX_13
(40F18h)
264
MIF4_TX_BYTE4 [7:0]
MIF4_TX_BYTE2 [7:0]
MIF4_TX_BYTE8 [7:0]
MIF4_TX_BYTE6 [7:0]
MIF4_TX_BYTE12 [7:0]
MIF4_TX_BYTE10 [7:0]
MIF4_TX_BYTE16 [7:0]
MIF4_TX_BYTE14 [7:0]
MIF4_TX_BYTE20 [7:0]
MIF4_TX_BYTE18 [7:0]
MIF4_TX_BYTE24 [7:0]
MIF4_TX_BYTE22 [7:0]
MIF4_TX_BYTE28 [7:0]
MIF4_TX_BYTE26 [7:0]
MIF4_TX_BYTE32 [7:0]
MIF4_TX_BYTE30 [7:0]
MIF4_TX_BYTE36 [7:0]
MIF4_TX_BYTE34 [7:0]
MIF4_TX_BYTE40 [7:0]
MIF4_TX_BYTE38 [7:0]
MIF4_TX_BYTE44 [7:0]
MIF4_TX_BYTE42 [7:0]
MIF4_TX_BYTE48 [7:0]
MIF4_TX_BYTE46 [7:0]
MIF4_TX_BYTE52 [7:0]
MIF4_TX_BYTE50 [7:0]
MIF4_TX_BYTE56 [7:0]
MIF4_TX_BYTE54 [7:0]
MIF4_TX_BYTE60 [7:0]
MIF4_TX_BYTE58 [7:0]
MIF4_TX_BYTE64 [7:0]
MIF4_TX_BYTE62 [7:0]
MIF4_RX_BYTE4 [7:0]
MIF4_RX_BYTE2 [7:0]
MIF4_RX_BYTE8 [7:0]
MIF4_RX_BYTE6 [7:0]
MIF4_RX_BYTE12 [7:0]
MIF4_RX_BYTE10 [7:0]
MIF4_RX_BYTE16 [7:0]
MIF4_RX_BYTE14 [7:0]
MIF4_RX_BYTE20 [7:0]
MIF4_RX_BYTE18 [7:0]
MIF4_RX_BYTE24 [7:0]
MIF4_RX_BYTE22 [7:0]
MIF4_RX_BYTE28 [7:0]
MIF4_RX_BYTE26 [7:0]
MIF4_RX_BYTE32 [7:0]
MIF4_RX_BYTE30 [7:0]
MIF4_RX_BYTE36 [7:0]
MIF4_RX_BYTE34 [7:0]
MIF4_RX_BYTE40 [7:0]
MIF4_RX_BYTE38 [7:0]
MIF4_RX_BYTE44 [7:0]
MIF4_RX_BYTE42 [7:0]
MIF4_RX_BYTE48 [7:0]
MIF4_RX_BYTE46 [7:0]
MIF4_RX_BYTE52 [7:0]
MIF4_RX_BYTE50 [7:0]
MIF4_RX_
0
0
REQUEST
0
0
0
MIF4_TX_BYTE_COUNT [15:0]
0
0
0
0
MIF4_RX_BYTE_COUNT [15:0]
MIF4_TX_BYTE3 [7:0]
MIF4_TX_BYTE1 [7:0]
MIF4_TX_BYTE7 [7:0]
MIF4_TX_BYTE5 [7:0]
MIF4_TX_BYTE11 [7:0]
MIF4_TX_BYTE9 [7:0]
MIF4_TX_BYTE15 [7:0]
MIF4_TX_BYTE13 [7:0]
MIF4_TX_BYTE19 [7:0]
MIF4_TX_BYTE17 [7:0]
MIF4_TX_BYTE23 [7:0]
MIF4_TX_BYTE21 [7:0]
MIF4_TX_BYTE27 [7:0]
MIF4_TX_BYTE25 [7:0]
MIF4_TX_BYTE31 [7:0]
MIF4_TX_BYTE29 [7:0]
MIF4_TX_BYTE35 [7:0]
MIF4_TX_BYTE33 [7:0]
MIF4_TX_BYTE39 [7:0]
MIF4_TX_BYTE37 [7:0]
MIF4_TX_BYTE43 [7:0]
MIF4_TX_BYTE41 [7:0]
MIF4_TX_BYTE47 [7:0]
MIF4_TX_BYTE45 [7:0]
MIF4_TX_BYTE51 [7:0]
MIF4_TX_BYTE49 [7:0]
MIF4_TX_BYTE55 [7:0]
MIF4_TX_BYTE53 [7:0]
MIF4_TX_BYTE59 [7:0]
MIF4_TX_BYTE57 [7:0]
MIF4_TX_BYTE63 [7:0]
MIF4_TX_BYTE61 [7:0]
MIF4_RX_BYTE3 [7:0]
MIF4_RX_BYTE1 [7:0]
MIF4_RX_BYTE7 [7:0]
MIF4_RX_BYTE5 [7:0]
MIF4_RX_BYTE11 [7:0]
MIF4_RX_BYTE9 [7:0]
MIF4_RX_BYTE15 [7:0]
MIF4_RX_BYTE13 [7:0]
MIF4_RX_BYTE19 [7:0]
MIF4_RX_BYTE17 [7:0]
MIF4_RX_BYTE23 [7:0]
MIF4_RX_BYTE21 [7:0]
MIF4_RX_BYTE27 [7:0]
MIF4_RX_BYTE25 [7:0]
MIF4_RX_BYTE31 [7:0]
MIF4_RX_BYTE29 [7:0]
MIF4_RX_BYTE35 [7:0]
MIF4_RX_BYTE33 [7:0]
MIF4_RX_BYTE39 [7:0]
MIF4_RX_BYTE37 [7:0]
MIF4_RX_BYTE43 [7:0]
MIF4_RX_BYTE41 [7:0]
MIF4_RX_BYTE47 [7:0]
MIF4_RX_BYTE45 [7:0]
MIF4_RX_BYTE51 [7:0]
MIF4_RX_BYTE49 [7:0]
Default
00000000h
00000000h
00000000h
00000000h
00000001h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
31
15
30
14
29
13
R266010 MIF4_RX_14
(40F1Ah)
R266012 MIF4_RX_15
(40F1Ch)
R266014 MIF4_RX_16
(40F1Eh)
R294912 EVENTLOG1_
(48000h) CONTROL
0
0
0
0
0
0
R294916 EVENTLOG1_TIMER_
(48004h) SEL
0
0
0
0
0
0
R294924 EVENTLOG1_FIFO_
(4800Ch) CONTROL1
R294926 EVENTLOG1_FIFO_
(4800Eh) POINTER1
R294944 EVENTLOG1_CH_
(48020h) ENABLE1
R294976 EVENTLOG1_CH1_
(48040h) DEFINE
R294978 EVENTLOG1_CH2_
(48042h) DEFINE
R294980 EVENTLOG1_CH3_
(48044h) DEFINE
R294982 EVENTLOG1_CH4_
(48046h) DEFINE
R294984 EVENTLOG1_CH5_
(48048h) DEFINE
R294986 EVENTLOG1_CH6_
(4804Ah) DEFINE
R294988 EVENTLOG1_CH7_
(4804Ch) DEFINE
R294990 EVENTLOG1_CH8_
(4804Eh) DEFINE
R294992 EVENTLOG1_CH9_
(48050h) DEFINE
R294994 EVENTLOG1_CH10_
(48052h) DEFINE
R294996 EVENTLOG1_CH11_
(48054h) DEFINE
R294998 EVENTLOG1_CH12_
(48056h) DEFINE
R295000 EVENTLOG1_CH13_
(48058h) DEFINE
R295002 EVENTLOG1_CH14_
(4805Ah) DEFINE
R295004 EVENTLOG1_CH15_
(4805Ch) DEFINE
DS1137PP1
28
12
27
11
MIF4_RX_BYTE56 [7:0]
MIF4_RX_BYTE54 [7:0]
MIF4_RX_BYTE60 [7:0]
MIF4_RX_BYTE58 [7:0]
MIF4_RX_BYTE64 [7:0]
MIF4_RX_BYTE62 [7:0]
0
0
0
0
0
0
0
0
26
10
25
9
0
0
0
0
0
0
0
0
24
8
0
EVENTLO
G1_FLL_
AO_
CLKENA
0
0
23
7
22
6
21
5
0
0
0
0
0
0
0
0
0
0
0
0
20
4
19
3
MIF4_RX_BYTE55 [7:0]
MIF4_RX_BYTE53 [7:0]
MIF4_RX_BYTE59 [7:0]
MIF4_RX_BYTE57 [7:0]
MIF4_RX_BYTE63 [7:0]
MIF4_RX_BYTE61 [7:0]
0
0
0
0
0
0
0
0
18
2
17
1
16
0
Default
00000000h
00000000h
00000000h
0
0
0
0
00000000h
EVENTLO EVENTLO
G1_RST G1_ENA
0
0
00000000h
0
0
EVENTLOG1_
TIMER_SEL [1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG1_FIFO_WMARK [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO EVENTLO
G1_FULL
G1_ G1_NOT_
WMARK_ EMPTY
STS
0
0
0
0
EVENTLOG1_FIFO_WPTR [3:0]
0
0
0
0
EVENTLOG1_FIFO_RPTR [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO
G1_CH16_ G1_CH15_ G1_CH14_ G1_CH13_ G1_CH12_ G1_CH11_ G1_CH10_ G1_CH9_ G1_CH8_ G1_CH7_ G1_CH6_ G1_CH5_ G1_CH4_ G1_CH3_ G1_CH2_ G1_CH1_
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH1_SEL [9:0]
G1_CH1_ G1_CH1_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH2_SEL [9:0]
G1_CH2_ G1_CH2_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH3_SEL [9:0]
G1_CH3_ G1_CH3_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH4_SEL [9:0]
G1_CH4_ G1_CH4_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH5_SEL [9:0]
G1_CH5_ G1_CH5_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH6_SEL [9:0]
G1_CH6_ G1_CH6_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH7_SEL [9:0]
G1_CH7_ G1_CH7_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH8_SEL [9:0]
G1_CH8_ G1_CH8_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH9_SEL [9:0]
G1_CH9_ G1_CH9_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH10_SEL [9:0]
G1_CH10_ G1_CH10_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH11_SEL [9:0]
G1_CH11_ G1_CH11_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH12_SEL [9:0]
G1_CH12_ G1_CH12_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH13_SEL [9:0]
G1_CH13_ G1_CH13_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH14_SEL [9:0]
G1_CH14_ G1_CH14_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG1_CH15_SEL [9:0]
G1_CH15_ G1_CH15_
DB
POL
00000001h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
265
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R295006 EVENTLOG1_CH16_
(4805Eh) DEFINE
R295040 EVENTLOG1_FIFO0_
(48080h) READ
31
15
30
14
0
0
EVENTLO EVENTLO
G1_CH16_ G1_CH16_
DB
POL
0
0
0
0
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO0_
POL
0
0
0
0
0
0
0
0
R295042 EVENTLOG1_FIFO0_
(48082h) TIME
R295044 EVENTLOG1_FIFO1_
(48084h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO1_
POL
0
0
0
0
R295046 EVENTLOG1_FIFO1_
(48086h) TIME
R295048 EVENTLOG1_FIFO2_
(48088h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO2_
POL
0
0
0
0
R295050 EVENTLOG1_FIFO2_
(4808Ah) TIME
R295052 EVENTLOG1_FIFO3_
(4808Ch) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO3_
POL
0
0
0
0
R295054 EVENTLOG1_FIFO3_
(4808Eh) TIME
R295056 EVENTLOG1_FIFO4_
(48090h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO4_
POL
0
0
0
0
R295058 EVENTLOG1_FIFO4_
(48092h) TIME
R295060 EVENTLOG1_FIFO5_
(48094h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO5_
POL
0
0
0
0
R295062 EVENTLOG1_FIFO5_
(48096h) TIME
R295064 EVENTLOG1_FIFO6_
(48098h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO6_
POL
0
0
0
0
R295066 EVENTLOG1_FIFO6_
(4809Ah) TIME
R295068 EVENTLOG1_FIFO7_
(4809Ch) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO7_
POL
0
0
0
0
R295070 EVENTLOG1_FIFO7_
(4809Eh) TIME
R295072 EVENTLOG1_FIFO8_
(480A0h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO8_
POL
0
0
0
0
R295074 EVENTLOG1_FIFO8_
(480A2h) TIME
R295076 EVENTLOG1_FIFO9_
(480A4h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO9_
POL
0
0
0
0
R295078 EVENTLOG1_FIFO9_
(480A6h) TIME
R295080 EVENTLOG1_FIFO10_
(480A8h) READ
R295082 EVENTLOG1_FIFO10_
(480AAh) TIME
266
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO10_
POL
0
0
0
0
EVENTLOG1_FIFO0_TIME [31:16]
EVENTLOG1_FIFO0_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO1_TIME [31:16]
EVENTLOG1_FIFO1_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO2_TIME [31:16]
EVENTLOG1_FIFO2_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO3_TIME [31:16]
EVENTLOG1_FIFO3_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO4_TIME [31:16]
EVENTLOG1_FIFO4_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO5_TIME [31:16]
EVENTLOG1_FIFO5_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO6_TIME [31:16]
EVENTLOG1_FIFO6_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO7_TIME [31:16]
EVENTLOG1_FIFO7_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO8_TIME [31:16]
EVENTLOG1_FIFO8_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO9_TIME [31:16]
EVENTLOG1_FIFO9_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO10_TIME [31:16]
EVENTLOG1_FIFO10_TIME [15:0]
21
5
20
4
19
3
18
2
17
1
16
0
Default
0
0
0
EVENTLOG1_CH16_SEL [9:0]
0
0
0
00000000h
0
0
0
EVENTLOG1_FIFO0_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO1_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO2_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO3_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO4_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO5_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO6_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO7_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO8_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO9_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO10_ID [9:0]
0
0
0
00000000h
00000000h
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R295084 EVENTLOG1_FIFO11_
(480ACh) READ
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO11_
POL
0
0
0
0
0
0
0
0
R295086 EVENTLOG1_FIFO11_
(480AEh) TIME
R295088 EVENTLOG1_FIFO12_
(480B0h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO12_
POL
0
0
0
0
R295090 EVENTLOG1_FIFO12_
(480B2h) TIME
R295092 EVENTLOG1_FIFO13_
(480B4h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO13_
POL
0
0
0
0
R295094 EVENTLOG1_FIFO13_
(480B6h) TIME
R295096 EVENTLOG1_FIFO14_
(480B8h) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO14_
POL
0
0
0
0
R295098 EVENTLOG1_FIFO14_
(480BAh) TIME
R295100 EVENTLOG1_FIFO15_
(480BCh) READ
0
0
0
0
0
0
0
EVENTLO
G1_
FIFO15_
POL
0
0
0
0
R295102 EVENTLOG1_FIFO15_
(480BEh) TIME
R295424 EVENTLOG2_
(48200h) CONTROL
0
0
0
0
0
0
0
0
0
0
0
0
R295428 EVENTLOG2_TIMER_
(48204h) SEL
0
0
0
0
0
0
0
0
0
0
0
0
R295436 EVENTLOG2_FIFO_
(4820Ch) CONTROL1
R295438 EVENTLOG2_FIFO_
(4820Eh) POINTER1
R295456 EVENTLOG2_CH_
(48220h) ENABLE1
R295488 EVENTLOG2_CH1_
(48240h) DEFINE
R295490 EVENTLOG2_CH2_
(48242h) DEFINE
R295492 EVENTLOG2_CH3_
(48244h) DEFINE
R295494 EVENTLOG2_CH4_
(48246h) DEFINE
R295496 EVENTLOG2_CH5_
(48248h) DEFINE
R295498 EVENTLOG2_CH6_
(4824Ah) DEFINE
R295500 EVENTLOG2_CH7_
(4824Ch) DEFINE
DS1137PP1
EVENTLOG1_FIFO11_TIME [31:16]
EVENTLOG1_FIFO11_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO12_TIME [31:16]
EVENTLOG1_FIFO12_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO13_TIME [31:16]
EVENTLOG1_FIFO13_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO14_TIME [31:16]
EVENTLOG1_FIFO14_TIME [15:0]
0
0
0
0
EVENTLOG1_FIFO15_TIME [31:16]
EVENTLOG1_FIFO15_TIME [15:0]
0
0
0
0
0
EVENTLO
0
0
G2_FLL_
AO_
CLKENA
0
0
0
0
0
0
0
0
21
5
20
4
19
3
0
0
0
EVENTLOG1_FIFO11_ID [9:0]
18
2
17
1
16
0
Default
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO12_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO13_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO14_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG1_FIFO15_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
0
0
0
0
0
0
0
00000000h
EVENTLO EVENTLO
G2_RST G2_ENA
0
0
0
0
0
0
0
0
00000000h
0
0
EVENTLOG2_
TIMER_SEL [1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_FIFO_WMARK [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO EVENTLO
G2_FULL
G2_ G2_NOT_
WMARK_ EMPTY
STS
0
0
0
0
EVENTLOG2_FIFO_WPTR [3:0]
0
0
0
0
EVENTLOG2_FIFO_RPTR [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO EVENTLO
G2_CH16_ G2_CH15_ G2_CH14_ G2_CH13_ G2_CH12_ G2_CH11_ G2_CH10_ G2_CH9_ G2_CH8_ G2_CH7_ G2_CH6_ G2_CH5_ G2_CH4_ G2_CH3_ G2_CH2_ G2_CH1_
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH1_SEL [9:0]
G2_CH1_ G2_CH1_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH2_SEL [9:0]
G2_CH2_ G2_CH2_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH3_SEL [9:0]
G2_CH3_ G2_CH3_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH4_SEL [9:0]
G2_CH4_ G2_CH4_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH5_SEL [9:0]
G2_CH5_ G2_CH5_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH6_SEL [9:0]
G2_CH6_ G2_CH6_
DB
POL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLO EVENTLO
0
0
0
0
EVENTLOG2_CH7_SEL [9:0]
G2_CH7_ G2_CH7_
DB
POL
00000001h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
267
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R295502 EVENTLOG2_CH8_
(4824Eh) DEFINE
R295504 EVENTLOG2_CH9_
(48250h) DEFINE
R295506 EVENTLOG2_CH10_
(48252h) DEFINE
R295508 EVENTLOG2_CH11_
(48254h) DEFINE
R295510 EVENTLOG2_CH12_
(48256h) DEFINE
R295512 EVENTLOG2_CH13_
(48258h) DEFINE
R295514 EVENTLOG2_CH14_
(4825Ah) DEFINE
R295516 EVENTLOG2_CH15_
(4825Ch) DEFINE
R295518 EVENTLOG2_CH16_
(4825Eh) DEFINE
R295552 EVENTLOG2_FIFO0_
(48280h) READ
31
15
30
14
0
0
EVENTLO EVENTLO
G2_CH8_ G2_CH8_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH9_ G2_CH9_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH10_ G2_CH10_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH11_ G2_CH11_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH12_ G2_CH12_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH13_ G2_CH13_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH14_ G2_CH14_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH15_ G2_CH15_
DB
POL
0
0
EVENTLO EVENTLO
G2_CH16_ G2_CH16_
DB
POL
0
0
0
0
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
2
17
1
16
0
Default
0
0
0
EVENTLOG2_CH8_SEL [9:0]
0
0
0
00000000h
0
0
0
0
EVENTLOG2_CH9_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
EVENTLOG2_CH10_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
EVENTLOG2_CH11_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
0
EVENTLOG2_CH12_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
0
0
0
EVENTLOG2_CH13_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_CH14_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_CH15_SEL [9:0]
0
0
0
00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_CH16_SEL [9:0]
0
0
0
00000000h
0
0
0
EVENTLO
G2_
FIFO0_
POL
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_FIFO0_ID [9:0]
0
0
0
00000000h
R295554 EVENTLOG2_FIFO0_
(48282h) TIME
R295556 EVENTLOG2_FIFO1_
(48284h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO1_
POL
0
0
0
0
R295558 EVENTLOG2_FIFO1_
(48286h) TIME
R295560 EVENTLOG2_FIFO2_
(48288h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO2_
POL
0
0
0
0
R295562 EVENTLOG2_FIFO2_
(4828Ah) TIME
R295564 EVENTLOG2_FIFO3_
(4828Ch) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO3_
POL
0
0
0
0
R295566 EVENTLOG2_FIFO3_
(4828Eh) TIME
R295568 EVENTLOG2_FIFO4_
(48290h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO4_
POL
0
0
0
0
R295570 EVENTLOG2_FIFO4_
(48292h) TIME
R295572 EVENTLOG2_FIFO5_
(48294h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO5_
POL
0
0
0
0
R295574 EVENTLOG2_FIFO5_
(48296h) TIME
R295576 EVENTLOG2_FIFO6_
(48298h) READ
R295578 EVENTLOG2_FIFO6_
(4829Ah) TIME
268
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO6_
POL
0
0
0
0
EVENTLOG2_FIFO0_TIME [31:16]
EVENTLOG2_FIFO0_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO1_TIME [31:16]
EVENTLOG2_FIFO1_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO2_TIME [31:16]
EVENTLOG2_FIFO2_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO3_TIME [31:16]
EVENTLOG2_FIFO3_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO4_TIME [31:16]
EVENTLOG2_FIFO4_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO5_TIME [31:16]
EVENTLOG2_FIFO5_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO6_TIME [31:16]
EVENTLOG2_FIFO6_TIME [15:0]
21
5
20
4
19
3
00000000h
0
0
0
EVENTLOG2_FIFO1_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO2_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO3_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO4_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO5_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO6_ID [9:0]
0
0
0
00000000h
00000000h
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R295580 EVENTLOG2_FIFO7_
(4829Ch) READ
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO7_
POL
0
0
0
0
0
0
0
0
R295582 EVENTLOG2_FIFO7_
(4829Eh) TIME
R295584 EVENTLOG2_FIFO8_
(482A0h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO8_
POL
0
0
0
0
R295586 EVENTLOG2_FIFO8_
(482A2h) TIME
R295588 EVENTLOG2_FIFO9_
(482A4h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO9_
POL
0
0
0
0
R295590 EVENTLOG2_FIFO9_
(482A6h) TIME
R295592 EVENTLOG2_FIFO10_
(482A8h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO10_
POL
0
0
0
0
R295594 EVENTLOG2_FIFO10_
(482AAh) TIME
R295596 EVENTLOG2_FIFO11_
(482ACh) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO11_
POL
0
0
0
0
R295598 EVENTLOG2_FIFO11_
(482AEh) TIME
R295600 EVENTLOG2_FIFO12_
(482B0h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO12_
POL
0
0
0
0
R295602 EVENTLOG2_FIFO12_
(482B2h) TIME
R295604 EVENTLOG2_FIFO13_
(482B4h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO13_
POL
0
0
0
0
R295606 EVENTLOG2_FIFO13_
(482B6h) TIME
R295608 EVENTLOG2_FIFO14_
(482B8h) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO14_
POL
0
0
0
0
R295610 EVENTLOG2_FIFO14_
(482BAh) TIME
R295612 EVENTLOG2_FIFO15_
(482BCh) READ
0
0
0
0
0
0
0
EVENTLO
G2_
FIFO15_
POL
0
0
0
0
R295614 EVENTLOG2_FIFO15_
(482BEh) TIME
R311296 Timer1_Control
(4C000h)
0
0
0
0
0
TIMER1_REFCLK_DIV [2:0]
0
0
R311298 Timer1_Count_Preset
(4C002h)
R311302 Timer1_Start_and_Stop
(4C006h)
0
0
0
0
0
0
0
0
0
0
R311304 Timer1_Status
(4C008h)
0
0
0
0
0
0
0
0
0
0
0
EVENTLOG2_FIFO13_TIME [31:16]
EVENTLOG2_FIFO13_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO14_TIME [31:16]
EVENTLOG2_FIFO14_TIME [15:0]
0
0
0
0
0
0
0
0
0
EVENTLOG2_FIFO9_ID [9:0]
R311308 Timer1_DSP_Clock_
(4C00Ch) Config
0
0
0
0
0
0
R311310 Timer1_DSP_Clock_
(4C00Eh) Status
0
0
0
0
0
0
0
0
0
0
17
1
16
0
Default
0
0
0
00000000h
0
0
0
00000000h
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO10_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO11_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO12_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO13_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO14_ID [9:0]
0
0
0
00000000h
00000000h
0
0
0
EVENTLOG2_FIFO15_ID [9:0]
EVENTLOG2_FIFO15_TIME [31:16]
EVENTLOG2_FIFO15_TIME [15:0]
0
0
0
0
0
0
18
2
00000000h
TIMER1_REFCLK_FREQ_SEL
0
0
[2:0]
TIMER1_MAX_COUNT [31:16]
TIMER1_MAX_COUNT [15:0]
0
0
0
0
0
0
0
0
0
0
R311306 Timer1_Count_
(4C00Ah) Readback
DS1137PP1
0
0
0
EVENTLOG2_FIFO8_ID [9:0]
EVENTLOG2_FIFO10_TIME [31:16]
EVENTLOG2_FIFO10_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO12_TIME [31:16]
EVENTLOG2_FIFO12_TIME [15:0]
0
0
0
0
19
3
00000000h
EVENTLOG2_FIFO8_TIME [31:16]
EVENTLOG2_FIFO8_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO11_TIME [31:16]
EVENTLOG2_FIFO11_TIME [15:0]
0
0
0
0
20
4
0
0
0
EVENTLOG2_FIFO7_ID [9:0]
EVENTLOG2_FIFO7_TIME [31:16]
EVENTLOG2_FIFO7_TIME [15:0]
0
0
0
0
EVENTLOG2_FIFO9_TIME [31:16]
EVENTLOG2_FIFO9_TIME [15:0]
0
0
0
0
21
5
0
0
TIMER1_CUR_COUNT [31:16]
TIMER1_CUR_COUNT [15:0]
0
0
0
0
TIMER1_DSPCLK_FREQ_SEL [15:0]
0
0
0
0
TIMER1_DSPCLK_FREQ_STS [15:0]
0
0
0
00000000h
00000000h
TIMER1_ TIMER1_
CONTINU
DIR
OUS
0
0
0
TIMER1_PRESCALE [2:0]
00000000h
TIMER1_REFCLK_SRC [3:0]
00000000h
0
0
0
0
0
TIMER1_
STOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000h
TIMER1_
START
0
00000000h
TIMER1_
RUNNING
_STS
00000000h
0
0
0
0
0
0
00000000h
0
0
0
0
0
0
00000000h
269
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R311424 Timer2_Control
(4C080h)
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
0
0
0
0
0
0
0
0
0
0
0
TIMER2_REFCLK_DIV [2:0]
0
R311426 Timer2_Count_Preset
(4C082h)
R311430 Timer2_Start_and_Stop
(4C086h)
0
0
0
0
0
0
0
0
0
0
R311432 Timer2_Status
(4C088h)
0
0
0
0
0
0
0
0
0
0
TIMER2_REFCLK_FREQ_SEL
0
0
[2:0]
TIMER2_MAX_COUNT [31:16]
TIMER2_MAX_COUNT [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
R311434 Timer2_Count_
(4C08Ah) Readback
R311436 Timer2_DSP_Clock_
(4C08Ch) Config
0
0
0
0
0
0
R311438 Timer2_DSP_Clock_
(4C08Eh) Status
0
0
0
0
0
0
R315392 DSPGP_Status_1
(4D000h)
0
0
R315424 DSPGP_SET1_Mask_1
(4D020h)
0
0
R315432 DSPGP_SET1_
(4D028h) Direction_1
0
0
R315440 DSPGP_SET1_Level_1
(4D030h)
0
0
R315456 DSPGP_SET2_Mask_1
(4D040h)
0
0
R315464 DSPGP_SET2_
(4D048h) Direction_1
0
0
R315472 DSPGP_SET2_Level_1
(4D050h)
0
0
R315488 DSPGP_SET3_Mask_1
(4D060h)
0
0
R315496 DSPGP_SET3_
(4D068h) Direction_1
0
0
R315504 DSPGP_SET3_Level_1
(4D070h)
0
0
R315520 DSPGP_SET4_Mask_1
(4D080h)
0
0
R315528 DSPGP_SET4_
(4D088h) Direction_1
0
0
R315536 DSPGP_SET4_Level_1
(4D090h)
0
0
R328704 RA_EVENTLOG_
(50400h) Thread_Ctrl_1
0
0
0
DSPGP15
_STS
0
DSPGP15
_SET1_
MASK
0
DSPGP15
_SET1_
DIR
0
DSPGP15
_SET1_
LVL
0
DSPGP15
_SET2_
MASK
0
DSPGP15
_SET2_
DIR
0
DSPGP15
_SET2_
LVL
0
DSPGP15
_SET3_
MASK
0
DSPGP15
_SET3_
DIR
0
DSPGP15
_SET3_
LVL
0
DSPGP15
_SET4_
MASK
0
DSPGP15
_SET4_
DIR
0
DSPGP15
_SET4_
LVL
0
0
0
DSPGP14
_STS
0
DSPGP14
_SET1_
MASK
0
DSPGP14
_SET1_
DIR
0
DSPGP14
_SET1_
LVL
0
DSPGP14
_SET2_
MASK
0
DSPGP14
_SET2_
DIR
0
DSPGP14
_SET2_
LVL
0
DSPGP14
_SET3_
MASK
0
DSPGP14
_SET3_
DIR
0
DSPGP14
_SET3_
LVL
0
DSPGP14
_SET4_
MASK
0
DSPGP14
_SET4_
DIR
0
DSPGP14
_SET4_
LVL
0
0
0
DSPGP13
_STS
0
DSPGP13
_SET1_
MASK
0
DSPGP13
_SET1_
DIR
0
DSPGP13
_SET1_
LVL
0
DSPGP13
_SET2_
MASK
0
DSPGP13
_SET2_
DIR
0
DSPGP13
_SET2_
LVL
0
DSPGP13
_SET3_
MASK
0
DSPGP13
_SET3_
DIR
0
DSPGP13
_SET3_
LVL
0
DSPGP13
_SET4_
MASK
0
DSPGP13
_SET4_
DIR
0
DSPGP13
_SET4_
LVL
0
0
0
DSPGP12
_STS
0
DSPGP12
_SET1_
MASK
0
DSPGP12
_SET1_
DIR
0
DSPGP12
_SET1_
LVL
0
DSPGP12
_SET2_
MASK
0
DSPGP12
_SET2_
DIR
0
DSPGP12
_SET2_
LVL
0
DSPGP12
_SET3_
MASK
0
DSPGP12
_SET3_
DIR
0
DSPGP12
_SET3_
LVL
0
DSPGP12
_SET4_
MASK
0
DSPGP12
_SET4_
DIR
0
DSPGP12
_SET4_
LVL
0
0
0
DSPGP11
_STS
0
DSPGP11
_SET1_
MASK
0
DSPGP11
_SET1_
DIR
0
DSPGP11
_SET1_
LVL
0
DSPGP11
_SET2_
MASK
0
DSPGP11
_SET2_
DIR
0
DSPGP11
_SET2_
LVL
0
DSPGP11
_SET3_
MASK
0
DSPGP11
_SET3_
DIR
0
DSPGP11
_SET3_
LVL
0
DSPGP11
_SET4_
MASK
0
DSPGP11
_SET4_
DIR
0
DSPGP11
_SET4_
LVL
0
0
R328708 RA_EVENTLOG_
(50404h) Thread_Ctrl_2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R328712 RA_EVENTLOG_
(50408h) Thread_Ctrl_3
R328720 RA_EVENTLOG1_
(50410h) Thread_Ctrl_1
270
0
0
0
0
0
0
RA_
RA_
EVENTLO EVENTLO
G1_IN_
G1_
USE_STS SHARE
0
0
0
0
0
0
0
0
21
5
20
4
TIMER2_ TIMER2_
CONTINU
DIR
OUS
0
0
19
3
18
2
17
1
16
0
0
TIMER2_PRESCALE [2:0]
Default
00000000h
TIMER2_REFCLK_SRC [3:0]
00000000h
0
0
0
0
0
TIMER2_
STOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000h
TIMER2_
START
0
00000000h
TIMER2_
RUNNING
_STS
TIMER2_CUR_COUNT [31:16]
TIMER2_CUR_COUNT [15:0]
0
0
0
0
0
0
0
0
0
0
TIMER2_DSPCLK_FREQ_SEL [15:0]
0
0
0
0
0
0
0
0
0
0
TIMER2_DSPCLK_FREQ_STS [15:0]
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_STS
STS
STS
STS
STS
STS
STS
STS
STS
STS
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET1_ SET1_
SET1_
SET1_
SET1_
SET1_
SET1_
SET1_
SET1_
SET1_
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET1_ SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR SET1_DIR
DIR
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET1_ SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL SET1_LVL
LVL
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET2_ SET2_
SET2_
SET2_
SET2_
SET2_
SET2_
SET2_
SET2_
SET2_
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET2_ SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR SET2_DIR
DIR
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET2_ SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL SET2_LVL
LVL
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET3_ SET3_
SET3_
SET3_
SET3_
SET3_
SET3_
SET3_
SET3_
SET3_
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET3_ SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR SET3_DIR
DIR
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET3_ SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL SET3_LVL
LVL
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET4_ SET4_
SET4_
SET4_
SET4_
SET4_
SET4_
SET4_
SET4_
SET4_
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
MASK
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET4_ SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR SET4_DIR
DIR
0
0
0
0
0
0
0
0
0
0
DSPGP10 DSPGP9_ DSPGP8_ DSPGP7_ DSPGP6_ DSPGP5_ DSPGP4_ DSPGP3_ DSPGP2_ DSPGP1_
_SET4_ SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL SET4_LVL
LVL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG_STS
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG_
SHARE_STS [1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG_NUM [5:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG1_OWNER [4:0]
00000000h
00000000h
00000000h
00000000h
00007FFFh
00007FFFh
00000000h
00007FFFh
00007FFFh
00000000h
00007FFFh
00007FFFh
00000000h
00007FFFh
00007FFFh
00000000h
00000003h
00000000h
00000002h
00000000h
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
R328722 RA_EVENTLOG1_
(50412h) Thread_Ctrl_2
R328724 RA_EVENTLOG1_
(50414h) Thread_Ctrl_3
31
15
30
14
29
13
28
12
27
11
26
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R328728 RA_EVENTLOG1_
(50418h) Thread_Ctrl_Debug_1
R328736 RA_EVENTLOG2_
(50420h) Thread_Ctrl_1
R328738 RA_EVENTLOG2_
(50422h) Thread_Ctrl_2
0
0
RA_
RA_
EVENTLO EVENTLO
G2_IN_
G2_
USE_STS SHARE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R328744 RA_EVENTLOG2_
(50428h) Thread_Ctrl_Debug_1
R329728 RA_TIMER_Thread_
(50800h) Ctrl_1
R329732 RA_TIMER_Thread_
(50804h) Ctrl_2
R329736 RA_TIMER_Thread_
(50808h) Ctrl_3
R329744 RA_TIMER1_Thread_
(50810h) Ctrl_1
R329746 RA_TIMER1_Thread_
(50812h) Ctrl_2
R329748 RA_TIMER1_Thread_
(50814h) Ctrl_3
R329750 RA_TIMER1_Thread_
(50816h) Ctrl_4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_
RA_
TIMER1_ TIMER1_
IN_USE_ SHARE
STS
0
0
0
0
0
0
0
0
0
0
0
0
R329762 RA_TIMER2_Thread_
(50822h) Ctrl_2
R329764 RA_TIMER2_Thread_
(50824h) Ctrl_3
R329766 RA_TIMER2_Thread_
(50826h) Ctrl_4
0
0
RA_
RA_
TIMER2_ TIMER2_
IN_USE_ SHARE
STS
0
0
0
0
0
0
0
0
0
0
0
0
R330756 RA_DSPGP_SET_
(50C04h) Thread_Ctrl_2
R330760 RA_DSPGP_SET_
(50C08h) Thread_Ctrl_3
R330768 RA_DSPGP_SET1_
(50C10h) Thread_Ctrl_1
R330770 RA_DSPGP_SET1_
(50C12h) Thread_Ctrl_2
R330772 RA_DSPGP_SET1_
(50C14h) Thread_Ctrl_3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_
RA_
DSPGP_ DSPGP_
SET1_IN_ SET1_
USE_STS SHARE
0
0
0
0
0
0
0
0
R330786 RA_DSPGP_SET2_
(50C22h) Thread_Ctrl_2
R330788 RA_DSPGP_SET2_
(50C24h) Thread_Ctrl_3
DS1137PP1
0
0
RA_
RA_
DSPGP_ DSPGP_
SET2_IN_ SET2_
USE_STS SHARE
0
0
0
0
0
0
0
0
22
6
21
5
20
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG1_IN_USE_DBG0 [31:16]
RA_EVENTLOG1_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG2_OWNER [4:0]
0
00000000h
0
0
0
0
0
0
0
0
RA_EVENTLOG2_IN_USE_DBG0 [31:16]
RA_EVENTLOG2_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_EVENTLOG2_IN_USE_SET [4:0]
0
00000000h
0
19
3
18
2
17
1
0
0
0
RA_EVENTLOG1_IN_USE_SET [4:0]
0
0
0
RA_EVENTLOG1_IN_USE_CLR [4:0]
16
0
Default
0
00000000h
0
00000000h
00000000h
00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_TIMER2_OWNER [4:0]
0
00000000h
0
0
0
0
0
0
0
0
0
0
RA_TIMER2_IN_USE_SET [4:0]
0
0
0
RA_TIMER2_IN_USE_CLR [4:0]
0
0
0
0
0
0
0
00000000h
0
00000000h
0
0
0
0
0
0
0
0
RA_TIMER1_IN_USE_DBG0 [31:16]
RA_TIMER1_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_TIMER2_IN_USE_DBG0 [31:16]
RA_TIMER2_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_DSPGP_SET1_IN_USE_DBG0 [31:16]
RA_DSPGP_SET1_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000003h
RA_TIMER_STS [1:0]
0
0
00000000h
RA_TIMER_SHARE_
STS [1:0]
0
0
00000002h
0
0
0
0
R330776 RA_DSPGP_SET1_
(50C18h) Thread_Ctrl_Debug_1
R330784 RA_DSPGP_SET2_
(50C20h) Thread_Ctrl_1
23
7
0
0
0
0
R329768 RA_TIMER2_Thread_
(50828h) Ctrl_Debug_1
R330752 RA_DSPGP_SET_
(50C00h) Thread_Ctrl_1
24
8
0
0
0
0
R329752 RA_TIMER1_Thread_
(50818h) Ctrl_Debug_1
R329760 RA_TIMER2_Thread_
(50820h) Ctrl_1
25
9
0
0
RA_TIMER_NUM [5:0]
0
0
0
RA_TIMER1_OWNER [4:0]
0
0
0
RA_TIMER1_IN_USE_SET [4:0]
0
0
0
RA_TIMER1_IN_USE_CLR [4:0]
0
0
0
0
0
0
0
00000000h
0
00000000h
0
00000000h
0
00000001h
RA_
TIMER1_
CAP_EVT
00000000h
0
0
0
0
00000001h
RA_
TIMER2_
CAP_EVT
00000000h
0
000000FFh
0
00000000h
0
00000008h
0
00000000h
0
0
0
0
RA_DSPGP_SET1_IN_USE_SET [4:0]
0
0
0
0
0
RA_DSPGP_SET1_IN_USE_CLR [4:0]
00000000h
0
0
0
0
0
RA_DSPGP_SET_STS [7:0]
0
0
0
0
0
RA_DSPGP_SET_SHARE_STS [7:0]
0
0
0
0
0
RA_DSPGP_SET_NUM [5:0]
0
0
0
0
0
0
RA_DSPGP_SET1_OWNER [4:0]
0
0
0
0
0
00000000h
00000000h
0
00000000h
0
0
0
0
RA_DSPGP_SET2_IN_USE_SET [4:0]
0
0
0
0
0
RA_DSPGP_SET2_IN_USE_CLR [4:0]
00000000h
0
0
0
0
0
0
0
0
0
0
0
RA_DSPGP_SET2_OWNER [4:0]
00000000h
271
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
31
15
30
14
29
13
28
12
27
11
26
10
R330792 RA_DSPGP_SET2_
(50C28h) Thread_Ctrl_Debug_1
R330800 RA_DSPGP_SET3_
(50C30h) Thread_Ctrl_1
R330802 RA_DSPGP_SET3_
(50C32h) Thread_Ctrl_2
0
0
RA_
RA_
DSPGP_ DSPGP_
SET3_IN_ SET3_
USE_STS SHARE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R330808 RA_DSPGP_SET3_
(50C38h) Thread_Ctrl_Debug_1
R330816 RA_DSPGP_SET4_
(50C40h) Thread_Ctrl_1
R330818 RA_DSPGP_SET4_
(50C42h) Thread_Ctrl_2
R330820 RA_DSPGP_SET4_
(50C44h) Thread_Ctrl_3
0
0
RA_
RA_
DSPGP_ DSPGP_
SET4_IN_ SET4_
USE_STS SHARE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R330824 RA_DSPGP_SET4_
(50C48h) Thread_Ctrl_Debug_1
25
9
24
8
23
7
RA_DSPGP_SET2_IN_USE_DBG0 [31:16]
RA_DSPGP_SET2_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_DSPGP_SET4_IN_USE_DBG0 [31:16]
RA_DSPGP_SET4_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R333956 RA_MIF4_Thread_Ctrl_
(51884h) 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R333970 RA_MIF41_Thread_
(51892h) Ctrl_2
R333972 RA_MIF41_Thread_
(51894h) Ctrl_3
R333976 RA_MIF41_Thread_
(51898h) Ctrl_Debug_1
R524288 DSP1_PMEM_0
(80000h)
R524290 DSP1_PMEM_1
(80002h)
0
0
0
0
0
0
0
0
0
0
0
0
R524292 DSP1_PMEM_2
(80004h)
R561146 DSP1_PMEM_18429
(88FFAh)
R561148 DSP1_PMEM_18430
(88FFCh)
0
0
0
0
0
0
0
0
0
0
0
0
R561150 DSP1_PMEM_18431
(88FFEh)
R610304 DSP1_PMEM_ROM_0
(95000h)
R610306 DSP1_PMEM_ROM_1
(95002h)
0
0
0
0
0
0
0
0
0
0
0
0
R610308 DSP1_PMEM_ROM_2
(95004h)
R613370 DSP1_PMEM_ROM_
(95BFAh) 1533
R613372 DSP1_PMEM_ROM_
(95BFCh) 1534
0
0
0
0
0
0
0
0
0
0
0
0
R613374 DSP1_PMEM_ROM_
(95BFEh) 1535
R655360 DSP1_XMEM_0
(A0000h)
0
0
0
0
0
0
R655362 DSP1_XMEM_1
(A0002h)
0
0
0
0
0
0
R696316 DSP1_XMEM_20478
(A9FFCh)
0
0
0
0
0
0
R696318 DSP1_XMEM_20479
(A9FFEh)
0
0
0
0
0
0
R786432 DSP1_YMEM_0
(C0000h)
0
0
0
0
0
0
272
19
3
18
2
17
1
16
0
Default
00000000h
0
0
0
0
0
0
0
0
RA_DSPGP_SET3_IN_USE_DBG0 [31:16]
RA_DSPGP_SET3_IN_USE_DBG0 [15:0]
0
0
0
0
0
0
0
0
0
0
R333968 RA_MIF41_Thread_
(51890h) Ctrl_1
20
4
0
0
0
0
0
0
0
0
0
RA_
RA_
MIF41_IN_ MIF41_
USE_STS SHARE
0
0
0
0
0
0
0
0
21
5
0
0
R333952 RA_MIF4_Thread_Ctrl_
(51880h) 1
R333960 RA_MIF4_Thread_Ctrl_
(51888h) 3
22
6
0
00000000h
0
0
0
0
RA_DSPGP_SET3_IN_USE_SET [4:0]
00000000h
0
0
0
RA_DSPGP_SET3_OWNER [4:0]
00000000h
0
00000000h
0
0
0
0
RA_DSPGP_SET4_IN_USE_SET [4:0]
0
0
0
0
0
RA_DSPGP_SET4_IN_USE_CLR [4:0]
00000000h
0
0
0
RA_DSPGP_SET4_OWNER [4:0]
00000000h
00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA_MIF41_IN_USE_DBG0 [31:16]
RA_MIF41_IN_USE_DBG0 [15:0]
0
0
DSP1_PM_START [31:16]
DSP1_PM_START [15:0]
0
0
DSP1_PM_1 [31:16]
DSP1_PM_1 [15:0]
0
0
DSP1_PM_12286 [31:16]
DSP1_PM_12286 [15:0]
0
0
DSP1_PM_END [31:16]
DSP1_PM_END [15:0]
0
0
DSP1_PM_ROM_START [31:16]
DSP1_PM_ROM_START [15:0]
0
0
DSP1_PM_ROM_1 [31:16]
DSP1_PM_ROM_1 [15:0]
0
0
DSP1_PM_ROM_1022 [31:16]
DSP1_PM_ROM_1022 [15:0]
0
0
DSP1_PM_ROM_END [31:16]
DSP1_PM_ROM_END [15:0]
0
0
DSP1_XM_START [15:0]
0
0
DSP1_XM_1 [15:0]
0
0
DSP1_XM_20478 [15:0]
0
0
DSP1_XM_END [15:0]
0
0
DSP1_YM_START [15:0]
0
0
0
0
0
0
0
0
0
RA_MIF4_NUM [5:0]
0
0
0
RA_MIF41_OWNER [4:0]
0
0
0
RA_MIF41_IN_USE_SET [4:0]
0
0
0
RA_MIF41_IN_USE_CLR [4:0]
0
00000001h
RA_MIF4_
STS
0
00000000h
RA_MIF4_
SHARE_
STS
0
00000001h
0
00000000h
0
00000000h
0
00000000h
00000000h
DSP1_PM_START [39:32]
00000000h
00000000h
DSP1_PM_1 [39:32]
00000000h
DSP1_PM_12286 [39:32]
00000000h
00000000h
DSP1_PM_END [39:32]
00000000h
DSP1_PM_ROM_START [39:32]
00000000h
00000000h
DSP1_PM_ROM_1 [39:32]
00000000h
DSP1_PM_ROM_1022 [39:32]
00000000h
00000000h
DSP1_PM_ROM_END [39:32]
00000000h
DSP1_XM_START [23:16]
00000000h
DSP1_XM_1 [23:16]
00000000h
DSP1_XM_20478 [23:16]
00000000h
DSP1_XM_END [23:16]
00000000h
DSP1_YM_START [23:16]
00000000h
DS1137PP1
CS47L15
6 Register Map
Table 6-2. Register Map Definition—32-bit region (Cont.)
31
15
30
14
29
13
28
12
27
11
26
10
25
9
R786434 DSP1_YMEM_1
(C0002h)
0
0
0
0
0
0
0
R794620 DSP1_YMEM_4094
(C1FFCh)
0
0
0
0
0
0
0
R794622 DSP1_YMEM_4095
(C1FFEh)
0
0
0
0
0
0
0
R917504 DSP1_ZMEM_0
(E0000h)
0
0
0
0
0
0
0
R917506 DSP1_ZMEM_1
(E0002h)
0
0
0
0
0
0
0
R925692 DSP1_ZMEM_4094
(E1FFCh)
0
0
0
0
0
0
0
R925694 DSP1_ZMEM_4095
(E1FFEh)
0
0
0
0
0
0
0
R1048064 DSP1_Config_1
(FFE00h)
0
0
0
0
0
0
0
0
0
0
Register
Name
0
DSP1_RATE [3:0]
24
8
23
7
0
DSP1_YM_1 [15:0]
0
DSP1_YM_4094 [15:0]
0
DSP1_YM_END [15:0]
0
DSP1_ZM_START [15:0]
0
DSP1_ZM_1 [15:0]
0
DSP1_ZM_4094 [15:0]
0
DSP1_ZM_END [15:0]
DSP1_
0
FLL_AO_
CLKENA
0
0
22
6
0
0
0
0
0
R1048066 DSP1_Config_2
(FFE02h)
0
0
0
0
0
0
R1048068 DSP1_Status_1
(FFE04h)
DSP1_
PING_
FULL
0
0
0
DSP1_
PONG_
FULL
0
0
0
0
0
0
0
0
0
0
DSP1_CLK_FREQ_SEL [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1048072 DSP1_Status_3
(FFE08h)
0
0
0
0
0
0
0
R1048074 DSP1_Watchdog_1
(FFE0Ah)
0
0
0
0
0
0
0
0
0
0
0
0
R1048070 DSP1_Status_2
(FFE06h)
R1048080 DSP1_WDMA_Buffer_1
(FFE10h)
R1048082 DSP1_WDMA_Buffer_2
(FFE12h)
R1048084 DSP1_WDMA_Buffer_3
(FFE14h)
R1048086 DSP1_WDMA_Buffer_4
(FFE16h)
R1048096 DSP1_RDMA_Buffer_1
(FFE20h)
R1048098 DSP1_RDMA_Buffer_2
(FFE22h)
R1048100 DSP1_RDMA_Buffer_3
(FFE24h)
R1048112 DSP1_DMA_Config_1
(FFE30h)
0
0
0
0
0
0
0
0
0
0
0
0
R1048118 DSP1_DMA_Config_4
(FFE36h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1048120 DSP1_External_Start
(FFE38h)
0
0
0
0
0
0
0
0
0
0
0
0
R1048114 DSP1_DMA_Config_2
(FFE32h)
R1048116 DSP1_DMA_Config_3
(FFE34h)
0
0
0
0
0
0
18
2
17
1
DSP1_YM_4094 [23:16]
00000000h
DSP1_YM_END [23:16]
00000000h
DSP1_ZM_START [23:16]
00000000h
DSP1_ZM_1 [23:16]
00000000h
DSP1_ZM_4094 [23:16]
00000000h
DSP1_ZM_END [23:16]
00000000h
0
0
DSP1_
DSP1_
MEM_ENA DBG_
CLK_ENA
0
0
0
0
0
0
DSP1_
CORE_
ENA
0
DSP1_
START
0
0
0
0
0
0
0
DSP1_CLK_FREQ_STS [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP1_WDT_MAX_COUNT [3:0]
DSP1_START_ADDRESS_WDMA_BUFFER_1 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_0 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_3 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_2 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_5 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_4 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_7 [15:0]
DSP1_START_ADDRESS_WDMA_BUFFER_6 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_1 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_0 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_3 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_2 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_5 [15:0]
DSP1_START_ADDRESS_RDMA_BUFFER_4 [15:0]
0
0
DSP1_WDMA_CHANNEL_ENABLE [7:0]
DSP1_DMA_BUFFER_LENGTH [13:0]
0
0
0
0
0
0
0
0
0
0
0
DSP1_WDMA_CHANNEL_OFFSET [7:0]
0
0
0
0
DSP1_RDMA_CHANNEL_OFFSET [5:0]
0
0
0
0
DSP1_RDMA_CHANNEL_ENABLE [5:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1048148 DSP1_Ext_window_A
(FFE54h)
DSP1_
EXT_A_
PSIZE16
0
0
0
0
0
R1048150 DSP1_Ext_window_B
(FFE56h)
DSP1_
EXT_B_
PSIZE16
0
0
0
0
0
0
DSP1_EXT_A_PAGE [15:0]
0
0
0
0
00000000h
00000000h
00000000h
0
0
0
0
0
DSP1_WDMA_ACTIVE_CHANNELS [7:0]
0
0
Default
00000000h
0
0
0
0
0
16
0
DSP1_YM_1 [23:16]
0
0
0
0
R1048146 DSP1_Bus_Error_Addr
(FFE52h)
19
3
0
0
0
0
R1048130 DSP1_Scratch_2
(FFE42h)
20
4
0
0
0
0
0
0
0
0
0
DSP1_SCRATCH_1 [15:0]
DSP1_SCRATCH_0 [15:0]
DSP1_SCRATCH_3 [15:0]
DSP1_SCRATCH_2 [15:0]
0
0
DSP1_BUS_ERROR_ADDR [15:0]
0
0
0
0
R1048128 DSP1_Scratch_1
(FFE40h)
21
5
0
0
0
DSP1_START_IN_SEL [4:0]
0
0
DSP1_
CLK_
AVAIL
0
00000000h
00000000h
0
00000000h
DSP1_
WDT_ENA
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
0
00000000h
00000000h
0
00000000h
DSP1_
DMA_
WORD_
SEL
0
00000000h
00000000h
00000000h
00000000h
DSP1_BUS_ERROR_ADDR [23:16]
0
0
0
0
0
0
00000000h
0
0
0
0
0
0
00000000h
DSP1_EXT_B_PAGE [15:0]
DS1137PP1
273
CS47L15
7 Thermal Characteristics
Table 6-2. Register Map Definition—32-bit region (Cont.)
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
Default
R1048152 DSP1_Ext_window_C
(FFE58h)
DSP1_
EXT_C_
PSIZE16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000h
R1048154 DSP1_Ext_window_D
(FFE5Ah)
DSP1_
EXT_D_
PSIZE16
0
0
0
0
0
0
DSP1_EXT_C_PAGE [15:0]
0
0
0
0
0
0
0
0
0
00000000h
R1048158 DSP1_Watchdog_2
(FFE5Eh)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000h
R1048160 DSP1_Identity
(FFE60h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register
Name
R1048164 DSP1_Region_lock_sts_
(FFE64h) 0
R1048166 DSP1_Region_lock_1__
(FFE66h) _DSP1_Region_lock_0
R1048168 DSP1_Region_lock_3__
(FFE68h) _DSP1_Region_lock_2
R1048186 DSP1_Region_lock_
(FFE7Ah) ctrl_0
R1048188 DSP1_PMEM_ERR_
(FFE7Ch) ADDR___DSP1_
XMEM_ERR_ADDR
0
0
0
DSP1_
DSP1_
DSP1_
LOCK_ ADDR_
WDT_
ERR_STS ERR_STS TIMEOUT_
STS
0
0
0
0
0
0
0
DSP1_EXT_D_PAGE [15:0]
0
0
DSP1_WDT_RESET [15:0]
0
0
0
0
0
0
0
0
DSP1_CTRL_REGION1_LOCK [15:0]
DSP1_CTRL_REGION0_LOCK [15:0]
DSP1_CTRL_REGION3_LOCK [15:0]
DSP1_CTRL_REGION2_LOCK [15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000h
DSP1_CORE_NUMBER [4:0]
0
0
0
0
00000000h
DSP1_
DSP1_
DSP1_
DSP1_
CTRL_
CTRL_
CTRL_
CTRL_
REGION3_REGION2_REGION1_REGION0_
LOCK_ LOCK_ LOCK_ LOCK_
STS
STS
STS
STS
00000000h
00000000h
0
0
0
DSP1_
SLAVE_
DBG_ENA
0
0
0
0
0
DSP1_
ERR_
PAUSE
0
DSP1_
ERR_
CLEAR
00000000h
00000000h
DSP1_PMEM_ERR_ADDR [14:0]
DSP1_XMEM_ERR_ADDR [15:0]
7 Thermal Characteristics
Table 7-1. Typical JEDEC Four-Layer, 2s2p Board Thermal Characteristics
Symbol
WLCSP
Units
Junction-to-ambient thermal resistance
Parameter
JA
43.4
°C/W
Junction-to-board thermal resistance
JB
16.2
°C/W
Junction-to-case thermal resistance
JC
2.87
°C/W
Junction-to-board thermal-characterization parameter
JB
16.1
°C/W
Junction-to-package-top thermal-characterization parameter
JT
0.17
°C/W
Notes:
• Natural convection at the maximum recommended operating temperature TA (see Table 3-3)
• Four-layer, 2s2p PCB as specified by JESD51-9 and JESD51-11; dimensions: 101.5 x 114.5 x 1.6 mm
• Thermal parameters as defined by JESD51-12
274
DS1137PP1
CS47L15
8 Package Dimensions
8 Package Dimensions
Ball A1 Location Indicator
(seen through package)
X
A
A2
g
X
M
A1
c
Ball A1
Location
Indicator
d
Seating
plane
e
Y
N
Z
Z
e
f
d
Y
WAFER BACK SIDE
c
SIDE VIEW
b
70 x Øb
Øddd M Z X Y
Øccc M Z
e
BUMP SIDE
Notes:
• Dimensioning and tolerances per ASME Y 14.5M–2009.
• The Ball A1 position indicator is for illustration purposes only and may not be to scale.
• Dimension “b” applies to the solder sphere diameter and is measured at the midpoint
between the package body and the seating plane Datum Z.
Table 8-1. WLCSP Package Dimensions
Dimension
Minimum
0.474
0.172
0.287
BSC
BSC
0.247
0.2017
0.1940
BSC
BSC
REF
2.9864
3.4886
Millimeters
Nominal
0.504
0.202
0.302
2.6
3.1176
0.262
0.2057
0.1980
0.40
0.3464
0.022
3.0114
3.5136
A
A1
A2
M
N
b
c
d
e
f
g
X
Y
ccc = 0.05
ddd = 0.15
Note: Controlling dimension is millimeters.
DS1137PP1
Maximum
0.534
0.232
0.317
BSC
BSC
0.277
0.2097
0.2020
BSC
BSC
REF
3.0364
3.5386
275
CS47L15
9 Ordering Information
9 Ordering Information
Table 9-1. Ordering Information
Product
Description
CS47L15 Smart Codec with
Low-Power Audio DSP
Package
70-ball
WLCSP
Halogen
Free
Pb
Free
Grade
Temperature
Range
Yes
Yes
Commercial
–40 to +85°C
Container
Order #
Tape and
Reel 1
CS47L15–CWZR
1.Reel quantity = 6,000
10 References
•
Google Inc, Android Wired Headset Specification, Version 1.1. https://source.android.com/accessories/
headset-spec.html
•
International Electrotechnical Commission, IEC60958-3 Digital Audio Interface—Consumer. http://www.ansi.org/
11 Revision History
Table 11-1. Revision History
Revision
PP1
NOV ‘16
276
Changes
•
•
•
•
•
•
•
Power sequencing requirements updated (Table 3-3).
IN2 noise specification updated (Table 3-9).
MICD accessory detection description updated (Table 4-66).
MICBIAS control for accessory detection updated (Table 4-66, Section 4.9.3.2).
Register bit position of GPn_POL corrected (Table 4-72).
FLL control requirements updated (Section 4.13.8).
Initialization sequence (patch) requirements added (Section 4.19.5).
DS1137PP1
CS47L15
11 Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
”Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. For the purposes of our terms and
conditions of sale, “Preliminary” or “Advanced” datasheets are non-final datasheets that include but are not limited to datasheets marked as “Target”, “Advance”, “Product
Preview”, “Preliminary Technical Data” and/or “Pre-production.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated
with “Preliminary” or “Advanced” designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.; and other companies in the
Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to applicable license terms. Cirrus
Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore
obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques
are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks
associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. Cirrus
Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Cirrus Logic products.
Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require action by the user, and some or
all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode over another. Likewise,
description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be suitable for operation.
Features and operations described herein are for illustrative purposes only.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
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constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein
only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without
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of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.
Copyright © 2016 Cirrus Logic, Inc. All rights reserved.
USB-C is a trademark of USB Implementers Forum.
Android is a trademark of Google, Inc.
SPI is a trademark of Motorola.
DS1137PP1
277
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