TPS54352/3/4/5/6/7: 4.5-V to 20-V Input, 3-A

TPS54352/3/4/5/6/7: 4.5-V to 20-V Input, 3-A
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004

FEATURES
D 100 mΩ, 4.5-A Peak MOSFET Switch for High
D
D
D
D
D
D
D
D
D
D
Efficiency at 3-A Continuous Output Current
Uses External Lowside MOSFET or Diode
Fixed Output Versions −
1.2V/1.5V/1.8V/2.5V/3.3V/5.0V
Internally Compensated for Low Parts Count
Synchronizes to External Clock
1805 Out of Phase Synchronization
Wide PWM Frequency − Fixed 250 kHz,
500 kHz or Adjustable 250 kHz to 700 kHz
Internal Slow Start
Load Protected by Peak Current Limit and
Thermal Shutdown
Adjustable Undervoltage Lockout
16-Pin TSSOP PowerPADE Package
APPLICATIONS
D Industrial & Commercial Low Power Systems
D LCD Monitors and TVs
D Computer Peripherals
D Point of Load Regulation for High
DESCRIPTION
The TPS5435x is a medium output current synchronous
buck PWM converter with an integrated high side
MOSFET and a gate driver for an optional low side
external MOSFET. Features include a high performance
voltage error amplifier that enables maximum
performance under transient conditions. The TPS5435x
has an under-voltage-lockout circuit to prevent start-up
until the input voltage reaches a preset value; an internal
slow-start circuit to limit in-rush currents; and a power good
output to indicate valid output conditions. The
synchronization feature is configurable as either an input
or an output for easy 180° out of phase synchronization.
The TPS5435x devices are available in a thermally
enhanced 16-pin TSSOP (PWP) PowerPAD package.
TI provides evaluation modules and the SWIFT Designer
software tool to aid in quickly achieving high-performance
power supply designs to meet aggressive equipment
development cycles.
EFFICIENCY
vs
OUTPUT CURRENT
100
Performance DSPs, FPGAs, ASICs and
Microprocessors
Input
Voltage
TPS54356
VI = 12 V
90
Efficiency − %
SIMPLIFIED SCHEMATIC
VI = 6 V
95
85
80
75
70
65
60
SYNC
VI= 12 V
VO= 3.3 V
fs = 500 kHz
VIN
55
PWRGD
50
0
ENA
BOOT
BIAS
1
2
3
4
IO − Output Current − A
PH
LSG
Output
Voltage
PGND
VSENSE
PWRPAD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
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Copyright  2004, Texas Instruments Incorporated
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
1.2 V
Plastic HTSSOP (PWP)
TPS54352PWP
1.5 V
Plastic HTSSOP (PWP)
TPS54353PWP
1.8 V
Plastic HTSSOP (PWP)
TPS54354PWP
2.5 V
Plastic HTSSOP (PWP)
TPS54355PWP
3.3 V
Plastic HTSSOP (PWP)
TPS54356PWP
5.0 V
Plastic HTSSOP (PWP)
TPS54357PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS5435xPWPR).
PACKAGE DISSIPATION RATINGS(1)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
16-Pin PWP with solder(2)
42.1°C/W
2.36
1.31
0.95
16-Pin PWP without solder
151.9°C/W
0.66
0.36
0.26
PACKAGE
(1) See Figure 47 for power dissipation curves.
(2) Test Board Conditions
1. Thickness: 0.062”
2. 3” x 3”
3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and ground planes, 1 oz. copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
2
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage range, VI
Output voltage range, VO
Source current, IO
Sink current, IS
Voltage differential
VIN
−0.3 V to 21.5 V
VSENSE
−0.3 V to 8.0 V
UVLO
−0.3 V to 8.0 V
SYNC
−0.3 V to 4.0 V
ENA
−0.3 V to 4.0 V
BOOT
VI(PH) + 8.0 V
VBIAS
−0.3 to 8.5 V
LSG
−0.3 to 8.5 V
SYNC
−0.3 to 4.0 V
RT
−0.3 to 4.0 V
PWRGD
−0.3 to 6.0 V
COMP
−0.3 to 4.0 V
PH
−1.5 V to 22 V
PH
Internally Limited (A)
LSG (Steady State Current)
10 mA
COMP, VBIAS
3 mA
SYNC
5 mA
LSG (Steady State Current)
100 mA
PH (Steady State Current)
500 mA
COMP
3 mA
ENA, PWRGD
10 mA
AGND to PGND
±0.3 V
Operating virtual junction temperature range, TJ
−40°C to +150°C
Storage temperature, Tstg
−65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
UNIT
Human body model
600
V
CDM
1.5
kV
RECOMMENDED OPERATING CONDITIONS
MIN
TPS54352−6
Input voltage range, VI
Operating junction temperature, TJ
TPS54357
NOM
MAX
4.5
20
6.65
20
−40
125
UNIT
V
°C
3
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IQ
Operating current, PH pin open,
No external low side MOSFET, RT = Hi-Z
Quiescent current
5
Shutdown, ENA = 0 V
1
TPS54352−6
Start threshold voltage
VIN
Stop threshold voltage
Hysteresis
mA
TPS54357
mA
4.32
4.49
6.4
6.65
TPS54352−6
3.69
3.97
TPS54357
5.45
5.80
V
V
TPS54352−6
350
mV
TPS54357
600
mV
OUTPUT VOLTAGE
VO
TPS54352
TJ = 25°C, IO = 100 mA to 3 A
IO = 100 mA to 3 A
1.88
1.2
1.212
1.176
1.2
1.224
TPS54353
TJ = 25°C, IO = 100 mA to 3 A
IO = 100 mA to 3 A
1.485
1.5
1.515
1.47
1.5
1.53
1.782
1.8
1.818
TPS54354
TJ = 25°C, IO = 100 mA to 3 A
IO = 100 mA to 3 A
1.764
1.8
1.836
2.475
2.5
2.525
TPS54355
TJ = 25°C, IO = 100 mA to 3 A
IO = 100 mA to 3 A
2.45
2.5
2.55
TJ = 25°C, VIN = 5.5 V to 20 V, IO = 100 mA to 3 A
VIN = 5.5 V to 20 V, IO = 100 mA to 3 A
3.267
3.3
3.333
TPS54356
3.234
3.3
3.366
4.95
5.0
5.05
TPS54357
TJ = 25°C, VIN = 7.5 V to 20 V, IO = 100 mA to 3 A
VIN = 7.5 V to 20 V, IO = 100 mA to 3 A
4.90
5.0
5.10
1.20
1.24
Output voltage
V
UNDER VOLTAGE LOCK OUT (UVLO PIN)
Start threshold voltage
UVLO
Stop threshold voltage
1.02
Hysteresis
V
1.10
V
100
mV
BIAS VOLTAGE (VBIAS PIN)
VBIAS
Output voltage
IVBIAS = 1 mA, VIN ≥ 12 V
IVBIAS = 1 mA, VIN = 4.5 V
7.5
7.8
8.0
4.4
4.47
4.5
RT Grounded
200
250
300
RT Open
400
500
600
RT = 100 kΩ (1% resistor to AGND)
425
500
575
V
OSCILLATOR (RT PIN)
Internally set PWM switching frequency
Externally set PWM switching frequency
4
kHz
kHz
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN)
SYNC out low-to-high rise time (10%/90%) (1)
25 pF to ground
200
500
ns
SYNC out high-to-low fall time (90%/10%) (1)
25 pF to ground
5
10
ns
Falling edge delay time (1)
Delay from rising edge to rising edge of PH
pins, see Figure 19
180
°
Minimum input pulse width (1)
RT = 100 kΩ
100
ns
Delay (falling edge SYNC to rising edge PH) (1)
RT = 100 kΩ
360
ns
SYNC out high level voltage
50-kΩ Resistor to ground, no pullup resistor
2.5
V
0.6
SYNC out low level voltage
0.8
SYNC in low level threshold
V
2.3
SYNC in high level threshold
Percentage of programmed frequency
SYNC in frequency range (1)
V
−10%
10%
225
770
V
kHz
FEED− FORWARD MODULATOR (INTERNAL SIGNAL)
Modulator gain
VIN = 12 V, TJ = 25°C
Modulator gain variation
8
−25%
Minimum controllable ON time (1)
Maximum duty factor (1)
V/V
25%
180
VIN = 4.5 V
80%
ns
86%
VSENSE PIN
Input bias current, VSENSE pin
µA
1
ENABLE (ENA PIN)
Disable low level input voltage
0.5
TPS54352
TPS54353
Internal slow-start time
(10% to 90%)
TPS54354
TPS54355
TPS54356
TPS54357
fs = 250 kHz, RT = ground (1)
fs = 500 kHz, RT = Hi−Z (1)
fs = 250 kHz, RT = ground (1)
3.20
fs = 500 kHz, RT = Hi−Z (1)
fs = 250 kHz, RT = ground (1)
fs = 500 kHz, RT = Hi−Z (1)
2.00
fs = 250 kHz, RT = ground (1)
fs = 500 kHz, RT = Hi−Z (1)
fs = 250 kHz, RT = ground (1)
4.40
fs = 500 kHz, RT = Hi−Z (1)
fs = 250 kHz, RT = ground (1)
2.90
fs = 500 kHz, RT = Hi−Z (1)
2.70
Pullup current source
Pulldown MOSFET
V
1.60
4.00
4.60
2.30
ms
2.20
5.90
5.40
1.8
5
II(ENA)= 1 mA
0.1
Power good threshold
Rising voltage
97%
Rising edge delay (1)
fs = 250 kHz
fs = 500 kHz
10
µA
V
POWER GOOD (PWRGD PIN)
Output saturation voltage
PWRGD
Output saturation voltage
Open drain leakage current
(1) Ensured by design, not production tested.
Isink = 1 mA, VIN > 4.5 V
Isink = 100 µA, VIN = 0 V
Voltage on PWRGD = 6 V
4
ms
2
0.05
V
0.76
V
3
µA
5
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT
Current limit
VIN = 12 V
Current limit hiccup time (1)
fs = 500 kHz
3.3
4.5
6.5
A
4.5
ms
165
_C
7
_C
VIN = 4.5 V, Capacitive load = 1000 pF
15
ns
VIN = 12 V
60
ns
VIN = 4.5 V sink/source
7.5
VIN = 12 V sink/source
5
THERMAL SHUTDOWN
Thermal shutdown trip point (1)
Thermal shutdown hysteresis (1)
LOW SIDE MOSFET DRIVER (LSG PIN)
Turn on rise time, (10%/90%) (1)
Deadtime (1)
Driver ON resistance
Ω
OUTPUT POWER MOSFETS (PH PIN)
Phase node voltage when disabled
Voltage drop, low side FET and diode
rDS(ON)
High side power MOSFET switch (2)
(1) Ensured by design, not production tested.
(2) Resistance from VIN to PH pins.
6
DC conditions and no load, ENA = 0 V
0.5
V
VIN = 4.5 V, Idc = 100 mA
1.13
1.42
VIN = 12 V, Idc = 100 mA
1.08
1.38
VIN = 4.5 V, BOOT−PH = 4.5 V, IO = 0.5 A
150
300
VIN = 12 V, BOOT−PH = 8 V, IO = 0.5 A
100
200
V
mΩ
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
1
2
3
4
5
6
7
8
THERMAL
PAD
16
15
14
13
12
11
10
9
BOOT
PH
PH
LSG
VBIAS
PGND
AGND
VSENSE
NOTE: If there is not a Pin 1 indicator, turn device to enable
reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.
Terminal Functions
TERMINAL
NO.
1, 2
DESCRIPTION
NAME
VIN
Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor. Place cap as close to device as
possible; see Figure 23 for an example.
3
UVLO
Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal
default VIN start and stop thresholds.
4
PWRGD
Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage.
There is an internal rising edge filter on the output of the PWRGD comparator.
5
RT
Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to
ground or floating will set the frequency to an internally preselected frequency.
6
SYNC
Bidirectional synchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a
falling edge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock
by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the
Application Information section. In ALL cases, a 10 kΩ resistor Must be tied to the SYNC pin in parallel with ground. For
information on how to extend slow start, see the Enable (ENA) and Internal Slow Start section on page 9.
7
ENA
Enable. Below 0.5 V, the device stops switching. Float pin to enable.
8
COMP
Error amplifier output. Do NOT connect ANYTHING to this pin.
9
VSENSE
Feedback pin
10
AGND
Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.
11
PGND
Power ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Connect
to AGND and PowerPAD.
12
VBIAS
Internal 8.0-V bias voltage. A 1.0-µF ceramic bypass capacitance is required on the VBIAS pin.
13
LSG
Gate drive for optional low side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency synchronous buck
converter configuration. Otherwise, leave open and connect schottky diode from ground to PH pins.
PH
Phase node—Connect to external L−C filter.
BOOT
Bootstrap capacitor for high side gate driver. Connect a 0.1-µF ceramic capacitor from BOOT to PH pins.
PowerPAD
PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 23 for an example PCB
layout.
14, 15
16
7
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
FUNCTIONAL BLOCK DIAGRAM
BOOT
VIN
PH
320 kΩ
Hiccup
UVLO
UVLO
125 kΩ(1)
SYNC
Current Limit
1.2V
2x Oscillator
RT
Bias + Drive
Regulator
PWM Ramp
(FeedFoward)
Z3
VBIAS
PWM
Comparator
COMP
S
Q
Adaptive Deadtime
and
Control Logic
Z1
Z4
VSENSE
VBIAS2
Z2
Error
Amplifier
LSG
R
Z5
Thermal
Shutdown
Reference
System
PWRGD
UVLO
5 µA
VSENSE
97% Ref
ENA
Hiccup
Timer
VBIAS
UVLO
Rising
Edge
Delay
Hiccup
TPS5435X
POWERPAD
(1) 75 kΩ for the TPS54357
VBIAS
PGND
AGND
DETAILED DESCRIPTION
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) system has an internal
voltage divider from VIN to AGND. The defaults for the
start/stop values are labeled VIN and given in Table 1. The
internal UVLO threshold can be overridden by placing an
external resistor divider from VIN to ground. The internal
divider values are approximately 320 kΩ for the high side
resistor and 125 kΩ for the low side resistor. The divider
ratio (and therefore the default start/stop values) is quite
accurate, but the absolute values of the internal resistors
may vary as much as 15%. If high accuracy is required for
an externally adjusted UVLO threshold, select lower value
external resistors to set the UVLO threshold. Using a 1-kΩ
resistor for the low side resistor (R2 see Figure 1) is
recommended. Under no circumstances should the UVLO
pin be connected directly to VIN.
Table 1. Start/Stop Voltage Threshold
VIN (Default)
START VOLTAGE THRESHOLD
STOP VOLTAGE THRESHOLD
TPS54352−6
4.49
3.69
TPS54357
6.65
5.45
1.24
1.02
UVLO
The equations for selecting the UVLO resistors are:
VIN(start) 1 kW
R1 1kW
1.24 V
8
(1)
VIN(stop) (R1 1 kW) 1.02 V
1 kW
(2)
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Input
Voltage
Supply
320 kΩ
R1
R2
1 kΩ
125 kΩ (1)
5 µA
Disabled
(1) 75 kΩ for the TPS54357
RSS
CSS
Enabled
Figure 1. Circuit Using External UVLO Function
Figure 2. Interfacing to the ENA Pin
For applications which require an undervoltage lock out
(UVLO) threshold greater than 4.49 V (6.6 V for
TPS54357), external resistors may be implemented, see
Figure 1, to adjust the start voltage threshold. For example,
an application needing an UVLO start voltage of
approximately 7.8 V using the equation (1), R1 is
calculated to the nearest standard resistor value of
5.36 kΩ. Using equation (2), the input voltage stop
threshold is calculated as 6.48 V.
Extending Slow Start Time
In applications that use large values of output capacitance
there may be a need to extend the slow start time to
prevent the startup current from tripping the current limit.
The current limit circuit is designed to disable the high side
MOSFET and reset the internal voltage reference for a
short amount of time when the high side MOSFET current
exceeds the current limit threshold. If the output
capacitance and load current cause the startup current to
exceed the current limit threshold, the power supply output
will not reach the desired output voltage. To extend the
slow start time and to reduce the startup current, an
external resistor and capacitor can be added to the ENA
pin. The slow start capacitance is calculated using the
following equation:
Enable (ENA) and Internal Slow Start
The TPS5435x has an internal digital slow start that ramps
the reference voltage to its final value in 1150 switching
cycles. The internal slow start time (10% − 90%) is
approximated by the following expression:
1.15k
T
(ms) SS_INTERNAL
ƒs(kHz) n
CSS(µF) = 5.55 10−3 n Tss(ms)
(4)
Use n in Table 2
(3)
Use n in Table 2
The RSS resistor must be 2 kΩ and the slow start capacitor
must be less than 0.47 µF.
Table 2. Slow Start Characteristics
DEVICE
n
TPS54352
1.485
TPS54353
1.2
TPS54354
1
TPS54355
1.084
TPS54356
0.818
TPS54357
0.900
Once the TPS5435x device is in normal regulation, the
ENA pin is high. If the ENA pin is pulled below the stop
threshold of 0.5 V, switching stops and the internal slow
start resets. If an application requires the TPS5435x to be
disabled, use open drain or open collector output logic to
interface to the ENA pin (see Figure 2). The ENA pin has
an internal pullup current source. Do not use external
pullup resistors.
Switching Frequency (RT)
The TPS5435x has an internal oscillator that operates at
twice the PWM switching frequency. The internal oscillator
frequency is controlled by the RT pin. Grounding the RT
pin sets the PWM switching frequency to a default
frequency of 250 kHz. Floating the RT pin sets the PWM
switching frequency to 500 kHz.
Connecting a resistor from RT to AGND sets the frequency
according to the following equation (also see Figure 30).
RT(kW) 46000
ƒ s(kHz) 35.9
(5)
The RT pin controls the SYNC pin functions. If the RT pin
is floating or grounded, SYNC is an output. If the switching
frequency has been programmed using a resistor from RT
to AGND, then SYNC functions as an input.
The internal voltage ramp charging current increases
linearly with the set frequency and keeps the feed forward
modulator constant (Km = 8) regardless of the frequency
set point.
9
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Table 3.
SWITCHING FREQUENCY
SYNC PIN
RT PIN
250 kHz, internally set
Generates SYNC output signal
AGND
500 kHz, internally set
Generates SYNC output signal
Float
Externally set to 250 kHz to 700 kHz
Terminate to quiet ground
with 10-kΩ resistor.
R = 215 kΩ to 69 kΩ
Synchronization Signal
Set RT resistor equal to 90% to 110% of external synchronization
frequency.When using a dual setup (see Figure 27 for example),
if the master 35x device RT pin is left floating, use a 110 kΩ
resistor to tie the slave RT pin to ground. Conversely, if the master
35x device RT pin is grounded, use a 237 kΩ resistor to tie the
slave RT pin to ground.
Externally synchronized frequency
1805 Out of Phase Synchronization (SYNC)
The SYNC pin is configurable as an input or as an output,
per the description in the previous section. When
operating as an input, the SYNC pin is a falling-edge
triggered signal (see Figures 3, 4, and 19). When operating
as an output, the signal’s falling edge is approximately
180° out of phase with the rising edge of the PH pins. Thus,
two TPS5435x devices operating in a system can share an
input capacitor and draw ripple current at twice the
frequency of a single unit.
When operating the two TPS5435x devices 180° out of
phase, the total RMS input current is reduced. Thus
reducing the amount of input capacitance needed and
increasing efficiency.
When synchronizing a TPS5435x to an external signal, the
timing resistor on the RT pin must be set so that the
oscillator is programmed to run at 90% to 110% of the
synchronization frequency.
VI(SYNC)
VO(PH)
Figure 3. SYNC Input Waveform
10
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Internal Oscillator
VO(PH)
VO(SYNC)
Figure 4. SYNC Output Waveform
Power Good (PWRGD)
The VSENSE pin is compared to an internal reference
signal, if the VSENSE is greater than 97% and no other
faults are present, the PWRGD pin presents a high
impedance. A low on the PWRGD pin indicates a fault. The
PWRGD pin has been designed to provide a weak
pull-down and indicates a fault even when the device is
unpowered. If the TPS5435x has power and has any fault
flag set, the TPS5435x indicates the power is not good by
driving the PWRGD pin low. The following events, singly
or in combination, indicate power is not good:
D
D
D
D
D
D
D
VSENSE pin out of bounds
Overcurrent
Thermal shutdown
UVLO undervoltage
Input voltage not present (weak pull-down)
Slow-starting
VBIAS voltage is low
Once the PWRGD pin presents a high impedance (i.e.,
power is good), a VSENSE pin out of bounds condition
forces PWRGD pin low (i.e., power is bad) after a time
delay. This time delay is a function of the switching
frequency and is calculated using equation 6:
T
delay
1000 ms
ƒs(kHz)
capacitor value of 1.0 µF. X7R or X5R grade dielectric
ceramic capacitors are recommended because of their
stable characteristics over temperature.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by cycle from
the VBIAS capacitor. A capacitor from the BOOT pin to the
PH pins is required for operation. The bootstrap
connection for the high side driver must have a bypass
capacitor of 0.1 µF.
Error Amplifier
The VSENSE pin is the error amplifier inverting input. The
error amplifier is a true voltage amplifier with 1.5 mA of
drive capability with a minimum of 60 dB of open loop
voltage gain and a unity gain bandwidth of 2 MHz.
Voltage Reference
The voltage reference system produces a precision
reference signal by scaling the output of a temperature
stable bandgap circuit. During production testing, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset
errors in the scaling and error amplifier circuits.
PWM Control and Feed Forward
(6)
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low side gate driver. Up to
1 mA of current can be drawn for use in an external
application circuit. The VBIAS pin must have a bypass
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, PWM latch, and the
adaptive dead-time control logic. During steady-state
operation below the current limit threshold, the PWM
comparator output and oscillator pulse train alternately
reset and set the PWM latch.
11
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Once the PWM latch is reset, the low-side driver and
integrated pull-down MOSFET remain on for a minimum
duration set by the oscillator pulse width. During this
period, the PWM ramp discharges rapidly to the valley
voltage. When the ramp begins to charge back up, the
low-side driver turns off and the high-side FET turns on.
The peak PWM ramp voltage varies inversely with input
voltage to maintain a constant modulator and power stage
gain of 8 V/V.
Low Side Gate Driver (LSG)
As the PWM ramp voltage exceeds the error amplifier
output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
Integrated Pulldown MOSFET
During transient conditions, the error amplifier output can
be below the PWM ramp valley voltage or above the PWM
peak voltage. If the error amplifier is high, the PWM latch
is never reset and the high-side FET remains on until the
oscillator pulse signals the control logic to turn the
high-side FET off and the internal low-side FET and driver
on. The device operates at its maximum duty cycle until the
output voltage rises to the regulation set point, setting
VSENSE to approximately the same voltage as the
internal voltage reference. If the error amplifier output is
low, the PWM latch is continually reset and the high-side
FET does not turn on. The internal low-side FET and low
side driver remain on until the VSENSE voltage decreases
to a range that allows the PWM comparator to change
states. The TPS5435x is capable of sinking current
through the external low side FET until the output voltage
reaches the regulation set point.
The minimum on time is designed to be 180 ns. During the
internal slow-start interval, the internal reference ramps
from 0 V to 0.891 V. During the initial slow-start interval, the
internal reference voltage is very small resulting in a
couple of skipped pulses because the minimum on time
causes the actual output voltage to be slightly greater than
the preset output voltage until the internal reference ramps
up.
Deadtime Control
Adaptive dead time control prevents shoot through current
from flowing in the integrated high-side MOSFET and the
external low-side MOSFET during the switching
transitions by actively controlling the turn on times of the
drivers. The high-side driver does not turn on until the
voltage at the gate of the low-side MOSFET is below 1 V.
The low-side driver does not turn on until the voltage at the
gate of the high-side MOSFET is below 1 V.
12
LSG is the output of the low-side gate driver. The 100-mA
MOSFET driver is capable of providing gate drive for most
popular MOSFETs suitable for this application. Use the
SWIFT Designer Software Tool to find the most
appropriate MOSFET for the application. Connect the LSG
pin directly to the gate of the low-side MOSFET. Do not use
a gate resistor as the resulting turn-on time may be too
slow.
The TPS5435x has a diode-MOSFET pair from PH to
PGND. The integrated MOSFET is designed for light−load
continuous-conduction mode operation when only an
external Schottky diode is used. The combination of
devices keeps the inductor current continuous under
conditions where the load current drops below the
inductor’s critical current. Care should be taken in the
selection of inductor in applications using only a low-side
Schottky diode. Since the inductor ripple current flows
through the integrated low-side MOSFET at light loads, the
inductance value should be selected to limit the peak
current to less than 0.3 A during the high-side FET turn off
time. The minimum value of inductance is calculated using
the following equation:
VO 1 VO
VI
L(H) ƒ s 0.6
(7)
Thermal Shutdown
The device uses the thermal shutdown to turn off the
MOSFET drivers and controller if the junction temperature
exceeds 165°C. The device is restarted automatically
when the junction temperature decreases to 7°C below the
thermal shutdown trip point and starts up under control of
the slow-start circuit.
Overcurrent Protection
Overcurrent protection is implemented by sensing the
drain-to-source voltage across the high-side MOSFET
and compared to a voltage level which represents the
overcurrent threshold limit. If the drain-to-source voltage
exceeds the overcurrent threshold limit for more than
100 ns, the ENA pin is pulled low, the high-side MOSFET
is disabled, and the internal digital slow-start is reset to 0 V.
ENA is held low for approximately the time that is
calculated by the following equation:
T
HICCUP
(ms) 2250
ƒs(kHz)
(8)
Once the hiccup time is complete, the ENA pin is released
and the converter initiates the internal slow-start.
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Switching Frequency Limitations
Due to the internal design of the TPS54352−6 there are
limitations to the maximum usable switching frequency for
any given input voltage. This limit is constrained by the
minimum controllable on time which may be as high as
220 ns. Figure 31 shows the maximum switching
frequency versus input voltage for each device. This family
of curves is valid for output currents greater than 0.5 A. As
output currents decrease towards no load (0 A), the
apparent on time increases, decreasing the maximum
switching frequency that may be obtained for a given input
and output voltage. Figure 32 shows the maximum
switching frequency versus input voltage for each device
for zero load current various operating frequencies.
13
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
Conditions are VI = 12 V, VO = 3.3 V, fs = 500 kHz, IO = 3 A, TA = 25 °C, unless otherwise noted
MEASURED LOOP RESPONSE
0.1
90
20
60
30
Gain
0
0
−10
−30
−20
−60
−30
−90
−40
−50
−60
100
Phase − Degrees
30
10
0.08
120
Phase
−120
See Figure 25
1k
10 k
100 k
−150
−180
1M
0.2
VI = 12 V
0.1
VI = 6 V
0
VI = 18 V
−0.1
−0.2
−0.3
0
0.5
1
0.06
0
−0.02
IO = 0 A
−0.04
−0.06
1.5
2
2.5
3
3.5
−0.1
4
See Figure 25
6
8
10
12
14
16
Figure 7
INPUT RIPPLE VOLTAGE
OUTPUT RIPPLE VOLTAGE
VI(RIPPLE) = 100 mV/div (ac coupled)
VI = 12 V
VO(RIPPLE) = 10 mV/div (ac coupled)
90
80
VI = 18 V
75
70
V(PH) = 5 V/div
Amplitude
Amplitude
85
Efficiency − %
V(PH) = 5 V/div
65
60
55
See Figure 25
50
0
1
See Figure 25
2
3
4
See Figure 25
Time − 1 µs/div
IO − Output Current − A
Figure 8
Time − 1 µs/div
Figure 9
Figure 10
POWER UP
LOAD TRANSIENT RESPONSE
GATE DRIVE VOLTAGE
See Figure 25
Time − 1 µs/div
Figure 11
I(PH) = 1 A/div
See Figure 25
Time − 200 µs/div
Figure 12
Power Up Response − mV
V(PH) = 5 V/div
Load Transient Response − mV
VO = 50 mV/div (ac coupled)
V(LSG) = 5 V/div
Amplitude
20
VI = 6 V
95
14
18
VI − Input Voltage − V
Figure 6
EFFICIENCY
vs
OUTPUT CURRENT
IO = 1.5 A
0.02
IO − Output Current − A
Figure 5
IO = 3 A
0.04
−0.08
See Figure 25
f − Frequency − Hz
100
Output Voltage Change − %
150
40
Output Voltage Change − %
50
G − Gain − dB
LINE REGULATION
LOAD REGULATION
0.3
180
60
VI = 5 V/div
VO= 2 V/div
V(PWRGD)= 2 V/div
See Figure 25
Time − 2 ms/div
Figure 13
22
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Conditions are VI = 12 V, VO = 3.3 V, fs = 500 kHz, IO = 3 A, TA = 25 °C, unless otherwise noted
EFFICIENCY
vs
OUTPUT CURRENT
100
CONTINUOUS CONDUCTION MODE
VI = 6 V
95
V(PH) = 5 V/div
VI = 12 V
Continuous Conduction Mode
POWER DOWN
Power Down Waveforms − V
90
85
Efficiency − %
VI = 5 V/div
VO= 2 V/div
VI = 18 V
80
75
70
65
V(PWRGD)= 2 V/div
60
I(L1) = 200 mA/div
55
See Figure 26
See Figure 26
50
See Figure 25
0
1
2
3
4
Time − 1 µs/div
IO − Output Current − A
Time − 2 ms/div
Figure 14
Figure 15
LIGHT LOAD CONDUCTION
Figure 16
SEQUENCING WAVEFORMS
INPUT RIPPLE CANCELLATION
V(PH1) = 10 V/div
I(L1) = 200 mA/div
VI = 10 V/div
Input Ripple Cancellation − V
Sequencing Waveforms − V
Light Load Conduction
V(PH) = 5 V/div
VO1(3.3)= 2 V/div
V(PWRGD1)= 2 V/div
V(PH2) = 10 V/div
VI = 50 mV/div (ac coupled)
VO2 (1.8)= 2 V/div
Time − 1 µs/div
MEASURED LOOP RESPONSE
100 mF POSCAP
30
90
20
60
G − Gain − dB
10
0
Gain
30
0
−10
−30
−20
−60
−30
−40
−50
−60
100
See Figure 28
1k
10 k
f − Frequency − Hz
Figure 20
100 k
Figure 19
MEASURED LOOP RESPONSE
2 x 180 mF SP CAPACITORS
MEASURED LOOP RESPONSE
330 mF OSCON
180
60
150
50
40
120
40
120
30
90
30
90
Phase
20
60
Gain
10
30
0
0
−90
−120
−40
−150
−180
1M
−50
−120
−40
−150
−50
−60
f − Frequency − Hz
Figure 21
0
−60
−30
100 k
30
0
−30
−90
10 k
60
Gain
10
−90
−60
1k
20
−30
−20
100
150
−20
−30
−180
1M
180
Phase
−10
−10
See Figure 29
Phase − Degrees
120
Phase
Figure 18
G − Gain − dB
50
Phase − Degrees
60
150
G − Gain − dB
180
50
40
Time − 1 µs/div
Time − 2 ms/div
Figure 17
60
See Figure 27
See Figure 27
Phase − Degrees
See Figure 26
−120
See Figure 30
−60
100
1k
−150
10 k
100 k
−180
1M
f − Frequency − Hz
Figure 22
15
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
LAYOUT INFORMATION
Figure 23. TPS5435x PCB Layout
PCB LAYOUT
The VIN pins should be connected together on the printed
circuit board (PCB) and bypassed with a low ESR ceramic
bypass capacitor. Care should be taken to minimize the
loop area formed by the bypass capacitor connections, the
VIN pins, and the TPS5435x ground pins. The minimum
recommended bypass capacitance is 10-µF ceramic with
a X5R or X7R dielectric and the optimum placement is
closest to the VIN pins and the AGND and PGND pins. See
Figure 23 for an example of a board layout. The AGND and
PGND pins should be tied to the PCB ground plane at the
pins of the IC. The source of the low-side MOSFET and the
anode of the Schottky diode should be connected directly
to the PCB ground plane. The PH pins should be tied
together and routed to the drain of the low-side MOSFET
or to the cathode of the external Schottky diode. Since the
PH connection is the switching node, the MOSFET (or
diode) should be located very close to the PH pins, and the
area of the PCB conductor minimized to prevent excessive
capacitive coupling. The recommended conductor width
from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce
16
copper. The length of the copper land pattern should be no
more than 0.2 inch.
For operation at full rated load, the analog ground plane
must provide adequate heat dissipating area. A 3-inch by
3-inch plane of copper is recommended, though not
mandatory, dependent on ambient temperature and
airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the bottom or top layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013-inch diameter vias to avoid solder
wicking through the vias. Four vias should be in the
PowerPAD area with four additional vias outside the pad
area and underneath the package. Additional vias beyond
those recommended to enhance thermal performance
should be included in areas not under the device package.
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
j0.0130
8 PL
Minimum recommended exposed copper
area for powerpad. 5mil stencils may
require 10 percent larger area.
Minimum recommended thermal vias: 4 x
.013 dia. inside powerpad area and
4 x .013 dia. under device as shown.
Additional .018 dia. vias may be used if top
side Analog Ground area is extended.
0.0150
0.06
0.0371
0.0400
0.1970
0.1942
0.0570
0.0400
0.0400
0.0256
Minimum recommended top
side Analog Ground area.
0.1700
0.1340
0.0690
0.0400
Connect Pin 10 AGND
and Pin 11 PGND to
Analog Ground plane in
this area for optimum
performance.
Figure 24. Thermal Considerations for PowerPAD Layout
17
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
APPLICATION INFORMATION
+
+
Figure 25. Application Circuit, 12 V to 3.3 V
Figure 25 shows the schematic for a typical TPS54356
application. The TPS54356 can provide up to 3-A output
current at a nominal output voltage of 3.3 V. For proper
thermal performance, the exposed PowerPAD underneath
the device must be soldered down to the printed circuit
board.
DESIGN PROCEDURE
The following design procedure can be used to select
component values for the TPS54356. Alternately, the
SWIFT Designer Software may be used to generate a
complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive
database of components when generating a design. This
section presents a simplified discussion of the design
process.
To begin the design process a few parameters must be
decided upon. The designer needs to know the following:
D
D
D
D
D
D
18
Input voltage range
For this design example, use the following as the input
parameters:
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 V to 18 V
Output voltage
3.3 V
Input ripple voltage
300 mV
Output ripple voltage
10 mV
Output current rating
3A
Operating frequency
500 kHz
SWITCHING FREQUENCY
The switching frequency is set using the RT pin.
Grounding the RT pin sets the PWM switching frequency
to a default frequency of 250 kHz. Floating the RT pin sets
the PWM switching frequency to 500 kHz. By connecting
a resistor from RT to AGND, any frequency in the range of
250 kHz to 700 kHz can be set. Use equation 9 to
determine the proper value of RT.
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
RT(kW) 46000
ƒ s(kHz) 35.9
(9)
In this example circuit, RT is not connected and the
switching frequency is set at 500 kHz.
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
INPUT CAPACITORS
The TPS54356 requires an input decoupling capacitor
and, depending on the application, a bulk input capacitor.
The minimum value for the decoupling capacitor, C9, is
10µF. A high quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than
the maximum input voltage. Additionally some bulk
capacitance may be needed, especially if the TPS54356
circuit is not located within about 2 inches from the input
voltage source. The value for this capacitor is not critical
but it also should be rated to handle the maximum input
voltage including ripple voltage and should filter the output
so that input ripple voltage is acceptable.
This input ripple voltage can be approximated by equation
10:
DVIN I OUT(MAX) 0.25
C BULK ƒ sw
I OUT(MAX) ESR (MAX)
(10)
The maximum RMS ripple current also needs to be
checked. For worst case conditions, this can be
approximated by equation 11:
OUT(MAX)
I
CIN
2
(11)
In this case the input ripple voltage would be 140 mV and
the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus
delta VIN/2. The chosen bulk and bypass capacitors are
each rated for 25 V and the combined ripple current
capacity is greater than 3 A, both providing ample margin.
It is very important that the maximum ratings for voltage
and current are not exceeded under any circumstance.
OUTPUT FILTER COMPONENTS
Inductor Selection
To calculate the minimum value of the output inductor, use
equation 12:
V
IN(MAX)
OUT
V
K
I
ƒ sw
IN(MAX)
IND
OUT
V
(MIN)
I
L(RMS)
1
I2
OUT(MAX) 12
V
V
OUT
V IN(MAX) V
OUT
IN(MAX)
L
OUT
ƒsw 0.8
2
(13)
and the peak inductor current can be determined with
equation 14:
V
OUT(MAX)
OUT
V IN(MAX) V
OUT
1.6 V IN(MAX) L
OUT
ƒsw
(14)
For this design, the RMS inductor current is 3.007 A and
the peak inductor current is 3.15 A. The chosen inductor
is a Coiltronics DR127−220 22 µH. It has a saturation
current rating of 7.57 A and a RMS current rating of 4 A,
easily meeting these requirements. A lesser rated inductor
could be used if less margin is desired. In general, inductor
values for use with the TPS54356 are in the range of 6.8
µH to 47 µH.
Capacitor Requirements
I
For the output filter inductor it is important that the RMS
current and saturation current ratings not be exceeded.
The RMS inductor current can be found from equation 13:
I L(PK) I
Where IOUT(MAX) is the maximum load current, ƒSW is the
switching frequency, CBULK is the bulk capacitor value and
ESRMAX is the maximum series resistance of the bulk
capacitor.
L
For this design example use KIND = 0.1 to keep the
inductor ripple current small. The minimum inductor value
is calculated to be 17.96 µH. The next highest standard
value is 22 µH, which is used in this design.
OUT
V
(12)
KIND is a coefficient that represents the amount of inductor
ripple current relative to the maximum output current. For
designs using low ESR output capacitors such as
ceramics, use KIND = 0.3. When using higher ESR output
capacitors, KIND = 0.2 yields better results.
The important design factors for the output capacitor are
dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current
ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the
amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do
exist.
Consider the relationship between the desired closed loop
crossover frequency of the design and LC corner
frequency of the output filter. In general, it is desirable to
keep the closed loop crossover frequency at less than 1/5
of the switching frequency. With high switching
frequencies such as the 500-kHz frequency of this design,
internal circuit limitations of the TPS54356 limit the
practical maximum crossover frequency to about 70 kHz.
Additionally, the capacitor type and value must be chosen
to work with the internal compensation network of the
TPS5435x family of dc/dc converters. To allow for
adequate phase gain in the compensation network, the LC
corner frequency should be about one decade or so below
the closed loop crossover frequency. This limits the
minimum capacitor value for the output filter to:
C
OUT(MIN)
(
1 K
2pƒCO
LOUT
)
2
(15)
19
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Where K is the frequency multiplier for the spread between
fLC and fCO. K should be between 5 and 15, typically 10 for
one decade difference. For a desired crossover of 20 kHz
and a 22-µH inductor, the minimum value for the output
capacitor is 288 µF. The selected output capacitor must be
rated for a voltage greater than the desired output voltage
plus one half the ripple voltage. Any derating amount must
also be included. The maximum RMS ripple current in the
output capacitor is given by equation 16:
VOUT VIN(MAX) VOUT
VIN(MAX) LOUT ƒsw (16)
ICOUT(RMS) 1 12
For a stable design, the closed loop crossover frequency
should be set less than one fifth of the switching frequency,
and the phase margin at crossover must be greater than
45 degrees. The general procedure outlined here
produces results consistent with these requirements
without going into great detail about the theory of loop
compensation.
In this case, the output filter LC corner frequency should be
selected to be near the first compensation zero frequency
as described by equation 17:
ƒ
LC
1
2p L
OUT
C2
ƒ
Z1
(17)
The calculated RMS ripple current is 156 mA in the
output capacitors.
Placement of the LC corner frequency at fZ1 is not critical,
it only needs to be close. For the design example, fLC = 2
kHz.
CHOOSING CAPACITOR VALUE
Solving for C2 using equation 18:
For this design example, a relatively large aluminum
electrolytic capacitor is combined with a smaller value
ceramic capacitor. This combination provides a stable high
performance design at a relatively low cost. Also, by
carefully choosing the capacitor values and ESRs, the
design can be tailored to complement the internal
compensation poles and zeros of the TPS54356.
These preconfigured poles and zeroes internal to the
TPS54356 limit the range of output filter configurations. A
variety of capacitor values and types of dielectric are
supported. There are a number of different ways to
calculate the output filter capacitor value and ESR to work
with the internal compensation network. This procedure
outlines a relatively simple procedure that produces good
results with an output filter consisting of a high ESR
dielectric capacitor in parallel with a low ESR ceramic
capacitor. Use of the SWIFT Designer Software for
designs with unusually high closed loop crossover
frequencies, low value, low ESR output capacitors such as
ceramics or if the designer is unsure about the design
procedure.
The TPS54356 contains a compensation network with the
following nominal characteristics:
ƒ
INT
ƒ
Z1
2.5 kHZ
ƒ
Z2
4.8 kHZ
ƒ
ƒ
1.7 kHZ
P1
95 kHZ
P2
125 kHZ
20
C2 4p 2ƒ2
1
L
Z1 OUT
(18)
The desired value for C2 is calculated as 184 µF. A close
standard value of 330 µF is chosen with a resulting LC
corner frequency of 1.9 kHz. As to be shown, this value is
not critical as long as it results in a corner frequency in the
vicinity of fZ1.
Next, when using a large ceramic capacitor in parallel with
a high ESR electrolytic capacitor, there is a pole in the
output filter that should be at fZ2 as shown in equation 19:
ƒ
P(ESR)
1
2pR
(C2ESR)
C5
ƒ
Z2
(19)
Now the actual C2 capacitor must be selected based on
the ESR and the value of capacitor C5 so that the above
equation is satisfied. In this example, the R(C2ESR)C5
product should be 3.18 10−5. From the available
capacitors, by choosing a Panasonic EEVFKOJ331XP
aluminum electrolytic capacitor with a nominal ESR of
0.34 Ω yields a calculated value for C5 of 98 µF. The
closest standard value is 100 µF. As the actual ESR of the
capacitor can vary by a large amount, this value also is not
critical.
The closed loop crossover frequency should be greater
than fLC and less than one fifth of the switching frequency.
Also, the crossover frequency should not exceed 70 kHz,
as the error amplifier may not provide the desired gain. As
stated previously, closed loop crossover frequencies
between 5 and 15 times fLC work well. For this design, the
crossover frequency can be estimated by:
ƒ
CO
1.125 10 3 ƒ
P(ESR)
ƒ
LC
(20)
This simplified equation is valid for this design because the
output filter capacitors are mixed technology. Compare
this result to the actual measured loop response plot of
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SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Figure 5. The measured closed loop crossover frequency
of 19.95 kHz differs from the calculated value because the
actual output filter capacitor component parameters
differed slightly from the specified data sheet values.
CAPACITOR ESR AND OUTPUT RIPPLE
The amount of output ripple voltage as specified in the
initial design parameters is determined by the
maximum ESR of the output capacitor and the input
ripple current. The output ripple voltage is the inductor
ripple current times the ESR of the output filter so the
maximum specified ESR as listed in the capacitor data
sheet is given by equation 21:
ESR (MAX) V IN(MAX) L
V
OUT
OUT
ƒsw 0.8
V IN(MAX) V
OUT
DV pp(MAX)
(21)
and the maximum ESR required is 33 mΩ. In this design,
the aluminum electrolytic capacitor has an ESR of 0.340
mΩ, but it is in parallel with an ultra low ESR ceramic
capacitor of 2 mΩ maximum. The measured output ripple
voltage for this design is approximately 4 mVp−p as shown
in Figure 10.
BIAS AND BOOTSTRAP CAPACITORS
Every TPS54356 design requires a bootstrap capacitor,
C3 and a bias capacitor, C4. The bootstrap capacitor must
be 0.1 µF. The bootstrap capacitor is located between the
PH pins and BOOT pin. The bias capacitor is connected
between the VBIAS pin and AGND. The value should be
1.0 µF. Both capacitors should be high quality ceramic
types with X7R or X5R grade dielectric for temperature
stability. They should be placed as close to the device
connection pins as possible.
LOW-SIDE FET
The TPS54356 is designed to operate using an external
low-side FET, and the LSG pin provides the gate drive
output. Connect the drain to the PH pin, the source to
PGND, and the gate to LSG. The TPS54356 gate drive
circuitry is designed to accommodate most common
n-channel FETs that are suitable for this application. The
SWIFT Designer Software can be used to calculate all the
design parameters for low-side FET selection. There are
some simplified guidelines that can be applied that
produce an acceptable solution in most designs.
The selected FET must meet the absolute maximum
ratings for the application:
D Drain-source voltage (VDSS) must be higher
than the maximum voltage at the PH pin,
which is VINMAX + 0.5 V.
D Gate-source voltage (VGSS) must be greater
than 8 V.
D Drain current (ld) must be greater than 1.1 x
IOUTMAX.
D Drain-source on resistance (RDSON) should be
as small as possible, less than 30 mW is
desirable. Lower values for RDSON result in
designs with higher efficiencies. It is
important to note that the low-side FET on
time is typically longer than the high-side
FET on time, so attention paid to low-side
FET parameters can make a marked
improvement in overall efficiency.
D Total gate charge (Qg) must be less than 50
nC. Again, lower Qg characteristics result in
higher efficiencies.
D Additionally, check that the device chosen is
capable of dissipating the power losses.
For this design, a Fairchild FDR6674A 30-V n-channel
MOSFET is used as the low-side FET. This particular FET
is specifically designed to be used as a low-side
synchronous rectifier.
POWER GOOD
The TPS54356 is provided with a power good output pin
PWRGD. This output is an open drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A
10-kΩ, pull-up resistor works well in this application. The
absolute maximum voltage is 6 V, so care must be taken
not to connect this pull-up resistor to VIN if the maximum
input voltage exceeds 6 V.
SNUBBER CIRCUIT
R10 and C11 of the application schematic in Figure 25
comprise a snubber circuit. The snubber is included to
reduce over-shoot and ringing on the phase node when the
internal high-side FET turns on. Since the frequency and
amplitude of the ringing depends to a large degree on
parasitic effects, it is best to choose these component
values based on actual measurements of any design
layout. See literature number SLVP100 for more detailed
information on snubber design.
21
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
+
+
Figure 26. 3.3-V Power Supply With Schottky Diode
Figure 26 shows an application where a clamp diode is
used in place of the low-side FET. The TPS54352−7
incorporates an integrated pull-down FET so that the
circuit remains operating in continuous mode during light
load operation. A 3-A, 40-V Schottky diode such as the
Motorola MBRS340T3 or equivalent is recommended.
See Figures 15−17 for efficiency data and switching
waveforms for this circuit.
+
+
Pull up to
3.3 V or 5 V
+
+
Figure 27. 3.3-V/1.8-V Power Supply with Sequencing
22
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
Figure 27 is an example of power supply sequencing using
a TPS54356 (U1) to generate an output of 3.3 V, and a
TPS54354 (U2) to generate a 1.8-V output. These output
voltages are typical I/O and core voltages for
microprocessors and FPGAs. In the circuit, the 3.3-V
supply is designed to power up first.
The PWRGD pin of U1 is tied to the ENA pin of U2 so that
the 1.8-V supply starts to ramp up after the 3.3-V supply is
within regulation. Figure 18 shows these start up
sequence waveforms.
Since the RT pin of U1 is floating, the SYNC pin is an
output. This synchronization signal is fed the SYNC pin of
U2. The RT pin of U2 has a 110-kΩ resistor to ground, and
the SYNC pin for this device acts as an input. The 1.8-V
supply operates synchronously with the 3.3-V supply and
their switching node rising edges are approximately 180
degrees out of phase allowing for a reduction in the input
voltage ripple. See Figure 19 for this wave form.
ALTERNATE OUTPUT FILTER DESIGNS
The previous design procedure example demonstrated a
technique to design a 3.3-V power supply using both
aluminum electrolytic and ceramic output filter capacitors.
Other types of output filter capacitors are supported by the
TPS5435x family of dc/dc converters. Figures 26−28 show
designs using other popular capacitor types.
In Figure 28, the TPS54356 shown with a single 100-µF
6-V POSCAP as the output filter capacitor. C10 is a high
frequency bypass capacitor and does not enter into the
design equations. The design procedure is similar to the
previous example except in the design of the output filter.
In the previous example, the output filter LC corner was set
at the first zero in the compensation network, while the
second compensation zero was used to counteract the
output filter pole caused by the interaction of the C2
capacitor ESR with C5. In this design example, the output
LC corner frequency is to be set at the second zero
frequency fZ2 of the internal compensation network,
approximately 5 kHz, while the first zero is used to provide
phase boost prior to the LC corner frequency.
+
+
Figure 28. 3.3-V Power Supply with Sanyo POSCAP Output Filter Capacitor
Inductor Selection
Using equation 12 and a KIND of 0.2, the minimum inductor
value required is 8.98 µH. The closest standard value, 10
µH is selected. RMS and peak inductor currents are the
same as calculated previously.
Capacitor Selection
With the inductor set at 10 µH and a desired corner
frequency of 5 kHz, the output capacitor value is given by:
C2 1
1
101 mF
4p2ƒ Z22 L out
4 p2 5000 2 10 5
Use 100 µF as the closest standard value.
Calculating the RMS ripple current in the output capacitor
using equation 16 yields 156 mA. The POSCAP
6TPC100M capacitor selected is rated for 1700 mA. See
the closed loop response curve for this design in Figure 20.
23
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
+
+
+
Figure 29. 3.3-V Power Supply with Panasonic SP Output Filter Capacitors
In Figure 29, the TPS54356 shown with two 180-µF 4-V
special polymer dielectric output filter capacitors(C2 and
C5). C10 is a high frequency bypass capacitor and does
not enter into the design equations. In the previous
example, the output LC corner frequency is to be set at the
second zero frequency fZ2 of the internal compensation
network, approximately 5 kHz, while the first zero is used
to provide phase boost prior to the LC corner frequency.
The special polymer electrolytic capacitors used in this
design require that the closed loop crossover frequency be
lowered due to the significantly lower ESR of this type of
capacitor.
Inductor Selection
The inductor is the same 10-µH value as the previous
example.
Capacitor Selection
To lower the closed loop crossover it is necessary to
reduce the LC corner frequency below 5 kHz. Using a
target value of 2500 Hz, the output capacitor value is given
by:
C2 1
1
405 mF
4p2ƒ Z22 L out
4 p2 2500 2 10 5
Use 2 x 180 µF = 360 µF as a combination of standard
values that is close to 405 µF.
The RMS ripple current in the output capacitor is the same
as before. The selected capacitors are each 3.3 A. See the
closed loop response curve for this design in Figure 21.
+
+
Figure 30. 3.3-V Power Supply with Sanyo OSCON Output Filter Capacitor
In Figure 30, the TPS54356 shown with a Sanyo OSCON
output filter capacitor(C2). C10 is a high frequency bypass
capacitor and does not enter into the design equations.
This design is identical to the previous example except that
a single OSCON capacitor of 330 µF is used for the
calculated value of 405 µF. Compare the closed loop
response for this design in Figure 22 to the closed loop
response in Figure 21. Note that there is only a slight
24
difference in the response and the general similarity in both
the gain and phase plots. This is the expected result for
these two similar output filters.
Many other additional output filter designs are possible.
Use the SWIFT Designer Software to generate other
designs or follow the general design procedures illustrated
in this application section.
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
800
800
600
500
TPS54355
400
TPS54354
300
TPS54353
TPS54352
200
100
IO > 0.5 A
0
200
TPS54356
600
500
400
300
TPS54354
TPS54353
200
TPS54352
100
Stop
5.0
TPS54352−6
Start
4.0
Stop
50
75
TJ = 25°C
8
7
6
5
4
3
100 125 150
0
5
TA − Free-Air Temperature − 5C
10
15
20
0
10
7.0
6.5
6.0
5.5
5.0
4.5
4.0
15
VI − Input Voltage − V
20
25
15
20
25
Figure 36
INTERNAL VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
0.8912
Vref − Internal Voltage Reference − V
PWRGD − Power Good Threshold − %
TJ = 25°C
7.5
Figure 37
5
VI − Input Voltage − V
98.0
10
1.0
0.9
25
POWER GOOD THRESHOLD
vs
JUNCTION TEMPERATURE
8.0
5
1.1
Figure 35
BIAS VOLTAGE
vs
INPUT VOLTAGE
0
1.2
VI − Input Voltage − V
Figure 34
700
1.3
TJ = 25°C
fS = 500 kHz
9
600
DISABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
Disabled Supply Current − mA
TPS54357
Enabled Supply Current − mA
VI − Input Voltage − V
6.0
500
Figure 33
10
25
400
Switching Frequency − kHz
ENABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
Start
0
300
Figure 32
6.5
3.5
−50 −25
100
VI − Input Voltage − V
VIN(UVLO) START AND STOP
vs
FREE-AIR TEMPERATURE
4.5
125
50
200
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 31
5.5
150
75
0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
175
IO < 0.1 A
VI − Input Voltage − V
VBIAS − Bias Voltage − V
225
TPS54357
TPS54355
700
RT Resistance − kW
TPS54356
Maximum Switching Frequency − kHz
Maximum Switching Frequency − kHz
TPS54357
700
RT RESISTANCE
vs
SWITCHING FREQUENCY
MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
97.5
97.0
96.5
96.0
−50 −25
0
25
50
75
100 125 150
TJ − Junction Temperature − 5C
Figure 38
VIN = 12 V
0.8910
0.8908
0.8906
0.8904
0.8902
0.8900
0.8898
−50 −25
0
25
50
75
100 125 150
TJ − Junction Temperature − 5C
Figure 39
25
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
ON RESISTANCE
vs
JUNCTION TEMPERATURE
CURRENT LIMIT
vs
INPUT VOLTAGE
PH VOLTAGE
vs
SINK CURRENT
2
150
6.0
VI = 12 V
IO = 0.5 A
TJ = 25°C
130
5.0
4.5
1.75
PH Voltage − V
On Resistance − mW
Current Limit − A
5.5
110
90
5.0
1.25
7.5
10.0
12.5
15.0
17.5
1
50
−50 −25
20.0
0
25
Figure 40
0.35
0.30
0.25
0.20
0.15
0.10
10
9
3.5
2.5
2
1.5
30
40
50
60
70
80
250
350
450
550
650
2
250
750
3
2.5
2
1.5
TPS54357
120
5
100
80
60
40
Figure 46
4
TPS54356
3
TPS54355
TPS54354
2
1
20
TPS54352
TPS54353
0
0
750
750
6
V O − Output Voltage − V
T A − Free-Air Temperature − ° C
4
3.5
650
MAXIMUM OUTPUT VOLTAGE
vs
INPUT VOLTAGE
TJ= 125°C
4.5
Switching Frequency − kHz
550
Figure 45
140
TPS54354
650
450
Switching Frequency − kHz
FREE-AIR TEMPERATURE
vs
MAXIMUM OUTPUT CURRENT
5
550
350
Figure 44
INTERNAL SLOW START TIME
vs
SWITCHING FREQUENCY
450
5
Switching Frequency − kHz
Figure 43
350
6
3
t − Time − ms
1
250
7
4
1
0
300
8
3
0.5
250
HICCUP TIME
vs
SWITCHING FREQUENCY
4
0
200
Figure 42
4.5
0.05
20
150
I CC − Sink Current − mA
Hiccup Time − ms
RSS = 2 kΩ
Power Good Delay − ms
Slow Start Capacitance − µ F
0.45
10
100
100 125 150
POWER GOOD DELAY
vs
SWITCHING FREQUENCY
0.50
0
75
Figure 41
SLOW START CAPACITANCE
vs
TIME
0.40
50
TJ − Junction Temperature − 5C
VI − Input Voltage − V
Slow Start Time − ms
VI = 12 V
70
4.0
26
VI = 4.5 V
1.50
0
0.5
1
1.5
2
2.5
I O − Output Current − A
Figure 47
3
3.5
0
5
10
15
V I − Input Voltage − V
Figure 48
20
25
www.ti.com
SLVS519A − MAY 2004 − REVISED OCTOBER 2004
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
PD − Power Dissipation − W
2.5
2
θJA = 42.1°C/W
1.5
1
θJA = 191.9°C/W
0.5
0
25
45
65
85
105
125
TA − Free-Air Temperature − °C
Figure 49
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54352PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54352
TPS54352PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54352
TPS54352PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54352
TPS54352PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54352
TPS54353PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54353
TPS54353PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54353
TPS54353PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54353
TPS54353PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54353
TPS54354PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54354
TPS54354PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54354
TPS54354PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54354
TPS54354PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54354
TPS54355PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54355
TPS54355PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54355
TPS54355PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54355
TPS54356PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54356
TPS54356PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54356
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54356PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54356
TPS54356PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54356
TPS54357PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54357
TPS54357PWPG4
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54357
TPS54357PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54357
TPS54357PWPRG4
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54357
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54354, TPS54356 :
• Enhanced Product: TPS54354-EP, TPS54356-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS54352PWPR
HTSSOP
PWP
16
2000
330.0
12.4
TPS54353PWPR
HTSSOP
PWP
16
2000
330.0
TPS54354PWPR
HTSSOP
PWP
16
2000
330.0
TPS54355PWPR
HTSSOP
PWP
16
2000
TPS54356PWPR
HTSSOP
PWP
16
TPS54357PWPR
HTSSOP
PWP
16
6.9
5.6
1.6
8.0
12.0
Q1
12.4
6.9
5.6
1.6
8.0
12.0
Q1
12.4
6.9
5.6
1.6
8.0
12.0
Q1
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54352PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
TPS54353PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
TPS54354PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
TPS54355PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
TPS54356PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
TPS54357PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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