Video and Image Processing Suite Release Notes

Video and Image Processing Suite Release Notes
Video and Image Processing Suite
Release Notes
RN-1094
2017.05.08
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Contents
Contents
1 Video and Image Processing Suite Release Notes............................................................ 3
1.1 Video and Image Processing Suite v17.0....................................................................3
1.2 Video and Image Processing Suite v16.1....................................................................4
1.3 Video and Image Processing Suite v16.0....................................................................5
Video and Image Processing Suite Release Notes
2
1 Video and Image Processing Suite Release Notes
1 Video and Image Processing Suite Release Notes
If a release note is not available for a specific IP core version, the IP core has no
changes in that version. Information on the latest update releases is in the Intel
Quartus Prime Design Suite Update Release Notes.
Attention:
The following IP cores are no longer supported in versions 17.0 and later:
•
2D FIR Filter
•
Alpha Blending Mixer
•
Chroma Resampler
•
Color Space Converter
•
Color Plane Sequencer
•
Control Synchronizer
•
Deinterlacer
•
Frame Buffer
•
Frame Reader
•
Gamma Corrector
•
Interlacer
•
Switch
Intel recommends that you use the upgraded versions of these IP cores.
Related Links
Intel Quartus Prime Design Suite Update Release Notes
1.1 Video and Image Processing Suite v17.0
Table 1.
v17.0 May 2017
Description
Added a new IP core: Configurable Guard Bands IP core. This IP core supports pixels in
parallel and run-time control.
Added device support for Intel Cyclone 10 LP and Cyclone 10 GX devices.
Impact
These changes are optional.
If you do not upgrade your
IP core, it does not have
these new features.
Removed the following IP cores. These IP cores are no longer supported in Quartus Prime
versions 17.0 and later.
• 2D FIR Filter
• Alpha Blending Mixer
• Chroma Resampler
• Color Space Converter
continued...
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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customers are advised to obtain the latest version of device specifications before relying on any published
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1 Video and Image Processing Suite Release Notes
Description
•
•
•
•
•
•
•
Impact
Color Plane Sequencer
Deinterlacer
Frame Buffer
Frame Reader
Gamma Corrector
Interlacer
Switch
Added new parameters for the Chroma Resampler II IP core:
• Enable vertical luma adaptive resampling
• Vertical chroma siting
• Variable 3 color interface
• Enable 4:2:0 input
• Enable 4:2:0 output
Removed these parameters for the Deinterlacer II IP core:
• How user packets are handled: Pass all user packets through to the output
(packets will always pass through)
• Enable embedded chroma resamplers
Changed Cadence Detect On register to Cadence Detect and advanced tuning
registers On register for the Deinterlacer II IP core. This updated register enables the
cadence detection feature and (if configured) the video over film feature together with all
the motion and cadence/VOF tuning registers.
Removed edge sharpening feature for the Scaler II IP core.
Related Links
•
Introduction to Intel FPGA IP Cores
•
Video and Image Processing Suite User Guide
•
Errata for the Video and Image Processing Suite in the Knowledge Base
1.2 Video and Image Processing Suite v16.1
Table 2.
v16.1 October 2016
Description
Added the following new IP cores for 16.1 release:
• 2D FIR Filter II
• Chroma Resampler II
• Color Plane Sequencer II
• Gamma Corrector II
• Interlacer II
All these IP cores support pixels in parallel and run-time control.
Impact
These changes are optional.
If you do not upgrade your
IP core, it does not have
these new features.
Removed the Broadcast Deinterlacer IP core and merged the features into the Deinterlacer
II IP core. If you were using the Broadcast Deinterlacer IP core versions 15.1 or 16.0, Qsys
will automatically upgrade your design to the Deinterlacer II version 16.1 with the same
configuration.
Mixer II IP core
• Updated alpha stream information for Mixer II IP core.
• When you enable alpha stream, the LSB is in Alpha value and the control packets are
composed of all symbols including Alpha.
Clocked Video Interface IP core
continued...
Video and Image Processing Suite Release Notes
4
1 Video and Image Processing Suite Release Notes
Description
•
Impact
Added new parameters for Clocked Video Input II IP core:
— Enable matching data packet to control by clipping:
Turning on this parameter clips the input video frame to match the resolution
sent in control packet.
— Enable matching data packet to control by padding:
Turning on this parameter pads the incoming frame if it is smaller and/or shorter
than the resolution specified in the control packet.
— Overflow handling:
Turning on this parameter ends the current frame (with dummy pixel data) based on
the resolution specified in the control packet if overflow happens.
•
Added new signals Clocked Video Input II IP core: Clipping and Padding.
•
Updated information about the Status register Clocked Video Input II IP core to
include bits to support clipping and padding features.
Added new parameter for Clocked Video Output II IP core:
— Low latency mode:
Setting this parameter to 1 enables the IP core to start timing for a new frame
immediately.
•
Related Links
•
Introduction to Intel FPGA IP Cores
•
Video and Image Processing Suite User Guide
•
Errata for the Video and Image Processing Suite in the Knowledge Base
1.3 Video and Image Processing Suite v16.0
Table 3.
v16.0 May 2016
Description
Impact
Avalon-ST Video Stream Cleaner IP core
• Added a new IP core. The Avalon-ST Video Stream Cleaner IP Core removes and repairs
non-ideal sequences and error cases present in the incoming data stream to produce a
compliant output stream.
These changes are optional.
If you do not upgrade your
IP core, it does not have
these new features.
Frame Buffer II IP core
• Added new Frame Buffer II IP core parameters:
— Enable use of fixed inter-buffer offset
— Inter-buffer offset
— Module is Frame Reader only
— Module is Frame Writer only
Mixer II IP core
continued...
Video and Image Processing Suite Release Notes
5
1 Video and Image Processing Suite Release Notes
Description
•
•
Impact
Added new or updated the following Mixer II IP core parameters:
— Number of inputs
— Alpha Blending Enable
— Layer Position Enable
— Register Avalon-ST ready signals
— Uniform values
— Number of pixels transmitted in 1 clock cycle
— Alpha Input Stream Enable
— 4:2:2 support
— How user packets are handled
Removed these Mixer II IP core parameters:
— Number of color planes
— Run-time control
— Output format
Clocked Video Interface IP core
• Added new or updated these Clocked Video Input II IP core signals:
— dout_empty
— vid_locked (updated)
— vid_datavalid (updated)
— vid_color_encoding
— vid_bit_width
— vid_total_sample_count
— vid_total_line_count
•
Added a new register, Color Pattern, for the Clocked Video Input II IP core.
•
Removed the Accept synchronization outputs parameter and the related signals
from the Clocked Video Output II IP core.
— vcoclk_div
— sof
— sof_locked
— vid_sof
— vid_sof_locked
Switch II IP core
• Added a new register: Din Consume Mode Enable.
Related Links
•
Introduction to Intel FPGA IP Cores
•
Video and Image Processing Suite User Guide
•
Errata for the Video and Image Processing Suite in the Knowledge Base
Video and Image Processing Suite Release Notes
6
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