USB 2.0 SD/MMC Card Reader Controller Datasheet - Quick-teck

USB 2.0 SD/MMC Card Reader Controller Datasheet - Quick-teck
Genesys Logic, Inc.
GL823
USB 2.0 SD/MMC Card Reader
Controller
Datasheet
Revision 1.03
Jun. 28, 2010
GL823 Datasheet
Copyright
Copyright © 2010 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any
form or by any means without prior written consent of Genesys Logic, Inc.
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Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein.
Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and
any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise,
regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual
property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any
direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys
Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel : (886-2) 8913-1888
Fax : (886-2) 6629-6168
http://www.genesyslogic.com
©2010 Genesys Logic, Inc. - All rights reserved.
Page 2
GL823 Datasheet
Revision History
Revision
Date
Description
1.00
09/18/2009
First formal release
1.01
12/15/2009
Add QFN 24 package
1.02
03/11/2010
Remove USB DP/DM port swap feature, p.7 & p.11
Modify Ch6 Package Dimension, p.19
Modify Ch7 Ordering Information, p.21
1.03
06/28/2010
Add Table 2.1: Product Difference Overview, p.7
©2010 Genesys Logic, Inc. - All rights reserved.
Page 3
GL823 Datasheet
Table of Contents
CHAPTER 1
GENERAL DESCRIPTION...................................................................... 6
CHAPTER 2
FEATURES ................................................................................................. 7
CHAPTER 3
PIN ASSIGNMENT.................................................................................... 8
3.1 SSOP-24 Pinout ............................................................................................................ 8
3.2 QFN-24 Pinout .............................................................................................................. 9
3.3 Pin List/Descriptions .................................................................................................. 11
CHAPTER 4
BLOCK DIAGRAM................................................................................. 13
4.1 OCCS USB PHY......................................................................................................... 13
4.2 SIE................................................................................................................................ 13
4.3 EPFIFO ....................................................................................................................... 13
4.4 MCU............................................................................................................................. 13
4.5 MHE............................................................................................................................. 14
4.6 Regulator ..................................................................................................................... 14
4.7 PMOS........................................................................................................................... 14
CHAPTER 5
ELECTRICAL CHARACTERISTICS .................................................. 15
5.1 Absolute Maximum Ratings ...................................................................................... 15
5.2 Operating Conditions................................................................................................. 15
5.3 DC Characteristics ..................................................................................................... 15
5.4 5V to 3.3V Regulator Characteristics ....................................................................... 16
5.5 PMOS Characteristics................................................................................................ 17
5.6 AC Characteristics ..................................................................................................... 17
5.6.1 Reset Timing........................................................................................................ 17
5.6.2 SD/MMC Card Clock Frequency ..................................................................... 18
CHAPTER 6
PACKAGE DIMENSION.......................................................................... 19
CHAPTER 7
ORDERING INFORMATION.................................................................. 21
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Page 4
GL823 Datasheet
List of Figures
Figure 3.1 - 24 Pin SSOP Pin out Diagram ............................................................................ 8
Figure 3.2 - 24 Pin QFN (A) Pin out Diagram ....................................................................... 9
Figure 3.3 - 24 Pin QFN (B) Pin out Diagram ..................................................................... 10
Figure 4.1 - Functional Block Diagram................................................................................ 13
Figure 5.1 - 5V to 3.3V Regulator Architecture .................................................................. 16
Figure 5.2 - Embedded PMOS Switch Architecture........................................................... 17
Figure 5.3 - Timing Diagram of Reset Width ...................................................................... 17
Figure 5.4 - Timing Diagram of Power Good to USB Command Receive Ready ............ 18
Figure 6.1 - SSOP 24 Pin Package ........................................................................................ 19
Figure 6.2 - QFN 24 Pin Package.......................................................................................... 20
List of Tables
Table 2.1 - Product Difference Overview............................................................................... 7
Table 3.1 - GL823 Pin List/Descriptions .............................................................................. 11
Table 5.1 - Absolute Maximum Ratings............................................................................... 15
Table 5.2 - Operating Conditions.......................................................................................... 15
Table 5.3 - DC Characteristics .............................................................................................. 15
Table 5.4 - Regulator Output Current ................................................................................. 16
Table 5.5 - PMOS I-V Table.................................................................................................. 17
Table 5.6 - Reset Timing ........................................................................................................ 18
Table 5.7 - SD/MMC Card Clock Frequency ...................................................................... 18
Table 7.1 - Ordering Information ......................................................................................... 21
©2010 Genesys Logic, Inc. - All rights reserved.
Page 5
GL823 Datasheet
CHAPTER 1
GENERAL DESCRIPTION
The GL823 is a USB 2.0 SD/MMC Flash Card Reader single chip. It supports USB 2.0 high-speed transmission
to Secure DigitalTM (SD), SDHC, SDXC, miniSD, microSD (T-Flash), MultiMediaCardTM (MMC), RS-MMC,
MMCmicro, MMCmobile on one chip. As a single chip solution for USB 2.0 flash card reader, the GL823
complies with Universal Serial Bus specification rev. 2.0, USB Storage Class specification ver.1.0, and
SD/MMC card interface specification.
The GL823 integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best data
transfer performance between USB and flash card interfaces. Its’ pin assignment design fits to card sockets to
provide easier PCB layout. Inside the chip, it integrates 5V to 3.3V and 3.3V to 1.8V regulators and power
MOSFETs and it enables the function of on-chip clock source (OCCS) which means no external 12MHz XTAL
is needed and that effectively reduces the total BOM cost.
©2010 Genesys Logic, Inc. - All rights reserved.
Page 6
GL823 Datasheet
CHAPTER 2
FEATURES
USB specification compliance
- Comply with 480Mbps Universal Serial Bus specification rev. 2.0
- Comply with USB Storage Class specification rev. 1.0
Support one device address and up to four endpoints: Control (0)/ Bulk Read (1)/ Bulk Write (2)/Interrupt
(3)
Integrated USB building blocks
- USB2.0 transceiver macro (UTM), Serial Interface Engine (SIE), Build-in power-on reset (POR) and
low-voltage detector (LVD)
Embedded 8051 micro-controller
- Operate @ 60 MHz clock, 12 clocks per instruction cycle
- Embedded mask ROM and internal SRAM
TM
TM
Secure Digital (SD) and MultiMediaCard (MMC)
-
Support SD specification v1.0 / v1.1 / v2.0/ SDHC (Up to 32GB)
Compatible with SDXC (Up to 2TB)
Support MMC specification v3.x / v4.0 / v4.1 / v4.2.
x1 / x4 bit data bus
On chip clock source and no need of 12MHz Crystal Clock input.
On-Chip 5V to 3.3V and 3.3V to 1.8V regulators
Support 5V to 3.3V Band Gap Regulator for stable voltage supply
Provide Over-Current protection mechanism for safety power supply
On-Chip power MOSFETs for supplying flash media card power
Support Power Saving mode/ Selective suspend mode for better power management.
Only available in QFN-24(A) package.
Support external serial EEPROM interface for the flexibility to load the vendor information and system
options
Operating system supported: Windows 7/Vista32&64/XP/2000/Me/98/98SE, Mac OS 9.X/10.X, Linux
Kernel 2.4.X/2.6.X
- Pass Windows Vista/ Windows 7 (Submission ID: 1355289)
USB-IF Logo (Submission TID: 40000940)
Package available in 24 pin SSOP (209 mil) and 24 pin QFN (4x4 mm)
Table 2.1 - Product Difference Overview
Package Type
Version
Power Source
Power Management
SSOP 24
04, 06, …N
5V
Not Support
QFN-24 (A)
04, 06, …N
3.3V
Power Saving Mode/ Selective Suspend Mode
QFN-24 (B)
05, 07, …N+1
5V
Not Support
©2010 Genesys Logic, Inc. - All rights reserved.
Page 7
GL823 Datasheet
CHAPTER 3
PIN ASSIGNMENT
3.1 SSOP-24 Pinout
Figure 3.1 - 24 Pin SSOP Pin out Diagram
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Page 8
GL823 Datasheet
D3
GPIO9
SD_CMD
GPIO8
PMOS
DVDD
18
17
16
15
14
13
3.2 QFN-24 Pinout
GPIO3
22
GL823
9
SD_CDZ
DVDD
23
QFN-24 (A)
8
SD_WP
GND
24
7
RSTZ
6
D1
AVDD
10
5
21
RREF
TEST
4
D0
DP
11
3
20
DM
LED
2
SD_CLK
SDA
12
1
19
SCL
D2
Figure 3.2 - 24 Pin QFN (A) Pin out Diagram
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Page 9
SD_CLK
6
AVDD
13
GPIO6
5
RREF
14
DVDD
4
DP
15
PMOS
3
DM
16
SD_CMD
2
SDA
17
1
SCL
18
D3
GL823 Datasheet
Figure 3.3 - 24 Pin QFN (B) Pin out Diagram
©2010 Genesys Logic, Inc. - All rights reserved.
Page 10
GL823 Datasheet
3.3 Pin List/Descriptions
Table 3.1 - GL823 Pin List/Descriptions
Pin Name
SSOP
24 pin
QFN
24 pin (A)
QFN
Type
24 pin (B)
Description
Power/Ground
DVDD
6, 14
13,23
15,23
P
3.3V Digital power
AVDD
21
6
6
P
3.3V Analog power
VBUS
15
-
24
P
5V Power source
GND
5, 22
24
7
P
PMOS
7
14
16
P
Ground
Card power: 300mA, Drain-Source
On-Resistance (RDS)= 1 (Max.) @3.3V, 25°C
G1
-
Die Pad
Die Pad
P
Ω
Ground
USB PHY Interface
DM
18
3
3
A
USB D-
DP
19
4
4
A
RREF
20
5
5
A
USB D+
USB reference resistor. This pin is used to
control the level of USB signal. A 680Ohm, 1%
resistor is recommended to be laid between
RREF and GND
SD Card Interface
SD Write Protect signal
9
I, pu 0: Write enable
1: Write protect
SD/MMC Card Detect signal
10
I, pu 0: Card insert
1: No card
SD_WP
24
8
SD_CDZ
1
9
SD_CLK
4
12
13
SD_CMD
8
16
17
D[3:0]
O
SD/MMC Clock signal
B, pu SD/MMC Command signal
9, 10, 2, 3 18,19,10,11 18,19,11,12 B, pu SD/MMC Data signal
Others
RSTZ
23
7
8
I, pu This pin is used to reset the chip, active-low
TEST
12
21
21
This pin is used to test the chip.
I, pd 0: Normal operation
1: Test mode
GPIO3
13
22
22
B
Hardware configuration
GPIO6
5
-
14
B
Hardware configuration
GPIO8
-
15
-
B
Hardware configuration
GPIO9
-
17
-
B
Hardware configuration
LED
11
20
20
O
Power & Access LED
SCL
16
1
1
B
Serial EEPROM Clock signal
SDA
17
2
2
B
Serial EEPROM Data signal
Notation:
©2010 Genesys Logic, Inc. - All rights reserved.
Page 11
GL823 Datasheet
Type
O
I
B
pu
pd
P
A
Output
Input
Bi-directional
Internal pull-up when input
Internal pull-down when input
Power / Ground
Analog
Note:
1. AVDD connect to DVDD through Bead
2. All I/O pads are Schmitt trigger and 8mA drive current
©2010 Genesys Logic, Inc. - All rights reserved.
Page 12
GL823 Datasheet
CHAPTER 4
BLOCK DIAGRAM
Figure 4.1 - Functional Block Diagram
4.1 OCCS USB PHY
The USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling,
and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. On
chip clock source and no need of 12MHz Crystal Clock input.
4.2 SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to handle USB packets and transactions.
4.3 EPFIFO
Endpoint FIFO includes Control FIFO (FIFO0), interrupt FIFO (FIFO3), Bulk In/Out FIFO (BULKFIFOA/B)
Control FIFO
FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.
Interrupt FIFO
64-byte depth FIFO of endpoint 3 for status interrupt
Bulk In/Out FIFO It can be in the TX mode or RX mode:
1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.
2. It can be directly accessed by uC
4.4 MCU
8051 micro-controller inside.
8051 Core
Compliant with Intel 8051 high speed micro-controller
ROM
FW code on ROM
SRAM
Internal RAM area for MCU access
©2010 Genesys Logic, Inc. - All rights reserved.
Page 13
GL823 Datasheet
4.5 MHE
MIF
MCFIFO
Media Interface: SD/MMC
It can access by MCU for memory card short data packet.
4.6 Regulator
5V to 3.3V
3.3V to 1.8V
Band Gap Regulator for stable voltage supply for USB PHY, PMOS.
When Power source is 3.3V, the 5V to 3.3V regulator will be disabled.
For core logic and internal memory.
4.7 PMOS
On-Chip power MOSFETs provide Over-Current protection mechanism.
©2010 Genesys Logic, Inc. - All rights reserved.
Page 14
GL823 Datasheet
CHAPTER 5
ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
Table 5.1 - Absolute Maximum Ratings
Parameter
Value
Storage Temperature
-65°C to +150 °C
Ambient Temperature
-40°C to +80 °C
5.2 Operating Conditions
Table 5.2 - Operating Conditions
Parameter
Value
Ta (Ambient Temperature Under Bias)
0°C to 70°C
Supply Voltage
SSOP-24 & QFN-24(B)
4.75V to 5.25V
QFN-24(A)
3.14V to 3.46V
Ground Voltage
0V
5.3 DC Characteristics
Table 5.3 - DC Characteristics
Symbol
V5
V3.3
Parameter
Supply Voltage for SSOP-24 &
QFN-24(B)
Supply Voltage for QFN-24(A)
Condition
Min.
Typ.
Max.
Unit
5V power source
4.75
-
5.25
V
3.3V power source
3.14
-
3.46
V
VIH
Input High Voltage
2.0
-
-
V
VIL
Input Low Voltage
-
-
0.4
V
II
Input Leakage Current
0 < VIN < DVDD
-10
-
10
µA
VOH
Output High Voltage
DVDD = 3.3V
3.0
-
-
V
VOL
Output Low Voltage
-
-
0.4
V
IOH
Output Current High
-
8
-
mA
IOL
Output Current Low
-
8
-
mA
CIN
Input Pin Capacitance
-
5
-
pF
-
33
-
mA
-
16
-
mA
-
38
-
mA
-
11
-
mA
-
-
450
µA
-
-
300
µA
INORMAL
IRESET
ISUS
AVDD Supply current
DVDD Supply current
AVDD Reset current
5V/3.3V power source
5V/3.3V power source
DVDD Reset current
SSOP-24 &
QFN-24(B) 1.5K pull-up included
Suspend current
QFN-24(A)
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Page 15
GL823 Datasheet
IPS
Rpu
Rpd
SSOP-24 &
QFN-24(B)
QFN-24(A)
-
-
200
µA
-
-
30
µA
Reset Pad pull-up
-
10
-
SD_CMD/GPIO Pad pull-up
-
20
-
SD_DATA Pad pull-up
-
50
-
SD_CMD/GPIO Pad pull-down
-
20
-
SD_DATA Pad pull-down
-
50
-
Power saving
current
Ω
KΩ
KΩ
KΩ
KΩ
K
5.4 5V to 3.3V Regulator Characteristics
Table 5.4 - Regulator Output Current
Parameters
Description
Test Conditions
Min. Typ. Max. Unit
Iq
Quiescent current
No loading
-
18
-
uA
Io
Output driving capability
DVDD > 3.2V
-
-
350
mA
Io_0mA
DVDD without loading
-
3.38
-
V
Io_200mA
DVDD with 200mA loading
-
3.31
-
V
Io_350mA
DVDD with 350mA loading
-
3.24
-
V
( VBUS = 5V, Temperature 25 °C)
Figure 5.1 - 5V to 3.3V Regulator Architecture
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Page 16
GL823 Datasheet
5.5 PMOS Characteristics
Table 5.5 - PMOS I-V Table
Driving Loading (I)
PMOS Output Voltage
100mA
3.21V
200mA
3.12V
300mA
3.01V
330mA
Turn Off *
( DVDD = 3.3V, Temperature 25 °C)
Note:
PMOS turn off by over-current protection mechanism when loading over 330mA.
Figure 5.2 - Embedded PMOS Switch Architecture
5.6 AC Characteristics
5.6.1 Reset Timing
Figure 5.3 - Timing Diagram of Reset Width
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Page 17
GL823 Datasheet
Figure 5.4 - Timing Diagram of Power Good to USB Command Receive Ready
Table 5.6 - Reset Timing
Parameter
Description
Min.
Unit
Trst
Chip reset sense timing width
2
us
T1
AVDD power up to reset de-assert
500
us
T2
Reset de-assert to respond USB command ready
42
ms
5.6.2 SD/MMC Card Clock Frequency
Table 5.7 - SD/MMC Card Clock Frequency
Parameter
Description
Typ.
Unit
FID
Clock frequency Identification Mode
387
KHz
FDS
Clock frequency Default Speed Mode
24
MHz
FHS
Clock frequency High Speed Mode
48
MHz
©2010 Genesys Logic, Inc. - All rights reserved.
Page 18
GL823 Datasheet
CHAPTER 6 PACKAGE DIMENSION
Internal No.
Green Package
+ AU Wire
GL823
Version No.
AAAAAAAGAA
YWWXXXXXXXX
Date Code
Lot Code
Figure 6.1 - SSOP 24 Pin Package
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Page 19
GL823 Datasheet
GL823
Version
AAAAAAA No.
YWWXXXX
Internal No.
Date Code Lot Code
Figure 6.2 - QFN 24 Pin Package
©2010 Genesys Logic, Inc. - All rights reserved.
Page 20
GL823 Datasheet
CHAPTER 7 ORDERING INFORMATION
Table 7.1 - Ordering Information
Part Number
Package
Green/Wire Material
Version
Status
GL823-HGGXX
SSOP 24
Green Package + AU Wire
XX
Available
GL823-OGG*XX
QFN 24
Green Package + AU Wire
XX
Available
*The marking of "OGG" will not be shown on the IC due to QFN 24 package size limitation.
©2010 Genesys Logic, Inc. - All rights reserved.
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