204 pin Unbuffered DDR3 SO-DIMM
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Based on 128Mx8 (2GB) DDR3 SDRAM C-Die
Features
•Performance:
Speed Sort
DIMM CAS Latency
PC3-8500
PC3-10600
-BE
-CG
Unit
7
9
533
667
tck – Clock Cycle
1.875
1.5
ns
fDQ – DQ Burst Frequency
1066
1333
Mbps
fck – Clock Frequency
MHz
• 204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 2GB: 256Mx64 Un-buffered DDR3 SO-DIMM based on 128Mx8
DDR3 SDRAM A-Die devices.
• Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
• VDD = VDDQ = 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Gold contacts
• Serial Presence Detect
• Programmable Operation:
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/10/2 (row/column/rank) Addressing for 2GB
• Extended operating temperature rage
• Auto Self-Refresh option
• 2GB: SDRAMs are in 78-ball BGA Package
• RoHS compliance
Description
M2N2G64CB8HC5N and M2N2G64CB8HC9N are un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Small Outline
Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 256Mx64 (2GB) high-speed memory array. Modules use sixteen
128Mx8 (2GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as
reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR3 SODIMMs
provide a high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
03/2010
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Ordering Information
Part Number
Speed
M2N2G64CB8HC5N -BE
DDR3-1066
PC3-8500 533MHz (1.875ns @ CL = 7)
M2N2G64CB8HC5N -CG
DDR3-1333
PC3-10600 667MHz (1.500ns @ CL = 9)
M2N2G64CB8HC9N -BE
DDR3-1066
PC3-8500 533MHz (1.875ns @ CL = 7)
M2N2G64CB8HC9N -CG
DDR3-1333
PC3-10600 667MHz (1.500ns @ CL = 9)
Organization
Power
Leads
256M x 64
1.5V
Gold
256M x 64
1.5V
Gold
Note
Pin Description
CK0, CK1
Clock Inputs, positive line
DQ0-DQ63
, 
Clock Inputs, negative line
DQS0-DQS7
Data strobes
Clock Enable
-
Data strobes complement
CKE0, CKE1

Row Address Strobe

Column Address Strobe

, 
A0-A9, A11, A13
DM0-DM7
Data input/output
Data Masks

Temperature event pin
Write Enable

Reset pin
Chip Selects
VREFDQ , VREFCA
Address Inputs
A10/AP
Address Input/Auto-Precharge
A12/
VDDSPD
Input/Output Reference
SPD and Temp sensor power
SA0, SA1
Serial Presence Detect Address Inputs
Address Input/Burst Chop
Vtt
Termination voltage
BA0-BA2
SDRAM Bank Address Inputs
VSS
Ground
ODT0, ODT1
Active termination control lines
VDD
Core and I/O power
SCL
Serial Presence Detect Clock Input
NC
No Connect
SDA
Serial Presence Detect Data input/output
REV 1.2
03/2010
2
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
2GB DDR3 SDRAM SODIMM Pinout
Pin
Front
Pin
Back
Pin
Front
Pin
Front
Pin
1
VREFDQ
3
VSS
54
VSS
56
DQ28
105
VDD
107
A10/AP
155
VSS
156
VSS
157
DQ42
158
DQ46
5
DQ0
DQ24
58
DQ29
109

159
DQ43
160
DQ47
7
DQ1
9
VSS
59
DQ25
60
61
VSS
62
VSS

112
VDD
161
VSS
162
VSS
114

163
DQ48
164
DQ52
11
DM0
12
DQS0
63
DM3
64
DQS3
115
116
ODT0
165
DQ49
166
DQ53
13
VSS
15
DQ2
14
VSS
65
VSS
16
DQ6
67
DQ26
66
VSS
117
VDD
68
DQ30
119
A13/NC
118
VDD
167
VSS
168
VSS
120
ODT1
169

170
DM6
17
19
DQ3
18
DQ7
69
VSS
20
VSS
71
DQ27
70
DQ31
121

VSS
72
VSS
123
VDD
122
NC
171
DQS6
172
VSS
124
VDD
173
VSS
174
DQ54
21
DQ8
22
DQ12
73
CKE0
74
CKE1
125
NC
126
VREFCA
175
DQ50
176
DQ55
23
DQ9
24
25
VSS
26
DQ13
75
VDD
76
VDD
VSS
77
NC
78
NC
127
VSS
128
VSS
177
DQ51
178
VSS
129
DQ32
130
DQ36
179
VSS
180
DQ60
27

28
DM1
79
BA2
80
NC
131
DQ33
132
DQ37
181
DQ56
182
DQ61
29
31
DQS1
30

81
VDD
VSS
32
VSS
83
A12/
82
VDD
133
VSS
134
VSS
183
DQ57
184
VSS
84
A11
135

136
DM4
185
VSS
186

33
DQ10
34
DQ14
85
A9
35
DQ11
36
DQ15
87
VDD
86
A7
137
DQS4
138
VSS
187
DM7
188
DQS7
88
VDD
139
VSS
140
DQ38
189
VSS
190
VSS
37
VSS
38
VSS
89
A8
90
A6
141
DQ34
142
DQ39
191
DQ58
192
DQ62
39
DQ16
40
DQ20
41
DQ17
42
DQ21
91
A5
92
A4
143
DQ35
144
VSS
193
DQ59
194
DQ63
93
VDD
94
VDD
145
VSS
146
DQ44
195
VSS
196
VSS
43
VSS
44
VSS
95
A3
96
A2
147
DQ40
148
DQ45
197
SA0
198

45

47
DQS2
46
DM2
97
A1
98
A0
149
DQ41
150
VSS
199
VDDSPD
200
SDA
48
VSS
99
VDD
100
VDD
151
VSS
152
 201
SA1
202
SCL
49
51
VSS
50
DQ22
101
CK0
102
CK1
153
DM5
154
DQS5
Vtt
204
Vtt
DQ18
52
DQ23
103

104

REV 1.2
03/2010
Back
Pin
Front
Pin
2
VSS
53
DQ19
4
DQ4
55
VSS
6
DQ5
57
8
VSS
10

Back
Pin
106
VDD
108
BA1
BA0
110
111
VDD
113


203
Back
3
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1
, 
Input
Cross
point
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE0, CKE1
Input
Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
, 
Input
Active
Low
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 
, , 
Input
Active
Low
When sampled at the positive rising edge of CK and falling edge of , signals , , 
define the operation to be executed by the SDRAM.
ODT0, ODT1
Input
Active
High
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
DM0 – DM7
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 Signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.
DQS0 – DQS7
 – 
I/O
Cross
point
BA0, BA1, BA2
Input
-
Selects which DDR3 SDRAM internal bank of four or eight is activated.
Input
-
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
A0 – A9
A10/AP
A11
A12/
A13
DQ0 – DQ63
Input
-
Data Input/Output pins.
VDD, VDDSPD, VSS
Supply
-
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ, VREFCA
Supply
-
Reference voltage for SSTL15 inputs
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull
up.
SCL
Input
-
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0 – SA2
Input
-
Address pins used to select the Serial Presence Detect and Temp sensor base address.

Output
-
The  pin is reserved for use to flag critical module temperature.

Input
-
This signal resets the DDR3 SDRAM
REV 1.2
03/2010
4
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Functional Block Diagram
D0
DQS

DM
DQ[0:7]
240ohm
+/-1%
ZQ
D2




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS2

DM2
DQ[16:23]
SCL
SA0
SA1
SCL
A0
A1
A2
D9
DQS

DM
DQ[0:7]
DQS

DM
DQ[0:7]
240ohm
+/-1%
DQS

DM
DQ[0:7]
ZQ
D8
240ohm
+/-1%
DQS

DM
DQ[0:7]
ZQ
D10
Vtt
VDDSPD
VREFCA
VREFDQ
VDD
VSS
CK0
CK1
Temp Sensor
SDA


SCL
SA0
SA1
SCL
A0
A1
A2
SPD


CKE0
CKE1


ODT0
ODT1


SDA
WP
Notes :
1. DQ wiring may differ from that shown however, DQ, DM,
DQS, and relationships are maintained as shown.
REV 1.2
03/2010
240ohm
+/-1%
ZQ
D14
240ohm
+/-1%
ZQ
D15
240ohm
+/-1%
ZQ
D13
240ohm
+/-1%
ZQ




CK

CKE
ODT
A[0:13]/BA[0:2]
D12
DQS4

DM4
DQ[32:39]
DQS

DM
DQ[0:7]
240ohm
+/-1%
ZQ
D6
DQS6

DM6
DQ[48:55]




CK

CKE
ODT
A[0:13]/BA[0:2]




CK

CKE
ODT
A[0:13]/BA[0:2]

CK0

CKE0
ODT0
DQS

DM
DQ[0:7]
DQS

DM
DQ[0:7]
DQS

DM
DQ[0:7]
240ohm
+/-1%
ZQ
D7
DQS7

DM7
DQ[56:63]




CK

CKE
ODT
A[0:13]/BA[0:2]
240ohm
+/-1%
ZQ
240ohm
+/-1%
ZQ
Vtt
DQS

DM
DQ[0:7]
240ohm
+/-1%
ZQ
D5




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS

DM
DQ[0:7]




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS0

DM0
DQ[0:7]
DQS

DM
DQ[0:7]
D4




CK

CKE
ODT
A[0:13]/BA[0:2]
D1
D3
240ohm
+/-1%
ZQ




CK

CKE
ODT
A[0:13]/BA[0:2]
240ohm
+/-1%
ZQ
DQS

DM
DQ[0:7]
Vtt




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS

DM
DQ[0:7]




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS1

DM1
DQ[8:15]
240ohm
+/-1%
ZQ




CK

CKE
ODT
A[0:13]/BA[0:2]
D11
DQS

DM
DQ[0:7]




CK

CKE
ODT
A[0:13]/BA[0:2]
240ohm
+/-1%
ZQ
Cterm
Vtt




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS

DM
DQ[0:7]




CK

CKE
ODT
A[0:13]/BA[0:2]
DQS3

DM3
DQ[24:31]
VDD
VDD
Cterm




CK

CKE
ODT
A[0:13]/BA[0:2]




CK1

CKE1
ODT1
A[0:13]/BA[0:2]
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs]
Vtt
SPD / TS
D0-D15
D0-D15
D0-D15
D0-D15, SPD, Temp sensor
D0-D7
D8-D15
D0-D7
D8-D15
D0-D7
D8-D15
D0-D7
D8-D15
D0-D7
D8-D15
Temp Sensor
D0-D15
5
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
DQS5

DM5
DQ[40:47]
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Serial Presence Detect -- Part 1 of 2 (2GB)
256Mx64 2Ranks DDR3 SODIMM based on 128Mx8, 1.5V DDR3 SDRAMs with SPD
Byte
SPD Entry Value
Description
-BE
0
CRC range, EEPROM bytes, bytes used
1
SPD revision
2
DRAM device type
3
Module type (form factor)
4
SDRAM Device density and banks
5
SDRAM device row and column count
6
Module minimum nominal voltage
7
Module ranks and device DQ count
8
ECC tag and module memory Bus width
-CG
Serial PD Data Entry
(Hexadecimal)
-BE
-CG
CRC Covers Bytes: 0~116,
Total SPD Bytes: 256,
SPD Bytes Used: 176,
92
Revision 10
10
DDR3 SDRAM
0B
SO-DIMM
03
8 banks, 1Gb
02
14 rows, 10 columns
11
1.5V
00
2 ranks, 8 bits
09
Non ECC, 64bits
03
2.5ps
52
1ns
01
9
Fine timebase dividend/divisor (in ps)
10
Medium timebase dividend
11
Medium timebase divisor
12
Minimum SDRAM cycle time (tCKmin)
13
Reserved
14
CAS latencies supported
15
CAS latencies supported
Undefined
00
16
Minimum CAS latency time (tAAmin)
13.125ns
69
17
Minimum write recovery time (tWRmin)
15ns
78
18
Minimum -to- delay (tRCDmin)
13.125ns
69
19
Minimum Row Active to Row Active delay (tRRDmin)
20
Minimum row Precharge delay (tRPmin)
21
Upper nibble for tRAS and tRC
22
Minimum Active-to-Precharge delay (tRASmin)
23
Minimum Active-to-Active/Refresh delay (tRCmin)
24
Minimum refresh recovery delay (tRFCmin) LSB
(Combo bytes 24,25)
70
25
Minimum refresh recovery delay (tRFCmin) MSB
110ns
03
26
Minimum internal Write-to-Read command delay (tWTRmin)
7.5ns
3C
27
Minimum internal Read-to-Precharge command delay
(tRTPmin)
7.5ns
3C
28
Minimum four active window delay (tFAWmin) LSB
29
Minimum four active window delay (tFAWmin) MSB
30
SDRAM device output drivers suported
31
8ns
1.875ns
08
1.5ns
0F
Undefined
6,7,8
00
6,7,8,9
7.5ns
6ns
1C
3C
3C
13.125ns
30
69
1,1
11
37.5ns
36ns
2C
50.625ns
49.125ns
95
(Combo byte 28, 29)
37.5ns
0C
30ns
20
89
01
00
2C
F0
RZQ / 7,
DLL-Off Mode Support,
82
SDRAM device thermal and refresh options
Extended Temperature Range,
ASR,
05
32
Module thermal sensor
Non Thermal Sensor Support
00
33
SDRAM device type
Standard Monolithic Device
00
Undefined
--
29 < height ≦ 30 mm
0F
34-59 Reserved
60
Module height (nominal)
REV 1.2
03/2010
6
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Note
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Serial Presence Detect -- Part 2 of 2 (2GB)
256Mx64 2Ranks DDR3 SODIMM based on 128Mx8, 1.5V DDR3 SDRAMs with SPD
Byte
SPD Entry Value
Description
-BE
-CG
Serial PD Data Entry
(Hexadecimal)
-BE
-CG
61
Module thickness (Max)
Back: 1 < thickness ≤ 2 mm, Front:
1 < thickness ≤ 2 mm,
11
62
Raw Card ID reference
Raw Card F
05
63
DRAM address mapping edge connector
Undefined
00
64-116
Reserved
Undefined
--
117-118
Module manufacture ID
119-125
Module information
126-127
CRC
128-145
Module part number
ASCII values
--
146
Module die revision
Undefined
00
147
Module PCB revision
Undefined
00
Nanya Technology
830B
Nanya Technology
830B
Undefined
Undefined
-503F
1296
148-149
DRAM device manufacturer ID
150-175
Manufacturer reserved
Undefined
--
176-255
Customer reserved
Undefined
--
REV 1.2
03/2010
7
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Note
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Environmental Requirements
Symbol
Rating
Units
Note
TOPR
Module Operating Temperature Range (ambient)
Parameter
0 to 55
°C
3
HOPR
Operating Humidity (relative)
10 to 90
%
1
TSTG
Storage Temperature (Plastic)
-55 to 100
°C
1
HSTG
Storage Humidity (without condensation)
5 to 95
%
1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal
1, 2
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Up to 9850 ft.
3. The component maximum case temperature shall not exceed the value specified in the component spec.
Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
Parameter
Rating
Units
Note
Voltage on VDD pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
Voltage on VDDQ pins relative to Vss
-0.4 V ~ 1.975 V
V
1, 3
Voltage on I/O pins relative to Vss
-0.4 V ~ 1.975 V
V
1
-55 to +100
°C
1, 2
Storage Temperature
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater
Operating temperature Conditions
Symbol
TOPER
Rating
Units
Note
Normal Operating Temperature Range
Parameter
0 to 85
°C
1, 2
Extended Temperature Range
85 to 95
°C
1, 3
Note:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions,
please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full
specifications are supported in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify
a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the
DIMM SPD for option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh
mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option
availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
REV 1.2
03/2010
8
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
DC Electrical Characteristics and Operating Conditions
Symbol
VDD
VDDQ
Parameter
Min
Typ
Max
Units
Notes
Supply Voltage
1.425
1.5
1.575
V
1,2
Output Supply Voltage
1.425
1.5
1.575
V
1,2
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
VIH.CA(DC)
DC Input Logic High
DDR3-1066 (-BE)
DDR3-1333 (-CG)
Units
Note
VDD
V
1
Min.
Max.
Min.
Max.
Vref + 0.100
VDD
Vref + 0.100
VIL.CA(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.CA(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.175
Note 2
V
1, 2
VIL.CA(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.175
V
1, 2
VIH.CA(AC150) AC Input Logic High
-
-
Vref + 0.15
Note 2
V
1, 2
VIL.CA(AC150) AC Input Logic Low
-
-
Note 2
Vref - 0.15
V
1, 2
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
VRefCA(DC)
Reference Voltage for
ADD, CMD Inputs
Note:
1. For input only pins except RESET#. Vref = VrefCA(DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-1066 (-BE)
Min.
DDR3-1333 (-CG)
Max.
Min.
Max.
Units
Note
1
VIH.DQ(DC)
DC Input Logic High
Vref + 0.100
VDD
Vref + 0.100
VDD
V
VIL.DQ(DC)
DC Input Logic Low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.DQ(AC)
AC Input Logic High
Vref + 0.175
Note 2
Vref + 0.15
Note 2
V
1, 2, 5
VIL.DQ(AC)
AC Input Logic Low
Note 2
Vref - 0.175
Note 2
Vref - 0.15
V
1, 2, 5
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
VRefDQ(DC)
Reference Voltage for
DQ, DM Inputs
Note:
1. For input only pins except RESET#. Vref = VrefDQ (DC).
2. See “Overshoot and Undershoot Specifications” in the device datasheet.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV
(peak to peak).
REV 1.2
03/2010
9
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V (2GB, 2Ranks, base on 128Mx8 DDR3 SDRAMs)
Symbol
Parameter/Condition
DDR3-1066
DDR3-1333
Unit
I DD0
Operating Current: one bank activate/Precharge
986
1074
mA
I DD1
Operating Current: one bank activate/Read/Precharge
1162
1250
mA
I DD2P(0) Precharge Power-Down Current Fast Exit-MR0 bit A12=0
211
211
mA
I DD2P(1) Precharge Power Down Current Slow Exit-MR0 bit A12=1
440
528
mA
I DD2N
Precharge Standby Current
968
1056
mA
I DD2Q
Precharge Quiet Standby current
880
968
mA
I DD3P
Active Power-Down Current Always Fast Exit
528
616
mA
I DD3N
Active Standby Current
968
1056
mA
I DD4W
Operating Current: Burst Write
1514
1866
mA
I DD4R
Operating Current: Burst Read
1514
1778
mA
I DD5B
Burst Refresh Current
2042
2218
mA
I DD6
Self-Refresh Current Normal Temperature Range (0-85C)
176
176
mA
I DD7
All Bank Interleave Read Current
3538
4418
mA
REV 1.2
03/2010
10
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Speed Bins
Speed Bin
DDR3-1066(-BE)
7-7-7
CL - nRCD - nRP
DDR3-1333 (-CG)
9-9-9
Unit
Symbol
Min
Max
Min
Max
tAA
13.125
20
13.125
20
ns
tRCD
13.125
--
13.125
--
ns
tRP
13.125
--
13.125
--
ns
tRC
50.625
--
49.125
--
ns
tRAS
37.5
9*tREFI
36
9*tREFI
ns
CWL=5
tCK(AVG)
2.5
3.3
2.5
3.3
ns
CWL=6
tCK(AVG)
Reserved
Reserved
ns
CWL=7, 8
tCK(AVG)
Reserved
Reserved
ns
CWL=5
tCK(AVG)
Reserved
ns
CWL=6
tCK(AVG)
CWL=7
tCK(AVG)
Reserved
Reserved
ns
CWL=8
tCK(AVG)
Reserved
Reserved
ns
CWL=5
tCK(AVG)
Reserved
Reserved
ns
CWL=6
tCK(AVG)
Parameter
Internal read command
to first data
ACT to internal read or
write delay time
PRE command period
ACT to ACT or REF
command period
ACT to PRE command
period
CL = 6
CL = 7
CL = 8
CL = 9
1.875
<2.5
1.875
<2.5
1.875
<2.5
ns
ns
CWL=7
tCK(AVG)
CWL=8
tCK(AVG)
Reserved
CWL=5, 6
tCK(AVG)
Reserved
CWL=7
tCK(AVG)
Reserved
tCK(AVG)
Reserved
Reserved
ns
6,7,8
6,7,8,9
nCK
6
6,7
nCK
Supported CL settings
Supported CWL Settings
03/2010
<2.5
Reserved
CWL=8
REV 1.2
Reserved
1.875
Reserved
ns
Reserved
ns
Reserved
ns
1.5
<1.875
ns
11
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
DDR3-1066
Parameter
DDR3-1333
Symbol
Min
Max
Min
tCK(DLL_O
FF)
8
-
8
Average high pulse width
tCH(avg)
0.47
0.53
0.47
Average low pulse width
tCL(avg)
0.47
0.53
Absolute Clock Period
tCK(abs)
tCK(avg)min
+tJIT(per)min
tCK(avg)max
+tJIT(per)max
Absolute clock high pulse width
tCH(abs)
0.43
-
Absolute clock low pulse width
tCL(abs)
0.43
Clock Period Jitter
tJIT(per)
-90
tJIT(per,lck)
-80
Max
Units
Clock Timing
Minimum Clock Cycle time (DLL off mode)
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Duty Cycle Jitter
ns
0.53
tCK(avg)
0.47
0.53
tCK(avg)
tCK(avg)min
+tJIT(per)min
tCK(avg)max
+tJIT(per)max
ps
0.43
-
ps
-
0.43
-
ps
90
-80
80
ps
80
-70
70
ps
tJIT(cc)
180
160
ps
tJIT(cc,lck)
160
140
ps
tJIT(duty)
-
-
-
-
ps
Cumulative error across 2 cycles
tERR(2per)
-132
132
-118
118
ps
Cumulative error across 3 cycles
tERR(3per)
-157
157
-140
140
ps
Cumulative error across 4 cycles
tERR(4per)
-175
175
-155
155
ps
Cumulative error across 5 cycles
tERR(5per)
-188
188
-168
168
ps
Cumulative error across 6 cycles
tERR(6per)
-200
200
-177
177
ps
Cumulative error across 7 cycles
tERR(7per)
-209
209
-186
186
ps
Cumulative error across 8 cycles
tERR(8per)
-217
217
-193
193
ps
Cumulative error across 9 cycles
tERR(9per)
-224
224
-200
200
ps
Cumulative error across 10 cycles
tERR(10per)
-231
231
-205
205
ps
Cumulative error across n=11~50 cycles
tERR(npr)min
tERR(npr)max
tERR(npr)min
tERR(npr)max
tERR(nper) =(1+0.68In(n))*tJIT =(1+0.68In(n))*tJIT =(1+0.68In(n))*tJIT =(1+0.68In(n))*tJIT
(per)min
(per)max
(per)min
(per)max
ps
Data Timing
DQS,  to DQ skew, per group, per access
tDQSQ
-
150
-
125
ps
DQ output hold time from DQS, 
tQH
0.38
-
0.38
DQ low-impedance time from CK, 
tLZ(DQ)
-600
300
-500
250
ps
DQ high-impedance time from CK, 
tHZ(DQ)
-
300
-
250
ps
25
-
-
-
ps
75
-
30
-
ps
Data setup time to DQS,  reference to Vih(ac) / Vil(ac) tDS(base)
levels
AC175
Data hold time to DQS,  reference to Vih(ac) / Vil(ac) tDS(base)
levels
AC150
Data hold time from DQS, referenced to Vih(dc) / Vil(dc) tDH(base)
levels
DC100
DQ and DM Input pulse width for each input
100
tCK(avg)
65
ps
tDIPW
490
-
400
-
ps
DQS,  differential READ Preamble
tRPRE
0.9
-
0.9
-
tCK(avg)
DQS,  differential READ Postamble
tRPST
0.3
-
0.3
-
tCK(avg)
DQS,  differential output high time
tQSH
0.38
-
0.40
-
tCK(avg)
Data Strobe Timing
DQS,  differential output low time
tQSL
0.38
-
0.40
-
tCK(avg)
DQS,  differential WRITE Preamble
tWPRE
0.9
-
0.9
-
tCK(avg)
DQS,  differential WRITE Postamble
tWPST
0.3
-
0.3
-
tCK(avg)
DQS,  rising dege output access time from rising CK,

tDQSCK
-300
300
-255
255
ps
DQS,  low-impedance time (Reference from RL-1)
tLZ(DQS)
-600
300
-500
250
ps
DQS,  high-impedance time (Reference from RL +
BL/2)
DQS,  differential input low pulse width
DQS,  differential input high pulse width
REV 1.2
03/2010
tHZ(DQS)
-
300
-
250
ps
tDQSL
0.45
0.55
0.45
0.55
tCK(avg)
tDQSH
0.45
0.55
0.45
0.55
tCK(avg)
12
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Parameter
Data Strobe Timing
DQS,  rising edge to CK,  rising edge
Symbol
DDR3-1066
Min
Max
Min
DDR3-1333
Max
Units
tDQSS
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,  falling edge setup time to CK,  rising edge
tDSS
0.2
-
0.2
-
tCK(avg)
DQS,  falling edge hold time to CK,  rising edge
tDSH
0.2
-
0.2
-
tCK(avg)
DLL locking time
Internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal read
command
WRITE recovery time
tDLLK
512
-
512
-
nCK
tRTP
max(4nCK, 7.5ns)
-
max(4nCK, 7.5ns)
-
tWTR
max(4nCK, 7.5ns)
-
max(4nCK, 7.5ns)
-
tWR
15
-
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
max(12nCK, 15ns)
-
max(12nCK, 15ns)
-
 to  command delay
tCCD
4
-
4
-
Command and Address Timing
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
tDAL(min)
WR + roundup (tRP/tCK(avg))
nCK
nCK
tMPRR
1
-
1
-
ACTIVE to ACTIVE command period for 1KB page size
tRRD
max(4nCK, 7.5ns)
-
max(4nCK, 6ns)
-
Four activate window for 1KB page size
Command and Address setup time to CK,  referenced to
Vih(ac) / Vil(ac) levels
Command and Address hold time to CK,  referenced to
Vih(ac) / Vil(ac) levels
tFAW
37.5
-
30
-
ns
tIS(base)
125
-
65
-
ps
tIH(base)
200
-
140
-
ps
Power-up and RESET calibration time
tZQinit
512
-
512
-
nCK
Normal operation Full calibration time
tZQoper
256
-
256
-
nCK
tZQCS
64
-
64
-
nCK
tXPR
max(5nCK,
tRFC(min) +
10ns)
-
max(5nCK,
tRFC(min) +
10ns)
-
Calibrating Timing
Normal operation Short calibration time
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timings
Exit Self Refresh to commands not requiring a locked DLL
tXS
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
Minimum CKE low width for Self Refresh entry to exit timing
tCKESR
Valid Clock Requirement after Self Refresh Entry (SRE) or
Power-Down Entry (PDE)
Valid Clock Requirement after Self Refresh Exit (SRX) or
Power-Down Exit (PDX) or Reset Exit
max(5nCK,
tRFC(min) +
10ns)
tDLLK(min)
tCKE(min) +
1nCK
-
max(5nCK,
tRFC(min) +
10ns)
tDLLK(min)
tCKE(min) +
1nCK
-
nCK
-
tCKSRE
max(5nCK, 10ns)
-
max(5nCK, 10ns)
-
tCKSRX
max(5nCK, 10ns)
-
max(5nCK, 10ns)
-
tXP
max(3nCK, 7.5ns)
-
max(3nCK, 6ns)
-
tXPDLL
max(10nCK, 24ns)
-
max(10nCK, 24ns)
-
Power Down Timings
Exit Power Down with DLL on to any valid command; Exit
Precharge Power Down with DLL frozen to commands not
requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
-
max(3nCK,
5.625ns)
1
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tACTPDEN
1
-
1
-
nCK
tPRPDEN
1
-
1
-
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL+4+1
Timing of WR command to Power Down entry (BL8OTF,
WL+4+(tWR/tCK(a
tWRPDEN
BL8MRS, BC4OTF)
vg))
Timing of WRA command to Power Down entry (BL8OTF,
tWRAPDEN
WL+4+WR+1
BL8MRS, BC4OTF)
WL+2+(tWR/tCK(a
Timing of WR command to Power Down entry (BC4MRS) tWRPDEN
vg))
Timing of WRA command to Power Down entry (BC4MRS) tWRAPDEN
WL+2+WR+1
-
RL+4+1
WL+4+(tWR/tCK(a
vg))
-
nCK
-
nCK
WL+4+WR+1
-
nCK
-
nCK
-
WL+2+(tWR/tCK(a
vg))
WL+2+WR+1
-
nCK
Timing of REF command to Power down entry
tREFPDEN
1
-
1
-
nCK
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE or PREA command to Power Down entry
REV 1.2
03/2010
tCPDED
max(3nCK,
5.625ns)
1
tPD
tCKE
-
-
-
nCK
13
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
DDR3-1066
Parameter
DDR3-1333
Symbol
Min
Max
Min
Max
Units
ODT high time without write command or with write
command and BC4
ODTH4
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
nCK
tAONPD
2
8.5
2
8.5
ns
tAOFPD
2
8.5
2
8.5
ns
RTT turn-on
tAON
-300
300
-250
250
ps
RTT_Nom and RTT_WR turn-off time from ODTLoff
reference
tAOF
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
tCK(avg)
tWLMRD
40
-
40
-
nCK
tWLDQSEN
25
-
25
-
nCK
tWLS
245
-
195
-
ps
tWLH
245
-
195
-
ps
Write leveling output delay
tWLO
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
ns
ODT Timings
Asynchronous RTT turn-on delay (Power - Down with DLL
frozen)
Asynchronous RTT turn-off delay (Power – Down with DLL
frozen)
Write Leveling Timings
First DQS/ rising edge after write leveling mode is
programmed
DQS/DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK,  crossing to
rising DQS,  crossing
Write leveling setup hold from rising CK,  crossing to
rising DQS,  crossing
REV 1.2
03/2010
14
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Package Dimensions
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs, M2N2G64CB8HC5N]
67. 60 +/- 0. 15
(2. 661+/- 0.006)
63. 60
(2.504)
6.0
(0.236)
1
30.0 +/- 0.15
(1.181 +/- 0.006)
3. 8 max.
(0. 150 max.)
20.0
(0.787)
2. 0
(0.079)
203
Detail A
21.0
(0.827)
Detail B
1+0.07/-0.1
(0. 039 +/- 0.004)
39 .0
(1.535)
4.0
(0.157)
3.0
(0.118 )
1. 35
(0.053)
2.55
(0.100)
0.25 max.
(0.010 max.)
2x 4.0 +/- 0.1
(0.157 +/- 0.004)
2x O 1. 80
(0. 071)
0. 45 +/- 0. 03
(0. 018 +/- 0. 001)
1.0
(0.039 )
0.6
(0.024)
1.65
(0. 065)
Detail A
Units:
Detail B
Millimeters (Inches)
Note: Device position and scale are only for reference.
REV 1.2
03/2010
15
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Package Dimensions
[2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs, M2N2G64CB8HC9N]
67. 60 +/- 0. 15
(2. 661+/- 0.006)
63. 60
(2.504)
6.0
(0.236)
1
30.0 +/- 0.15
(1.181 +/- 0.006)
3. 8 max.
(0. 150 max.)
20.0
(0.787)
2. 0
(0.079)
203
Detail A
21.0
(0.827)
Detail B
1+0.07/-0.1
(0. 039 +/- 0.004)
39 .0
(1.535)
4.0
(0.157)
3.0
(0.118 )
1. 35
(0.053)
2.55
(0.100)
0.25 max.
(0.010 max.)
2x 4.0 +/- 0.1
(0.157 +/- 0.004)
2x O 1. 80
(0. 071)
0. 45 +/- 0. 03
(0. 018 +/- 0. 001)
1.0
(0.039 )
0.6
(0.024)
1.65
(0. 065)
Detail A
Units:
Detail B
Millimeters (Inches)
Note: Device position and scale are only for reference.
REV 1.2
03/2010
16
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
M2N2G64CB8HC5N / M2N2G64CB8HC9N
2GB: 256M x 64
Unbuffered DDR3 SO-DIMM
Revision Log
Rev
Date
0.1
11/2009
Preliminary Edition
1.0
01/2010
Official Release
1.1
01/2010
Revision Updated
1.2
03/2010
Add Heat Sink Part Number
REV 1.2
03/2010
Modification
17
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
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