Carrier Board Design Guide
MityDSP
TM
Document
1
Document:
MityDSP-L138, MitySOM-1808, MitySOM-1810, MityDSP-6748 Carrier Board Design Guide
Revision:
1.7
Date:
March 5, 2014
Overview
1.1 Fast Facts for Getting Started
Facts
Required socket connector
Voltages required
Supported I/O standards
SOC Peripherals*
MityDSP-L138, MitySOM-1808, MitySOM-1810, MityDSP-6748
FCI 10033853-152FSLF, FCI 10116658-152FSLF or equivalent
3.3V
LVCMOS33
3x UART, 2x SPI, EMAC (MII or RMII), 2x I2C, McASP, 2x McBSP
*SOC peripherals share pins, see SOC datasheet for specific pin-multiplexing options
1.2 Introduction
The MityDSP-L138, MitySOM-1808, MitySOM-1810 and MityDSP-6748 modules are System On Modules (SOMs)
designed to be easy to integrate into an end-user embedded system. The modules integrate many crucial
elements of an embedded system, and do so with an established design framework utilizing a common set of
core libraries. End-user design of the application PCB is also intended to be as simple as possible, allowing the
PCB designer to concentrate on the custom I/O interfaces – especially analog & mixed-signal – instead of getting
distracted with the learning curve of designing a brand new embedded digital system from scratch.
1.3 MityDSP-L138 Family Modules
The MityDSP-L138, MitySOM-1808, and MityDSP-6748 family of modules represents a 3rd generation SOM in the
MityDSP product line. These modules are based on a Texas Instruments OMAP-L138, Sitara-1808, Sitara-1810
and the TMS320C6748 System On Chip (SOC) modules, respectively. Each of these SOC modules are pin
compatible devices that employ one or both of an ARM 9 core and a DSP 674x floating point DSP core according
to the table below.
Core
OMAP-L138
AM1808
TMS320C6748
ARM926EJ-S 300/375/456 MHz
Y
Y
N
DSP 674X Floating Point DSP 300/375/456 MHz
Y
N
Y
Page 1 of 17
Document Revision: 1.7 – MityDSP-L138 Revision 4A
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Each module includes power management, DDR2 SDRAM, NAND and NOR Flash memories, and is interfaced by a
200-pin low-profile SO-DIMM card-edge connector. Carrier board design for these types of MityDSP is the main
focus of this document.
The 2nd generation module, the MityDSP-Pro (MityDSP-6455), is based on a Texas Instruments TMS320C645x
DSP, includes DDR2 SDRAM and Flash memories, and is interfaced by the same 200-pin SO-DIMM card-edge
connector and a 100-pin high-density, low-profile Hirose connector. The module integrates a large Xilinx
Spartan3 FPGA for implementing required on-board logic and I/O interfaces, but primarily for end-user
customizable logic and I/O interfaces. The module also incorporates a number of high bandwidth I/O interfaces
including: PCI/HPI, Serial RapidIO, and Gigabit Ethernet interfaces provided by the DSP; and DDR SDRAM
dedicated to the FPGA.
The 1st generation family of modules, the MityDSP and MityDSP-XM (MityDSP-6711 and MityDSP-6711XM), are
based on a Texas Instruments TMS3206711 DSP, include SDRAM and Flash memories, and are interfaced using a
144-pin SO-DIMM card edge connector. The module integrates a Xilinx Spartan 3 FPGA for implementing
required on-board logic and I/O interfaces.
All types of MityDSP are available with options for speed grade, memory size, FPGA size (or complete removal),
operating temperature ranges, and RoHS / non-RoHS compliance. Please contact Critical Link for the current list
of MityDSP and MitySOM variants.
1.4 MityDSP-L138F Family Modules (With FPGA)
An available option to the MityDSP-L138 family of modules is a module that includes a Spartan6 FPGA. This unit
is slightly larger than the non-FPGA module, and it requires slightly more power to run. Many of the IO pins
previously reserved for SoC functions have been instead routed to FPGA pins, but those functions are still
available by passing them through the FPGA. The difference in the part name is the addition of the “F” at the
end. See the datasheets and design guide for these parts for pin-out information.
Page 2 of 17
Document Revision: 1.7 – MityDSP-L138 Revision 4A
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
1.5 Module Dimensions
A dimensioned drawing of module is included below in Figure 1.
Figure 1: MityDSP-L138, MitySOM-1808, MitySOM-1810 MityDSP-6748 Mechanical Drawing
Page 3 of 17
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
2 Connectors
All types of MityDSP utilize SO-DIMM style edge-connectors for main connectivity with the end user application
PCB. These connectors were chosen for their high density, compact size, ease of procurement, and low cost.
With edge connectors, a physical socket component is only required on one side – the main PCB side. The SODIMM standard also allows the MityDSP module to lay flat, in parallel with the main PCB, as they were intended
for use by memory modules in compact equipment, such as laptops.
2.1 Card-edge compatibility
The MityDSP-L138 family of SOMs is designed to plug into a 200-pin SO-DIMM DDR2 RAM socket. These sockets
are used for memory on PC laptop systems. Please note that the MityDSP is NOT electrically compatible with
the DDR2 socket standard, and intermixing modules/sockets from the two standards would very possibly cause
permanent damage to one or both sides.
2.2 Module Pin-out
The SO-DIMM card edge interface contains 4 classes of signals:
Power (PWR)
Dedicated signals mapped to the processor (D)
Dedicated signals when NAND memory is populated on the module (D*)
Multi-function signals mapped to the processor (M)
Table 1: MityDSP-L138, MitySOM-1808, MitySOM-1810 and MityDSP-6748 Card-edge (J100) Pin-out
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
Ball
K14
J1
J2
L1
L2
P16
P18
P19
N19
M18
M19
Type
PWR
PWR
PWR
PWR
PWR
D
D
D
D
D
D
D
D
D
D
D
I/O
I
O
O
I
I
I
I/O
I/O
O
I/O
I/O
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
RESET_IN#
SATA_TX_P
SATA_TX_N
SATA_RX_P
SATA_RX_N
USB0_ID
USB1_D_N
USB1_D_P
USB0_VBUS
USB0_D_N
USB0_D_P
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Ball
A4
A3
A2
A1
B4
B1
B2
B3
C2
C3
Type
PWR
PWR
PWR
PWR
PWR
D
M
M
M
M
M
M
M
M
M
M
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
Page 4 of 17
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Pin
33
35
37
39
41
43
45
47
491
51
53
552
572
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
Ball
K18
H17
G17
H16
G19
F18
G16
G18
F16
F17
F19
E18
E16
D17
D19
C17
D16
E17
D18
C19
C18
C16
A18
B15
C15
A15
C14
D15
B14
D14
A14
C13
E13
Type
D
D
PWR
PWR
PWR
D
D
D
D
M
D
D
D
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
D*
M
M
M
D*
D*
M
PWR
M
M
M
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
Signal
USB0_DRVVBUS
3V RTC Battery
+3.3 V in
+3.3 V in
GND
SPI1_MISO
SPI1_MOSI
SPI1_ENA
SPI1_CLK
SPI1_SCS[1]
Reserved
I2C0_SCL
I2C0_SDA
UART2_TXD / I2C1_SDA
UART2_RXD / I2C1_SCL
GND
UART1_TXD
UART1_RXD
MDIO_CLK
MDIO_D
MII_RXCLK
MII_RXDV
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
GND
MII_CRS
MII_RXER
EMA_CS[0]
EMA_OE
EMA_BA[0]
EMA_BA[1]
EMA_A[0]
EMA_A[1]
EMA_A[2]
EMA_A[3]
GND
EMA_A[4]
EMA_A[5]
EMA_A[6]
Pin
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
Ball
C4
C5
D4
E4
F4
D5
A12
C11
E12
B11
E11
C10
A11
B10
A10
E9
D3
E3
E2
E1
F3
C1
D1
W15
V15
U18
V16
R14
W16
V17
W17
W18
W19
V18
Type
M
M
PWR
PWR
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
D
M
M
M
M
M
M
M
M
PWR
M
M
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
GP0_4
GP0_3
+3.3 V in
+3.3 V in
GND
GP0_2
GP0_0
GP0_8
GP0_9
MMCSD0_DAT[7]
MMCSD0_DAT[6]
MMCSD0_DAT[5]
MMCSD0_DAT[4]
MMCSD0_DAT[3]
MMCSD0_DAT[2]
GND
MMCSD0_DAT[1]
MMCSD0_DAT[0]
MMCSD0_CMD
MMCSD0_CLK
MII_TXCLK
MII_TXD[3]
MII_TXD[2]
MII_TXD[1]
MII_TXD[0]
MII_TXEN
GND
MII_COL
NC
UPP_CHA_START
VP_CLKIN1
UPP_D[15] / RMII_TXD[1]
UPP_D[14] / RMII_TXD[0]
UPP_D[13] / RMII_TXEN
UPP_D[12] / RMII_RXD[1]
UPP_D[11] / RMII_RXD[0]
UPP_D[10] / RMII_RXER
GND
UPP_D[9] / RMII_REF_CLK
UPP_D[8] / RMII_CRS_DV
UPP_D[7]
Page 5 of 17
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Pin
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
1713
173
175
177
179
181
183
185
187
189
191
193
195
Ball
B13
A13
D12
C12
B12
D13
D11
E6
C7
B6
A6
D6
A7
D9
E10
D7
C6
E7
B5
E8
B8
A8
C9
C8
A5
D8
B7
B9
A9
A16
B17
F9
B16
T17
J3
K4
F2
-
Type
M
M
M
M
M
M
M
PWR
D*
D*
D*
D*
D*
D*
D*
D*
D*
D*
PWR
D*
D*
D*
D*
D*
D*
M
M
M
M
PWR
D*
M
M
M
M
M
D
M
M
M
PWR
I/O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
-
Signal
EMA_A[7]
EMA_A[8]
EMA_A[9]
EMA_A[10]
EMA_A[11]
EMA_A[12]
EMA_A[13]
GND
EMA_D[15]
EMA_D[14]
EMA_D[13]
EMA_D[12]
EMA_D[11]
EMA_D[10]
EMA_D[9]
EMA_D[8]
EMA_D[7]
EMA_D[6]
GND
EMA_D[5]
EMA_D[4]
EMA_D[3]
EMA_D[2]
EMA_D[1]
EMA_D[0]
EMA_WEN_DQM[0]
EMA_WEN_DQM[1]
EMA_SDCKE
EMA_CLK
GND
EMA_WE
EMA_CAS
EMA_RAS
EMA_CS[2]
EMA_CS[4]
EMA_CS[5]
RESET_OUT
VP_CLKIN3
VP_CLKOUT3
LCD_MCLK
GND
Pin
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
Ball
V19
U16
U19
T16
R18
R19
T15
R15
P17
U17
J4
K3
H3
G3
G2
G1
W14
P4
R3
R2
R1
T3
T2
T1
U3
U2
U1
G4
H4
V3
F1
V2
V1
W3
W2
W1
R5
-
Type
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
-
Signal
UPP_D[6]
UPP_CHA_ENABLE
UPP_D[5]
UPP_D[4]
UPP_D[3]
UPP_D[2]
UPP_CHA_WAIT
GND
UPP_D[1]
UPP_D[0]
UPP_CHA_CLK
UPP_CHB_ENABLE
VP_CLKOUT2
VP_CLKIN2
UPP_CHB_WAIT
UPP_CHB_START
UPP_CHB_CLK
VP_CLKIN0
GND
LCD_D[15]
LCD_D[14]
LCD_D[13]
LCD_D[12]
LCD_D[11]
LCD_D[10]
LCD_D[9]
LCD_D[8]
LCD_D[7]
LCD_D[6]
GND
LCD_VSYNC
LCD_HSYNC
LCD_D[5]
LCD_PCLK
LCD_D[4]
LCD_D[3]
LCD_D[2]
LCD_D[1]
LCD_D[0]
LCD_AC_ENB_CS
GND
Page 6 of 17
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Pin
Ball
4
197 D10
1994 A17
Type I/O Signal
M
O
EMA_A_RW
D*
O
EMA_CS[3]
Pin Ball
198 B184
200 B194
Type I/O Signal
D*
I
EMA_WAIT[0]
M
I
EMA_WAIT[1]
Note 1: Pin 49, SPI1_CLK, has a 100K Ohm pull-down resistor on the module
Note 2: Pins 55 and 57 have 4.70K pull-up resistors on the module
Note 3: Pin 171, EMA_CLK, has a 49.9 Ohm resistor in series with the signal on the module
Note 4: Pins 197, 198, 199 and 200 have 1.00K Ohm resistors in series with the signals on the module
The signal group description for the above pins is included in Table 2.
Table 2: MityDSP-L138, MitySOM-1808, MityDSP-6748 Signal Group Description
Signal / Group
Type
Description
3.3 V in
EXT_BOOT#
N/A
I
RESET_IN#
I
3.3 volt input power referenced to GND.
Bootstrap configuration pin. Pull low to configure booting from
external UART1.
Manual Reset. When pulled to GND for a minimum of 1 usec,
resets the DSP processor.
Serial Peripheral Interface 1 pins.
These pins are direct connects to the corresponding SPI1_* pins on
the OMAP-L138 processor.
The SPI1_* function pins are
multiplexed with other functions. These include PWM, Timers,
UARTs, I2C0, and GPIO. For details please refer to the OMAP-L138,
Sitara-1808, or TMS320C6748 processor specifications.
Media Independent Interface (Ethernet) pins.
These pins are direct connects to the corresponding MII_* pins on
the OMAP-L138 processor.
The MII_* function pins are
multiplexed with other functions. These include SPI0, PWM,
Timers, UART0, MCBSP, MCASP, and GPIO. For details please refer
to the OMAP-L138, Sitara-1808, or TMS320C6748 processor
specifications.
MII/RMII Management Interface pins.
The MDIO_CLK and MDIO_DAT signals are direct connects to the
corresponding MDIO_* signals on the OMAP-L138 processor. The
MDIO_* function pins are multiplexed with other functions. These
include SPI0 and Timer functions. For details please refer to the
OMAP-L138,
Sitara-1808,
or
TMS320C6748
processor
specifications.
SPI1_*
I/O
MII_*
I/O
MDIO_DAT
MDIO_CLK
I/O
Page 7 of 17
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MityDSP-L138 Carrier Board Design Guide
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Signal / Group
Type
Description
GP0_*
I/O
General Purpose / multiplexed pins. These pins are direct connects
to the corresponding GP0[*] pins on the OMAP-L138 processor.
The include support for the McASP, general purpose I/O, UART
flow control, and McBSP 1. For details please refer to the OMAPL138 processor specifications.
Serial ATA Controller Transmit pins.
These pins are direct connects to the corresponding SATA_TX_*
pins on the OMAP-L138 processor. For details please refer to the
OMAP-L138,
Sitara-1808,
or
TMS320C6748
processor
specifications.
Serial ATA Controller Receive pins.
These pins are direct connects to the corresponding SATA_RX_*
pins on the OMAP-L138 processor. For details please refer to the
OMAP-L138,
Sitara-1808,
or
TMS320C6748
processor
specifications.
System Digital Ground.
EMIF-A pins. These pins are direct connects to the corresponding
EMA_* pins on the OMAP-L138 processor. Alternatively, these
pins can be configured as GPIOs. For details please refer to the
OMAP-L138,
Sitara-1808,
or
TMS320C6748
processor
specifications.
Universal Parallel Port pins.
These pins are direct connects to the corresponding UPP_* pins on
the OMAP-L138 processor.
The UPP_* function pins are
multiplexed with other functions. These include RMII, VP_DIN,
MMCSD1, and GPIO. For details please refer to the OMAP-L138,
Sitara-1808, or TMS320C6748 processor specifications.
Reduced Media Independent Interface pins.
These pins are direct connects to the corresponding RMII_* pins
on the OMAP-L138 processor. The RMII_* function pins are
multiplexed with other functions. These include UPP and VP_DIN.
For details please refer to the OMAP-L138, Sitara-1808, or
TMS320C6748 processor specifications.
Liquid Crystal Display pins.
These pins are direct connects to the corresponding LCD_* pins on
the OMAP-L138 processor.
The LCD_* function pins are
multiplexed with other functions. These include VP_DOUT, UPP,
MMCSD1, and GPIO. For details please refer to the OMAP-L138,
Sitara-1808, or TMS320C6748 processor specifications.
SATA_TX_P
SATA_TX_N
O
SATA_RX_P
SATA_RX_N
I
GND
EMA_*
N/A
I/O
UPP_*
I/O
RMII_*
I/O
LCD_*
I/O
Page 8 of 17
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MityDSP-L138 Carrier Board Design Guide
March 5, 2014
Signal / Group
Type
Description
VP_*
I/O
RESET_OUT
I/O
USB0_*,
USB1_*
I/O
Video Port In/Out.
These pins are direct connects to the corresponding VP_* pins on
the OMAP-L138 processor. The VP_* function pins are multiplexed
with other functions. These include UPP, MMCSD1, and GPIO. For
details please refer to the OMAP-L138, Sitara-1808, or
TMS320C6748 processor specifications.
Reset Output pin.
This pin is a direct connect to the RESET_OUT pin on the OMAPL138 processor. This pin can also be configured as a GPIO. For
details please refer to the OMAP-L138, Sitara-1808, or
TMS320C6748 processor specifications.
Universal Serial Bus 0 / 1 pins.
These pins are direct connects to the corresponding USB_* pins on
the OMAP-L138 processor. For details please refer to the OMAPL138, Sitara-1808, or TMS320C6748 processor specifications.
Page 9 of 17
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3 Electrical Requirements
The following sections describe the various electrical requirements for the MityDSP-L138, MitySOM-1808,
MitySOM-1810 and MityDSP-6748 modules.
3.1 Power Supplies
The MityDSP-L138, MitySOM-1808, MitySOM-1810 and MityDSP-6748 module requires only one regulated
power supply for the main +3.3V I/O power rail. All other required power rails are generated on-module by a
combination of switching and linear, high-efficiency voltage regulators. The main +3.3V power rail can be
sourced by either a linear or switching regulator as system requirements dictate. Table 3 describes the
specifications of the input voltage, allowed ripple, and current requirements.
Table 3: Module Voltage and Current Specifications
Module
MityDSP-L138
Spec.
Minimum
Typical
Maximum
V3.3
I3.3
3.14
170
3.3
300
3.46
TBD
Units
V
mA
3.2 Recommended Capacitance
All MityDSP-L138 family modules include some power supply rail bypass capacitors on-board, however
additional capacitance is recommended on the carrier board to minimize the ripple effect caused by changing
load currents. It is common practice to place one 10uF tantalum capacitor nearby each power supply pin pair.
Please note that this is the minimum recommended amount of additional capacitance, and even more is always
better.
3.3 I/O Interfaces
All I/O pins directly connected to the CPU SOC are compliant to only 3.3V I/O standards. The only exceptions to
this are the SATA and USB data lines. These are I/Os directly connect to the OMAP-L138’s built-in PHY
transceivers, and as such are low voltage differential signaling standards.
The following sections describe I/O interfaces that are found on all MityDSP-L138, MitySOM-1808, and MityDSP6748 types.
3.3.1 Module Reset
On the each module the main 3.3V input supply and all on-module generated power supplies are monitored and
will trigger a module hard-reset if any of them fails or becomes unstable. Also included on this module is a
manual-reset (MRESET#) input pin that can be connected to carrier board system reset and power supply
monitoring circuitry.
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3.3.2 Emulator/JTAG
All modules include connectivity for ARM/DSP emulation. There is a dedicated on-module Hirose header that is
intended for use with a Critical Link supplied breakout cable/adaptor.
The ARM/DSP emulator connection is used for code download to RAM, and real-time debugging with TI’s Code
Composer Studio. All on-module signals are directly connected to the processor pins.
3.3.3 McASP Port
All modules include a Multi-Channel Audio Serial Port provided by the SOC. The McASP supports audio
generation in Time Division Multiplexed (TDM) mode and Inter-IC Sound (I2S) format for as many as 16 stereo
audio channels at standard professional audio sampling rates. The McASP signals are direct connects to the SOC
and are configured for 3.3 V I/O logic. For more information, please consult the DSP device datasheets and
McASP user guide documents provided by Texas Instruments. The McASP pins are shared with other peripherals
on the SOC. Refer to the SOC datasheet for more details.
3.3.4 McBSP Ports
All modules include two Multi-channel Buffered Serial Ports provided by the SOC. These ports support a variety
of synchronous serial communication protocols including TDM and SPI types. They can be used for connectivity
to a wide array of data converters (DACs and ADCs), other DSPs, and other communications equipment. The
signals are connected directly to the CPU SOC device pins and are configured for 3.3 V I/O logic. For more
information, please consult the DSP device datasheets and McBSP user guide documents provided by Texas
Instruments. The McBSP pins are shared with other peripherals on the SOC. Refer to the SOC datasheet for
more details.
3.3.5 Serial UARTs
All modules include support for up to 3 UARTs directly connected to the processor. UART1 should be configured
as a UART as that is the factory default console port used to support the bootloading application as well as the
console for most higher level operating systems. The other UARTs may be configured per application needs.
The UARTs share pins with other peripherals on the SOC processor. Refer to the SOC datasheet for more details.
3.3.6 Serial ATA (SATA)
The SOC device on the MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 includes a serial ATA
bus controller. The bus controller lines have been routed to the edge connector for application use. For details,
refer to the SOC datasheet.
3.3.7 SPI Ports
All modules include support for up to 2 SPI ports each having up to 8 chip selects directly controlled by the
peripheral and may also use general GPIO pins as chip select pins if necessary. SPI1 chip select 0, however, is
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reserved in order to support booting from the on-board NOR flash. After bootloading, access to the NOR flash is
typically not required, and the SPI port may be used with other chip selects if required. The SPI ports share pins
with other peripherals on the SOC processor. Refer to the SOC datasheet for more details.
3.3.8 I2C Ports
All modules include support for up to 2 Inter-Integrated Circuit (I2C) ports. I2C0 is connected to an on-board
prom (address 1010XXXb) that is used to hold factory configuration data (serial number, MAC address, etc.) and
is therefore dedicated to this function. I2C0 is also connected to an on-board Power Management Integrated
Circuit (PMIC), the TPS65023 (address 1001000b). Users may use the I2C0 port however, to interface to other
devices having different addresses than those mentioned on this bus. The I2C ports share pins with other
peripherals on the SOC processor. Refer to the SOC datasheet for more details.
3.3.9 10/100 Ethernet
Ethernet on the MityDSP-L138, MitySOM-1808, MitySOM-1810, or MityDSP-6748 is available as a MAC core in
the CPU SOC. This Ethernet MAC is capable of full and half duplex 10/100 Mbit operation. To complete the
interface, the MAC core requires a physical-layer device (PHY), an Ethernet isolation transformer (H1102 or
equivalent), and an RJ-45 style connector (RJHSE-5381 or equivalent) on the carrier board. A connector with
integrated magnetics and passives may also be used in place of discrete components.
All of the SOCs in this family of MityDSP (OMAP-L138, Sitara-1808, Sitara-1810, and DSP6748) provide support
for both standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) formats.
The MityDSP-L138 family of SOMs expose the RMII SOC interface directly to the edge connector. In general,
designs requiring Ethernet should use the MII interface with MityDSP-L138 family SOMS. However, the RMII
interface may still be used if the UPP and Video-Port-In functions are not needed.
The PHY IC’s commonly used by Critical Link are the TI TLK100, and SMSC LAN87x0 family. It is also possible to
connect the MAC core directly to an Ethernet Switch IC, such as the Micrel KS8995, via its standard Ethernet MII
port. This option gives the carrier board the flexibility of easily making connections with several other Ethernet
devices, without the need for additional networking equipment.
3.3.10 USB
The SOC provides two Universal Serial Bus (USB) interfaces that are mapped directly to the edge connector of
the module. One port is capable of running as a host controller using USB 1.1 compliant protocols. The second
port is capable of operating using the On-The-Go (OTG) protocol and is USB 2.0 compliant. OTG protocols
support dynamic switching from host mode (e.g., for controlling USB mass storage devices such as thumb drives)
to client mode (e.g., for interfacing to a PC) based on application software. For details in implementing the USB
physical interface, refer to the TI SOC datasheets. The USB functions are not multiplexed with any other
interfaces on the module.
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3.3.11 EMIFA
All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s External
Memory Interface-A (EMIFA) bus interface on the SO-DIMM edge connector. This memory interface bus is
utilized on-module to support the NAND flash device on chip select 3 (CS3). The memory interface can be used
externally to the module for connection to SDRAM, SRAM, flash memories (parallel NAND / NOR), FPGAs, and
ASICs. Please refer to the SOC datasheets and user guides for more information on the operation of the EMIF
bus.
3.3.12 UPP
All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Universal
Parallel Ports. These two ports each consist of a 8/16-bit wide data bus and synchronization and flow control
signals. Each port can be configured as input or output, but they are not intended to be used in applications
requiring a bi-directional data bus. Instead, one port can be configured as output, the other as input, and both
can operate independently and simultaneously. The UPP ports are useful in moving data to/from CODECs
(DACs/ADCx), FPGAs, ASICs, and other processors. Please refer to the SOC datasheets and user guides for more
information on the operation of the UPP ports.
3.3.13 LCD Controller
All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Liquid Crystal
Display (LCD) Controller port. This port consists of a 16-bit data bus, and strobes and clocks necessary to
connect to industry standard LCD module interfaces. The controller can operate in raster mode, or
asynchronous memory-mapped mode (LIDD). Please refer to the SOC datasheets and user guides for more
information on the operation of the LCD Controller.
3.3.14 Video Port Interface
All MityDSP-L138, MitySOM-1808, MitySOM-1810, and MityDSP-6748 modules expose the SOC’s Video Port
Interface (VPIF). This port consists of two separate data paths – one input and one output. Each is a 16-bit data
bus with clock signals. The ports can be used to move TV/video data into and out of the SOC. The port pins are
multiplexed with other functions such as the UPP, RMII, and MMCSD1. Please refer to the SOC datasheets and
user guides for more information on the operation of the Video Port Interface.
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4 Mechanical Requirements
The following sections describe some of the mechanical requirements of incorporating a MityDSP-L138,
MitySOM-1808, MitySOM-1810, or MityDSP-6748 module in a board design.
4.1 Module Connectors
The module requires as its main interface the low-profile connector socket P/N 10116658-152FSLF from FCI,
which is available from Digi-Key and other vendors. Sockets which are compatible with this industry standard
DDR2 memory module socket are also available from other manufacturers and vendors.
The module may also be able to use a higher-profile connector socket that is mechanically compatible, but not
necessarily footprint compatible with the connector mentioned above. Please contact Critical Link for a current
list of compatible connector sockets for the module.
4.2 Module Clearance
All module types use a SO-DIMM style main interface connector for electrical and mechanical attachment to the
carrier board. This style of connector positions the MityDSP module in parallel with the carrier board, and as
such there is limited clearance between the MityDSP module and the carrier board. Therefore it is impossible to
place high-profile carrier board components underneath the MityDSP module. However, it is possible to utilize
most of this space for low-profile components. Please refer to the following diagrams and tables for modulespecific clearances.
Socket Connector
MityDSP-L138/6748 / MitySOM-1808/1810 Module
1.00
1.20
Module Center-Line
Keep-out
3.30
2.80
1.60
Carrier Board
All dimensions are in millimeters.
X-dimension is not to scale.
Figure 2: MityDSP-L138, MityDSP-6748, MitySOM-1808, MitySOM-1810 Module Clearance - Side View
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4.3 Mounting Methods
The modules feature an additional optional mechanical attachment method. A hard mechanical attachment by
board-to-board standoffs and screw hardware may be used to mount the module. The corners of the freefloating edge of the SOMs feature mounting holes that are compatible with 4-40 size mounting hardware. The
mechanical drawing in Figure 1 below illustrates the mechanical requirements of this optional attachment
method. Another option to secure the module is with the use of a screw, spacer and a self-clinching nut (PEM)
that is inserted into the carrier board mounting holes, please contact Critical Link for details about utilizing this
option.
Socket Connector
Module Center-Line
MityDSP-L138, MitySOM-1808, MitySOM-1810, MityDSP-6748 Module
3.0mm
Standoff
&
Hardware
2.8mm
3.3mm
Carrier Board
Drawing is not to scale.
Figure 3: Standoff based Hold Down Concept Drawing
4.4 Shock & Vibration
For customers who are interested in using MityDSP modules in rugged environments, the optional mechanical
attachment methods discussed in section 4.3 above enable MityDSP modules to tolerate much greater
mechanical shock and vibration forces than without any additional mounting support.
4.5 Thermal Management
The MityDSP-L138 family of SOMs have no specific requirements regarding thermal management. The modules
can be operated without heat sinks or air flow, and inside tight enclosures. However, if a module is intended to
be used in hot industrial environments, it is advisable to do plenty of testing in the enclosure and environment
that the module will be used in. In these cases, it may be necessary to either add thermal management to the
enclosure, or lower the operating temperature specification of the end product.
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5 Board Layout Recommendations
The following sections discuss topics for successful board layouts incorporating any module.
5.1 Placement
Placement of the module site is crucial to a successful carrier board layout. Because the module connector
footprint is fine-pitch and dual-row, it is generally best to place the connector fairly centered in the overall board
layout. This placement allows traces to be routed out from both sides of the connector, using mainly top-side
copper tracks. The use of less signal layers, and therefore less vias, generally results in a more compact design
with better signal integrity than a board using many layers and vias. Of course, ideally central placement is not
always possible because of other mechanical constraints.
Mechanically, enough space must be allocated for the full extension of the module. Although it is possible for a
module to hang over the edge of its carrier board, this may not be desirable if additional mechanical attachment
methods are desired for ruggedness, as discussed in sections 4.3 and 4.4. Another thing to keep in mind with
placement on the carrier board and in enclosures is the cam-in action of the MityDSP modules into their
respective sockets. The modules are generally installed at an angle of about 25° to 30° before swinging down to
locked position. Enclosure designs should accommodate this motion.
5.2 Pin-out and Routing
Care must be taken when routing the SOC high speed interfaces – specifically the USB 1.0 and 2.0 OTG ports and
the SATA ports. Please refer to the specific SOC device specification for guidance related to these pins.
5.3 Access issues
Given that it is possible and often desirable to make best use of available space by placing components
underneath the MityDSP module (refer to section 4.2), hardware and software engineers who will be debugging
code on the platform could find themselves in a tough situation if the component they need to access is blocked
by the installed MityDSP module. Because of these situations it is advisable to either not use the space under
the MityDSP module for active components that might need live probing with the MityDSP in-circuit, or only
place circuits there that are already tried and tested by engineers on other platforms. In the event that an
obscured circuit does need to be probed, it may be necessary to solder temporary wires onto probe points. An
even better solution would be to design the board with bottom-side test points, at least in the MityDSP region, if
this is possible on a given design.
5.4 PCB/PCA Technology
MityDSP modules do not have any specific requirements about the PCB technology used for its carrier board.
The required socket connectors are available as RoHS compliant, and may be used in both leaded and lead-free
assembly processes. The only recommendation is to fabricate the carrier board thick enough to rigidly support
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the MityDSP socket connector. In practice, FR-4 with a common finished thickness of 0.062 inches is enough for
all types of MityDSP modules.
5.5 PCB Footprints
Figure 4: 10033853-152FSLF Recommended PCB Footprint
6
Revision History
Revision
1.0
1.1
Date
11-September-2010
11-November-2011
1.2
1.3
13-February-2012
13-February-2012
1.4
1.5
1.6
19-April-2012
13-August-2012
27-March-2013
1.7
5-March-2014
Description of Changes
Initial Revision
- Added Revision History
- Added I2C address for PMIC
Fix typo in signal names for pins 79, 81, and 83
Fix typo in pinout table, pins 160, 170, and 180 were incorrectly
numbered.
Remove erroneous references to FPGA in the JTAG description.
Fix typos in pinout table for pins 79, 81, 83, and 84
Added processor ball numbers to the pin-out table and added 1810 to
the datasheet.
Update MitySOM product name.
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