512MB, 1GB Unbuffered DIMMs
240-Pin Unbuffered DIMM
DDR2 SDRAM
DDR2 Unbuffered DIMM Module
2GB based on 1Gbit components
60 Balls TFBGA with Pb-Free
Revision 1.0 (Mar. 2006)
-Initial Release
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Products and Specifications discussed herein are subject to change without notice
1
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
1.0 Feature
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JEDEC standard 1.8V +/- 0.1V Power Supply
Standard Double-Data-Rate-Two Synchronous DRAMs with single 1.8V power supply
Programmable CAS latencies (3,4,5,6), Burst Length (4 & 8) and Burst Type
Auto Refresh (CRB) and Self Refresh
Bi-directional Differential Data Strobe (Single ended data strobe is option)
Off Chip Driver (OCD) impedance adjustment
On-Die termination with selectable values (50/75/150 ohms or disable)
PASR (Partial Array Self Refresh)
Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh
rate enable feature
Serial presence detect with EEPROM
DIMM Dimension (Nominal) 30.00 mm high, 133.35 mm wide
All speed grades faster than DDR400 comply with DDR400 timing specifications
Based on JEDEC standard reference Raw Cards Lay out.
RoHS compliant
Gold plated contacts
2.0 Ordering Information
Part number
Density
Module
Organization
Component
composition
Component
PKG
Module
Rank
Description
T800UB2GMT
2GB
256Mx64
128Mx8*16
TFBGA
2
2GB 2Rx8 PC2-6400R
3.0 Operating Frequencies
Speed @ CL6
DDR2-800
800
Unit
Mbps
CL-tRCD-tRP
6-6-6
CK
4.0 Absolute Maximum DC Rating
Symbol
Vin , Vout
VDD
VDDQ
VDDL
TSTG
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Parameter
Voltage on any pin relative to VSS
Voltage on VDD & VDDQ supply relative to Vss
Short circuit current
Power dissipation
Storage Temperature
Rating
-0.5 ~ 2.3
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-55 ~ + 100
Units
V
V
V
V
°C
Products and Specifications discussed herein are subject to change without notice
2
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
5.0 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREF
121
VSS
31
DQ19
151
VSS
61
A4
181
VDDQ
91
VSS
211
DM5/DQS14
2
VSS
122
DQ4
32
VSS
152
DQ28
62
VDDQ
182
A3
92
DQS5
212
NC/DQS14
3
DQ0
123
DQ5
33
DQ24
153
DQ29
63
A2
183
A1
93
DQS5
213
VSS
4
DQ1
124
VSS
34
DQ25
154
VSS
64
VDD
184
VDD
94
VSS
214
DQ46
5
VSS
125
DM0/DQS9
35
VSS
155
DM3/DQS12
KEY
95
DQ42
215
DQ47
6
DQS0
126
NC/DQS9
36
DQS3
156
NC/DQS12
65
VSS
185
CK0
96
DQ43
216
VSS
7
DQS0
127
VSS
37
DQS3
157
VSS
66
VSS
186
CK0
97
VSS
217
DQ52
8
VSS
128
DQ6
38
VSS
158
DQ30
67
VDD
187
VDD
98
DQ48
218
DQ53
9
DQ2
129
DQ7
39
DQ26
159
DQ31
68
NC/Par_in
188
A0
99
DQ99
219
VSS
10
DQ3
130
VSS
40
DQ27
160
VSS
69
VDD
189
VDD
100
VSS
220
RFU
11
VSS
131
DQ12
41
VSS
161
CB4
70
A10/AP
190
BA1
101
SA2
221
RFU
12
DQ8
132
DQ13
42
CB0
162
CB5
71
BA0
191
VDDQ
102
NC(Test)
222
VSS
13
DQ9
133
VSS
43
CB1
163
VSS
72
VDDQ
192
RAS
103
VSS
223
DM6/DQS15
14
VSS
134
DM1/DQS10
44
VSS
164
DM8/DQS17
73
WE
193
S0
104
DQS6
224
NC/DQS15
15
DQS1
135
NC/DQS10
45
DQS8
165
NC/DQS17
74
CAS
194
VDDQ
105
DQS6
225
VSS
16
DQS1
136
VSS
46
DQS8
166
VSS
75
VDDQ
195
ODT0
106
VSS
226
DQ54
17
VSS
137
RFU
47
VSS
167
CB6
76
S1
196
A13
107
DQ50
227
DQ55
18
RESET
138
RFU
48
CB2
168
CB7
77
ODT1
197
VDD
108
DQ51
228
VSS
19
NC
139
VSS
49
CB3
169
VSS
78
VDDQ
198
VSS
109
VSS
229
DQ60
20
VSS
140
DQ14
50
VSS
170
VDDQ
79
VSS
199
DQ36
110
DQ56
230
DQ61
21
DQ10
141
DQ15
51
VDDQ
171
CKE1
80
DQ32
200
DQ37
111
DQ57
231
VSS
22
DQ11
142
VSS
52
CKE0
172
VDD
81
DQ33
201
VSS
112
VSS
232
DM7/DQS16
23
VSS
143
DQ20
53
VDD
173
NC
82
VSS
202
DM4/DQS13
113
DQS7
233
NC/DQS16
24
DQ16
144
DQ21
54
NC
174
NC
83
DQS4
203
NC/DQS13
114
DQS7
234
VSS
25
DQ17
145
VSS
55
NC/Err_Out
175
VDDQ
84
DQS4
204
VSS
115
VSS
235
DQ62
26
VSS
146
DM2/DQS11
56
VDDQ
176
A12
85
VSS
205
DQ38
116
DQ58
236
DQ63
27
DQS2
147
NC/DQS11
57
A11
177
A9
86
DQ34
206
DQ39
117
DQ59
237
VSS
28
DQS2
148
VSS
58
A7
178
VDD
87
DQ35
207
VSS
118
VSS
238
VDDSPD
29
VSS
149
DQ22
59
VDD
179
A8
88
VSS
208
DQ44
119
SDA
239
SA0
30
DQ18
150
DQ23
60
A5
180
A6
89
DQ40
209
DQ45
120
SCL
240
SA1
90
DQ41
210 VSS
NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
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Products and Specifications discussed herein are subject to change without notice
3
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
6.0 DIMM Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A9, A11~A13
Address input (Multiplexed)
ODT0~ODT1
On Die Termination
A10/AP
Address Input/Auto pre-charge
CB0~CB7
Data check bits Input/Output
BA0 ~ BA1
Bank Select
DQ0~DQ63
Data Input/Output
CK0 ~ CK2
Clock (positive line of different pair)
CK0 ~ CK2
Clock (negative line of different pair)
CKE0, CKE1
Clock enable input
DQS9~DQS17
Data strobes (Read), negative line
S0, S1
Chip select input
DQS0~DQS8
Data Strobes
RAS
Row address strobe
RFU
Reserved for future used
CAS
Column address strobe
NC
No connection
WE
Write Enable
TEST
Memory bus test tool
SCL
SPD Clock Input
VDD
Core Power
SDA
SPD Data Input/Output
VDDQ
I/O Power
SA0~SA2
SPD Address
VSS
Ground
Par_In
Parity bit for address & Control bus
VREF
Input/Output Reference
Err_Out
Parity error found in the Address and
Control bus
VDDSPD
Serial EEPROM positive power supply
RESET
Register and PLL control pin
DQS0~DQS8
DM(0~8),
DQS(9~17)
Data strobes, negative line
Data Masks/Data strobes (Read)
7.0 Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
128Mx8(1Gb) base
A0-A13
A0-A9
BA0-BA2
A10
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Products and Specifications discussed herein are subject to change without notice
4
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
8.0 Functional Block Diagram: 2GB, 256Mx64 Module (Populated as 2 ranks of x8 SDRAM DDR2 Module)
http://www.supertalent.com/oem
Products and Specifications discussed herein are subject to change without notice
5
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
9.0 AC & DC Operating Conditions
Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70°C)
Symbol
VDD
VDDL
VDDQ
VREF
VTT
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
Min
1.7
1.7
1.7
0.49*VDDQ
VREF-0.04
Typ
1.8
1.8
1.8
0.50*VDDQ
VREF
Max
1.9
1.9
1.9
0.51*VDDQ
VREF+0.04
Unit
V
V
V
mV
V
10.0 AC Timing Parameters & Specifications
(AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR2-800
Units
DQ output access time from CK/CK
tAC
min
- 400
DQS output access time from CK/CK
tDQSCK
-350
+350
ps
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP
min(tCL,tCH)
x
ps
Clock cycle time, CL=x
tCK
2500
8000
ps
DQ and DM input hold time
tDH(base)
125
x
ps
DQ and DM input setup time
tDS(base)
50
x
ps
Control & Address input pulse width for each input
tIPW
0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
x
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
x
200
ps
DQ hold skew factor
tQHS
x
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
x
ps
First DQS latching transition to associated clock edge
tDQSS
-0.25
0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
tCK
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max
+400
ps
Products and Specifications discussed herein are subject to change without notice
6
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
Parameter
Symbol
DDR2-800
min
max
Units
Write postamble
tWPST
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
tCK
Address and control input hold time
tIH(base)
250
x
ps
Address and control input setup time
tIS(base)
175
x
ps
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
tCK
Active to active command period for 1KB page size products
tRRD
7.5
x
ns
Active to active command period for 2KB page size products
tRRD
10
x
ns
Four Activate Window for 1KB page size product
tFAW
35
ns
Four Activate Window for 2KB page size products
tFAW
45
ns
CAS to CAS command delay
tCCD
2
x
tCK
Write recovery time
tWR
15
x
ns
x
Auto pre-charge write recovery + pre-charge time
tDAL
WR+tRP
Internal write to read command delay
tWTR
7.5
Internal read to pre-charge command delay
tCK
ns
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNRt
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tXP
2
x
tCK
Exit active power down to read command
tXARD
2
x
tCK
Exit active power down to read command (slow exit, lower power)
tXARDS
8 - AL
tCK
tCKE
3
tCK
tAOND
2
Exit pre-charge power down to any non-read command
CKE minimum pulse width (high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
tCK
2
tCK
tAON
tAC(min)
tAC(max)+ 0.7
ns
tAONPD
tAC(min)+2
2tCK+tAC(max)+1
ns
tAOFD
2.5
2.5
tAOF
tAC(min)
tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
2.5tCK+tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
tDelay
tIS+tCK +tIH
ODT turn-off
Minimum time clocks remains ON after CKE asynchronously drops LOW
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12
tCK
ns
ns
Products and Specifications discussed herein are subject to change without notice
7
© 2006 Super Talent Tech., Corporation.
240-Pin Unbuffered DIMM
DDR2 SDRAM
11.0 Physical Dimensions: (128Mx8 Based)
256Mx64 (2 Ranks)
Units : Millimeters
Tolerances :± 0.005(.13) unless otherwise specified
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Products and Specifications discussed herein are subject to change without notice
8
© 2006 Super Talent Tech., Corporation.
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