LM3631 Complete LCD Backlight and Bias Power

LM3631 Complete LCD Backlight and Bias Power
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LM3631
SNVS834 – AUGUST 2014
LM3631 Complete LCD Backlight and Bias Power
1 Features
•
1
•
•
•
•
•
•
•
•
2 Applications
Drives up to Two Strings with Maximum of Eight
LEDs in Series
– Integrated Backlight Boost with 29-V Maximum
Output Voltage
– Two Low-Side Constant-Current LED Drivers
with 25-mA Maximum Output Current
Backlight Efficiency Up to 90%
11-Bit Linear or Exponential Dimming with up to
17-Bit Output Resolution
External PWM Input for CABC Backlight
Operation
LCD Bias Efficiency > 85%
Programmable Positive LCD bias, 4-V to 6-V,
100-mA Maximum Output Current
Programmable Negative LCD bias, –4-V to –6-V,
80-mA Maximum Output Current
Two Positive Programmable LDO Reference
Outputs
– 4-V to 6-V, 50-mA Maximum Output Current
– 1.8-V to 3.3-V, 80-mA Maximum Output
Current
2.7-V to 5-V Input Voltage Range
Mobile Device LCD Backlighting and Bias
3 Description
The LM3631 is a complete LCD backlight and bias
power solution for mobile devices. This one-chip
solution has an integrated high-efficiency backlight
LED driver and positive/negative bias supplies for
LCD drivers addressing the power requirements of
high-definition LCDs. Integrated solution allows small
solution size while still maintaining high performance.
Capable of driving up to 16 LEDs, the LM3631 is
ideal for small- to medium-size displays. Two
additional programmable LDO regulator outputs can
be used to power display controller, LCD gamma
reference, or any additional peripherals.
A high level of integration and programmability allows
the LM3631 to address a variety of applications
without the need for hardware changes. Voltage
levels, backlight configuration, and power sequences
are all configurable through I2C interface.
Device Information(1)
PART NUMBER
DSBGA (24)
+
- VIN
BODY SIZE (MAX)
2.585 mm x 1.885 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
LSW
PACKAGE
LM3631
Backlight Efficiency, 2P6S
95
D1
Up to 8 LEDs / string
CIN
90
COUT
LBST
LED1
VOUT
BST_SW
LED2
CIN
SDA
C2
CFLY
SCL
C1
LM3631
nRST
BST_OUT
LCD_EN
CP_VNEG
PWM
LDO_OREF
OTP_SEL
LDO_VPOS
FLAG
LDO_CONT
GND_BST_SW
AGND
GND_SW
VNEG (-5.4V)
VOREF (+4.0V to +6.0V)
Total Efficiency (%)
85
SW
VIN
80
75
70
65
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VPOS (+5.4V)
50
VCONT (+1.8V)
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
D007
CCONT CVPOS COREF CNEG CBST
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3631
SNVS834 – AUGUST 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.3
8.4
8.5
8.6
1
1
1
2
3
4
5
9
Features Description ...............................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
20
34
36
40
Application and Implementation ........................ 46
9.1 Application Information............................................ 46
9.2 Typical Application .................................................. 46
10 Power Supply Recommendations ..................... 49
11 Layout................................................................... 49
Absolute Maximum Ratings ...................................... 5
Handling Ratings ...................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 6
Electrical Characteristics .......................................... 6
I2C Timing Requirements (SDA, SCL) .................. 10
Typical Characteristics ............................................ 11
11.1 Layout Guidelines ................................................ 49
11.2 Layout Example ................................................... 50
12 Device and Documentation Support ................. 51
12.1
12.2
12.3
12.4
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 19
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
51
51
51
51
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
2
DATE
REVISION
NOTES
August 2014
*
Initial release.
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5 Device Comparison Table
Table 1. Register Default Values
2
I C Address
Register
Read/Write
OTP_SEL Low
0x00
Device Control
R/W
0x01
OTP_SEL High
0x01
0x01
LED Brightness LSB
R/W
0x00
0x00
0x02
LED Brightness MSB
R/W
0x00
0x00
0x03
Faults
R/W
0x00
0x00
0x04
Faults and Power-Good
R/W
0x00
0x00
0x05
Backlight Configuration 1
R/W
0xCF
0xCF
0x06
Backlight Configuration 2
R/W
0x07
0x27
0x07
Backlight Configuration 3
R/W
0xC7
0xC6
0x08
Backlight Configuration 4
R/W
0x49
0x49
0x09
Backlight Configuration 5
R/W
0x03
0x03
0x0A
LCD_Configuration 1
R/W
0x1E
0x1E
0x0B
LCD_Configuration 2
R/W
0x01
0x14
0x0C
LCD_Configuration 3
R/W
0xDC
0x1A
0x0D
LCD_Configuration 4
R/W
0x20
0x1E
0x0E
LCD_Configuration 5
R/W
0x20
0x1E
0x0F
LCD_Configuration 6
R/W
0x1E
0x1E
0x10
LCD_Configuration 7
R/W
0x05
0x0F
0x11
LCD_Configuration 8
R/W
0x50
0x60
0x12
LCD_Configuration 9
R/W
0x00
0x00
0x13
FLAG Configuration
R/W
0x09
0x09
0x16
Revision (6 LSB bits only)
R
0x01
0x01
Values in bold are OTP configurable.
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6 Pin Configuration and Functions
DSBGA
24 BUMPS
F4
F3
F2
F1
F1
F2
F3
F4
E4
E3
E2
E1
E1
E2
E3
E4
D4
D3
D2
D1
D1
D2
D3
D4
C4
C3
C2
C1
C1
C2
C3
C4
B4
B3
B2
B1
B1
B2
B3
B4
A4
A3
A2
A1
A1
A2
A3
A4
TOP VIEW
BOTTOM VIEW
Pin Functions
PIN
4
DESCRIPTION
NUMBER
NAME
A1
CP_VNEG
A2
C2
A3
PGND
A4
C1
B1
LDO_OREF
LDO_OREF output voltage. Can be left unconnected if LDO is disabled.
B2
PWM
PWM input for brightness control. Must be connected to GND if not used.
B3
SDA
Serial data connection for I2C-compatible interface. Must be pulled high to VDDIO if not used.
B4
BST_OUT
Negative LCD bias supply voltage. Can be left unconnected if charge pump is disabled.
Inverting charge pump flying capacitor negative pin. Can be left unconnected if charge pump is
disabled.
Power ground connection for boost converters and charge pump.
Inverting charge pump flying capacitor positive pin. Can be left unconnected if charge pump is
disabled.
LCD bias boost output voltage. Internally connected to the input of CP_VNEG, LDO_VPOS, and
LDO_OREF.
C1
LDO_VPOS
Positive LCD bias supply rail. Can be left unconnected if LDO is disabled.
C2
LDO_CONT
Positive supply voltage for display panel controller. Can be left unconnected if disabled.
C3
SCL
C4
BST_SW
D1
AGND
D2
OTP_SEL
D3
FLAG
D4
GND_BST_SW
E1
LED2
E2
LCD_EN
E3
nRST
E4
VIN
Serial clock connection for I2C-compatible interface. Must be pulled high to VDDIO if not used.
LCD bias boost switch pin.
Analog ground connection for control circuitry.
Default setting selection. Must be tied to GND or to VDDIO.
Programmable interrupt flag. Open drain output. Can be left unconnected if not used.
LCD bias boost and inverting charge pump ground connection.
Input pin to internal LED current sink 2. Can be left unconnected if not used.
LCD enable input. Logic high turns on LCD bias voltages and backlight per sequencing settings.
Active low reset input.
Input voltage connection. Connect to 2.7-V to 5-V supply voltage.
F1
LED1
Input pin to internal LED current sink 1. Can be left unconnected if not used.
F2
VOUT
Backlight boost output voltage. Output capacitor is connected to this pin.
F3
SW
F4
GND_SW
Backlight boost switch pin.
Backlight boost ground connection.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage on VIN, nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL
PARAMETER
–0.3
6
V
Voltage on BST_SW, BST_OUT, LDO_VPOS, LDO_OREF, C1
–0.3
7
V
Voltage on CP_VNEG, C2
–7.0
0.3
V
Voltage on SW, VOUT, LED1, LED2
–0.3
30
V
Internally
limited
Continuous power dissipation
TJ(MAX)
Maximum junction temperature
TSOLDERING
(1)
(2)
Note
150
°C
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1112: DSBGA Wafer Level
Chip Scale Package (AN-1112).
7.2 Handling Ratings
PARAMETER
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–45
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
except SW (1)
–1000
1000
Human body model (HBM), SW pin
–600
600
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
–500
500
Storage temperature range
Electrostatic
discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input voltage
MIN
NOM
2.7
3.7
MAX
UNIT
5
V
Voltage on nRST, LCD_EN, PWM, SCL, SDA, FLAG, LDO_CONT, OTP_SEL
0
VIN + 0.3V with
5V max
V
Voltage on LDO_VPOS, LDO_OREF, C1
0
6.5
V
Voltage on BST_SW, BST_OUT
0
7
V
–6.5
0
V
0
29
V
–40
85
°C
Voltage on CP_VNEG, C2
Voltage on SW, VOUT, LED1, LED2
TA
(1)
Operating ambient temperature
(1)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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7.4 Thermal Information
DSBGA
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
63.5
RθJC
Junction-to-case (top) thermal resistance
0.3
RθJB
Junction-to-board thermal resistance
9.4
ΨJT
Junction-to-top characterization parameter
1.6
ΨJB
Junction-to-board characterization parameter
9.3
(1)
UNIT
(20 PINS)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), VIN = 3.6 V,
VPOS = VOREF = 5.4 V, VNEG = –5.4 V, VBST = 5.7 V, VCONT = 3.3V.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CURRENT CONSUMPTION
ISD
Shutdown current
nRST = LOW, LCD_EN = LOW
1
µA
IQ
Quiescent current, device not
switching
nRST = HIGH, LCD_EN = LOW,
2.7 V ≤ VIN ≤ 5 V
60
µA
nRST = HIGH, LCD_EN = HIGH,
2.7 V ≤ VIN ≤ 5 V, no load,
Backlight disabled
1
ILCD_EN
mA
DEVICE PROTECTION
UVLO
Undervoltage lockout
TSD
Thermal shutdown (1)
TSD(hyst)
Hysteresis (1)
VIN decreasing
2.5
VIN increasing
V
2.6
V
140
°C
20
°C
LED CURRENT SINKS
ILED1/2
Minimum output current
Brightness code 0x001
Maximum output current
Brightness code 0x7FF,
exponential mapping
Maximum output current
Brightness code 0x7FF, linear
mapping
IACCURACY
Absolute LED current accuracy
IMATCH
LED1 to LED2 current matching
VHR_MIN
Current sink saturation voltage
(2)
(2)
50
µA
mA
25
mA
25.3
2.7 V ≤ VIN ≤ 5.0 V, LED Currents
0.05 mA, 1 mA, 5 mA, 25 mA
–3%
3%
2.7 V ≤ VIN ≤ 5.0 V, LED Currents
0.05 mA, 1 mA, 5 mA, 25 mA
0%
3%
ILED = 95% of 5 mA
30
50
mV
BACKLIGHT BOOST CONVERTER
VOVP_BL
Backlight boost output overvoltage
protection
ηLED_DRIVE
LED drive efficiency
VHR
Regulated current sink headroom
voltage
ILED = 25 mA
250
mV
ILED = 5 mA
100
mV
RDSON
NMOS switch on resistance
ISW = 250 mA
0.5
Ω
ICL
Selectable NMOS switch current limit
900-mA setting
900
mA
(1)
(2)
6
(1)
2.7 V ≤ VIN ≤ 5 V, 29-V Option
28.8
ILED = 10 mA/string, 2P6S LED
configuration
1235AS-H-220M Inductor
88%
V
Typical value only for reference.
Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current sinks on the part (LED1 and LED2), the following is
determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of both outputs
(AVG). Matching number is calculated: (MAX - MIN)/AVG. The typical specification provided is the most likely norm of the matching
figure of all parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different
definitions in use.
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Electrical Characteristics (continued)
Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), VIN = 3.6 V,
VPOS = VOREF = 5.4 V, VNEG = –5.4 V, VBST = 5.7 V, VCONT = 3.3V.
PARAMETER
ƒSW
TEST CONDITION
Switching frequency
DMAX
MIN
TYP
MAX
500-kHz mode
450
500
550
1-MHz mode
900
1000
1100
Maximum duty cycle
UNIT
kHz
94%
LCD BIAS BOOST CONVERTER
VOVP_BST
ƒSW_BST
LCD bias boost output overvoltage
protection
Switching frequency
6.8
(1)
Load current 100mA
2500
Minimum Bias boost output voltage
LCD_BST_OUT = 000000b
4.5
Maximum Bias boost output voltage
LCD_BST_OUT = 100101b
6.35
Output voltage step size
Peak-to-peak ripple voltage
(3)
ILOAD = 50 mA, CBST = 10 µF
VBST
BST_OUT line transient response
BST_OUT load transient response
ICL_BST
RDSON_BST
(3)
(3)
V
VIN + 500 mVp-p AC square wave,
Tr = 100 mV/µs, 200 Hz, 12.5%
Duty, ILOAD 5 mA, CIN = 10 µF,
CBST = 10 µF
–50
Load current step 0 mA - 150 mA,
TRISE/FALL = 100 mA/µs, CIN = 10
µF, CBST = 10 µF
–150
Valley current limit
kHz
V
50
mV
50
mVpp
±25
50
mV
150
mV
1000
High-side MOSFET on resistance
TA = 25°C
170
Low-side MOSFET on resistance
TA = 25°C
290
(4)
ηBST
Efficiency
tST_BST
Start-up time (BST_OUT), VBST_OUT
= 10% to 90% (5)
80 mA < IBST < 200 mA
mA
mΩ
92%
CBST = 20 µF
1000
µs
LCD POSITIVE BIAS OUTPUT (LDO_VPOS)
Minimum output voltage
LDO_VPOS_TARGET = 000000b
4.0
Maximum output voltage
LDO_VPOS_TARGET = 101000b
6.0
V
50
mV
Output voltage step size
Output voltage = 5.4 V, ILOAD= 1
mA
Output voltage accuracy
VPOS
LDO_VPOS line transient response
(5)
LDO_VPOS load transient response
(5)
DC load regulation
(5)
V
–1.5%
1.5%
VIN + 500 mVp-p AC square wave,
Tr = 100 mV/µs, 200 Hz, ILOAD 25
mA, CIN = 10 µF
–25
25
mV
5 mA to 100 mA load transient,
TRISE/FALL = 2 µs , CVPOS = 10 µF
–100
100
mV
20
mV
1 mA ≤ ILOAD ≤ 100 mA
PGRISING
Power-good threshold, voltage
increasing
% of target VPOS
95%
PGFALLING
Power-good threshold, voltage
decreasing
% of target VPOS
90%
IPOS_MAX
Maximum output current
100
mA
ICL_VPOS
Output current limit
200
mA
500
mA
80
mV
IRUSH_PK_VPOS
Peak start-up inrush current
(5)
VBST = 6.3 V, VPOS = 6 V, CVPOS =
10 µF
VDO_VPOS
LDO_VPOS dropout voltage
(6)
ILOAD = 100 mA, VPOS = 4 V
(3)
(4)
(5)
(6)
Limits set by characterization and/or simulation only.
Typical value only for reference.
Limits set by characterization and/or simulation only.
VBST – VPOS when VPOS has dropped 100 mV below target.
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Electrical Characteristics (continued)
Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), VIN = 3.6 V,
VPOS = VOREF = 5.4 V, VNEG = –5.4 V, VBST = 5.7 V, VCONT = 3.3V.
PARAMETER
TEST CONDITION
MIN
ƒ = 10 Hz to 500 kHz, ILOAD= 50
mA, VBST to VPOS, 300 mV
minimum headroom
PSRRVPOS
Power supply rejection ratio,
LDO_VPOS (5)
tST_VPOS
Start-up time LDO_VPOS, VLDO_VPOS CVPOS = 10 µF
= 10% to 90% (5)
RPD_VPOS
Output pull-down resistor,
LDO_VPOS
LDO_VPOS pull-down enabled,
LDO_VPOS disabled
TYP
MAX
25
52
80
UNIT
dB
1
ms
110
Ω
LCD NEGATIVE BIAS OUTPUT (CP_VNEG)
VOVP_VNEG
LCD bias negative charge-pump
output overvoltage protection
VSHORT_VNEG
LCD bias negative charge-pump
output short circuit protection
Below VNEG output voltage target
–250
V
V
CP_VNEG_TARGET = 101000b
–6.0
Maximum output voltage
CP_VNEG_TARGET = 000000b
–4.0
Output voltage = –5.4V
Peak-to-peak ripple voltage
–1.5%
ILOAD = 50 mA,
CVNEG = 10 µF
(5)
CP_VNEG line transient response
(5)
(5)
CP_VNEG load transient response
VIN + 500 mVp-p AC square wave,
100 mV/µs 200 Hz, 12.5% DS at 5
mA
5 mA to 50 mA load transient,
TRISE/FALL = 1 µs, CVNEG = 10 µF
60
–50
±25
–100
Power good increasing
% of Target VNEG
95%
PGFALLING
Power good decreasing
% of Target VNEG
90%
Efficiency (7)
VIN = 3,7V, VBST = 5,7V VNEG = 5.4V, 20mA < ILOAD < 80mA
92%
INEG_MAX
Maximum output current
(8)
Output current limit
tST_VNEG
Start-up time, CP_VNEG,
VCP_VNEG = 10 % to 90 %
RPU_VNEG
Output pull-up resistor, CP_VNEG
50
mV
100
mV
50
mA
VIN = 3.7 V, VBST = 5.7 V,
VNEG = –5.4 V
80
mA
150
mA
VNEG = –6V, CVNEG = 10 µF
(8)
mVpp
VIN = 3.7 V, VBST = 5.6 V,
VNEG = –5.4V
(8)
ICL_VNEG
mV
1.5%
PGRISING
ηCP
V
50
Output accuracy
VNEG
–1
Minimum output voltage
Output voltage step size
mV
1
ms
40
Ω
CP_VNEG Pull-Up Enabled,
CP_VNEG Disabled, VBST > 4.8V
30
Minimum Output voltage
LDO_OREF_TARGET = 000000b
4.0
Maximum Output voltage
LDO_OREF_TARGET = 101000b
6.0
V
50
mV
(8)
LCD GAMMA REFERENCE OUTPUT (LDO_OREF)
Output voltage step size
ILOAD_LDO_OREF < 5 mA, VOREF=
5.4V
Output accuracy
VOREF
LDO_OREF line transient response
(8)
LDO_OREF load transient
DC load regulation
PGRISING
(7)
(8)
8
(8)
–1.5%
1.5%
VIN + 500 mVp-p AC Square
Wave, 100 mV/µs 200 Hz at 5 mA,
CIN = 10 µF
–50
50
mV
5 mA to 50 mA load transient @ 2
µs TRISE/FALL, CIN = 10 µF
–50
50
mV
20
mV
1 mA ≤ ILOAD_LDO_OREF ≤
ILOAD_LDO_OREF_MAX
(8)
Power good increasing
V
% of target VLDO_OREF
95%
Typical value only for reference.
Limits set by characterization and/or simulation only.
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Electrical Characteristics (continued)
Unless otherwise specified, limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), VIN = 3.6 V,
VPOS = VOREF = 5.4 V, VNEG = –5.4 V, VBST = 5.7 V, VCONT = 3.3V.
PARAMETER
TEST CONDITION
MIN
% of target VLDO_OREF
TYP
MAX
UNIT
PGFALLING
Power good decreasing
IOREF_MAX
Maximum output current
50
mA
ICL_OREF
Output current limit
80
mA
VBIASBST = 5.8 V, VOREF = 5.5 V,
COREF = 10 µF
250
mA
ILOAD_LDO_OREF =
ILOAD_LDO_OREF_MAX, VLDO_OREF =
4.0 V
80
mV
F = 10 Hz to 500 kHz @ Imax/2,
VBST_OUT to VLDO_OREF, 300 mV
minimum headroom
25
dB
IRUSH_PK_OREF
Peak start-up inrush current
(8)
VDO_OREF
LDO_OREF dropout voltage
(9)
PSRROREF
Power supply rejection ratio,
LDO_OREF (8)
tST_OREF
Start-up time, LDO_OREF,
VLDO_OREF = 10% to 90%
RPD_OREF
Output pull-down resistor,
LDO_OREF
90%
COREF = 10 µF, VLDO_OREF = 5.5 V
(8)
LDO_OREF pull-down enabled,
LDO_OREF disabled
130
200
1
ms
270
Ω
LCD CONTROLLER SUPPLY OUTPUT (LDO_CONT)
Output voltage
LDO_CONT_VOUT = 00
1.8
LDO_CONT_VOUT = 01
2.3
LDO_CONT_VOUT = 10
2.8
LDO_CONT_VOUT = 11
VCONT
V
3.3
Output accuracy
Output Voltage = 1.8 V, 1-mA load
–2%
2%
LDO_CONT line transient response
VIN + 500 mVp-p AC Square
Wave, 100 mV/µs 200 Hz at 5 mA
–50
50
mV
LDO_CONT load transient response
5-mA to 80-mA load transient @ 2
µs TRISE/FALL
–50
50
mV
20
mV
(8)
(8)
DC load regulation
(8)
1 mA ≤ ILOAD_LDO_CONT ≤ 80 mA
ICONT_MAX
Maximum output current
ICL_CONT
Output current limit
80
VDO_CONT
LDO_CONT dropout voltage
PSRRLDO_CONT
Power supply rejection ratio,
LDO_CONT (11)
F = 10 Hz to 500 kHz @ Imax/2 VIN
to VLDO_CONT, 300-mV minimum
headroom
tST_CONT
Start-up time, LDO_CONT, VCONT =
10% to 90% (11)
VCONT = 1.8 V
RPD_CONT
Output pull-down resistor,
LDO_CONT
LDO_CONT pull-down enabled,
LDO_CONT disabled
mA
130
(10)
ILOAD = 80 mA, VCONT = 3.3 V
mA
80
25
mV
dB
1
ms
Ω
200
LOGIC INPUTS (PWM, NRST, LCD_EN, SCL, SDA, OTP_SEL)
VIL
Input logic low
0
0.4
VIH
Input logic high
1.2
VIN
V
V
IINPUT
Logic input current
–1
1
µA
0
0.4
V
1
µA
20000
Hz
LOGIC OUTPUTS (SDA, FLAG)
VOL
Output logic low
ILEAKAGE
Output leakage current
IOL = 3 mA
PWM INPUT
ƒPWM_INPUT
PWM input frequency
tMIN
Minimum PWM ON/OFF time
tTIMEOUT
PWM timeout
100
(11)
400
ns
24
ms
(9) VBST – VOREF when VOREF has dropped 100 mV below target.
(10) VIN – VCONT when VCONT has dropped 100 mV below target.
(11) Limits set by characterization and/or simulation only.
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I2C Timing Requirements (SDA, SCL)
7.6
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
kHz
ƒSCL
Clock frequency
1
Hold time (repeated) START
condition
0.6
µs
2
Clock low time
1.3
µs
3
Clock high time
600
ns
4
Set-up time for a repeated START
condition
600
ns
5
Data hold time
50
ns
6
Data set-up time
7
Rise time of SDA and SCL
20 + 0.1Cb
300
ns
8
Fall time of SDA and SCL
15 + 0.1Cb
300
ns
9
Set-Up time between a STOP and a
START condition
1.3
Cb
Capacitive load for each bus line
10
(1)
100
ns
µs
200
pF
Limits set by characterization and/or simulation only
Figure 1. I2C Timing Parameters
10
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7.7 Typical Characteristics
90
90
85
85
80
80
Total Efficiency (%)
Boost Efficiency (%)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
75
70
65
60
75
70
65
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
5
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
20
25
30
Load (mA)
35
40
45
50
D002
Figure 3. Backlight Total Efficiency
95
95
90
90
85
85
Total Efficiency (%)
Boost Efficiency (%)
15
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 2. Backlight Boost Efficiency
80
75
70
65
60
80
75
70
65
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
5
10
15
20
25
30
Load (mA)
35
40
45
0
50
5
10
15
D006
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
20
25
30
Load (mA)
35
40
45
50
D007
1235AS-H-220M 22-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 4. Backlight Boost Efficiency
Figure 5. Backlight Total Efficiency
90
90
85
85
80
80
Total Efficiency (%)
Boost Efficiency (%)
10
D001
75
70
65
60
75
70
65
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
D008
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
5
10
15
20
25
30
Load (mA)
35
40
45
50
D009
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
500-kHz Boost SW Frequency
Figure 6. Backlight Boost Efficiency
Figure 7. Backlight Total Efficiency
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Typical Characteristics (continued)
90
90
85
85
80
80
Total Efficiency (%)
Boost Efficiency (%)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
75
70
65
75
70
65
60
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
5
10
15
20
25
30
Load (mA)
35
40
45
0
50
5
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
3
2.8
2.8
2.6
2.6
2.4
2.4
2.2
2.2
IVIN (mA)
IVIN (mA)
20
25
30
Load (mA)
35
40
45
50
D011
Figure 9. Backlight Total Efficiency
3
2
1.8
1.6
2
1.8
1.6
1.4
1.4
VIN 2.7V
VIN 3.7V
VIN 5.0V
1.2
VIN 2.7V
VIN 3.7V
VIN 5.0V
1.2
1
1
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
5
10
15
D003
No load on LCD Bias
2P6S LED Configuration
500-kHz BL Boost SW Frequency
20
25
30
Load (mA)
35
40
45
50
D012
No load on LCD Bias
2P6S LED Configuration
1-MHz BL Boost SW Frequency
Figure 10. Device Current Consumption, Backlight Driving
Figure 11. Device Current Consumption, Backlight Driving
22
0.28
21
0.26
20
0.24
VHEADROOM (V)
VOUT (V)
15
VLF403210MT-100M 10-µH Inductor
2P6S LED Configuration
1-MHz Boost SW Frequency
Figure 8. Backlight Boost Efficiency
19
18
17
16
0.22
0.2
0.18
0.16
0.14
VIN 2.7V
VIN 3.7V
VIN 5.0V
15
VIN 2.7V
VIN 3.7V
VIN 5.0V
0.12
14
0.1
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
2
4
6
8
D004
2P6S LED Configuration
10 12 14 16 18 20 22 24 26
LED Current (mA)
D005
2P6S LED Configuration
Figure 12. Backlight Boost Output Voltage
12
10
D010
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Figure 13. LED Driver Headroom Voltage
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Typical Characteristics (continued)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
27
0.2
VIN 2.7V
VIN 3.7V
VIN 5.0V
0.18
0.16
24
21
LED Current (mA)
Mismatch (%)
0.14
0.12
0.1
0.08
0.06
18
15
12
9
0.04
6
0.02
3
VIN 2.7V
VIN 3.7V
VIN 5.0V
0
0
0
2
4
6
8
0
10 12 14 16 18 20 22 24 26
LED Current (mA)
D013
Figure 14. LED Current Matching
750
1000 1250 1500 1750 2000 2250
Step (DEC)
D014
Figure 15. LED Current, Linear Control
27
100
24
95
21
90
85
Efficiency (%)
18
15
12
9
80
75
70
65
6
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
3
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
0
0
250
500
750
0
1000 1250 1500 1750 2000 2250
Step (DEC)
D015
I2C Brightness Control
20
40
60
80 100 120
Load (mA)
140
160
180
200
D016
VBST set to 5.2 V
Figure 16. LED Current, Exponential Control
Figure 17. LCD Boost Efficiency
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
500
I2C Brightness Control
VLF403210MT-100M 10-µH Inductor
1-MHz BL Boost SW Frequency
2P6S LED Configuration
LED Current (mA)
250
80
75
70
80
75
70
65
65
60
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
20
40
60
80 100 120
Load (mA)
140
160
180
VBST set to 5.5 V
200
0
20
D017
40
60
80 100 120
Load (mA)
140
160
180
200
D018
VBST set to 5.9 V
Figure 18. LCD Boost Efficiency
Figure 19. LCD Boost Efficiency
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Typical Characteristics (continued)
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
80
75
70
65
80
75
70
65
60
60
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
50
50
0
10
20
30
40
50
Load (mA)
60
70
80
0
10
20
VNEG set to –5 V
5.3
95
5.28
90
5.26
85
5.24
80
5.22
VBST (V)
Efficiency (%)
60
70
80
D020
Figure 21. VNEG Efficiency
100
75
70
65
5.2
5.18
5.16
60
5.14
VIN 2.7V
VIN 3.7V
VIN 5.0V
55
VIN 2.7V
VIN 3.6V
VIN 4.3V
5.12
50
5.1
0
10
20
30
40
50
Load (mA)
60
70
80
0
50
100
150
D021
VNEG set to –6 V
200 250 300
Load (mA)
350
400
450
500
D022
VBST set to 5.2 V
Figure 22. VNEG Efficiency
Figure 23. LCD Boost Load Regulation
5.6
6
5.58
5.98
5.56
5.96
5.54
5.94
5.52
5.92
VBST (V)
VBST (V)
40
50
Load (mA)
VNEG set to –5.5 V
Figure 20. VNEG Efficiency
5.5
5.48
5.46
5.9
5.88
5.86
5.44
5.84
VIN 2.7V
VIN 3.6V
VIN 4.3V
5.42
VIN 2.7V
VIN 3.6V
VIN 4.3V
5.82
5.4
5.8
0
50
100
150
200 250 300
Load (mA)
350
400
450
500
0
50
D023
VBST set to 5.5 V
100
150
200 250 300
Load (mA)
350
400
450
500
D024
VBST set to 5.9 V
Figure 24. LCD Boost Load Regulation
14
30
D019
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Figure 25. LCD Boost Load Regulation
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Typical Characteristics (continued)
-4.9
-5.4
-4.92
-5.42
-4.94
-5.44
-4.96
-5.46
-4.98
-5.48
VNEG (V)
VNEG (V)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
-5
-5.02
-5.04
-5.5
-5.52
-5.54
-5.06
-5.56
VIN 2.7V
VIN 3.7V
VIN 5.0V
-5.08
VIN 2.7V
VIN 3.7V
VIN 5.0V
-5.58
-5.1
-5.6
0
10
20
30
40
50
Load (mA)
60
70
80
0
10
VNEG set to –5 V
40
50
Load (mA)
60
70
80
D026
Figure 27. VNEG Load Regulation
-5.9
5.05
-5.92
5.04
-5.94
5.03
-5.96
5.02
-5.98
5.01
VPOS (V)
VNEG (V)
30
VNEG set to –5.5 V
Figure 26. VNEG Load Regulation
-6
-6.02
5
4.99
4.98
-6.04
-6.06
4.97
VIN 2.7V
VIN 3.7V
VIN 5.0V
-6.08
VIN 2.7V
VIN 3.7V
VIN 5.0V
4.96
4.95
-6.1
0
10
20
30
40
50
Load (mA)
60
70
0
80
10
20
30
D027
VNEG set to –6 V
40
50
60
Load (mA)
70
80
90
100
D028
VPOS set to 5 V
Figure 28. VNEG Load Regulation
Figure 29. VPOS Load Regulation
5.55
6.05
5.54
6.04
5.53
6.03
5.52
6.02
5.51
6.01
VPOS (V)
VPOS (V)
20
D025
5.5
5.49
5.48
6
5.99
5.98
5.47
5.97
VIN 2.7V
VIN 3.7V
VIN 5.0V
5.46
VIN 2.7V
VIN 3.7V
VIN 5.0V
5.96
5.45
5.95
0
10
20
30
40
50
60
Load (mA)
70
80
VPOS set to 5.5 V
90
100
0
10
D029
20
30
40
50
60
Load (mA)
70
80
90
100
D030
VPOS set to 6 V
Figure 30. VPOS Load Regulation
Figure 31. VPOS Load Regulation
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Typical Characteristics (continued)
5.05
5.55
5.04
5.54
5.03
5.53
5.02
5.52
5.01
5.51
VOREF (V)
VOREF (V)
Ambient temperature is 25°C unless otherwise noted. Backlight load is the sum of LED1 and LED2 current. Backlight Total
Efficiency defined as PLED / PIN, where PLED is actual power consumed in LEDs.
5
4.99
4.98
5.5
5.49
5.48
4.97
5.47
VIN 2.7V
VIN 3.7V
VIN 5.0V
4.96
VIN 2.7V
VIN 3.7V
VIN 5.0V
5.46
4.95
5.45
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
5
VOREF set to 5 V
1.85
6.04
1.84
6.03
1.83
6.02
1.82
6.01
1.81
VCONT (V)
VOREF (V)
20
25
30
Load (mA)
35
40
45
50
D032
Figure 33. VOREF Load Regulation
6.05
6
5.99
5.98
1.8
1.79
1.78
5.97
1.77
VIN 2.7V
VIN 3.7V
VIN 5.0V
5.96
VIN 2.7V
VIN 3.7V
VIN 5.0V
1.76
5.95
1.75
0
5
10
15
20
25
30
Load (mA)
35
40
45
50
0
10
20
30
D033
VOREF set to 6 V
40
50
Load (mA)
60
70
80
D034
VCONT set to 1.8 V
Figure 34. VOREF Load Regulation
Figure 35. VCONT Load Regulation
2.85
3.35
2.84
3.34
2.83
3.33
2.82
3.32
2.81
3.31
VCONT (V)
VCONT (V)
15
VOREF set to 5.5 V
Figure 32. VOREF Load Regulation
2.8
2.79
2.78
3.3
3.29
3.28
2.77
3.27
VIN 3.7V
VIN 5.0V
2.76
VIN 3.7V
VIN 5.0V
3.26
2.75
3.25
0
10
20
30
40
50
Load (mA)
60
70
80
0
10
20
D035
VCONT set to 2.8 V
30
40
50
Load (mA)
60
70
80
D036
VCONT set to 3.3 V
Figure 36. VCONT Load Regulation
16
10
D031
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Figure 37. VCONT Load Regulation
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8 Detailed Description
8.1 Overview
The LM3631 is a single-chip complete LCD power and backlight solution. It can drive up to two LED strings with
up to 8 LEDs each (up to 27 V typ.), with a maximum of 25 mA per string. The power for the LED strings comes
from a integrated asynchronous backlight boost converter with two selectable switching frequencies (500 kHz or
1 MHz) to optimize performance or solution area. LED current is regulated by two low-headroom current sinks.
Automatic voltage scaling adjust the output voltage of the backlight boost converter to minimize the LED driver
head room voltage.
The LCD bias power portion of the LM3631 consists of an LCD bias boost converter, inverting charge pump, and
three integrated LDOs. The device can generate all the required voltages for a LCD panel:
1. The LCD positive bias voltage VPOS (up to 6V). VPOS voltage is post-regulated from the LCD bias boost
converter output voltage.
2. LCD negative bias voltage VNEG (down to –6 V). VNEG is generated from the LCD bias boost converter output
using a regulated inverting charge pump.
3. The third output VOREF can supply the LCD gamma (or VCOM reference) voltage. VOREF is post-regulated
from the LCD bias boost converter output voltage.
4. The fourth output VCONT can be used to supply the display controller. VCONT regulator is powered from the
VIN input.
The LM3631 flexible control interface consists from nRST active low reset input, LCD_EN enable input, PWM
input for content adaptive backlight control (CABC), and an I2C-compatible interface. In applications with limited
IO pin count the LCD_EN input pin function can be replaced with the LCD_EN I2C register bit. In this case the
LCD_EN pin needs to be connected to ground. OTP_SEL input can be used to select from two different factoryprogrammed default One Time Programmable Memory (OTP) settings. The default OTP settings can be
overwritten using the I2C-compatible interface. Programmable settings include LED ramp up/down profiles, LED
output current and brightness control modes, enabling/disabling individual power supply outputs, and
programmable LCD output power up/down sequencing. Open drain FLAG output can be used to notify host
processor from various power-good signals or fault conditions.
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VLED+
COG
4-16 LED Backlight
VCONT
VPOS
VNEG
VOREF(Gamma/VCOM)
Overview (continued)
LCD
Diffuser
LCD Module
LCD Panel
Connector
Image Data
LED
Sinks1,2
CABC
PWM
LM3631
System
I2C Bus
Prox
EN_LCD
nRST
ALS
Apps Processor
V+ BUS
Main Board
Figure 38. System Example
18
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8.2 Functional Block Diagram
Up to 8 LEDs/String
with up to 27 V
VIN
+
CIN
COUT
-
VIN
SW
Programmable
Overvoltage Protection
Reference and
Thermal Shutdown
Programmable Current
Limit
nRST
OTP_SEL
FLAG
VOUT
Global Active-low
Reset
Backligh Boost Converter
Programmable
500 kHz/1 MHz
Oscillator
OTP Memory
VHR Voltage
Feedback
LED1
LED2
LED String Open/Short
Detection
FLAG Control
(Power OK or Fault)
GND_SW
Backlight LED Control
1. 11-bit brightness
adjustment
PWM
LED Drivers
PWM Detector
With
Low Pass Filter
2. Exponential/Linear
Dimming
3. LED Current
Ramping
VIN
SDA
SCL
I2C Compatible
Interface
LDO_CONT (Panel
controller)
LDO_CONT
LDO_OREF (Gamma
Reference, VCOM, VCS)
LDO_OREF
C1
Power OK
LCD_EN
CP_VNEG
(LCD Negative Bias)
Enable
LCD Bias Output
Sequencing Control
C2
CP_VNEG
LCD Boost Converter
LDO_VPOS
(LCD Postive Bias)
Internal Logic
AGND
VIN
BST_SW
GND_BST_SW
BST_OUT
LDO_VPOS
PGND
+
-
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8.3 Features Description
8.3.1 Backlight
The backlight is enabled by setting the BL_EN = 1 and a brightness value higher than zero. LCD bias power rails
need to reach their target voltages before the backlight can be started. Note that all bias voltages don't need to
be enabled to start up the backlight. For example, if only VPOS and VNEG are required, the backlight can be
enabled once these voltages have reach their target voltages. In this case VCONT and VOREF can be disabled. If
all four outputs (LDO_CONT, LDO_OREF, CP_VNEG, and LDO_VPOS) are disabled, the backlight can be
enabled once the LCD biast boost converter has settled. The LCD bias boost is always enabled when the
LCD_EN pin or bit is set high.
When the brightness value is '0', or BL_EN bit is ‘0’, the backlight is disabled. The BL_EN bit is '1' by default. The
backlight can be disabled at any time by setting the brightness value to zero or by writing the BL_EN bit to ‘0’.
LED driver LED2 can be separately enabled and disabled from the I2C register. LED driver LED1 is always
enabled when the backlight is turned on.
Table 2. Backlight Control
BL_EN BIT
BRIGHTNESS VALUE (I2C AND/OR
EXTERNAL PWM)
BACKLIGHT ON/OFF
0
0
OFF
0
≥1
OFF
1
0
OFF
1
≥1
ON
8.3.1.1 Backlight Brightness Control
Brightness can be controlled either by the I2C brightness register, with an external PWM control, or a
combination of both. BRT_MODE bits select the brightness control mode. Different brightness control modes are
shown in Table 3.
When controlling brightness through I2C, registers 0x01 and 0x02 are used. Registers 0x01 and 0x02 hold the
11-bit brightness data. Register 0x02 contains the 8 MSBs, and register 0x01 contains the 3 LSBs. The LED
current only transitions to the new level after a write is done to register 0x02.
When controlling brightness through I2C, setting brightness value to '0' shuts down the backlight. When
controlling the brightness with PWM input, if PWM input is low for a certain period of time (24 ms typ.), the
backlight shuts down. When using the combination of a PWM input and the I2C register, either option shuts down
the backlight.
NOTE
The backlight does not start before the LCD bias start-up sequence is finished even if
BL_EN bit is '1' and the brightness setting is ≥ 1.
Table 3. Brightness Control
20
BRT_MODE bits
BRIGHTNESS CONTROL
00
I2C register used for brightness control
01
PWM input duty cycle used for brightness control
10
I2C register code multiplied with PWM duty cycle before sloping
11
Sloped I2C register code multiplied with PWM duty cycle
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Up to 8 LEDs/string
with up to 27V
Up to 8 LEDs/string
with up to 27V
VOUT
VOUT
Digital
Domain
Analog
Domain
Digital
Domain
High Efficiency
Boost Regulator
Analog
Domain
High Efficiency
Boost Regulator
EN_ADVANCED_SLOPE
EN_ADVANCED_SLOPE
min
min
PWM input signal
DACi
2
Sloper
I C BRT Reg
Curve
bending
ILED1
ILED2
DACi
PWM
detector
Sloper
Curve
bending
ILED1
Mapper
Dither
DAC
Dither
DAC
ILED2
Mapper
Driver_1
Driver_1
HYSTERESIS
[1:0]
MAPPER_SEL
SLOPE[3:0]
Driver_2
MAPPER_SEL
SLOPE[3:0]
Driver_1
DITHER[3:0]
DITHER[3:0]
Figure 39. Brightness Control with
BRT_MODE bit 00
Figure 40. Brightness Control with
BRT_MODE bit 01
Up to 8 LEDs/string
with up to 27V
Up to 8 LEDs/string
with up to 27V
VOUT
Digital
Domain
Analog
Domain
VOUT
Digital
Domain
High Efficiency
Boost Regulator
EN_ADVANCED_SLOPE
EN_ADVANCED_SLOPE
Analog
Domain
High Efficiency
Boost Regulator
MAPPER_SEL
min
DACi
2
I C BRT Reg
Sloper
Curve
bending
ILED1
min
ILED2
Mapper
DACi
2
DAC
Dither
Sloper
I C BRT Reg
Driver_1
Curve
bending
ILED1
Mapper
DAC
PWM input signal
PWM
detector
Dither
ILED2
Driver_1
MAPPER_SEL
SLOPE[3:0]
Driver_1
SLOPE[3:0]
Driver_2
DITHER[3:0]
HYSTERESIS
[1:0]
DITHER[3:0]
PWM input signal
PWM
detector
HYSTERESIS
[1:0]
Figure 41. Brightness Control with
BRT_MODE bit 10
Figure 42. Brightness Control with
BRT_MODE bit 11
8.3.1.1.1 LED Current With Brightness Selection '00'
When LED brightness is controlled from the I2C brightness registers, the 11-bit brightness data directly controls
the LED current in LED1 and LED2. LED mapping can be selected as either linear or exponential. When this
mode is selected setting PWM input to 0 does not disable the backlight.
With exponential mapping the 11-bit code-to-current response is approximated by the equation:
ILED = 50 µA × 1.003040572I2C BRT CODE (for codes > 0)
(1)
This equation is valid for I2C brightness codes between 1 and 2047. Code 0 disables the backlight. Resolution
achieved at the output is maximum 16-bit at low brightness levels and additional 1 bit can be achieved with the
dithering resulting in up to 17-bit output resolution. Step sizes increase when the current increases with the
exponential control.
Figure 43 and Figure 44 detail the exponential response of the LED current vs. brightness code. Figure 43 shows
the response on a linear Y axis while Figure 44 shows the response on a log Y axis to show the low current
levels at the lower codes.
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25
100
20
LED Current (mA)
LED Current (mA)
10
15
10
1
0.1
5
0
0.01
0
256
512
768
1024
1280
1536
1792
2048
0
256
11-Bit Brightness Code
512
768
1024
1280
1536
1792
2048
11-Bit Brightness Code
C001
Figure 43. Exponential Response of the LED Current vs
Brightness Code
C002
Figure 44. Response of the LED Current vs Brightness
Code on a Log Y Axis
With linear mapping the 11-bit code to current response is approximated by the equation:
ILED = 37.67 µA + 12.33 µA × I2C BRT CODE (for codes > 0)
(2)
This equation is valid for codes between 1 and 2047. Code 0 disables the backlight.
8.3.1.1.2 LED Current With Brightness Selection '01'
When LED brightness is controlled from the PWM, the PWM duty cycle directly controls the LED current in LED1
and LED2. LED mapping can be selected to be either linear or exponential. When this mode is selected, setting
the I2C brightness register to 0 does not disable the backlight.
With exponential mapping the PWM duty cycle-to-current response is approximated by the equation:
ILED = 50 µA × 1.0030405722047 × PWM D/C (PWM D/C ≠ 0)
(3)
Equation 3 is valid for PWM duty cycles other than 0. Duty cycle 0 disables the backlight.
With linear mapping the PWM duty cycle-to-current response is approximated by the equation:
ILED = 37.67 µA + (12.33 µA × 2047 × PWM D/C) (PWM D/C ≠ 0)
(4)
Equation 4 is valid for PWM duty cycles other than 0. Duty cycle 0 disables the backlight.
8.3.1.1.3 LED Current With Brightness Selections '10' and '11'
When LED brightness is controlled with the combination of the I2C register and the PWM duty cycle, the
multiplication result of I2C register value and PWM duty cycle controls the LED current in LED1 and LED2. LED
mapping can be selected as either linear or exponential.
With exponential mapping the multiplication result-to-current response is approximated by the equation:
ILED = 50 µA × 1.003040572I2C BRT CODE × PWM D/C
(5)
Equation 5 is valid for brightness values other than 0. Brightness value (PWM D/C or I2C BRT CODE) 0 disables
the backligh.
With linear mapping the PWM duty cycle-to-current response is approximated by the equation:
ILED = 37.67 µA + (12.33 µA × I2C BRT CODE × PWM D/C)
(6)
Equation 6 is valid for brightness values other than 0. Brightness value (PWM D/C or I2C BRT CODE) 0
programs 0 current.
The key difference between the two brightness modes is how the PWM input affects the LED output current.
When brightness mode is '10', changing PWM value causes LED current to slope form the current value to the
new value. With the brightness setting '11', a change in PWM value causes an instant change in the LED current.
This makes brightness setting '11' suitable for CABC operation.
8.3.1.2 Linear Slope and Advanced Slope
Sloper smooths the transition from one brightness value to another. Slope time can be adjusted from 0 ms to
4000 ms with SLOPE[3:0] bits. Slope time is used for sloping up and down. Slope time always remains the same
regardless of the amount of change in brightness. Advanced slope makes brightness changes smooth for the
human eye.
22
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Dithering function further smooths the slope by jumping between two adjacent current values. Dithering
frequency can be programmed with DITHER_FREQ_SEL[3:0] bits. Dithering function can be disabled with
DISABLE_DITHER bit.
Brightness
Sloper
Input
Brightness
Output
Time
Normal
slope
Steady state with or without dithering
Advanced
slope
Time
If dither is enabled it will
be used during transition
to enable smooth effect.
Slope
Time
Figure 45. Sloper
Table 4. Slope Times
SLOPE BITS[3:0]
SLOPE TIME (ms)
0000
0, slope function disabled, immediate brightness change
0001
1
0010
2
0011
5
0100
10
0101
20
0110
50
0111
100
1000
250
1001
500
1010
750
1011
1000
1100
1500
1101
2000
1110
3000
1111
4000
8.3.1.3 Mapper
The mapper block maps the digital word into current code which is set for the LED driver. The user can select
whether the mapping is exponential or linear with the LINEAR_MAPPER bit.
Exponential control is tailored to the response of the human eye such that the perceived change in brightness
during ramp up or ramp down is linear.
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8.3.1.4 PWM Detector and PWM Input
The PWM detector block measures the duty cycle in the PWM pin. The PWM period is measured from the
rising/falling edge to the next rising/falling edge. PWM edge detection can be selected as rising or falling from
register 0x08 bit 7. PWM polarity can be changed with register 0x08 bit 6. The PWM input block timeout is 24 ms
after the last rising edge, which should be taken into account for 0% and 100% brightness settings (for setting
100% brightness, high level of PWM input signal should be at least 24 ms). Minimum on and off times for PWM
input signal are 400 ns.
PWM input resolution is defined by the PWM detector sampling rate (24 MHz typ.). Resolution depends on the
input signal frequency — for example, with 10-kHz PWM input frequency the resolution is 11-bit. If a higher input
frequency is used, the resolution is lower. The minimum recommended PWM frequency is 100 Hz, and maximum
recommended PWM frequency is 20 kHz.
PWM hysteresis selection sets the minimum allowable change to the input. If a smaller change is detected, it is
ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in
the input signal. Hysteresis is selected with HYSTERESIS bits in register 0x08. Using a higher hysteresis setting
is recommended with high PWM input frequencies.
The PWM detector is disabled in I2C brightness mode to minimize current consumption.
8.3.2 Backlight Boost Converter
The LM3631 can drive two LED strings with up to 8 LEDs per string. The high voltage required by the LED
strings is generated with an asynchronous backlight boost converter. An adaptive voltage control loop
automatically adjusts the output voltage based on the voltage over the LED drivers LED1 and LED2.
The LM3631 has two switching frequency modes (high and low). These are set via the Boost Frequency Select
bit. The nominal low- and high-frequency set points are 500 kHz and 1 MHz, respectively. Operation in lowfrequency mode results in better efficiency at lighter load currents due to the decreased switching losses.
Operation in high-frequency mode gives better efficiency at higher load currents due to the reduced inductor
current ripple and the resulting lower conduction losses in the MOSFETs and inductor.
LED1
LED2
VOUT
SW
BOOST_SEL_I [1:0]
BOOST_SEL_P [1:0]
FB Divider
BL_BST_OVP [1:0]
VHR
(Feedback)
OVP
LIGHT
LOAD
R
R
S
-
GM
R
+
VREF
R
GATE
DRIVER
OCP
BL_BST_FREQ [0]
OFF/BLANK TIME
PULSE GENERATOR
CURRENT RAMP
GENERATOR
BOOST OSCILLATOR
INDUCTOR [0]
GM
ISENSE 25m
CURRENT
SENSE
LED Driver
PEAK_CURR_LIM [1:0]
Figure 46. Backlight Boost Block Diagram
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8.3.2.1 Headroom Voltage
Saturation voltage of the LED drivers depends on the output current setting. In order to optimize LED drive
efficiency, while maintaining good LED current accuracy, the LED-driver-regulated headroom voltage (VHR) is
kept slightly above LED driver saturation voltage. To maintain good LED current accuracy with lower current
settings, LED driver size is scaled down for the lower current settings (below 1/16 of max current). In order to
ensure that both current sinks remain in regulation when there is a mismatch in string voltages, the boost
converter output voltage is regulated based on the LED driver with lower headroom voltage. For example, if the
LEDs connected to LED1 require 25 V at the programmed current, and the LEDs connected to LED2 require
25.5 V at the programmed current, the voltage at LED1 is VHR + 0.5 V, and the voltage at LED2 is VHR.
0.3
0.25
VHR (mV)
0.2
0.15
0.1
0.05
0
0.01
0.1
1
10
String LED Current (mA)
100
D001
Figure 47. Regulated Headroom vs LED Current
8.3.2.2 Automatic Switching Frequency Shift
To take advantage of frequency vs load dependent losses, the LM3631 has an automatic frequency-select mode.
In automatic frequency-select mode the switching-frequency bit is automatically changed based on the
programmed LED current. The threshold (or LED Brightness Code) at which the frequency switchover occurs is
programmable via the AUTOFREQ_THRESHOLD. This register contains an 8-bit code which is compared
against the 8 MSB’s of the brightness code (BRT[10:3]). When BRT[10:3] > AUTOFREQ_THRESH[7:0], the
Boost Frequency Select Bit is set to a ‘1’, and the device operates in high-frequency mode. When BRT[10:3] ≤
AUTOFREQ_THRESH[7:0], the Frequency Select Bit is automatically set to ‘0’, and the device operates in lowfrequency mode.
When automatic frequency-select mode is disabled, the switching frequency operates at the programmed highor low-frequency setting across the entire LED current range.
8.3.2.3 Inductor Select Bit
The LM3631 can operate with a 10-µH or 22-µH inductor. However, the LM3631 backlight boost-control loop
requires adjustment of internal loop compensation parameters based on the inductance value selected for the
application. This is done through the INDUCTOR bit. For 10-µH inductors, the INDUCTOR bit must be set to '1'.
For a 22-µH inductor, the INDUCTOR bit should be set to ‘0’.
8.3.2.4 PI-Compensator
The LM3631 backlight boost converter internal loop-compensation parameters (SEL_I[1:0] and SEL_P[1:0]) are
factory-selected to optimize performance and stability for most backlight configurations. These settings should
not need adjustment. If these settings are changed, application needs to be carefully evaluated to ensure stability
and performance in all operating conditions.
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8.3.3 Backlight Protection and Faults
8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection
The LM3631 provides an OVP that monitors the LED boost output voltage (VOUT) and protects OUT and SW
from exceeding safe operating voltages. The OVP threshold can be set with the I2C register bits. The OVP limit
can be set to 17 V, 21 V, 25 V, or 29 V. The OVP monitor differentiates between two overvoltage conditions and
responds accordingly as outlined below:
Case 1 (OVP Threshold hit and (VLED1 and VLED2 ) > 40 mV): In steady-state operation with VOUT near the
OVP threshold (VOVP), a rapid change in VIN or brightness code can result in a momentary transient
excursion of VOUT above the OVP threshold. In this case the boost circuitry is disabled until VOUT
drops below VOVP - VHYST. Once this happens the boost is re-enabled, and steady state regulation
can commence. If the OVP pulse length is over 1 ms, an OVP fault is set.
Case 2 (OVP Threshold hit and (VLED1 and VLED2 ) < 40 mV): When one or all of the LED strings is open,
the boost converter drives VOUT above VOVP and at the same time the open string(s) current sink
headroom voltage(s) drops to 0. When LM3631 detects three pulses (if VOUT > VOVP and (VLED1 or
VLED2) < 40 mV), the OVP Fault flag (BL_OVPFLT) is set. If the OVP pulse length is over 1 ms, an
OVP fault is set. The flag is cleared with rising LCD_EN or an I2C write.
8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault
The LM3631 has 4 selectable OCP thresholds. The programmable options are 600 mA, 700 mA, 800 mA, or 900
mA. The OCP threshold is a cycle-by-cycle current limit detected in the low-side NFET. Once the threshold is
reached, the NFET turns off for the remainder of the switching period.
8.3.3.2.1 Overcurrent Protection Fault Flag (BL_OCPFLT)
If enough OCP threshold events occur the Overcurrent Protection Fault (BL_OCPFLT) flag is set. To avoid
transient conditions from inadvertently setting the BL_OCPFLT Flag, a Pulse Density Counter monitors OCP
threshold events over a 128-µs period. If the Pulse Density Counter counts 2 or more OCP events during the
128-µs period, the pulse density count is considered true. If 8 consecutive 128-µs periods occur where the pulse
density count is true (1024 µs total), the BL_OCPFLT fault is set. Fault is cleared by rising edge of the LCD_EN
or an I2C write '1' to the BL_OCPFLT bit.
NOTE
The OCP signaling is ignored for 4 ms after the backlight boost is started or the brightness
value is changed.
8.3.3.2.2 Short Circuit Fault Flag (BL_SCFLT)
If an OCP fault has occurred, and the headroom voltage is too low (VLED1 or VLED2 < 40 mV), the Short Circuit
Fault (BL_SCFLT) fault is set, and all power is shut down. The fault must be cleared to enable power — it is
cleared by the rising edge of the LCD_EN or by an I2C write '1' to the BL_SCFLT bit.
NOTE
The OCP signaling is ignored for 4 ms after the backlight boost is started or the brightness
value is changed.
8.3.4 LCD Bias
8.3.4.1 Display Bias Power (VPOS, VNEG, VOREF)
A single high-efficiency boost converter provides a positive voltage rail, VBST_OUT, which serves as the power rail
for the LCD VPOS and VNEG biases, as well as for an additional regulated output VOREF. This can be used to
supply the display gamma reference, VCOM and VCS voltages.
• The VPOS output LDO, LDO_VPOS, has a programmable range from 4 V up to 6 V with 50-mV steps and can
supply up to 100 mA.
• The VNEG output, CP_VNEG, is generated from a regulated, inverting charge pump and has an adjustable
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range of –6 V up to –4 V with 50-mV steps and a maximum load of 80 mA. During start-up there is a
minimum delay of 500 µs due to biasing the flycap.
The VOREF output LDO, LDO_OREF, has programmable range from 4 V to 6 V, further adjustable in 50-mV
increments and can supply up to 50 mA.
The boost voltage can be selected from the an I2C register. When selecting suitable boost-output voltage, the
following estimation can be used VBST = max(VLDO_VPOS, |VCP_VNEG|,VLDO_OREF) + 200 mV (with lower currents) or
+ 300 mV (with higher currents). When the device input voltage (VIN) > sets the LCD boost output voltage, the
boost voltage goes to VIN + 100 mV.
Table 5. LCD Boost VOUT
LCD_BOOST_VOUT BITS
LCD BOOST OUTPUT VOLTAGE (V)
000 000
4.50
000 001
4.55
000 010
4.60
000 011
4.65
000 100
4.70
000 101
4.75
000 110
4.80
...
...
011 111
6.05
100 000
6.10
100 001
6.15
100 010
6.20
100 011
6.25
100 100
6.30
100 101
6.35
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LCD Controller
Supply Output
LDO_CONT
VIN
BST_SW
VIN
+
±
VCONT
LDO_CONT
10 µF
LCD Bias Boost
Converter
BST_OUT
LCD Gamma
Reference Output
LDO_OREF
LDO_OREF
VOUT
10 µF
CIN
10 µF
VOREF
10 µF
LCD Positive
Bias Output
LDO_VPOS
VPOS
LDO_VPOS
10 µF
C1
10 µF
C2
LCD Negative
Bias Output
CP_VNEG
VNEG
CP_VNEG
10 µF
Figure 48. LCD Boost
8.3.4.2 Display Bias Power Sequencing (VPOS, VNEG, VOREF, VCONT)
The LM3631 supports configurable output power-up and power-down timing for VPOS, VNEG, VCONT and VOREF.
The LED current sinks can start up after the bias voltages power ok signals (or after the timeout period has
elapsed (20 ms typ.)) and shuts down before the bias power-down sequence begins. The bias power-down
sequence does not start until after the LED current sinks have turned off.
The trigger for the power-up sequence is either a change from logic LOW to logic HIGH on the LCD_EN pin or
the Display Bias Outputs bit. The trigger for the power-down sequence is either a change from logic HIGH to
logic LOW on the LCD_EN pin or the Display Bias Outputs bit. The pull-downs or pull-ups for each output, if
enabled, disengage immediately upon start-up of each respective output and re-engages immediately upon
shutdown of each respective output.
Table 6. Start-Up and Shutdown Delays
28
START-UP DELAY SETTING (LDO_OREF_SU_DLY,
LDO_VPOS_SU_DLY, CP_VNEG_SU_DLY) (ms)
SHUTDOWN DELAY SETTING (LDO_OREF_SD_DLY,
LDO_VPOS_SD_DLY, CP_VNEG_SD_DLY) (ms)
0000 = 0
0000 = 0
0001 = 1
0001 = 1
0010 = 2
0010 = 2
0011 = 3
0011 = 3
0100 = 4
0100 = 4
0101 = 5
0101 = 5
0110 = 6
0110 = 6
0111 = 7
0111 = 7
1000 = 8
1000 = 8
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Table 6. Start-Up and Shutdown Delays (continued)
START-UP DELAY SETTING (LDO_OREF_SU_DLY,
LDO_VPOS_SU_DLY, CP_VNEG_SU_DLY) (ms)
SHUTDOWN DELAY SETTING (LDO_OREF_SD_DLY,
LDO_VPOS_SD_DLY, CP_VNEG_SD_DLY) (ms)
1001 = 9
1001 = 9
1010 = 10
1010 = 10
1011 = 11
1011 = 11
1100 = 12
1100 = 12
1101 = 13
1101 = 13
1110 = 14
1110 = 14
1111 = 15
1111 = 15
LDO_CONT start-up/shutdown delay has a 3-bit programmable range.
Table 7. LDO_CONT Start-Up/Shutdown Delays
LDO_CONT START-UP/SHUTDOWN DELAY SETTING
(LDO_CONT_SU_DLY, LDO_CONT_SD_DLY)
START-UP/SHUTDOWN DELAY (ms)
000
0
001
2
010
5
011
10
100
20
101
50
110
100
111
200
LDO_OREF_SD_DLY
ULVO_OK
SU_DLY
LDO_CONT_
SU_DLY
LDO_OREF_
SU_DLY
LDO_VPOS_SD_DLY
VIN
nRST
LCD_EN
LDO_CONT
BST_OUT
LDO_OREF
BST_PWROK
(Internal Signal)
LDO_VPOS
CP_VNEG
BSTOK
LDO_VPOS_SU_DLY
CP_VNEG_SU_DLY
CP_VNEG_
SD_DLY
LDO_CONT_
SD_DLY
Figure 49. General LCD Bias Power Sequence Without Backlight
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Last bias
power OK
LDO_OREF_SD_DLY
ULVO_OK
SU_DLY
LDO_CONT_
SU_DLY
LDO_VPOS_SD_DLY
LDO_OREF_SU_DLY
VIN
nRST
LCD_EN
LDO_CONT
BST_OUT
LCD bias and
Backlight ON
LDO_OREF
BST_PWROK
(Internal Signal)
LDO_VPOS
CP_VNEG
BSTOK
LDO_VPOS_SU_DLY
CP_VNEG_SU_DLY
CP_VNEG_
SD_DLY
LDO_CONT_
SD_DLY
Backlight
LED sinks
turned off
Figure 50. General LCD Bias Power Sequence With Backlight
8.3.4.2.1 Start-Up and Shutdown Delays
SU_DLY
Start-up delay from LCD_EN = HIGH to start up of the internal references, bias, and oscillator.
LDO_CONT_SU_DLY Delay between the time LDO_CONT signal starts to rise ‘HIGH’, and the time before
BST_OUT starts to rise. LDO_CONT delay can be adjusted with LDO_CONT_SU_DLY I2C register
start-up delay bits. In case LDO_CONT is disabled, BST_OUT starts to rise after LCD_EN is set
‘HIGH’.
BSTOK
Bias boost startup delay. Time between the time when BST_OUT voltage starts to rise and the time
when BST_PWROK (internal) signal rises to ‘HIGH’.
LDO_OREF_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and LDO_OREF
signal starts to rise. Delay can be adjusted with I2C register start-up delay bits
LDO_OREF_SU_DLY.
LDO_VPOS_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and LDO_VPOS
signal starts to rise. Delay can be adjusted with I2C register start-up delay bits
LDO_VPOS_SU_DLY.
CP_VNEG_SU_DLY Delay between the time when BST_PWROK signal rises to ‘HIGH’ and CP_VNEG signal
starts to fall. Delay can be adjusted with I2C register start-up delay bits CP_VNEG_SU_DLY. Note
that there is a minimum delay of 500 µs (typ.) due to biasing of the flycap.
CP_VNEG_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when CP_VNEG
signal starts to rise. Delay can be adjusted with I2C register off delay bits CP_VNEG_SD_DLY.
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LDO_VPOS_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when
LDO_VPOS signal starts to fall. Delay can be adjusted with I2C register off delay bits
LDO_VPOS_SD_DLY.
LDO_OREF_SD_DLY Delay between the time when LCD_EN signal is set LOW and the time when
LDO_OREF signals start to fall. Delay can be adjusted with I2C register off delay bits
LDO_OREF_SD_DLY.
LDO_CONT_SD_DLY After last of the LDO_OREF, CP_VNEG, or LDO_VPOS shutdown time has ended
LDO_CONT signal starts to fall in case it is enabled.
8.3.4.2.2 Special Conditions During Display Bias Power Sequencing
Short nRST Condition During Shutdown Sequence If nRST is logic LOW for longer than the deglitch time, all
appropriate outputs are sequenced down completely. If nRST is toggled or is held at logic HIGH
before the all outputs are shutdown, the shutdown sequencing continues to turn off all outputs and
set all the internal registers to the default state. Note that if nRST is toggled or is held at logic HIGH
before all outputs are shut down, and FLAG pin is configured as fault, there are small glitches in the
FLAG line after nRST is set HIGH.
Thermal Fault During Shutdown Sequence A thermal fault, when the die temperature is greater than TSD,
shuts down all outputs. When the die temperature drops by TSD(HYSTERESIS), the outputs can be restarted by toggling LCD_EN or the “LCD_EN” bit of register 0x00.
Backlight Sequence During LCD Bias Start-up Sequence Backlight cannot be enabled before LCD bias startup sequence is complete. If the backlight is enabled (via either the PWM or I2C register) before the
LCD bias start-up sequence is complete, the backlight start-up sequence starts after LCD bias
start-up sequence is complete.
8.3.4.3 Active Discharge
An active discharge is implemented for each output rail (LDO_OREF, LDO_VPOS, LDO_CONT and CP_VNEG)
with internal switch resistance. The discharge function is programmable by I2C interface and is triggered by
LCD_EN = “LOW”. During power-up, each output programmed to be actively discharged (at power-down) is
actively discharged as long as it is not enabled internally.
8.3.4.4 LCD Bias Protection
The LM3631 provides OVP that monitors the LCD Bias boost output voltage (VOUT) and protects BST_OUT and
BST_SW from exceeding safe operating voltages. The OVP threshold can be set with the I2C register bits. If
there is an LCD bias overvoltage fault, an LCD_OVPFLT fault is set. The fault is cleared with the rising edge of
LCD_EN or an I2C write '1' to the LCD_OVPFLT bit.
LDO_VPOS has an OCP that limits the maximum current drawn to 200 mA (typ.). If the fault condition persists
over 2 ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_VPOS_FLT fault is
set. The fault must be cleared to enable power; the fault is cleared with rising edge of LCD_EN or an I2C write '1'
to LDO_VPOS_FLT bit.
LDO_OREF has OCP that limits the maximum current drawn to 80 mA (typ.). If the fault condition persists over 2
ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_OREF_FLT fault is set. The
fault must be cleared to enable powers; the fault is cleared with rising edge of LCD_EN or I2C write '1' to
LDO_OREF_FLT bit.
CP_VNEG has a short-circuit and OVP feature, which monitors the charge-pump voltage.
• If the charge-pump voltage goes 250 mv (typ.) below its target set-point, the charge pump is shut down. If the
OVP persists for 2 ms, all bias outputs are turned off following the normal shutdown sequence, and a
NEG_CP_OVP fault is set. The fault must be cleared, to re-enable the outputs, with the rising edge of
LCD_EN or an I2C write '1' to NEG_CP_OVP bit.
• If the charge-pump voltage goes over –1 V, the charge pump is shut down, and a NEG_CP_SC fault gets set.
The fault must be cleared, to re-enable the outputs, with rising edge of LCD_EN or an I2C write '1' to
NEG_CP_SC.
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8.3.5 Display Controller Power (VLDO_CONT)
The LM3631 supports an additional regulated output VLDO_CONT which can supply, for example, the display’s
controller voltage. The LDO_CONT has a 2-bit programmable range with 1.8-V, 2.3-V, 2.8-V and 3.3-V values
and can supply up to 80 mA. This LDO is powered directly from VIN voltage.
NOTE
When the LDO voltage is set to 2.8 V, VIN voltage must be kept over 2.8 V to ensure LDO
proper functionality. Similarly, when LDO voltage is set to 3.3 V, the battery voltage must
be kept over 3.3 V to ensure LDO proper functionality.
LDO_CONT has an OCP feature. If the OCP fault condition persists over 2 ms, a fault is set. LDO_CONT limits
the current. Fault is cleared with rising edge of LCD_EN or an I2C write '1' to the LDO_CONT_FLT bit.
8.3.6 RESET Register
I2C register 0x14 is the register reset. Writing FFh into this register resets all I2C register values to default values.
Default values are described in Table 1.
8.3.7 nRST Input
The nRST input is a global hardware enable for the LM3631. This pin must be pulled to logic HIGH to enable the
device and the I2C-compatible interface. This pin is high-impedance and cannot be left floating. When this pin is
at logic LOW, the LM3631 is placed in shutdown, the I2C-compatible interface is disabled, and the internal
registers are reset to their default state. It is recommended that VIN has risen above a 2.7-V before setting nRST
HIGH.
8.3.8 FLAG Pin
The FLAG pin can be used as an indicator to the application processor when the LM3631 encounters, for
example, OVP. The fault conditions which set the FLAG pin to pull low can be programmed via I2C. Additionally,
the power-good flag can be set to trigger from the flag for the bias voltages.
The FLAG pin is an open-drain output. When this pin is used, a pullup resistor is needed. If not used, this pin can
be left floating.
Table 8. FLAG Pin Configuration
FLAG PIN CONFIGURATION BITS
FLAG PIN INFORMATION
00
Flag disabled, no flag indication
01
Power-Good state, selectable with Power-Good flag control bits
(PG_FLAG_CTRL)
10
Backlight on state
11
Fault state
8.3.9 Power-Good Flag
The Power-Good flag can be used to indicate an application processor power-good situation of the bias voltages.
The Power-Good flag information can be selected with Power-Good Flag control bits (PG_FLAG_CTRL). This
information can be directed to the FLAG pin with FLAG pin configuration bits.
NOTE
When nRST is pulled low before the power sequence is complete, the Power-Good Flag
indication is triggered even though the condition (described in Table 9) to trigger that the
Power-Good flag is not fulfilled. When the Power-Good configuration is '00' (after last
supply reaches target), LDO_VPOS, CP_VNEG, and LDO_OREF all need to be enabled.
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Table 9. Power-Good Flag Configuration
POWER-GOOD FLAG
CONFIGURATION BITS
FLAG PIN INFORMATION DURING START-UP
FLAG PIN INFORMATION DURING SHUTDOWN
00
Power-Good bit set to '1' after last supply reaches
target
Power-Good bit set to '0' after first supply falls below
target
01
Power-Good bit set to '1' after LDO_VPOS reaches
target
Power-Good bit set to '0' after LDO_VPOS falls below
target
10
Power-Good bit set to '1' after CP_VNEG reaches
target
Power-Good bit set to '0' after CP_VNEG falls below
target
11
Power-Good bit set to '1' after LDO_OREF reaches
target
Power-Good bit set to '0' after LDO_OREF falls below
target
8.3.10 OTP_SEL Pin
The OTP selection pin is dedicated for selection between two different default setups. Setting this pin to VBATT
or GND selects the OTP from where the default setup is loaded. Note that this selection applies only for the
backlight and LCD configuration registers (registers from 0x05h to 0x12h).
8.3.11 Thermal Shutdown
The LM3631 has Thermal Shutdown protection which shuts down the backlight, all bias voltage outputs and
enters standby mode when the die temperature reaches or exceeds 140°C (typ.). When the die temperature falls
below 120°C (typ.), the LM3631 comes out of standby. The I2C interface remains active during a Thermal
Shutdown event. If a TSD fault occurs, TMPFLT fault is set — the fault is cleared by an I2C write '1' to TMPFLT
bit or by setting LCD_EN high.
8.3.12 Undervoltage Lockout
The LM3631 has an undervoltage lockout feature (UVLO), which indicates of the device operation at low input
voltages. If the supply voltage VIN is below the UVLO threshold, a UVLO fault is set. UVLO fault is cleared by an
I2C write '1' to UVLO bit. UVLO does not shut down the outputs.
UVLO rising threshold is 2.6 V (typ.), and UVLO falling threshold is 2.5 V (typ.).
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8.4 Device Functional Modes
8.4.1 Modes of Operation
Shutdown: The LM3631 is in shutdown when nRST pin is low.
Standby:
After nRST pin is set high, and VIN is over UVLO limit, the LM3631 goes into Standby mode. Before
entering Standby mode, references and bias currents are enabled (bias delay typically 200 µs), and
registers are read from OTP (EPROM read delay typically 700 µs). In Standby mode references
and bias currents are enabled, and I2C writes are allowed. LCD powers, and backlight are disabled.
Normal mode: When LCD_EN is set to high (pin or bit), the start-up sequence is started. During the start-up
sequence LDO_CONT, LCD Boost, and LCD bias powers are started. If the LDO_CONT is
disabled, the start-up sequence goes directly to LCD Boost start-up.
• LDO_CONT start-up: LDO_CONT is enabled. Programmable delay of 0 to 200 ms.
• LCD Boost start-up: LCD Boost is enabled. Waits until Boost output voltage is reached
90% of target value.
• LCD bias start-up enables, sequentially, LDO_VPOS, CP_VNEG, and LDO_OREF
according to start-up delay settings.
After the LCD bias start-up has completed, the LM3631 enters backlight start-up mode if
BL_EN bit is set to ‘1’, and the PWM brightness value is different than 0. Even if the
backlight is not enabled, LCD powers remains active. If the backlight is enabled, and BL_EN
bit is set to ‘0’ or PWM brightness value is set to 0, backlight is disabled. LCD powers
remains active.
If LCD_EN is set to ‘0’, the LM3631 shuts down backlight and bias powers and enters
Standby mode. During power down the backlight is shut down first if it was enabled. After
backlight shutdown is completed, the device enters LCD Bias shutdown. In LCD bias
shutdown LDO_VPOS, CP_VNEG, and LDO_OREF are shut down sequentially according to
shutdown delay settings. After the LDO_VPOS, CP_VNEG, and LDO_OREF shutdown
sequence is complete, LCD Boost and LDO_CONT (if it was enabled) are shut down.
LDO_CONT is shut down after adjustable delay (0 to 200 ms). Once LDO_CONT has shut
down, the LM3631 enters Standby mode.
In a fault situation (thermal, backlight boost short circuit, LDO_OREF overcurrent, VPOS
overcurrent, or CP short circuit), the device starts the shutdown sequence and enters
Standby mode.
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Device Functional Modes (continued)
Shutdown
UVLO fault
during startup
nRST = HIGH &
VIN > UVLO
Bias delay
(200 µs typ)
No UVLO fault
during startup
Eprom read
(700 µs typ)
eprom_read_done
Standby
LCD Bias Shutdown done
and
LDO_CONT disabled
LDO Cont
Shutdown done
LCD_EN = 1 (pin or bit)
and no faults active
LDO_CONT enabled
LCD disable
LDO Cont
Shutdown
LDO_Cont
Start Up
LCD_EN = 1 (pin or bit)
and no faults active
LDO_CONT disabled
LCD Bias
Shutdown done
LCD Bias
Shutdown
LCD disable
LCD_Boost
Start Up
BST_PWROK
LCD disable
LCD Bias
Start Up
LCD disable
Normal Operation
LCD disable or
BL_EN=0 or PWM=0
Backlight
Shutdown
LCD bias
Startup done
LCD Active
LCD enabled and
backlight shutdown
done
Power Good OK,
BL_EN=1 DQG3:00
Backlight startup done
Backlight
Startup
Figure 51. Modes of Operations
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8.5 Programming
8.5.1 I2C-Compatible Serial Bus Interface
8.5.1.1 Interface Bus Overview
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines
should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending
whether it generates or receives the serial clock (SCL).
8.5.1.2 Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New
data should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
change
allowed
data
valid
Figure 52. Data Validity
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
Data Output
by Receiver
Data Output
by Transmitter
Transmitter Stays off the
Bus During the Acknowledge Clock
SCL
Acknowledge Signal from Receiver
1
2
3...6
7
8
9
S
Start
Condition
Figure 53. Acknowledge Signal
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Programming (continued)
The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 54. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a register read cycle.
8.5.1.3 Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device.
The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter
releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver
must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the
high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to
receive the next byte.
8.5.1.4 Acknowledge After Every Byte Rule
The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge
signal after every byte received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
8.5.1.5 Addressing Transfer Formats
Each device on the bus has a unique slave address. The LM3631 operates as a slave device with the 7-bit
address. If an 8-bit address is used for programming, the 8th bit is '1' for read and '0' for write. The 7-bit address
for the LM3631 is 0x29.
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device
should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the
first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the
slave address — the eighth bit.
When the slave address is sent, each device in the system compares this slave address with its own. If there is a
match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the
R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.
MSB
ADR6
Bit7
LSB
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
R/W
bit0
I2C SLAVE address (chip address)
Figure 55. I2C Device Address
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Programming (continued)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Control Register Write Cycle
Master device generates start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the addressed register.
Slave sends acknowledge signal.
If master sends further data bytes the control register address is incremented by one after acknowledge
signal.
Write cycle ends when the master creates stop condition.
Control Register Read Cycle
Master device generates a start condition.
Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
Slave device sends acknowledge signal if the slave address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
Slave sends acknowledge signal if the slave address is correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control register address is incremented by one. Slave
device sends data byte from addressed register.
Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition.
Table 10. I2C Data Read/Write (1)
ADDRESS MODE
(1)
38
Data Read
<Start Condition>
<Slave Address><r/w =0>[Ack]
<Register Addr>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = 1>[Ack]
[Register Data]<Ack or NAck>
...additional reads from subsequent register address possible
<Stop Condition>
Data Write
<Start Condition>
<Slave Address><r/w = 0>[Ack]
<Register Addr>[Ack]
<Register Data>[Ack]
...additional writes to subsequent register address possible
<Stop Condition>
< > = Data from master, [ ] = Data from slave
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ack from slave
ack from slave
start
MSB
Chip id
LSB
w
ack
MSB Register Addr LSB
ack
w
ack
address = 02H
ack
ack from slave
MSB
Data
LSB
ack
stop
ack
stop
SCL
SDA
start
id = 010 1001b
address 02H data
Figure 56. Register Write Format
When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in
the Read Cycle waveform.
ack from slave repeated start
ack from slave
start
MSB Chip id LSB
w
MSB
Register
LSB
Addr
rs
ack from slave data from slave nack from master
MSB Chip Address LSB r
MSB
Data
LSB
stop
SCL
SDA
start
id = 010 1001b
w ack
address = 00H
ack rs
id = 010 1001b
r ack
address 00H data
nack stop
Figure 57. Register Read Format
NOTE
w = write (SDA = 0), r = read (SDA = 1), ack = acknowledge (SDA pulled down by either
master or slave), rs = repeated start id = 7-bit chip address
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8.6 Register Maps
Table 11. Device Control Register (0x00)
[Bit 7]
Not Used
[Bit 6]
Not Used
[Bit 5]
[Bit 4]
Not Used
Not Used
[Bit 2]
[Bit 1]
LCD_EN
[Bit 0]
BL_EN
Not Used
0 = LCD
disabled
1 = LCD
enabled
0 = Backlight
disabled
1 = Backlight
enabled
[Bit 3]
Not Used
Table 12. LED Brightness Register LSB (0x01)
[Bit 7]
[Bit 6]
[Bit 5]
[Bit 4]
[Bit 3]
[Bits 2:0]
Brightness LSB
Not Used
Not Used
Not Used
Not Used
Not Used
BRT[2:0]. Lower 3 bits (LSB's) of brightness code.
Concatenated with brightness bits in Register 0x02
(MSB).
Table 13. LED Brightness Register MSB (0x02)
[Bits 7:0] Brightness MSB
BRT[10:3]. Upper 8 bits (MSB's) of brightness code. Concatenated with brightness bits in Register 0x01 (LSB).
Table 14. Faults Register (0x03)
[Bit 7]
BL_SCFLT
[Bit 6]
TMPFLT
[Bit 5]
BL_OCPFLT
[Bit 4]
BL_OVPFLT
[Bit 3]
LCD_OVPFLT
[Bit 2]
LDO_OREF_F
LT
[Bit 1]
LDO_VPOS_F
LT
[Bit 0]
UVLO FLAG
0 = normal
1 = backlight
short circuit
condition
0 = normal
1 = device has
hit thermal
shutdown
threshold
0 = normal
1 = fault,
backlight boost
current limit
reached
0 = normal
1 = fault,
backlight boost
overvoltage
protection limit
reached
0 = normal
1 = fault, LCD
boost
overvoltage
protection limit
reached
0 = normal
1 = fault,
LDO_OREF
short circuit
condition
0 = normal
1 = fault,
LDO_VPOS
short circuit
condition
0 = normal
1 = UVLO
event
Table 15. Faults and Power-Good Register (0x04)
[Bit 7]
Not Used
[Bit 6]
Not Used
[Bit 5]
Not Used
[Bit 4]
[Bit 3]
NEG_CP_SC
[Bit 2]
NEG_CP_OVP
[Bit 1]
LDO_CONT_F
LT
[Bit 0]
PG_FLAG
Not Used
0 = normal
1 = fault,
negative
chargepump
short circuit
condition
0 = normal
1 = fault,
negative
chargepump
overvoltage
protection limit
reached
0 = normal
1 = fault, LDO
Controller
current limit
reached
Power-Good
flag
Table 16. Backlight Configuration (Auto Frequency Threshold) Register 1 (0x05)
[Bits 7:0]
AUTO_FREQ_THRES
LED current threshold value. When the Auto Frequency Select Mode Bit is ‘1’ (Bit[3] in register 0x07), the 8 bit code in this register
(AUTOFREQ_THRESH) is compared against the MSB’s of the I2C Brightness code (BRT [10:3]), and this comparison is used to determine
whether the device operates in Low Frequency or High Frequency Mode.
1. When BRT[10:3] > AUTOFREQ_THRESH[7:0] , the Boost Frequency Select Bit is automatically set to ‘1’ forcing the device into High
Frequency Mode.
2. When BRT[10:3] ≤ AUTOFREQ_THRESH[7:0], the Boost Frequency Select Bit automatically set to ‘0’ and the device operates in Low
Frequency Mode.
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Table 17. Backlight Configuration Register 2 (0x06)
[Bit 6]
[Bit 5]
LINEAR_MAP
PER
Not Used
0= Exponential
mapping in use
1 = Linear
mapping in use
[Bit 7]
Not Used
[Bit 4]
[Bit 3]
STRING_MOD
E
[Bit 2]
INDUCTOR
Not Used
0 = Both LED
strings enabled
1 = Only LED
string 1
enabled
0 = Inductor
typical value =
22 µH
1 = Inductor
typical value =
10 µH
[Bits 1:0]
PEAK_CURR_LIM
00
01
10
11
= 600 mA
= 700 mA
= 800 mA
= 900 mA
Table 18. Backlight Configuration Register 3 (0x07)
[Bits 7:6]
SEL_I
[Bits 5:4]
SEL_P
[Bit 3]
BL_AUTOFRQ
[Bits 2:1]
BL_BST_OVP
[Bit 0]
BL_BST_FRE
Q
Backlight boost compensator
adjustment. Select value
according to number of LEDs in
LED string.
Backlight boost compensator
adjustment. Select value
according to inductor
0 = Manual
frequency
mode
1 = Auto
frequency
mode
Backlight Boost OVP target
00 = 17 V
01 = 21 V
10 = 25 V
11 = 29 V
Backlight Boost
frequency
0 = 500 kHz
1 = 1 MHz
Table 19. Backlight Configuration Register 4 (0x08)
[Bit 7]
PWM_EDGE_D
ET_SEL
[Bit 6]
PWM
POLARITY
PWM edge
detection
selection
0 = PWM active
0 = PWM
polarity LOW
measured from
1 = PWM active
rising edge
polarity HIGH
1 = PWM
measured from
falling edge
[Bits 5:4]
HYSTERESIS
[Bits 3:2]
BRT_MODE
[Bit 1]
EN__ADV_SL
OPE
[Bit 0]
DISABLE_DIT
HER
PWM input hysteresis selection
(change in 11-bit brightness)
00 = 0.05% shift causes change
01 = 0.1% shift causes change
10 = 0.2% shift causes change
11 = 0.4% shift causes change
Brightness mode selection
00 = I2C register used for
brightness control
01 = PWM input duty cycle used
for brightness control
10 = I2C code multiplied with
PWM duty cycle before sloping
11 = Sloped I2C brightness code
multiplied with PWM duty cycle
0 = Advanced
slope disabled
1 = Advanced
slope enabled
0 = Dither
enabled
1 = Dither
disabled
Table 20. Backlight Configuration Register 5 (0x09)
[Bits 7:4]
SLOPE
[Bits 3:0]
DITHER_FREQ_SEL
0000 = Slope function disabled, immediate brightness change
0001 = 1 ms
0010 = 2 ms
0011 = 5 ms
0100 = 10 ms
0101 = 20 ms
0110 = 50 ms
0111 = 100 ms
1000 = 250 ms
1001 = 500 ms
1010 = 750 ms
1011 = 1000 ms
1100 = 1500 ms
1101 = 2000 ms
1110 = 3000 ms
1111 = 4000 ms
Dithering frequency selection
0000 = 62.5 kHz
0001 = 31.3 kHz
0010 = 15.6 kHz
0011 = 7.8 kHz
0100 = 3.9 kHz
0101 = 1.95 kHz
0110 = 977 Hz
0111 = 488 Hz
1000 = 244 Hz
1001 = 122 Hz
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Table 21. LCD Configuration Register 1 (0x0A)
[Bit 7]
[Bit 6]
LDO_CONT_S
D_PULLDN
[Bit 5]
LDO_OREF_S
D_PULLDN
Not Used
0=
LDO_CONT
pull-down
resistor
disabled
1=
LDO_CONT
pull-down
resistor
enabled
0=
LDO_OREF
pull-down
resistor
disabled
1=
LDO_OREF
pull-down
resistor
enabled
[Bit 4]
CP_VNEG_SD
_PULLUP
[Bit 3]
LDO_VPOS_S
D_PULLDN
[Bit 2]
LDO_VPOS_E
N
[Bit 1]
CP_VNEG_EN
[Bit 0]
LDO_OREF_E
N
0 = CP_VNEG
pull-up resistor
disabled
1 = CP_VNEG
pull-up resistor
enabled
0=
LDO_VPOS
pull-down
resistor
disabled
1=
LDO_VPOS
pull-down
resistor
enabled
0=
LDO_VPOS
disabled
1=
LDO_VPOS
enabled
0 = CP_VNEG
disabled
1 = CP_VNEG
enabled
0=
LDO_OREF
disabled
1=
LDO_OREF
enabled
Table 22. LCD Configuration Register 2 (LDO_CONT) (0x0B)
[Bit 7]
[Bits 6:4]
LDO_CONT_SU_DELAY
[Bits 3:1]
LDO_CONT_SD_DELAY
[Bit 0]
LDO_CONT_E
N
Not Used
LDO_CONT start-up delay
000 = 0 ms
001 = 2 ms
010 = 5 ms
011 = 10 ms
100 = 20 ms
101 = 50 ms
110 = 100 ms
111 = 200 ms
LDO_CONT shutdown delay
000 = 0 ms
001 = 2 ms
010 = 5 ms
011 = 10 ms
100 = 20 ms
101 = 50 ms
110 = 100 ms
111 = 200 ms
0=
LDO_CONT
disabled
1=
LDO_CONT
enabled
Table 23. LCD Configuration Register 3 (0x0C)
42
[Bits 7:6]
LDO_CONT_VOUT
[Bits 5:0]
LCD_BST_OUT
LDO_CONT output voltage
00 = 1.8 V
01 = 2.3 V
10 = 2.8 V
11 = 3.3 V
LCD Boost output voltage
000 000 = 4.50 V
000 001 = 4.55 V
000 010 = 4.60 V
000 011 = 4.65 V
000 100 = 4.70 V
...
010 111 = 5.65 V
011 000 = 5.70 V
011 001 = 5.75 V
...
100 001 = 6.15 V
100 010 = 6.20 V
100 011 = 6.25 V
100 100 = 6.30 V
100 101 = 6.35 V
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Table 24. LCD Configuration Register 4 (LDO_VPOS) (0x0D)
[Bit 7]
Not Used
[Bit 6]
[Bits 5:0]
LDO_VPOS_TARGET
Not Used
000 000 = 4.00 V
000 001 = 4.05 V
000 010 = 4.10 V
000 011 = 4.15 V
000 100 = 4.20 V
...
011 011 = 5.35 V
011 100 = 5.40 V
011 101 = 5.45 V
...
100 100 = 5.80 V
100 101 = 5.85 V
100 110 = 5.90 V
100 111 = 5.95 V
101 000 = 6.00 V
(6.00V is the maximum level regardless of the adjustment level above value '101 000')
Table 25. LCD Configuration Register 5 (CP_VNEG) (0x0E)
[Bit 7]
Not Used
[Bit 6]
[Bits 5:0]
CP_VNEG_TARGET
Not Used
000 000 = –4.00 V
000 001 = –4.05 V
000 010 = –4.10 V
000 011 = –4.15 V
000 100 = –4.20 V
...
011 011 = –5.35 V
011 100 = –5.40 V
011 101 = –5.45 V
...
100 100 = –5.80 V
100 101 = –5.85 V
100 110 = –5.90 V
100 111 = –5.95 V
101 000 = –6.00 V
(–6.00V is the maximum level regardless of the adjustment level above value '101 000')
Table 26. LCD Configuration Register 6 (LDO_OREF) (0x0F)
[Bit 7]
Not Used
[Bit 6]
[Bits 5:0]
LDO_OREF_TARGET
Not Used
000 000 = 4.00 V
000 001 = 4.05 V
000 010 = 4.10 V
000 011 = 4.15 V
000 100 = 4.20 V
...
011 011 = 5.35 V
011 100 = 5.40 V
011 101 = 5.45 V
...
100 100 = 5.80 V
100 101 = 5.85 V
100 110 = 5.90 V
100 111 = 5.95 V
101 000 = 6.00 V
(6.00V is the maximum level regardless of the adjustment level above value '101 000')
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Table 27. LCD Configuration Register 7 (LDO_VPOS Sequence Control) (0x10)
[Bits 7:4]
LDO_VPOS START-UP DELAY
[Bits 3:0]
LDO_VPOS SHUTDOWN DELAY
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
Table 28. LCD Configuration Register 8 (CP_VNEG Sequence Control) (0x11)
[Bits 7:4]
CP_VNEG START-UP DELAY (ms)
[Bits 3:0]
CP_VNEG SHUTDOWN DELAY (ms)
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
Table 29. LCD Configuration Register 9 (LDO_OREF Sequence Control) (0x12)
44
[Bits 7:4]
LDO_OREF START-UP DELAY
[Bits 3:0]
LDO_OREF SHUTDOWN DELAY
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
0000 = 0.0 ms
0001 = 1.0 ms
0010 = 2.0 ms
0011 = 3.0 ms
0100 = 4.0 ms
0101 = 5.0 ms
0110 = 6.0 ms
0111 = 7.0 ms
1000 = 8.0 ms
1001 = 9.0 ms
1010 = 10.0 ms
1011 = 11.0 ms
1100 = 12.0 ms
1101 = 13.0 ms
1110 =14.0 ms
1111 = 15.0 ms
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Table 30. FLAG Configuration Register (0x13)
[Bit 7]
Not Used
[Bit 6]
Not Used
[Bit 5]
Not Used
[Bit 4]
FLAG_PIN_POLAR
ITY
[Bits 3:2]
PG_FLAG_CTRL
[Bits 1:0]
PG_FLAG_CONFIG
0 =FLAG pin active
polarity LOW
1 = FLAG pin active
polarity HIGH
00 = Power-Good set after last
supply reaches target
01 = Power-Good set after
LDO_VPOS
10 = Power-Good set after
CP_VNEG
11 = Power-Good set after
LDO_OREF
00 = FLAG disabled, no flag
indication
01 = Power-Good state, selectable
with PG_FLAG_CTRL bits
10 = Backlight ON state
11 = Fault state
Table 31. BOOT/RESET Register (0x14)
[Bit 7:0]
BOOT
Write FFh to set all I2C registers to RESET value
Table 32. Revision Register (0x16)
[Bit 7:6]
DIE TRACEABILITY
[Bit 5:3]
OTP
REVISION
[Bit 2:0]
DEVICE REVISION
Die Traceability Information
Device OTP
Revision
Information
Device Revision Information
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9 Application and Implementation
9.1 Application Information
The LM3631 integrates an LCD backlight driver and LCD positive and negative bias voltage supplies into a single
device. The backlight boost converter generates the high voltage required for the LEDs. The LM3631 can drive
one or two LED strings with 4 to 8 white LEDs per string. Positive and negative bias voltages are post-regulated
from the LCD bias boost output voltage. In addition, for the LCD bias voltages, the device has two programmable
LDO regulator outputs which can be used to the power display controller, the LCD gamma reference, or any
additional peripherals within output-current capability.
LDC bias voltages can be used without the backlight. Pulling LCD_EN high starts the LCD bias boost regulator.
Once the LCD bias boost regulator has started up all voltage outputs can be enabled individually. The LM3631
can also be programmed to enable any voltage outputs automatically per a preset start-up sequence. The
backlight cannot be enabled until enabled bias voltages have settled.
9.2 Typical Application
L1
10/22µH
D1
C6
2.2µF
C2
0.1µF
C1
10µF
VIN
C3
0.1µF
SW
VOUT
LED1
L2
1.5µH
LED2
Up to 8 LEDs / string
BST_SW
VIN
2.7V ± 5.0V
+
-
C7
100pF
C4
10µF
C5
0.1µF
BST_OUT
C8
10µF
LM3631
SDA
SDA
SCL
SCL
C9
100pF
C2
C10
10µF
C1
nRST
nRST
VNEG (-5.4V)
CP_VNEG
LCD_EN
LCD_EN
VOREF (+4.0V to +6.0V)
LDO_OREF
PWM
PWM
VPOS (+5.4V)
LDO_VPOS
FLAG
FLAG
VCONT (+1.8V)
LDO_CONT
OTP_SEL
GND_BST_SW
AGND
C11
C12
C13
C14
10µF
10µF
10µF
10µF
GND_SW
PGND
Figure 58. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Example requirements based on default register values (OTP_SEL = 1):
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage Range
2.7 V to 4.5 V (Single Li-Ion cell battery)
Brightness Control
I2C Register
LED Configuration
2 parallel, 6 series
LED Current
max 25 mA / string
Backlight Boost maximum voltage
28 V
Backlight boost SW frequency
1MHz
Backlight Boost inductor
10-µH, 900-mA saturation current
LCD boost output voltage
5.9 V
VNEG output voltage
–5.4 V
VPOS output voltage
5.4 V
VOREF output voltage
5.6 V
VCONT output voltage
1.8 V
LCD Boost inductor
1.5-µH, 1-A saturation current
9.2.2 Detailed Design Procedure
9.2.2.1 External Components
Table 33 shows examples of external components for the LM3631. Small 100-pF ceramic capacitors parallel with
boost-converter-output capacitors are optional and are used to reduce high-frequency noise generated by the
boost converters. Boost-converter dual-output capacitors can be replaced with a single capacitor of higher output
capacitance as long as the minimum effective capacitance requirement is met. DC bias effect of the ceramic
capacitors must be taken into consideration when choosing the output capacitors. This is especially true for the
high output-voltage backlight-boost converter.
Table 33. Recommended External Components
DESIGNATOR
(Figure 58)
DESCRIPTION
VALUE
EXAMPLE
C1, C4, C8,
C10, C11, C12,
C13, C14
Ceramic capacitor
10 µF, 10V or
16V
EMK107BBJ106MA-T
C2, C3, C5
Ceramic capacitor
0.1 µF, 10V
GRM188R71H104KA93D
C6
Ceramic capacitor
2.2 µF, 35V or
50V
C2012X5R1H225K
C7, C9
Ceramic capacitor
100 pF, 50V
06035A101JAT2A
L1
Inductor
22 or 10 µH,
900mA
VLF403210MT-100M or 1235ASH-220M
NOTE
Optional, only for HF interference
reduction.
L2
Inductor
1.5 µH
DFE252010R-H-1R5M
D1
Schottky diode
40V, 200mA
NSR0240P2T5G
9.2.2.2 Inductor Selection
Both of the LM3631 boost converters are internally compensated. The compensation parameters of the LCD bias
boost converter are fixed and set for a 1.5-µH inductor. The backlight boost converter has a selection bit to
choose between 10-µH or 22-µH inductors. The inductor typical inductance is selected with the INDUCTOR bit
(Register 0x06, bit 2). Effective inductance of the inductors should be ±20%.
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There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor
current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of
application should be requested from the manufacturer. The saturation current should be greater than the sum of
the maximum load current and the worst-case average-to-peak inductor current. The equation below shows the
worst case conditions.
IOUTMAX
ISAT >
'¶
+ IRIPPLE
VIN
(VOUT ± VIN)
x
Where IRIPPLE =
(2 x L x f)
VOUT
(VOUT ± VIN)
DQG'¶= (1 - D)
Where D =
VOUT
where
•
•
•
•
•
•
IRIPPLE = peak inductor current
IOUTMAX = maximum load current
VIN = minimum input voltage in application
L = minimum inductor value including worst case tolerances
f = minimum switching frequency
VOUT = output voltage
(7)
As a result the inductor should be selected according to the ISAT. A more conservative and recommended
approach is to choose an inductor that has a saturation current rating greater than the maximum current limit.
The inductor’s resistance should be kept small for good efficiency.
See detailed information in “Understanding Boost Power Stages in Switch Mode Power Supplies”
http://focus.ti.com/lit/an/slva061/slva061.pdf. “Power Stage Designer™ Tools” can be used for the boost
calculation: http://www.ti.com/tool/powerstage-designer.
9.2.2.3 Boost Output Capacitor Selection
Two 2.2-μF capacitors are recommended for the backlight boost converter output capacitors. A single 2.2-μF
capacitor can be used for reducing solution size as long as the effective output capacitance is higher than 1 µF.
A high-quality ceramic type X5R or X7R is recommended. Voltage rating must be greater than the maximum
output voltage that is used.
For the LCD-bias-boost output two 10-μF capacitors are recommended. A high-quality ceramic type X5R or X7R
is recommended. Voltage rating must be greater than the maximum output voltage that is used.
The DC-bias effect of the capacitors must be taken into consideration when selecting the output capacitors. The
effective capacitance of a ceramic capacitor can drop down to less than 10% with maximum rated DC bias
voltage depending on capacitor type. Note that with a same voltage applied, the capacitors with higher voltage
rating suffer less from the DC-bias effect than capacitors with lower voltage rating.
9.2.2.4 Backlight Boost Diode Selection
A Schottky diode should be used for the output diode. Peak repetitive current should be greater than inductor
peak current to ensure reliable operation. Average current rating should be greater than the maximum output
current. Reverse breakdown voltage of the Schottky diode should be significantly larger than the maximum
output voltage.
9.2.2.5 Charge Pump Capacitor Selection
Voltage ratings for the flying capacitor and output capacitor must be higher than the maximum output voltage.
Ceramic X5R/X7R capacitors are recommended. 10-V voltage rating and 10 µF capacitors are recommended for
both.
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9.2.2.6 LDO Output Capacitor Selection
Voltage ratings for the LDO output capacitors must be higher than the maximum output voltage. Ceramic
X5R/X7R capacitors are recommended. 10-V voltage rating and 10-µF capacitors are recommended for all.
9.2.3 Application Curves
Figure 59 and Figure 60 show typical backlight start-up and shutdown curves using the LCD_EN pin control.
LCD_EN
2V/DIV
LCD_EN
2V/DIV
VOUT
10V/DIV
VOUT
10V/DIV
IOUT
10V/DIV
IOUT
10V/DIV
1ms/DIV
1ms/DIV
Figure 60. Backlight Shutdown with LCD_EN Pin Control
Figure 59. Backlight Start-up with LCD_EN Pin Control
Figure 61 and Figure 62 show the default start-up and shutdown waveforms with OTP_SEL = GND. LDO_CONT
pulldown is disabled by default causing VCONT to float after shutdown.
VBST
5V/DIV
VBST
5V/DIV
VCONT
5V/DIV
VCONT
5V/DIV
VPOS
5V/DIV
VPOS
5V/DIV
VNEG
5V/DIV
VNEG
5V/DIV
2ms/DIV
2ms/DIV
Figure 61. Default LCD Bias Startup, OTP_SEL = GND.
Figure 62. Default LCD Bias Shutdown, OTP_SEL = GND.
10 Power Supply Recommendations
The LM3631 is designed to operate from an input voltage supply range between 2.7 V and 5 V. This input supply
must be well regulated and capable to supply the required input current. If the input supply is located far from the
LM3631 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
•
•
•
Place the boost converters output capacitors as close to the output voltage and GND pins as possible.
Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and
switch pins.
If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the
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Layout Guidelines (continued)
•
•
•
switch node to minimize switch pin parasitic capacitance while preserving adequate routing width.
VIN input voltage pin needs to be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor
as close to VIN pin as possible
Place the output capacitors of the LDOs as close to output pins as possible. Also place the charge pump
flying capacitor and output capacitor close to respective pins.
Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid layer1. Avoid
routing the signal traces directly under the switching loops of the boost converters.
11.2 Layout Example
L1
VIAs to VIN plane
C1
D1
C2
Route the
switching loops on
top layer if possible
GND on Top layer.
Connect to internal
ground plane with
multible VIAs
C7
GND
C6
VOUT
GND_
SW
SW
VOUT
LED1
LED1
VIN
nRST
LCD_
EN
LED2
LED2
GND_
BST_
SW
FLAG
OTP_
SEL
AGND
GND
BST_
SW
SCL
LDO_
CONT
LDO_
VPOS
C3
GND
C4
C5
L2
C9
C12
C8
BST_
OUT
SDA
LDO_
OREF
PWM
C13
VIAs to VIN plane
C1
PGND
CP_
VNEG
C2
C11
Route LDO_CONT
on internal layer
C10
GND
C14
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM3631YFFR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
24
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
LM3631
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Sep-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM3631YFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
2.1
B0
(mm)
K0
(mm)
P1
(mm)
2.76
0.81
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3631YFFR
DSBGA
YFF
24
3000
182.0
182.0
20.0
Pack Materials-Page 2
D: Max = 2.585 mm, Min =2.524 mm
E: Max = 1.885 mm, Min =1.825 mm
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