Ultra High Performance Audio ADC 120dB, 192kHz
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Features
Dynamic Range: 120dB
THD+N: -110dB
Sampling Frequency: up to 192kS/s
PCM formats: I2S™, Left justified
Multibit and DSD outputs
Lowest Group Delay Filter
Digital High Pass & Offset Cancellation
Overflow Indicator
Supports Logic Levels from 3.3V to 5V
Power dissipation: 450mW
QFN-64 Green Package, 9mm x 9mm
High Performance Audio
Multichannel converters
Digital Audio Mixing Consoles
Live Sound Production
Surround Sound Encoders
Effects Processors
Broadcast Studio Equipment
A/V Receivers
DVD-R, CD-R
Data Acquisition and Test Equipment
Input / Output Interface
Applications
General Description
The AT12612 is a stereo A/D converter designed for extremely high performance audio systems.
Using a proprietary multibit sigma-delta modulator architecture, the AT12612 provides outstanding
dynamic range of 120dB, THD+N of -110dB and a sampling rate of up to 192kS/s. It is pin compatible
with the flagship AT1201 and achieves a low power dissipation of 450mW.
On-chip digital filters are designed for acoustically transparent response at all sampling rates. The
filters can be bypassed to bring out multibit modulator outputs or DSD outputs directly to pins to
enable the use of an external filter. Each of the three output modes (PCM, DSD, and multibit) can be
enabled independently of the others allowing all three to be active simultaneously.
Rev. 1.0
Page 1 of 27
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Pinout
Rev. 1.0
Page 2 of 27
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
1. Pin Description
Terminal
No.
Name
Type
1
REFPL
Analog Input
2
REFNL
Analog Input
3
CMREFL
Analog Output
AGND
Analog Ground
4, 7,
10, 13,
18, 19,
62, 63,
64
5
6
8, 9
11
12
Pin Description
High Reference Left Channel – High reference voltage for
left channel, ties to capacitor
Low Reference Left Channel – Low reference voltage for
left channel, ties to analog ground
Common-Mode Voltage - Internally generated reference
voltage, ties to capacitor
Analog Ground – Ground return for analog section
Differential Left Channel Input – Differential analog input to
the left channel Σ∆ modulator
Analog Power – Positive power supply for analog section
Differential Right Channel Input – Differential analog input
to the right channel Σ∆ modulator
Common-Mode Voltage - Internally generated reference
voltage, ties to capacitor
Low Reference Right Channel – Low reference voltage for
right channel, ties to analog ground
High Reference Right Channel – High reference voltage for
right channel, ties to capacitor
Input Buffer Common-Mode Reference Voltage – Reference
voltage for the buffers driving the analog inputs
Enable PCM Output – Enables internal filters and generates
serial audio output
INLP
INLN
AVDD
INRN
INRP
Analog Supply
14
CMREFR
Analog Output
15
REFNR
Analog Input
16
REFPR
Analog Input
17
BUFREF
Analog Output
20
PCM_EN
Digital Input
DGND
Digital Ground
Digital Ground – Ground return for digital section
DVDD
Digital Supply
Digital Power – Positive power supply for digital section
27
MBO_EN
Digital Input
28
DSD_EN
Digital Input
29
MS
Digital Input
30
31
32
MBR5
MBR4
MBR3
33
LRCLK
34
SCLK
Digital Output
Digital Output
Digital Output
Digital
Input/Output
Digital
Input/Output
21, 22,
23, 24,
26, 37,
45, 56
25, 36,
44, 55
Rev. 1.0
Analog Input
Analog Input
Multibit Modulator Output Enable – Enables right and left
channel multibit modulator outputs
DSD Output Enable – Enables right and left channel DSD
outputs
Master/Slave mode – Selects clock master or clock slave
mode for PCM output, high=master / low=slave
Multibit Modulator Output – Right channel output bit 5
Multibit Modulator Output – Right channel output bit 4
Multibit Modulator Output – Right channel output bit 3
Left Right Clock – Indicates whether left or right channel is
active on the serial audio data line
Serial Clock – Clock for the serial audio interface
Page 3 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
35
38
39
40
41
42
43
RSTB
MBR2
MBR1
MBR0
DCLK
DSDR
DSDL
Digital Input
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
46
SDOUT
Digital Output
47
48
49
50
51
52
53
54
MBL0
MBL1
MBL2
MBL3
MBL4
MBL5
MDIV
HPFB
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Digital Output
Digital Input
Digital Input
57
I2S_LJ
Digital Input
58
59
60
61
M0
M1
OVFLB
MCLK
Digital Input
Digital Output
Digital Input
Reset – active low input places devices in a low power mode
Multibit Modulator Output – Right channel output bit 2
Multibit Modulator Output – Right channel output bit 1
Multibit Modulator Output – Right channel output bit 0
Clock Out – Clock for DSD and Multibit outputs
DSD Output – Right channel DSD output
DSD Output – Left channel DSD output
Serial Audio Data Output – PCM output for left and right
channels
Multibit Modulator Output – Left channel output bit 0
Multibit Modulator Output – Left channel output bit 1
Multibit Modulator Output – Left channel output bit 2
Multibit Modulator Output – Left channel output bit 3
Multibit Modulator Output – Left channel output bit 4
Multibit Modulator Output – Left channel output bit 5
MCLK Divider – Enables divide by 2 of master clock
Highpass Filter – Enables digital highpass filter, active low
Audio Output Format Select – Selects either the I2S or left
justified output format, high=I2S / low=LJ
Mode Selection – Selects among the following sampling
rates: Half, single, double, and quad
Overflow – Detects overflow on either channel
Master Clock – Clock for the Σ∆ modulator and digital filters
2. Specifications
Absolute Maximum Ratings
Parameter
DC Power Supplies:
Analog
Digital
Analog Input Voltage
Digital Input Voltage
Input Current
Ambient Operating Temperature
Storage Temperature
Symbol
Min
Max
Units
AVDD
DVDD
VINA
VIND
Iin
TA
Tstg
-0.3
-0.3
GND-0.7
GND-0.7
-10
-50
-65
+6.0
+6.0
AVDD+0.7
DVDD+0.7
+10
+95
+150
V
V
V
V
mA
ºC
ºC
Recommended Operating Conditions
Parameters
DC Power Supplies:
Ground
Ambient Operating Temperature
Rev. 1.0
Analog
Digital
Symbol
Min
Typ
Max
Units
AVDD
DVDD
GND
TA
4.75
3.0
5.0
3.3
0
5.25
5.25
V
V
V
ºC
Page 4 of 27
-10
+70
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Dynamic Electrical Characteristics
Unless otherwise stated, the test conditions are: input signal is a 1kHz sine wave, measurement
bandwidth is 20Hz to 20kHz, AVDD=5.0V, DVDD=3.3V, TA=25 ºC.
Parameters
Symbol
Min
Typ
Max
Units
114
113
120
119
-
dB
dB
-104
-110
-99
-59
113
110
119
116
-104
-110
-96
-56
113
110
107
119
116
113
-104
-110
-96
-56
-110
113
110
107
119
116
113
PCM Output, Half-Speed: FS=24kHz
Dynamic Range
10 kHz, A-weighted
10 kHz, unweighted
DR
THD+N
10 kHz, -2 dB
10 kHz, -20 dB
10 kHz, -60 dB
THD+N
dB
dB
dB
PCM Output, Single-Speed: FS=48kHz
Dynamic Range
20 kHz, A-weighted
20 kHz, unweighted
DR
-
dB
dB
THD+N
20 kHz, -2 dB
20 kHz, -20 dB
20 kHz, -60 dB
THD+N
dB
dB
dB
PCM Output, Double-Speed: FS=96kHz
Dynamic Range
20 kHz, A-weighted
20 kHz, unweighted
40 kHz, unweighted
DR
-
dB
dB
dB
THD+N
20 kHz, -2
20 kHz, -20
20 kHz, -60
40 kHz, -2
dB
dB
dB
dB
THD+N
dB
dB
dB
dB
PCM Output, Quad-Speed: FS=192kHz
Dynamic Range
20 kHz, A-weighted
20 kHz, unweighted
40 kHz, unweighted
DR
-
dB
dB
dB
THD+N
20 kHz, -2
20 kHz, -20
20 kHz, -60
40 kHz, -2
dB
dB
dB
dB
-110
-96
-56
-109
THD+N
dB
dB
dB
dB
Multibit Outputs: FS=6.144MHz
Dynamic Range
20kHz, A-weighted
20kHz, Unweighted
Rev. 1.0
114
112
Page 5 of 27
120
118
-
dB
dB
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
THD+N
-2 dB
-20 dB
-60 dB
THD+N
-104
-110
-98
-58
dB
dB
dB
DSD Outputs: FS=6.144MHz
Dynamic Range
20kHz, A-weighted
20kHz, Unweighted
100
98
-
dB
dB
THD+N
-2 dB
-20 dB
-60 dB
-100
-80
-40
THD+N
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation
-
130
-
dB
-
0.1
-
dB
-5
-
±100
5
0
%
ppm/ºC
-
0
100
-
LSB
LSB
0.87 x
AVDD
-
0.90 x
AVDD
100
3.0
0.93 x
AVDD
-
Vpp
Parameters
Symbol
Min
Typ
Filter Response: Half-Speed Mode (2kHz to 27kHz)
Max
Units
Passband
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (FS= Output
Sample Rate)
0.42
0
FS
dB
FS
dB
s
0.44
0
FS
dB
FS
dB
s
DC Accuracy
Channel Level Matching
(20kHz input signal)
Gain Error
Gain Drift
Offset Error
HPF Enabled
HPF Disabled
Analog Input Characteristics
Full Scale Input Voltage
(Single Ended)
Common Mode Rejection Ratio
Input Impedance (Differential)
CMRR
dB
kΩ
Digital Filter Characteristics
0
-0.015
0.58
-100
tgd
12/FS
Filter Response: Single-Speed Mode (25kHz to 54kHz)
Passband
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (FS= Output
Sample Rate)
Rev. 1.0
0
-0.015
0.70
-117
tgd
Page 6 of 27
7/FS
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Filter Response: Double-Speed Mode (50kHz to 108kHz)
Passband
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (FS= Output
Sample Rate)
0
-0.015
0.80
-108
tgd
0.25
0
FS
dB
FS
dB
s
0.22
0
5/FS
FS
dB
FS
dB
s
0.23
0.0004
0.7
10.24
Hz
dB
Deg
s
0.47
0.0024
1.33
5.12
Hz
dB
Deg
s
0.94
0.0094
2.7
2.56
Hz
dB
Deg
s
1.9
0.038
5.3
1.28
Hz
dB
Deg
s
5/FS
Filter Response: Quad-Speed Mode (100kHz to 216kHz)
Passband (-0.1dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (FS= Output
Sample Rate)
0
-0.015
0.79
-116
tgd
High Pass Filter Characteristics
Half-Speed Mode, Fs=24kHz
Frequency Response, -3.0dB
Passband droop, 20Hz
Phase Deviation, 20Hz
Filter Settling Time
Single-Speed Mode, Fs=48kHz
Frequency Response, -3.0dB
Passband droop, 20Hz
Phase Deviation, 20Hz
Filter Settling Time
Double-Speed Mode, Fs=96kHz
Frequency Response, -3.0dB
Passband droop, 20Hz
Phase Deviation, 20Hz
Filter Settling Time
Quad-Speed Mode, Fs=192kHz
Frequency Response, -3.0dB
Passband droop, 20Hz
Phase Deviation, 20Hz
Filter Settling Time
Rev. 1.0
Page 7 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Digital Filter Frequency Response Plots
Half-Speed Mode
Figure 1: Frequency response, half-speed filter
Figure 2: Transition band response, half-speed filter
Rev. 1.0
Page 8 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Figure 3: Band edge response, half-speed filter
Figure 4: Passband response, half-speed filter
Rev. 1.0
Page 9 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Single-Speed Mode
Figure 5: Frequency response, single-speed filter
Figure 6: Transition band response, single-speed filter
Rev. 1.0
Page 10 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Figure 7: Band edge response, single-speed filter
Figure 8: Passband response, single-speed filter
Rev. 1.0
Page 11 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Double-Speed Mode
Figure 9: Frequency response, double-speed filter
Figure 10: Transition band response, double-speed filter
Rev. 1.0
Page 12 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Figure 11: Band edge response, double-speed filter
Figure 12: Passband response, double-speed filter
Rev. 1.0
Page 13 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Quad-Speed Mode
Figure 13: Frequency response, quad-speed filter
Figure 14: Transition band response, quad-speed filter
Rev. 1.0
Page 14 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Figure 15: Transition band response, quad-speed filter
Figure 16: Passband response, quad-speed filter
Rev. 1.0
Page 15 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Switching Characteristics
Conditions: Logic “0” = 0V; Logic “1” = DVDD, CL = 20pF
Parameter
Output Sample Rate
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
OVFL to LRCK Edge Setup Time
OVFL to LRCK Edge Hold Time
OVFL time-out
Symbol
Min
Typ
Max
Unit
FS
FS
FS
FS
2
25
50
100
16/fsclk
1/fsclk
-
680
27
54
108
216
-
kHz
kHz
kHz
kHz
s
s
ms
36.2
45
6.144
12.288
-
1953
6.912
13.824
55
ns
MHz
MHz
%
tmslr
tsdo
-4
-
0
50
4
5
-
ns
ns
%
FS
2
40
580
45
10
5
-20
50
50
-
27
60
55
20
kHz
%
ns
%
ns
ns
ns
25
40
290
45
10
5
-20
50
50
-
54
60
55
20
kHz
%
ns
%
ns
ns
ns
50
40
145
45
10
5
-20
50
50
-
108
60
55
20
kHz
%
ns
%
ns
ns
ns
tsetup
thold
MCLK Specifications
MCLK Period
MCLK Frequency, MDIV=0
MCLK Frequency, MDIV=1
MCLK Duty Cycle
Master Mode
SCLK falling to LRCK transition
SCLK falling to SDOUT valid
SCLK Duty Cycle
Slave Mode
Half Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Single Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Double Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
Rev. 1.0
tsclk
tstp
thld
tslrd
FS
tsclk
tstp
thld
tslrd
FS
tsclk
tstp
thld
tslrd
Page 16 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Quad Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK transition
DSDR/DSDL and MBR/MBL
DCLK period, MDIV=0
DCLK period, MDIV=1
DSDx/MBx valid to DCLK rising
DCLK rising to DSDx/MBx not valid
Rev. 1.0
FS
tsclk
tstp
thld
tslrd
tDCLK
tDCLK
tMBDC
tDCMB
Page 17 of 27
100
40
72
45
10
5
-8
50
50
-
216
60
55
8
kHz
%
ns
%
ns
ns
ns
10
s
s
ns
ns
1/fsclk
1/2fsclk
10
Company Confidential
Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
LRCK
AT12612
Left Channel Frame
Right Channel Frame
SCLK
OVFLB
OVFLB on Right Channel
OVFLB on Left Channel
OVFLB Timing, Left-Justified
Rev. 1.0
Page 18 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
DC Electrical Characteristics
All parameters are specified at TA = +25ºC, GND = 0V, all voltages with respect to ground. MCLK =
12.288 MHz; Master Mode
Parameter
Symbol
Min
Typ
Max
Unit
AVDD = 5V
IA
-
82
-
mA
DVDD = 5V
DVDD = 3.3V
ID
ID
-
18
12
-
mA
mA
DVDD = 5V
DVDD = 3.3V
ID
ID
-
21
14
-
mA
mA
DVDD = 5V
DVDD = 3.3V
ID
ID
-
24
16
-
mA
mA
DVDD = 5V
DVDD = 3.3V
ID
ID
-
33
22
-
mA
mA
DVDD = 5V
DVDD = 3.3V
ID
ID
-
2
1
-
mA
mA
DVDD = 5V
DVDD = 3.3V
AVDD = 5V
DVDD = 5V
ID
ID
IA
ID
-
5
3
250
50
-
mA
mA
µA
µA
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
PCM Single Speed Mode
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
PCM Double Speed Mode
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
PCM Quad Speed Mode
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
DSD Mode
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
Multibit Mode
AVDD = DVDD = 5V
AVDD = 5V, DVDD = 3.3V
Power-Down Mode
Power Supply Rejection Ratio
(1kHz, 25mVpp applied to AVDD, DVDD)
Pt
Pt
-
500
450
-
mW
mW
Pt
Pt
-
515
456
-
mW
mW
Pt
Pt
-
530
463
-
mW
mW
Pt
Pt
-
575
483
-
mW
mW
Pt
Pt
-
420
413
-
mW
mW
Pt
Pt
Pt
-
435
420
1.5
-
mW
mW
mW
PSRR
-
70
-
dB
Power Supply Current
PCM Half Speed Mode
PCM Single Speed Mode
PCM Double Speed Mode
PCM Quad Speed Mode
DSD Mode
Multibit Mode
Power Supply Current
(Power-Down Mode8)
Power Consumption
PCM Half Speed Mode
Rev. 1.0
Page 19 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
CMREF Nominal Voltage
-
Output Impedance
Maximum allowable DC current source/sink
REFPR / REFPL Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
BUFREF Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
8
2.5
2.2
0.01
4.8
130
0.1
2.4
14.5
0.01
-
V
kΩ
mA
V
Ω
mA
V
kΩ
mA
Power down mode entered when RST = Low and all clocks and data lines are held static.
Digital Characteristics
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at IO = 100 µA
(% of VL)
(% of VL)
Symbol
Min
Typ
Max
Unit
VIH
VIL
VOH
70%
70%
-
30%
-
V
V
V
VOL
-
-
15%
V
IIN
IOVFL
-10
4
-
10
-
µA
mA
(% of VL)
Low-Level Output Voltage at IO = 100 µA
(% of VL)
Input Leakage Current
OVFLB Current Sink
Thermal Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Tjmax
θJA-QFN
-
31
135
-
°C
°C/W
Maximum Junction Temperature
Junction to Ambient Thermal Resistance
Rev. 1.0
Page 20 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
Typical Connection to the AT12612
For more detailed information about schematic considerations, consult application note AN-AT1201-1:
Design and Layout Guidelines.
Rev. 1.0
Page 21 of 27
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Ultra High Performance Audio ADC
120dB, 192kHz, 24-Bit Conversion
Datasheet
AT12612
3. Applications
DSD Output
The AT12612 enters DSD output mode when the DSD_EN pin is pulled high. Bit streams running at
MCLK or MCLK/2, depending on the state of MDIV, are generated at the DSDL/DSDR pins.
Furthermore, a full rate clock signal, DCLK, is provided to facilitate the acquisition of the DSD data.
The DSD output rate is 128x.
Multibit Output
The AT12612 enters multibit output mode when the MBO_EN pin is pulled high. Bit streams running at
MCLK or MCLK/2, depending on the state of MDIV, are generated at the MBL[5:0]/MBR[5:0] pins.
Furthermore, a full rate clock signal, DCLK, is provided to facilitate the acquisition of the multibit
data. The multibit data is represented in two’s complement form. The multibit modulator output
rate is 128x.
MCLK/DCLK
MDIV = 0
1
MDIV = 1
2
PCM Mode Sampling Range Selection
The mode selection pins, M0 and M1, together with the clock divider pin, MDIV, can be used to select
the output sample rate, FS.
MCLK
128x
128x
128x
256x
256x
256x
256x
MDIV
0
0
0
1
1
1
0
M1
0
0
1
0
0
1
1
M0
0
1
0
0
1
0
1
Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Output Sample Rate (FS)
2kHz – 27kHz
25kHz – 54kHz
50kHz – 108kHz
2kHz – 27kHz
25kHz – 54kHz
50kHz – 108kHz
100kHz – 216kHz
Combinations of MDIV, M1, M0, and MCLK rate other than those shown above are invalid. Note that
the only way to operate at quad speed mode is for the MCLK frequency to be 256x, or nominally
12.288MHz.
PCM Output Format Selection
The AT12612 can produce both I2S and LJ (left justified) formatted PCM output. The format selection
is made by setting the package pin, I2S_LJ, as shown in the Table below.
PCM Format
Rev. 1.0
I2S_LJ = 0
LJ
Page 22 of 27
I2S_LJ = 1
I2S
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AT12612
Master Clock
The master clock signal, MCLK, is the only logic signal that operates at the AVDD voltage. All other
logic signals run at the DVDD level. The clocking interface circuitry within the AT12612 has been
engineered to achieve the best possible performance with a 5V master clock.
System Clocking
The pin, MS, selects operation in PCM master or slave mode. In Master Mode, LRCK and SCLK are
generated synchronously on-chip. In Slave Mode, LRCK and SCLK are generated externally and are
inputs to the device. In addition, in Master Mode the MDIV input is used to internally divide the
master clock.
Clock Mode
MS = 0
Slave
MS = 1
Master
Master Mode
In Master Mode the internally generated LRCK and SCLK clocks function as outputs. The LRCK is equal
to FS, the sampling frequency, and the SCLK is equal to 64xFS. Note that to operate in quad speed
mode, MCLK must be a 512x clock, MDIV must be set low, and M1/M0 must both be set high.
÷1
0
128x in half,
single, double
÷ 256
Half
Speed
00
÷ 128
Single
Speed
01
÷ 64
Double
Speed
÷ 64
Quad
Speed
MCLK
10
LRCK
Equal to FS
11
M1 M0
256x in quad
÷2
1
÷4
Half
Speed
00
÷2
Single
Speed
01
÷1
Double
Speed
10
÷1
Quad
Speed
11
MDIV
Rev. 1.0
Page 23 of 27
SCLK
64 x FS
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AT12612
Slave Mode
In Slave mode the SCLK and LRCK are inputs. It is recommended that both the LRCK and SCLK be
generated synchronously with the MCLK. In addition, it is recommended that LRCK be equal to FS, the
sampling frequency, and the SCLK should be equal to 64 x FS.
MCLK/LRCK
SCLK/LRCK
Half-Speed
FS=2kHz-27kHz
256x, 512x
64x
Single-Speed
FS=25kHz-54kHz
128x, 256x
64x
Double-Speed
FS=50kHz-108kHz
64x, 128x
64x
Quad-Speed
FS=100kHz-216kHz
64x
64x
Power-Up Sequence
The AT12612 has an active low reset pin, RSTB. The device should be maintained in reset until power
supplies, clocks and configuration pins are stable or be placed in reset if any of the supply voltages
drop below their minimum operating voltages.
For the device to produce valid data, all internal reference voltages should be stable. To ensure the
output data is valid, there is an internal delay, less than 2500 LRCK cycles, between the reset pin
going high and the generation of valid outputs.
Input Buffer Design
It is critical to design a high performance input buffer to achieve optimum performance with the
AT12612. The input buffer must be able to drive the switched-capacitor input impedance of the
modulator as well as provide anti-aliasing at multiples of the sampling rate, which is nominally
6.144MHz. The circuits shown below achieve both of these goals. Note that feedback capacitor
around the operational amplifier should be a C0G, NP0, or PPS type with low voltage coefficient. The
inverting buffer configuration is recommended. For more detailed information regarding the input
buffer schematic, consult application note AN-AT1201-1: Design and Layout Guidelines.
Rev. 1.0
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AT12612
Simplified Input Buffer Circuit (see AN-AT1201-1 for more details)
Highpass Filter and DC Offset Calibration
The AT12612 has a digital highpass filter that can be used to remove DC offset. By disabling the
highpass filter after the filter has settled, the offset is frozen and continues to be subtracted from
the output result. Therefore, the filter can either continuously track the offset, or it can capture the
offset during a calibration cycle, then be disabled.
Overflow Detection
The AT12612 detects overflow on each input channel. The active low OVFLB signal is time
multiplexed with LRCK for ease of latching. After an overflow condition has been detected, OVFLB
remains asserted as indicated on page 8. Each channel can enter the overflow condition
independently of the other. If both channels are in overflow at the same time, they exit overflow
simultaneously, after the timeout period has expired on the last channel to enter overflow.
The OVFLB signal is asserted one SCLK period after an LRCK transition in left-justified mode. In this
mode, the rising edge of LRCK latches the right channel overflow condition, while the falling edge of
LRCK latches that of the left channel.
Rev. 1.0
Page 25 of 27
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AT12612
The OVFLB signal is asserted two SCLK periods after an LRCK transition in I2S mode. In this mode, the
rising edge of LRCK latches the left channel overflow condition, while the falling edge of LRCK
latches that of the right channel.
The OVFLB signal is an open-drain signal requiring a 10kΩ pull up resistor to DVDD on the PC board.
This allows multiple AT12612 devices to share a single pull up resistor to form a wired-OR function.
Synchronization of Multiple Devices
When multiple ADCs are required within a system, attention should be paid to ensure simultaneous
sampling. When only a single MCLK is needed, then one AT12612 can be placed in master mode and
the rest of the AT12612s are in slave mode to the master. If multiple MCLKs are required, then, one
possible solution is to have all the clocks generated from the same external source and timing the
reset of all the AT12612s to the falling edge of the MCLK, thus ensuring all converters begin sampling
on the same clock edge.
Broadband Spectrum
The AT12612 has extremely low and well behaved quantization noise far past the audio band.
Therefore, operating at quad rate does not introduce any high frequencies spikes in the output
spectrum that could adversely affect audio processing equipment.
Rev. 1.0
Page 26 of 27
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AT12612
Package Dimensions
64-QFN Package Drawing
JEDEC #
Type
Dimension
Symbol
A
A1
A3
D
E
D2
E2
e
NX b
NX L
θ°
MO 220 / WMMD
64 Lead
mm
Min
Max
0.70
0.80
0
0.05
0.175
0.225
8.9
9.1
8.9
9.1
6.13
6.23
6.13
6.23
0.5 BSC
0.20
0.30
0.35
0.45
0°
4°
mils
Min
Max
27.56
31.49
0
1.97
6.89
8.86
350.39
358.27
350.39
358.27
241.34
245.28
241.34
245.28
19.69 BSC
7.87
11.81
13.78
17.71
0°
4°
The package features an exposed pad denoted by dimensions D2 and E2. The pad should be
soldered to the board’s analog ground plane. See the application note AN-AT1201-1 Design
and Layout Guidelines for details.
Arda Technologies, Inc
148 Castro Street, Suite A1, Mountain View, CA 94041-1202 USA
Tel: +1.650.961.9100, Fax: +1.650.961.9102, sales@ardatech.com
Rev. 1.0
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