Family of Low-Power Rail-to-Rail Input/Output
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Rail-to-Rail Output Swing
Gain Bandwidth Product . . . 6.4 MHz
± 80 mA Output Drive Capability
D
Supply Current . . . 500 µA/channel
Input Offset Voltage . . . 100 µV
Input Noise Voltage . . . 11 nV/√Hz
Slew Rate . . . 1.6 V/µs
Micropower Shutdown Mode
(TLV2460/3) . . . 0.3 µA/Channel
Universal Operational Amplifier EVM
TLV2460
D PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
8
2
7
3
6
4
5
SHDN
VDD+
OUT
NC
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Devices are available with an optional shutdown
terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown,
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
ORDERING INFORMATION†
−40°C to 125°C
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
D
Tape and reel
TLV2462AQDREP
2462AE
D
Tape and reel
TLV2463AQDREP
V2463AQE
D
Tape and reel
TLV2462AMDREP
2462AM
D
Tape and reel
TLV2464AMDREP
V2464AME
PW
Tape and reel
TLV2464AMPWREP
2464AME
† Some of the TLV246x family, along with packaging options, are in the Product Preview stage of
development. Contact the local Texas Instruments sales office for availability.
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TLV246x PACKAGE PINOUTS
TLV2461
D or PW PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
1OUT
1IN −
1IN+
GND
NC
1SHDN
NC
1
8
2
7
3
6
4
5
TLV2462
D or PW PACKAGE
(TOP VIEW)
NC
VDD+
OUT
NC
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
TLV2463
D or PW PACKAGE
TLV2464
D or PW PACKAGE
(TOP VIEW)
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD+
2OUT
2IN −
2IN+
NC
2SHDN
NC
1OUT
1IN −
1IN+
VDD+
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
NC − No internal connection
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VDD+
2OUT
2IN −
2IN+
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to VDD + 0.2 V
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 175 mA
Total input current, II (into VDD +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Total output current, IO (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
THERMAL RESISTANCE TABLE
θJC
(°C/W)
PACKAGE
θJA
(°C/W, 0 Air Flow)
High K
Low K
D (8)
39.4
42.4
97.1
High K
165.5
Low K
D (14)
51.5
53.7
86.2
133.5
PW (8)
65.1
69.4
149.4
230.5
PW (14)
45.8
46.6
111.7
131.4
NOTE: Thermal resistances are not production tested and are for
informational purposes only.
1e+08
805C 1.7e+07 Hrs (1.9e+03 years)
1e+07
Time-to-Fail − Hr
905C 5.2e+06 Hrs (5.9e+02 years)
1005C 1.7e+06 Hrs (1.9e+02 years)
1e+06
1105C 5.8e+05 Hrs (66 years)
1205C 2.1e+05 Hrs (24 years)
100000
1305C 8.2e+04 Hrs (9.3 years)
1405C 3.3e+04 Hrs (3.7 years)
10000
1000
80
90
100
110
120
130
140
150
Degrees C Continous − TJ
Figure 1. Wirebond Life Estimation Plot
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
recommended operating conditions
MIN
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage range, VICR
VIH
VIL
Shutdown on/off voltage level‡
Operating free-air temperature, TA
‡ Relative to voltage on the GND terminal of the device.
4
POST OFFICE BOX 655303
2.7
6
±1.35
±3
−0.2 VDD+0.2
2
0.7
−40
• DALLAS, TEXAS 75265
MAX
125
UNIT
V
V
V
°C
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient of input
offset voltage
IIO
Input offset current
IIB
Input bias current
TEST CONDITIONS
TA†
25°C
VDD = 3 V,
VO = 1.5 V,
VIC = 1.5 V,
RS = 50 Ω
Full range
VDD = 3 V,
VO = 1.5 V,
VIC = 1.5 V,
RS = 50 Ω
Full range
MIN
2.8
4.4
High-level output voltage
IOL = 2.5 mA
Low-level output voltage
IOL = 10 mA
Sourcing
2.5
0.1
Full range
0.2
0.5
Full range
IO
Output current
Measured 1 V from rail
AVD
Large-signal differential voltage
amplification
RL = 10 kΩ
ri(d)
Differential input resistance
ci(c)
Common-mode input
capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 100 kHz,
kSVR
Common-mode rejection ratio
Supply voltage rejection ratio
((∆V
VDD //∆V
VIO)
50
20
25°C
Sinking
AV = 10
VICR = 0 V to 3 V,
RS = 50 Ω
VDD = 2.7 V to 6 V,
No load
VIC = VDD /2,
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
Supply current (per channels)
VO = 1.5 V,
No load
IDD(SHDN)
Supply current in shutdown
(TLV2460, TLV2463)
SHDN < 0.7 V,
Per channel in shutdown
mA
40
20
± 40
25°C
25°C
90
Full range
89
mA
105
dB
25°C
109
Ω
25°C
7
pF
33
Ω
25°C
25°C
66
Full range
60
25°C
80
Full range
75
25°C
85
Full range
80
25°C
IDD
V
0.3
Full range
Full range
nA
V
2.7
25°C
Short-circuit output current
14
2.9
25°C
VIC = 1.5 V,
nA
2.8
25°C
VIC = 1.5 V,
V
µV
7
75
25°C
Full range
UNIT
µV/°C
75
25°C
Full range
IOH = − 10 mA
CMRR
1500
2
25°C
IOS
150
Full range
IOH = − 2.5 mA
VOL
MAX
1700
25°C
VOH
TYP
80
dB
85
0.5
Full range
25°C
Full range
dB
95
0.575
0.9
0.3
2.5
mA
A
µA
† Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
THD + N
t(on)
TEST CONDITIONS
VO(PP) = 2 V,
RL = 10 kΩ
CL = 160 pF,
TA†
25°C
Full
range
25°C
11
Equivalent input noise current
f = 1 kHz
25°C
0.13
Total harmonic distortion plus
noise
VO(PP) = 2 V,
RL = 10 kΩ, f = 1 kHz
Amplifier turnon time
AV = 1
AV = 10
Channel 1 only,
Channel 2 on
Amplifier turnoff time
Channel 1 only,
Channel 2 on
AV = 1, RL = 10 kΩ
Settling time
f = 10 kHz, CL = 160 pF
RL = 10 kΩ,
7.6
25°C
7.65
25°C
25
C
328
ns
329
25°C
5.2
0.1%
1.77
0.01%
1.98
RL = 10 kΩ,
CL = 160 pF
MHz
1.47
0.01%
1.78
25°C
• DALLAS, TEXAS 75265
µs
333
V(STEP)PP = 2 V,
AV = −1, CL = 56 pF,
RL = 10 kΩ
POST OFFICE BOX 655303
pA /√Hz
0.08%
0.1%
† Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
nV/√Hz
0.02%
V(STEP)PP = 2 V,
AV = −1, CL = 10 pF,
RL = 10 kΩ
Phase margin at unity gain
UNIT
0.006%
25°C
25
C
AV = 100
Both channels
AV = 1, RL = 10 kΩ
MAX
V/µs
0.8
f = 1 kHz
Gain margin
6
1.6
16
Gain-bandwidth product
φm
1
25°C
Channel 2 only,
Channel 1 on
ts
TYP
f = 100 Hz
Both channels
t(off)
MIN
25°C
44°
25°C
7
µss
dB
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset
voltage
IIO
Input offset current
IIB
Input bias current
VDD = 5 V,
VO = 2.5 V,
VDD = 5 V,
VO = 2.5 V,
TA†
25°C
VIC = 2.5,
RS = 50 Ω
Full range
VIC = 2.5 V,
RS = 50 Ω
Full range
MIN
1500
25°C
2
25°C
0.3
1.3
IOL = 2.5 mA
Low-level output voltage
IOL = 10 mA
Sourcing
4.7
0.1
Full range
0.2
0.3
145
60
25°C
Sinking
Full range
60
± 80
Output current
Measured at 1 V from rail
25°C
VIC = 2.5 V,
VO = 1 V to 4 V
25°C
92
AVD
Large-signal differential voltage
amplification
Full range
90
ri(d)
Differential input resistance
ci(c)
Common-mode input capacitance
f = 10 kHz
zo
Closed-loop output impedance
f = 100 kHz,
CMRR
Common-mode rejection ratio
VICR = 0 V to 5 V,
RS = 50 Ω
kSVR
Supply voltage rejection ratio
((∆V
VDD //∆V
VIO)
AV = 10
VDD = 2.7 V to 6 V,
No load
VIC = VDD /2,
VDD = 3 V to 5 V,
No load
VIC = VDD /2,
No load,
Supply current (per channel)
VO = 2.5 V,
IDD(SHDN)
Supply current in shutdown
(TLV2460, TLV2463)
SHDN < 0.7 V, Per channels in
shutdown
mA
109
dB
25°C
109
Ω
25°C
7
pF
25°C
29
Ω
25°C
71
Full range
60
25°C
80
Full range
75
25°C
85
Full range
80
25°C
IDD
mA
100
IO
RL = 10 kΩ,
V
0.2
Full range
Full range
nA
V
4.8
25°C
Short-circuit output current
14
4.8
25°C
VIC = 2.5 V,
nA
4.9
25°C
VIC = 2.5 V,
V
µV
7
60
25°C
Full range
UNIT
µV/°C
V/°C
60
25°C
Full range
High-level output voltage
IOH = − 10 mA
IOS
150
1700
25°C
VOL
MAX
Full range
IOH = − 2.5 mA
VOH
TYP
85
dB
85
dB
95
dB
0.55
Full range
25°C
Full range
0.65
1
1
3
mA
µA
A
† Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
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7
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
SR
Slew rate at unity gain
Vn
Equivalent input noise voltage
In
THD + N
t(on)
t(off)
TEST CONDITIONS
VO(PP) = 2 V,
RL = 10 kΩ
CL = 160 pF,
TA†
25°C
Full
range
1.6
f = 1 kHz
25°C
11
Equivalent input noise current
f = 100 Hz
25°C
0.13
Total harmonic distortion plus noise
VO(PP) = 4 V,
RL = 10 kΩ,
f = 10 kHz
Amplifier turnon time
Amplifier turnoff time
AV = 1
AV = 10
AV = 1, RL = 10 kΩ
AV = 1, RL = 10 kΩ
Settling time
7.6
25°C
25
C
7.65
Both channels
333
25
C
25°C
328
RL = 10 kΩ,
V(STEP)PP = 2 V,
AV = −1,
CL = 10 pF,
RL = 10 kΩ
0.1%
V(STEP)PP = 2 V,
AV = −1,
CL = 56 pF,
RL = 10 kΩ
0.1%
3.13
0.01%
3.33
RL = 10 kΩ,
CL = 160 pF
POST OFFICE BOX 655303
25°C
ns
6.4
MHz
1.53
0.01%
1.83
µss
25°C
• DALLAS, TEXAS 75265
µs
329
f = 10 kHz,
CL = 160 pF
† Full range is −40°C to 125°C for the Q suffix and −55°C to 125°C for the M suffix.
pA /√Hz
0.04%
7.25
Phase margin at unity gain
nV/√Hz
0.01%
Channel 2 only,
Channel 1 on
Channel 1 only,
Channel 2 on
UNIT
0.004%
25°C
25
C
AV = 100
Both channels
Channel 1 only,
Channel 2 on
MAX
V/µs
0.8
14
Gain margin
8
1
25°C
Gain-bandwidth product
φm
TYP
f = 100 Hz
Channel 2 only,
Channel 1 on
ts
MIN
25°C
45°
25°C
7
dB
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
IIB
Input offset voltage
vs Common-mode input voltage
1, 2
Input bias current
vs Free-air temperature
3, 4
IIO
VOH
Input offset current
vs Free-air temperature
3, 4
High-level output voltage
vs High-level output current
5, 6
VOL
VO(PP)
Low-level output voltage
vs Low-level output current
7, 8
Peak-to-peak output voltage
vs Frequency
9, 10
Open-loop gain
vs Frequency
11, 12
Phase
vs Frequency
11, 12
Differential voltage amplification
vs Load resistance
13
Capacitive load
vs Load resistance
14
Zo
CMRR
Output impedance
vs Frequency
15, 16
Common-mode rejection ratio
vs Frequency
17
kSVR
Supply-voltage rejection ratio
vs Frequency
18, 19
AVD
IDD
Supply current
vs Supply voltage
20
vs Free-air temperature
21
Amplifier turnon characteristics
22
Amplifier turnoff characteristics
23
Supply current turnon
24
Supply current turnoff
SR
25
Shutdown supply current
vs Free-air temperature
Slew rate
vs Supply voltage
26
27
vs Frequency
28, 29
vs Common-mode input voltage
30, 31
Vn
Equivalent input noise voltage
THD
Total harmonic distortion
vs Frequency
32, 33
THD+N
Total harmonic distortion plus noise
vs Peak-to-peak signal amplitude
34, 35
vs Frequency
11, 12
φm
Phase margin
vs Load capacitance
36
vs Free-air temperature
37
vs Supply voltage
38
vs Free-air temperature
39
Gain bandwidth product
Large signal follower
40, 41
Small signal follower
42, 43
Inverting large signal
44, 45
Inverting small signal
46, 47
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9
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
VDD = 5 V
TA = 25°C
0.8
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
0.8
1
VDD = 3 V
TA = 25°C
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
0.5
1
1.5
2
2.5
−1
3
0
VICR − Common-Mode Input Voltage − V
1
Figure 2
VDD = 3 V
VI = 1.5 V
4.5
IIB
4
3.5
3
2.5
2
1.5
1
0.5
IIO
−15
5
25
5
45
65
85
105
125
6
VDD = 5 V
VI = 2.5 V
5
IIB
4
3
2
1
IIO
0
−1
−55 −35
TA − Free-Air Temperature − °C
−15
5
25
Figure 5
POST OFFICE BOX 655303
45
65
85
TA − Free-Air Temperature − °C
Figure 4
10
4
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
I IB and I IO − Input Bias and Input Offset Current − nA
I IB and I IO − Input Bias and Input Offset Current − nA
5
−0.5
−55 −35
3
Figure 3
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0
2
VICR − Common-Mode Input Voltage − V
• DALLAS, TEXAS 75265
105
125
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
5
VDD = 5 VDC
4.5
2.5
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 3 VDC
TA = −55°C
2
1.5
TA = 125°C
TA = 85°C
TA = 25°C
1
TA = −40°C
0.5
TA = −55°C
4
3.5
3
2.5
2
TA = 125°C
TA = 85°C
TA = 25°C
1.5
TA = −40°C
1
0.5
0
0
10
20
30
40
50
60
70
0
80
0
IOH − High-Level Output Current − mA
20
40
60
Figure 6
100 120 140 160 180 200
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
4.5
VDD = 3 VDC
VDD = 5 VDC
4
2.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
80
IOH − High-Level Output Current − mA
TA = −40°C
2
TA = 25°C
1.5
TA = 85°C
TA = 125°C
1
0.5
0
10
20
30
40
50
60
TA = −40°C
3
TA = 25°C
2.5
TA = 85°C
TA = 125°C
2
1.5
1
TA = −55°C
0.5
TA = −55°C
0
3.5
70
IOL − Low-Level Output Current − mA
0
0
20
40
60
80
100
120
140
160
IOL − Low-Level Output Current − mA
Figure 8
Figure 9
POST OFFICE BOX 655303
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11
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
5.5
VDD = 3 V
AV = −10
THD = 1%
RL = 10 kΩ
2.5
2
1.5
1
0.5
0
10k
100k
1M
VDD = 5 V
AV = −10
THD = 1%
RL = 10 kΩ
5
VO(PP) − Peak-to-Peak Output Voltage − V
VO(PP) − Peak-to-Peak Output Voltage − V
3
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
10k
10M
100k
f − Frequency − Hz
1M
f − Frequency − Hz
Figure 10
Figure 11
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
VDD = ±1.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
90
80
60
0°
−20°
−40°
AVD
50
−60°
40
−80°
−100°
30
Phase
20
−120°
10
−140°
0
−160°
−10
−180°
−20
10
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 12
12
20°
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−200°
10M
Phase
Open-Loop Gain − dB
70
40°
10M
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
VDD = ±2.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
90
80
60
20°
0°
−20°
−40°
AVD
50
−60°
40
−80°
−100°
30
Phase
20
−120°
10
−140°
0
−160°
−10
−20
10
Phase
Open-Loop Gain − dB
70
40°
−180°
100
1k
100k
10k
1M
−200°
10M
f − Frequency − Hz
Figure 13
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
CAPACITIVE LOAD
vs
LOAD RESISTANCE
10000
TA = 25°C
160
140
CL − Capacitive Load − pF
A VD − Differential Voltage Amplification − V/mV
180
120
VDD = ±2.5 V
100
VDD = ±1.5 V
80
60
40
Phase Margin < 30°
1000
Phase Margin > 30°
VDD = 5 V
Phase Margin = 30°
TA = 25°C
20
0
100
1k
10k
100k
1M
100
10
RL − Load Resistance − Ω
100
1k
10k
RL − Load Resistance − Ω
Figure 15
Figure 14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
VDD = ±1.5 V
TA = 25°C
100
Zo − Output Impedance − Ω
Zo − Output Impedance − Ω
100
10
AV = 100
1
AV = 10
0.1
VDD = ±2.5 V
TA = 25°C
AV = 1
10
AV = 100
1
AV = 10
0.1
AV = 1
0.01
100
1k
10k
100k
1M
0.01
100
10M
1k
f − Frequency − Hz
10k
Figure 16
Figure 17
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
90
85
80
VDD = 5 V
VIC = 2.5 V
75
VDD = 3 V
VIC = 1.5 V
70
65
60
10
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 18
14
100k
f − Frequency − Hz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10M
1M
10M
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
90
+kSVR
VDD = ±1.5 V
TA = 25°C
100
k SVR − Supply Voltage Rejection Ratio − dB
k SVR − Supply Voltage Rejection Ratio − dB
110
90
−kSVR
80
70
60
+kSVR
50
−kSVR
40
10
100
1k
10k
100k
1M
+kSVR
80
−kSVR
70
60
+kSVR
50
−kSVR
40
10
10M
VDD = ±2.5 V
TA = 25°C
100
1k
f − Frequency − Hz
10k
100k
1M
10M
f − Frequency − Hz
Figure 19
Figure 20
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.8
0.80
IDD = 125°C
I DD − Supply Current − mA
I DD − Supply Current − mA
0.75
IDD = 85°C
0.7
0.6
0.5
0.40
IDD = 25°C
0.30
IDD = −55°C
VDD = 5 V
VI = 2.5 V
0.65
0.60
0.55
VDD = 3 V
VI = 1.5 V
0.50
0.45
0.40
IDD = −40°C
0.20
0.70
0.35
0.10
2.5
3
3.5
4
4.5
5
5.5
6
0.30
−55 −35
VDD − Supply Voltage − V
−15
5
25
45
65
85
105
125
TA − Free-Air Temperature − °C
Figure 21
Figure 22
POST OFFICE BOX 655303
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15
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
5
5
4
Shutdown Pin
3
2
1
0
Amplifier Output
3
2
1
0
−5
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
3
VSD − Shutdown Voltage − V
VSD − Shutdown Voltage − V
4
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
−3
−1
2
1
0
Amplifier Output
3
2
1
1
3
5
9
7
0
−5
11
−3
−1
t − Time − µs
1
t − Time − µs
Figure 24
Figure 23
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
1
5.5
0.8
4.5
0.6
3.5
Supply Current
0.4
2.5
0.2
1.5
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0
−0.2
−0.4
−0.2
0
0.2
0.4
t − Time − µs
Figure 25
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.5
−0.5
0.6
VSD − Shutdown Voltage − V
I DD − Supply Current − mA
Shutdown Pin
3
5
7
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
1
5.5
4.5
0.6
0.4
3.5
Supply Current
2.5
0.2
1.5
0
0.5
−0.2
−0.4
−0.2
0
0.2
VSD − Shutdown Voltage − V
Shutdown Pin
0.8
I DD − Supply Current − mA
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
−0.5
0.6
0.4
t − Time − µs
Figure 26
SLEW RATE
vs
SUPPLY VOLTAGE
3
1.8
2.5
1.75
1.7
VDD = 5 V
VI = 2.5 V
2
SR − Slew Rate − V/ µs
I DD − Shutdown Supply Current − µ A
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.5
1
VDD = 3 V
VI = 1.5 V
0.5
0
SR+
1.65
1.6
1.55
1.5
1.45
1.4
−0.5
−1
−55 −35
1.35
−15
5
25
45
65
85
105
125
SR−
1.3
2.5
VO(PP) = 2 V
CL = 160 pF
AV = 1
RL = 10 kΩ
TA = 25°C
3
TA − Free-Air Temperature − °C
3.5
4
4.5
5
5.5
6
VDD − Supply Voltage − V
Figure 28
Figure 27
POST OFFICE BOX 655303
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17
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
18
VDD = 3 V
AV = 10
VI = 1.5 V
TA = 25°C
17
Vn − Equivalent Input Noise Voltage − nV/ Hz
Vn − Equivalent Input Noise Voltage − nV/ Hz
18
16
15
14
13
12
11
10
100
1k
10k
VDD = 5 V
AV = 10
VI = 2.5 V
TA = 25°C
17
16
15
14
13
12
11
10
100
100k
1k
f − Frequency − Hz
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
20
20
VDD = 3 V
AV = 10
f = 1 kHz
TA = 25°C
15
Vn − Equivalent Input Noise Voltage − nV/ Hz
Vn − Equivalent Input Noise Voltage − nV/ Hz
100k
Figure 30
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
14
13
12
11
10
0
0.5
1
1.5
2
2.5
3
VICR − Common-Mode Input Voltage − V
VDD = 5 V
AV = 10
f = 1 kHz
TA = 25°C
15
14
13
12
11
10
0
1
2
Figure 32
POST OFFICE BOX 655303
3
4
VICR − Common-Mode Input Voltage − V
Figure 31
18
10k
f − Frequency − Hz
• DALLAS, TEXAS 75265
5
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1
VDD = ±1.5 V
VO(PP) = 2 V
RL = 10 kΩ
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
0.5
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
AV = 100
0.1
AV = 10
0.010
0.001
AV = 1
10
100
1k
10k
0.1
AV = 100
AV = 10
0.010
AV = 1
0.001
100k
VDD = ±2.5 V
VO(PP) = 4 V
RL = 10 kΩ
10
100
1k
f − Frequency − Hz
Figure 33
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
1
RL = 250 Ω
RL = 2 kΩ
0.1
RL = 10 kΩ
0.010
RL = 100 kΩ
0.001
1
1.2 1.4 1.6 1.8 2
100k
Figure 34
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
VDD = 3 V
AV = 1
TA = 25°C
10k
f − Frequency − Hz
2.2 2.4 2.6 2.8
3
3.2
1
RL = 250 Ω
RL = 2 kΩ
0.1
RL = 10 kΩ
0.010
RL = 100 kΩ
VDD = 5 V
AV = 1
TA = 25°C
0.001
4
4.1 4.2
Peak-to-Peak Signal Amplitude − V
4.3
4.4
4.5 4.6
4.7 4.8 4.9
5
Peak-to-Peak Signal Amplitude − V
Figure 35
Figure 36
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• DALLAS, TEXAS 75265
19
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
90
80
RL = 10 kΩ
CL = 160 pF
55
70
φ m − Phase Margin − degrees
φ m − Phase Margin − degrees
60
VDD = ±2.5 V
TA = 25°C
RL = 10 kΩ
Rnull = 50 Ω
60
50
40
Rnull = 20 Ω
30
20
Rnull = 0 Ω
50
VDD = ±2.5 V
45
VDD = ±1.5 V
40
35
10
0
100
10
1k
30
−55 −35
100k
10k
CL − Load Capacitance − pF
−15
Figure 37
45
65
85
105
125
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
5
5
CL = 160 pF
RL = 10 kΩ
f = 10 kHz
TA = 25°C
4.75
Gain Bandwidth Product − MHz
Gain Bandwidth Product − MHz
25
Figure 38
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
4.75
5
TA − Free-Air Temperature − °C
4.5
4.25
4
3.75
4.5
RL = 10 kΩ
CL = 160 pF
VDD = ±2.5 V
4.25
4
3.75
3.5
VDD = ±1.5 V
3.25
3.5
2.5
3
3.5
4
4.5
5
5.5
6
3
−55 −35
VDD − Supply Voltage − V
Figure 39
20
−15
5
25
Figure 40
POST OFFICE BOX 655303
45
65
85
TA − Free-Air Temperature − °C
• DALLAS, TEXAS 75265
105
125
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
LARGE SIGNAL FOLLOWER
LARGE SIGNAL FOLLOWER
2.2
3.7
2
3.3
VO − Voltage − V
Input
VO − Voltage − V
Input
1.8
Output
1.6
1.4
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
1.2
1
0.8
−2
0
2
4
6
Input
2.9
Output
2.5
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
2.1
Output
1.7
8
10
12
14
16
1.3
−2
18
0
2
4
6
t − Time − µs
8
10
12
14
16
18
Figure 42
SMALL SIGNAL FOLLOWER
SMALL SIGNAL FOLLOWER
1.6
2.6
1.55
2.55
VO − Voltage − V
VO − Voltage − V
Output
t − Time − µs
Figure 41
Input
1.5
Output
1.45
1.4
−0.2
Input
Input
2.5
Output
2.45
VDD = 3 V
VI(PP) = 100 mV CL = 160 pF
AV = 1
VI = 1.5 V
TA = 25°C
RL = 10 kΩ
0
0.2
0.4
0.6
0.8
1
1.2 1.4
1.6 1.8
2.4
−0.2
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
0
t − Time − µs
0.2
0.4
0.6
CL = 160 pF
AV = 1
TA = 25°C
0.8
1
1.2 1.4
1.6 1.8
t − Time − µs
Figure 43
Figure 44
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• DALLAS, TEXAS 75265
21
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
INVERTING LARGE SIGNAL
INVERTING LARGE SIGNAL
4
2.3
Input
2.1
Input
3.5
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.7
1.5
1.3
VO − Voltage − V
VO − Voltage − V
1.9
1.1
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
3
2.5
2
Output
0.9
Output
1.5
0.7
0.5
−0.2
0
0.2
0.4
0.6
0.8
1
1.2 1.4
1
−0.2
1.6 1.8
0
0.2
0.4
t − Time − µs
0.6
Figure 45
INVERTING SMALL SIGNAL
1.6 1.8
INVERTING SMALL SIGNAL
Input
Input
2.55
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.5
VO − Voltage − V
VO − Voltage − V
1.2 1.4
2.6
1.55
1.45
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
2.5
2.45
Output
0
0.2
0.4
0.6
0.8
Output
1
1.2 1.4
1.6 1.8
2.4
−0.2
0
t − Time − µs
0.2
0.4
0.6
0.8
1
t − Time − µs
Figure 47
22
1
Figure 46
1.6
1.4
−0.2
0.8
t − Time − µs
Figure 48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.2 1.4
1.6 1.8
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
Rnull
_
+
RL
CL
Figure 49
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
RF
RG
RNULL
_
Input
Output
+
CLOAD
Figure 50. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
IIB+
V
OO
+V
IO
ǒ ǒ ǓǓ
1)
R
R
F
G
VO
+
RS
"I
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
R
F
Figure 51. Output Offset Voltage Model
POST OFFICE BOX 655303
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23
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
RG
RF
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
1)
R
R
F
G
–3dB
Ǔǒ
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 52. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
RG =
Figure 53. 2-Pole Low-Pass Sallen-Key Filter
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–3dB
+
(
1
2pRC
RF
1
2−
Q
)
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
APPLICATION INFORMATION
shutdown function
Two members of the TLV246x family (TLV2460/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g. ± 2.5 V), the shutdown terminal needs to
be pulled to VDD− (not GND) to disable the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
P
D
+
Where:
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of THS246x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
TJ = 150°C
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 54. Maximum Power Dissipation vs Free-Air Temperature
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
EGND +
R2
3
VDD +
−
+
ISS
RSS
CSS
VD
−
53
RP
10
2
IN −
J1
FB
6
7
+
9
VLIM
+
VB
8
GA
GCM
J2
−
−
DC
RO1
OUT
IN +
1
11
12
RD1
5
DLN
DE
92
54
C1
DP
+
RD2
VE
GND
RO2
C2
.SUBCKT TLV246X 1 2 3 4 5
C1
11
12
2.46034E−12
C2
6
7
10.0000E−12
CSS
10
99
443.21E−15
DC
5
53
DY
DE
54
5
DY
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
GA
6
0
11
12 345.26E−6
GCM
0
6
10
99 15.4226E−9
ISS
10
4
DC 18.850E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX1
J2
12
1
10 JX2
R2
6
9
100.00E3
−
−
−
+
90
HLIM
−
4
+ DLP
91
+
VLP
VLN
RD1
3
11
2.8964E3
RD2
3
12
2.8964E3
R01
8
5
5.6000
R02
7
99
6.2000
RP
3
4
8.9127
RSS
10
99
10.610E6
VB
9
0
DC 0
VC
3
53
DC .7836
VE
54
4
DC .7436
VLIM
7
8
DC 0
VLP
91
0
DC 117
VLN
0
92
DC 117
.MODEL DX D (IS=800.00E−18)
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.ENDS
Figure 55. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SGLS132C − AUGUST 2002 − REVISED OCTOBER 2005
macromodel information (continued)
.subckt TLV_246Y 1 2 3 4 5 6
c1
11
12
2.4603E−12
c2
72
7
10.000E−12
css
10
99
443.21E−15
dc
70
53
dy
de
54
70
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
21.600E6 −1E3 1E3 22E6 −22E6
ga
72
0
11 12 345.26E−6
gcm
0
72
10 99 15.422E−9
iss
74
4
dc 18.850E−6
hlim
90
0
vlim 1K
j1
11
2
10 jx1
j2
12
1
10 jx2
r2
72
9
100.00E3
rd1
3
11
2.8964E3
rd2
3
12
2.8964E3
ro1
8
70
5.6000
ro2
7
99
6.2000
rp
3
71
8.9127
rss
10
99
10.610E6
rs1
6
4
1G
rs2
6
4
1G
rs3
6
4
1G
rs4
6
4
1G
s1
71
4
6 4 s1x
s2
70
5
6 4 s1x
s3
10
74
6 4 s1x
s4
74
4
6 4 s2x
vb
9
0
dc 0
vc
3
53
dc .7836
ve
54
4
dc .7436
vlim
7
8
dc 0
vlp
91
0
dc 117
vln
0
92
dc 117
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
Figure 54. Boyle Macromodels and Subcircuit (Continued)
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2462AMDREP
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2462AM
TLV2462AQDREP
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462AE
TLV2464AMDREP
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
V2464AME
TLV2464AMDREPG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
V2464AME
TLV2464AMPWREP
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2464AME
V62/03619-03XE
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2462AE
V62/03619-06XE
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2462AM
V62/03619-07YE
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
V2464AME
V62/03619-07ZE
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2464AME
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2462A-EP, TLV2464A-EP :
• Catalog: TLV2462A, TLV2464A
• Automotive: TLV2462A-Q1, TLV2464A-Q1
• Military: TLV2462AM
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TLV2462AMDREP
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2462AQDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLV2464AMDREP
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLV2464AMPWREP
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2462AMDREP
SOIC
D
8
2500
367.0
367.0
35.0
TLV2462AQDREP
SOIC
D
8
2500
367.0
367.0
35.0
TLV2464AMDREP
SOIC
D
14
2500
333.2
345.9
28.6
TLV2464AMPWREP
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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