Selecting the right core for your MIL-STD-1553

Selecting the right core for your MIL-STD-1553
Release 100126
Selecting the right core for your MIL-STD-1553 application
Sital Technology offers several 1553 Remote Terminal (RT) and Bus Controller (BC) cores.
These cores are intended for different applications. A proper selection of the right core would
reduce design and maintenance efforts.
The BRM1553FE is an RT, BC or MT core intended for subsystems that need 1553 interface but
the messages transferred to and from the RT are defined as “simple”.
“Simple” means that every 1553 message is composed of a command pointing to a Sub Address
(SA), and indicating the number of words for that SA. (i.e., SA is the paragraph, and the words
are the sentences). If the words are dealt with individually for all the messages, then the RT is
defined as simple.
On the other hand, if 2 or more words define a data record such that if one of the words of the
record has errors then the whole record is an error, the messages could not be defined as simple.
For example: Assume an ICD (Interface Communication Document) for an F-16 camera RT uses
two SAs. The first SA has one word. If this word’s value is 0xAAAA, than the camera should start
recording, and if its 0xBBBB it should stop. The second SA has two words for reading. The first
word defines the Camera model. The second word indicates the tape position.
This application would be considered a simple RT and can use the BRM1553FE core saving the
need for a CPU to control 1553 interface to the camera.
Usage of the BRM1553FE has shown dramatic development cost reductions gain by saving the
need for a CPU and Software development, Hardware-software integration, and firmware
maintenance.
An ICD that incorporates a SA with 3 words of which the first define a relative X position, the
second word defines the Y position, and the third defines the Z position would not be considered
a simple message. If, for some reason, only part of the message is transferred, the whole SA
message should be dropped.
For these applications, the BRM1553D core should be used. This core is a superset of the
BRM1553FE with a backend logic that arranges the messages in a predefined memory structure
that will validate or invalidate a message on a message base rather than on a word base, as does
the BRM1553FE.
It should be noted that there are other / simpler ways to manage the message level control rather
than the method used at the BRM1553D core, and these methods could be developed by the
user logic that interfaces the BRM1553FE.
Sital can work with the user to suggest ways to implement different interfaces over the
BRM1553FE core.
The BRM1553PCI core is a superset of the BRM1553D. This IP core includes the DDC
Enhanced MiniACE software interface, with PCI interface to the host CPU, saving the need for a
PCI to local bus bridge.
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Release 100126
Comparison Table:
BRM1553FE / ERL
BRM1553D
BRM1553PCI
Main Application
Simple 1553 interface (FE)
Space, Radiation Tolerant
(ERL)
Complex 1553
applications, DDC
MiniACE, Enhanced
MiniACE and uACE
replacement .
Complex 1553 applications,
DDC MiniACE, Enhanced
MiniACE and uACE
replacement, with PCI
interface.
Compatibility
Mil-Std-1553B Notice 2
Mil-Std-1553B Notice 2
DDC Enhanced MiniACE
Back-End
Mil-Std-1553B Notice 2
DDC Enhanced MiniACE
Back-End
33/66MHz PCI bus interface
Available Modes
Bus Controller (BC)
Remote Terminal (RT)
Bus Monitor (MT)
And any combination.
Bus Controller (BC)
Remote Terminal (RT)
Bus Monitor (MT)
And any combination.
Bus Controller (BC)
Remote Terminal (RT)
Bus Monitor (MT)
And any combination.
764 to 1059 4-LUT,
Depending on FPGA type
RT only:
2800 to 3400 4-LUT
Depending on FPGA type
RT only:
3100 to 3700 4-LUT
Depending on FPGA type
BC + RT + MT:
3950 to 4320 4-LUT
Depending on FPGA type
BC + RT + MT:
4250 to 4620 4-LUT
Depending on FPGA type
FPGA Requirements
Area Utilization
External Pins
10 pins to connect to
Xceiver
Standard FPGA pins
10 pins to connect to
Xceiver
Standard FPGA pins
10 pins to connect to Xceiver
Standard FPGA pins
PCI bus interface
(depending on configuration)
Memory Required
32 x 16 bits
2, 4, 8, 16, 32
or 64K x 16 bits
2, 4, 8, 16, 32
or 64K x 16 bits
Clock Frequency
Any even frequency of
12Mhz or more.
Any even frequency of
12Mhz or more.
33 or 66MHz
CPU Required
No
Yes
Yes
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