User manual | X20CP1301, X20CP1381 and X20CP1382

X20CP1301, X20CP1381 and X20CP1382
X20CP1301, X20CP1381 and X20CP1382
1 General information
Compact CPUs are available with processor speeds of 200 MHz and 400 MHz. Depending on the variant, up to
256 MB RAM and up to 32 kB nonvolatile onboard RAM is available. A built-in flash drive is available to store up
to 2 GB of application and other data.
All CPUs come equipped with Ethernet, USB and one RS232 interface. In both performance classes, integrated
POWERLINK and CAN bus interfaces are also available. If additional fieldbus connections are needed, all CPUs
can be upgraded with an interface module from the standard X20 product range. These CPUs do not require fans
or batteries and are therefore maintenance-free. 30 different digital inputs and outputs and two analog inputs are
integrated in the devices. One analog input can be used for PT1000 resistance temperature measurement.
•
•
•
•
•
•
•
•
•
CPU is Intel® ATOM™ 400 MHz compatible with integrated I/O processor
Ethernet, POWERLINK with poll-response chaining and USB onboard
1 slot for modular interface expansion
30 digital inputs/outputs and two analog inputs integrated in the device
1/2 GB flash drive onboard
128/256 MB DDR3 SDRAM
Fanless
No battery
Battery-backed real-time clock
Data sheet V 0.38
1
X20CP1301, X20CP1381 and X20CP1382
2 Order data
Model number
X20CP1301
X20CP1381
X20CP1382
Short description
X20 CPUs
X20 CPU, with integrated I/O, x86-200, 128 MB DDR3 RAM, 16 kB FRAM, 1 GB flash drive
onboard, 1 insert slot for X20 interface modules, 1 USB interface, 1 RS232 interface, 1 Ethernet
interface 10/100 Base-T, 14 digital inputs, 24 VDC, sink, 4 digital inputs, 2 µs, 24 VDC, sink, 4
digital outputs, 24 VDC, 0.5 A, source, 4 digital outputs, 2 µs, 24 VDC, 0.2 A, 4 digital inputs/outputs, 24 VDC, 0.5 A, 2 analog inputs ±10 V or 0 to 20 mA / 4 to 20 mA, 1 PT1000 instead of an
analog input, including power supply module, 3x X20TB1F terminal blocks, slot cover and X20
locking plate X20AC0SR1 (right) included
X20 CPU, with integrated I/O, x86-200, 128 MB DDR3 RAM, 16 kB FRAM, 2 GB flash drive
on board, 1 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 CAN
bus interface, 1 POWERLINK interface, 1 Ethernet interface 10/100 Base-T, 14 digital inputs, 24
VDC, sink, 4 digital inputs, 2 µs, 24 VDC, sink, 4 digital outputs, 24 VDC, 0.5 A, source, 4 digital
outputs, 2 µs, 24 VDC, 0.2 A, 4 digital inputs/outputs, 24 VDC, 0.5 A, 2 analog inputs ±10 V or 0 to
20 mA / 4 to 20 mA, 1 PT1000 instead of an analog input, including supply module, 3x X20TB1F
terminal blocks, slot cover and X20AC0SR1 locking plate (right) included
X20 CPU, with integrated I/O, x86-400, 256 MB DDR3 RAM, 32 kB FRAM, 2 GB flash drive
on board, 2 insert slot for X20 interface modules, 2 USB interfaces, 1 RS232 interface, 1 CAN
bus interface, 1 POWERLINK interface, 1 Ethernet interface 10/100 Base-T, 14 digital inputs, 24
VDC, sink, 4 digital inputs, 2 µs, 24 VDC, sink, 4 digital outputs, 24 VDC, 0.5 A, source, 4 digital
outputs, 2 µs, 24 VDC, 0.2 A, 4 digital inputs/outputs, 24 VDC, 0.5 A, 2 analog inputs ±10 V or 0 to
20 mA / 4 to 20 mA, 1 PT1000 instead of an analog input, including supply module, 3x X20TB1F
terminal blocks, slot cover and X20AC0SR1 locking plate (right) included
Table 1: Order data
Content of delivery
Model number
X20AC0SR1
X20TB1F
Quantity
1
1
3
Short description
Interface module slot cover
X20 locking plate, right
X20 terminal block, 16-pin, 24 VDC keyed
Table 2: Content of delivery
2
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
3 Technical data
Product ID
Short description
Interfaces
System module
General information
Cooling
B&R ID code
Status indicators
Diagnostics
Outputs
CPU function
CAN bus data transfer
RS232 data transfer
Inputs
Ethernet
I/O supply
POWERLINK
Supply voltage monitoring
Overtemperature
Terminating resistors
CPU redundancy possible
ACOPOS capability
reACTION-capable I/O channels
Visual Components support
Power consumption without interface module and
USB
Internal power consumption of the X2X Link and I/
O supply 1)
Bus
Internal I/O
Additional power dissipation caused by the actuators (resistive) [W]
Electrical isolation
Power supply
I/O feed - I/O supply
CPU/X2X Link feed - CPU/IF6
IF1 - IF2
IF1 - IF3
IF1 - IF4
IF1 - IF5
IF1 - IF6
IF1 - IF7
IF2 - IF3
IF2 - IF4
IF2 - IF5
IF2 - IF6
IF2 - IF7
IF3 - IF4
IF3 - IF5
IF3 - IF6
IF3 - IF7
IF4 - IF5
IF4 - IF6
IF4 - IF7
IF5 - IF6
IF5 - IF7
IF6 - IF7
Channel - Bus
Channel - Channel
Channel - PLC
PLC - IF1 (RS232)
PLC - IF2 (Ethernet)
PLC - IF3 (POWERLINK)
PLC - IF4 (USB)
PLC - IF5 (USB)
PLC - IF6 (X2X Link)
PLC - IF7 (CAN bus)
Certification
CE
GOST-R
X20CP1301
X20CP1381
1x RS232, 1x Ethernet,
1x USB, 1x X2X Link
0xE35B
CPU function, Ethernet,
RS232, CPU supply, I/O supply, I/O function per channel
X20CP1382
1x RS232, 1x Ethernet, 1x POWERLINK, 2x USB, 1x X2X Link, 1x CAN bus
CPU
Fanless
0xE35C
0xDABB
CPU function, Ethernet, POWERLINK, RS232, CAN bus, CAN bus
terminating resistor, CPU supply, I/O supply, I/O function per channel
Digital outputs: Yes, using status LED and software (output error status)
Yes, using status LED
Yes, using status LED
Yes, using status LED
Analog inputs: Yes, using status LED and software
Yes, using status LED
Yes, using status LED
Yes, using status LED
Yes, using status LED
Yes, using software
Yes, using status LED
No
Yes
No
Yes
TBD
TBD
TBD
-
No
Yes
Yes
-
Yes
No
-
No
Yes
-
No
Yes
Yes
-
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
No
Yes
-
No
Yes
No
Yes
Yes
No
No
No
Yes
-
Yes
No
-
No
Yes
-
No
Yes
Yes
Table 3: Technical data
Data sheet V 0.38
3
X20CP1301, X20CP1381 and X20CP1382
Product ID
CPU and X2X Link supply
Input voltage
Input current
Fuse
Reverse polarity protection
X2X Link supply output
Nominal output power
Parallel operation
Redundant operation
Input I/O supply
Input voltage
Fuse
Output I/O supply
Rated output voltage
Permitted contact load
Controller
Real-time clock
FPU
Processor
Type
Clock frequency
L1 cache
Data code
Program code
L2 cache
Integrated I/O processor
Modular interface slots
Remanent variables
Shortest task class cycle time
Typical instruction cycle time
Standard memory
RAM
Application memory
Type
Data retention
Writable data amount
Guaranteed
Results for 5 years
Guaranteed clear/write cycles
Error correction coding (ECC)
Interfaces
IF1 interface
Signal
Design
Max. distance
Transfer rate
IF2 interface
Signal
Design
Cable length
Transfer rate
Transmission
Physical interfaces
Half-duplex
Full-duplex
Autonegotiation
Auto-MDI / MDIX
IF3 interface
Fieldbus
Type
Design
Cable length
Transfer rate
Transmission
Physical interfaces
Half-duplex
Full-duplex
Autonegotiation
Auto-MDI / MDIX
IF4 interface
Type
Design
Max. output current
X20CP1301
X20CP1381
X20CP1382
24 VDC -15% / +20%
Max. TBD A
Integrated, cannot be replaced
Yes
2W
Yes 2)
Yes 3)
24 VDC -15% / +20%
Required line fuse: Max. 10 A, slow-blow
24 VDC
10 A
Buffering for at least 300 hours at 25°C, 1 s resolution, -18 to 28 ppm accuracy at 25°C
Yes
Vx86EX
200 MHz
400 MHz
16 kB
16 kB
128 kB
Processes I/O data points in the background
1
16 kB FRAM, buffering >10 years 4)
2 ms
0.0419 µs
32 kB FRAM, buffering >10 years 4)
1 ms
0.0199 µs
128 MB DDR3 SDRAM
256 MB DDR3 SDRAM
1 GB eMMC flash memory
2 GB eMMC flash memory
10 years
40 TB
21.9 GB/day
20,000
Yes
RS232
Connection made using 16-pin X20TB1F terminal block
900 m
Max. 1152 kbit/s
Ethernet
1x RJ45 shielded
Max. 100 m between 2 stations (segment length)
10/100 Mbit/s
10BASE-T / 100BASE-TX
Yes
Yes
Yes
Yes
-
POWERLINK managing or controlled node
Type 4 5)
1x RJ45 shielded
Max. 100 m between 2 stations (segment length)
100 Mbit/s
-
100BASE-TX
Yes
No
Yes
Yes
USB 1.1/2.0
Type A
0.5 A
Table 3: Technical data
4
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
Product ID
IF5 interface
Type
Design
Max. output current
IF6 interface
Fieldbus
IF7 interface
Signal
Design
Max. distance
Transfer rate
Terminating resistors
Controller
Digital inputs
Quantity
Nominal voltage
Input voltage
Input current at 24 VDC
Input filter
Hardware
Software
Connection type
Input circuit
Additional functions
Input resistance
Switching threshold
Low
High
AB incremental encoder
Quantity
Encoder inputs
Counter size
Input frequency
Evaluation
Encoder supply
Overload behavior of the encoder supply
ABR incremental encoder
Quantity
Encoder inputs
Counter size
Input frequency
Evaluation
Encoder supply
Overload behavior of the encoder supply
Event counter
Quantity
Signal form
Evaluation
Input frequency
Counter frequency
Counter size
Time measurement
Possible measurements
Measurements per module
Counter size
Timestamp
Signal form
Analog inputs
Quantity
Input
Input type
Digital converter resolution
Voltage
Current
X20CP1301
X20CP1381
-
X20CP1382
USB 1.1/2.0
Type A
0.1 A
X2X Link master
-
CAN bus
Connection made using 16-pin X20TB1F terminal block
1000 m
Max. 1 MBit/s
Integrated in the module
SJA 1000
14 standard inputs, 4 high-speed inputs and 4 mixed channels, configurable as inputs or outputs using software
24 VDC
24 VDC -15% / +20%
X1 - Standard inputs: Typ. 3.5 mA
X2 - Standard inputs: Typ. 2.68 mA
X2 - High-speed inputs: Typ. 3.5 mA
X3 - Mixed channels: Typ. 2.68 mA
Standard inputs and mixed channels: ≤200 μs
High-speed inputs: ≤2 μs, when used as standard inputs: ≤200 μs
Default 1 ms, configurable between 0 and 25 ms in 0.1 ms intervals
1-wire connections
Sink
X2 - High-speed digital inputs:
2x 250 kHz event counting, 2x AB counter, ABR incremental encoder, direction/frequency, period measurement, gate measurement, differential time measurement, edge counters, edge times
X1 - Standard inputs: 6.8 kΩ
X2 - Standard inputs: 8.9 kΩ
X2 - High-speed inputs: 6.8 kΩ
X3 - Mixed channels: 8.9 kΩ
<5 VDC
>15 VDC
2
24 V, asymmetrical
32-bit
Max. 100 kHz
4x
Module-internal, max. 300 mA
Short circuit protection, overload protection
1
24 V, asymmetrical
32-bit
Max. 100 kHz
4x
Module-internal, max. 300 mA
Short circuit protection, overload protection
2
Square wave pulse
1x
Max. 250 kHz
250 kHz
32-bit
Period measurement, gate measurement, differential time measurement, edge counter, edge times
Each function up to 4x
32-bit
1 µs resolution
Square wave pulse
2 6)
±10 V or 0 to 20 mA / 4 to 20 mA, via different terminal connections
Differential input
±12-bit
12-bit
Table 3: Technical data
Data sheet V 0.38
5
X20CP1301, X20CP1381 and X20CP1382
Product ID
Conversion time
Output format
Data type
Voltage
Current
Input impedance in signal range
Voltage
Current
Load
Voltage
Current
Input protection
Permitted input signal
Voltage
Current
Output of the digital value during overload
Conversion procedure
Input filter
Max. error at 25°C
Voltage
Gain
Offset
Current
Gain
Offset
Max. gain drift
Voltage
Current
Max. offset drift
Voltage
Current
Common-mode rejection
DC
50 Hz
Common-mode range
Crosstalk between channels
Non-linearity
Voltage
Current
Temperature inputs resistance measurement
Quantity
Input
Digital converter resolution
Conversion time
Conversion procedure
Output format
Sensor
PT1000
Resistance measurement range
Temperature sensor resolution
Resistance measurement resolution
Input filter
Sensor standard
Common-mode range
Linearization method
Measuring current
Permitted input signal
Max. error at 25°C
Gain
Offset
Max. gain drift
Max. offset drift
Non-linearity
Standardized value range for resistance measurement
Crosstalk between channels
Common-mode rejection
50 Hz
DC
Temperature sensor standardization
PT1000
X20CP1301
X20CP1381
1 channel enabled: 100 µs
2 channels enabled: 200 µs
X20CP1382
INT
INT 0x8001 - 0x7FFF / 1 LSB = 0x0008 = 2.441 mV
INT 0x0000 - 0x7FFF / 1 LSB = 0x0008 = 4.883 μA
20 MΩ
<300 Ω
TBD: Protection against wiring with supply voltage
Max. ±30 V
Max. ±50 mA
Configurable
SAR
3rd-order low pass / cutoff frequency 1 kHz
0.18% (Rev. <C0: 0.37%) 7)
0.04% (Rev. <C0: 0.25%) 8)
0 to 20 mA = 0.15% (Rev. <C0: 0.52%) / 4 to 20 mA = 0.25% 7)
0 to 20 mA = 0.1% (Rev. <C0: 0.4%) / 4 to 20 mA = 0.15% 9)
0.017 %/°C 7)
0 to 20 mA = 0.015 %/°C / 4 to 20 mA = 0.023 %/°C 7)
0.008 %/°C 8)
0 to 20 mA = 0.008 %/°C / 4 to 20 mA = 0.012 %/°C 9)
70 dB
70 dB
±12 V
<-70 dB
<0.025 % 8)
<0.05 % 9)
1
Resistance measurement with constant current supply for 2-wire connections
13-bit
Only temperature input enabled: 200 µs
Temperature and analog input enabled: 400 µs
SAR
INT or UINT for resistance measurement
-200 to 850°C
01 to 4000 Ω
TBD: 1 LSB = 0.16°C
TBD: 1 LSB = 0.61 Ω
1st-order low pass / cutoff frequency 7 Hz
IEC/EN 60751
1V
Internal
1 mA
Short-term max. ±30 V
0.3% (Rev. <C0: 1.93%) 10)
0.15% (Rev. <C0: 0.32%) 11)
0.023 %/°C 10)
0.012 %/°C 11)
<0.05 % 11)
01 Ω to 40,000 Ω
<-70 dB
>60 dB
TBD
-200 to 850°C
Table 3: Technical data
6
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
Product ID
Digital outputs
Design
Quantity
Nominal voltage
Switching voltage
Nominal output current
Total nominal current
Connection type
Output circuit
Output protection 12)
Pulse width modulation 13)
Period duration
Pulse duration
Resolution for pulse duration
Diagnostic status
Leakage current when switched off
RDS(on)
Residual voltage
Peak short circuit current
Switching on after overload or short circuit cutoff
X20CP1301
X20CP1382
Standard outputs and mixed channels: FET positive switching
High-speed outputs: Push-Pull
4 standard outputs, 4 high-speed outputs and 4 mixed channels, configurable as inputs or outputs using software
24 VDC
24 VDC -15% / +20%
Standard outputs and mixed channels: 0.5 A
High-speed outputs: 0.2 A
Standard outputs and mixed channels: 4 A
High-speed outputs: 0.8 A
1-wire connections
Standard outputs and mixed channels: Source
High-speed outputs: Sink or source
Thermal cutoff if overcurrent or short circuit occurs (see value "Peak short circuit current")
Internal inverse diode for switching inductive loads (see section "Switching inductive loads")
5 to 65535 µs corresponds to 200 kHz to 15 Hz
0.0 to 100.0%, minimum 2.5 µs
0.1% of the configured frequency
Standard outputs and mixed channels: Output monitoring with 10 ms delay
High-speed outputs: Output monitoring with 10 µs delay
Standard outputs and mixed channels: 5 µA
High-speed outputs: 25 µA
140 mΩ 14)
Standard outputs and mixed channels: <0.1 V at 0.5 A rated current
High-speed outputs: <0.9 V at 0.1 A rated current
Standard outputs and mixed channels: <3 A
High-speed outputs: <20 A
Standard outputs and mixed channels: Approx. 10 ms (depends on the module temperature)
High-speed outputs: TBD
Switching delay
0 -> 1
Standard outputs and mixed channels: <300 µs
High-speed outputs: <3 µs
Standard outputs and mixed channels: <300 µs
High-speed outputs: <3 µs
1 -> 0
Switching frequency
Resistive load 15)
Standard outputs and mixed channels: Max. 500 Hz
High-speed outputs: 50 kHz, max. 200 kHz (see section
"Switching frequency derating for high-speed digital outputs")
See section "Switching inductive loads"
Standard outputs and mixed channels: Typ. 45 VDC
Inductive load
Braking voltage when switching off inductive loads
Operating conditions
Mounting orientation
Horizontal
Vertical
Installation at elevations above sea level
0 to 2000 m
>2000 m
EN 60529 protection
Environmental conditions
Temperature
Operation
Horizontal installation
Yes
Yes
No limitations
Reduction of ambient temperature by 0.5°C per 100 m
IP20
-25 to 60°C
Vertical installation
Derating
Storage
Transport
Relative humidity
Operation
Storage
Transport
Mechanical characteristics
Note
Dimensions
Width
Height
Depth
Weight
X20CP1381
-25 to 60°C (Rev.
<D0: -25 to 55°C)
TBD
TBD
-40 to 85°C
-40 to 85°C
5 to 95%, non-condensing
5 to 95%, non-condensing
5 to 95%, non-condensing
X20 locking plate (right) included in delivery
3 X20 terminal blocks (16-pin) included in delivery
Interface module slot cover included in delivery
164 mm
99 mm
75 mm
300 g
310 g
Table 3: Technical data
1)
2)
3)
4)
The values specified here are maximum values. The exact calculation is available with the other module documentation for download from the B&R website.
When operated in parallel, the nominal power of 2 W is not permitted to be added to the total power.
Up to 2 W bus load.
Can be set in Automation Studio.
Data sheet V 0.38
7
X20CP1301, X20CP1381 and X20CP1382
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
8
See the POWERLINK section of the AS help system under "General information, Hardware - IF/LS".
To reduce power dissipation, B&R recommends bridging unused inputs on the terminals or configuring them as current signals.
Based on the current measured value.
Based on the 20 V measurement range.
Based on the 20 mA measurement range.
Based on the current resistance value.
Based on the entire resistance measurement range.
For high-speed digital outputs, derating must be applied at switching frequencies >50 kHz (see section "Switching frequency derating for high-speed digital
outputs"). Overtemperature protection is not provided.
The high-speed digital outputs can be used for pulse width modulation.
Only for standard outputs and mixed channels.
Standard outputs and mixed channels: At loads ≤1 kΩ.
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
4 LED status indicators on the integrated X1 I/O slot
Figure
LED
E
Color
Red
Status
On
Double flash
On
On
On
R
RF
SE
Green
Red
Yellow
Green/Red
ET
Green
On
Blinking
PL
Green
On
Blinking
A1 - A2
Green
Off
Blinking
On
1-4
C
S
T
DC
Green
Yellow
Yellow
Yellow
Yellow
On
On
On
On
Description
SERVICE mode
BOOT mode (during firmware update)1)
Application running
Reset in progress
SERVICE or BOOT mode
Status/Error LED. The statuses of this LED are described in section 4.1 ""S/E"
LED".
A link to the peer station has been established.
A link to the peer station has been established. Indicates Ethernet activity is
taking place on the bus.
A link to the POWERLINK peer station has been established.
A link to the POWERLINK peer station has been established. Indicates Ethernet
activity is taking place on the bus.
Open line or disconnected sensor
Input signal overflow or underflow
Analog/digital converter running, value OK
Input state of the corresponding digital input
CPU transmitting or receiving data via the CAN bus interface
CPU transmitting or receiving data via the RS232 interface
The terminating resistor integrated in the CPU is switched on.
CPU power supply OK
Table 4: LED status indicators on the integrated X1 I/O slot
1)
A firmware update can take several minutes depending on the configuration.
4.1 "S/E" LED
The Status/Error LED is a green/red dual LED. The LED status can have different meanings depending on the
operating mode.
4.1.1 Ethernet mode
In this mode, the interface is operated as an Ethernet interface.
Green - Status
On
Description
Interface operated as an Ethernet interface
Table 5: Status/Error LED - Ethernet operating mode
4.1.2 POWERLINK
Red - Error
On
Description
The module is in an error mode (failed Ethernet frames, increased number of collisions on the network, etc.).
If an error occurs in the following states, then the green LED blinks over the red LED:
•
•
•
PRE_OPERATIONAL_1
PRE_OPERATIONAL_2
READY_TO_OPERATE
Status
Green
t
Error
Red
t
"S/E" LED
Note:
The LED blinks red several times immediately after startup. This is not an error.
t
Table 6: Status/Error LED as Error LED - POWERLINK operating mode
Data sheet V 0.38
9
X20CP1301, X20CP1381 and X20CP1382
Green - Status
Off
Description
Mode
The module is in NOT_ACTIVE mode or:
•
•
•
•
Switched off
Starting up
Not configured correctly in Automation Studio
Defective
Managing node (MN)
The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter PRE_OPERATIONAL_1 mode.
If POWERLINK communication is detected before the time expires, however, then the MN will not be started.
Green flickering (approx. 10 Hz)
Controlled node (CN)
The bus is monitored for POWERLINK frames. If a corresponding frame is not received within the defined time frame
(timeout), then the module will immediately enter BASIC_ETHERNET mode. If POWERLINK communication is detected
before this time passes, however, then the module will immediately go into PRE_OPERATIONAL_1 mode.
Mode
The module is in BASIC_ETHERNET mode. The interface is being operated as an Ethernet TCP/IP interface.
Managing node (MN)
This state can only be changed by resetting the module.
Single flash (approx. 1 Hz)
Controlled node (CN)
If POWERLINK communication is detected while in this state, the module will transition to the PRE_OPERATIONAL_1
state.
Mode
The module is in PRE_OPERATIONAL_1 mode.
Managing node (MN)
The MN starts "reduced cycle" operation. Cyclic communication is not yet taking place.
Double flash (approx. 1 Hz)
Controlled node (CN)
The module can be configured by the MN in this state. The CN waits until it receives an SoC frame and then transitions
to the PRE_OPERATIONAL_2 state.
An LED lit red in this state indicates a failure of the MN.
Mode
The module is in PRE_OPERATIONAL_2 mode.
Managing node (MN)
The MN begins cyclic communication (cyclic input data is not yet evaluated).
The CNs are configured in this state.
Triple flash (approx. 1 Hz)
Controlled node (CN)
The module can be configured by the MN in this state. A command then changes the state to READY_TO_OPERATE.
An LED lit red in this mode indicates a failure of the MN.
Mode
The module is in the READY_TO_OPERATE state.
Managing node (MN)
Cyclic and asynchronous communication. The received PDO data is ignored.
On
Blinking (approx. 2.5 Hz)
Controlled node (CN)
The module configuration is complete. Normal cyclic and asynchronous communication. The PDO data sent corresponds
to the PDO mapping. Cyclic data is not yet evaluated, however.
An LED lit red in this mode indicates a failure of the MN.
Mode
The module is in PRE_OPERATIONAL_2 mode. PDO mapping is active and cyclic data is being evaluated.
Mode
The module is in STOPPED mode.
Managing node (MN)
This status is not possible for the MN.
Controlled node (CN)
No output data is produced or input data supplied. It is only possible to enter or leave this mode after the MN has given
the appropriate command.
Table 7: Status/Error LED as Status LED - POWERLINK operating mode
10
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
Triple flash
200
200
200
200
200
200
200
200
1000
Double flash
1000
Single flash
200
1000
Blinking
200
200
Flickering
All times in ms
Figure 1: LED status indicators - Blinking patterns
4.2 System failure error codes
Incorrect configuration or defective hardware can cause a system failure error code.
The error code is indicated by the red Error LED using four switch-on phases. The switch-on phases have a duration
of either 150 ms or 600 ms. The error code is output cyclically every 2 seconds.
Error description
RAM error:
The module is defective and must be replaced.
Hardware error:
The module or a system component is defective and must be replaced.
Error code indicated by red status LED
●
●
●
Pause
●
-
●
●
-
Pause
-
●
●
-
Pause
●
●
-
Pause
Table 8: Status/Error ("S/E") LED - System failure error codes
Key:
●
... 150 ms
... 600 ms
Pause ... 2 second delay
5 LED status indicators on the integrated X2 I/O slot
Figure
LED
1 - 14
Color
Green
Status
Description
Input state of the corresponding digital input
Table 9: LED status indicators on the integrated X2 I/O slot
6 LED status indicators on the integrated X3 I/O slot
Figure
LED
DC
E
Color
Yellow
Red
1-4
5-8
9 - 12
Yellow
Yellow
Yellow
Status
On
Off
Double flash
Description
I/O supply OK
Everything OK
No power to module
Output status of the corresponding digital output
Input or output status of the corresponding digital input or output
Output status of the corresponding high-speed digital output
Table 10: LED status indicators on the integrated X3 I/O slot
Data sheet V 0.38
11
X20CP1301, X20CP1381 and X20CP1382
7 Operating and connection elements
X20CP1301
Integrated flash drive
Top-hat rail
tchla
Slot for
interface module
LED status indicators
IF6 - X2X Link
Connections for:
- Supplies
- I/O channels
- IF1 - RS232
X1 X2 X3
Button for
reset and operating mode
IF2 - Ethernet
IF4 - USB
Three integrated I/O slots:
X1, X2 and X3
Figure 2: Operating elements for X20CP1301
X20CP1381 and X20CP1382
Switch for CAN bus
Terminating resistors
Integrated flash drive
Mounting rail
lock
Slot for
Interface module
LED status indicators
IF6 - X2X Link
Connections for:
- Supplies
- I/O channels
- IF1 - RS232
- IF7 - CAN bus
X1 X2 X3
Button for
reset and operating mode
IF3 - POWERLINK
IF2 - Ethernet
IF5 - USB
IF4 - USB
Three integrated I/O slots:
X1, X2 and X3
Figure 3: Operating elements for X20CP1381 and X20CP1382
12
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
8 Flash drive
These CPUs require application memory in order to operate. This application memory is integrated on a flash drive.
9 Reset and operating mode button
Figure 4: Reset and operating mode button
9.1 Reset
The button must be pressed for less than 2 seconds to trigger a reset. This triggers a hardware reset on the CPU,
which means that:
• All application programs are stopped.
• All outputs are set to zero.
The PLC then boots into service mode by default. The boot mode that follows after pressing the reset button can
be defined in Automation Studio.
•
•
•
•
Service mode (default)
Warm restart
Cold restart
Diagnostic mode
9.2 Operating mode
Three operating modes can be configured using different button sequences:
Operating mode
BOOT
Button sequence
Boot mode is enabled by the following button sequence:
•
•
RUN
DIAGNOSE
Press the button for less than two seconds.
As soon as the "R" LED on the X1 I/O slot is lit RED, the
button can be released.
Then press the button within two seconds for longer than
two seconds.
As soon as the "R" LED is no longer lit, the button can be
released.
Press the button for less than two seconds.
As soon as the "R" LED on the X1 I/O slot is lit RED, the button
can be released.
Press the button for more than 2 seconds.
The "R" LED on the X1 I/O slot lights up RED and then goes out.
As soon as the "R" LED is no longer lit, the button can be released.
Description
The default Automation Runtime system is started and the runtime
system can be installed via the online interface (Automation Studio).
User flash memory is deleted only after the download begins.
RUN mode:
The triggering and boot behavior are the same as what happens
when a hardware reset is triggered (see section 9.1 "Reset" on page
13).
Boots the CPU in diagnostic mode. Program sections in User RAM
and User FlashPROM are not initialized. After diagnostic mode, the
CPU always boots with a cold restart.
Table 11: Operating mode description
Data sheet V 0.38
13
X20CP1301, X20CP1381 and X20CP1382
10 CPU supply
A power supply is integrated in these compact CPUs. It has a feed for the CPU, X2X Link and the internal I/O
supply. The supply for the CPU and X2X Link is electrically isolated.
The connections are located on the X3 I/O slot.
10.1 Compact CPU supply concept
To ensure proper operation of compact CPUs, the following items must be taken into consideration:
The supply concept
CPU and I/O GND
Plug-in X20 I/O modules
Integrated X1 I/O slot
Integrated X2 I/O slot
Integrated X3 I/O slot
Description
The GND contact is provided five times on the terminal blocks of the integrated I/O slots. All GND contacts are connected to one
another. The GND contacts of the CPU and I/O supply therefore use the same voltage.
Supply of X20 I/O modules that can be connected to the compact CPU:
•
•
X2X Link: Supplied by the CPU supply
I/O channels: Supplied by the I/O supply
•
•
All 12 digital signals are supplied by the I/O supply.
The status messages for each channel also work without an I/O supply. This guarantees that status messages will continue
to be transferred during an E-stop.
The status of the I/O supply is indicated by a separate status message.
All digital and analog signals as well as the RS232 and CAN bus interface are supplied by the CPU supply. Their operation is
therefore guaranteed even if there is no I/O supply.
• All digital signals are supplied by the CPU supply. Their operation is therefore guaranteed even if there is no I/O supply.
• The encoder supply is supplied by the I/O supply. If the encoder is not to be connected to the E-stop chain, then it must
be connected to an external power supply or it will be supplied by the CPU supply.
•
Caution!
Channels 5 to 8 are designed as mixed channels. If one of these channels is being used, it is absolutely essential
to ensure that there is no external voltage present on the I/O channel when the I/O supply is cut off. Otherwise,
power will be regenerated back to the plus terminal of the I/O supply via the I/O channel. This will result in defective
components.
The following solutions are available for preventing power regeneration from occurring:
•
•
The I/O supply of the CPU is not permitted to be switched off, which allows the reference potential to
be maintained.
If the I/O supply is switched off anyway (e.g. as part of the E-stop chain), then the sensor/actuator supplies must also be switched off. This prevents potential power regeneration and protects components
from being destroyed.
Table 12: Compact CPU supply concept
14
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
10.2 Pinout
DC
1
3
5
7
9
11
E
2
4
6
8
10
12
+24 V CP/X2X L.
+24 V I/O
GND
GND
Figure 5: Integrated power supply - Pinout
10.3 Connection example
X3
CPU / X2X Link
Power supply
+
_
+24 VDC
GND
10 A slow-blow
+
_
I/OPower supply
+24 VDC
GND
Figure 6: CPU supply - Connection example
Data sheet V 0.38
15
X20CP1301, X20CP1381 and X20CP1382
11 RS232 interface (IF1)
The non-electrically isolated RS232 interface is primarily intended to serve as an online interface for communication
with the programming device. It is located on the X1 I/O slot.
E
RF
F
ET
A1
1
3
C
T
R
SE
PL
A2
2
4
RS232 TXD
RS232 RXD
GND
Figure 7: RS232 interface (IF1) on the X1 I/O slot - Pinout
12 Ethernet interface (IF2)
The IF2 interface is designed for 10BASE-T / 100BASE-TX transmission.
The INA2000 station number can be set using the Automation Studio software.
Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
at www.br-automation.com.
Information:
The Ethernet interface (IF2) is not suited for POWERLINK (see section 13 "POWERLINK interface (IF3)"
on page 17).
Pinout
Interface
Pinout
1
Shielded RJ45
Pin
1
2
3
4
5
6
7
8
Ethernet
TXD
TXD\
RXD
Termination
Termination
RXD\
Termination
Termination
Transmit data
Transmit data\
Receive data
Receive data\
Table 13: Pinout
16
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
13 POWERLINK interface (IF3)
Compact CPUs X20CP1381 and X20CP1382 are equipped with a POWERLINK interface.
POWERLINK
Node numbers between 0x01 and 0xF0 are permitted. The node number can be configured using software.
Switch position
0x00
0x01 - 0xEF
0xF0
0xF1 - 0xFF
Description
Reserved, switch position not permitted
Node number of the POWERLINK node. Operation as a controlled node.
Operation as a managing node.
Reserved, switch position not permitted
Table 14: POWERLINK node number
Ethernet mode
In this mode, the interface is operated as an Ethernet interface. The INA2000 station number can be set using
the Automation Studio software.
Pinout
Information about cabling X20 modules with an Ethernet interface can be found in the module's download section
at www.br-automation.com.
Pin
1
2
3
4
5
6
7
8
Assignment
RxD
RxD\
TxD
Termination
Termination
TxD\
Termination
Termination
Receive data
Receive data\
Transmit data
Transmit data\
Table 15: POWERLINK interface (IF3) - Pinout
Data sheet V 0.38
17
X20CP1301, X20CP1381 and X20CP1382
14 USB interfaces (IF4 and IF5)
IF4 - USB
IF5 - USB
Figure 8: USB interfaces (IF4 and IF5)
IF4 and IF5 are non-electrically isolated USB interfaces. The connection is made using a USB 2.0 interface. Only
IF4 is available on the entry level CPU.
The USB interfaces can only be used for devices approved by B&R (e.g. floppy disk drive, DiskOnKey or dongle).
Information:
• USB interfaces cannot be used for online communication with a programming device.
• Only devices isolated from GND can be connected to the USB interfaces.
• The USB interfaces can handle up to the following current:
° IF4: Max. 0.5 A
° IF5: Max. 0.1 A
15 CAN bus interface (IF7)
With the exception of the entry level CPU, all compact CPUs are equipped with a non-electrically isolated CAN
bus interface. It is located on the X1 I/O slot.
15.1 Pinout
E
RF
F
ET
A1
1
3
C
T
R
SE
PL
A2
2
4
S
DC
CAN high
CAN low
GND
Figure 9: CAN bus interface (IF7) on the X1 I/O slot - Pinout
18
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
15.2 Terminating resistors
Integrated I/O slot
Terminating resistor switch
X1
On
Off
X2
X3
Figure 10: Switch positions for the CAN bus terminating resistor
A terminating resistor is already installed on the X1 I/O slot. It can be turned on and off with a switch on top of the
housing. An active terminating resistor is indicated by the "T" LED.
16 Slot for interface modules
These CPUs are equipped with one slot for interface modules.
Various bus and network systems can easily be integrated into the X20 system by selecting the corresponding
interface module.
17 Overtemperature cutoff
To prevent damage, a shutdown/reset is triggered on the CPU when the processor reaches 95°C.
The following errors are entered in the logbook:
Error number
9204
9210
Error description
WARNING: System halted because of temperature check
WARNING: Boot by watchdog or manual reset
Table 16: Logbook entries after overtemperature cutoff
18 Data and real-time clock buffering
Compact CPUs are not designed for use with batteries. This makes them completely maintenance-free. The following features make operation without a backup battery possible.
Data and real-time clock buffering
Remanent variables
Type of buffering
FRAM
Real-time clock
Gold foil capacitor
Data sheet V 0.38
Note
This FRAM stores its contents ferroelectrically. Unlike normal SRAM, this does
not require a battery.
The real-time clock is buffered for approx. 1000 hours by a gold foil capacitor. The
gold foil capacitor is completely charged after 3 continuous hours of operation.
19
X20CP1301, X20CP1381 and X20CP1382
19 Programming the system flash memory
General information
In order for the application project to be executed on the CPU, the Automation Runtime operating system, system
components and application project must be installed on the flash drive.
Installation over an online connection
These CPUs come standard with an Automation Runtime system (with limited functionality) already installed. This
runtime system is started in boot mode (see section 9 "Reset and operating mode button" on page 13 or an invalid
flash drive). Some of its tasks include initializing the Ethernet and integrated serial RS232 interfaces so that it is
possible to download a runtime system.
1. Switch on the supply voltage for the CPU. The CPU starts with the default Automation Runtime in boot mode
(see section 9 "Reset and operating mode button" on page 13 or an invalid flash drive).
2. Establish a physical online connection between the programming device (PC or industrial PC) and the CPU
(e.g. over an Ethernet network or the RS232 interface).
3. Before you can establish an online connection via Ethernet, the CPU must be assigned an IP address. Search
for available B&R target system in the local network by selecting Online / Settings from the Automation
Studio menu and then clicking the Browse targets button. The CPU should appear in the list. If the CPU has
not already received an IP address from a DHCP server, right-click on it and select Set IP parameters from
the shortcut menu. All necessary network configurations can be made on a temporary basis in this dialog box
(should be identical to the settings defined in the project).
4. Configure an online connection in Automation Studio. For details about the configuration: See AS help system
under "Automation Software / Communication / Online communication"
5. Start the download procedure by selecting Services from the Project menu. Then select Transfer Automation Runtime from the pop-up menu. Now follow the instructions provided by Automation Studio.
20
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
20 I/O channels
Compact CPUs are equipped with three integrated I/O slots. These devices have 30 digital inputs/outputs and
two analog inputs. One analog input can also be used for PT1000 resistance temperature measurement.
Information about the functions of the high-speed digital inputs and outputs can be found in the section 24 "Functions of the high-speed digital inputs/outputs" on page 26.
Overview of available I/O channels:
Integrated I/O
Digital inputs
High-speed digital inputs
Digital outputs
Fast digital outputs
Digital inputs/outputs
Analog inputs
Temperature inputs
Quantity
14
4
4
4
4
2
1
I/O slot
X1: DI 1 to DI 4
X2: DI 1 to DI 10
X2: DI 11 to DI 14
X3: DO 1 to DO 4
X3: DO 9 to DO 12
X3: DI 5 / DO 5 to DI 8 / DO 8
X1: AI 1 to AI 2
X1: AI 1 (Sensor + and Sense -)
Description
24 VDC, sink, ≥0.5 ms, configurable software filter
24 VDC, sink, 2 μs, configurable software filter
24 VDC, 0.5 A, source
24 VDC, 0.2 A, 2 μs
24 VDC, 0.5 A, configurable software filter
±10 V / 0 to 20 mA or 4 to 20 mA, 12-bit, 1 ms
PT1000 resistance temperature measurement
Measurement takes place using the AI 1 analog input.
Table 17: I/O channels on compact CPUs
Data sheet V 0.38
21
X20CP1301, X20CP1381 and X20CP1382
21 Pinout
X1 I/O slot - Pinout
E
RF
F
ET
A1
1
3
C
T
R
SE
PL
A2
2
4
S
DC
AI + 1 I
AI + 2 I
AI + 1 U / Sensor +
AI + 2 U
AI - 1 U/I / Sense -
AI - 2 U/I
DI 1
DI 2
DI 3
DI 4
CAN high
RS232 TXD
CAN low
RS232 RXD
GND
GND
Figure 11: Pinout of the integrated X1 I/O slot
X2 I/O slot - Pinout
1
3
5
7
9
11
13
2
4
6
8
10
12
14
DI 1
DI 2
DI 3
DI 4
DI 5
DI 6
DI 7
DI 8
DI 9
DI 10
DI 11 (high-speed)
DI 12 (high-speed)
DI 13 (high-speed)
DI 14 (high-speed)
GND
+24 V encoder
Figure 12: Pinout of the integrated X2 I/O slot
X3 I/O slot - Pinout
To ensure proper operation of the digital mixed channels (DI 5 / DO 5 to DI 8 / DO 8), it is important to observe the
notes in section 10.1 "Compact CPU supply concept" on page 14.
DC
1
3
5
7
9
11
DO 1
E
2
4
6
8
10
12
DO 2
DO 3
DO 4
DI 5 / DO 5
DI 6 / DO 6
DI 7 / DO 7
DI 8 / DO 8
DO 9 (high-speed)
DO 10 (high-speed)
DO 11 (high-speed)
DO 12 (high-speed)
+24 V CPU/X2X L.
+24 V I/O
GND
GND
Figure 13: Pinout of the integrated X3 I/O slot
22
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
22 Connection examples
22.1 X1 I/O slot - Connection examples
Voltage/Current measurement, digital inputs and CAN bus
Voltage
measurement
X1
Current
measurement
+
+
Sensor 1
Sensor 2
Sensor 3
Sensor 4
CAN high
CAN low
GND
+24 VDC
GND
+24 VDC
+24 VDC
Figure 14: Connection example 1 for integrated X1 I/O slot
PT1000 resistance temperature measurement, voltage measurement, digital inputs and RS232
PT1000
Resistance
temperature measurement
X1
Voltage
measurement
+
+
_
Sensor 1
Sensor 2
Sensor 3
Sensor 4
RS232 TXD
RS232 RXD
GND
+24 VDC
GND
+24 VDC
+24 VDC
Figure 15: Connection example 2 for integrated X1 I/O slot
Data sheet V 0.38
23
X20CP1301, X20CP1381 and X20CP1382
22.2 X2 I/O slot - Connection example
Digital inputs and ABR incremental encoder
X2
Sensor 1
Sensor 2
Sensor 3
Sensor 4
Sensor 5
Sensor 6
Sensor 7
Sensor 8
Sensor 9
Sensor 10
+24 VDC
GND
Counter
A
B
R
+24 VDC
GND
+24 VDC
+24 VDC
Figure 16: Connection example for integrated X2 I/O slot
22.3 X3 I/O slot - Connection example
Digital inputs/outputs, direction/frequency (DF), PWM, CPU / X2X Link supply and I/O supply
X3
CPU / X2X Link
Power supply
Actuator 1
Actuator 2
Actuator 3
Actuator 4
Actuator 5
Sensor 6
Actuator 7
Sensor 8
DF
DF
PWM
PWM
+
_
+24 VDC
GND
10 A slow-blow
+
_
I/OPower supply
+24 VDC
GND
Figure 17: Connection example for integrated X3 I/O slot
24
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
23 X20 shielding bracket
The X20 shielding bracket (model number X20AC0FE1.0010) is installed below the X20 system. The shield is
pressed against the shielding bracket using ground terminals from another manufacturer (e.g. PHOENIX or WAGO)
or a cable tie.
Attaching the shield with a ground terminal
Attaching the shield with a cable tie
①
①
Cable duct
Cable duct
Table 18: Cable shield via X20 shielding bracket
To reduce the EMC emissions most effectively, the cable shield must reach as high as possible after the cable
tie (see ① in the diagram above).
Dimensions
6
7.5
10
5.5
33
Dimensions [mm]
40
48
48
Figure 18: X20 shielding bracket - Dimensions
Content of delivery
• 10 X20 shielding brackets
• Installation template
Data sheet V 0.38
25
X20CP1301, X20CP1381 and X20CP1382
24 Functions of the high-speed digital inputs/outputs
24.1 Functions of the high-speed digital inputs
Possible functions
The high-speed digital inputs DI 11 to DI 14 can be configured for the following functions:
Channel
DI 11
Counter function
Event counter 1
DI 12
DI 13
Event counter 2
DI 14
Edge detection
• Period measurement
• Gate measurement
• Differential time measurement
A
A
D - Direction
B
B
F - Frequency
•
•
•
A
R
R
B
E - Reference enable
E - Reference enable
•
•
Edge counters
Edge times
Period measurement
Gate measurement
Differential time measurement
•
•
Edge counters
Edge times
•
•
•
Period measurement
Gate measurement
Differential time measurement
•
•
Edge counters
Edge times
•
•
•
Period measurement
Gate measurement
Differential time measurement
•
•
Edge counters
Edge times
Table 19: Possible functions of the high-speed digital inputs DI 11 to DI 14
Please note
The following points must be taken into account to correctly configure the high-speed digital inputs:
• The counter functions are mutually exclusive. Only one type of counter function can be selected at a time.
It is not possible to select two event counters (DI 11 and DI 13) at the same time together with an AB or
DF counter (each on DI 13 and DI 14)!
• It is possible to select a counter function and edge detection at the same time.
• A position or counter latch is possible when configuring the high-speed inputs as a 2x event counter, ABR
incremental encoder or DF function.
Examples of possible configurations
Channel
DI 11
DI 12
DI 13
DI 14
Channel
DI 11
DI 12
DI 13
DI 14
26
Configuration 1
Event counter 1
Configuration 3
A
Configuration 4
D
B
F
Event counter 2
A
B
• Period measurement
• Gate measurement
• Differential time measurement
R
E - Reference enable
R
E - Reference enable
Configuration 5
Event counter 1
Configuration 7
Configuration 8
D - Direction
• Period measurement
• Gate measurement
• Differential time measurement
•
•
•
•
•
Period measurement
Gate measurement
Differential time measurement
Edge counters
Edge times
Event counter 2
•
•
•
Period measurement
Gate measurement
Differential time measurement
Configuration 2
• Edge counters
• Edge times
•
•
Edge counters
Edge times
Configuration 6
A
B
•
•
•
F - Frequency
Period measurement
Gate measurement
Differential time measurement
•
•
•
Period measurement
Gate measurement
Differential time measurement
•
•
Edge counters
Edge times
•
•
Edge counters
Edge times
•
•
Edge counters
Edge times
•
•
Edge counters
Edge times
•
•
•
Period measurement
Gate measurement
Differential time measurement
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
24.2 Functions of the high-speed digital outputs
Possible functions
The high-speed digital outputs DO 9 to DO 12 can be configured for the following functions:
Channel
DO 9
DO 10
DO 11
DO 12
Function
PWM - Pulse width modulation
PWM - Pulse width modulation
PWM - Pulse width modulation
PWM - Pulse width modulation
D - Direction
F - Frequency
D - Direction
F - Frequency
Table 20: Possible functions of the high-speed digital inputs DO 9 to DO 12
Examples of possible configurations
Channel
DO 9
DO 10
DO 11
DO 12
Configuration 1
PWM - Pulse width modulation
PWM - Pulse width modulation
D - Direction
F - Frequency
Data sheet V 0.38
Configuration 2
D - Direction
F - Frequency
PWM - Pulse width modulation
PWM - Pulse width modulation
Configuration 3
PWM - Pulse width modulation
PWM - Pulse width modulation
PWM - Pulse width modulation
PWM - Pulse width modulation
Configuration 4
D - Direction
F - Frequency
D - Direction
F - Frequency
27
X20CP1301, X20CP1381 and X20CP1382
25 Input/Output circuit diagram
25.1 Input circuit diagram of the analog inputs and temperature input on X1
PT1000 switching (channel 1 only)
Current/Voltage switching
PTC
AI + x I
AI + x U
A/D
Converter
Shunt
Input value
I/O status
AI - x U/I
Ax LED (green)
Figure 19: Input circuit diagram of the analog inputs and temperature input on the integrated X1 I/O slot
25.2 Input circuit diagram of the digital inputs
25.2.1 Input circuit diagram of the digital inputs on X1 and the high-speed digital inputs on X2
DI x
I/O status
LED (green)
Input status
Figure 20: Input circuit diagram of the digital inputs on the integrated
X1 I/O slot and the high-speed digital inputs on the integrated X2 I/O slot
25.2.2 Input circuit diagram of the digital inputs on X2
DI x
I/O status
LED (green)
Input status
Figure 21: Input circuit diagram of the digital inputs on the integrated X2 I/O slot
28
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
25.3 Output circuit diagram of the digital outputs
25.3.1 Output circuit diagram of the digital outputs on X3
High-side
Output status
Logic
DO x
Output monitoring
I/O status
LED (orange)
Figure 22: Output circuit diagram of the digital outputs on the integrated X3 I/O slot
25.3.2 Output circuit diagram of the high-speed digital outputs on X3
Push-Pull
Output status
PTC
Logic
DO x
Output monitoring
I/O status
LED (orange)
Figure 23: Output circuit diagram of the fast digital outputs on the integrated X3 I/O slot
25.4 Input/Output circuit diagram of the digital mixed channels on X3
To ensure proper operation of the digital mixed channels (DI 5 / DO 5 to DI 8 / DO 8), it is important to observe the
notes in section 10.1 "Compact CPU supply concept" on page 14.
High-side
Output status
Output monitoring or
Input status
Logic
DI x / DO x
I/O status
LED (orange)
Figure 24: Input/Output circuit diagram of the digital mixed channels on the integrated X3 I/O slot
25.5 Circuit diagram for the encoder supply on X2
Output status
+24 V encoder
Figure 25: Circuit diagram of the encoder supply on the integrated X2 I/O slot
Data sheet V 0.38
29
X20CP1301, X20CP1381 and X20CP1382
25.6 Circuit diagram of the CPU, X2X Link and I/O supply on X3
Input status
DC OK
+24 V I/O
+24 V CPU/X2X L.
DC OK status
LED DC (orange)
I/O error status
PTC
LED E (red)
GND
GND
PTC
Overvoltage and
reverse polarity protection
Figure 26: Circuit diagram of the CPU, X2X Link and I/O supply on the integrated X3 I/O slot
26 Switching frequency derating for high-speed digital outputs
The high-speed digital outputs can be switched with a frequency of max. 200 kHz. Derating may be necessary
depending on the mounting orientation and operating temperature.
Switching frequency derating for horizontal mounting orientations
Switching frequency [kHz]
200
150
100
50
0
-25 -20
-10
0
10
20
30
40
50
60
Operating temperature [°C]
Figure 27: Switching frequency derating for high-speed digital outputs with horizontal mounting orientations
30
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27 Register description
27.1 Register overview of the I/O data points on the integrated X1 I/O slot
Register
Name
Data type
Read
Cyclic
X1 - Configuration
2048
X1CfO_DI_Filter
2128
X1CfO_AI_Mode
2112
X1CfO_AI1_Filter
2116
X1CfO_AI1_LowerLim
2118
X1CfO_AI1_UpperLim
2120
X1CfO_AI2_Filter
2124
X1CfO_AI2_LowerLim
2126
X1CfO_AI2_UpperLim
X1 - Communication
0
Digital inputs
DigitalInput01
DigitalInput02
DigitalInput03
DigitalInput04
64
AnalogInput01
66
80
Write
Acyclic
USINT
USINT
USINT
INT
INT
USINT
INT
INT
Acyclic
●
●
●
●
●
●
●
●
USINT
Bit 0
Bit 1
Bit 2
Bit 3
INT
UINT
INT
USINT
AnalogInput02
StatusInput01
Cyclic
●
●
●
●
●
27.1.1 Digital inputs
Unfiltered
The input status is recorded in a 100 µs cycle.
Filtered
The filtered status is transferred in a 100 µs cycle.
Filtering takes place asynchronously in an interval of 100 μs.
27.1.1.1 Digital input filter
Name:
X1CfO_DI_Filter
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs.
Data type
USINT
Value
0
1
...
250
Filter
No SW filter
0.1 ms
...
25 ms - Higher values are limited to this value
27.1.1.2 Input state of digital inputs 1 to 4
Name:
DigitalInput01 to DigitalInput04
This register is used to indicate the input state of digital inputs 1 to 4.
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0
...
3
Name
DigitalInput01
DigitalInput04
Data sheet V 0.38
Value
0 or 1
...
0 or 1
Information
Input status of digital input 1
Input status of digital input 4
31
X20CP1301, X20CP1381 and X20CP1382
27.1.2 Analog inputs
Analog input values are recorded in a fixed interval. The time required for conversion/updating depends on the
number of analog inputs and on the input signal:
Input signal
1 current/voltage input
1 temperature/resistance input
2 current/voltage inputs
1 current/voltage input and 1 temperature/resistance input
Time required for conversion/updating
100 µs
200 µs
200 µs
400 µs
27.1.2.1 Analog input values
Name:
AnalogInput01
The analog input value is mapped to this register depending on the configured operating mode.
Data type
INT
Value
-32,768 to 32,767
0 to 32,767
-8,192 to 32,767
-2,000 to 8,500
0 to 40,000
UINT
Input signal
Voltage signal -10 to 10 VDC
Current signal 0 to 20 mA (with 0 to 20 mA configuration)
Current signal 0 to 20 mA (with 4 to 20 mA configuration)
PT1000 signal -200.0 to 850.0°C
Resistance signal 0 to 4000.0 Ω
Name:
AnalogInput02
The analog input value is mapped to this register depending on the configured operating mode.
Data type
INT
Value
-32,768 to 32,767
0 to 32,767
-8,192 to 32,767
Input signal
Voltage signal -10 to 10 VDC
Current signal 0 to 20 mA (with 0 to 20 mA configuration)
Current signal 0 to 20 mA (with 4 to 20 mA configuration)
27.1.2.2 Input status
Name:
StatusInput01
This register holds the status of the analog inputs. A change in the monitoring status generates an error message.
The following states are monitored depending on the settings:
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0-1
Description
Channel 1
2-3
Channel 2
4-7
Reserved
Value
00
01
10
11
00
01
10
11
0
Information
No error
Lower limit value exceeded
Upper limit value exceeded
Open line
No error
Lower limit value exceeded
Upper limit value exceeded
Open line
Limiting the analog value
In addition to the status information, the analog value is set to the limit values listed below by default when an error
occurs (see 27.1.2.5 "Limit values"). The analog value is limited to the new values if the limit values were changed.
32
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.1.2.3 Input filter
The analog inputs are equipped with a configurable input filter.
27.1.2.3.1 Input ramp limitation
Input ramp limitation can only take place when a filter is used; the input ramp is limited before filtering takes place.
The amount the input value changes is checked to make sure that specified limits are not exceeded. If the values
are exceeded, the adjusted input value is equal to the old value ± the limit value.
Configurable limit values:
Value
0
1
2
3
4
5
6
7
Limit value
The input value is used without limitation.
0x3FFF = 16383
0x1FFF = 8191
0x0FFF = 4095
0x07FF = 2047
0x03FF = 1023
0x01FF = 511
0x00FF = 255
Input ramp limitation is well suited for suppressing disturbances (spikes). The following examples show the function
of the input ramp limitation based on an input jump and a disturbance.
Example 1
The input value jumps from 8,000 to 17,000. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering
17000
8000
0
1
2
3
4
5
6
7
8
t [ms]
Input jump
Figure 28: Adjusted input value for input jump
Data sheet V 0.38
33
X20CP1301, X20CP1381 and X20CP1382
Example 2
A disturbance interferes with the input value. The diagram shows the adjusted input value with the following settings:
Input ramp limitation = 4 = 0x07FF = 2047
Filter level = 2
Input value
Internally adjusted input value before filtering
16000
Disturbance (spike)
8000
0
1
2
3
4
5
6
7
8
t [ms]
Figure 29: Adjusted input value for disturbance
27.1.2.3.2 Filter level
A filter can be defined to prevent large input jumps. This filter is used to bring the input value closer to the actual
analog value over a period of several bus cycles.
Filtering takes place after input ramp limitation.
Formula for calculating the input value:
Value New =
Value Old -
Value Old
Filter level
+
Input value
Filter level
Adjustable filter levels:
Value
0
1
2
3
4
5
6
7
34
Filter level
Filter switched off
Filter level 2
Filter level 4
Filter level 8
Filter level 16
Filter level 32
Filter level 64
Filter level 128
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
The following examples show how filtering works in the event of an input jump or disturbance.
Example 1
The input value jumps from 8,000 to 16,000. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4
16000
8000
0
1
2
3
4
5
6
7
8
t [ms]
Input jump
Figure 30: Calculated value during input jump
Example 2
A disturbance interferes with the input value. The diagram shows the calculated value with the following settings:
Input ramp limitation = 0
Filter level = 2 or 4
Input value
Calculated value: Filter level 2
Calculated value: Filter level 4
16000
Disturbance (spike)
8000
0
1
2
3
4
5
6
7
8
t [ms]
Figure 31: Calculated value during disturbance
Data sheet V 0.38
35
X20CP1301, X20CP1381 and X20CP1382
27.1.2.3.3 Configuring the input filter
Name:
X1CfO_AI1_Filter
X1CfO_AI2_Filter
This register is used to define the filter level and input ramp limitation of the input filter.
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0-2
Description
Defines the filter level
3
4-6
Reserved
Defines the input ramp limitation
7
Reserved
Value
000
001
010
011
100
101
110
111
0
000
001
010
011
100
101
110
111
0
Information
Filter switched off
Filter level 2
Filter level 4
Filter level 8
Filter level 16
Filter level 32
Filter level 64
Filter level 128
The input value is used without limitation
Limit value = 0x3FFF (16383)
Limit value = 0x1FFF (8191)
Limit value = 0x0FFF (4095)
Limit value = 0x07FF (2047)
Limit value = 0x03FF (1023)
Limit value = 0x01FF (511)
Limit value = 0x00FF (255)
27.1.2.4 Channel type
Name:
X1CfO_AI_Mode
This register can be used to define the type and range of signal measurement.
Each channel is capable of handling current, voltage or resistance signals. This differentiation is made using multiple connection terminal points and an integrated switch. The switch is automatically activated depending on the
specified configuration. The following input signals can be set:
Input signal
±10 V voltage signal (default)
0 to 20 mA current signal
4 to 20 mA current signal
PT1000 measurement
Resistance measurement
Data type
USINT
On channel
1 and 2
1 and 2
1 and 2
1
1
Value
See bit structure.
Bit structure:
36
Bit
0-2
Description
Analog input - Channel 1
3
4-5
Reserved
Analog input - Channel 2
6-7
Reserved
Value
000
001
010
011
100
101
0
00
01
10
11
0
Information
Channel disabled
±10 V voltage signal
0 to 20 mA current signal
4 to 20 mA current signal
PT1000 measurement
Resistance measurement
Channel disabled
±10 V voltage signal
0 to 20 mA current signal
4 to 20 mA current signal
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.1.2.5 Limit values
The input signal is monitored at the upper and lower limit values. By default the following limits are set for each
mode:
Limit value (default)
Upper maximum limit value
Lower minimum limit value
Voltage signal ±10 V
10 V
32767 (0x7FFF)
-10 V
-32767 (0x8001)
Current signal 0 to 20 mA
20 mA
32767 (0x7FFF)
0 mA
01)
Current signal 4 to 20 mA
20 mA
32767 (0x7FFF)
4 mA
02)
Table 21: Limit values for voltage and current signals
1)
2)
The analog value is limited down to 0.
Due to the default limit value, the analog value is limited to a minimum of 0 at currents <4 mA.
Limit value (default)
Upper maximum limit value
Lower minimum limit value
Temperature measurement
8000°C
8000 (0x1F40)
-2000°C
-2000 (0xF830)
Resistance measurement
4000.0 Ω
32767 (0x7FFF)
0Ω
0
Table 22: Limit values for temperature and resistance measurement
Other limit values can be defined if necessary. These are activated automatically by writing the limit value register
(see 27.1.2.5.1 "Lower limit value" and 27.1.2.5.2 "Upper limit value"). From this point on, the analog values will
be monitored and limited according to the new limits. The results of monitoring are displayed in the status register
(see 27.1.2.2 "Input status").
Application example of setting limit values
A negative limit value must be configured in order to measure values <4 mA with a current signal of 4 to 20 mA:
0 mA corresponds to a value of -8192 (0xE000).
27.1.2.5.1 Lower limit value
Name:
X1CfO_AI1_LowerLim
X1CfO_AI2_LowerLim
These registers can be used to configure the lower limit for analog values. If the analog value goes below the limit
value, it is frozen at this value and the corresponding error status bit is set (see 27.1.2.2 "Input status").
Data type
INT
UINT
Value
-32,768 to 32,767
0 to 65,535
Information:
When configured as 4 to 20 mA, this value can be set to -8192 (corresponds to 0 mA) in order to display
values <4 mA.
27.1.2.5.2 Upper limit value
Name:
X1CfO_AI1_UpperLim
X1CfO_AI2_UpperLim
These registers can be used to configure the upper limit for analog values. If the analog value goes above the limit
value, it is frozen at this value and the corresponding error status bit is set (see 27.1.2.2 "Input status").
Data type
INT
UINT
Data sheet V 0.38
Value
0 to 32,767
0 to 65,535
37
X20CP1301, X20CP1381 and X20CP1382
27.2 Register overview of the I/O data points on the integrated X2 I/O slot
Register
Name
Data type
Read
Cyclic
X2 - Configuration
7168
X2CfO_EdgeDetectUnit01Mode
7169
X2CfO_EdgeDetectUnit01Master
7170
X2CfO_EdgeDetectUnit01Slave
7184
X2CfO_EdgeDetectUnit02Mode
7185
X2CfO_EdgeDetectUnit02Master
7186
X2CfO_EdgeDetectUnit02Slave
6144
X2CfO_DI_Filter
6528
X2CfO_CounterMode
6400
X2CfO_Latch01Mode
6401
X2CfO_Latch01Comparator
6416
X2CfO_Latch02Mode
6417
X2CfO_Latch02Comparator
X2 - Communication
4096
Digital inputs
DigitalInput01
DigitalInput02
DigitalInput03
DigitalInput04
DigitalInput05
DigitalInput06
DigitalInput07
DigitalInput08
4097
Digital inputs
DigitalInput09
DigitalInput10
DigitalInput11
DigitalInput12
DigitalInput13
DigitalInput14
5120
EdgeDetect01Mastertime
5124
EdgeDetect01Difference
5128
EdgeDetect01Mastercount
5136
EdgeDetect02Mastertime
5140
EdgeDetect02Difference
5144
EdgeDetect02Mastercount
4384
Counter 1
Counter01Reset
Latch01Enable
4352
Counter01Value
4356
Counter01Latch
4360
Counter01TimeChanged
4364
Counter01TimeValid
4368
Latch01Count
4448
Counter 2
Counter02Reset
Latch02Enable
4416
Counter02Value
4420
Counter02Latch
4424
Counter02TimeChanged
4428
Counter02TimeValid
4432
Latch02Count
38
Write
Acyclic
Cyclic
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
USINT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
DINT
DINT
INT
DINT
DINT
INT
USINT
Bit 0
Bit 1
DINT
DINT
DINT
DINT
SINT
USINT
Bit 0
Bit 1
DINT
DINT
DINT
DINT
SINT
Acyclic
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.2.1 Digital inputs
Unfiltered
The input status is recorded in a 100 µs cycle.
Filtered
The filtered status is transferred in a 100 µs cycle.
Filtering takes place asynchronously in an interval of 100 μs.
27.2.1.1 Digital input filter
Name:
X2CfO_DI_Filter
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs.
Data type
USINT
Value
0
1
...
250
Filter
No SW filter
0.1 ms
...
25 ms - Higher values are limited to this value
27.2.1.2 Input state of digital inputs 1 to 14
Name:
DigitalInput01 to DigitalInput14
These registers are used to indicate the input state of digital inputs 1 to 14.
Data type
USINT
Value
See bit structure.
Bit structure of register 4096:
Bit
0
...
7
Name
DigitalInput01
DigitalInput08
Value
0 or 1
...
0 or 1
Information
Input status of digital input 1
Value
0 or 1
...
0 or 1
Information
Input status of digital input 9
Input status of digital input 8
Bit structure of register 4097:
Bit
0
...
5
Name
DigitalInput09
DigitalInput14
Data sheet V 0.38
Input status of digital input 14
39
X20CP1301, X20CP1381 and X20CP1382
27.2.2 Edge detection
Digital inputs 11 to 14 can be used for fast edge detection. This runs parallel to all other functions such as counters,
etc. This function does not use the digital input filter.
The edge detection function measures edges with µs precision. 2 units are available. A master and a slave edge
can be configured for each unit. At each master edge, the timestamp of the master edge and the differential time
to the previous slave edge (if present) are logged. A "Master count" can always be utilized to determine how many
edges have been detected since the last task class cycle. The timestamp is based on the system time of the CPU.
The combination of rising/falling edges of each channel can be used to configure the following functions for each
unit:
Function
Edge time
Period duration
Gate time
Time offset
Description
Measure an edge time
Measure the master and differential time
Measure the master and differential time
Measure the master and differential time of edges on different channels
27.2.2.1 Edge detection unit - Mode settings
The edge detection unit needs to be configured according to the desired function.
Function
Basic timestamp, master edge mode
Timestamp and/or differential time, master and
slave edge mode
Description
The current system time is saved as the master time at the time of the edge.
The slave edge starts the measurement and the system time is saved temporarily. When the master edge occurs,
the current system time is saved as the master time and the difference between the master and slave edges
is calculated.
Name:
X2CfO_EdgeDetectUnit01Mode
X2CfO_EdgeDetectUnit02Mode
These registers are used to configure the mode of the basic function for either just the master edge or both master
and slave edges.
Data type
USINT
Value
0x00
0x80
0xC0
Information
Edge detection disabled on Unit0x: Time measurement not possible
Edge detection enabled on Unit0x:
Reaction only possible for master edge, no differential measurement possible
Edge detection enabled on Unit0x:
Reaction possible for configured master and slave edges
27.2.2.2 Edge detection unit - Selection of master edge
Name:
X2CfO_EdgeDetectUnit01Master
X2CfO_EdgeDetectUnit02Master
These registers are used to select the source of the master edge for the respective unit. Either the rising or falling
edge of one of the 4 fast digital input channels can be selected. Only one edge can be selected for each unit.
Data type
USINT
40
Value
0
2
4
6
1
3
5
7
Information
Digital input channel 11: Rising edge
Digital input channel 12: Rising edge
Digital input channel 13: Rising edge
Digital input channel 14: Rising edge
Digital input channel 11: Falling edge
Digital input channel 12: Falling edge
Digital input channel 13: Falling edge
Digital input channel 14: Falling edge
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.2.2.3 Edge detection unit - Selection of slave edge
Name:
X2CfO_EdgeDetectUnit01Slave
X2CfO_EdgeDetectUnit02Slave
These registers are used to select the source of the slave edge for the respective unit. Either the rising or falling
edge of one of the 4 fast digital input channels can be selected. Only one edge can be selected for each unit.
Data type
USINT
Value
0
2
4
6
1
3
5
7
Information
Digital input channel 11: Rising edge
Digital input channel 12: Rising edge
Digital input channel 13: Rising edge
Digital input channel 14: Rising edge
Digital input channel 11: Falling edge
Digital input channel 12: Falling edge
Digital input channel 13: Falling edge
Digital input channel 14: Falling edge
27.2.2.4 Edge detection unit - Master edge counter
Name:
EdgeDetect01Mastercount
EdgeDetect02Mastercount
These registers hold the counter values of the detected master edges. The counter value is used to detect new
measurements.
Data type
INT
Value
-32,768 to 32,767
Information
Running counter: Number of detected master edges
27.2.2.5 Edge detection unit - Master edge timestamp
Name:
EdgeDetect01Mastertime
EdgeDetect02Mastertime
The exact CPU system time of the respective unit is saved to these registers when a master edge occurs. If multiple
master edges occur within a single cycle (task class), then the time of the last edge is shown.
Data type
DINT
Value
-2,147,483,648 to 2,147,483,647
Information
CPU system time of master edge [µs]
27.2.2.6 Edge detection unit - Time difference
Name:
EdgeDetect01Difference
EdgeDetect02Difference
The difference between the master edge and the slave edge of the respective unit is saved to these registers. If
multiple measurement periods are completed within a single cycle (task class), then the time difference from the
last period is shown.
Data type
DINT
Data sheet V 0.38
Value
-2,147,483,648 to 2,147,483,647
Information
Time difference between master edge and slave edge [µs]
41
X20CP1301, X20CP1381 and X20CP1382
27.2.3 Counter functions
Fast digital inputs 11 to 14 can be used for counter functions. This function does not use the digital input filter. The
following functions are available. Only one of these basic configurations can be enabled at a time:
•
•
•
•
2x event counter with latch function
2x AB incremental counter without latch function
DF counter function
ABR counter function
27.2.3.1 Configuring the counter function
The following counter functions can be configured:
Counter function
2x event counter with latch function
2x AB incremental counter without latch function
DF counter:
Direction/Frequency with latch function
ABR counter with latch function
Description
Input 11 for event counter 1 and input 13 for event counter 2 can be used simultaneously as event counters. Both
rising and falling edges are counted. The latch function of all 4 inputs can be used.
Inputs 11 and 12 as AB counter 1 and inputs 13 and 14 as AB counter 2. Since no more fast inputs are available,
the latch function is not available.
The D, F and R signals are linked to inputs 11, 12 and 13. Signal D defines the positive (Level = 0) or negative
(Level = 1) counting direction. The latch function of all 4 inputs can be used.
The A, B and R signals are linked to inputs 11, 12 and 13. The latch function of all 4 inputs can be used.
Name:
X2CfO_CounterMode
This register configures the counter function:
Data type
USINT
Value
0
1
2
3
Information
2x event counter with latch function
2x AB incremental counter without latch function
DF counter with latch function
ABR counter with latch function
27.2.3.2 Configuring the mode of the latch function
Name:
X2CfO_Latch01Mode
X2CfO_Latch02Mode
This register sets the mode of the latch function. The following latch functions can be configured:
Latch function
Single shot latch mode
Continuous latch mode
Description
The latch function must be enabled/set. After a successful latch procedure the function must first be reset. Then
it can be enabled again.
The latch function only has to be enabled/set as long as latching is desired.
A changed counter value on "LatchCount" indicates that the latch procedure has been performed (see 27.2.3.7
"Counter value of latch events"). The counter value is stored in the latch register (see 27.2.3.6 "Latched counter
value").
Data type
USINT
42
Value
0
1
Information
Single shot latch mode
Continuous latch mode
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.2.3.3 Configuring the latch signals
Name:
X2CfO_Latch01Comparator
X2CfO_Latch02Comparator
This register defines the inputs and their level for triggering the latch procedure.
• This defines which inputs are linked to generate the latch event. All 4 digital input signals can be used for
an "AND" connection.
• The "active voltage level" needed for the latch procedure can be defined to adjust for the physical signals.
It is not possible to configure a high and low level at the same time.
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
Information
Input 11 high level disabled
Input 11 high level enabled for comparator
Input 12 high level disabled
Input 12 high level enabled for comparator
Input 13 high level disabled
Input 13 high level enabled for comparator
Input 14 high level disabled
Input 14 high level enabled for comparator
Input 11 low level disabled
Input 11 low level enabled for comparator
Input 12 low level disabled
Input 12 low level enabled for comparator
Input 13 low level disabled
Input 13 low level enabled for comparator
Input 14 low level disabled
Input 14 low level enabled for comparator
27.2.3.4 Clear counter value and enable/disable latch function
Name:
Counter01Reset
Counter02Reset
Latch01Enable
Latch02Enable
The respective bits in these registers clear the counter value or start the latch procedure.
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0
1
2-7
Description
Counter0xReset
Value
0
1
0
1
0
Latch0xEnable
Reserved
Information
Do not reset the counter
Reset the counter
Do not latch the counter
Latch the counter
27.2.3.5 Counter value
Name:
Counter01Value
Counter02Value
The current counter values are saved in these registers.
Data type
DINT
Data sheet V 0.38
Value
-2,147,483,648 to 2,147,483,647
Information
Current counter value
43
X20CP1301, X20CP1381 and X20CP1382
27.2.3.6 Latched counter value
Name:
Counter01Latch
Counter02Latch
As soon as the latch conditions have been met, the value of the respective counter is copied to these registers.
Data type
DINT
Value
-2,147,483,648 to 2,147,483,647
Information
Latched counter value
27.2.3.7 Counter value of latch events
Name:
Latch01Count
Latch02Count
These registers hold the counter values of the latch events. This allows detection of whether a new latched counter
value has been saved.
Data type
DINT
Value
-128 to 127
Information
Running counter: Number of detected latch events
27.2.3.8 Timestamp of last counter change
Name:
Counter01TimeChanged
Counter02TimeChanged
The CPU system time at the time of the last change to the counter value is saved in these registers.
Data type
DINT
Value
-2,147,483,648 to 2,147,483,647
Information
The CPU system time at the time of the last change to the counter value
27.2.3.9 Timestamp of last valid counter value
Name:
Counter01TimeValid
Counter02TimeValid
The CPU system time at the time of the last valid counter value is saved in these registers.
Data type
DINT
44
Value
-2,147,483,648 to 2,147,483,647
Information
CPU system time of current counter value
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.3 Register overview of the I/O data points on the integrated X3 I/O slot
Register
Name
Data type
Read
Cyclic
X3 - Configuration
10240
X3CfO_DI_Filter
10752
X3CfO_Mov01Mode
10756
X3CfO_Mov01SpeedLimit
10768
X3CfO_Mov02Mode
10772
X3CfO_Mov02SpeedLimit
12032
X3CfO_PhyIOConfigCh01
12033
X3CfO_PhyIOConfigCh02
12034
X3CfO_PhyIOConfigCh03
12035
X3CfO_PhyIOConfigCh04
12036
X3CfO_PhyIOConfigCh05
12037
X3CfO_PhyIOConfigCh06
12038
X3CfO_PhyIOConfigCh07
12039
X3CfO_PhyIOConfigCh08
12040
X3CfO_PhyIOConfigCh09
12041
X3CfO_PhyIOConfigCh10
12042
X3CfO_PhyIOConfigCh11
12043
X3CfO_PhyIOConfigCh12
X3 - Communication
8192
Digital inputs
DigitalInput05
DigitalInput06
DigitalInput07
DigitalInput08
8208
Digital outputs
DigitalOutput01
DigitalOutput02
DigitalOutput03
DigitalOutput04
DigitalOutput05
DigitalOutput06
DigitalOutput07
DigitalOutput08
8209
Digital outputs
DigitalOutput09
DigitalOutput10
DigitalOutput11
DigitalOutput12
8193
Status feedback
StatusDigitalOutput01
StatusDigitalOutput02
StatusDigitalOutput03
StatusDigitalOutput04
StatusDigitalOutput05
StatusDigitalOutput06
StatusDigitalOutput07
StatusDigitalOutput08
8194
Status feedback
StatusDigitalOutput09
StatusDigitalOutput10
StatusDigitalOutput11
StatusDigitalOutput12
4864
PWMPeriod09
4866
PWMOutput09
4880
PWMPeriod10
4882
PWMOutput10
4896
PWMPeriod11
4898
PWMOutput11
4912
PWMPeriod12
4914
PWMOutput12
8704
Movement 1
Mov01Enable
8706
Mov01Speed
8708
Mov01Position
8720
Movement 2
Mov02Enable
8722
Mov02Speed
8724
Mov02Position
8196
StatusInput01
Data sheet V 0.38
Write
Acyclic
Cyclic
USINT
USINT
UDINT
USINT
UDINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
USINT
Bit 0
Bit 1
Bit 2
Bit 3
USINT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
USINT
Bit 0
Bit 1
Bit 2
Bit 3
USINT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
USINT
Bit 0
Bit 1
Bit 2
Bit 3
UINT
INT
UINT
INT
UINT
INT
UINT
INT
USINT
Bit 1
INT
DINT
USINT
Bit 2
INT
DINT
BOOL
Acyclic
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
45
X20CP1301, X20CP1381 and X20CP1382
27.3.1 Physical configuration of I/O channels
These registers are used to define the functionality of the channels. Depending on the desired configuration, the
following assignments can be made with respect to the existing software and hardware:
•
•
•
•
A physical configuration as input or output for mixed channels
An explicit assignment as direct I/O channel: i.e. digital input or digital output
An explicit assignment as PWM output
An explicit assignment as D or F movement output
27.3.1.1 Physical configuration
Name:
X3CfO_PhyIOConfigCh01 to X3CfO_PhyIOConfigCh12
These registers are used to configure the functionality of the channels.
Data type
USINT
Value
See bit structure.
Bit structure:
Name:
X3CfO_PhyIOConfigCh01 to X3CfO_PhyIOConfigCh04
Channels 1 to 4 are digital outputs and can only be used as direct I/O channel.
Bit
0-7
Description
Value
0
Information
Direct I/O operation of output
Name:
X3CfO_PhyIOConfigCh05 to X3CfO_PhyIOConfigCh08
Channels 5 to 8 are digital mixed channels and can be configured as either input or output.
Bit
0-1
Description
2-7
Value
00
01
10
11
0
Information
Configured as digital output
Reserved
Reserved
Configured as digital input
Direct I/O operation of output
Name:
X3CfO_PhyIOConfigCh09 to X3CfO_PhyIOConfigCh12
Channels 9 to 12 are fast digital outputs and can be configured as direct I/O, PWM or movement channels.
46
Bit
0-3
4-5
Description
Reserved
6-7
Reserved
Value
0
00
01
10
11
0
Information
Direct I/O operation of output
Output operated as PWM
Reserved
Output operated as D/F movement
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.3.2 Monitoring of the I/O supply voltage
Name:
StatusInput01
The status of the I/O supply voltage is shown in this register.
Data type
USINT
Value
0
1
Information
I/O supply voltage within permitted range
I/O supply voltage not connected or outside of the permitted range
27.3.3 Digital inputs
Unfiltered
The input status is recorded in a 100 µs cycle.
Filtered
The filtered status is transferred in a 100 µs cycle.
Filtering takes place asynchronously in an interval of 100 μs.
27.3.3.1 Digital input filter
Name:
X3CfO_DI_Filter
This register can be used to specify the filter value for all digital inputs.
The filter value can be configured in steps of 100 μs.
Data type
USINT
Value
0
1
...
250
Filter
No SW filter
0.1 ms
...
25 ms - Higher values are limited to this value
27.3.3.2 Input state of digital inputs 5 to 8
Name:
DigitalInput05 to DigitalInput08
This register is used to indicate the input state of digital inputs 5 to 8.
Data type
USINT
Value
See bit structure.
Bit structure:
Bit
0
...
3
Name
DigitalInput05
DigitalInput08
Data sheet V 0.38
Value
0 or 1
...
0 or 1
Information
Input status of digital input 5
Input status of digital input 8
47
X20CP1301, X20CP1381 and X20CP1382
27.3.4 Digital outputs
The output status is processed in a 100 µs cycle.
27.3.4.1 Switching state of digital outputs 1 to 12
Name:
DigitalOutput01 to DigitalOutput12
These registers are used to store the switching state of digital outputs 1 to 12.
Data type
USINT
Value
See bit structure.
Bit structure:
Register 8208:
Bit
0
Description
DigitalOutput01
...
7
DigitalOutput08
Value
0
1
...
0
1
Information
Digital output 1 reset
Digital output 1 set
Value
0
1
...
0
1
Information
Digital output 9 reset
Digital output 9 set
Digital output 8 reset
Digital output 8 set
Register 8209:
48
Bit
0
Description
DigitalOutput09
...
3
DigitalOutput12
Digital output 12 reset
Digital output 12 set
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.3.5 Monitoring status of the digital outputs
The error states of the outputs must be programmed in the application. The status information that is read is the
actual voltage state on the channel (set or reset). The error state is therefore determined by a difference between
the data points "DigitalOutputxx" and the corresponding "StatusDigitalOutputxx".
At least 3 system ticks are needed internally to read the output status. This is the reason for the delay after which
the earliest possible comparison can be made after a change in the status of the output.
The digital input filter is not applied to this status information.
27.3.5.1 Status of digital outputs 1 to 12
Name:
StatusDigitalOutput01 to StatusDigitalOutput12
These registers are used to indicate the status of digital outputs 1 to 12.
Data type
USINT
Value
See bit structure.
Bit structure:
Register 8193:
Bit
0
Description
StatusDigitalOutput01
...
7
StatusDigitalOutput08
Value
0
1
...
0
1
Information
Channel 1: Digital output reset or short circuit
Channel 1: Digital output set or voltage feedback
Value
0
1
...
0
1
Information
Channel 9: Digital output reset or short circuit
Channel 9: Digital output set or voltage feedback
Channel 8: Digital output reset or short circuit
Channel 8: Digital output set or voltage feedback
Register 8194:
Bit
0
Description
StatusDigitalOutput09
...
3
StatusDigitalOutput12
Data sheet V 0.38
Channel 12: Digital output reset or short circuit
Channel 12: Digital output set or voltage feedback
49
X20CP1301, X20CP1381 and X20CP1382
27.3.6 Pulse width modulation (PWM) function
Digital inputs 9 to 12 can be configured as PWM outputs. Two data points are available per channel for controlling
the PWM signal.
Pulse width
U
24 VDC
t
Period (frequency)
Figure 32: The PWM signal is controlled by setting the pulse width and the duration of the period
27.3.6.1 Period duration of the PWM outputs
Name:
PWMPeriod09 to PWMPeriod12
These registers are used to define the duration of the period, i.e. the time base for the respective PWM output.
This time represents the 100% value, which can be resolved to 0.1% through the duty cycle.
Data type
UINT
Value
5 to 65,535
Information
Duration of period, between 5 and 65535 µs: Corresponds to a frequency between 200 kHz and
∼15 Hz
27.3.6.2 Duty cycle of the PWM outputs
Name:
PWMOutput09 to PWMOutput12
These registers output the duty cycle of the respective PWM output in a resolution of 0.1% of the period.
Data type
INT
Value
0 to 1,000
Information
Duty cycle of the output in 0 to 100.0%
Example: Period duration T [µs] with a duty cycle of 25% equals a duty time of t1 [µs].
U
24 VDC
t
t1
T
t1
T
= 0.25 = 25%
Figure 33: Duty time as a function of the period and the duty cycle
50
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.3.7 DF movement generator function
Digital output channels 9 to 12 can be configured as 2 independently functioning movement generators (Direction/Frequency) for stepper motor control. The movement generators are assigned to the following channels:
Movement generator
1
2
Channel
DO 9
DO 10
DO 11
DO 12
Function
D: Direction
Q: Frequency
D: Direction
Q: Frequency
The frequency is output via the respective F channel, and the direction is output via the respective D channel. The
switchover between directions (movement/counter) takes place via the sign of the speed setpoint.
F - Frequency
D - Direction
Positive direction of movement/counter
Negative direction of movement/counter
Figure 34: Frequency output via F channel, direction output via D channel
The respective output must be configured correctly in order to completely process the movement function (see
27.3.1.1 "Physical configuration").
The data points described below are available for configuring and controlling the respective movements.
Data sheet V 0.38
51
X20CP1301, X20CP1381 and X20CP1382
27.3.7.1 Configuring the movement mode
Name:
X3Cfo_Mov01Mode
X3Cfo_Mov02Mode
These registers are used to configure how the speed setpoint is interpreted. The difference between the two modes
is whether edges or periods are output for each increment of the setpoint.
Data type
USINT
Value
0
1
Information
Edge mode: Each increment generates an edge on the output
Pulse mode: Each increment generates a period on the output
Edge mode
4 increments of the speed setpoint correspond to 2 periods on the output:
U
24 VDC
t
Figure 35: Interpretation of the speed setpoint with edge output for each increment
Pulse mode
2 increments of the speed setpoint correspond to 2 periods on the output:
U
24 VDC
t
Figure 36: Interpretation of the speed setpoint with period output for each increment
52
Data sheet V 0.38
X20CP1301, X20CP1381 and X20CP1382
27.3.7.2 Configuring the maximum speed of the movement
The maximum speed or output frequency of the movement is configured in order to protect the digital output, the
actuator/drive being controlled and/or the mechanical system.
Name:
X3Cfo_Mov01SpeedLimit
X3Cfo_Mov02SpeedLimit
These registers are used to configure the maximum speed / output frequency permitted in the system. It is important
that the limit values for edge and pulse mode are different.
Edge mode
Data type
UDINT
Value
10 to 400,000
Information
Speed [increments per second]
Value
5 to 200,000
Information
Speed [increments per second]
Pulse mode
Data type
UDINT
27.3.7.3 Activates the movement
When a movement is active, the two channels are operated according to the preset values.
Name:
Mov01Enable
Mov02Enable
These registers are used to enable or disable the movement function.
Mov01Enable
Data type
USINT
Value
0
2
Information
Movement 1 disabled
Movement 1 enabled: The speed setpoint is evaluated
Value
0
4
Information
Movement 2 disabled
Movement 2 enabled: The speed setpoint is evaluated
Mov02Enable
Data type
USINT
Data sheet V 0.38
53
X20CP1301, X20CP1381 and X20CP1382
27.3.7.4 Speed and direction control of the movement
The following parameters are important for speed and direction control of the movement:
Characteristic value
Speed control
Direction control
Resolution of the speed setpoint
Relationship: Speed / Frequency
Description
The joint axes receive this speed setpoint from the standard application.
0 to ±32767 correspond to 0 to ±100% of the configured maximum speed
The direction of movement is defined by the sign of the speed setpoint:
0 to +32767 correspond to 0 to the maximum speed in the positive direction of movement
0 to -32767 correspond to 0 to the maximum speed in the negative direction of movement
The resolution of the speed setpoint is:
Maximum speed / 32767
The relationship between speed and output frequency is:
(Speed setpoint / Maximum speed) * 32767
U
24 VDC
t
Speed / output frequency
Table 23: Parameters for speed and direction control of the movement
Name:
Mov01Speed
Mov02Speed
These registers are used to set the speed of the movement.
Data type
INT
Value
0 to 32,767
0 to -32,767
Information
Speed setpoint 0 to 100%:
Movement output F = 0 to maximum speed
Positive direction of movement: Movement output D = 0
Speed setpoint 0 to 100%:
Movement output F = 0 to maximum speed
Negative direction of movement: Movement output D = 1
27.3.7.5 Position feedback for movement
The position feedback is represented by a fixed point value [16.16]:
• HighWord = whole number increments
• LowWord = positions after the decimal of the increments
Name:
Mov01Position
Mov02Position
These registers show the current position of the movement.
Data type
DINT
54
Value
-2,147,483,648 to 2,147,483,647
Information
Position value in fixed point format [16.16]
Data sheet V 0.38

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