ASX340AT - 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC

ASX340AT - 1/4‐inch Color CMOS NTSC/PAL Digital Image SOC
ASX340AT
1/4‐inch Color CMOS
NTSC/PAL Digital Image
SOC with Overlay Processor
General Description
The ON Semiconductor ASX340AT is a VGA-format, single-chip
CMOS active-pixel digital image sensor for automotive applications.
It captures high-quality color images at VGA resolution and outputs
NTSC or PAL interlaced composite video.
The VGA CMOS image sensor features ON Semiconductor’s
breakthrough low-noise imaging technology that achieves superior
image quality (based on signal-to-noise ratio and low-light sensitivity)
while maintaining the inherent size, cost, low power, and integration
advantages of ON Semiconductor’s advanced active pixel CMOS
process technology.
The ASX340AT is a complete camera-on-a-chip. It incorporates
sophisticated camera functions on-chip and is programmable through
a simple two-wire serial interface or by an attached SPI EEPROM or
Flash memory that contains setup information that may be loaded
automatically at startup.
The ASX340AT performs sophisticated processing functions
including color recovery, color correction, sharpening, programmable
gamma correction, auto black reference clamping, auto exposure,
50Hz/60Hz flicker detection and avoidance, lens shading correction,
auto white balance (AWB), and on-the-fly defect identification and
correction.
The ASX340AT outputs interlaced-scan images at 60 or 50 fields
per second, supporting both NTSC and PAL video formats. The image
data can be output on one or two output ports:
• Composite analog video (single-ended and differential
output support)
• Parallel 8-, 10-bit digital
Features
• Low-Power CMOS Image Sensor with Integrated Image Flow
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•
•
•
•
•
•
•
Processor (IFP) and Video Encoder
1/4-inch Optical Format, VGA Resolution (640 H x 480 V)
2x Upscaling Zoom and Pan Control
±40 Additional Columns and ± 36 Additional Rows to Compensate
for Lens Alignment Tolerances
Option to Use Single 2.8 V Power Supply with Off-Chip Bypass
Transistor
Overlay Generator for Dynamic Bitmap Overlay
Integrated Video Encoder for NTSC/PAL with Overlay Capability
and 10-bit I-DAC
Integrated Microcontroller for Flexibility
On-Chip Image Flow Processor Performs Sophisticated Processing,
Such as Color Recovery and Correction, Sharpening, Gamma, Lens
Shading Correction, On-the-Fly Defect Correction, Auto White
Balancing, and Auto Exposure
© Semiconductor Components Industries, LLC, 2014
October, 2016 − Rev. 10
1
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IBGA63 7.5 y 7.5
CASE 503AE
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
• Auto Black-Level Calibration
• 10-Bit, On-Chip Analog-to-Digital
Converter (ADC)
• Internal Master Clock Generated by
•
•
•
•
•
•
On-Chip Phase-Locked Loop (PLL)
Two-Wire Serial Programming Interface
Interface to Low-Cost EEPROM and Flash
through SPI Bus
High-Level Host Command Interface
Stand-Alone Operation Support
Comprehensive Tool Support for Overlay
Generation and Lens Correction Setup
Development System with DevWare
Applications
• Automotive Rear View Camera and Side
Mirror
• Blind Spot and Surround View
Publication Order Number:
ASX340AT/D
ASX340AT
TABLE 1. KEY PARAMETERS
Parameter
Typical Value
Pixel Size and Type
5.6 mm x 5.6 mm active pinned-photodiode with high-sensitivity mode for low-light
conditions
Sensor Clear Pixels
728 H x 560 V (includes VGA active pixels, demosaic and lens alignment pixels)
NTSC Output
720 H x 487 V
PAL Output
720 H x 576 V
Optical Area (Clear Pixels)
4.077 mm x 3.136 mm
Optical Format
1/ -inch
4
Frame Rate
50/60 fields/sec
Sensor Scan Mode
Progressive scan
Color Filter Array
RGB standard Bayer
Chief Ray Angle (CRA)
0°
Shutter Type
Electronic rolling shutter (ERS)
Automatic Functions
Exposure, white balance, black level offset correction, flicker detection and avoidance,
color saturation control, on the-fly defect correction, aperture correction
Programmable Controls
Exposure, white balance, horizontal and vertical blanking, color, sharpness, gamma
correction, lens shading correction, horizontal and vertical image flip, zoom, windowing,
sampling rates, GPIO control
Overlay Support
Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the
following features:
− Available in Analog output and BT656 Digital output
− Overlay Size 360 x 480 pixel rendered into 720 x 480 (NTSC) or 720 x 576 (PAL)
− Up to four (4) overlays may be blended simultaneously
− Selectable readout: Rotating order user-selected
− Dynamic scenes by loading pre-rendered frames from external memory
− Palette of 32 colors out of 64 000
− 8 colors per bitmap
− Blend factor dynamically-programmable for smooth transitions
− Fast update rate of up to 30 fps
− Every bitmap object has independent x/y position
− Statistic Engine to calibrate optical alignment
− Number Generator
ADC
10-bit, on-chip
Output Interface
Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output
Output Data Formats1
Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB
Data Rate
Parallel: 27 MHz Pixel clock
NTSC: 60 fields/sec
PAL: 50 fields/sec
Control Interface
Two-wire I/F for register interface plus high-level command exchange. SPI port to
interface to external memory to load overlay data, register settings, or firmware
extensions.
Input Clock for PLL
27 MHz
SPI Clock Frequencies
1.6875 – 18 MHz, programmable
Supply Voltage
Analog: 2.8 V + 5%
Core: 1.8 V + 5% (2.8 V + 5% power supply with off-chip bypass transistor generates a
1.70 − 1.95 V core voltage supply, which is acceptable for performance.)
Supply Voltage
Power Consumption
Package
IO: 2.8 V + 5%
Analog Output Only
Full resolution at 60 fps: 291 mW
Digital Output Only
Full resolution at 60 fps: 192 mW
63-BGA, 7.5 mm x 7.5 mm, 0.65 mm pin pitch
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2
ASX340AT
TABLE 1. KEY PARAMETERS (CONTINUED)
Parameter
Typical Value
Ambient Temperature
Operating: −40°C to 105°C
Functional: −40°C to + 85°C
Storage: −50°C to + 150°C
Dark Current
< 200 e/s at 60°C with a gain of 1
Fixed Pattern Noise
Column
<2%
Row
<2%
Responsivity
16.5 V/lux−s at 550 nm
Signal to Noise Ratio (S/N)
46 dB
Pixel Dynamic Range
87 dB
NEW FEATURES
• Temperature sensor for dynamic feedback and sensor
• Horizontal field of view adjustment between 700 and
•
•
•
•
control
Automatic 50 Hz/60 Hz flicker detection
2x upscaling zoom and pan/tilt control
Independent control of colorburst parameters in the
NTSC/PAL encoder
•
720 pixels on the analog output
Option to use single 2.8 V power supply with off-chip
bypass transistor
SPI EEPROM support for lower cost system design.
ORDERING INFORMATION
TABLE 2. AVAILABLE PART NUMBERS
Part Number
Product Description
Orderable Product Attribute Description
ASX340AT2C00XPED0−DPBR1
Rev2, Color, 0deg CRA, iBGA Package
Drypack, Protective Film, Anti-Reflective
Glass
ASX340AT2C00XPED0−DRBR1
Rev2, Color, 0deg CRA, iBGA Package
Drypack, Anti-Reflective Glass
ASX340AT2C00XPED0−TPBR
Rev2, Color, 0deg CRA, iBGA Package
Tape & Reel, Protective Film,
Anti-Reflective Glass
ASX340AT2C00XPED0−TRBR
Rev2, Color, 0deg CRA, iBGA Package
Tape & Reel, Anti-Reflective Glass
ASX340AT2C00XPEDD3−GEVK
Rev2, Color, Demo Kit
ASX340AT2C00XPEDH3−GEVB
Rev2, Color, Head Board
ASX340AT3C00XPED0−DPBR
Rev3, Color, 0deg CRA, iBGA Package
Drypack, Protective Film, Anti-Reflective
Glass
ASX340AT3C00XPED0−DRBR
Rev3, Color, 0deg CRA, iBGA Package
Drypack, Anti-Reflective Glass
ASX340AT3C00XPED0−TPBR
Rev3, Color, 0deg CRA, iBGA Package
Tape & Reel, Protective Film,
Anti-Reflective Glass
ASX340AT3C00XPED0−TRBR
Rev3, Color, 0deg CRA, iBGA Package
Tape & Reel, Anti-Reflective Glass
ASX340AT3C00XPEDD3−GEVK
Rev 3, Color, Demo Kit
ASX340AT3C00XPEDH3−GEVB
Rev 3, Color, Head Board
See the ON Semiconductor Device Nomenclature document
(TND310/D) for a full description of the naming convention used for
image sensors. For reference documentation, including information on
evaluation kits, please visit our web site at www.onsemi.com.
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3
ASX340AT
ARCHITECTURE
System Block Diagram
The system block diagram will depend on the application.
The system block diagram in Figure 2 shows all
components; optional peripheral components are
highlighted. Control information will be received by a
microcontroller through the automotive bus to communicate
with the ASX340AT through its two-wire serial bus.
Optional components will vary by application.
18 pF −NPO
EXTCLK
27.000 MHz
18pF −NPO
XTAL
RESET_BAR
FRAME_SYNC
System Bus
μC
Serial Data
EEPROM/Flash
1KB − 16MB
SPI
2WIRE I/F
LP Filter
2.35 kΩ
DAC _POS
DAC _REF
DAC _NEG
37.5Ω
V DD_DAC (2.8 V)
VDD_PLL (2.8. V)
2.8V
VDD_IO (2.8 V)
Optional
VAA _PIX ( 2.8 V)
VAA (2.8 V )
VDD ( 1.8 V )
VREG_BASE
DOUT [7: 0]
DOUT_LSB0, 1
PIXCLK
FRAME_VALID
LINE_VALID
Figure 1. System Block Diagram
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CCIR 656/
GPO
Composite
Video
PAL /NTSC
ASX340AT
Internal Block Diagram
SPI
4
Two−Wire I/F
1.8V
2.8V
2
Camera control
AWB
AE
SPI & 2WI/F
Interface
640 x 480 Active Array
¼’’VGA ROI
@ 60 frames per sec.
Image Flow Processor
10
Overlay
Graphics
Generation
Color & Gama Correction
Color Space Conversion
Edge enhancement
VideoEncoder
DAC
8
BT−656
NTSC/
PAL
Figure 2. Internal Block Diagram
Crystal Usage
As an alternative to using an external oscillator, a
fundamental 27 MHz crystal may be connected between
EXTCLK and XTAL. Two small loading capacitors of
10–22 pF of NPO dielectric should be added as shown in
Figure 3.
ON Semiconductor does not recommend using the crystal
option for applications above 85°C. A crystal oscillator with
temperature compensation is recommended.
Sensor
18 pF −NPO
EXTCLK
27.000 MHz
XTAL
18pF −NPO
NOTE:
Value of load capacitor is crystal dependent. Crystal with small load capacitor is recommended.
Figure 3. Using a Crystal Instead of an External Oscillator
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ASX340AT
PIN DESCRIPTIONS AND ASSIGNMENTS
TABLE 3. PIN DESCRIPTION
Pin Name
Type
A2
EXTCLK
Input
Master input clock (27 MHz): This can either be a
square-wave generated from an oscillator (in which
case the XTAL input must be left unconnected) or
connected directly to a crystal.
B1
XTAL
Output
If EXTCLK is connected to one pin of a crystal, this
signal is connected to the other pin; otherwise this
signal must be left unconnected.
D2
RESET_BAR
Input
Asynchronous active-low reset: When asserted, the
device will return all interfaces to their reset state.
When released, the device will initiate the boot
sequence. This signal has an internal pull-up resistor.
E1
FRAME_SYNC
Input
This input can be used to set the output timing of the
ASX340AT to a fixed point in the frame.
The input buffer associated with this input is
permanently enabled. This signal must be connected
to GND if not used.
SCLK
Input
F2
SDATA
Input/Output
These two signals implement the serial
communications protocol for access to the internal
registers and variables.
E2
SADDR
Input
D4
SPI_SCLK
Output
E4
SPI_SDI
Input
H3
SPI_SDO
Output
Data out to SPI device. Tri-state when RESET_BAR is
asserted.
H2
SPI_CS_N
Output
Chip selects to SPI device. Tri-state when
RESET_BAR is asserted.
F7
FRAME_VALID
Input/Output
G7
LINE_VALID
Input/Output
E6
PIXCLK
Output
F8, D6, D7, C6, C7, B6, B7, A6
DOUT[7:0]
Output
B3
DOUT_LSB1
Input/Output
C2
DOUT_LSB0
Input/Output
Pin Number
Description
Clock and Reset
Register Interface
F1
This signal controls the device ID that will respond to
serial communication commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
SPI Interface
Clock output for interfacing to an external SPI memory
such as Flash/EEPROM. Tri-state when RESET_BAR
is asserted.
Data in from SPI device. This signal has an internal
pull-up resistor.
(Parallel) Pixel Data Output
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Pixel data from the ASX340AT can be routed out on
this interface and processed externally.
To save power, these signals are driven to a constant
logic level unless the parallel pixel data output or
alternate (GPIO) function is enabled for these pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose
input/outputs.
When the sensor core is running in bypass mode, it
will generate 10 bits of output data per pixel. These
two pins make the two LSB of pixel data available
externally. Leave DOUT_LSB1and DOUT_LSB0
unconnected if not used. To save power, these signals
are driven to a constant logic level unless the sensor
core is running in bypass mode or the alternate
function is enabled for these pins. The slew rate of
these outputs is programmable.
ASX340AT
TABLE 3. PIN DESCRIPTION (CONTINUED)
Pin Name
Type
Description
F5
DAC_POS
Output
Positive video DAC output in differential mode.
Video DAC output in single-ended mode. This
interface is enabled by default using NTSC/PAL
signaling. For applications where composite video
output is not required, the video DAC can be placed in
a power-down state under software control.
G5
DAC_NEG
Output
Negative video DAC output in differential mode.
A4
DAC_REF
Output
External reference resistor for the video DAC.
Pin Number
Composite Video Output
Manufacturing Test Interface
D3
TDI
Input
JTAG Test pin (Reserved for Test Mode)
G2
TDO
Output
JTAG Test pin (Reserved for Test Mode)
F3
TMS
Input
JTAG Test pin (Reserved for Test Mode)
C3
TCK
Input
JTAG Test pin (Reserved for Test Mode)
C4
TRST_N
Input
Connect to GND.
G6
ATEST1
Input
Analog test input. Connect to GND in normal
operation.
F6
ATEST2
Input
Analog test input. Connect to GND in normal
operation.
C1
GPIO12
Input/Output
Dedicated general-purpose input/output pin.
A3
GPIO13
Input/Output
Dedicated general-purpose input/output pin.
G4
VREG_BASE
Supply
Voltage regulator control. Leave floating if not used.
A5, A7, D8, E7, G1, G3
VDD
Supply
Supply for VDD core: 1.8 V nominal. Can be connected
to the output of the transistor of the off-chip bypass
transistor or an external 1.8 V power supply.
B2, B8, C8, E3, E8, G8, H8
VDD_IO
Supply
Supply for digital IOs: 2.8 V nominal.
H5
VDD_DAC
Supply
Supply for video DAC: 2.8 V nominal.
A8
VDD_PLL
Supply
Supply for PLL: 2.8 V nominal.
B4, H6
VAA
Supply
Analog power: 2.8 V nominal.
H7
VAA_PIX
Supply
Analog pixel array power: 2.8 V nominal. Must be at
same voltage potential as VAA.
H4
Reserved
B5, C5, D1, D5, H1
DGND
Supply
Digital ground.
E5, F4
AGND
Supply
Analog ground.
GPIO
Power
Leave floating for normal operation.
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ASX340AT
Pin Assignments
Pin 1 is not populated with a ball. That allows the device
to be identified by an additional marking.
TABLE 4. PIN ASSIGNMENTS
1
A
2
3
4
5
6
7
8
EXTCLK
GPIO13
DAC_REF
VDD
DOUT0
VDD
VDD_PLL
B
XTAL
VDD_IO
DOUT_LSB1
VAA
GND
DOUT2
DOUT1
VDD_IO
C
GPIO12
DOUT_LSB0
TCK
TRST_N
GND
DOUT4
DOUT3
VDD_IO
D
GND
RESET_BAR
TDI
SPI_SCLK
GND
DOUT6
DOUT5
VDD
E
FRAME_SYNC
SADDR
VDD_IO
SPI_SDI
AGND
PIXCLK
VDD
VDD_IO
F
SCLK
SDATA
TMS
AGND
DAC_POS
ATEST2
FRAME_VALID
DOUT7
G
VDD
TDO
VDD
VREG_BASE
DAC_NEG
ATEST1
LINE_VALID
VDD_IO
H
GND
SPI_CS_N
SPI_SDO
Reserved
VDD_DAC
VAA
VAA_PIX
VDD_IO
TABLE 5. RESET/DEFAULT STATE OF INTERFACES
Name
Reset State
Default State
Clock running or stopped
Clock running
Input
N/A
N/A
Input
Asserted
De-asserted
Input
SCLK
N/A
N/A
Input. Must always be driven to high via
a pull-up resistor in the range of 1.5 to 4.7 kΩ.
SDATA
High impedance
High impedance
Input/Output. Must always be driven to high via
a pull-up resistor in the range of 1.5 to 4.7 kΩ.
SADDR
N/A
N/A
EXTCLK
XTAL
RESET_BAR
SPI_SCLK
Notes
Input. Must be permanently tied to VDD_IO or
GND.
High impedance.
Driven, logic 0
SPI_SDI
Internal pull-up enabled.
Internal pull-up enabled
SPI_SDO
High impedance
Driven, logic 0
Output enable is R0x0032[13].
SPI_CS_N
High impedance
Driven, logic 1
Output enable is R0x0032[13].
FRAME_VALID
High impedance
High impedance
High impedance
Driven, logic 0
LINE_VALID
PIXCLK
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
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Output. Output enable is R0x0032[13].
Input. Internal pull-up is permanently enabled.
Input/Output. This interface is disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can be
left unconnected (floating). After reset, these
pins are powered up, sampled, then powered
down again as part of the auto-configuration
mechanism. See Note 2.
Output. This interface disabled by default.
See Note 1.
ASX340AT
TABLE 5. RESET/DEFAULT STATE OF INTERFACES (CONTINUED)
Name
Reset State
Default State
Notes
DOUT_LSB1
High impedance
High impedance
DOUT_LSB0
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered-up, sampled, then powered down
again as part of the auto-configuration
mechanism.
DAC_POS
High impedance
Driven
TDI
Internal pull-up enabled
Internal pull-up enabled
TDO
High impedance
High impedance
TMS
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can be
left unconnected (floating).
TCK
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can be
left unconnected (floating).
TRST_N
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be driven to GND for normal
operation.
FRAME_SYNC
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be driven to GND if not used.
GPIO12
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating)
GPIO13
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating).
ATEST1
N/A
N/A
Must be driven to GND for normal operation.
ATEST2
N/A
N/A
Must be driven to GND for normal operation.
DAC_NEG
Output. Interface disabled by hardware reset
and enabled by default when the device starts
streaming.
DAC_REF
Input. Internal pull-up means that this pin can be
left unconnected (floating).
Output. Driven only during appropriate parts of
the JTAG shifter sequence.
1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired in a system (for example, on ON
Semiconductor’s demo boards), these outputs will be connected, and the inputs to which they are connected will want to see a valid logic
level. No current drain should result from driving these to a valid logic level (unless there is a pull-up at the system level).
2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they can be left floating but they will not
drive a valid logic level to an attached device.
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ASX340AT
SOC DESCRIPTION
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout
chain, a 10-bit ADC with programmable gain and black
offset, and timing and control as illustrated in Figure 4.
Array
Control Register
Communication
Timing and Control
Clock
ADC
10−Bit Data
to IFP
Analog Processing
Figure 4. Sensor Core Block Diagram
Pixel Array Structure:
The sensor core pixel array is configured as 728 columns
by 560 rows, as shown in Figure 5.
(40, 36)
(0, 0)
Pixel logical address = (727, 559)
demosaic columns
Active pixel array
640 x 480
Pixel logical address = (0, 0)
lens alignment columns
lens alignment columns
demosaic columns
lens alignment rows
demosaic rows
demosaic rows
lens alignment rows
(687, 523)
(not to scale)
Figure 5. Pixel Array Description
alignment rows on the top and bottom, and 40 lens alignment
columns on the left and right; and there are 4 demosaic rows
and 4 demosaic columns on each side.
Figure 6 illustrates the process of capturing the image.
The original scene is flipped and mirrored by the sensor
optics. Sensor readout starts at the lower right corner. The
image is presented in true orientation by the output display.
Black rows used internally for automatic black level
adjustment are not addressed by default, but can be read out
in raw output mode via a register setting.
There are 728 columns by 560 rows of optically-active
pixels (that is, clear pixels) that include a pixel boundary
around the VGA (640 x 480) image to avoid boundary
effects during color interpolation and correction. Among the
728 columns by 560 rows of clear pixels, there are 36 lens
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ASX340AT
SCENE
(Front view)
OPTICS
Process of Image Gathering and Image Display
IMAGE SENSOR
(Rear view)
IMAGE CAPTURE
Row by Row
Start Rasterization
Start Readout
IMAGE RENDERING
DISPLAY
(Front view)
Figure 6. Image Capture Example
SENSOR PIXEL ARRAY
The active pixel array is 640 x 480 pixels. In addition,
there are 72 rows and 80 columns for lens alignment and 8
rows and 8 columns for demosaic.
Column Readout Direction
..
.
G
Direction
...
B
G
Black Pixels
G
G
R
R
R
G
G
G
B
B
First Lens Alignment
Pixel
(64, 0)
B
Figure 7. Pixel Color Pattern Detail (top right corner)
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ASX340AT
Output Data Format:
The sensor core image data are read out in progressive
scan order. Valid image data are surrounded by horizontal
and vertical blanking, shown in Figure 8.
For NTSC output, the horizontal size is stretched from 640
to 720 pixels. The vertical size is 243 pixels per field; 240
image pixels and 3 dark pixels that are located at the bottom
of the image field.
For PAL output, the horizontal size is also stretched from
640 to 720 pixels. The vertical size is 288 pixels per field.
P0,0 P0,1 P0,2 .....................................P0,n−1 P0,n
P2,0 P2,1 P2,2 .....................................P2,n−1 P2,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Horizontal
Blanking
Valid Image Odd Field
Pm−2,0 Pm−2,1 .....................................Pm−2,n−1 Pm−2,n
Pm,0 Pm,1 .....................................Pm,n−1 Pm,n
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical/Horizontal
Blanking
Vertical Even Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P1,0 P1,1 P1,2.....................................P1,n−1 P1,n
P3,0 P3,1 P3,2.....................................P3,n−1 P3,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Horizontal
Blanking
Valid Image Even Field
Pm−1,0 Pm−1,1 .....................................Pm−1,n−1 Pm−1,n
Pm+1,0 Pm+1,1 ..................................Pm+1,n−1 Pm+1,n
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical/Horizontal
Blanking
Vertical Odd Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Figure 8. Spatial Illustration on Image Readout
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ASX340AT
Image Flow Processor
Image and color processing in the ASX340AT are
implemented as an image flow processor (IFP) coded in
hardware logic. During normal operation, the embedded
microcontroller will automatically adjust the operation
parameters. The IFP is broken down into different sections,
as outlined in Figure 9.
RAW 10
Pixel Array
ADC
Raw Data
IFP
Test Pattern
Generator
MUX
Black
Digital Gain Control
Lens Shading
Correction
Defect Correction,
Noise Reduction,
Color Interpolation
Statistics
Engine
8−bit
RGB
RGB to YUV
10/12−Bit
RGB
8-bit
YUV
Color Correction
Color Kill
Aperture
Correction
YUV to RGB
(12−to−8 Lookup)
Overlay Control
Output
Interface
Parallel Output Mux
Analog Output Mux
Parallel
Output
NTSC/PAL
Figure 9. Color Pipeline
Test Patterns
During normal operation of the ASX340AT, a stream of
raw image data from the sensor core is continuously fed into
the color pipeline. For test purposes, this stream can be
replaced with a fixed image generated by a special test
module in the pipeline. The module provides a selection of
test patterns sufficient for basic testing of the pipeline.
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13
ASX340AT
NTSC/PAL Test Pattern Generation
There is a built-in standard EIA (NTSC) and EBU (PAL)
color bars to support hue and color saturation
characterization. Each pattern consists of seven color bars
(white, yellow, cyan, green, magenta, red, and blue). The Y,
Cb and Cr values for each bar are detailed in Tables 6 and 7.
Figure 10. Color Pipeline
TABLE 6. EIA COLOR BARS (NTSC)
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
Y
16 to 235
180
162
131
112
84
65
35
Cb
16 to 240
128
44
156
72
184
100
212
Cr
16 to 240
128
142
44
58
198
212
114
TABLE 7. EBU COLOR BARS (PAL)
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
Y
16 to 235
235
162
131
112
84
65
35
Cb
16 to 240
128
44
156
72
184
100
212
Cr
16 to 240
128
142
44
58
198
212
114
CCIR-656 Format
The color bar data is encoded in 656 data streams. The
duration of the blanking and active video periods of the
generated 656 data are summarized in Tables 8 and 9.
TABLE 8. NTSC
Line Numbers
Field
Description
1−3
2
Blanking
4−19
1
Blanking
20−263
1
Active video
264−265
1
Blanking
266−282
2
Blanking
283−525
2
Active Video
Line Numbers
Field
1−22
1
Blanking
23−310
1
Active video
TABLE 9. PAL
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14
Description
ASX340AT
TABLE 9. PAL (CONTINUED)
Line Numbers
Field
Description
311−312
1
Blanking
313−335
2
Blanking
336−623
2
Active video
624−625
2
Blanking
Black Level Subtraction and Digital Gain
seeks the best compromise between preserving edges and
filtering out high frequency noise in flat field areas. The
edge threshold can be set through register settings.
Image stream processing starts with black level
subtraction and multiplication of all pixel values by a
programmable digital gain. Both operations can be
independently set to separate values for each color channel
(R, Gr., Gb, B). Independent color channel digital gain can
be adjusted with registers. Independent color channel black
level adjustments can also be made. If the black level
subtraction produces a negative result for a particular pixel,
the value of this pixel is set to 0.
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output,
interpolated RGB values of all pixels are subjected to color
correction. The IFP multiplies each vector of three pixel
colors by a 3 x 3 color correction matrix. The three
components of the resulting color vector are all sums of three
10-bit numbers. Since such sums can have up to 12
significant bits, the bit width of the image data stream is
widened to 12 bits per color (36 bits per pixel). The color
correction matrix can be either programmed by the user or
automatically selected by the auto white balance (AWB)
algorithm implemented in the IFP. Color correction should
ideally produce output colors that are corrected for the
spectral sensitivity and color crosstalk characteristics of the
image sensor. The optimal values of the color correction
matrix elements depend on those sensor characteristics and
on the spectrum of light incident on the sensor. The color
correction parameters can be adjusted through register
settings.
To increase image sharpness, a programmable 2D
aperture correction (sharpening filter) is applied to
color-corrected image data. The gain and threshold for 2D
correction can be defined through register settings.
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is
significantly attenuated near the edges. There are also other
factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these
factors is known as image shading. The ASX340AT has an
embedded shading correction module that can be
programmed to counter the shading effects on each
individual R, Gb, Gr., and B color signal.
The Correction Function
The correction functions can then be applied to each pixel
value to equalize the response across the image as follows:
Pcorrected (row,col)=Psensor(row,col)*f(row,col)
(EQ 1)
where P is the pixel values and f is the color dependent
correction functions for each color channel.
Gamma Correction
The ASX340AT includes a block for gamma correction
that can adjust its shape based on brightness to enhance the
performance under certain lighting conditions. Two custom
gamma correction tables may be uploaded corresponding to
a brighter lighting condition and a darker lighting condition.
At power-up, the IFP loads the two tables with default
values. The final gamma correction table used depends on
the brightness of the scene and takes the form of an
interpolated version of the two tables.
The gamma correction curve (as shown in Figure 11) is
implemented as a piecewise linear function with 19 knee
points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64,
128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304,
2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit
ordinates are programmable through registers.
Color Interpolation
In the raw data stream fed by the sensor core to the IFP,
each pixel is represented by a 10-bit integer number, which
can be considered proportional to the pixel’s response to a
one-color light stimulus, red, green, or blue, depending on
the pixel’s position under the color filter array. Initial data
processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream,
but after the defect correction it must be converted to a
three-colors-per-pixel stream appropriate for standard color
processing. The conversion is done by an edge-sensitive
color interpolation module. The module pads the incomplete
color information available for each pixel with information
extracted from an appropriate set of neighboring pixels. The
algorithm used to select this set and extract the information
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ASX340AT
Gamma Correction
300
Output RB, 8 bit
250
200
0.45
150
100
50
0
0
1000
2000
3000
Input RGB, 12-bit
4000
Figure 11. Gamma Correction Curve
YUV-to-RGB/YUV Conversion and Output Formatting
RGB to YUV Conversion
For further processing, the data is converted from RGB
color space to YUV color space.
The YUV data stream emerging from the colorpipe can
either exit the color pipeline as-is or be converted before exit
to an alternative YUV or RGB data format.
Color Kill
To remove high-or low-light color artifacts, a color kill
circuit is included. It affects only pixels whose luminance
exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the
difference between their luminance and the threshold.
Output Format and Timing
YUV/RGB Data Ordering
The ASX340AT supports swapping YCbCr mode, as
illustrated in Table 10.
YUV Color Filter
As an optional processing step, noise suppression by
one-dimensional low-pass filtering of Y and/or UV signals
is possible. A 3- or 5-tap filter can be selected for each signal.
TABLE 10. YCbCr OUTPUT DATA ORDERING
Mode
Data Sequence
Default (no swap)
Cbi
Yi
Cri
Yi+1
Swapped CbCr
Cri
Swapped YC
Yi
Yi
Cbi
Yi+1
Cbi
Yi+1
Cri
Swapped CbCr, YC
Yi
Cri
Yi+1
Cbi
TABLE 11. RGB ORDERING IN DEFAULT MODE
Mode (Swap Disabled)
Byte
D7 D6 D5 D4 D3 D2 D1 D0
565RGB
Odd
R7 R6 R5 R4 R3 G 7 G 6 G 5
Even
G4G3G2B7B6B5B4B3
Odd
0 R7R6R5R4R3G7G6
Even
G5G4G3B7B6B5B4B3
Odd
R7 R6 R5 R4 G 7 G 6 G 5 G 4
555RGB
444 x RGB
x444RGB
Even
B7B6B5B4 0 0 0 0
Odd
0 0 0 0 R7R6R5R4
Even
G7G6G5G4B7B6B5B4
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ASX340AT
• Using only 8 signals (DOUT[7:0]) and a special 8 + 2
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output
in bypass mode in two ways:
• Using 8 data output signals (DOUT[7:0]) and
GPIO[1:0]. The GPIO signals are the least significant 2
bits of data.
data format, shown in Table 12.
TABLE 12. 2-BYTE BAYER FORMAT
Byte
Bits Used
Bit Sequence
Odd bytes
8 data bits
D9 D8 D7 D6 D5 D4 D3 D2
Even bytes
2 data bits + 6 unused bits
0 0 0 0 0 0 D1 D 0
Output Ports
Composite Video Output:
The
composite
video
output
DAC
is
external-resistor-programmable and supports both
single-ended and differential output. The DAC is driven by
the on-chip video encoder output.
Parallel Output:
Parallel output uses either 8-bit or 10-bit output. Eight-bit
output is used for ITU-R BT.656 and RGB output. Ten-bit
output is used for raw Bayer output.
Readout Formats
Progressive format is used for raw Bayer output.
Output Formats
ITU-R BT.656 and RGB Output:
TheASX340AT can output processed video as a standard
ITU-R BT.656 (CCIR656) stream, an RGB stream, or as
unprocessed Bayer data. The ITU-R BT.656 stream contains
YCbCr 4:2:2 data with embedded synchronization codes.
This output is typically suitable for subsequent display by
standard video equipment or JPEG/MPEG compression.
Colorpipe data (pre-lens correction and overlay) can also
be output in YCbCr 4:2:2 and a variety of RGB formats in
640 by 480 progressive format in conjunction with
LINE_VALID and FRAME_VALID.
The ASX340AT can be configured to output 16-bit RGB
(565RGB), 15-bit RGB (555RGB), and two types of 12-bit
RGB (444RGB). Refer to Table 23 and Table 24 for details.
Bayer Output:
Unprocessed Bayer data are generated when bypassing
the IFP completely−that is, by simply outputting the sensor
Bayer stream as usual, using FRAME_VALID,
LINE_VALID, and PIXCLK to time the data. This mode is
called sensor bypass mode.
Zoom Support
The ASX340AT supports zoom x1 and x2 modes, in
interlaced and progressive scan modes. The progressive
support is limited to the VGA at either 60 fps or 50 fps.
In the zoom x2 modes, the sensor is configured for QVGA
(320 x 240), and the zoom x2 window can be configured to
pan around the VGA window.
FOV Stretch Support
The ASX340AT supports the ability to control the active
“width” of the TV output line, between 692 and 720 pixels.
The hardware supports two margins, each a maximum of 14
pixels width, and has to be an even number of pixels.
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17
ASX340AT
SYSTEM CONFIGURATION AND USAGE MODES
How a camera based on the ASX340AT will be
configured depends on what features are used. There are
essentially three configuration modes for ASX340AT:
Auto-Config Mode, Flash-Config Mode, and Host-Config
Mode. Refer to System Configuration and Usage
Serial
EEPROM/Flash
ASX340AT
SPI
ASX340AT
External device
Auto-Config Mode
Analog Out
Figure 14.
Digital Out
ASX340AT
ASX340AT
8/16 bit ∝C
Figure 12.
System
Bus
Serial
EEPROM/Flash
Two−wire
Serial
EEPROM/Flash
SPI
Figure 15.
SPI
8/16 bit ∝C
Figure 13.
System Bus
ASX340AT
Two−wire
Figure 16.
MULTICAMERA SUPPORT
Two or more ASX340AT sensors may be synchronized to
a frame by asserting the FRAME_SYNC signal. At that
point, the sensor and video encoder will reset without
affecting any register settings. The ASX340AT may be
triggered to be synchronized with another ASX340AT or an
external event.
Decoder/DSP
Dual Camera
CVBS
ASX340
OSC
Camera 1
F_SYNC
CVBS
ASX340
F_SYNC
1
System Bus
mC
Figure 17. Multicamera System Block Diagram
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18
Camera 2
ASX340AT
EXTERNAL SIGNAL PROCESSING
An external signal processor can take data from ITU656
or raw Bayer output format and post-process or compress
the data in various formats.
27 MHz
EXTCLK
SPI
1KB to 16MB
VIDEO_P
VIDEO_N
Signal processor
D
Figure 18. External Signal Processing Block Diagram
Device Configuration
• If a device is detected, the firmware switches to the
After power is applied and the device is out of reset by
de-asserting the RESET_BAR pin, it will enter a boot
sequence to configure its operating mode. There are
essentially
three
three
configuration
modes:
Flash/EEPROM Config, Auto Config, and Host Config.
Figure 14: “Power-Up Sequence – Configuration Options
Flow Chart,” contains more details on the configuration
options.
The SOC firmware supports a System Configuration
phase at start-up. This consists of five modes of execution:
1. Flash Detection
2. Flash-Config
3. Auto-Config
4. Host-Config
5. Change-Config (commences streaming −
completes the System Configuration mode).
Flash-Config mode.
In the Flash-Config phase, the firmware interrogates the
device to determine if it contains valid configuration
records:
• If no records are detected, then the firmware enters the
Auto-Config mode.
• If records are detected, the firmware processes them.
By default, when all Flash records are processed the
firmware switches to the Host-Config mode. However,
the records encoded into the Flash can optionally be
used to instruct the firmware to proceed to one of the
other mode (auto-config/change-config).
The Auto-Config mode uses the FRAME_VALID,
LINE_VALID, DOUT_LSB0 and DOUT_LSB1 pins to
configure the operation of the device, such as video format
and pedestal (refer to the Developer Guide for more details).
After Auto-Config completes the firmware switches to the
Change-Config mode.
In the Host-Config mode, the firmware performs no
configuration, and remains idle waiting for configuration
and commands from the host. The System Configuration
phase is effectively complete and the SOC will take no
actions until the host issues commands.
In the Change-Config mode, the firmware performs a
“Change-Config” operation. This applies the current
configuration settings to the SOC, and commences
streaming. This completes the System Configuration phase.
The System Configuration phase is entered immediately
after the firmware initializes following SOC power-up or
reset. By default, the firmware first enters the Flash
Detection mode.
The Flash Detection mode attempts to detect the presence
of an SPI Flash or EEPROM device:
• If no device is detected, the firmware then samples the
SPI_SDI pin state to determine the next mode:
− If SPI_SDI = 0 then it enters the Host-Config
mode.
− If SPI_SDI = 1 then it enters the Auto-Config
mode.
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ASX340AT
Power Sequence
In power-up, refer to the power-up sequence in Figure 44:
“Power Up Sequence.”
In power down, refer to Figure 45: “Power Down
Sequence”, for details.Modes in the Developer Guide
document for details.
Power Up/RESET
yes
EEPROM/Flash
device present?
no
yes
EEPROM/Flash
contents valid?
no
SPI_SDI = 0?
Parse
EEPROM/Flash
Content
no
Disable Auto−Config
Auto Configuration
FRAME_ VALID
LINE_VALID
D_LSB0
OUT
DOUT_LSB1
(optional)
:
Auto−Config
Change−Config
(default)
Auto−Config
Wait for Host
Command
Host Config
Wait for Host
Command
Change Config
Change−Config
Wait for Host
Command
Figure 19. Power-Up Sequence – Configuration Options Flow Chart
Supported NVM Devices
The ASX340AT supports a variety of SPI non-volatile
memory (NVM) devices. Refer to Flash/EEPROM
Programming section in Developer Guide document for
details.
TABLE 13. SPI FLASH DEVICES
Type
Density
Manufacturer
Device
Speed
(MHz)
Temp Range
(5C)
Supported
Flash
1 MB
ST
M25P10−AVMB3
50
–40 to +125
Yes
Flash
8 MB
Atmel
AT26DF081A
70
–20 to +85
Yes
EEPROM
1 MB
ST
M95M01−R
5
–40 to +130
Yes
EEPROM
8 KB
Microchip
25LC080
2
–40 to +125
Yes
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20
Standard
JEDEC/Device ID
ASX340AT
TABLE 14. SPI COMMANDS SUPPORTED
Command
Value
Read Array
0x03
Block Erase
0 x D8
Chip Erase
0 x C7
Read Status
0 x 05
Write status
0 x 01
Byte Page Program
0 x 02
Write Enable
0 x 06
Write Disable
0 x 04
Read Manufacturer and Device ID
0 x 9F
(Fast) Read Array
0 x 0B
TABLE 15. GPIO BIT DESCRIPTIONS
GPIO[9]
(FRAME_VALID
GPI[8] (LINE_VALI
NTSC
Normal
No pedestal
PAL
Horizontal mirror
Pedestal
GPIO[11] (DOUT_LSB1)
GPIO[10] (DOUT_LSB0)
Low (“0”)
Normal
High (“1”)
Vertical Flip
Host Command Interface
reported back. In general, registers should not be accessed
with the exception of registers that are marked for “User
Access.”
EEPROM or Flash memory is also available to store
commands for later execution. Under DMA control, a
command is written into the SOC and executed.
For a complete description of host commands, refer to the
ASX340AT Host Command Interface Specification.
ON Semiconductor sensors and SOCs contain numerous
registers that are accessed through a two-wire interface with
speeds up to 400 kHz.
The ASX340AT in addition to writing or reading straight
to/from registers or firmware variables, has a mechanism to
write higher level commands, the Host Command Interface
(HCI). Once a command has been written through the HCI,
it will be executed by on-chip firmware and the results are
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21
ASX340AT
bit
Addr 0x40
15
1
0
14
0
Host Command to FW
Response from FW
command register
door bell
bit
Addr 0xFC00
15
0
Parameter 0
cmd_handler_params_pool_0
Addr 0xFC02
cmd_handler_params_pool_1
Addr 0xFC04
cmd_handler_params_pool_2
Addr 0xFC06
cmd_handler_params_pool_3
Addr 0xFC08
cmd_handler_params_pool_4
Addr 0xFC0A
cmd_handler_params_pool_5
Addr 0xFC0C
cmd_handler_params_pool_6
Addr 0xFC0E
Parameter 7
Figure 20. Interface Structure
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22
cmd_handler_params_pool_7
ASX340AT
Host Command Process Flow
Issue
Command
Wait for a
response?
Host could insert an
optional delay here
Yes
Read Command
register
Host could insert an
optional delay here
No
Read Command
register
No
Doorbell
bit clear ?
Yes
At this point
Command Register
contains response code
Command has
parameters ?
Doorbell bit
clear?
Yes
Command
has response
parameters ?
Yes
No
No
Write parameters
to
Parameter Pool
No
Yes
Read response
parameters from
Parameter Pool
Write command
to
Command register
Done
Figure 21. Interface Structure
COMMAND FLOW
The host issues a command by writing (through a
two-wire interface bus) to the command register. All
commands are encoded with bit 15 set, which automatically
generates the host command (doorbell) interrupt to the
microprocessor.
Assuming initial conditions, the host first writes the
command parameters (if any) to the parameters pool (in the
command handler’s logical page), then writes the command
to command register. The firmware interrupt handler then
signals the Command Handler task to process the command.
If the host wishes to determine the outcome of the
command, it must poll the command register waiting for the
doorbell bit to be cleared. This indicates that the firmware
completed processing the command. When the doorbell bit
is cleared, the contents of the command register indicate the
command’s result status. If the command generated
response parameters, the host can now retrieve these from
the parameters pool.
NOTES: The host must not write to the parameters pool,
nor issue another command, until the previous
command completes. This is true even if the
host does not care about the result of the
previous command. Therefore, the host must
always poll the command register to determine
the state of the doorbell bit, and ensure the bit is
cleared before issuing a command.
For a complete command list and further information
consult the Host Command Interface Specification.
An example of how (using DevWare) a command may be
initiated in the form of a “Preset” follows.
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23
ASX340AT
Issue the SYSMGR_SET_STATE Command
All DevWare presets supplied by ON Semiconductor poll
and test the doorbell bit after issuing the command.
Therefore there is no need to check if the doorbell bit is clear
before issuing the next command.
# Set the desired next state in the parameters pool(SYS_STATE_ENTER_CONFIG_CHANGE)
REG= 0xFC00, 0x2800 // CMD_HANDLER_PARAMS_POOL_0
# Issue the HC_SYSMGR_SET_STATE command
REG= 0x0040, 0x8100 // COMMAND_REGISTER
# Wait for the FW to complete the command (clear the Doorbell bit)
POLL_FIELD= COMMAND_REGISTER, DOORBELL,!=0, DELAY=10, TIMEOUT=100
# Check the command was successful
ERROR_IF= COMMAND_REGISTER, HOST_COMMAND,!=0, ”Set State command failed”,
Summary of Host Commands
Table13 through Table 21 show summaries of the host
commands. The commands are divided into the following
sections:
• System Manager
• Overlay
• GPIO
• Flash Manager
• Sequencer
• Patch Loader
• Miscellaneous
• Calibration Stats
Following is a summary of the Host Interface commands.
The description gives a quick orientation. The “Type”
column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including
parameters, consult the Host Command Interface
Specification document.
TABLE 16. SYSTEM MANAGER COMMANDS
System Manager
Host Command
Value
Type
Description
Set State
0x8100
Synchronous
Request the system enter a new state
Get State
0x8101
Synchronous
Get the current state of the system
TABLE 17. OVERLAY HOST COMMANDS
Overlay Host
Command
Value
Type
Enable Overlay
0x8200
Synchronous
Enable or disable the overlay subsystem
Get Overlay State
0x8201
Synchronous
Retrieve the state of the overlay subsystem
Set Calibration
0x8202
Synchronous
Set the calibration offset
Set Bitmap Property
0x8203
Synchronous
Set a property of a bitmap
Get Bitmap Property
0x8204
Synchronous
Get a property of a bitmap
Set String Property
0x8205
Synchronous
Set a property of a character string
Load Buffer
0x8206
Asynchronous
Load an overlay buffer with a bitmap (from Flash)
Load Status
0x8207
Synchronous
Retrieve status of an active load buffer operation
Write Buffer
0x8208
Synchronous
Write directly to an overlay buffer
Read Buffer
0x8209
Synchronous
Read directly from an overlay buffer
Enable Layer
0x820A
Synchronous
Enable or disable an overlay layer
Get Layer Status
0x820B
Synchronous
Retrieve the status of an overlay layer
Set String
0x820C
Synchronous
Set the character string
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Description
ASX340AT
TABLE 17. OVERLAY HOST COMMANDS (CONTINUED)
Overlay Host
Command
Value
Type
Description
Get String
0x820D
Synchronous
Get the current character string
Load String
0x820E
Asynchronous
Load a character string (from Flash)
TABLE 18. GPIO HOST COMMANDS
GPIO Host Command
Value
Type
Description
Set GPIO Property
0x8400
Synchronous
Set a property of one or more GPIO pins
Get GPIO Property
0x8401
Synchronous
Retrieve a property of a GPIO pin
Set GPO State
0x8402
Synchronous
Set the state of a GPO pin or pins
Get GPIO State
0x8403
Synchronous
Get the state of a GPI pin or pins
Set GPI Association
0x8404
Synchronous
Associate a GPI pin state with a Command
Sequence stored in SPI Flash
Get GPI Association
0x8405
Synchronous
Retrieve an GPIO pin association
TABLE 19. FLASH MANAGER HOST COMMANDS
Flash Manager
Host Command
Value
Type
Description
Get Lock
0x8500
Asynchronous
Request the Flash Manager access lock
Lock Status
0x8501
Synchronous
Retrieve the status of the access lock request
Release Lock
0x8502
Synchronous
Release the Flash Manager access lock
Config
0x8503
Synchronous
Configure the Flash Manager and underlying SPI
Flash subsystem
Read
0x8504
Asynchronous
Read data from the SPI Flash
Write
0x8505
Asynchronous
Write data to the SPI Flash
Erase Block
0x8506
Asynchronous
Erase a block of data from the SPI Flash
Erase Device
0x8507
Asynchronous
Erase the SPI Flash device
Query Device
0x8508
Asynchronous
Query device-specific information
Status
0x8509
Synchronous
Obtain status of current asynchronous operation
Config Device
0x850A
Synchronous
Configure the attached SPI NVM device
TABLE 20. SEQUENCER HOST COMMANDS
Flash Manager
Host Command
Value
Type
Refresh
0x8606
Synchronous
Refresh the automatic image processing algorithm
configuration
Refresh Status
0x8607
Synchronous
Retrieve the status of the last Refresh operation
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Description
ASX340AT
TABLE 21. PATCH LOADER HOST COMMANDS
Patch Loader Host
Command
Value
Type
Description
Load Patch
0x8700
Asynchronous
Load a patch from SPI Flash and automatically
apply
Status
0x8701
Synchronous
Get status of an active Load Patch or Apply Patch
request
Apply Patch
0x8702
Asynchronous
Apply a patch (already located in Patch RAM)
Reserve RAM
0x8706
Synchronous
Reserve RAM to contain a patch
TABLE 22. MISCELLANEOUS HOST COMMANDS
Miscellaneous Host
Command
Value
Type
Description
Invoke Command Seq
0x8900
Synchronous
Invoke a sequence of commands stored in NVM
Config Command Seq
Processor
0x8901
Synchronous
Configures the Command Sequencer processor
Wait For Event
0x8902
Synchronous
Wait for a system event to be signalled
TABLE 23. CALIBRATION STATS HOST COMMANDS
Calibration Stats Host
Command
Value
Type
Control
0x8B00
Asynchronous
Start statistics gathering
Read
0x8B01
Synchronous
Read the results back
SLAVE TWO-WIRE SERIAL INTERFACE
The two-wire serial interface bus enables read/write
access to control and status registers within the ASX340AT.
This interface is designed to be compatible with the MIPI
Alliance Standard for Camera Serial Interface 2 (CSI-2) 1.0,
which uses the electrical characteristics and transfer
protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (SCLK) that
is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a
bidirectional signal (SDATA). SDATA is pulled up to VDD_IO
off-chip by a pull-up resistor in the range of 1.5 to 4.7 kΩ.
Description
The bus is idle when both SCLK and SDATA are HIGH.
Control of the bus is initiated with a start condition, and the
bus is released with a stop condition. Only the master can
generate the start and stop conditions.
The SADDR pin is used to select between two different
addresses in case of conflict with another device. If SADDR
is LOW, the slave address is 0 x 90; if SADDR is HIGH, the
slave address is 0 x BA. See Table 21.
TABLE 24. TWO-WIRE INTERFACE ID ADDRESS
SWITCHING
Protocol
Data transfers on the two-wire serial interface bus are
performed by a sequence of low-level protocol elements, as
follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
• data bytes
• a stop condition
SADDR
Two-Wire Interface Address ID
0
0x90
1
0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition
on SDATA while SCLK is HIGH. At the end of a transfer, the
master can generate a start condition without previously
generating a stop condition; this is known as a “repeated
start” or “restart” condition.
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26
ASX340AT
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB
transmitted first. Each byte of data is followed by an
acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte
and for message bytes.
One data bit is transferred during each SCLK clock period.
SDATA can change when SCLK is low and must be stable
while SCLK is HIGH.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition
on SDATA while SCLK is HIGH.
Typical Operation
A typical READ or WRITE sequence begins by the
master generating a start condition on the bus. After the start
condition, the master sends the 8-bit slave address/data
direction byte. The last bit indicates whether the request is
for a READ or a WRITE, where a “0” indicates a WRITE
and a “1” indicates a READ. If the address matches the
address of the slave device, the slave device acknowledges
receipt of the address by generating an acknowledge bit on
the bus.
If the request was a WRITE, the master then transfers the
16-bit register address to which a WRITE will take place.
This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate
that the byte has been received. The master will then transfer
the 16-bit data, as two 8-bit sequences and the slave sends an
acknowledge bit after each sequence to indicate that the byte
has been received. The master stops writing by generating
a (re)start or stop condition. If the request was a READ, the
master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The
master then generates a (re)start condition and the 8-bit read
slave address/data direction byte, and clocks out the register
data, 8 bits at a time. The master generates an acknowledge
bit after each 8-bit transfer. The data transfer is stopped
when the master sends a no-acknowledge bit.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address
and bit [0] indicates the data transfer direction. A “0” in bit
[0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the ASX340AT are 0 x 90 (write
address) and 0 x 91 (read address). Alternate slave addresses
of 0 x BA (write address) and 0 x BB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and
register write data to the slave device and for retrieving
register read data. The protocol used is outside the scope of
the two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit
or a no-acknowledge bit in the SCLK clock period following
the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The
receiver indicates an acknowledge bit by driving SDATA
LOW. As for data transfers, SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
Single READ from Random Location
Figure 17 shows the typical READ cycle of the host to the
ASX340AT. The first two bytes sent by the host are an
internal 16-bit register address. The following 2-byte READ
cycle sends the contents of the registers to host.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver
does not drive SDATA low during the SCLK clock period
following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Previous Reg Address, N
S
Slave Address
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
0 A
Reg Address[15:8]
A
M+1
Reg Address, M
Reg Address[7:0]
A
Sr
Slave Address
slave to master
master to slave
Figure 22. Single READ from Random Location
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27
1 A
Read Data
[15:8]
A
Read Data
[7:0]
A
P
ASX340AT
Single READ from Current Location
Figure 18 shows the single READ cycle without writing
the address. The internal address will use the previous
address value written to the register.
Previous Reg Address, N
S
Slave Address
1
Reg Address, N+1
Read Data
A
[15:8]
A
Read Data
A
[7:0]
P
S
N+2
Slave Address
Read Data
1 A
A
[15:8]
Read Data
A
[7:0]
P
Figure 23. Single READ from Current Location
Sequential READ, Start from Random Location
This sequence (Figure 21) starts in the same way as the
single READ from random location (Figure 17). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte READs until “L” bytes
have been read.
Previous Reg Address, N
S
Slave Address
0
A
Reg Address[15:8]
M+1
Read Data
A
(15:8)
Reg Address, M
M+2
Read Data
A
(7:0)
Read Data
A
(15:8)
Reg Address[7:0]
A
A
Sr
Slave Address
1
M+L−2
M+3
Read Data
(15:8)
Read Data
A
(7:0)
A
M+1
A
M+L−1
Read Data
(7:0)
Read Data
(15:8)
A
A
A
Read Data
M+L
Read Data A
(7:0)
P
Figure 24. Sequential READ, Start from Random Location
Sequential READ, Start from Current Location
This sequence (Figure 20) starts in the same way as the
single READ from current location (Figure 18). Instead of
generating a no-acknowledge bit after the first byte of data
Previous Reg Address, N
S
Slave Address
1
A
has been transferred, the master generates an acknowledge
bit and continues to perform byte reads until “L” bytes have
been read.
N+1
Read Data
Read Data
A
(15:8)Read AData (7:0)
Read Data
(15:8)
N+2
Read Data
A
(7:0)
A
Read Data
A
(15:8)
N+L−1
Read Data
A
A
(7:0)
N+L
Read Data
Read Data
A
A
(15:8)
(7:0)
P
Read Data
Figure 25. Sequential READ, Start from Current Location
of the internal registers with most−significant byte first. The
following 2 bytes indicate the 16−bit data.
Single Write to Random Location
Figure 21 shows the typical WRITE cycle from the host
to the ASX340AT.The first 2 bytes indicate a 16−bit address
Previous Reg
S
Slave Address
Address, N
Reg
Address, M
M+1
A
0
A
Reg Address[15:8]
Reg Add ress[7:0]
A
Figure 26. Single WRITE to Random Location
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28
A
Wri te Data
A
P
ASX340AT
Sequential WRITE, Start at Random Location
This sequence (Figure 22) starts in the same way as the
single WRITE to random location (Figure 21). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte writes until “L” bytes have
been written. The WRITE is terminated by the master
generating a stop condition.
Previous Reg Address, N
S
Slave Address
0
A
M+1
Write Data
(15:8)
A
Reg Address[15:8]
Reg Address, M
M+2
Write Data
A
(7:0)
Write Data
(15:8)
A
Reg Address[7:0]
A
M+L−2
M+3
Write Data
(7:0)
A
A
M+1
Write Data
A
M+L−1
Write Data
Write Data
Write Data
A
Write Data
AA Data(15:8)
(15:8)
(7:0) Write
AA
A
M+L
Write Data
(7:0)
A
A
P
Write Data
Figure 27. Single WRITE to Random Location
OVERLAY CAPABILITY
Figure 23 highlights the graphical overlay data flow of
theASX340AT. The images are separated to fit into 2 KB
blocks of memory after compression.
• Up to four overlays may be blended simultaneously
• Overlay size 360 x 480 pixels rendered into a display
area of 720 x 480 pixels (NTSC) or 720 x 576 (PAL)
• Selectable readout: rotating order is user programmable
• Dynamic movement through predefined overlay images
• Palette of 32 colors out of 64,000 with eight colors per
bitmap
• Blend factors may be changed dynamically to achieve
smooth transitions
The host commands allow a bitmap to be written
piecemeal to a memory buffer through the two-wire serial
interface, and also through DMA direct from SPI Flash
memory. Multiple encoding passes may be required to fit an
image into a 2 KB block of memory; alternatively, the image
can be divided into two or more blocks to make the image
fit. Every graphic image may be positioned in the horizontal
and vertical direction and overlap with other graphic
images.
The host may load an image at any time. Under control of
DMA assist, data are transferred to the off-screen buffer in
compressed form. This assures that no display data are
corrupted during the replenishment of the four active
overlay buffers.
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29
ASX340AT
Overlay buffers: 2KB each
Flash
Decompress
Blend and Overlay
Bitmaps − compressed
NOTE:
Off-screen
buffer
These images are not actually rendered, but show conceptual objects and object blending.
Figure 28. Overlay Data Flow
NVM PARTITION
The contents of the Flash/EEPROM memory partition
logically into three blocks (see Figure 24):
• Memory for overlay data and descriptors
• Memory for register settings, which may be loaded at
boot-up
Flash
Partitioning
• Firmware extensions or software patches; in addition to
the on-chip firmware, extensions reside in this block of
memory
These blocks are not necessarily contiguous.
Fixed−size
Overlays − RLE
E
Fixed−size
Overlays − RLE
12−byte
1 2 ByteHeader
Head er
Overlay
Overlay Data
Data
RLE
R
L EEncoded
Enc o d ed
Data
2KB
k Byte
Lens Shading
Correction
Parameter
Alternate
Alternate
Reg.
Register Setting
S/W Patch
Software Patch
Figure 29. Memory Partitioning
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30
E
ASX340AT
External Memory Speed Requirement
For a 2 KB block of overlay to be transferred within a
frame time to achieve maximum update rate, the SPI NVM
must operate at a certain minimum speed.
TABLE 25. TRANSFER TIME ESTIMATE
Value
Type
Description
33.3ms
4.5 MHz
1ms
OVERLAY ADJUSTMENT
To ensure a correct position of the overlay to compensate
for assembly deviation, the overlay can be adjusted with
assistance from the overlay statistics engine:
• The overlay statistics engine supports a windowed
8-bin luma histogram, either row-wise (vertical) or
column-wise (horizontal).
• The calibration statistics can be used to perform an
automatic successive-approximation search of a
cross-hair target within the scene.
• On the first frame, the firmware performs a coarse
horizontal search, followed by a coarse vertical search
in the second frame.
• In subsequent frames, the firmware reduces the
•
•
region-of-interest of the search to the histogram bins
containing the greatest accumulator values, thereby
refining the search.
The resultant row and column location of the cross-hair
target can be used to assign a calibration value to offset
selected overlay graphic image positions within the
output image.
The calibration statistics patch also supports a manual
mode, which allows the host to access the raw
accumulator values directly.
Figure 30. Overlay Calibration
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31
ASX340AT
The position of the target will be used to determine the
calibration value that shifts the row and column position of
adjustable overlay graphics.
The overlay calibration is intended to be applied on a
device by device basis “in system,” which means after the
camera has been installed. ON Semiconductor provides
basic programming scripts that may reside in the SPI Flash
memory to assist in this effort.
OVERLAY CHARACTER GENERATOR
In addition to the four overlay layers, a fifth layer exists
for a character generator overlay string.
There are a total of:
• 16 alphanumeric characters available
• 22 characters maximum per line
• 16 x 32 pixels with 1-bit color depth
Any update to the character generator string requires the
string to be passed in its entirety with the Host Command.
Character strings have their own control properties aside
from the Overlay bitmap properties.
BT656
Overlay
Layer3
Register Bus
Layer2
User Registers
Data Bus
DMA/CPU
Layer1
Layer0
Timing control
ROM
BT656
Figure 31. Internal Block Diagram Overlay
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32
ASX340AT
Character Generator
The character generator can be seen as the fifth top layer,
but instead of getting the source from RLE data in the
memory buffers, it has 16 predefined characters stored in
ROM.
ROM 15
0
0x00
0
0x02
0
0x04
0
0x06
0
0x08
0
0x0a
0
0x0c
0
0x0e
0
0x10
0
0x12
0
0x14
0
0x16
0
0x18
0
0x1a
0
0x1c
0
0x1e
0
0x20
0x22
0
0
0x24
0
0x26
0
0x28
0
0x2a
0
0x2c
0
0x2e
0
0x30
0
0x32
0
0x34
0
0x36
0
0x38
0
0x3a
0
0x3c
0
0x3e
…
All the characters are 1-bit depth color and are sharing the
same YCbCr look up table.
14
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
13
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
12
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
10
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
9
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4 3
0 0
0 0
0 0
0 0
1 0
1 1
1 1
1 1
1 1
1 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 1
1 1
1 1
1 1
2
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 32. Example of Character Descriptor 0 Stored in ROM
It can show a row of up to 22 characters of 16 x 32 pixels
resolution (32 x 32 pixels when blended with the BT 656
data).
Character Generator Details
TABLE 26. CHARACTER GENERATOR DETAILS
Item
Quantity
Description
16-bit character
22
Code for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, –, (comma), (period)
1 bpp color
1
Depth of the bit map is 1 bpp
NOTES: No error is generated if the character row
overruns the horizontal or vertical limits of the
frame.
It is the responsibility of the user to set up proper values
in the character positioning to fit them in the same row (that
is one of the reasons that 22 is the maximum number of
characters).
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33
ASX340AT
Full Character Set for Overlay
Figure 28 shows all of the characters that can be generated
by the ASX340AT.
0x0 0x4 0x8 0xC
0x1 0x5 0x9 0xD
0x2 0x6 0xA 0xE
0x3 0x7 0xB 0xF
Figure 33. Full Character Set for Overlay
MODES AND TIMING
This section provides an overview of the typical usage
modes and related timing information for the ASX340AT.
PAL
The PAL format is supported with 576 active image rows.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or
differential mode by simply changing the external resistor
configuration. Refer to the Developer Guide for
configuration options.
Composite Video Output
The external pin DOUT_LSB0 can be used to configure the
device for default NTSC or PAL operation (auto-config
mode). This and other video configuration settings are
available as register settings accessible through the serial
interface.
Parallel Output (DOUT)
The DOUT[7:0] port supports both progressive and
Interlaced mode. Progressive mode (with FV and LV signal)
include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced
mode is CCIR656 compliant.
Figure 29 shows the data that is output on the parallel port
for CCIR656. Both NTSC and PAL formats are displayed.
The blue values in Figure 29 represent NTSC (525/60). The
red values represent PAL (625/50).
NTSC
Both differential and single-ended connections of the full
NTSC format are supported. The differential connection
that uses two output lines is used for low noise or long
distance applications. The single-ended connection is used
for PCB tracks and screened cable where noise is not a
concern. The NTSC format has three black lines at the
bottom of each image for padding (which most LCDs do not
display).
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34
ASX340AT
Start of digital line
Start of digital active line
EAV CODE
F
F
0
0
0
0
X
Y
BLANKING
8
0
1
0
8
0
8
0
1
0
F
F
0
0
268
280
4
4
_
CO
_ −
CO − SITED SITED
SAV CODE
1
0
0
0
X
Y
C
B
N
C
R
Y
4
4
Y
C
B
Y
C
R
Y
C
R
Y
F
F
Digital
video
stream
1440
1440
Figure 34. CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems
Figure 30 shows detailed vertical blanking information
for NTSC timing. Table 24 for data on field, vertical
blanking, EAV, and SAV states.
Line 4
Line 1 (V = 1)
Blanking
Field 1
(F = 0)
Odd
Line 20 (V = 0)
Field 1 Active Vi deo
266
Line 26 4 (V =1)
Field 2
(F = 1)
Even
Blanking
Line 2 83 (V = 0)
Field 2 Active Vi
deo
Line 525 (V = 0)
H=1
EAV
H=0
SAV
Figure 35. Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System
TABLE 27. FIELD, VERTICAL BLANKING, EAV, AND SAV STATES 525/60 VIDEO SYSTEM
Line Number
F
V
H (EAV)
H (SAV)
1–3
1
1
1
0
4–9
0
1
1
0
20–263
0
0
1
0
264–265
0
1
1
0
266–282
1
1
1
0
283–525
1
0
1
0
1. NTSC defines active video from line 20 to line 263 (corresponding to a field). This allows up to 244 active video lines in a field.
2. ASX340 image output is configured to 240 lines per field; this is common practice of digital video formatting.
3. When 240 lines are displayed within a field of 244 lines, the image content should start from line 22 to line 261 of the field. This ensures center
of the image and the center of the field is aligned.
4. Similar consideration applies to Odd & Even fields.
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35
ASX340AT
Figure 31 shows detailed vertical blanking information
for PAL timing. See Table 25 for data on field, vertical
blanking, EAV, and SAV states.
Line 1 (V = 1)
Blanking
Line 2 3 (V = 0)
Field 1
(F = 0)
Odd
Field 1 Active Video
Line 311 (V = 1)
Blanking
Line 336 (V = 0)
Field 2
(F =
n
Field 2 Active Vi
deo
Line 62 4 (V = 1)
Blanking
Line 625 (V = 1)
H =
H=
Figure 36. Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
TABLE 28. FIELD, VERTICAL BLANKING, EAV, AND SAV STATES FOR 625/50 VIDEO SYSTEM
Line Number
F
V
H (EAV)
H (SAV)
1–22
0
1
1
0
23–310
0
0
1
0
311–312
0
1
1
0
313–335
1
1
1
0
336–623
1
0
1
0
624–625
1
1
1
0
Reset and Clocks
Reset
Power-up reset is asserted or de-asserted with the
RESET_BAR pin, which is active LOW. In the reset state,
all control registers are set to default values. See “Device
Configuration” for more details on Auto, Host, and Flash
configurations.
Soft reset is asserted or de-asserted by the two-wire serial
interface. In soft-reset mode, the two-wire serial interface
and the register bus are still running. All control registers are
reset using default values.
• In default mode, a pixel clock (PIXCLK) running at
2 * EXTCLK. In raw Bayer bypass mode, PIXCLK
runs at the same frequency as EXTCLK.
When the ASX340AT operates in raw Bayer bypass
mode, the image flow pipeline clocks can be shut off to
conserve power.
The sensor core is a master in the system. The sensor core
frame rate defines the overall image flow pipeline frame
rate. Horizontal blanking and vertical blanking are
influenced by the sensor configuration, and are also a
function of certain image flow pipeline functions. The
relationship of the primary clocks is depicted in Figure 32.
Clocks
The ASX340AT has two primary clocks:
• A master clock coming from the EXTCLK signal.
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36
ASX340AT
The image flow pipeline typically generates up to 16 bits
per pixel − for example, YCbCr or 565RGB − but has only
an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core
requires a 27 MHz clock.
Sensor
Master Clock
EXTCLK
Sensor Core
Sensor
Pixel Clock
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
Figure 37. Primary Clock Relationships
Floating Inputs
•
•
•
•
The following ASX340AT pins cannot be floated:
• SDATA–This pin is bidirectional and should not be
floated
• FRAME_SYNC
• TRST_N
SCLK
SADDR
ATEST1
ATEST2
Output Data Ordering
TABLE 29. EIA COLOR BARS (NTSC)
Mode
(Swap Disabled)
565RGB
555RGB
444xRGB
x444RGB
Byte
D7
D6
D5
D4
D3
D2
D1
D0
First
R7
R6
R5
R4
R3
G7
G6
G5
Second
G4
G3
G2
B7
B6
B5
B4
B3
First
0
R7
R6
R5
R4
R3
G7
G6
Second
G5
G4
G3
B7
B6
B5
B4
B3
First
R7
R6
R5
R4
G7
G6
G5
G4
Second
B7
B6
B5
B4
0
0
0
0
First
0
0
0
0
R7
R6
R5
R4
Second
G7
G6
G5
G4
B7
B6
B5
B4
1. PIXCLK is 54 MHz when EXTCLK is 27 MHz.
TABLE 30. EIA COLOR BARS (NTSC)
Mode
10-bit Output
D7
D6
D5
D4
D3
D2
D1
D0
DOUT_LSB1
DOUT_LSB0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1. PIXCLK is 27 MHz when EXTCLK is 27 MHz.
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37
ASX340AT
I/O Circuitry
Figure 33 illustrates typical circuitry used for each input,
output, or I/O pad.
VDD
_IO
Input Pad
Pad
Receiver
GND
VDD_IO
SPI_SDI and RESET_BAR
Input Pad
Receiver
Pad
GND
VDD_IO
Receiver
I/O Pad
Pad
Slew
Rate
Control
GND
VDD_IO
SCLK and XTAL_IN
Input Pad
Pad
Receiver
GND
DD_IO
XTAL
Output Pad
GND
NOTE:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
Figure 38. Typical I/O Equivalent Circuits
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38
ASX340AT
NTSC Block
VDD_DAC
DAC_REF
Pad
ESD
Pad
DAC_POS
Pad
DAC_NEG
ESD
Resistor
2.35 kW
ESD
GND
NOTE:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
Figure 39. NTSC Block
VDD_I0
SDATA
Input/output
Pad
Pad
Receiver
Transmitter
GND
Figure 40. Serial interface
I/O Timing
Digital Output
By default, the ASX340AT launches pixel data, FV, and
LV synchronously with the falling edge of PIXCLK. The
expectation is that the user captures data, FV, and LV using
the rising edge of PIXCLK. The timing diagram is shown in.
As an option, the polarity of the PIXCLK can be inverted
from the default by programming R0x0016[14].
t
Input
EXTCLK
Output
PIXCLK
Output
t
DOUT [7:0]
FRAME_VALID
LINE_VALID
dout_ho
t
t
Output
t
pixclkf_dout
dout_su
pixclkf_fvlv
t
fvlv_su
Figure 41. Digital Output I/O Timing
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39
extclk_period
t
fvlv_ho
ASX340AT
TABLE 31. PARALLEL DIGITAL OUTPUT I/O TIMING
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; Default slew rate)
Signal
Parameter
Min
Typ
Max
Unit
fextclk
6
27
54
MHz
textclk_period
18.52
37
166.67
ns
EXTCLK
Duty cycle
45
50
55
%
PIXCLK1
fpixclk
6
27
54
MHz
tpixclk_period
18.52
37.04
166.67
ns
Duty cycle
45
50
55
%
tpixclkf_dout
1.55
–
1.9
ns
tdout_su
18
–
20
ns
tdout_ho
18
–
20
ns
tpixclkf_fvlv
1.6
–
3.05
ns
tfvlv_su
15
–
16
ns
tfvlv_ho
20
–
21
ns
EXTCLK
DATA[7:0]
FV/LV
Conditions
TABLE 32. SLEW RATE FOR POXCLK AND DOUT
(fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; T = 25°C; CLOAD = 40 pF)
PIXCLK
DOUT[7:0]
R0x1E [10:8]
Rise Time
Fall Time
R0x1E [2:0]
Rise Time
Fall Time
Unit
000
NA
NA
000
15.0
13.5
ns
001
NA
NA
001
9.0
8.5
ns
010
7.0
6.9
010
6.8
6.0
ns
011
5.2
5.0
011
5.2
4.8
ns
100
4.0
3.8
100
3.8
3.5
ns
101
3.0
2.8
101
3.3
3.3
ns
110
2.4
2.2
110
3.0
3.0
ns
111
1.9
1.7
111
2.8
2.8
ns
90%
10%
PIXCLK
t rise
t fall
D OUT
t rise
t fall
Figure 42. Slew Rate Timing
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40
ASX340AT
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled.
Setup and hold timing for the RESET_BAR signal with
respect to DOUT_LSB0, LV, and FV are shown in Figure 38
and Table 30. These signals are sampled once by the on-chip
firmware, which yields a long tHOLD time.
RESET_BAR
tSETUP
tHOLD
Valid Data
LINE_VALID
Figure 43. Configuration Timing
TABLE 33. CONFIGURATION TIMING
Signal
Parameter
Min
tSETUP
0
μs
tHOLD
50
μs
DOUT_LSB0, FRAME_VALID,
LINE_VALID
Typ
Max
Units
1. Table data is based on EXTCLK = 27 MHz.
VDD_PLL
VDD_DAC (2.8)
t0
VAA_PIX
VAA (2.8)
t1
V DD_IO (2.8)
t2
VDD (1.8)
EXTCLK
RESET_BAR
t4
t3
Hard Reset
Internal
Initialization
t5
Patch Config
SPI or Host
Streaming
Figure 44. Power Up Sequence
TABLE 34. POWER UP SEQUENCE
Definition
Symbol
Min
Typical
Max
Unit
VDD_PLL to VAA/VAA_PIX
t0
0
–
–
ms
VAA/VAA_PIX to VDD_IO
t1
0
–
–
ms
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41
ASX340AT
TABLE 34. POWER UP SEQUENCE (CONTINUED)
Definition
Symbol
Min
Typical
Max
Unit
VDD_IO to VDD
t2
0
–
–
ms
Hard Reset
t3
2
–
–
ms
Internal Initialization
t4
14
–
–
ms
1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There is no requirement on this from the
sensor.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required for the sensor itself, assuming all
power rails are settled. In a circuit where Hard reset is performed by the RC circuit, then the RC time must include the all power rail settle
time and Xtal.
3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.
VDD (1.8)
t0
VDD_IO (2.8)
t1
V
AA
(2.8)
t2
V
DD_DAC
(2.8)
EXTCLK
t3
Power Down until next Power Up Cycle
Figure 45. Power Down Sequence
TABLE 35. POWER DOWN SEQUENCE
Definition
Symbol
Min
Typical
Max
Unit
VDD to VDD_IO
t0
0
–
–
ms
VDD_IO to VAA/VAA_PIX
t1
0
–
–
ms
VAA/VAA_PIX to VDD_PLL/DAC
t2
0
–
–
ms
t3
1001
–
–
ms
Power Down until Next Power Up Time
(1) t3 is required between power down and next power up
time, all decoupling caps from regulators must completely
discharge before next power up.
tFRAME_SYNC
FRAME_SYNC
FRMSYNH_FVH
t
FRAME_VALID
LINE_VALID
Figure 46. FRAME_SYNC to FRAME_VALID/LINE_VALID
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42
ASX340AT
TABLE 36. FRAME_SYNC TO FRAME_VALID/LINE_VALID PARAMETERS
Parameter
FRAME_SYNC to FV/LV
tFRAME_SYNC
Name
Conditions
Min
Typical
Max
Unit
tFRMSYNC_FVH
Interlaced mode
1.22
–
–
ms
tFRAMESYNC
1
ms
RESET_BAR
tRSTH_CSL
SPI_CS_N
Figure 47. Reset to SPI Access Delay
RESET_BAR
tRSTH_SDATAL
SDATA
Figure 48. Reset to Serial Access Delay
RESET_BAR
VIDEO
First Frame
Overlay from
Flash
tRSTH_FVL
AE/AWB settled
tRSTH_OVL
tRSTH_AEAWB
Figure 49. Reset to AE/AWB Image
TABLE 37. RESET_BAR DELAY PARAMETERS
Parameter
Min
Typical
Max
Unit
tRSTH_CSL
13
–
–
ms
tRSTH_SDATAL
18
–
–
ms
RESET_BAR HIGH to FRAME_VALID
tRSTH_FVL
14
–
–
ms
RESET_BAR HIGH to first Overlay
tRSTH_OVL
Overlay size dependent
–
–
–
ms
tRSTH_AEAWB
Scene dependent
–
–
–
ms
RESET_BAR HIGH to SPI_CS_N LOW
RESET_BAR HIGH to SDATA LOW
RESET_BAR HIGH to AE/AWB settled
Name
Conditions
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43
ASX340AT
TABLE 37. RESET_BAR DELAY PARAMETERS (CONTINUED)
Parameter
Name
RESET_BAR HIGH to first NTSC frame
Min
Typical
Max
Unit
tRSTH_NTSC
47
–
–
ms
tRSTH_PAL
53
–
–
ms
RESET_BAR HIGH to first PAL frame
Conditions
ELECTRICAL SPECIFICATIONS
t CS_SCLK
SPI_CS_N
SPI_SCLK
SPI_SDI
t su
t SCLK_SDO
SPI_SDO
Figure 50. SPI Output Timing
TABLE 38. SPI DATA SETUP AND HOLD TIMING
Parameter
fSPI_SCLK
tSPI_SCLK
tsu
tSCLK_SDO
tCS_SCLK
Name
Conditions
Min
Typical
Max
SPI_SCLK Frequency
1.6875
4.5
18
MHz
SPI_SCLK Period
55.556
592.593
ns
Setup time
0.5 * tSPI_SCLK
ns
Hold time
0.5 * tSPI_SCLK + 20
ns
Delay from falling edge of SPI_CS_N to
rising edge of SPI_SCLK
230
ns
CAUTION: Stresses greater than those listed in Table 37 may
cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at
these or any other conditions above those indicated in
the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TABLE 39. ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Min
Max
Unit
Digital power (1.8 V)
−0.3
2.4
V
I/O power (2.8 V)
−0.3
4
V
VAA
VAA analog power (2.8 V)
−0.3
4
V
VAA_PIX
Pixel array power (2.8 v)
−0.3
4
V
VDD_PLL
PLL power (2.8 V)
−0.3
4
V
VDD_DAC
DAC power (2.8 V)
−0.3
4
V
DC Input Voltage
−0.3
VDD_IO+0.3
V
Symbol
VDD
VDD_IO
VIN
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ASX340AT
TABLE 39. ABSOLUTE MAXIMUM RATINGS (CONTINUED)
Rating
Parameter
Min
Max
Unit
VOUT
DC Output Voltage
−0.3
VDD_IO+0.3
V
TSTG
Storage temperature
−50
150
°C
Symbol
1. “Rating” column gives the maximum and minimum values that the device can tolerate.
TABLE 40. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
Parameter
Condition
Min
Typ
Max
Unit
Core digital voltage (VDD)
–
1.70
1.8
1.95
V
IO digital voltage (VDD_IO)
–
2.66
2.8
2.94
V
Video DAC voltage (VDD_DAC)
–
2.66
2.8
2.94
V
PLL Voltage (VDD_PLL)
–
2.66
2.8
2.94
V
Analog voltage (VAA)
–
2.66
2.8
2.94
V
Pixel supply voltage (VAA_PIX)
–
2.66
2.8
2.94
V
Imager operating temperature2
–
–40
+105
°C
–40
+85
°C
–50
+150
°C
Functional operating
temperature3
Storage temperature
–
1. VAA and VAA−_PIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection
in the analog supplies if all three supplies are tied together.
2. The imager operates in this temperature range, but image quality may degrade if it operates beyond the functional operating temperature
range.
3. Image quality is not guaranteed at temperatures equal to or greater than this range.
TABLE 41. VIDEO DAC ELECTRICAL CHARACTERISTICS–SINGLE-ENDED MODE
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V)
Parameter
Min
Typ
Max
Unit
Resolution
–
10
−
bits
DNL
–
0.2
0.4
bits
INL
–
0.7
3.5
bits
Output pad (DAC_POS)
–
37.5
−
W
Unused output (DAC_NEG)
–
37.5
−
W
Single-ended mode, code 000h
–
.021
−
V
Single-ended mode, code 3FFh
–
1.392
−
V
Single-ended mode, code 000h
–
0.560
−
mA
Single-ended mode, code 3FFh
–
37.120
−
mA
Estimate
–
−
25.0
mA
DAC_REF
DAC Reference
–
1.200
−
V
R DAC_REF
DAC Reference
–
2.4
−
KW
Output local load
Output voltage
Output current
Supply current
Condition
1. DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output
swing of 1.4V. Their resistor loadings may be different from the loadings in a real single-ended or differential-ended video output system with
an actual receiving end. Please refer to the Developer Guide for proper resistor loadings.
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45
ASX340AT
TABLE 42. VIDEO DAC ELECTRICAL CHARACTERISTICS–DIFFERENTIAL MODE
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V)
Parameter
Condition
Min
Typ
Max
Unit
DNL
–
0.2
0.4
Bits
INL
–
0.7
3.5
Bits
Differential mode per pad
(DAC_POS and DAC_NEG)
–
37.5
–
Ω
Differential mode, code 000h, pad dacp
–
.022
–
V
Differential mode, code 000h, pad dacn
–
1.421
–
V
Differential mode, code 3FFh, pad dacp
–
1.421
–
V
Differential mode, code 3FFH, pad dacn
–
.022
–
V
Differential mode, code 000h, pad dacp
–
.587
–
mA
Differential mode, code 000h, pad dacn
–
37.893
–
mA
Output local
load
Output voltage
Output current
Differential mode, code 3FFh, pad dacp
–
37.893
–
mA
Differential mode, code 3FFH, pad dacn
–
.587
–
mA
Estimate
–
–
50
mA
DAC_REF
DAC Reference
–
1.2
V
R DAC_REF
DAC Reference
2.4
KΩ
Supply current
1. DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into a low pass filter and achieve a full output
swing of 1.4 V. Their resistor loadings may be different from the loadings in a real single-ended or differential-ended video output system
with an actual receiving end. Please refer to the Developer Guide for proper resistor loadings.
TABLE 43. DIGITAL I/O PARAMETERS (TA = Ambient = 25°C; All supplies at 2.8 V)
Signal
All
Outputs
All
Inputs
Parameter
Definition
Condition
Load capacitance
Min
Typ
Max
Unit
5
–
30
pF
–
V
VOH
Output high voltage
0.7 * VDD_IO
VOL
Output low voltage
–
–
0.3* VDD_IO
V
IOH
Output high current
VOH = VDD_IO − 0.4 V
20
–
35
mA
IOL
Output low current
VOL = 0.4 V
29
–
53
mA
VIH
Input high voltage
0.7 * VDD_IO
–
VDD_IO + 0.5
V
VIL
Input low voltage
–0.3
–
0.3 * VDD_IO
V
IIH
Input high leakage current
0.02
–
0.26
mA
IIL
Input low leakage current
0.01
–
0.05
mA
Signal CAP
Input signal capacitance
–
6.5
–
pF
1. All inputs are protected and may be active when all supplies (2.8 V and 1.8 V) are turned off.
Power Consumption, Operating Mode
TABLE 44. POWER CONSUMPTION – CONDITION 1
(EXTCLK = 27 MHz; T = 25°C, dark condition (lens with cover))
Power Plane
Supply
Typ Power
Max Power
Unit
48.2
72
mW
2.2
10
mW
2.8
96
140
mW
2.8
2.2
5
mW
VDD
1.8
VDD_IO
2.8
VAA
VAA_PIX
Condition 1
Parallel off
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46
ASX340AT
TABLE 44. POWER CONSUMPTION – CONDITION 1 (CONTINUED)
(EXTCLK = 27 MHz; T = 25°C, dark condition (lens with cover))
Supply
Condition 1
Typ Power
Max Power
Unit
VDD_DAC
Power Plane
2.8
Single 75W
122.9
146
mW
VDD_PLL
2.8
18.8
25
mW
290.3
398
mW
Typ Power
Max Power
Unit
47.5
72
mW
Total
Analog output uses single-ended mode: DAC_Pos = 75 Ω,
DAC_Neg = 37.5 Ω, DAC_Ref = 2.4 kΩ, parallel output is
disabled.
TABLE 45. POWER CONSUMPTION – CONDITION 2
(fEXTCLK = 27 MHz; T = 25°C, dark condition (lens with cover), CLOAD = 40pF)
Power Plane
Supply
Condition 1
VDD
1.8
VDD_IO
2.8
26.6
50
mW
VAA
2.8
95.5
140
mW
VAA_PIX
2.8
2.2
5
mW
VDD_DAC
2.8
1.1
5
mW
VDD_PLL
2.8
18.8
25
mW
191.7
297
mW
Parallel on
VDAC off
Total
Analog output is disabled; parallel output is enabled.
VIDEO Signal Parameters
TABLE 46. KEY VIDEO SIGNAL PARAMETER TABLE
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V)
NTSC
PAL
UNITS
525
625
Hz
Line Frequency
15734.264
15625
Hz
Field Frequency
Parameter
Number of lines per frame
Notes
59.94
50
Hz
Sync Level
40
43
IRE
2, 3
Burst Level
40
43
IRE
2, 3
Black Level
7.5
0
IRE
1, 2, 3
White Level
100
100
IRE
1, 2, 3
1.
2.
3.
4.
Black and white levels are referenced to the blanking level.
1 IRE ~ 7.14 mV
DAC ref = 2.8 Kohm; load = 37.5 Ohm
Reference to ITU−R BT.470−6
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47
ASX340AT
A
DE
C
B
F
H
G
H
Figure 51. Video Timing
TABLE 47. VIDEO TIMING: SPECIFICATION FROM REC. ITU-R BT.470-6
Parameter
Signal
NTSC (27 MHz)
PAL (27 MHz)
Units
A
H Period
63.556
64.00
ms
B
Hsync to burst
4.71 to 5.71
5.60 ± 0.10
ms
C
burst
2.23 to 3.11
2.25 ± 0.23
ms
D
Hsync to Signal
9.20 to 10.30
10.20 ± 0.30
ms
E
Video Signal
52.655 ±0.20
52 +0, −0.3
ms
F
Front
1.27 to 2.22
1.5 +0.3, −0.0
ms
G
Hsync Period
4.70 ± 0.10
4.70 ± 0.20
ms
H
Sync rising/falling edge
3 0.25
0.20 ±0.10
ms
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48
ASX340AT
L
I
J
K
K
Figure 52. Equalizing Pulse
TABLE 48. EQUALIZING PULSE: SPECIFICATION FROM REC. ITU-R BT.470−6
Parameter
Signal
NTSC (27 MHz)
PAL (27 MHz)
Units
I
H/2 Period
31.778
32.00
ms
J
Pulse width
2.30 ± 0.10
2.35 ± 0.10
ms
K
Pulse rising/falling edge
30.25
0.25 ± 0.05
ms
L
Signal to pulse
1.50 ± −0.10
3.0 ± 2.0
ms
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49
ASX340AT
M
O
N
P
P
Figure 53. V Pulse
TABLE 49. V PULSE: SPECIFICATION FROM REC. ITU-R BT.470-6
Parameter
Signal
NTSC (27 MHz)
PAL (27 MHz)
Units
M
H/2 Period
31.778
32.00
ms
N
Pulse width
27.10 (nominal)
27.30 ± 0.10
ms
O
V pulse interval
4.70 ± 0.10
4.70 ± 0.10
ms
P
Pulse rising/falling edge
30.25
0.25 ± 0.05
ms
Two-Wire Serial Bus Timing
Figure 49 and Table 48 describe the timing for the
two-wire serial interface.
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
S
tHD;STA
tHD;DAT
tSU;STA
tHIGH
tSU;STO
Sr
P
S
Figure 54. Two-Wire Serial Bus Timing Parameters
TABLE 50. TWO-WIRE SERIAL BUS CHARACTERISTICS
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C)
Standard Mode
Parameter
SCLK Clock Frequency
Fast Mode
Symbol
Min
Max
Min
Max
Units
fSCL
0
100
0
400
KHz
Hold time (repeated) START
condition.
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50
ASX340AT
TABLE 50. TWO-WIRE SERIAL BUS CHARACTERISTICS
(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C)
Standard Mode
Fast Mode
Symbol
Min
Max
Min
Max
Units
After this period, the first clock
pulse is generated
tHD;STA
4.0
−
0.6
−
ms
LOW period of the SCLK clock
tLOW
4.7
−
1.3
−
ms
HIGH period of the SCLK clock
tHIGH
4.0
−
0.6
−
ms
Se-up time for a repeated START
condition
tSU;STA
4.7
−
0.6
−
ms
Data hold time
tHD;DAT
04
3.455
06
0.95
ms
Data set-up time
tSU;DAT
250
−
1006
−
ns
Rise time of both SDATA and SCLK
signals
tr
−
1000
20 + 0.1Cb7
300
ns
Fall time of both SDATA and SCLK
signals
tf
−
300
20 + 0.1Cb7
300
ns
Set-up time for STOP condition
tSU;STO
4.0
−
0.6
−
ms
Bus free time between a STOP
and START condition
tBUF
4.7
−
1.3
−
ms
Cb
−
400
−
400
pF
CIN_SI
−
3.3
−
3.3
pF
CLOAD_SD
−
30
−
30
pF
RSD
1.5
4.7
1.5
4.7
KW
Parameter
Capacitive load for each bus line
Serial interface input pin
capacitance
SDATA max load capacitance
SDATA pull-up resistor
This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period
of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
1.
2.
3.
4.
5.
6.
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51
ASX340AT
SPECTRAL CHARACTERISTICS
70
Red
Green
Blue
60
Quantum Efficiency (%)
50
40
30
20
10
0
350
450
550
650
750
850
Wavelength (nm)
NOTE:
The measurements were done on packaged parts with regular glass coating
(that is, without Anti-Reflective Glass (ARC) coating).
Figure 55. Quantum Efficiency
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52
950
1050
ASX340AT
PACKAGE DIMENSIONS
IBGA63 7.5 x 7.5
CASE 503AE
ISSUE O
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53
ASX340AT
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ASX340AT/D
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