Aalborg Universitet A CMOS Power Amplifier using Ground Separation Technique Aniktar, Hüseyin; Sjöland, Henrik; Mikkelsen, Jan Hvolgaard; Larsen, Torben Published in: Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2007 Publication date: 2007 Document Version Publisher's PDF, also known as Version of record Link to publication from Aalborg University Citation for published version (APA): Aniktar, H., Sjöland, H., Mikkelsen, J. H., & Larsen, T. (2007). A CMOS Power Amplifier using Ground Separation Technique. In Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2007 (pp. 281-284). IEEE Signal Processing Society. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. ? Users may download and print one copy of any publication from the public portal for the purpose of private study or research. ? You may not further distribute the material or use it for any profit-making activity or commercial gain ? You may freely distribute the URL identifying the publication in the public portal ? Take down policy If you believe that this document breaches copyright please contact us at email@example.com providing details, and we will remove access to the work immediately and investigate your claim. Downloaded from vbn.aau.dk on: juli 26, 2017 ,A wer mp,nilifier A using Ground Separation Technique Aniktar', Henrik Sj6land2, Jan H. Mikkelsen', and Torben Larsen 'Department of Electronic Systems, Aalborg University, Denmark, E-mail: risc(@kom.aau.dk Hiiseyin 2Department of Electroscience, Lund University, Sweden, E-mail: Henrik.Sjoland@ es.lth.se Abstract- This work presents an on-chip ground separation technique for power amplifiers. The ground separation technique is based on separating the grounds of the amplifier stages on the chip and thus any parasitic feedback paths are removed. Simulation and experimental results show that the technique makes the amplifier less sensitive to bondwire inductance, and consequently improves the stability and performance. A two-stage CMOS RF power amplifier for WCDMA mobile phones is designed using the proposed on chip ground separation technique. The power amplifier is fabricated in a 0.25,utm CMOS process. It has a measured 1-dB compression point between 1920MHz and 1980MHz of 21.3 ±0.5dBm with a maximum PAE of 24 c. The amplifier has sufficiently low ACLR for WCDMA (-33 dB) at an output power of 20 dBm. I. INTRODUCTION amplifier performance improved with ground separation is also discussed in this section. Simulation and measurement results demonstrating the PA performance are offered in Section III. Section IV describes the chip layout, and Section V concludes. II. CIRCUIT DESIGN The reported amplifier is designed as a single-ended two stage common source amplifier. It is biased in Class-AB to get high linearity and reasonable efficiency. Simulations are performed using the 0.25 ,um CMOS process library components with Agilent-ADS. Figure 1 shows the schematic of the CMOS PA which is designed to operate from a single 2.5 V supply. A. Core Amplifier To achieve about 23dBm output power with a 2.5V supply, a transistor width of 2870jim was used in the output stage. The estimation of the required transistor size is an iterative process using the DC characteristics of the transistor. The length of the transistor was set to minimum (0.24 jim) to maximize its high frequency gain. The load impedance for optimum power output was determined to approximately 10 -ll Q. The gate bias voltage was set to 0.75 V in the output stage. The driver stage transistor size is established after simulation of the output stage. To ensure that the driver stage doesn't enter saturation before the output stage, a transistor width of 1120jm was chosen. The bias voltage for the driver stage was set to 0.85 V. The input and output matching networks were designed using passive network synthesis techniques to achieve optimum VSWR characteristics over the desired frequency band (1920 -1980 MHz). An output impedance transformation network including the MOS output capacitance and interconnection elements (bond wires, pad capacitances, and PCB board traces) is designed to transform the 50 Q load into the 10 -jl I Q optimum load. The network includes the MOS output capacitance, 6nH off-chip load inductance, 6pF on- Most modern digital modulation forms with high spectral efficiency present a varying envelope, which requires RF circuits with high linearity to prevent signal degradation. Efficient but nonlinear power amplifiers are thus not suitable for such linear modulations. The use of linearization techniques can help alleviate this issue, but at the price of high complexity and additional power consumption which may be critical in the case of low or medium power amplifiers . In order to satisfy the linearity requirement for preserving modulation accuracy with minimum spectral regrowth, such power amplifiers are typically operated in highly linear Class-A or Class-AB configurations. However, high linearity, particularly in CMOS technology, comes at the cost of poor efficiency. Stability requirements place restrictions on PA characteristics, and limitations of CMOS technology such as low breakdown voltage introduce additional challenges for PA realization. Stability is a key issue in amplifier design. RF oscillations are especially common in single-ended multi-stage designs . The instability occurs when some of the output energy is fed back to the input port with a phase that makes negative resistance appear at the output or input of the amplifier . Ground bounce inductance plays an important role on the amplifier stability. If all stages in a multi-stage amplifier chip DC blocking capacitance, and interconnection elements share the same on-chip ground, they will also share the same (see Figure 1). inductance to PCB ground Signal current in the output stage To improve the stability and performance of the amplifier, converted to voltage by this inductance will thus be fed back to driver and output stage grounds are separated on the chip. This the input with a risk of instability. Using the proposed ground is described in miore detail in the following section. separation technique this feedback path is removed. The paper is organized as follows In Section II, the brief B. Interconnection Models In the circuit simulations, two interconnection models are design procedure of the amplifier is given, and then interconnection models of the amplifier are investigated. How the used, one is from chip signal/bias pad to PCB signal/bias pad, 281 0-7803-9764-9/07/$20.00 ©2007 IEEE 1=~~~~~~I1343 .4 D1 =2.5V urnN E L 0.24pm W: 11 20prp 15 pF 11 GND2 -i VG1 =0. Fig. 1. Schematic of the CMOS power amplifier. Fig. 3. Interconnection model for chip ground pad to PCB ground pad. and the other is from chip ground pad to PCB ground pad. These models are shown in Figures 2 and 3. The models are suitable for the chip-on-board technique used in the measurements. The inductance value of the bondwires is assumed to equal approximately 1 nH/mm . Multiple bondwires are used in order to reduce the bondwire inductance both in output and ground connections. It is assumed that three parallel connected bondwires has about 0.4 nH/mm inductance . On the chip, 85 um x 85 um pads are used for all connections. The shunt capacitance of a single pad was found to be approximately 65 fF in prior measurements. The PCB track capacitance was roughly estimated to 1.5 pF for simulations. L 1 2.5 2 1. 0 JAl LL - 0..5 a) Al 0- cn K -0..5 -1. .5 0 R bondwire 0.25 0.5 0.75 1 1.25 1.5 1.75 Frequency [GHz] PC C PCB_pad PCB_GND Fig. 2. pad. (CChip_pad Chip_GND Stability with Ground Separation Stability without Ground Separation --- 2 2.25 2.5 2.75 3 x 109 Simulated stability factor with and without ground separation Fig. 4. technique. as follows : Interconnection model for chip signal/bias pad to PCB signal/bias K 1= -S Figure 3 shows the interconnection model for chip ground pad to PCB ground pad. Different chip grounds are assigned for driver and output stages, GND1 and GND2. PCB ground is assumed to be a perfect ground and is denoted by GND. Driver and output stage grounds are isolated from each other by the cubstrate reicstivlity Investigations showed that when driver and output stage grounds are separated, the stability and performance were improved. Figure 4 shows the simulated stability factor of the amplifier with and without ground separation. As can be seen the PA with the ground separation technique is stable whereas without the technique the amplifier is potentially unstable and 1A1 . Stable: K > I = S22 + A 2 (1) 2 S12S211 1SIIS22 - S12S215 (2) and 1A\ < 1 -Unconditionally stable- -rs> 1 for S11 cj l- ri > I for: 1S7j1 cs 1 (3) 1 (4) 1 (5) 1 (6) Conditionally stable: cs - rs| < I for S2 lcj -ril malfunctioning. To quantify the stability of the amplifier, the Rollet Stability criteria is used. The Rollet Stability criteria can be expressed . 282 U < I for |S1 nstable (potentially): K > 1 & 1A1 > 1 and K 1A1 < 1, where c , cl, rs, and rl parameters represent the center and radius of the source and load stability circles respectively. Simulations show that 12 Q resistance between GNDI and GND2 is enough to sufficiently isolate them from each other. In the 0.25 ,um CMOS process, the substrate resistivity (R) is 20 Q Jicm and the substrate thickness (T) is 29 mils. The substrate resistance between GND I and GND2 can be roughly estimated using the formula: RSub = R[Q -X] Ad[m] EF 71:1. 0 .-.5 ZF) E2CZ t C) C: 0 .t11) z rr :51 .a (7) -00 C: 2 where the substrate distance (d) between the GNDI and GND2 is 100 jim (See Figure 3) and the substrate cross-section area (A) can be found as follow: A = T[m] x Wim3 = C: 0.25 10-9M2, 36 x CL where the chip width (W) is 360 ,um. Using Eq. (7), the resistance (RSulb) between GNDI and GND2 is roughly estimated to 76 Q, which is much larger than the 12 Q which is needed. This means that the simple calculation is sufficient in this case, and that there will be no problem to achieve the III. SIMULATION AND MEASUREMENT RESULTS The CMOS power amplifier was tested using chip on board assembly. Measurements were performed to find the Sparameters, l-dB compression point, power added efficiency (PAE), third order intercept point (IP3), adjacent channel leakage ratio (ACLR), and error vector magnitude (EVM). A. Frequency Response The measured and simulated forward and reverse gain characteristics (S21 & SI ) and input and output reflection characteristics (S 1 & S22 ) of the PA are shown in Figures 5 and 6. In Table I, some measured values in the WCDMA band are listed. 1~ ~ ~ S21 15 10 °55 - 1 E 7. -5- C: .C15 CD -10 (1) p -15 l (1) (1) rr 7C3 c m 7C3 m 0 LL -20 -25 -30 -35 -40 -45 IS121 -50 A 4 / --- Simulated Results Measured Results 2 2.25 2.5 2.75 -55 -60C iN,, 0 Fi 5 0.25 0.5 0.75 1 1.25 1.5 1.75 Frequency [GHz] 0.75 3 x 109 Simulated and measured forward and reverse gain characteristics 1 1.25 1.5 1.75 Frequency [GHz] 2 2.25 2.5 2.75 x 3 lo' Fig. 6. Simulated and measured input and output reflection characteristics. TABLE I MEASURED S PARAMETERS IN THE WCDMA BAND. Freq. [MHz] isolation. 20 0.5 (8) 1920 1950 1980 .21 11.8 11.2 10.7 IS111 dB -10.4 -105 -106 IS2 dB. -12.7 11 .4 -10 While the simulated gain is 14dB at 1.95GHz, the measured gain is only 11.2 dB. Differences between simulation and measurement results are due to imperfections of parasitic models used in simulations, on-chip and off-chip component tolerances, and also measurement inaccuracy. B. Efficiency The measured I -dB output compression point is 21.8 dBm with 24% PAE at 1920 MHz, it is 20.8 dBm with 20.4% PAE at 1950 MHz, and it is 21.4 dBm with 22.4% PAE at 1980 MHz. At the compression point, the current drawn from the 2.5 V supply voltage is 232 mA, 216 mA, and 222 mA respectively. The simulated 1 -dB compression point at 1950 MHz is 22.7 dBm with 32% PAE. The difference between the simulated and measured results is related to the measured gain being lower than the simulated one. Simulated and measured PAE are illustrated in Figure 7. C Linearity The linearity performance of the amplifier was analyzed according to the WCDMA/3GPP user equipment requirements  Third order output intercept point (01P) ACLR, and EVM measurements are performed. For two tone measurement the frequencies (tones) are set at f±H 500 kHz. The measured third order intercept points are 30.9 dBm, 30 dBm, and 30.1 dBm for 1920 MHz, 1950 MHz, and 1980 MHz center frequencies. In Figure 8, ACLR measurement is illustrated. The measurement has been performed at 1950 MHz with 20 dBm PA output power. 283 TABLE II M1EASUREDI)ERFORMANCE AND WCDMA/3GPP SpvECIFICATIONS. :i4 32 | ~~ Measured PAE 30 - - - Simulated PAE 28 26 24 22 20 o 18 < 16 0L 14 12 10 8 6 4 2 , o) -10 -8 -6 -4 -2 0 2 Parameter Output Power & PAE 1920 MHz 1950 MHz 1980 MHz ACLR Performance 1950 D5MHz 1950 ±1OMHz RMSEVM Peak EYM 21.8 dBm & 24% 20.8 dBm & 20.4% 21.4 dBmn & 22.4' o WCDMA/3GPP Specs Class 3: 23dBrn +1L/ -3dB Class 4: 21dBn ±2dB -33.2 dB -60.7 dB 4 <-33 dB <-43 dB < 175 %' Measured 10 7% 11 4 6 8 10 12 14 16 18 20 22 244 Pout [dBm] Fig. 7. Silmulated anLd lmeasured power added efficiency. Max/Ref Lvl Marker 1 [T1] RBW 30 kHz 40 dBm -0.18 dBm IJBW 300 kHz 20 dBm 1.95000000 GHz SWT [ 2 s tI RF Att TUnit Fig. 9. Die photo. 4 0 d:B d:Bmc C 0 ~~~~~~~~~~~~~~~~1.95000 area of the chip with 0.036 mm2 V. CONCLUSION 1. RH 1 -~ ~ ~ ~T,.~ AI. 33. Fig. 8. The ACLR performance of the amplifier output signal. In Table II, all measured results are listed and compared to system requirements. In WCDMA 3GPP UE document, transmitter characteristics are specified at the antenna connector of the UE. There will likely be some devices between the PA output and the antenna terminals such as circulator, duplex filter, and switch(es) with several dB of loss. When making the comparison, these losses also have to be taken into account. The inductance of the ground bondwires is one of the most single-ended integrated amplifier design. The inductance creates parasitic feedback which can cause the amplifier to self-oscillate. In this work it is demonstrated that the parasitic feedback path can be broken using a ground separation technique, and consequently amplifier's stability and performance can be improved. To demonstrate the technique, a CMOS RF power amplifier with ground separation has been realized. With 2.5 V supply voltage, 21.3 ± 0.5 dBm output power with maximum 24% PAE, and a good linearity were measured. At 2OdBm it fulfills the WCDMA/3GPP requirements on ACLR and EVM. serious problems in VI. ACKNOWLEDGMENT The authors would like to thank Peter Boie Jensen for lab assistance. This work was supported by the Danish Technical Research Council, project number 26-03-0030. REFERENCES    IV. CHIP LAYOUT A microphotograph of the CMOS PA is shown in Figure 9. The chip was fabricated in a 0.254m 2.5V single poly 5-metal layer (1P5M) CMOS technology. The chip size is 1343 ,um x 360 ,m. Driver and output stage layouts are separated with lOO1/m distance. Each block is connected to PCB ground with different GND pads. Ground separation increases the overall  [S]   284 A. Giry, J.-M. Fournier, and M. Pons, "A 1.9GHz Low Voltage CMOS Power Am-plifier for Medium Power RF Applications," IEEE RFIC Symposium, June 2000, Boston, USA. M. M. Hella and M. Ismail, RF CMOS Power Amplifiers: TI,eory, Desnig and Implementation. Kluwer Academic Publishers, Norwell, Massachusetts, USA, 2002. S. C. Cripps, RF Power Airiplifiers for Wireless Communication. Artech House, First Edition, Norwood, Massachusetts, USA, 1999. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998, Caim-bridge, United Kingdom. P. Howard, "Analysis of Ground Bond Wire Arrays for RFICS," IEEE RFIC Symposium, June 1997, Denver, USA. S. Y. Liao, Microwave Circuit Analysis and Amplifier Design. Prentice Hall, Englewood Cliffs, New Jersey, USA, 1987. "User Equipment Radio Transmission and Reception FDD," 3GPP TS 25.J01 v3.17.0, 1999.
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