GL854G-1x - Arrival Electronics
Genesys Logic, Inc.
GL854G-1x
USB 2.0 MTT 7-Port Hub
Controller
Datasheet
Revision 1.07
May 30, 2013
GL854G-1x Datasheet
Copyright
Copyright © 2013 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any
form or by any means without prior written consent of Genesys Logic, Inc.
Ownership and Title
Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein.
Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights
and any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise,
regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of
intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without
limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or
omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at
anytime without notice.
Genesys Logic, Inc.
12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231,
New Taipei City, Taiwan
Tel : (886-2) 8913-1888
Fax : (886-2) 6629-6168
http ://www.genesyslogic.com
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GL854G-1x Datasheet
Revision History
Revision
Date
Description
1.00
08/13/2010
First formal release
1.01
09/09/2010
Update Ch3 Pin Assignment, p.8-11
1.02
01/19/2011
Modify Ch4 Block Diagram, p.12
1.03
07/15/2011
Update Table 3.1, 3.2 RREF I/O type, p.9, 10
1.04
05/23/2012
Update Table 3.2 - Pin Descriptions-Power/ Ground, p.11
Updated CH8 Ordering Information, p.24
1.05
07/09/2012
Updated Figure 5.5 and Table 5.1, p. 16, 17
1.06
08/31/2012
Updated Table 6.6 - GL854G-1x Power Consumption, p. 22
1.07
05/30/2013
Updated CH5.2.4 Non-removable Port Configuration, p. 19
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GL854G-1x Datasheet
Table of Contents
CHAPTER 1 GENERAL DESCRIPTION ......................................................................... 6
CHAPTER 2 FEATURES..................................................................................................... 7
CHAPTER 3 PIN ASSIGNMENT ....................................................................................... 8
3.1 Pinouts ............................................................................................................................ 8
3.2 Pin List ............................................................................................................................ 9
3.3 Pin Descriptions ............................................................................................................. 9
CHAPTER 4 BLOCK DIAGRAM .................................................................................... 12
CHAPTER 5 FUNCTION DESCRIPTION ...................................................................... 13
5.1 General Hub Functions ............................................................................................... 13
5.1.1 MCP Architecture ............................................................................................... 13
5.1.2 USB Transceiver .................................................................................................. 13
5.1.3 Multiple-TT Architecture ................................................................................... 13
5.1.4 Port Power Control ............................................................................................. 13
5.1.5 Port Indicator ....................................................................................................... 14
5.1.6 Operation Scheme................................................................................................ 14
5.2 Configuration and I/O Settings .................................................................................. 16
5.2.1 RESET Setting ..................................................................................................... 16
5.2.2 PGANG/SUSPND Setting ................................................................................... 17
5.2.3 Power Control ...................................................................................................... 19
5.2.4 Non-removable Port Configuration ................................................................... 19
5.2.5 EEEPROM Setting .............................................................................................. 19
CHAPTER 6 ELECTRICAL CHARACTERISTICS...................................................... 20
6.1 Maximum Ratings ....................................................................................................... 20
6.2 Operating Ranges ........................................................................................................ 20
6.3 DC Characteristics ...................................................................................................... 20
6.4 Power Consumption .................................................................................................... 22
6.5 AC Characteristics ...................................................................................................... 23
CHAPTER 7 PACKAGE DIMENSION ........................................................................... 24
CHAPTER 8 ORDERING INFORMATION ................................................................... 25
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GL854G-1x Datasheet
List of Figures
Figure 3.1 - GL854G 64 Pin LQFP Pinout Diagram ............................................................ 8
Figure 4.1 - GL854G Block Diagram (Multiple TT) ........................................................... 12
Figure 5.1 - LED Connection ................................................................................................ 14
Figure 5.2 - Operating in USB 1.1 Scheme .......................................................................... 14
Figure 5.3 - Operating in USB 2.0 Scheme .......................................................................... 15
Figure 5.4 - Power on Reset Diagram ................................................................................... 16
Figure 5.5 - Power on Sequence of GL854G ........................................................................ 16
Figure 5.6 - Timing of PGANG/SUSPND Strapping .......................................................... 17
Figure 5.7 - GANG Mode Setting ......................................................................................... 18
Figure 5.8 - SELF/BUS Power Setting ................................................................................. 19
Figure 7.1 - GL854G 64 Pin LQFP Package ........................................................................ 24
List of Tables
Table 3.1 - GL854G 64 Pin List .............................................................................................. 9
Table 3.2 - Pin Descriptions ..................................................................................................... 9
Table 5.1 - Reset Timing ........................................................................................................ 17
Table 6.1 - Maximum Ratings ............................................................................................... 20
Table 6.2 - Operating Ranges ................................................................................................ 20
Table 6.3 - DC Characteristics except USB Signals ............................................................ 20
Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode .................................. 21
Table 6.5 - DC Characteristics of USB Signals under HS Mode ....................................... 21
Table 6.6 - GL854G-1x power consumption ........................................................................ 22
Table 6.7 - AC Characteristics of EEPROM Interface (24C02) ........................................ 23
Table 8.1 - Ordering Information ......................................................................................... 25
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GL854G-1x Datasheet
CHAPTER 1 GENERAL DESCRIPTION
GL854G is Genesys Logic’s premium 7-port hub solution which fully complies with Universal Serial Bus
Specification Revision 2.0. GL854G implements multiple TT* (Note1) architecture that provide dedicated
TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple
FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge
technology on cost and power efficient serial interface design. GL854G has proven compatibility, lower power
consumption figure and better cost structure above all USB 2.0 hub solutions worldwide.
GL854G implements multiple hub configuration features onto internal mask ROM, which traditionally
requires external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial
stage to configure hub settings such as (1) declare of compound device (2) gang/individual mode
selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is
required for the application.
GL854G provides 12MHz clock output that can be used as a reference clock source for multi-chip, hub
compound applications. The output clock provides enough driving capacity to support up to 2 devices that
connected to the downstream port. The chip-to-chip clock trace is relatively sensitive to PCB noise. Please
refers to design guide for PCB layout suggestions.
*Note 1: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the
unbalanced traffic speed between the upstream port and the downstream ports.
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GL854G-1x Datasheet
CHAPTER 2 FEATURES










Multiple Chip Package (MCP) architecture
 Integrates two standard USB 4-port hub silicon dies into single chip
 Supports 7 USB 2.0 compliant downstream ports
Multiple Transaction Translator (MTT)
 Provides dedicated TT control logics for each downstream port
 Superior performance when multiple FS devices operate concurrently
Compliant with USB specification Revision 2.0
 Upstream port supports both high-speed (HS) and full-speed (FS) traffic
 Downstream ports support HS, FS, and low-speed (LS) traffic
 Backward compatible to USB specification Revision 1.1
 Each downstream port supports status indicator, with automatic and manual modes
 Conform to self power and bus power requirements
Integrated USB transceiver
 Compliant with USB electrical requirements
 Ultralow power consumption
 Improve output drivers with slew-rate control for EMI reduction
 Internal power-fail detection for ESD recovery
On-chip 8-bit micro-processor
 Support customized PID, VID by reading external EEPROM
 Support downstream port configuration by reading external EEPROM
Smart power management features
 Support individual / gang mode over-current detection for all downstream ports
 Automatic switching between self-powered and bus-powered modes
Lower BOM cost
 Single external 12 MHz crystal / Oscillator clock input
 On-chip 5V to 3.3V power regulator
 Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors
 Support low-cost 24C02 EEPROM
Features for hub compound applications
 Support compound-device (non-removable in downstream ports) by I/O pin configuration
 Provide 12MHz clock source for other USB device connected to the downstream ports
Available package type: 64 pin LQFP package (7x7mm)
Applications:
 UMPC/MID, motherboard on-board applications
 Consumer electronics built-in hub application
 Monitor built-in hub
 Embedded systems
 Hub compound applications
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GL854G-1x Datasheet
CHAPTER 3 PIN ASSIGNMENT
GREEN2_C1
DVDD
GND
DVDD
GREEN3_C1
GREEN3_C2
OVCUR3#_C1
OVCUR3#_C2
OVCUR4#_C1
OVCUR4#_C2
TEST/SCL_C2
TEST/SCL_C
1
RESET#
GREEN4_C2
GREEN4_C
1
CLKOUT
3.1 Pinouts
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GREEN2_C2
49
32
GND
PESLF
50
31
GND
PGANG_C
2
51
30
DP4_C2
PGANG_C1
52
29
DM4_C2
OVCUR2#_C2
53
28
DP4_C1
OVCUR2#_C1
54
27
DM4_C1
OVCUR1#_C2
55
26
AVDD
OVCUR1#_C
1
56
25
DP3_C2
SDA_C2
57
24
DM3_C2
SDA_C1
58
23
DP3_C1
GREEN1_C2
59
22
DM3_C
1
GREEN1_C1
60
21
GND
AMBER1_C2
61
20
X2
V5
62
19
X1
V33
63
18
CLKIN_C2
V33
64
17
GND
GL854G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DM0
DP0
DM1_C1
DP1_C1
AVDD
NC
NC
GND
DM1_C2
DP1_C2
AVDD
DM2_C2
DP2_C2
RREF_C2
RREF_C
1
AVDD
LQFP - 64
Figure 3.1 - GL854G 64 Pin LQFP Pinout Diagram
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GL854G-1x Datasheet
3.2 Pin List
Table 3.1 - GL854G 64 Pin List
Pin# Pin Name Type Pin#
Pin Name
Type Pin#
Pin Name
Type Pin#
Pin Name
Type
1
DM0
B
17
GND
P
33
CLKOUT
O
49
GREEN2_C2
B
2
DP0
B
18
CLKIN_C2
I
34
GREEN4_C1
B
50
PSELF
I_5V
3
DM1_C1
B
19
X1
I
35
GREEN4_C2
B
51
PGANG_C2
B
4
DP1_C1
B
20
X2
O
36
RESET#
I_5V 52
PGANG_C1
B
5
AVDD
P
21
GND
P
37 TEST/SCL_C1
B
53 OVCUR2#_C2 I_5V
6
NC
-
22
DM3_C1
B
38 TEST/SCL_C2
B
54 OVCUR2#_C1 I_5V
7
NC
-
23
DP3_C1
B
39 OVCUR4#_C2 I_5V 55 OVCUR1#_C2 I_5V
8
GND
P
24
DM3_C2
B
40 OVCUR4#_C1 I_5V 56 OVCUR1#_C1 I_5V
9
DM1_C2
B
25
DP3_C2
B
41 OVCUR3#_C2 I_5V 57
SDA_C2
B
10
DP1_C2
B
26
AVDD
P
42 OVCUR3#_C1 I_5V 58
SDA_C1
B
11
AVDD
P
27
DM4_C1
B
43
GREEN3_C2
B
59
GREEN1_C2
B
12
DM2_C2
B
28
DP4_C1
B
44
GREEN3_C1
B
60
GREEN1_C1
B
13
DP2_C2
B
29
DM4_C2
B
45
DVDD
P
61 AMBER1_C2
B
14
RREF_C2
A
30
DP4_C2
B
46
GND
P
62
V5
P/I
15
RREF_C1
A
31
GND
P
47
DVDD
P
63
V33
P/O
16
AVDD
P
32
GND
P
48
GREEN2_C1
B
64
V33
P/O
3.3 Pin Descriptions
Table 3.2 - Pin Descriptions
USB Interface
Pin Name
GL854G-1x
64 Pin#
I/O
Type
DM0
DP0
1,2
B
USB signals for USPORT
DM1_C1
DP1_C1
3,4
B
USB signals for DSPORT1 of 1-tier hub
DM3_C1
DP3_C1
22,23
B
USB signals for DSPORT3 of 1-tier hub
DM4_C1
DP4_C1
27,28
B
USB signals for DSPORT4 of 1-tier hub
DM1_C2
DP1_C2
9,10
B
USB signals for DSPORT1 of 2-tier hub
DM2_C2
DP2_C2
12,13
B
USB signals for DSPORT2 of 2-tier hub
Description
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GL854G-1x Datasheet
DM3_C2
DP3_C2
24,25
B
USB signals for DSPORT3 of 2-tier hub
DM4_C2
DP4_C2
29,30
B
USB signals for DSPORT4 of 2-tier hub
RREF_C1
RREF_C2
15,14
A
Ref. resistor for 1-tier and 2-tier hub. (C1=1-tier, C2=2-tier)
Resistor value of 680Ω should be connected between RREF pin and
ground (GND).
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to
USB 2.0 Hub Design Guide.
Hub Interface
Pin Name
GL854G-1x
64 Pin#
I/O
Type
OVCUR1#~4#_C1
56,54,
42,40
I_5V
(pu)
OVCUR1#~4#_C2
55,53,
41,39
I_5V
(pu)
GREEN1~4_C1
60,48,
44,34
B
(pd)
GREEN1~4_C2
59,49,
43,35
B
(pd)
PSELF
50
I_5V
(pu)
PGANG_C1
PGANG_C2
52
51
B
Description
Active low. Over current indicator for 1-tier hub’s
DSPORT1~4
OVCUR1# is the only over current flag for GANG mode.
Active low. Over current indicator for 2-tier hub’s
DSPORT1~4
OVCUR1# is the only over current flag for GANG mode.
Green LED indicator for 1-tier hub’s DSPORT1~4 (Output
mode)
Strapping pin for DSPORT non-removable configuration.
(Input mode)
Details please check Chapter 5, sec. 5.2
Green LED indicator for 2-tier hub’s DSPORT1~4
Strapping pin for DSPORT non-removable configuration.
* Details please check: Chapter 5, sec. 5.2
Self-powered detection for 1-tier and 2-tier hub.
* PSELF should be pull-high concurrently
Strapping pin for gang / individual mode selection. (input
mode)
Host Suspend notification output pin (output mode)
Gang
input:1, output: 0@normal, 1@suspend
Individual
input:0, output: 1@normal, 0@suspend
* Details please check: Chapter 5, 5.2
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GL854G-1x Datasheet
Others Interface
Pin Name
GL854G-1x
64 Pin#
I/O
Type
X1
19
I
Crystal / OSC clock input ( for 1-tier hub)
X2
20
O
Crystal clock output. (for 1-tier hub)
CLKOUT
33
O
On-chip PLL output (12MHz output)
CLKIN_C2
18
I
OSC clock input ( for 2-tier hub)
RESET#
36
I_5V
TEST/SCL_C1
SDA_C1
37,
58
B
TEST/SCL_C2
SDA_C2
38,
57
B
NC
6,7
-
Description
Active low. External reset input, default pull high 10KΩ
When RESET# = low, whole chip is reset to the initial state
I2C EEPROM interface for 1-tier hub
*TEST/SCL pin cannot pull-high during initial stage to prevent hub
get into test mode
I2C EEPROM interface for 2-tier hub
*TEST/SCL pin cannot pull-high during initial stage to prevent hub
get into test mode
Reserved
*Not connected
Power / Ground
GL854G-1x
64 Pin#
5,11,16,
26
I/O
Type
P
3.3V analog power input for analog circuits.
DVDD
45,47
P
3.3V digital power input for digital circuits
GND
8,17,21,31,
32,46,
P
Ground
V5
62
P/I
5V Power input. It need be NC if using external regulator
V33
63,64
P/O
5V-to-3.3V regulator Vout & 3.3 input
Pin Name
AVDD
Description
*Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power
routing and the ground plane. For detailed information, please refer to USB 2.0 Hub Design Guide.
Notation:
Type
O
I
I_5V
B
P
pu
pd
P/I
P/O
Output
Input
Input_5V tolerance
Bi-directional
Power / Ground
Internal pull up
Internal pull down
Power input
Power output
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GL854G-1x Datasheet
CHAPTER 4 BLOCK DIAGRAM
CLK CLK
Output Input
US
Port
2-tier hub (C2)
1-tier hub (C1)
12MHz
DS #1_C2
LED1_C2
DSPort
Port #2-1
DS #2_C2
LED2_C2
DSPort
Port #2-2
DS #3_C2
LED3_C2
DSPort
Port #2-3
USport
Port #2-0
USport
Port #1-0
DS#2_C1
Connect to
US#0_C2
DSPort
Port #2-4
DS #4
_C2
DSPort
Port #1-2
DSPort
Port #1-1
DS #1_C1
LED1_C1
DSPort
Port #1-3
DS #3_C1
LED3_C1
DSPort
Port #1-4
DS #4_C1
LED4_C1
LED4
_C2
Figure 4.1 - GL854G Block Diagram (Multiple TT)
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GL854G-1x Datasheet
CHAPTER 5 FUNCTION DESCRIPTION
5.1 General Hub Functions
5.1.1 MCP Architecture
GL854G leverages multi-chip package (MCP) technology that incorporates two USB 4-port hubs onto a
standard 7x7mm 64 pin LQFP package to provide 7 downstream ports that fully compliant to USB 2.0
specifications. The 1-tier hub’s PLL integrates on-chip clock output for 2-tier hub’s reference clock, therefore,
only one external 12MHz crystal is required for GL854G whole chip operation.
5.1.2 USB Transceiver
USB transceiver is the analog circuit to support USB electrical requirements. GL854G integrated all
USPORT (upstream port) and DSPORT (downstream port) transceivers into single chip.
USPORT supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB
specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL854G
is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when
GL854G is plugged into a 2.0 host/hub.
DSPORT supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of
USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch
level to detect the detachment and attachment of devices.
5.1.3 Multiple-TT Architecture
Transaction Translator (TT) implements the control logic defined in section 11.14 ~ 11.22 of USB
specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT
(operating in HS) and DSPORTS (operating in FS/LS) of hub. GL854G implements multiple-TT architecture
that provide dedicated TT and control logic to each downstream (DS) ports, which guarantee Full-Speed(FS)
data passing bandwidth when multiple FS device perform heavy loading operations.
5.1.4 Port Power Control
An USB hub is required to report DSPORT power status to host in case of any over-current event occurs.
GL854G can support either individual mode or gang mode over-current detection scheme. (Please check
5.2.2 for gang/individual mode configuration) For individual mode, one DSPORT over-current event does
not affect other ports. The OVCUR# pin corresponding to each downstream port should be connected to a
power fuse with 500mA+ max current tolerance. For gang mode, multiple ports share the same power
protection circuit. For 7-port application, there are two options to gang power fuse: (1) One 1.5A+ power
fuse for 1-tier hub DSPORT (port2~4_C1) and One 2A+ power fuse for 2-tier (port1~4_C2).
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GL854G-1x Datasheet
5.1.5 Port Indicator
GL854G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus
Specification Revision2.0. Both manual mode and Automatic mode are supported in GL854G. When
GL854G is globally suspended, GL854G will turn off the LED to save power.
AMBER/GREEN
LED
DGND
Inside GL854G
On PCB
Figure 5.1 - LED Connection
5.1.6 Operation Scheme
5.1.6.1 Connected to USB 1.1 Host/Hub
If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1
mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing
through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the
REPEATER.
USB 1.1 HOST/HUB
USPORToperating
in FS signaling
Traffic channel
is routed to
REPEATER
REPEATER
TT
DSPORT operating
in FS/LS signaling
Figure 5.2 - Operating in USB 1.1 Scheme
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GL854G-1x Datasheet
5.1.6.2 Connected to USB 2.0 Host/Hub
If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port
signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will
then be routed to the REPEATER when the device connected to the downstream port is signaling also in
high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to
the downstream port is signaling in full/low speed.
USB 2.0 HOST/HUB
USPORToperating
in HS signaling
HS vs. HS:
Traffic channel is
routed to REPEATER
REPEATER
TT
DSPORT operating
in HS signaling
HS vs. FS/LS:
Traffic channel
is routed to TT
TT
DSPORT operating
in FS/LS signaling
Figure 5.3 - Operating in USB 2.0 Scheme
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GL854G-1x Datasheet
5.2 Configuration and I/O Settings
5.2.1 RESET Setting
GL854G’s power on reset can either be triggered by external reset or internal power good reset circuit. The
external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V
voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested
value refers to schematics) GL854G’s internal reset is designed to monitor silicon’s internal core power
(3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power
good voltage has been met, and the reset will be released after approximately 2.7 uS after power good.
GL854G’s reset circuit as depicted in the picture.
Silicon
PCB
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
VBUS
(External 5V)
R1
R2
Global
Reset#
EXT
INT
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
Figure 5.4 - Power on Reset Diagram
To fully control the reset process of GL854G, we suggest the reset time applied in the external reset circuit
should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure.
Power good voltage, 2.5 ~ 2.8V
VDD
Internal reset
TPG
External reset
Clock
…
…
USB command
T1
T2
Figure 5.5 - Power on Sequence of GL854G
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GL854G-1x Datasheet
Table 5.1 - Reset Timing
Symbol
Parameter
Min.
Max.
Unit
TPG
VDD power up to internal reset (power good) assert (12MHz)
-
2.7
μs
T1
VDD power up to external reset (RESETJ) assert
3
-
μs
T2
RESET assert to respond USB command ready
70
-
ms
To fully control the reset process of GL854G, we suggest the reset time applied in the external reset circuit
should longer than that of the internal reset circuit.
5.2.2 PGANG/SUSPND Setting
To save pin count, GL854G uses the same pin to decide individual/gang mode as well as to output the
suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later,
this pin is changed to output mode (as indicated in Figure 5.6). GL854G outputs the suspend flag once it is
globally suspended. To setup individual mode, a pull-down resister should be placed, while gang mode on
the contrary requires a pull high resister. The resistor value should be greater than 100KΩ. Figure 5.7
illustrate gang strapping and suspend LED indicator reference schematics. It should be noticed that the
polarity of LED must be followed to prevent unwanted driving during host suspend.
RESET#
50 ms
GANG_CTL
Input mode, strapping
to decide individual or
gang mode
Output mode, indicating
GL854G is in normal
mode or suspend mode
Figure 5.6 - Timing of PGANG/SUSPND Strapping
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 17
GL854G-1x Datasheet
GAND Mode
DVDD(3.3V)
"0": Individual Mode
"1": GANG Mode
DVDD(3.3V)
100K ohm
Suspend LED
Indicator
SUSPNDO
GANG_CTL
100K ohm
Suspend LED
Indicator
Inside GL854G
On PCB
Individual
Mode
Figure 5.7 - GANG Mode Setting
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 18
GL854G-1x Datasheet
5.2.3 Power Control
GL854G targets 7-DSport hub application. It can only operate under self-power mode due to USport Vbus
maximum power supply (500mA) is not enough to support 7 DSport operate concurrently (100/500mA per
port x 7) To configure 1-tier and 2-tier hub into self-power mode, PSELF pin must be configured as a
self-power hub (pull-high). Please check GL854G reference schematics for additional in formations.
1: Power Self
PSELF
0: Power Bus
Inside GL854G
On PCB
Figure 5.8 - SELF/BUS Power Setting
5.2.4 Non-removable Port Configuration
For compound application or embedded system, downstream ports that always connected inside the system
can be set as non-removable based on the state of corresponding status LED, pin GREEN2~4_C1 and
GREEN1~4_C2. If the pin is pulled high in the initial stage, the corresponding port will be set as
non-removable.
5.2.5 EEEPROM Setting
GL854G provides flexibility to reply host with customer oriented PID/VID or desired hub settings through a
low-cost 24C02 EEPROM. GL854G verifies the check sum after power on reset to make sure EEPROM
content follows Genesys required format. If the check sum is correct, GL854G will take the configuration
table that stored in EEPROM as part of the descriptor contents. In absence of external EEPROM, GL854G
replies to host commands by the default settings in the internal ROM. The detail setting information please
refers to the USB 2.0 Hub AP Note_EEPROM Info document.
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 19
GL854G-1x Datasheet
CHAPTER 6 ELECTRICAL CHARACTERISTICS
6.1 Maximum Ratings
Table 6.1 - Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
VCC
Power Supply
4.75
5.25
V
VIN
Input Voltage for digital I/O(EE_DO) pins
-0.5
+3.6
V
VIN
Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins
-0.5
+5.5
V
VINUSB
Input Voltage for USB signal (DP, DM) pins
-0.5
+3.6
V
+100
o
TS
Storage Temperature under bias
FOSC
Frequency
-60
C
12 MHz  0.05%
6.2 Operating Ranges
Table 6.2 - Operating Ranges
Symbol
Parameter
Min.
Typ.
Max.
Unit
V5
5V Power Supply
4.75
5.0
5.25
V
VDD
3.3V Power Supply
3.0
3.3
3.6
V
VIND
Input Voltage for digital I/O pins
-0.5
3.3
3.6
V
VINUSB
Input Voltage for USB signal (DP, DM) pins
0.5
3.3
3.6
V
70
o
125
o
TA
TJ
θ
JA
Ambient Temperature
Absolute maximum junction temperature
Thermal Characteristics LQFP 64
0
-
0
-
185.18
-
C
C
o
C/W
6.3 DC Characteristics
Table 6.3 - DC Characteristics except USB Signals
Symbol
Parameter
Min.
Typ.
Max.
Unit
PD
Power Dissipation
490
-
980
mW
VDD
Power Supply Voltage
3
3.3
3.6
V
VIL
LOW level input voltage
-
-
0.8
V
VIH
HIGH level input voltage
2.0
-
-
V
VTLH
LOW to HIGH threshold voltage
1.4
1.5
1.6
V
VTHL
HIGH to LOW threshold voltage
0.87
0.94
0.99
V
VOL
LOW level output voltage when IOL=8mA
-
-
0.4
V
VOH
2.4
-
-
V
-
-
30
A
RDN
HIGH level output voltage when IOH=8mA
Leakage current for pads with internal pull up or pull
down resistor
Pad internal pull down resister
81K
103K
181K
Ω
RUP
Pad internal pull up resister
81K
103K
181K
Ω
IOLK
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 20
GL854G-1x Datasheet
Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
VOL
DP/DM static output LOW
0
-
0.3
V
VOH
DP/DM static output HIGH
2.8
-
3.6
V
VDI
Differential input sensitivity
0.2
-
-
V
VCM
Differential common mode range
0.8
-
2.5
V
VSE
Single-ended receiver threshold
0.2
-
-
V
CIN
Transceiver capacitance
-
-
20
pF
ILO
Hi-Z state data line leakage
-10
-
+10
A
ZDRV
Driver output resistance
28
-
44
Ω
Table 6.5 - DC Characteristics of USB Signals under HS Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
VOL
DP/DM static output LOW
-
-
0.1
V
CIN
Transceiver capacitance
4
4.5
5
pF
ILO
Hi-Z state data line leakage
-5
0
+5
A
ZDRV
Driver output resistance for USB 2.0 HS
48
45
42
Ω
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 21
GL854G-1x Datasheet
6.4 Power Consumption
Table 6.6 - GL854G-1x power consumption
Condition
Symbol
Active ports
ISUSP
ICC
Host
Current
Unit
1.5
mA
Device
Suspend
7
H
H
144.3
mA
6
H
H
136.3
mA
5
H
H
127.5
mA
4
H
H
120.8
mA
3
H
H
113.9
mA
2
H
H
106.3
mA
1
H
H
97.6
mA
Up Port Config
H
N/A
88.9
mA
*: H: High-Speed
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 22
GL854G-1x Datasheet
6.5 AC Characteristics
GL854G- supports 24C02 type EEPROM for customized VID/PID or hub configuration settings. AC
characteristics of 24C02 interface summarized as below figures and tables.
Table 6.7 - AC Characteristics of EEPROM Interface (24C02)
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 23
GL854G-1x Datasheet
CHAPTER 7 PACKAGE DIMENSION
Internal
No.
GL854G Versio
n No.
AAAAAAAAAA
YWWXXXXXXXX
Date
Code
Lot Code
Figure 7.1 - GL854G 64 Pin LQFP Package
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 24
GL854G-1x Datasheet
CHAPTER 8 ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number
Package
Green/Wire Material
Version
Status
GL854G -MSGXX
LQFP 64
Green Package
XX
Available
© 2013 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 25
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