CY7C65642 - Cypress Semiconductor

CY7C65642 - Cypress Semiconductor
CY7C65642
HX2VL - Very Low-Power USB 2.0
TetraHub™ Controller
HX2VL - Very Low-Power USB 2.0 TetraHub™ Controller
Features
❐
Integrated upstream/downstream termination resistors
Integrated port status indicator control
❐ 12-MHz +/-500 ppm external crystal with drive level 600 W
(integrated PLL) clock input with optional 27/48-MHz
oscillator clock input.
❐ Internal power failure detection for ESD recovery
❐
■
High-performance, low-power USB 2.0 hub, optimized for
low-cost designs with minimum bill-of-material (BOM).
■
USB 2.0 hub controller
❐ Compliant with USB2.0 specification, TID# 30000059
❐ Up to four downstream ports support
❐ Downstream ports are backward compatible with FS, LS
❐ Multiple translator (TT), one per downstream port for
maximum performance.
■
Very low-power consumption
❐ Supports bus-powered and self-powered modes
❐ Auto switching between bus-powered and self-powered
❐ Single MCU with 2 K ROM and 64 byte RAM
❐ Lowest power consumption.
■
Highly integrated solution for reduced BOM cost
❐ Internal regulator – single power supply 5 V required.
❐ Provision of connecting 3.3 V with external regulator.
❐ Integrated upstream pull-up resistor
❐ Integrated pull-down resistors for all downstream ports
■
Downstream port management
❐ Support individual and ganged mode power management
❐ Overcurrent detection
❐ Two status indicators per downstream port
■
Maximum configurability
❐ VID and PID are configurable through external EEPROM
❐ Number of ports, removable/non-removable ports are
configurable through EEPROM and I/O pin configuration
❐ I/O pins can configure gang/individual mode power
switching, reference clock source and polarity of power
switch enable pin
❐ Configuration options also available through mask ROM
■
Available in space saving 48-pin TQFP (7 × 7 mm) and 28-pin
QFN (5 × 5 mm) packages
■
Supports 0 C to +70 C temperature range
Block Diagram
D+
12/27/48
MHz
OSC-in
OR 12
MHz
Crystal
I2C /
SPI
MCU
D-
RAM
USB 2.0 PHY
Serial
Interface
Engine
PLL
ROM
HS USB
Control Logic
USB Upstream Port
5 V i/p (for internal
regulator)
NC (for external regulator)
Transaction Translator x 4
1.8 V
Regulator
Hub Repeater
3.3 V
3.3 V i/p (with ext. reg. & 28-QFN
NC (with ext. reg. & 48-TQFP)
3.3 V o/p (for int. reg.)
Routing Logic
USB Downstream Port 2
USB Downstream Port 3
USB Downstream Port 4
USB 2.0
PHY
USB 2.0
PHY
USB 2.0
PHY
USB 2.0
PHY
Cypress Semiconductor Corporation
Document Number: 001-65659 Rev. *J
•
198 Champion Court
LED
•
D+ D-
Port
Control
O V R # [4]
D+ D-
O V R # [3]
LED
Port
Control
P W R # [3]
D+ D-
O V R # [2]
LED
Port
Control
P W R # [2]
O V R # [1]
P W R # [1]
D+ D-
Port
Control
P W R # [4]
USB Downstream Port 1
LED
San Jose, CA 95134-1709
•
408-943-2600
Revised June 22, 2017
CY7C65642
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right HX2VL device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
http://www.cypress.com/?id=2411.
■
■
■
Overview: USB Portfolio, USB Roadmap
USB 2.0 Hub Controller Selectors: HX2LP, HX2VL
Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with HX2VL are:
❐ AN72332 - Guidelines on System Design using Cypress's
USB 2.0 Hub (HX2VL)
❐ AN69235 - Migrating from HX2/HX2LP to HX2VL
■
Reference Designs:
❐ CY4608 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
❐ CY4607 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
■
Models: HX2VL (CY7C65632/34/42) - IBIS
HX2VL Development Kit
HX2VL Development Kit board is a tool to demonstrate the features of HX2VL devices (CY7C65632, CY7C65634). In the initial phase
of the design, this board helps developers to understand the chip features and limitations before proceeding with a complete design.
The Development kit includes support documents related to board hardware, PC application software, and EEPROM configuration
data (.iic) files.
Document Number: 001-65659 Rev. *J
Page 2 of 26
CY7C65642
Contents
Introduction ....................................................................... 4
HX2VL Architecture .......................................................... 4
USB Serial Interface Engine ........................................ 4
HS USB Control Logic ................................................. 4
Hub Repeater .............................................................. 4
MCU ............................................................................ 4
Transaction Translator ................................................ 4
Port Control ................................................................. 4
Applications ...................................................................... 4
Functional Overview ........................................................ 5
System Initialization ..................................................... 5
Enumeration ................................................................ 5
Multiple Transaction Translator Support ..................... 5
Upstream Port ............................................................. 5
Downstream Ports ....................................................... 5
Power Switching .......................................................... 5
Overcurrent Detection ................................................. 5
Port Indicators ............................................................. 5
Power Regulator .......................................................... 6
External Regulation Scheme ....................................... 6
Internal Regulation Scheme ........................................ 6
Pin Configurations ........................................................... 7
Pin Definitions .................................................................. 9
Pin Definitions ................................................................ 12
EEPROM Configuration Options ................................... 14
Pin Configuration Options ............................................. 15
Power ON Reset ....................................................... 15
Gang/Individual Power Switching Mode .................... 15
Power Switch Enable Pin Polarity ............................. 15
Document Number: 001-65659 Rev. *J
Port Number Configuration ........................................ 15
Non Removable Ports Configuration ......................... 15
Reference Clock Configuration ................................. 15
Absolute Maximum Ratings .......................................... 16
Operating Conditions ..................................................... 16
Electrical Characteristics ............................................... 17
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 18
Thermal Resistance ........................................................ 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Silicon Errata for the HX2VL,
CY7C65642 Product Family ........................................... 23
Part Numbers Affected .............................................. 23
HX2VL Qualification Status ....................................... 23
HX2VL Errata Summary ............................................ 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Page 3 of 26
CY7C65642
Introduction
HX2VL is Cypress’s next generation family of high- performance,
very low-power USB 2.0 hub controllers. HX2VL has integrated
upstream and downstream transceivers; a USB serial interface
engine (SIE); USB hub control and repeater logic; and
transaction translator (TT) logic. Cypress has also integrated
external components such as voltage regulator and
pull-up/pull-down resistors, reducing the overall BOM required to
implement a USB hub system.
The CY7C65642 is a part of the HX2VL portfolio with four
downstream ports and an independent TT dedicated for each
downstream port. This device option is for low-power but
high-performance applications that require up to four
downstream ports. The CY7C65642 is available in 48-pin TQFP
and 28-pin QFN package options.
All device options are supported by Cypress’s world class
reference design kits, which include board schematics, BOM,
Gerber files, Orcad files, and thorough design documentation.
HX2VL Architecture
The Block Diagram on page 1 shows the HX2VL TetraHub™
architecture.
USB Serial Interface Engine
The SIE allows HX2VL to communicate with the USB host. The
SIE handles the following USB activities independently of the
Hub Control Block.
■
Bit stuffing and unstuffing
■
Checksum generation and checking
■
TOKEN type identification
■
Address checking.
HS USB Control Logic
‘Hub Control’ block co-ordinates enumeration, suspend and
resume. It generates status and control signals for host access
to the hub. It also includes the frame timer that synchronizes the
hub to the host. It has status/control registers which function as
the interface to the firmware in the MCU.
Hub Repeater
The hub repeater manages the connectivity between upstream
and downstream facing ports that are operating at the same
speed. It supports full and high-speed connectivity. According to
the USB 2.0 specification, the hub repeater provides the
following functions:
■
Sets up and tears down connectivity on packet boundaries
■
Ensures orderly entry into and out of ‘Suspend’ state, including
proper handling of remote wakeups.
Document Number: 001-65659 Rev. *J
MCU
The HX2VL has MCU with 2 K ROM and 64 byte RAM. The MCU
operates with a 12 MHz clock to decode USB commands from
host and respond to the host. It can also handle GPIO settings
to provide higher flexibility to the customers and control the read
interface to the EEPROM which has extended configuration
options.
Transaction Translator
The TT translates data from one speed to another. A TT takes
high-speed split transactions and translates them to full or
low-speed transactions when the hub is operating at high-speed
(the upstream port is connected to a high speed host controller)
and has full or low- speed devices attached. The operating speed
of a device attached on a downstream port determines whether
the routing logic connects a port to the TT or to hub repeater.
When the upstream host and downstream device are functioning
at different speeds, the data is routed through the TT. In all other
cases, the data is routed through the repeater. For example, If a
full or low-speed device is connected to the high-speed host
upstream through the hub, then the data transfer route includes
TT. If a high-speed device is connected to the high-speed host
upstream through the hub, the transfer route includes the
repeater. When the hub is connected to a full-speed host
controller upstream, then high-speed peripheral does not
operate at its full capability. These devices only work at full
speed. Full and low-speed devices connected to this hub operate
at their normal speed.
Port Control
The downstream ‘Port Control’ block handles the
connect/disconnect and over current detection as well as the
power enable and LED control. It also generates the control
signals for the downstream transceivers.
Applications
Typical applications for the HX2VL device family are:
■
Docking stations
■
Standalone hubs
■
Monitor hubs
■
Multi-function printers
■
Digital televisions
■
Advanced port replicators
■
Keyboard hubs
■
Gaming consoles
Page 4 of 26
CY7C65642
Functional Overview
The Cypress CY7C65642 USB 2.0 Hubs are low-power hub
solutions for USB which provide maximum transfer efficiency
with no TT multiplexing between downstream ports. The
CY7C65642 USB 2.0 Hubs integrate 1.5 k upstream pull-up
resistors for full speed operation and all downstream 15 k
pull-down resistors and series termination resistors on all
upstream and downstream D+ and D– pins. This results in
optimization of system costs by providing built-in support for the
USB 2.0 specification.
Downstream D+ and D– pull-down resistors are incorporated in
CY7C65642 for each port. Before the hubs are configured, the
ports are driven Single Ended Zero, ((SE0) where both D+ and
D– are driven low) and are set to the unpowered state. When the
hub is configured, the ports are not driven and the host may
power the ports by sending a SetPortPower command for each
port. After a port is powered, any connect or disconnect event is
detected by the hub. Any change in the port state is reported by
the hubs back to the host through the Status Change Endpoint
(endpoint 1). On receipt of SetPortReset request for a port with
a device connected, the hub does as follows:
System Initialization
■
Performs a USB Reset on the corresponding port
On power up, CY7C65642 has an option to enumerate from the
default settings in the mask ROM or from reading an external
EEPROM for configuration information. At the most basic level,
this EEPROM has the Vendor ID (VID) and the Product ID (PID),
for the customer's application. For more specialized
applications, other configuration options can be specified. See
EEPROM Configuration Options on page 14 for more details.
CY7C65642 verifies the checksum before loading the EEPROM
contents as the descriptors.
■
Puts the port in an enabled state
■
Enables babble detection after the port is enabled.
Enumeration
CY7C65642 enables the pull-up resistor on D+ to indicate its
presence to the upstream hub, after which a USB Bus Reset is
expected. After a USB Bus Reset, CY7C65642 is in an
unaddressed, unconfigured state (configuration value set to ‘0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Multiple Transaction Translator Support
After TetraHub is configured in a high speed system, it is in single
TT mode. The host may then set the hub into multiple TT mode
by sending a SetInterface command. In multiple TT mode, each
full speed port is handled independently and thus has a full
12 Mbps bandwidth available. In Single TT mode, all traffic from
the host destined for full or low-speed ports are forwarded to all
of those ports. This means that the 12 Mbps bandwidth is shared
by all full and low-speed ports.
Upstream Port
The upstream port includes the transmitter and the receiver state
machine. The transmitter and receiver operate in high speed and
full speed depending on the current hub configuration. The
transmitter state machine monitors the upstream facing port
while the Hub Repeater has connectivity in the upstream
direction. This machine prevents babble and disconnect events
on the downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is attached.
Downstream Ports
The CY7C65642 supports a maximum of four downstream ports,
each of which may be marked as usable or removable in the
EEPROM configuration, see EEPROM Configuration Options on
page 14. Additionally, it can also be configured by pin strapping,
see Pin Configuration Options on page 15.
Document Number: 001-65659 Rev. *J
Babble consists of a non idle condition on the port after EOF2. If
babble is detected on an enabled port, that port is disabled. A
ClearPortEnable request from the host also disables the
specified port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend request. If the hub is not suspended, a
remote wakeup event on that port is reflected to the host through
a port change indication in the Hub Status Change Endpoint. If
the hub is suspended, a remote wakeup event on this port is
forwarded to the host. The host may resume the port by sending
a ClearPortSuspend command.
Power Switching
The CY7C65642 includes interface signals for external port
power switches. Both ganged and individual (per-port)
configurations are supported by pin strapping, see Pin
Configuration Options on page 15.
After enumerating, the host may power each port by sending a
SetPortPower request for that port. Power switching and
overcurrent detection are managed using respective control
signals (PWR#[n] and OVR#[n]) which are connected to an
external power switch device. Both High/Low enabled power
switches are supported and the polarity is configured through
GPIO setting, see Pin Configuration Options on page 15.
Overcurrent Detection
The OVR#[n] pins of the CY7C65642 series are connected to the
respective external power switch’s port overcurrent indication
(output) signals. After detecting an overcurrent condition, hub
reports overcurrent condition to the host and disables the
PWR#[n] output to the external power device. OVR#[n] has a
setup time of 20 ns. It takes 3 to 4 ms from overcurrent detection
to deassertion of PWR#[n]
Port Indicators
The USB 2.0 port indicators are also supported directly by
CY7C65642. According to the specification, each downstream
port of the hub optionally supports a status indicator. The
presence of indicators for downstream facing ports is specified
by bit 7 of the wHubCharacteristics field of the hub class
descriptor. The default CY7C65642 descriptor specifies that the
port indicators are supported. The CY7C65642 port indicators
has two modes of operation: automatic and manual.
Page 5 of 26
CY7C65642
On power up the CY7C65642 defaults to automatic mode, where
the color of the Port Indicator (green, amber, off) indicates the
functional status of the CY7C65642 port. The LEDs are turned
off when the device is suspended.
5 V to 3.3 V Regulator
5 V to 3.3 V Regulator
NC
NC
Port Status
Indicator
LED
VCC
VREG
NC
VREG
CY7C65642
48 Pin
VCC_A
Power Regulator
CY7C65642 requires 3.3 V source power for normal operation of
internal core logic and USB physical layer (PHY). The integrated
low-drop power regulator converts 5 V power input from USB
cable (Vbus) to 3.3 V source power. The 3.3 V power output is
guaranteed by an internal voltage reference circuit when the
input voltage is within the 4 V–5.5 V range. The regulator’s
maximum current loading is 150 mA, which provides tolerance
margin over CY7C65642’s normal power consumption of below
100 mA. The on chip regulator has a quiescent current of 28 µA.
VCC
CY7C65642
28 Pin
VCC_D
VCC_A
VCC_D
External Regulation Scheme
Internal Regulation Scheme
When the built-in internal regulator is chosen, then the VCC pin
has to be connected to a 5 V, in both 48-pin and 28-pin packages.
Internally, the built-in regulator generates a 3.3 V and 1.8 V for
the chip’s internal usage. Also a 3.3 V output is available at
VREG pin, that has to be connected externally to VCC_A and
VCC_D.
External Regulation Scheme
CY7C65642 supports both external regulation and internal
regulation schemes. When an external regulation is chosen,
then for the 48-pin package, VCC and VREG are to be left open
with no connection. The external regulator output 3.3 V has to be
connected to VCC_A and VCC_D pins. This connection has to
be done externally, on board. For the 28-Pin package, the 3.3 V
output from the external regulator has to be connected to VREG,
VCC_A and VCC_D. The VCC pin has to be left open with no
connection. From the external input 3.3 V, 1.8 V is internally
generated for the chip’s internal usage.
3.3 V
VREG
5 V
VCC
CY7C65642
48 Pin
VCC_A
3.3 V
VREG
5 V
VCC
CY7C65642
28 Pin
VCC_D
VCC_A
VCC_D
Internal Regulation Scheme
Document Number: 001-65659 Rev. *J
Page 6 of 26
CY7C65642
Pin Configurations
Figure 1. 48-pin TQFP (7 × 7 × 1.4 mm) pinout
OVR#[1]
PWR#[2]
OVR#[2]
GANG
VCC_D
SELFPWR
43
42
41
40
39
38
37
44
45
PWR#[1]
/
I2C_SDA
SEL27
GREEN[1] /
SPI_SK /
47
46
VCC
48
FIXED_PORT
1
AMBER[1] /
SPI_CS
VREG
VCC_A
1
36
AMBER[2] / SPI_MOSI /
PWR_PIN_POL
GND
2
35
GREEN[2] /
SPI_MISO /
FIXED_PORT2
D-
3
34
VCC_D
D+
4
33
AMBER[3] /
SET_PORT_NUM2
DD-[1]
5
32
GREEN[3] /
FIXED_PORT3
DD+[1]
5
31
PWR#[3]
VCC_A
7
30
OVR#[3]
GND
8
29
PWR#[4]
DD-[2]
9
28
OVR#[4]
DD+[2]
10
27
TEST / I2C_SCL
RREF
11
26
RESET#
VCC_A
12
25
SEL48
CY7C65642
48-pin TQFP
13
14
15
16
17
18
19
20
21
22
23
24
GND
XIN
XOUT
VCC_A
DD-[3]
DD+[3]
VCC_A
GND
DD-[4]
DD+[4]
GREEN[4] /
FIXED_PORT
4
AMBER[4] /
SET_PORT_NUM1
Document Number: 001-65659 Rev. *J
Page 7 of 26
CY7C65642
Pin Configurations (continued)
Figure 2. 28-pin QFN (5 × 5 × 0.8 mm) pinout
VREG
VCC
PWR#/
I2C_SDA
OVR # [1]
O VR # [2]
GANG
SELFPWR
28
27
26
25
24
23
22
1
21
VC C_ D
D+
2
20
O V R # [3]
D D - [1]
3
19
O V R # [4]
D D + [1]
4
18
TEST/I2C_SCL
V C C_ A
5
17
RESET#
DD
- [2]
6
CY7C65642
16
D D + [4]
DD
+ [2]
7
28-pin QFN
15
DD
-
D -
9
10
11
12
13
14
RREF
V C C_ A
XIN
XOUT
DD
D D + [3]
V C C_ A
- [3]
8
Document Number: 001-65659 Rev. *J
- [4]
Page 8 of 26
CY7C65642
Pin Definitions
48-pin TQFP Package
Pin Name
Power and Clock
VCC_A
VCC_A
VCC_A
VCC_A
VCC_A
VCC_D
VCC_D
VCC
Pin No.
Type [1]
1
7
12
16
19
34
38
47
P
P
P
P
P
P
P
P
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_D. 3.3 V digital power to the chip.
VCC_D. 3.3 V digital power to the chip.
VCC. 5 V input to the internal regulator; NC if using external regulator
VREG
GND
GND
GND
GND
XIN
XOUT
SEL48 / SEL27
48
2
8
13
20
14
15
25 / 44
P
P
P
P
P
I
O
I
RESET#
26
I
SELFPWR
GANG
37
39
I
I/O
RREF
System Interface
11
I/O
VREG. 5–3.3 V regulator o/p during internal regulation; NC if using external regulator.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
12-MHz crystal clock input, or 12/27/48MHz clock input
12-MHz Crystal OUT. (NC if external clock is used).
Clock source selection inputs.
00: Reserved
01: 48-MHz OSC-in
10: 27-MHz OSC-in
11: 12-MHz Crystal or OSC-in
Active LOW Reset. External reset input, default pull high 10 k; When RESET =
low, whole chip is reset to the initial state
Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered.
GANG. Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for suspend
Individual Mode: Input:0 -> Output is 1 for normal operation and 0 for suspend
Refer to gang / individual power switching modes in Pin Configuration Options on
page 15 for details.
649  resistor must be connected between RREF and Ground.
Test
I2C_SCL
27
I(RDN)
I/O(RDN)
3
4
I/O/Z
I/O/Z
Upstream Port
D–
D+
Description
Test. 0: Normal Operation and 1: Chip will be put in test mode.
I2C_SCL. Can be used as I2C clock pin to access I2C EEPROM.
Upstream D– Signal.
Upstream D+ Signal.
Note
1. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
Document Number: 001-65659 Rev. *J
Page 9 of 26
CY7C65642
Pin Definitions (continued)
48-pin TQFP Package
Pin No.
Type [1]
Description
5
6
46
I/O/Z
I/O/Z
O(RDN)
O(RDN)
O(RDN)
O(RDN)
I(RDN)
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for amber LED. port indicator support.
SPI_CS. Can be used as chip select to access external SPI EEPROM.
LED. Driver output for green LED. Port indicator support.
SPI_SK. Can be used as SPI Clock to access external SPI EEPROM.
FIXED_PORT1. At POR used to set Port1 as non removable port. Refer Pin
Configuration Options on page 15.
42
I(RUP)
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input.
43
O/Z
I/O
9
10
36
I/O/Z
I/O/Z
O(RDN)
O(RDN)
I(RDN)
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port Indicator Support.
SPI_MOSI. Can be used as Data Out to access external SPI EEPROM.
PWR_PIN_POL. Used for power switch enable pin polarity setting. Refer Pin
Configuration Options on page 15.
GREEN[2] [2]
SPI_MISO
FIXED_PORT2
35
O(RDN)
I(RDN)
I(RDN)
LED. Driver output for Green LED. Port Indicator Support.
SPI_MISO. Can be used as Data In to access external SPI EEPROM.
FIXED_PORT2. At POR used to set Port2 as non removable port. Refer Pin
Configuration Options on page 15.
OVR#[2]
40
I(RUP)
41
O/Z
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input.
Power Switch Driver Output. Default is Active LOW
17
18
33
I/O/Z
I/O/Z
O(RDN)
I(RDN)
GREEN[3]
FIXED_PORT3
32
O(RDN)
I(RDN)
OVR#[3]
30
I(RUP)
PWR#[3]
31
O/Z
Pin Name
Downstream Port 1
DD–[1]
DD+[1]
AMBER[1]
SPI_CS
GREEN[1] [2]
SPI_SK
FIXED_PORT1
OVR#[1]
PWR#[1]
I2C_SDA
Downstream Port 2
DD–[2]
DD+[2]
AMBER[2]
SPI_MOSI
PWR_PIN_POL
PWR#[2]
Downstream Port 3
DD–[3]
DD+[3]
AMBER[3]
SET_PORT_NUM2
45
Power Switch Driver Output. Default is Active LOW.
I2C_SDA. Can be used as I2C Data pin, connected with I2C EEPROM.
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port indicator support.
SET_PORT_NUM2. Used to set port numbering along with SET_PORT_NUM1.
Refer Pin Configuration Options on page 15.
LED. Driver output for Green LED. Port indicator support.
FIXED_PORT3. At POR used to set Port3 as non removable port. Refer Pin
Configuration Options on page 15.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input.
Power Switch Driver Output. Default is Active LOW.
Note
2. Pin-strapping GREEN[1] and GREEN[2] enables proprietary function that may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as non-removable
by pin-strapping should be avoided.
Document Number: 001-65659 Rev. *J
Page 10 of 26
CY7C65642
Pin Definitions (continued)
48-pin TQFP Package
Pin No.
Type [1]
Description
21
22
24
I/O/Z
I/O/Z
O(RDN)
I(RDN)
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port Indicator Support.
SET_PORT_NUM1. Used to set port numbering along with SET_PORT_NUM2.
Refer “Pin Configuration Options” on page 15
GREEN[4]
FIXED_PORT4
23
O(RDN)
I(RDN)
OVR#[4]
28
I(RUP)
LED. Driver output for Green LED. Port Indicator Support.
FIXED_PORT4. At POR used to set Port4 as non removable port. Refer Pin
Configuration Options on page 15.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input.
PWR#[4]
29
O/Z
Pin Name
Downstream Port 4
DD–[4]
DD+[4]
AMBER[4]
SET_PORT_NUM1
Power Switch Driver Output. Default is Active LOW.
Note: The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high, unless a separate
circuit is designed to support logic high. Disconnect after 60 ms of power-on reset (POR), when these pins are reconfigured as
outputs.
Document Number: 001-65659 Rev. *J
Page 11 of 26
CY7C65642
Pin Definitions
28-pin QFN Package
Pin Name
Power and Clock
VCC_A
VCC_A
VCC_A
VCC_D
VCC
Pin No.
Type[3]
Description
5
9
14
21
27
P
P
P
P
P
VREG
28
P
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_D. 3.3 V digital power to the chip.
VCC. 5 V input to the internal regulator; NC if using external regulator
VCC. 5–3.3 V regulator o/p during internal regulation; 3.3 V i/p if using external
regulator.
12-MHz crystal clock input, or 12-MHz clock input
XIN
10
I
XOUT
11
O
RESET#
17
I
SELFPWR
22
I
GANG
23
I/O
RREF
System Interface
Test
I2C_SCL
8
I/O
18
O(RDN)
I/O(RDN)
26
I/O
PWR# [4]
I2C_SDA
12-MHz Crystal OUT. (NC if external clock is used).
Active LOW Reset. External reset input, default pull high 10k Ohm;
When RESET = low, whole chip is reset to the initial state
Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered.
GANG Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for suspend
Individual Mode: Input:0 -> Output is 1 for normal operation and 0 for suspend
Refer to gang / individual power switching modes in Pin Configuration Options on
page 15 for details.
649- resistor must be connected between RREF and Ground
Test. 0: Normal Operation & 1: Chip will be put in test mode
I2C_SCL. I2C Clock pin.
Power switch driver output. Default is active low
I2C_SDA. I2C Data pin.
Notes
3. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
4. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin will act as I2C_SDA, it will not switch to PWR#
mode (as it does in 48-pin TQFP package).
Document Number: 001-65659 Rev. *J
Page 12 of 26
CY7C65642
Pin Definitions (continued)
28-pin QFN Package
Pin No.
Type[3]
1
2
I/O/Z
I/O/Z
Upstream D– Signal.
Upstream D+ Signal.
3
4
I/O/Z
I/O/Z
25
I(RUP)
Downstream D– Signal.
Downstream D+ Signal.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input. Only OVR#[1](pin 25) is enabled in Gang mode. OVR#[2](pin 24),
OVR#[3](pin 20) and OVR#[4](pin 19) are disabled in Gang mode.
DD–[2]
DD+[2]
6
7
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
OVR#[2]
24
I(RUP)
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input. Only OVR#[1](pin 25) is enabled in Gang mode. This (OVR#[2]) pin
is disabled in Gang mode.
12
13
I/O/Z
I/O/Z
20
I(RUP)
15
16
I/O/Z
I/O/Z
OVR#[4]
19
I(RUP)
GND
PAD
P
Pin Name
Upstream Port
D–
D+
Downstream Port 1
DD–[1]
DD+[1]
OVR#[1]
Description
Downstream Port 2
Downstream Port 3
DD–[3]
DD+[3]
OVR#[3]
Downstream Port 4
DD–[4]
DD+[4]
Document Number: 001-65659 Rev. *J
Downstream D– Signal.
Downstream D+ Signal.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input. Only OVR#[1](pin 25) is enabled in Gang mode. This (OVR#[3]) pin
is disabled in Gang mode.
Downstream D– Signal.
Downstream D+ Signal.
Overcurrent Condition Detection Input. Active LOW Overcurrent Condition
Detection Input. Only OVR#[1](pin 25) is enabled in Gang mode. This (OVR#[4]) pin
is disabled in Gang mode.
Ground pin for the chip. It is the solderable exposed pad beneath the chip. Refer to
the Figure 4 on page 21.
Page 13 of 26
CY7C65642
EEPROM Configuration Options
Systems using CY7C65642 have the option of using the default
descriptors to configure the hub. Otherwise, it must have an
external EEPROM for the device to have a unique VID, and PID.
The CY7C65642 can communicate with an SPI (microwire)
EEPROM like 93C46 or I2C EEPROM like 24C02. Example
EEPROM connections are shown as follows:
Byte
41h–6Fh
70 h
71h–80h
Value
Product string (ASCII code)
Serial number length
Serial number string
Byte 0: VID (LSB)
Least Significant Byte of Vendor ID
S P I E E P R O M C o n n e c tio n
A M B E R [1 ]
CS
VCC
G R E E N [1 ]
SK
NC1
A M B E R [2 ]
DI
NC2
G R E E N [2 ]
DO
GND
VDD
Most Significant Byte of Vendor ID
Byte 2: PID (LSB)
Least Significant Byte of Product ID
Byte 3: PID (MSB)]
Most Significant Byte of Product ID
AT 93C 46
I2 C E E P R O M C o n n e c tio n
A0
VCC
A1
WP
Byte 4: ChkSum
VDD
A2
SCL
TEST
GND
SDA
P W R # [1 ]
Note The 28-pin QFN package includes only support for I2C
EEPROM like ATMEL/24C02N_SU27 D, MICROCHIP/4LC028
SN0509, SEIKO/S24CS02AVH9. The 48-pin TQFP package
includes both I2C and SPI EEPROM connectivity options. In this
case, user can use either SPI or I2C connectivity at a time for
communicating to EEPROM. The 48-pin package supports
ATMEL/AT93C46DN-SH-T, in addition to the above mentioned
families. HX2VL can only read from SPI EEPROM. So field
programming of EEPROM will be supported only for I2C
EEPROM. The default VID and PID are 0x04B4 and 0x6572.
CY7C65642 verifies the check sum after power on reset and if
validated loads the configuration from the EEPROM. To prevent
this configuration from being overwritten, AMBER[1] is disabled
when the SPI EEPROM is present.
Value
VID_LSB
VID_MSB
PID_LSB
PID_MSB
ChkSum
Reserved–FEh
Removable ports
Port number
Maximum power
Reserved–FFh
Vendor string length
Vendor string (ASCII code)
Product string length
CY7C65642 will ignore the EEPROM settings if ChkSum is
not equal to VID_LSB + VID_MSB + PID_LSB + PID_MSB +1
Byte 5: Reserved
AT24C02
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h–0Fh
10h
11h–3Fh
40h
Byte 1: VID (MSB)
Set to FEh
Byte 6: RemovablePorts
RemovablePorts[4:1] are the bits that indicate whether the
device attached to the corresponding downstream port is
removable (set to 0) or non-removable (set to 1). Bit 1
corresponds to Port 1, Bit 2 to Port 2 and so on. Default value
is 0 (removable). These bit values are reported appropriately
in the HubDescriptor:DeviceRemovable field.
Bits 0,5,6,7 are set to 0.
Byte 7: Port Number
Port Number indicates the number of downstream ports. The
values must be 1 to 4. Default value is 4.
Byte 8: Maximum Power
This value is reported in the Configuration Descriptor:
bMax-Power field and is the current in 2 mA increments that
is required from the upstream hubs. The allowed range is 00h
(0mA) to FAh(500mA). Default value is 32h (100mA)
Byte 9–15: Reserved
Set to FFh (except 11 which is FEh)
Byte 16: Vendor String Length
Length of the Vendor String
Byte 17–63: Vendor String
Value of Vendor String in ASCII code.
Byte 64: Product String Length
Length of the Product String
Byte 65–111: Product String
Value of Product String in ASCII code
Byte 112: Serial Number Length
Length of the Serial Number
Byte 113 onwards: Serial Number String
Serial Number String in ASCII code.
Document Number: 001-65659 Rev. *J
Page 14 of 26
CY7C65642
Pin Configuration Options
Table 1. Features supported in 48-pin and 28-pin packages
Power ON Reset
The power on reset can be triggered by external reset or internal
circuitry. The internal reset is initiated, when there is an unstable
power event for silicon’s internal core power (3.3 V ± 10%). The
internal reset is released 2.7 µs ± 1.2% after supply reaches
power good voltage (2.5 V to 2.8 V). The external reset pin,
continuously senses the voltage level (5 V) on the upstream
VBUS as shown in the figure. In the event of USB plug/unplug or
drop in voltage, the external reset is triggered. This reset trigger
can be configured using the resistors R1 and R2. Cypress
recommends that the reset time applied in external reset circuit
should be longer than that of the internal reset time.
PCB
VBUS
(External 5V)
Silicon
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
R1
EXT
Global
Reset#
INT
R2
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
Supported Features
48-pin
28-pin
Port number configuration
Yes
No
Non-removable port configuration
Yes
No
Reference clock configuration
Yes
No
Power switch enable polarity
Yes
No
LED Indicator
Yes
No
Power Switch Enable Pin Polarity
The pin polarity is set active-high by pin-strapping the
PWR_PIN_POL pin to 1 and Active-Low by pin-strapping the
PWR_PIN_POL pin to 0. Thus, both kinds of power switches
are supported. This feature is not supported in 28-pin QFN
package.
Port Number Configuration
In addition to the EEPROM configuration, as described
above, configuring the hub for 2/3/4 ports is also supported
using
pin-strapping
SET_PORT_NUM1
and
SET_PORT_NUM2, as shown in following table.Pin strapping
option is not supported in the 28-pin QFN package.
SET_PORT_NUM2
SET_PORT_NUM1
Gang/Individual Power Switching Mode
1
1
1 (Port 1)
A single pin is used to set individual / gang mode as well as
output the suspend flag. This is done to reduce the pin count.
The individual or gang mode is decided within 20 µs after power
on reset. It has a setup time of 1ns. 50 to 60ms after reset, this
pin is changed to output mode. CY7C65642 outputs the suspend
flag, once it is globally suspended. Pull-down resistor of greater
than 100K is needed for Individual mode and a pull-up resistor
greater than 100K is needed for Gang mode. Figure below
shows the suspend LED indicator schematics. The polarity of
LED must be followed, otherwise the suspend current will be
over the spec limitation (2.5 mA).
1
0
2 (Port 1/2)
0
1
3 (Port 1/2/3)
0
0
4 (All ports)
VDD (3.3V)
VDD (3.3V)
PCB
SUSPEND OUT
SUSPEND
INDICATOR
100K
Document Number: 001-65659 Rev. *J
In embedded systems, downstream ports that are always
connected inside the system, can be set as non-removable
(always connected) ports, by pin-strapping the corresponding
FIXED_PORT# pins 1~4 to High, before power on reset. At POR,
if the pin is pull high, the corresponding port is set to
non-removable. This is not supported in the 28-pin QFN
package.
Reference Clock Configuration
GANG/SUSPEND
INDIVIDUAL MODE
Non Removable Ports Configuration
Silicon
GANG MODE
100K
# Ports
This hub can support, optional 27/48-MHz clock source. When
on-board 27/48-MHz clock is present, then using this feature,
system integrator can further reduce the BOM cost by eliminating
the external crystal. This is available through GPIO pin
configuration shown below. This is not supported in the 28-pin
QFN package.
0 : INDIVIDUAL MODE
1: GANG MODE
SEL48
SEL27
0
1
48-MHz OSC-in
Clock Source
1
0
27-MHz OSC-in
1
1
12-MHz X’tal/OSC-in
Page 15 of 26
CY7C65642
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient temperature ..................................... 0 °C to +70 °C
Storage temperature ................................ –60 °C to +100 °C
5 V supply voltage to ground potential ......4.75 V to +5.25 V
Ambient temperature ..................................... 0 °C to +70 °C
3.3 V supply voltage to ground potential .....3.15 V to +3.6 V
5 V supply voltage to ground potential ........–0.5 V to +6.0 V
Input voltage for USB signal pins ..................0.5 V to +3.6 V
3.3 V supply voltage to ground potential .....–0.5 V to +3.6 V
Voltage at open drain input pins ..................–0.5 V to +5.0 V
Voltage at open drain input pins
(OVR#1-4, SELFPWR, RESET#) ................–0.5 V to +5.5 V
Thermal characteristics 48-pin TQFP ................... 78.7 °C/W
3.3 V Input Voltage for Digital I/O ................–0.5 V to +3.6 V
Ambient max junction temperature .............. 0 °C to +125 °C
Thermal characteristics 28-pin QFN ..................... 33.3 °C/W
FOSC (oscillator or crystal frequency) ........ 12 MHz ± 0.05%
Document Number: 001-65659 Rev. *J
Page 16 of 26
CY7C65642
Electrical Characteristics
DC Electrical Characteristics
Parameter
Description
Conditions
Min
Typ
–
–
Max
External regulator Internal regulator
Unit
PD
Power dissipation
VIH
Input high voltage
–
2
–
–
V
VIL
Input low voltage
–
–
–
0.8
V
Full speed / low speed
(0 < VIN < VCC)
–10
–
+10
A
High speed mode
(0 < VIN < VCC)
–5
0
+5
A
Il
Input leakage current
Excluding USB signals
432
mW
VOH
Output voltage high
IOH = 8 mA
2.4
–
–
V
VOL
Output low voltage
IOL= 8 mA
–
–
0.4
V
RDN
Pad internal pull-down resistor
–
29
59
135

RUP
Pad internal pull-up resistor
CIN
Input pin capacitance
ISUSP
Suspend current
–
80
108
140

Full speed / low speed
mode
–
–
20
pF
high speed mode
4
4.5
–
0.786
1.043
1.3
mA
Full speed host,
full speed devices
–
88.7
103.9
105.4
mA
High speed host,
high speed devices
–
81.9
88.2
89.3
mA
High speed host,
full speed devices
–
88.2
101.2
102.3
mA
Full speed host,
full speed devices
–
79.1
91.6
93
mA
High speed host,
high speed devices
–
72.9
78.5
78.6
mA
High speed host,
full speed devices
–
75.9
88.7
88.8
mA
Full speed host,
full speed devices
–
68.1
78.4
78.6
mA
High speed host,
high speed devices
–
61.9
67.6
69.6
mA
High speed host,
full speed devices
–
64.9
75.4
76.1
mA
Full speed host,
full speed devices
–
57.1
66.3
66.7
mA
High speed host,
high speed devices
–
51.9
57.6
59.3
mA
High speed host,
full speed devices
–
54.7
61.1
62.5
mA
Full speed host
–
42.8
48.9
50.3
mA
High speed host
–
44.2
49.1
50.6
mA
–
5
pF
Supply Current
4 Active ports
3 Active ports[5]
ICC
2 Active ports
1 Active ports
No Active ports[6]
Notes
5. Current measurement is with device attached and enumerated.
6. No devices attached.
Document Number: 001-65659 Rev. *J
Page 17 of 26
CY7C65642
AC Electrical Characteristics
USB Transceiver is USB 2.0 certified in low, full and high speed modes.
Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0 Electrical Certification
Testing.
The 48-pin TQFP package can support communication to EEPROM using either I2C or SPI. The 28-pin QFN package can support
only I2C communication to EEPROM.
AC characteristics of these two interfaces to EEPROM are summarized in tables below:
AC Characteristics of SPI EEPROM interface
Parameter
Parameter
Min
Typ
Max
tCSS
CS setup time
3.0
–
–
tCSH
CS hold time
3.0
–
–
tSKH
SK high time
1.0
–
–
tSKL
SK low time
2.2
–
–
tDIS
DI setup time
1.8
–
–
tDIH
DI hold time
2.4
–
–
tPD1
Output delay to ‘1’
–
–
1.8
tPD0
Output delay to ‘0’
–
–
1.8
Units
µs
AC Characteristics of I2C EEPROM interface
1.8 V–5.5 V
Parameter
2.5 V–5.5 V
Parameter
Units
Min
Max
Min
Max
fSCL
SCL clock frequency
0.0
100
0.0
400
KHz
tLOW
Clock LOW Period
4.7
–
1.2
–
us
tHIGH
Clock HIGH Period
4.0
–
0.6
–
us
tSU:STA
Start condition setup time
4.7
–
0.6
–
us
tSU:STO
Stop condition setup time
4.7
–
0.6
–
us
tHD:STA
Start condition hold time
4.0
–
0.6
–
us
tHD:STO
Stop condition hold time
4.0
–
0.6
–
us
tSU:DAT
Data in setup time
200.0
–
100.0
–
ns
tHD:DAT
Data in hold time
0
–
0
–
ns
tDH
Data out hold time
100
–
50
–
ns
tAA
Clock to output
0.1
4.5
0.1
–
us
tWR
Write cycle time
–
10
–
5
ns
Thermal Resistance
Parameter
Description
48-pin TQFP
Package
28-pin QFN
Package
Unit
JA
Thermal resistance (junction to ambient)
78.7
33.3
°C/W
JC
Thermal resistance (junction to case)
35.3
18.4
°C/W
Document Number: 001-65659 Rev. *J
Page 18 of 26
CY7C65642
Ordering Information
Ordering Code
Package Type
CY7C65642-48AXC
48-pin TQFP - Tray
CY7C65642-48AXCT
48-pin TQFP - Tape and Reel
CY7C65642-28LTXC
28-pin QFN - Tray
Ordering Code Definitions
CY 7
C 65642 - XX
A
X
C
X
X = blank or T
blank = Tray; T = Tape and Reel
Temperature Range:
C = Commercial
Pb-free
Package Type: XX = A or LT
A = TQFP; LT = QFN
Pin Count: XX = 48 or 28
Part Identifier
Technology Code: C = CMOS
Marketing Code
Company ID: CY = Cypress
Document Number: 001-65659 Rev. *J
Page 19 of 26
CY7C65642
Package Diagrams
The CY7C65642 is available in following packages:
Figure 3. 48-pin TQFP (7 × 7 × 1.4 mm) A48 Package Outline, 51-85135
51-85135 *C
Document Number: 001-65659 Rev. *J
Page 20 of 26
CY7C65642
Figure 4. 28-pin QFN (5 × 5 × 0.8 mm), LT28A (3.5 × 3.5 E-Pad), Sawn Package Outline, 001-64621
001-64621 *A
Document Number: 001-65659 Rev. *J
Page 21 of 26
CY7C65642
Acronyms
Acronym
Document Conventions
Description
AC
Alternating Current
ASCII
American Standard Code for Information
Interchange
EEPROM
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
Electrically Erasable Programmable Read Only
Memory
kHz
kilohertz
k
kilohm
EMI
Electromagnetic Interference
MHz
megahertz
ESD
Electrostatic Discharge
A
microampere
GPIO
General Purpose Input/Output
s
microsecond
I/O
Input/Output
W
microwatt
LED
Light Emitting Diode
mA
milliampere
LSB
Least Significant Bit
mm
millimeter
MSB
Most Significant Bit
ms
millisecond
PCB
Printed Circuit Board
mW
milliwatt
PLL
Phase-Locked Loop
ns
nanosecond
POR
Power On Reset

ohm
PSoC®
Programmable System-on-Chip™
%
percent
QFN
Quad Flat No-leads
pF
picofarad
RAM
Random Access Memory
ppm
parts per million
ROM
Read Only Memory
V
volt
SIE
Serial Interface Engine
W
watt
TQFP
Thin Quad Flat Pack
TT
Transaction Translator
USB
Universal Serial Bus
Document Number: 001-65659 Rev. *J
Page 22 of 26
CY7C65642
Silicon Errata for the HX2VL, CY7C65642 Product Family
This section describes the errata for the HX2VL, CY7C65642. The details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative, if you have any questions.
Part Numbers Affected
Part Number
Device Characteristics
CY7C65642
USB 2.0 Multi TT Hub
HX2VL Qualification Status
Product Status: In production
HX2VL Errata Summary
This is the initial version of the HX2VL Errata. As of now, there is no known issue with respect to the HX2VL.
Document Number: 001-65659 Rev. *J
Page 23 of 26
CY7C65642
Document History Page
Document Title: CY7C65642, HX2VL - Very Low-Power USB 2.0 TetraHub™ Controller
Document Number: 001-65659
Rev.
ECN
Orig. of
Change
Submission
Date
**
3176751
SWAK
02/18/2011
New data sheet.
*A
3250883
SWAK /
AASI
06/29/2011
Updated Functional Overview (Updated Port Indicators (Added a Note
“Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary function that
may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as
non-removable by pin-strapping should be avoided.”).
Updated Pin Configurations (Updated Figure 1 (Pin of the 48-pin TQFP
package was named SELF_PWR. It is changed to SELFPWR.)).
Updated Pin Definitions (Updated description of XIN pin to “12-MHz crystal
clock input, or 12-MHz clock input” (since 28-pin package does not support 27
and 48 MHz), updated description of XOUT pin to “12-MHz Crystal OUT. (NC
if external clock is used)”, changed value from 680  to 650 in description of
RREF pinchanged description ofOVR# pins from “Default is Active LOW” to
“Active LOW Overcurrent Condition Detection Input” (since the polarity is not
configurable), changed all seven occurrences of “Refer “48-pin TQFP Pin
Configuration” on page 5” to “Refer Pin Configuration Options on page 15”,
added Note 2 and referred the same Note in GREEN#[1] and GREEN#[2] pins).
Updated Pin Definitions (Updated description of XIN pin to “12-MHz crystal
clock input, or 12-MHz clock input” (since 28-pin package does not support 27
and 48 MHz), updated description of XOUT pin to “12-MHz Crystal OUT. (NC
if external clock is used)”, changed description of OVR# pins from “Default is
Active LOW” to “Active LOW Overcurrent Condition Detection Input” (since the
polarity is not configurable)).
Updated Functional Overview (Updated Power Regulator (Changed regulator’s
maximum current loading from 200 mA to 150 mA)).
Updated Pin Configuration Options (Updated Power Switch Enable Pin Polarity
(Replaced first two occurrences of the word “setting” with “pin-strapping”)).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Updated maximum value of ISUSP parameter to 903 µA, updated maximum
values of ICC parameter)).
*B
3327505
AASI
07/27/2011
Changed status from Preliminary to Final.
Updated Pin Definitions (Minor edits).
Updated Ordering Information (Updated part numbers) and Ordering Code
Definitions.
*C
3525169
AASI
02/16/2012
Updated Pin Configurations (Updated Figure 1 (Renamed SPI_DI to
SPI_MOSI, renamed SPI_DO to SPI_MISO respectively for clarity)).
Updated Pin Definitions (Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to
SPI_MISO respectively for clarity).
Updated Pin Definitions (Updated description of PWR# of 28-pin package (To
describe the alternate function I2C_SDA)).
*D
3637477
AASI
07/02/2012
Updated EEPROM Configuration Options (Changed the value of Byte 5 to FEh
to match with the tabular column).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Splitted the Max column into two columns namely External regulator and
Internal regulator for ISUSP and ICC parameters and updated the corresponding
values)).
Added Thermal Resistance.
Updated Ordering Information (Updated part numbers).
Updated to new template.
*E
3995708
PRJI
05/09/2013
Added Silicon Errata for the HX2VL, CY7C65642 Product Family.
Document Number: 001-65659 Rev. *J
Description of Change
Page 24 of 26
CY7C65642
Document History Page (continued)
Document Title: CY7C65642, HX2VL - Very Low-Power USB 2.0 TetraHub™ Controller
Document Number: 001-65659
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*F
4694741
PRJI
03/20/2015
Added More Information.
Updated Functional Overview:
Updated Port Indicators:
Updated description.
Updated Pin Definitions:
Added Note at the bottom.
Updated EEPROM Configuration Options:
Updated details in “Value” column corresponding to “09h–0Fh” in the table.
Updated Electrical Characteristics:
Updated DC Electrical Characteristics:
Updated all values of RDN and RUP parameters.
Added Note 5 and referred the same note in “3 Active ports” in “Description”
column of ICC parameter.
Added Note 6 and referred the same note in “No Active ports” in “Description”
column of ICC parameter.
Updated Package Diagrams:
spec 51-85135 – Changed revision from *B to *C.
spec 001-64621 – Changed revision from ** to *A.
Updated Silicon Errata for the HX2VL, CY7C65642 Product Family:
Updated HX2VL Qualification Status:
Replaced “Sampling” with “In production”.
Updated to new template.
Completing Sunset Review.
*G
5363572
HBM
07/21/2016
Updated CY Logo and Sales Disclaimer.
Updated Features: Added TID number along with Compliant with USB2.0
specification. Removed Slew rate control for EMI management.
Updated Pin Definitions for 28-pin QFN Package: Updated Description for
OVR#[1], OVR#[2], OVR#[3], and OVR#[4].
*H
5545393
HBM
12/07/2016
Updated More Information.
Updated Copyright and Disclaimer.
*I
5688033
RUPA
04/10/2017
Updated logo and copyright.
*J
5782612
ANII
06/22/2017
Updated Ordering Information:
No change in part numbers.
Replaced “Tube” with “Tray”.
Document Number: 001-65659 Rev. *J
Page 25 of 26
CY7C65642
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-65659 Rev. *J
Revised June 22, 2017
Page 26 of 26
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